Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 56646680 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21047253 1 T1 6 T2 270 T3 23



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 74036969 1 T1 57 T2 539 T3 19930
values[0x0] 1736757 1 T1 4 T2 211 T3 28
values[0x1] 1920207 1 T1 4 T2 213 T3 24



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 39955853 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 37738080 1 T1 21 T2 428 T3 6696



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 335764 1 T2 4 T3 89 T5 1800
valid_sources[0x01] 276343 1 T2 8 T3 65 T5 1711
valid_sources[0x02] 274753 1 T2 8 T3 59 T5 1727
valid_sources[0x03] 291981 1 T2 3 T3 76 T5 1708
valid_sources[0x04] 310253 1 T3 96 T5 1665 T6 2342
valid_sources[0x05] 287033 1 T1 2 T2 5 T3 61
valid_sources[0x06] 279963 1 T2 9 T3 95 T5 1692
valid_sources[0x07] 273078 1 T2 4 T3 88 T5 1723
valid_sources[0x08] 303942 1 T2 5 T3 80 T5 1690
valid_sources[0x09] 405393 1 T3 88 T5 1690 T6 2286
valid_sources[0x0a] 305989 1 T2 5 T3 81 T5 1634
valid_sources[0x0b] 270755 1 T2 7 T3 71 T5 1725
valid_sources[0x0c] 270783 1 T2 3 T3 83 T5 1690
valid_sources[0x0d] 298666 1 T1 1 T2 2 T3 83
valid_sources[0x0e] 283686 1 T2 1 T3 75 T5 1673
valid_sources[0x0f] 271296 1 T3 76 T5 1766 T6 2268
valid_sources[0x10] 281731 1 T1 1 T2 4 T3 97
valid_sources[0x11] 273798 1 T2 6 T3 97 T5 1685
valid_sources[0x12] 270915 1 T2 4 T3 75 T5 1684
valid_sources[0x13] 352007 1 T2 1 T3 88 T5 1735
valid_sources[0x14] 318366 1 T2 3 T3 60 T5 1776
valid_sources[0x15] 268156 1 T2 1 T3 64 T5 1826
valid_sources[0x16] 298241 1 T1 3 T2 3 T3 84
valid_sources[0x17] 314890 1 T3 103 T5 1704 T6 2398
valid_sources[0x18] 289743 1 T2 3 T3 59 T5 1717
valid_sources[0x19] 301174 1 T2 4 T3 73 T5 1728
valid_sources[0x1a] 332300 1 T2 4 T3 89 T5 1714
valid_sources[0x1b] 257847 1 T2 4 T3 99 T5 1744
valid_sources[0x1c] 308749 1 T2 5 T3 91 T5 1661
valid_sources[0x1d] 318529 1 T1 2 T2 3 T3 75
valid_sources[0x1e] 339570 1 T1 1 T2 1 T3 82
valid_sources[0x1f] 260865 1 T2 4 T3 82 T5 1713
valid_sources[0x20] 286709 1 T2 3 T3 73 T5 1696
valid_sources[0x21] 275206 1 T2 3 T3 84 T5 1690
valid_sources[0x22] 252296 1 T2 5 T3 93 T5 1618
valid_sources[0x23] 313006 1 T2 5 T3 71 T5 1711
valid_sources[0x24] 273552 1 T1 1 T2 7 T3 76
valid_sources[0x25] 342890 1 T2 5 T3 83 T5 1698
valid_sources[0x26] 310459 1 T2 4 T3 68 T5 1753
valid_sources[0x27] 303133 1 T2 16 T3 82 T5 1707
valid_sources[0x28] 272073 1 T1 5 T2 4 T3 85
valid_sources[0x29] 455839 1 T2 6 T3 55 T5 1663
valid_sources[0x2a] 287885 1 T1 1 T2 3 T3 59
valid_sources[0x2b] 318108 1 T2 8 T3 90 T5 1701
valid_sources[0x2c] 328069 1 T2 1 T3 71 T5 1752
valid_sources[0x2d] 286477 1 T1 1 T2 5 T3 67
valid_sources[0x2e] 325273 1 T2 2 T3 104 T5 1693
valid_sources[0x2f] 287213 1 T1 1 T2 3 T3 78
valid_sources[0x30] 281342 1 T2 4 T3 60 T5 1734
valid_sources[0x31] 300243 1 T2 7 T3 63 T5 1766
valid_sources[0x32] 272261 1 T2 3 T3 85 T5 1772
valid_sources[0x33] 263182 1 T2 6 T3 101 T5 1765
valid_sources[0x34] 279563 1 T1 3 T2 1 T3 79
valid_sources[0x35] 274195 1 T2 2 T3 76 T5 1642
valid_sources[0x36] 316770 1 T2 15 T3 92 T5 1722
valid_sources[0x37] 301250 1 T1 1 T2 6 T3 74
valid_sources[0x38] 257922 1 T2 2 T3 103 T5 1702
valid_sources[0x39] 318430 1 T2 5 T3 79 T5 1678
valid_sources[0x3a] 296965 1 T2 5 T3 84 T5 1668
valid_sources[0x3b] 295103 1 T2 2 T3 77 T5 1651
valid_sources[0x3c] 308127 1 T2 7 T3 47 T5 1649
valid_sources[0x3d] 294787 1 T1 1 T2 4 T3 88
valid_sources[0x3e] 298175 1 T2 2 T3 66 T5 1727
valid_sources[0x3f] 326871 1 T2 11 T3 91 T5 1638
valid_sources[0x40] 260015 1 T2 1 T3 90 T5 1617
valid_sources[0x41] 642719 1 T2 3 T3 114 T5 1773
valid_sources[0x42] 278412 1 T2 7 T3 80 T5 1736
valid_sources[0x43] 275831 1 T2 5 T3 73 T5 1684
valid_sources[0x44] 269667 1 T1 5 T2 9 T3 59
valid_sources[0x45] 290927 1 T2 3 T3 90 T5 1691
valid_sources[0x46] 324506 1 T2 1 T3 67 T5 1698
valid_sources[0x47] 290039 1 T2 3 T3 68 T5 1683
valid_sources[0x48] 323588 1 T2 2 T3 86 T5 1708
valid_sources[0x49] 296265 1 T2 3 T3 68 T5 1731
valid_sources[0x4a] 294600 1 T2 6 T3 58 T5 1739
valid_sources[0x4b] 314344 1 T2 5 T3 74 T5 1734
valid_sources[0x4c] 290642 1 T2 2 T3 81 T5 1691
valid_sources[0x4d] 298637 1 T2 2 T3 79 T5 1697
valid_sources[0x4e] 280647 1 T1 1 T2 2 T3 74
valid_sources[0x4f] 326707 1 T2 4 T3 67 T5 1717
valid_sources[0x50] 272437 1 T2 4 T3 89 T5 1692
valid_sources[0x51] 264289 1 T2 5 T3 85 T5 1775
valid_sources[0x52] 289629 1 T2 2 T3 104 T5 1743
valid_sources[0x53] 338135 1 T3 90 T5 1718 T6 2538
valid_sources[0x54] 288089 1 T1 1 T2 3 T3 75
valid_sources[0x55] 306643 1 T2 4 T3 110 T5 1694
valid_sources[0x56] 344821 1 T2 2 T3 85 T5 1649
valid_sources[0x57] 319552 1 T2 3 T3 73 T5 1652
valid_sources[0x58] 346914 1 T2 1 T3 67 T5 1680
valid_sources[0x59] 279777 1 T2 2 T3 123 T5 1712
valid_sources[0x5a] 288725 1 T2 5 T3 52 T5 1741
valid_sources[0x5b] 254791 1 T3 93 T5 1773 T6 2365
valid_sources[0x5c] 357617 1 T1 1 T2 5 T3 80
valid_sources[0x5d] 368045 1 T2 4 T3 72 T5 1711
valid_sources[0x5e] 302033 1 T2 4 T3 73 T5 1757
valid_sources[0x5f] 276527 1 T2 3 T3 97 T5 1743
valid_sources[0x60] 304899 1 T2 4 T3 86 T5 1642
valid_sources[0x61] 288040 1 T2 2 T3 102 T5 1629
valid_sources[0x62] 354669 1 T2 2 T3 75 T5 1749
valid_sources[0x63] 371588 1 T1 4 T2 4 T3 72
valid_sources[0x64] 255386 1 T3 93 T5 1736 T6 2302
valid_sources[0x65] 287494 1 T2 8 T3 91 T5 1748
valid_sources[0x66] 274901 1 T3 85 T5 1683 T6 2339
valid_sources[0x67] 298753 1 T2 7 T3 83 T5 1751
valid_sources[0x68] 270431 1 T1 1 T2 1 T3 63
valid_sources[0x69] 399931 1 T2 5 T3 95 T5 1755
valid_sources[0x6a] 287549 1 T2 2 T3 61 T5 1712
valid_sources[0x6b] 314353 1 T2 9 T3 68 T5 1824
valid_sources[0x6c] 446049 1 T2 2 T3 74 T5 1730
valid_sources[0x6d] 354827 1 T3 86 T5 1761 T6 2269
valid_sources[0x6e] 265560 1 T2 2 T3 59 T5 1695
valid_sources[0x6f] 292017 1 T2 2 T3 97 T5 1674
valid_sources[0x70] 284919 1 T2 7 T3 101 T5 1746
valid_sources[0x71] 297044 1 T2 6 T3 74 T5 1694
valid_sources[0x72] 341897 1 T2 6 T3 58 T5 1664
valid_sources[0x73] 266809 1 T2 2 T3 103 T5 1715
valid_sources[0x74] 291898 1 T2 3 T3 75 T5 1702
valid_sources[0x75] 311284 1 T2 5 T3 67 T5 1732
valid_sources[0x76] 314418 1 T3 92 T5 1744 T6 2286
valid_sources[0x77] 297680 1 T3 81 T5 1721 T6 2302
valid_sources[0x78] 300931 1 T2 2 T3 80 T5 1839
valid_sources[0x79] 300972 1 T2 4 T3 73 T5 1720
valid_sources[0x7a] 295148 1 T2 5 T3 56 T5 1741
valid_sources[0x7b] 317604 1 T1 1 T2 10 T3 55
valid_sources[0x7c] 310093 1 T2 2 T3 74 T5 1719
valid_sources[0x7d] 303486 1 T2 6 T3 66 T5 1712
valid_sources[0x7e] 299101 1 T2 6 T3 51 T5 1627
valid_sources[0x7f] 304198 1 T2 5 T3 66 T5 1717
valid_sources[0x80] 313548 1 T2 1 T3 100 T5 1670



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 18038336 1 T1 1 T2 141 T3 8
values[0x0] all_enables biggest_size 1527805 1 T1 3 T2 82 T3 11
values[0x1] all_enables biggest_size 1481112 1 T1 2 T2 47 T3 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%