Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	4832723	0	0
ctrl_rd_A	2147483647	79438	0	0
intr_enable_rd_A	2147483647	69474	0	0
ovrd_rd_A	2147483647	78067	0	0
timeout_ctrl_rd_A	2147483647	78059	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4832723	0	0
T9	112069	310339	0	0
T10	205258	0	0	0
T12	0	119244	0	0
T13	121625	0	0	0
T14	155384	0	0	0
T16	568335	0	0	0
T22	841602	0	0	0
T26	126817	0	0	0
T27	0	301277	0	0
T28	0	43219	0	0
T36	0	156943	0	0
T37	0	220623	0	0
T38	0	136999	0	0
T39	0	175595	0	0
T40	0	80840	0	0
T41	0	211084	0	0
T42	210909	0	0	0
T43	383634	0	0	0
T44	10523	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	79438	0	0
T28	169308	4642	0	0
T36	384864	0	0	0
T39	0	7236	0	0
T60	0	3427	0	0
T104	0	5652	0	0
T105	0	1848	0	0
T106	0	5714	0	0
T107	0	7040	0	0
T108	0	23672	0	0
T109	0	7026	0	0
T110	0	9457	0	0
T111	159740	0	0	0
T112	228681	0	0	0
T113	352900	0	0	0
T114	131954	0	0	0
T115	619132	0	0	0
T116	294694	0	0	0
T117	293425	0	0	0
T118	197580	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69474	0	0
T28	169308	4103	0	0
T36	384864	0	0	0
T39	0	6651	0	0
T60	0	3113	0	0
T104	0	4839	0	0
T105	0	1532	0	0
T106	0	4866	0	0
T107	0	6247	0	0
T111	159740	0	0	0
T112	228681	0	0	0
T113	352900	0	0	0
T114	131954	0	0	0
T115	619132	0	0	0
T116	294694	0	0	0
T117	293425	0	0	0
T118	197580	0	0	0
T119	0	14	0	0
T120	0	18	0	0
T121	0	10	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	78067	0	0
T28	169308	4501	0	0
T36	384864	0	0	0
T39	0	7776	0	0
T60	0	3596	0	0
T104	0	5697	0	0
T105	0	1895	0	0
T106	0	5721	0	0
T107	0	7085	0	0
T108	0	23759	0	0
T109	0	6969	0	0
T110	0	9331	0	0
T111	159740	0	0	0
T112	228681	0	0	0
T113	352900	0	0	0
T114	131954	0	0	0
T115	619132	0	0	0
T116	294694	0	0	0
T117	293425	0	0	0
T118	197580	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	78059	0	0
T28	169308	4619	0	0
T36	384864	0	0	0
T39	0	7540	0	0
T60	0	3446	0	0
T104	0	5470	0	0
T105	0	1885	0	0
T106	0	5759	0	0
T107	0	7613	0	0
T108	0	23284	0	0
T109	0	7144	0	0
T110	0	9597	0	0
T111	159740	0	0	0
T112	228681	0	0	0
T113	352900	0	0	0
T114	131954	0	0	0
T115	619132	0	0	0
T116	294694	0	0	0
T117	293425	0	0	0
T118	197580	0	0	0