Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5198606	0	0
ctrl_rd_A	2147483647	163784	0	0
intr_enable_rd_A	2147483647	145045	0	0
ovrd_rd_A	2147483647	161194	0	0
timeout_ctrl_rd_A	2147483647	161917	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5198606	0	0
T9	342329	86555	0	0
T10	103471	0	0	0
T14	102533	0	0	0
T15	335528	0	0	0
T17	249473	0	0	0
T19	163385	0	0	0
T20	99909	0	0	0
T22	107224	0	0	0
T23	0	130362	0	0
T24	0	73480	0	0
T31	0	57809	0	0
T32	0	145600	0	0
T33	0	41708	0	0
T34	0	113129	0	0
T35	0	46236	0	0
T36	0	193322	0	0
T37	0	263888	0	0
T38	299204	0	0	0
T39	232178	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	163784	0	0
T9	342329	8537	0	0
T10	103471	0	0	0
T14	102533	0	0	0
T15	335528	0	0	0
T17	249473	0	0	0
T19	163385	0	0	0
T20	99909	0	0	0
T22	107224	0	0	0
T23	0	14240	0	0
T31	0	7214	0	0
T32	0	16391	0	0
T33	0	4587	0	0
T38	299204	0	0	0
T39	232178	0	0	0
T99	0	9127	0	0
T100	0	5675	0	0
T101	0	5139	0	0
T102	0	6588	0	0
T103	0	7837	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	145045	0	0
T9	342329	7740	0	0
T10	103471	0	0	0
T14	102533	0	0	0
T15	335528	0	0	0
T17	249473	0	0	0
T19	163385	0	0	0
T20	99909	0	0	0
T22	107224	0	0	0
T23	0	12384	0	0
T31	0	5802	0	0
T32	0	14387	0	0
T33	0	4218	0	0
T38	299204	0	0	0
T39	232178	0	0	0
T99	0	8172	0	0
T100	0	5324	0	0
T104	0	24	0	0
T105	0	17	0	0
T106	0	8	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	161194	0	0
T9	342329	8635	0	0
T10	103471	0	0	0
T14	102533	0	0	0
T15	335528	0	0	0
T17	249473	0	0	0
T19	163385	0	0	0
T20	99909	0	0	0
T22	107224	0	0	0
T23	0	14783	0	0
T31	0	6884	0	0
T32	0	16135	0	0
T33	0	4235	0	0
T38	299204	0	0	0
T39	232178	0	0	0
T99	0	8824	0	0
T100	0	5702	0	0
T101	0	5464	0	0
T102	0	6690	0	0
T103	0	8292	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	161917	0	0
T9	342329	9525	0	0
T10	103471	0	0	0
T14	102533	0	0	0
T15	335528	0	0	0
T17	249473	0	0	0
T19	163385	0	0	0
T20	99909	0	0	0
T22	107224	0	0	0
T23	0	14397	0	0
T31	0	6726	0	0
T32	0	15941	0	0
T33	0	4320	0	0
T38	299204	0	0	0
T39	232178	0	0	0
T99	0	8694	0	0
T100	0	5895	0	0
T101	0	5261	0	0
T102	0	6786	0	0
T103	0	7698	0	0