Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59715497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24723726

1

T1

12

T3

745

T4

130

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80302725	1			T1	1157		T2	1		T3	26189
values[0x0]	1967655	1			T1	5		T2	2		T3	158
values[0x1]	2168843	1			T1	8		T2	1		T3	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42306092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42133131

1

T1

423

T2

1

T3

9077

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	390838	1			T4	16		T5	82072		T6	4
valid_sources[0x01]	380836	1			T4	16		T5	54010		T6	2
valid_sources[0x02]	326591	1			T1	34		T4	16		T5	3208
valid_sources[0x03]	316052	1			T4	13		T5	3878		T6	2
valid_sources[0x04]	304208	1			T4	10		T5	2708		T6	1
valid_sources[0x05]	318644	1			T4	13		T5	14494		T8	97
valid_sources[0x06]	299152	1			T4	16		T5	2565		T6	3
valid_sources[0x07]	351044	1			T4	17		T5	2838		T6	1
valid_sources[0x08]	322829	1			T4	9		T5	3324		T6	2
valid_sources[0x09]	341335	1			T4	9		T5	3022		T6	1
valid_sources[0x0a]	315862	1			T4	10		T5	3795		T6	8
valid_sources[0x0b]	337037	1			T4	13		T5	19147		T6	1
valid_sources[0x0c]	367400	1			T4	16		T5	60258		T6	2
valid_sources[0x0d]	364552	1			T4	11		T5	2137		T6	1
valid_sources[0x0e]	296560	1			T4	9		T5	3041		T6	2
valid_sources[0x0f]	304040	1			T4	11		T5	1895		T6	1
valid_sources[0x10]	303783	1			T4	4		T5	3233		T8	89
valid_sources[0x11]	314701	1			T4	17		T5	3635		T6	2
valid_sources[0x12]	308233	1			T4	10		T5	2916		T8	107
valid_sources[0x13]	316118	1			T4	15		T5	3219		T6	1
valid_sources[0x14]	348579	1			T4	11		T5	4893		T6	2
valid_sources[0x15]	313614	1			T4	14		T5	2832		T6	2
valid_sources[0x16]	319054	1			T4	8		T5	2672		T6	3
valid_sources[0x17]	314327	1			T1	16		T4	13		T5	2578
valid_sources[0x18]	324458	1			T4	14		T5	2332		T6	1
valid_sources[0x19]	328698	1			T4	15		T5	2457		T8	97
valid_sources[0x1a]	304890	1			T4	15		T5	2724		T6	9
valid_sources[0x1b]	317399	1			T4	4		T5	2115		T8	104
valid_sources[0x1c]	337098	1			T4	14		T5	2609		T6	3
valid_sources[0x1d]	361588	1			T4	9		T5	2125		T6	4
valid_sources[0x1e]	316088	1			T4	15		T5	2872		T6	2
valid_sources[0x1f]	322049	1			T4	7		T5	2478		T6	1
valid_sources[0x20]	317085	1			T4	10		T5	2472		T6	3
valid_sources[0x21]	385004	1			T4	21		T5	2756		T6	3
valid_sources[0x22]	296441	1			T4	7		T5	2549		T8	90
valid_sources[0x23]	295863	1			T4	8		T5	2181		T6	5
valid_sources[0x24]	298412	1			T3	2785		T4	7		T5	3046
valid_sources[0x25]	322924	1			T4	13		T5	3011		T6	2
valid_sources[0x26]	327904	1			T4	14		T5	2549		T6	2
valid_sources[0x27]	304321	1			T4	15		T5	3326		T6	1
valid_sources[0x28]	311286	1			T4	14		T5	2177		T6	2
valid_sources[0x29]	319018	1			T4	14		T5	2459		T8	101
valid_sources[0x2a]	312323	1			T4	14		T5	3020		T6	2
valid_sources[0x2b]	314879	1			T4	8		T5	3904		T6	1
valid_sources[0x2c]	348243	1			T4	15		T5	30403		T8	111
valid_sources[0x2d]	310222	1			T4	10		T5	2171		T6	5
valid_sources[0x2e]	303534	1			T4	15		T5	1952		T6	2
valid_sources[0x2f]	316876	1			T4	7		T5	2462		T6	4
valid_sources[0x30]	349641	1			T4	11		T5	39748		T6	1
valid_sources[0x31]	323838	1			T4	9		T5	2876		T6	4
valid_sources[0x32]	309590	1			T4	14		T5	1726		T8	110
valid_sources[0x33]	376729	1			T3	1		T4	12		T5	2043
valid_sources[0x34]	301908	1			T4	10		T5	2316		T8	107
valid_sources[0x35]	321356	1			T3	1071		T4	18		T5	2058
valid_sources[0x36]	330187	1			T3	5068		T4	14		T5	3365
valid_sources[0x37]	300744	1			T4	27		T5	2069		T8	101
valid_sources[0x38]	362667	1			T3	1		T4	22		T5	2789
valid_sources[0x39]	334763	1			T4	7		T5	3925		T6	6
valid_sources[0x3a]	316725	1			T4	18		T5	2173		T6	4
valid_sources[0x3b]	353519	1			T4	17		T5	2216		T8	114
valid_sources[0x3c]	328105	1			T2	2		T4	14		T5	3412
valid_sources[0x3d]	334439	1			T4	17		T5	2989		T6	6
valid_sources[0x3e]	307635	1			T4	15		T5	6661		T6	3
valid_sources[0x3f]	323169	1			T4	9		T5	2784		T6	4
valid_sources[0x40]	331306	1			T4	13		T5	2467		T6	1
valid_sources[0x41]	328031	1			T4	25		T5	3817		T6	2
valid_sources[0x42]	349590	1			T4	12		T5	2613		T6	2
valid_sources[0x43]	369335	1			T4	13		T5	3742		T6	2
valid_sources[0x44]	334257	1			T4	13		T5	2223		T6	3
valid_sources[0x45]	460513	1			T4	13		T5	4120		T6	3
valid_sources[0x46]	303421	1			T4	9		T5	3109		T8	116
valid_sources[0x47]	306767	1			T4	12		T5	2228		T6	1
valid_sources[0x48]	314047	1			T4	7		T5	2665		T6	2
valid_sources[0x49]	299912	1			T2	1		T4	8		T5	4427
valid_sources[0x4a]	315368	1			T4	16		T5	2562		T6	2
valid_sources[0x4b]	312342	1			T4	12		T5	2561		T8	99
valid_sources[0x4c]	325851	1			T4	16		T5	2919		T6	3
valid_sources[0x4d]	304422	1			T4	16		T5	2468		T6	6
valid_sources[0x4e]	295679	1			T4	10		T5	3281		T8	123
valid_sources[0x4f]	301208	1			T4	13		T5	2497		T6	2
valid_sources[0x50]	323292	1			T3	1		T4	14		T5	2586
valid_sources[0x51]	315019	1			T4	8		T5	3036		T6	1
valid_sources[0x52]	348612	1			T4	10		T5	2085		T6	4
valid_sources[0x53]	311315	1			T4	13		T5	3124		T6	1
valid_sources[0x54]	336478	1			T4	11		T5	3209		T8	113
valid_sources[0x55]	344846	1			T4	18		T5	2221		T6	3
valid_sources[0x56]	301854	1			T4	12		T5	4420		T8	121
valid_sources[0x57]	317087	1			T4	10		T5	2376		T6	2
valid_sources[0x58]	314698	1			T4	8		T5	2914		T8	131
valid_sources[0x59]	326113	1			T4	8		T5	2642		T6	3
valid_sources[0x5a]	329249	1			T4	13		T5	3375		T6	4
valid_sources[0x5b]	311087	1			T4	13		T5	2448		T8	129
valid_sources[0x5c]	333336	1			T4	2		T5	2460		T6	1
valid_sources[0x5d]	327404	1			T4	10		T5	2056		T6	3
valid_sources[0x5e]	355283	1			T4	13		T5	2859		T8	129
valid_sources[0x5f]	327693	1			T4	16		T5	2356		T8	121
valid_sources[0x60]	423951	1			T4	16		T5	2895		T6	5
valid_sources[0x61]	341949	1			T4	10		T5	3019		T6	2
valid_sources[0x62]	305311	1			T4	13		T5	2605		T6	6
valid_sources[0x63]	336065	1			T4	23		T5	2013		T6	7
valid_sources[0x64]	311462	1			T4	13		T5	2565		T6	3
valid_sources[0x65]	325024	1			T4	10		T5	3343		T6	10
valid_sources[0x66]	490055	1			T4	10		T5	16474		T6	2
valid_sources[0x67]	302014	1			T4	15		T5	4729		T6	4
valid_sources[0x68]	327310	1			T1	1		T4	22		T5	2683
valid_sources[0x69]	303952	1			T4	13		T5	2424		T6	1
valid_sources[0x6a]	402600	1			T1	1		T4	9		T5	2780
valid_sources[0x6b]	330062	1			T4	14		T5	2534		T6	2
valid_sources[0x6c]	310569	1			T4	13		T5	3901		T8	104
valid_sources[0x6d]	305955	1			T4	16		T5	2965		T6	1
valid_sources[0x6e]	339802	1			T4	11		T5	10217		T6	1
valid_sources[0x6f]	313928	1			T4	12		T5	2679		T6	1
valid_sources[0x70]	478645	1			T4	15		T5	2928		T6	4
valid_sources[0x71]	306507	1			T4	12		T5	2883		T6	2
valid_sources[0x72]	322590	1			T4	10		T5	2973		T6	2
valid_sources[0x73]	315078	1			T4	7		T5	3318		T6	1
valid_sources[0x74]	323910	1			T4	15		T5	3207		T6	1
valid_sources[0x75]	302729	1			T4	11		T5	2436		T6	2
valid_sources[0x76]	301173	1			T3	1		T4	10		T5	3238
valid_sources[0x77]	368874	1			T4	12		T5	3209		T6	1
valid_sources[0x78]	483311	1			T4	21		T5	121105		T8	94
valid_sources[0x79]	323242	1			T4	17		T5	2566		T6	2
valid_sources[0x7a]	322525	1			T4	15		T5	2743		T6	1
valid_sources[0x7b]	306967	1			T4	10		T5	2738		T6	4
valid_sources[0x7c]	323274	1			T4	10		T5	2233		T6	1
valid_sources[0x7d]	319733	1			T4	14		T5	2606		T6	4
valid_sources[0x7e]	306018	1			T4	13		T5	2325		T6	2
valid_sources[0x7f]	334486	1			T2	1		T4	12		T5	2609
valid_sources[0x80]	327799	1			T4	7		T5	2706		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21282134

1

T1

7

T3

638

T4

69

values[0x0]

all_enables

biggest_size

1746817

1

T1

3

T3

57

T4

37

values[0x1]

all_enables

biggest_size

1694775

1

T1

2

T3

50

T4

24