Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5411569	0	0
ctrl_rd_A	2147483647	165827	0	0
intr_enable_rd_A	2147483647	146548	0	0
ovrd_rd_A	2147483647	164618	0	0
timeout_ctrl_rd_A	2147483647	164742	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5411569	0	0
T11	919368	123857	0	0
T12	0	47379	0	0
T15	407456	0	0	0
T18	62909	0	0	0
T21	521525	0	0	0
T24	522593	0	0	0
T25	0	78942	0	0
T33	0	75185	0	0
T34	0	137832	0	0
T35	0	211215	0	0
T36	0	296244	0	0
T37	0	147745	0	0
T38	0	131243	0	0
T39	0	100889	0	0
T40	560009	0	0	0
T41	652128	0	0	0
T42	123193	0	0	0
T43	223618	0	0	0
T44	88497	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	165827	0	0
T11	919368	7268	0	0
T12	0	5641	0	0
T15	407456	0	0	0
T18	62909	0	0	0
T21	521525	0	0	0
T24	522593	0	0	0
T34	0	16202	0	0
T35	0	11565	0	0
T36	0	24202	0	0
T40	560009	0	0	0
T41	652128	0	0	0
T42	123193	0	0	0
T43	223618	0	0	0
T44	88497	0	0	0
T47	0	10069	0	0
T53	0	11905	0	0
T103	0	7742	0	0
T104	0	17111	0	0
T105	0	5751	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	146548	0	0
T11	919368	6497	0	0
T12	0	4800	0	0
T15	407456	0	0	0
T18	62909	0	0	0
T21	521525	0	0	0
T24	522593	0	0	0
T34	0	14069	0	0
T35	0	10250	0	0
T36	0	21735	0	0
T40	560009	0	0	0
T41	652128	0	0	0
T42	123193	0	0	0
T43	223618	0	0	0
T44	88497	0	0	0
T47	0	8918	0	0
T53	0	10508	0	0
T103	0	6741	0	0
T106	0	14	0	0
T107	0	2	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	164618	0	0
T11	919368	7523	0	0
T12	0	5454	0	0
T15	407456	0	0	0
T18	62909	0	0	0
T21	521525	0	0	0
T24	522593	0	0	0
T34	0	15580	0	0
T35	0	11709	0	0
T36	0	23906	0	0
T40	560009	0	0	0
T41	652128	0	0	0
T42	123193	0	0	0
T43	223618	0	0	0
T44	88497	0	0	0
T47	0	9982	0	0
T53	0	11916	0	0
T103	0	7607	0	0
T104	0	16527	0	0
T105	0	6174	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	164742	0	0
T11	919368	7700	0	0
T12	0	5276	0	0
T15	407456	0	0	0
T18	62909	0	0	0
T21	521525	0	0	0
T24	522593	0	0	0
T34	0	15396	0	0
T35	0	11637	0	0
T36	0	24486	0	0
T40	560009	0	0	0
T41	652128	0	0	0
T42	123193	0	0	0
T43	223618	0	0	0
T44	88497	0	0	0
T47	0	10390	0	0
T53	0	12116	0	0
T103	0	7687	0	0
T104	0	17112	0	0
T105	0	5846	0	0