Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.95 99.38 97.89 100.00 98.83 100.00 97.61


Total test records in report: 1258
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T1042 /workspace/coverage/default/14.uart_noise_filter.2932891968 Mar 10 12:50:33 PM PDT 24 Mar 10 12:52:17 PM PDT 24 68517223006 ps
T1043 /workspace/coverage/default/36.uart_fifo_reset.1755028072 Mar 10 12:54:05 PM PDT 24 Mar 10 12:55:12 PM PDT 24 144539244712 ps
T1044 /workspace/coverage/default/14.uart_smoke.3768599426 Mar 10 12:50:28 PM PDT 24 Mar 10 12:50:29 PM PDT 24 108803319 ps
T1045 /workspace/coverage/default/38.uart_fifo_overflow.187840966 Mar 10 12:54:12 PM PDT 24 Mar 10 12:55:20 PM PDT 24 166078703948 ps
T1046 /workspace/coverage/default/38.uart_fifo_full.705001033 Mar 10 12:54:12 PM PDT 24 Mar 10 01:03:34 PM PDT 24 247770835739 ps
T1047 /workspace/coverage/default/40.uart_fifo_full.917289313 Mar 10 12:54:34 PM PDT 24 Mar 10 12:55:13 PM PDT 24 59417650567 ps
T1048 /workspace/coverage/default/40.uart_stress_all.3983860282 Mar 10 12:54:50 PM PDT 24 Mar 10 01:13:25 PM PDT 24 105045889735 ps
T1049 /workspace/coverage/default/176.uart_fifo_reset.1141014872 Mar 10 12:58:24 PM PDT 24 Mar 10 12:58:34 PM PDT 24 11350156176 ps
T1050 /workspace/coverage/default/29.uart_rx_start_bit_filter.1067986946 Mar 10 12:52:59 PM PDT 24 Mar 10 12:53:01 PM PDT 24 1766372191 ps
T371 /workspace/coverage/default/240.uart_fifo_reset.4005501164 Mar 10 12:59:10 PM PDT 24 Mar 10 12:59:29 PM PDT 24 139550032723 ps
T1051 /workspace/coverage/default/20.uart_fifo_overflow.1336588711 Mar 10 12:51:30 PM PDT 24 Mar 10 12:51:46 PM PDT 24 99179064232 ps
T1052 /workspace/coverage/default/235.uart_fifo_reset.2180879727 Mar 10 12:59:06 PM PDT 24 Mar 10 12:59:24 PM PDT 24 13443250218 ps
T1053 /workspace/coverage/default/187.uart_fifo_reset.4235510652 Mar 10 12:58:29 PM PDT 24 Mar 10 12:59:57 PM PDT 24 57437033806 ps
T1054 /workspace/coverage/default/33.uart_tx_ovrd.3032388669 Mar 10 12:53:33 PM PDT 24 Mar 10 12:53:35 PM PDT 24 2156161358 ps
T1055 /workspace/coverage/default/11.uart_rx_oversample.2041289043 Mar 10 12:50:08 PM PDT 24 Mar 10 12:51:10 PM PDT 24 6734438838 ps
T346 /workspace/coverage/default/43.uart_fifo_overflow.1213864708 Mar 10 12:55:03 PM PDT 24 Mar 10 01:00:40 PM PDT 24 215870127544 ps
T1056 /workspace/coverage/default/11.uart_smoke.2124250719 Mar 10 12:50:01 PM PDT 24 Mar 10 12:50:04 PM PDT 24 648751552 ps
T1057 /workspace/coverage/default/132.uart_fifo_reset.2169630757 Mar 10 12:57:45 PM PDT 24 Mar 10 12:58:49 PM PDT 24 120716389783 ps
T246 /workspace/coverage/default/248.uart_fifo_reset.872477182 Mar 10 12:59:16 PM PDT 24 Mar 10 12:59:56 PM PDT 24 44939858309 ps
T1058 /workspace/coverage/default/37.uart_perf.3205875200 Mar 10 12:54:12 PM PDT 24 Mar 10 01:06:36 PM PDT 24 18154403762 ps
T1059 /workspace/coverage/default/41.uart_rx_start_bit_filter.171280745 Mar 10 12:54:48 PM PDT 24 Mar 10 12:54:50 PM PDT 24 5303504048 ps
T1060 /workspace/coverage/default/13.uart_rx_start_bit_filter.3725231814 Mar 10 12:50:26 PM PDT 24 Mar 10 12:50:37 PM PDT 24 6740569771 ps
T1061 /workspace/coverage/default/39.uart_noise_filter.2843878283 Mar 10 12:54:31 PM PDT 24 Mar 10 12:54:49 PM PDT 24 51911480537 ps
T1062 /workspace/coverage/default/21.uart_loopback.3852465965 Mar 10 12:51:40 PM PDT 24 Mar 10 12:51:43 PM PDT 24 1493958880 ps
T1063 /workspace/coverage/default/20.uart_rx_start_bit_filter.13994707 Mar 10 12:51:35 PM PDT 24 Mar 10 12:51:38 PM PDT 24 4482794843 ps
T1064 /workspace/coverage/default/2.uart_stress_all.2850267444 Mar 10 12:48:30 PM PDT 24 Mar 10 12:51:11 PM PDT 24 293646042116 ps
T1065 /workspace/coverage/default/44.uart_tx_ovrd.1353297960 Mar 10 12:55:23 PM PDT 24 Mar 10 12:55:26 PM PDT 24 2639575308 ps
T1066 /workspace/coverage/default/91.uart_fifo_reset.4014886684 Mar 10 12:57:02 PM PDT 24 Mar 10 12:57:39 PM PDT 24 70445614298 ps
T1067 /workspace/coverage/default/67.uart_fifo_reset.3415446405 Mar 10 01:00:30 PM PDT 24 Mar 10 01:01:14 PM PDT 24 100733016672 ps
T1068 /workspace/coverage/default/41.uart_stress_all.1592220489 Mar 10 12:54:52 PM PDT 24 Mar 10 12:57:50 PM PDT 24 575418234219 ps
T1069 /workspace/coverage/default/37.uart_loopback.484732733 Mar 10 12:54:12 PM PDT 24 Mar 10 12:54:20 PM PDT 24 3557033998 ps
T1070 /workspace/coverage/default/28.uart_smoke.2222768580 Mar 10 12:52:41 PM PDT 24 Mar 10 12:52:43 PM PDT 24 290185338 ps
T1071 /workspace/coverage/default/30.uart_smoke.3154309376 Mar 10 12:53:07 PM PDT 24 Mar 10 12:53:09 PM PDT 24 310533939 ps
T1072 /workspace/coverage/default/23.uart_stress_all.3604946721 Mar 10 12:52:01 PM PDT 24 Mar 10 12:58:37 PM PDT 24 471115304781 ps
T1073 /workspace/coverage/default/24.uart_smoke.1516694296 Mar 10 12:52:02 PM PDT 24 Mar 10 12:52:13 PM PDT 24 5520589810 ps
T275 /workspace/coverage/default/37.uart_stress_all.3014695505 Mar 10 12:54:12 PM PDT 24 Mar 10 01:11:26 PM PDT 24 282640635935 ps
T1074 /workspace/coverage/default/25.uart_long_xfer_wo_dly.2321977685 Mar 10 12:52:21 PM PDT 24 Mar 10 12:54:44 PM PDT 24 88308574390 ps
T1075 /workspace/coverage/default/74.uart_fifo_reset.643575115 Mar 10 12:56:43 PM PDT 24 Mar 10 12:57:12 PM PDT 24 38474644931 ps
T93 /workspace/coverage/default/4.uart_sec_cm.1664022261 Mar 10 12:48:55 PM PDT 24 Mar 10 12:48:56 PM PDT 24 148236714 ps
T1076 /workspace/coverage/default/18.uart_tx_rx.1463215161 Mar 10 12:51:07 PM PDT 24 Mar 10 12:51:45 PM PDT 24 58036699707 ps
T1077 /workspace/coverage/default/146.uart_fifo_reset.3747575380 Mar 10 12:58:02 PM PDT 24 Mar 10 12:58:26 PM PDT 24 12539637185 ps
T1078 /workspace/coverage/default/42.uart_intr.1192584195 Mar 10 12:54:56 PM PDT 24 Mar 10 01:03:21 PM PDT 24 1029211736609 ps
T1079 /workspace/coverage/default/2.uart_perf.637050034 Mar 10 12:48:26 PM PDT 24 Mar 10 12:56:33 PM PDT 24 17979369947 ps
T311 /workspace/coverage/default/194.uart_fifo_reset.1444969425 Mar 10 12:58:35 PM PDT 24 Mar 10 12:59:24 PM PDT 24 101222201453 ps
T1080 /workspace/coverage/default/20.uart_alert_test.3425723457 Mar 10 12:51:36 PM PDT 24 Mar 10 12:51:37 PM PDT 24 15115697 ps
T1081 /workspace/coverage/default/4.uart_tx_ovrd.4020665132 Mar 10 12:48:55 PM PDT 24 Mar 10 12:49:41 PM PDT 24 7359404815 ps
T1082 /workspace/coverage/default/33.uart_fifo_reset.3550099510 Mar 10 12:53:32 PM PDT 24 Mar 10 12:53:37 PM PDT 24 9849814637 ps
T1083 /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2321838121 Mar 10 12:53:55 PM PDT 24 Mar 10 01:03:36 PM PDT 24 196324835839 ps
T1084 /workspace/coverage/default/41.uart_tx_rx.2526141597 Mar 10 12:54:49 PM PDT 24 Mar 10 12:55:26 PM PDT 24 26693050924 ps
T94 /workspace/coverage/default/0.uart_sec_cm.1863190301 Mar 10 12:48:08 PM PDT 24 Mar 10 12:48:10 PM PDT 24 73683997 ps
T1085 /workspace/coverage/default/4.uart_rx_oversample.595177966 Mar 10 12:48:50 PM PDT 24 Mar 10 12:48:58 PM PDT 24 3924558503 ps
T1086 /workspace/coverage/default/30.uart_stress_all_with_rand_reset.7639255 Mar 10 12:53:11 PM PDT 24 Mar 10 01:00:18 PM PDT 24 43717352969 ps
T1087 /workspace/coverage/default/39.uart_tx_ovrd.4261140413 Mar 10 12:54:28 PM PDT 24 Mar 10 12:54:42 PM PDT 24 6397693148 ps
T1088 /workspace/coverage/default/5.uart_rx_start_bit_filter.1700134014 Mar 10 12:49:01 PM PDT 24 Mar 10 12:49:02 PM PDT 24 600429363 ps
T1089 /workspace/coverage/default/10.uart_perf.3651348616 Mar 10 12:50:03 PM PDT 24 Mar 10 12:59:53 PM PDT 24 11982695070 ps
T1090 /workspace/coverage/default/48.uart_fifo_full.78198549 Mar 10 12:55:58 PM PDT 24 Mar 10 12:56:58 PM PDT 24 40768372536 ps
T1091 /workspace/coverage/default/284.uart_fifo_reset.4212187247 Mar 10 12:59:45 PM PDT 24 Mar 10 01:01:34 PM PDT 24 121266038586 ps
T1092 /workspace/coverage/default/45.uart_rx_parity_err.185577086 Mar 10 12:55:28 PM PDT 24 Mar 10 12:57:04 PM PDT 24 55005300073 ps
T1093 /workspace/coverage/default/43.uart_loopback.3487770461 Mar 10 12:55:07 PM PDT 24 Mar 10 12:55:15 PM PDT 24 10377762518 ps
T1094 /workspace/coverage/default/21.uart_tx_ovrd.1495362587 Mar 10 12:51:40 PM PDT 24 Mar 10 12:51:42 PM PDT 24 1435100569 ps
T220 /workspace/coverage/default/208.uart_fifo_reset.1138000785 Mar 10 12:58:49 PM PDT 24 Mar 10 01:00:22 PM PDT 24 57501616459 ps
T1095 /workspace/coverage/default/8.uart_loopback.2816168805 Mar 10 12:49:39 PM PDT 24 Mar 10 12:49:41 PM PDT 24 1056780858 ps
T1096 /workspace/coverage/default/0.uart_tx_ovrd.2220744034 Mar 10 12:47:58 PM PDT 24 Mar 10 12:47:59 PM PDT 24 538841589 ps
T1097 /workspace/coverage/default/44.uart_tx_rx.4099240507 Mar 10 12:55:11 PM PDT 24 Mar 10 12:56:06 PM PDT 24 85497389306 ps
T1098 /workspace/coverage/default/5.uart_loopback.2698977217 Mar 10 12:49:02 PM PDT 24 Mar 10 12:49:07 PM PDT 24 5727930824 ps
T1099 /workspace/coverage/default/3.uart_fifo_full.3931649054 Mar 10 12:48:34 PM PDT 24 Mar 10 12:49:02 PM PDT 24 32663426914 ps
T1100 /workspace/coverage/default/38.uart_rx_start_bit_filter.1545275424 Mar 10 12:54:18 PM PDT 24 Mar 10 12:54:22 PM PDT 24 4333420050 ps
T1101 /workspace/coverage/default/46.uart_fifo_overflow.1025403829 Mar 10 12:55:33 PM PDT 24 Mar 10 12:57:30 PM PDT 24 69024403984 ps
T218 /workspace/coverage/default/43.uart_stress_all.2716848588 Mar 10 12:55:09 PM PDT 24 Mar 10 01:14:59 PM PDT 24 229164267499 ps
T1102 /workspace/coverage/default/8.uart_fifo_full.2445998115 Mar 10 12:49:34 PM PDT 24 Mar 10 12:49:50 PM PDT 24 29908333378 ps
T1103 /workspace/coverage/default/15.uart_rx_oversample.1293441097 Mar 10 12:50:39 PM PDT 24 Mar 10 12:51:11 PM PDT 24 4233440317 ps
T1104 /workspace/coverage/default/12.uart_fifo_full.2682629511 Mar 10 12:50:14 PM PDT 24 Mar 10 12:51:02 PM PDT 24 443106289586 ps
T1105 /workspace/coverage/default/47.uart_smoke.2942037736 Mar 10 12:55:42 PM PDT 24 Mar 10 12:55:46 PM PDT 24 936251845 ps
T1106 /workspace/coverage/default/35.uart_fifo_reset.142958211 Mar 10 12:53:50 PM PDT 24 Mar 10 12:55:43 PM PDT 24 134308826327 ps
T1107 /workspace/coverage/default/24.uart_fifo_reset.1765693288 Mar 10 12:52:06 PM PDT 24 Mar 10 12:53:53 PM PDT 24 251417697853 ps
T1108 /workspace/coverage/default/29.uart_long_xfer_wo_dly.1257023570 Mar 10 12:53:00 PM PDT 24 Mar 10 01:12:28 PM PDT 24 145057953506 ps
T358 /workspace/coverage/default/171.uart_fifo_reset.1080888710 Mar 10 12:58:19 PM PDT 24 Mar 10 12:58:40 PM PDT 24 48255369038 ps
T1109 /workspace/coverage/default/11.uart_tx_ovrd.2162398594 Mar 10 12:50:08 PM PDT 24 Mar 10 12:50:18 PM PDT 24 7888212364 ps
T1110 /workspace/coverage/default/31.uart_tx_rx.62204446 Mar 10 12:53:12 PM PDT 24 Mar 10 12:53:52 PM PDT 24 44278373066 ps
T1111 /workspace/coverage/default/19.uart_intr.4136241748 Mar 10 12:51:21 PM PDT 24 Mar 10 12:54:10 PM PDT 24 98531022480 ps
T1112 /workspace/coverage/default/10.uart_alert_test.2023979456 Mar 10 12:50:01 PM PDT 24 Mar 10 12:50:03 PM PDT 24 21784601 ps
T1113 /workspace/coverage/default/192.uart_fifo_reset.4069011025 Mar 10 12:58:34 PM PDT 24 Mar 10 12:59:16 PM PDT 24 114747034293 ps
T1114 /workspace/coverage/default/36.uart_noise_filter.4050323627 Mar 10 12:54:01 PM PDT 24 Mar 10 12:54:18 PM PDT 24 36920620494 ps
T1115 /workspace/coverage/default/167.uart_fifo_reset.2087257190 Mar 10 12:58:18 PM PDT 24 Mar 10 12:58:36 PM PDT 24 11664945774 ps
T1116 /workspace/coverage/default/15.uart_perf.1037195212 Mar 10 12:50:42 PM PDT 24 Mar 10 12:52:56 PM PDT 24 2263574832 ps
T1117 /workspace/coverage/default/9.uart_fifo_overflow.1359835542 Mar 10 12:49:48 PM PDT 24 Mar 10 12:50:27 PM PDT 24 23585090178 ps
T1118 /workspace/coverage/default/117.uart_fifo_reset.2884809583 Mar 10 12:57:32 PM PDT 24 Mar 10 01:05:05 PM PDT 24 277433851051 ps
T1119 /workspace/coverage/default/4.uart_fifo_overflow.1351669293 Mar 10 12:48:50 PM PDT 24 Mar 10 12:50:02 PM PDT 24 247807655086 ps
T1120 /workspace/coverage/default/4.uart_perf.3459542046 Mar 10 12:48:56 PM PDT 24 Mar 10 12:58:20 PM PDT 24 20361034489 ps
T1121 /workspace/coverage/default/13.uart_smoke.1997674426 Mar 10 12:50:25 PM PDT 24 Mar 10 12:50:26 PM PDT 24 250110720 ps
T1122 /workspace/coverage/default/30.uart_rx_parity_err.788412534 Mar 10 12:53:11 PM PDT 24 Mar 10 12:53:44 PM PDT 24 106008257360 ps
T1123 /workspace/coverage/default/114.uart_fifo_reset.1266946727 Mar 10 12:57:31 PM PDT 24 Mar 10 12:58:15 PM PDT 24 27656173697 ps
T1124 /workspace/coverage/default/34.uart_smoke.851656450 Mar 10 12:53:39 PM PDT 24 Mar 10 12:53:42 PM PDT 24 664671131 ps
T1125 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2934426283 Mar 10 12:20:59 PM PDT 24 Mar 10 12:21:00 PM PDT 24 54809421 ps
T1126 /workspace/coverage/cover_reg_top/21.uart_intr_test.3502623811 Mar 10 12:21:24 PM PDT 24 Mar 10 12:21:25 PM PDT 24 98094140 ps
T60 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3165734863 Mar 10 12:32:53 PM PDT 24 Mar 10 12:32:54 PM PDT 24 45404784 ps
T1127 /workspace/coverage/cover_reg_top/20.uart_intr_test.1038649558 Mar 10 12:23:58 PM PDT 24 Mar 10 12:23:59 PM PDT 24 14334989 ps
T1128 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3457575335 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:13 PM PDT 24 68793362 ps
T80 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.594882365 Mar 10 12:21:29 PM PDT 24 Mar 10 12:21:30 PM PDT 24 37512076 ps
T1129 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3767436846 Mar 10 12:22:38 PM PDT 24 Mar 10 12:22:39 PM PDT 24 140160952 ps
T1130 /workspace/coverage/cover_reg_top/11.uart_intr_test.1111979983 Mar 10 12:21:21 PM PDT 24 Mar 10 12:21:22 PM PDT 24 12573655 ps
T81 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3566399855 Mar 10 12:22:52 PM PDT 24 Mar 10 12:22:54 PM PDT 24 105000161 ps
T71 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2622702175 Mar 10 12:24:38 PM PDT 24 Mar 10 12:24:39 PM PDT 24 22197153 ps
T82 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4045233485 Mar 10 12:27:34 PM PDT 24 Mar 10 12:27:36 PM PDT 24 735815243 ps
T1131 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1470672175 Mar 10 12:21:24 PM PDT 24 Mar 10 12:21:26 PM PDT 24 149088826 ps
T1132 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2702235844 Mar 10 12:24:32 PM PDT 24 Mar 10 12:24:33 PM PDT 24 21554241 ps
T87 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3096033933 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:14 PM PDT 24 273488172 ps
T1133 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3262962723 Mar 10 12:20:26 PM PDT 24 Mar 10 12:20:28 PM PDT 24 487842018 ps
T1134 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2526521020 Mar 10 12:21:20 PM PDT 24 Mar 10 12:21:21 PM PDT 24 89719541 ps
T1135 /workspace/coverage/cover_reg_top/3.uart_tl_errors.485337239 Mar 10 12:32:59 PM PDT 24 Mar 10 12:33:01 PM PDT 24 79746438 ps
T1136 /workspace/coverage/cover_reg_top/33.uart_intr_test.4223281594 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:07 PM PDT 24 15285266 ps
T1137 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3955423684 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:10 PM PDT 24 57907997 ps
T374 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3945469696 Mar 10 12:27:38 PM PDT 24 Mar 10 12:27:39 PM PDT 24 97551427 ps
T1138 /workspace/coverage/cover_reg_top/26.uart_intr_test.873132350 Mar 10 12:24:27 PM PDT 24 Mar 10 12:24:28 PM PDT 24 38308671 ps
T88 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3122720790 Mar 10 12:21:03 PM PDT 24 Mar 10 12:21:04 PM PDT 24 60614548 ps
T89 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.97589608 Mar 10 12:23:29 PM PDT 24 Mar 10 12:23:30 PM PDT 24 154313612 ps
T1139 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.615024644 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:10 PM PDT 24 90509942 ps
T1140 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1973515290 Mar 10 12:33:53 PM PDT 24 Mar 10 12:33:56 PM PDT 24 318359258 ps
T1141 /workspace/coverage/cover_reg_top/34.uart_intr_test.50626995 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:07 PM PDT 24 16247334 ps
T72 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1493321064 Mar 10 12:20:06 PM PDT 24 Mar 10 12:20:07 PM PDT 24 28357305 ps
T1142 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1926095536 Mar 10 12:33:57 PM PDT 24 Mar 10 12:33:58 PM PDT 24 58188716 ps
T90 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4116294194 Mar 10 12:18:18 PM PDT 24 Mar 10 12:18:19 PM PDT 24 146252637 ps
T1143 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3143551591 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:13 PM PDT 24 74023085 ps
T61 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1375977280 Mar 10 12:29:35 PM PDT 24 Mar 10 12:29:35 PM PDT 24 61561082 ps
T73 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.282489995 Mar 10 12:21:20 PM PDT 24 Mar 10 12:21:21 PM PDT 24 49787751 ps
T74 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3485984498 Mar 10 12:22:52 PM PDT 24 Mar 10 12:22:53 PM PDT 24 40829281 ps
T1144 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2557105006 Mar 10 12:22:25 PM PDT 24 Mar 10 12:22:27 PM PDT 24 149907753 ps
T62 /workspace/coverage/cover_reg_top/17.uart_csr_rw.117578560 Mar 10 12:27:40 PM PDT 24 Mar 10 12:27:41 PM PDT 24 18793713 ps
T1145 /workspace/coverage/cover_reg_top/25.uart_intr_test.1469412559 Mar 10 12:24:27 PM PDT 24 Mar 10 12:24:28 PM PDT 24 35654887 ps
T1146 /workspace/coverage/cover_reg_top/12.uart_intr_test.180145121 Mar 10 12:24:32 PM PDT 24 Mar 10 12:24:33 PM PDT 24 40918726 ps
T1147 /workspace/coverage/cover_reg_top/2.uart_tl_errors.4073449423 Mar 10 12:26:22 PM PDT 24 Mar 10 12:26:26 PM PDT 24 472359346 ps
T1148 /workspace/coverage/cover_reg_top/13.uart_intr_test.3575767178 Mar 10 12:24:15 PM PDT 24 Mar 10 12:24:16 PM PDT 24 36715531 ps
T1149 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3218280089 Mar 10 12:20:48 PM PDT 24 Mar 10 12:20:51 PM PDT 24 41347897 ps
T1150 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.109791847 Mar 10 12:19:23 PM PDT 24 Mar 10 12:19:25 PM PDT 24 38183521 ps
T1151 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1534469251 Mar 10 12:20:52 PM PDT 24 Mar 10 12:20:54 PM PDT 24 20965925 ps
T75 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1723874987 Mar 10 12:24:42 PM PDT 24 Mar 10 12:24:43 PM PDT 24 15025770 ps
T1152 /workspace/coverage/cover_reg_top/48.uart_intr_test.1437719807 Mar 10 12:23:55 PM PDT 24 Mar 10 12:23:57 PM PDT 24 23497865 ps
T76 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.146709659 Mar 10 12:24:26 PM PDT 24 Mar 10 12:24:28 PM PDT 24 31274772 ps
T1153 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3225227959 Mar 10 12:21:16 PM PDT 24 Mar 10 12:21:17 PM PDT 24 92914421 ps
T1154 /workspace/coverage/cover_reg_top/23.uart_intr_test.2855917446 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:12 PM PDT 24 46478868 ps
T1155 /workspace/coverage/cover_reg_top/46.uart_intr_test.1039201884 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:12 PM PDT 24 20648382 ps
T1156 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2609175421 Mar 10 12:24:57 PM PDT 24 Mar 10 12:24:58 PM PDT 24 12849896 ps
T83 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3011644232 Mar 10 12:27:37 PM PDT 24 Mar 10 12:27:39 PM PDT 24 1177475563 ps
T63 /workspace/coverage/cover_reg_top/10.uart_csr_rw.4001278666 Mar 10 12:22:26 PM PDT 24 Mar 10 12:22:27 PM PDT 24 14431052 ps
T1157 /workspace/coverage/cover_reg_top/43.uart_intr_test.3650284444 Mar 10 12:21:36 PM PDT 24 Mar 10 12:21:37 PM PDT 24 27113234 ps
T1158 /workspace/coverage/cover_reg_top/35.uart_intr_test.1081092541 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:07 PM PDT 24 10831026 ps
T1159 /workspace/coverage/cover_reg_top/12.uart_tl_errors.404164711 Mar 10 12:23:20 PM PDT 24 Mar 10 12:23:22 PM PDT 24 66259481 ps
T1160 /workspace/coverage/cover_reg_top/5.uart_tl_errors.968966756 Mar 10 12:23:10 PM PDT 24 Mar 10 12:23:12 PM PDT 24 102249502 ps
T1161 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4266336925 Mar 10 12:21:38 PM PDT 24 Mar 10 12:21:39 PM PDT 24 121944874 ps
T1162 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.465927466 Mar 10 12:26:23 PM PDT 24 Mar 10 12:26:25 PM PDT 24 26136185 ps
T85 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3871458350 Mar 10 12:24:57 PM PDT 24 Mar 10 12:24:59 PM PDT 24 93325002 ps
T1163 /workspace/coverage/cover_reg_top/16.uart_intr_test.599539283 Mar 10 12:21:28 PM PDT 24 Mar 10 12:21:29 PM PDT 24 28684596 ps
T1164 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3893033450 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:13 PM PDT 24 39989053 ps
T1165 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1862572752 Mar 10 12:19:52 PM PDT 24 Mar 10 12:19:53 PM PDT 24 18935032 ps
T1166 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4115657525 Mar 10 12:27:06 PM PDT 24 Mar 10 12:27:06 PM PDT 24 90391516 ps
T1167 /workspace/coverage/cover_reg_top/0.uart_intr_test.1187829652 Mar 10 12:24:38 PM PDT 24 Mar 10 12:24:39 PM PDT 24 45793417 ps
T375 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3889728707 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:02 PM PDT 24 159091885 ps
T1168 /workspace/coverage/cover_reg_top/1.uart_intr_test.2466363028 Mar 10 12:33:02 PM PDT 24 Mar 10 12:33:04 PM PDT 24 15813833 ps
T1169 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1040849684 Mar 10 12:21:29 PM PDT 24 Mar 10 12:21:30 PM PDT 24 105723458 ps
T1170 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.86369356 Mar 10 12:20:39 PM PDT 24 Mar 10 12:20:39 PM PDT 24 247775466 ps
T1171 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1957933123 Mar 10 12:21:38 PM PDT 24 Mar 10 12:21:38 PM PDT 24 45642160 ps
T1172 /workspace/coverage/cover_reg_top/5.uart_intr_test.2636507099 Mar 10 12:23:25 PM PDT 24 Mar 10 12:23:26 PM PDT 24 53949317 ps
T64 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1937152073 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:01 PM PDT 24 40942919 ps
T86 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1753255715 Mar 10 12:27:37 PM PDT 24 Mar 10 12:27:38 PM PDT 24 53530219 ps
T1173 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1302545266 Mar 10 12:24:43 PM PDT 24 Mar 10 12:24:47 PM PDT 24 687006065 ps
T91 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2343232470 Mar 10 12:18:02 PM PDT 24 Mar 10 12:18:04 PM PDT 24 185172250 ps
T1174 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3258154188 Mar 10 12:22:57 PM PDT 24 Mar 10 12:22:58 PM PDT 24 36369335 ps
T1175 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2939689381 Mar 10 12:27:05 PM PDT 24 Mar 10 12:27:08 PM PDT 24 171696600 ps
T1176 /workspace/coverage/cover_reg_top/8.uart_intr_test.2177369647 Mar 10 12:27:30 PM PDT 24 Mar 10 12:27:31 PM PDT 24 14937970 ps
T1177 /workspace/coverage/cover_reg_top/3.uart_intr_test.3815072871 Mar 10 12:24:13 PM PDT 24 Mar 10 12:24:14 PM PDT 24 13862976 ps
T1178 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1050055463 Mar 10 12:20:26 PM PDT 24 Mar 10 12:20:27 PM PDT 24 55797245 ps
T65 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3262886280 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:24 PM PDT 24 46970515 ps
T1179 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3315550120 Mar 10 12:26:43 PM PDT 24 Mar 10 12:26:44 PM PDT 24 69315273 ps
T70 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2363045763 Mar 10 12:23:28 PM PDT 24 Mar 10 12:23:29 PM PDT 24 31788965 ps
T1180 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4215986815 Mar 10 12:19:05 PM PDT 24 Mar 10 12:19:06 PM PDT 24 153964939 ps
T1181 /workspace/coverage/cover_reg_top/49.uart_intr_test.502215251 Mar 10 12:21:34 PM PDT 24 Mar 10 12:21:34 PM PDT 24 19848465 ps
T1182 /workspace/coverage/cover_reg_top/32.uart_intr_test.3433825423 Mar 10 12:27:30 PM PDT 24 Mar 10 12:27:30 PM PDT 24 23945487 ps
T1183 /workspace/coverage/cover_reg_top/41.uart_intr_test.3035859850 Mar 10 12:24:10 PM PDT 24 Mar 10 12:24:11 PM PDT 24 63163425 ps
T1184 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.172009728 Mar 10 12:21:08 PM PDT 24 Mar 10 12:21:10 PM PDT 24 119869234 ps
T1185 /workspace/coverage/cover_reg_top/18.uart_intr_test.1355230942 Mar 10 12:23:36 PM PDT 24 Mar 10 12:23:37 PM PDT 24 14470984 ps
T1186 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1408198895 Mar 10 12:33:10 PM PDT 24 Mar 10 12:33:11 PM PDT 24 30264769 ps
T1187 /workspace/coverage/cover_reg_top/22.uart_intr_test.3936488205 Mar 10 12:33:10 PM PDT 24 Mar 10 12:33:11 PM PDT 24 18653358 ps
T1188 /workspace/coverage/cover_reg_top/9.uart_intr_test.38472590 Mar 10 12:24:56 PM PDT 24 Mar 10 12:24:58 PM PDT 24 18878720 ps
T1189 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1398553809 Mar 10 12:33:55 PM PDT 24 Mar 10 12:33:57 PM PDT 24 29976066 ps
T1190 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.135913307 Mar 10 12:21:21 PM PDT 24 Mar 10 12:21:22 PM PDT 24 25382452 ps
T1191 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.358249238 Mar 10 12:24:23 PM PDT 24 Mar 10 12:24:24 PM PDT 24 32281828 ps
T1192 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1598963612 Mar 10 12:32:22 PM PDT 24 Mar 10 12:32:24 PM PDT 24 165315227 ps
T1193 /workspace/coverage/cover_reg_top/29.uart_intr_test.2894345854 Mar 10 12:21:29 PM PDT 24 Mar 10 12:21:30 PM PDT 24 52293704 ps
T1194 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2607883826 Mar 10 12:27:03 PM PDT 24 Mar 10 12:27:09 PM PDT 24 194276808 ps
T1195 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3341239117 Mar 10 12:23:58 PM PDT 24 Mar 10 12:23:59 PM PDT 24 35518310 ps
T1196 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1393062813 Mar 10 12:22:56 PM PDT 24 Mar 10 12:22:57 PM PDT 24 61434534 ps
T1197 /workspace/coverage/cover_reg_top/30.uart_intr_test.3584069319 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:07 PM PDT 24 14053939 ps
T1198 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3202078485 Mar 10 12:26:22 PM PDT 24 Mar 10 12:26:24 PM PDT 24 41982872 ps
T1199 /workspace/coverage/cover_reg_top/42.uart_intr_test.2224134634 Mar 10 12:21:38 PM PDT 24 Mar 10 12:21:39 PM PDT 24 49453903 ps
T1200 /workspace/coverage/cover_reg_top/31.uart_intr_test.1389126478 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:07 PM PDT 24 17903742 ps
T1201 /workspace/coverage/cover_reg_top/24.uart_intr_test.2574219541 Mar 10 12:23:58 PM PDT 24 Mar 10 12:23:59 PM PDT 24 40285457 ps
T66 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.349316877 Mar 10 12:24:19 PM PDT 24 Mar 10 12:24:22 PM PDT 24 58578500 ps
T1202 /workspace/coverage/cover_reg_top/0.uart_tl_errors.4047092037 Mar 10 12:24:38 PM PDT 24 Mar 10 12:24:39 PM PDT 24 28451663 ps
T1203 /workspace/coverage/cover_reg_top/7.uart_tl_errors.237699586 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:29 PM PDT 24 42602667 ps
T1204 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.47847198 Mar 10 12:20:11 PM PDT 24 Mar 10 12:20:13 PM PDT 24 22787660 ps
T1205 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3302030016 Mar 10 12:24:23 PM PDT 24 Mar 10 12:24:24 PM PDT 24 66755373 ps
T1206 /workspace/coverage/cover_reg_top/37.uart_intr_test.861003451 Mar 10 12:21:29 PM PDT 24 Mar 10 12:21:30 PM PDT 24 23102889 ps
T1207 /workspace/coverage/cover_reg_top/15.uart_intr_test.1500620302 Mar 10 12:21:29 PM PDT 24 Mar 10 12:21:30 PM PDT 24 139894190 ps
T1208 /workspace/coverage/cover_reg_top/17.uart_intr_test.400073528 Mar 10 12:21:15 PM PDT 24 Mar 10 12:21:16 PM PDT 24 17275687 ps
T1209 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3973549829 Mar 10 12:21:55 PM PDT 24 Mar 10 12:21:57 PM PDT 24 149441212 ps
T1210 /workspace/coverage/cover_reg_top/44.uart_intr_test.1345501223 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:12 PM PDT 24 16305426 ps
T67 /workspace/coverage/cover_reg_top/4.uart_csr_rw.526310478 Mar 10 12:33:47 PM PDT 24 Mar 10 12:33:48 PM PDT 24 13922678 ps
T1211 /workspace/coverage/cover_reg_top/4.uart_intr_test.2946314535 Mar 10 12:33:50 PM PDT 24 Mar 10 12:33:51 PM PDT 24 23238527 ps
T1212 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1916496669 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:11 PM PDT 24 40080527 ps
T1213 /workspace/coverage/cover_reg_top/19.uart_intr_test.3956036519 Mar 10 12:24:37 PM PDT 24 Mar 10 12:24:38 PM PDT 24 77655516 ps
T1214 /workspace/coverage/cover_reg_top/2.uart_intr_test.1442176037 Mar 10 12:21:03 PM PDT 24 Mar 10 12:21:04 PM PDT 24 32105915 ps
T1215 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3246524039 Mar 10 12:24:27 PM PDT 24 Mar 10 12:24:28 PM PDT 24 114123247 ps
T1216 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3790439180 Mar 10 12:33:45 PM PDT 24 Mar 10 12:33:46 PM PDT 24 12377729 ps
T1217 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3326951609 Mar 10 12:18:28 PM PDT 24 Mar 10 12:18:29 PM PDT 24 55216112 ps
T1218 /workspace/coverage/cover_reg_top/6.uart_intr_test.3213999827 Mar 10 12:21:03 PM PDT 24 Mar 10 12:21:04 PM PDT 24 28677209 ps
T1219 /workspace/coverage/cover_reg_top/40.uart_intr_test.3094205736 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:12 PM PDT 24 15659090 ps
T1220 /workspace/coverage/cover_reg_top/10.uart_intr_test.3755743388 Mar 10 12:20:54 PM PDT 24 Mar 10 12:20:57 PM PDT 24 11989853 ps
T1221 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1879093094 Mar 10 12:21:21 PM PDT 24 Mar 10 12:21:22 PM PDT 24 27601714 ps
T1222 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.799422850 Mar 10 12:33:54 PM PDT 24 Mar 10 12:33:55 PM PDT 24 177110528 ps
T68 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.271611555 Mar 10 12:32:05 PM PDT 24 Mar 10 12:32:07 PM PDT 24 52202987 ps
T1223 /workspace/coverage/cover_reg_top/47.uart_intr_test.3471802365 Mar 10 12:21:33 PM PDT 24 Mar 10 12:21:34 PM PDT 24 13470155 ps
T69 /workspace/coverage/cover_reg_top/3.uart_csr_rw.388382033 Mar 10 12:21:19 PM PDT 24 Mar 10 12:21:20 PM PDT 24 42378410 ps
T1224 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4233853325 Mar 10 12:24:23 PM PDT 24 Mar 10 12:24:25 PM PDT 24 113569339 ps
T1225 /workspace/coverage/cover_reg_top/39.uart_intr_test.1950184011 Mar 10 12:23:55 PM PDT 24 Mar 10 12:23:57 PM PDT 24 80050686 ps
T1226 /workspace/coverage/cover_reg_top/14.uart_intr_test.3210148650 Mar 10 12:21:21 PM PDT 24 Mar 10 12:21:21 PM PDT 24 19894821 ps
T1227 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.758563714 Mar 10 12:32:53 PM PDT 24 Mar 10 12:32:53 PM PDT 24 24328961 ps
T1228 /workspace/coverage/cover_reg_top/7.uart_intr_test.3870319846 Mar 10 12:24:23 PM PDT 24 Mar 10 12:24:24 PM PDT 24 16161256 ps
T1229 /workspace/coverage/cover_reg_top/8.uart_csr_rw.4230066214 Mar 10 12:33:53 PM PDT 24 Mar 10 12:33:54 PM PDT 24 25344120 ps
T1230 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1173765991 Mar 10 12:21:06 PM PDT 24 Mar 10 12:21:08 PM PDT 24 106844531 ps
T1231 /workspace/coverage/cover_reg_top/8.uart_tl_errors.887768983 Mar 10 12:29:34 PM PDT 24 Mar 10 12:29:35 PM PDT 24 118971538 ps
T84 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4989541 Mar 10 12:21:21 PM PDT 24 Mar 10 12:21:22 PM PDT 24 80382127 ps
T1232 /workspace/coverage/cover_reg_top/36.uart_intr_test.1070790395 Mar 10 12:27:33 PM PDT 24 Mar 10 12:27:34 PM PDT 24 157934286 ps
T1233 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3009636339 Mar 10 12:24:32 PM PDT 24 Mar 10 12:24:33 PM PDT 24 83639967 ps
T1234 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2100274335 Mar 10 12:33:43 PM PDT 24 Mar 10 12:33:45 PM PDT 24 1043798722 ps
T1235 /workspace/coverage/cover_reg_top/18.uart_tl_errors.365084155 Mar 10 12:21:24 PM PDT 24 Mar 10 12:21:26 PM PDT 24 508776346 ps
T1236 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2182730385 Mar 10 12:26:40 PM PDT 24 Mar 10 12:26:41 PM PDT 24 45596189 ps
T1237 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.903114672 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:10 PM PDT 24 47280137 ps
T1238 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1533756623 Mar 10 12:24:27 PM PDT 24 Mar 10 12:24:28 PM PDT 24 185533334 ps
T1239 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.534864662 Mar 10 12:22:57 PM PDT 24 Mar 10 12:22:57 PM PDT 24 24833027 ps
T1240 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1340411101 Mar 10 12:24:32 PM PDT 24 Mar 10 12:24:33 PM PDT 24 45894576 ps
T1241 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4228472224 Mar 10 12:24:27 PM PDT 24 Mar 10 12:24:28 PM PDT 24 99824875 ps
T1242 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2275578145 Mar 10 12:24:26 PM PDT 24 Mar 10 12:24:28 PM PDT 24 16674543 ps
T1243 /workspace/coverage/cover_reg_top/27.uart_intr_test.2353054161 Mar 10 12:24:27 PM PDT 24 Mar 10 12:24:28 PM PDT 24 21576146 ps
T1244 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2935609099 Mar 10 12:17:56 PM PDT 24 Mar 10 12:17:59 PM PDT 24 507664938 ps
T1245 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1556594739 Mar 10 12:21:17 PM PDT 24 Mar 10 12:21:17 PM PDT 24 51116573 ps
T1246 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3585969981 Mar 10 12:24:32 PM PDT 24 Mar 10 12:24:34 PM PDT 24 30007209 ps
T1247 /workspace/coverage/cover_reg_top/45.uart_intr_test.2387528347 Mar 10 12:21:46 PM PDT 24 Mar 10 12:21:48 PM PDT 24 42323717 ps
T1248 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3045265104 Mar 10 12:21:32 PM PDT 24 Mar 10 12:21:34 PM PDT 24 134079584 ps
T1249 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3874958399 Mar 10 12:20:40 PM PDT 24 Mar 10 12:20:41 PM PDT 24 18512559 ps
T1250 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2091352167 Mar 10 12:24:32 PM PDT 24 Mar 10 12:24:33 PM PDT 24 181136470 ps
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