Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.95	99.38	97.89	100.00		98.83	100.00	97.61

Total test records in report: 1258

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.329428723			Mar 10 12:21:06 PM PDT 24	Mar 10 12:21:07 PM PDT 24	32053636 ps
T1252	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2639515710			Mar 10 12:20:48 PM PDT 24	Mar 10 12:20:50 PM PDT 24	27425994 ps
T1253	/workspace/coverage/cover_reg_top/38.uart_intr_test.505491469			Mar 10 12:27:20 PM PDT 24	Mar 10 12:27:22 PM PDT 24	33394531 ps
T1254	/workspace/coverage/cover_reg_top/19.uart_csr_rw.2515640216			Mar 10 12:24:27 PM PDT 24	Mar 10 12:24:28 PM PDT 24	16478009 ps
T1255	/workspace/coverage/cover_reg_top/5.uart_csr_rw.4147789627			Mar 10 12:24:24 PM PDT 24	Mar 10 12:24:25 PM PDT 24	38690387 ps
T1256	/workspace/coverage/cover_reg_top/28.uart_intr_test.2762086600			Mar 10 12:24:11 PM PDT 24	Mar 10 12:24:12 PM PDT 24	13782245 ps
T1257	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.934860082			Mar 10 12:26:41 PM PDT 24	Mar 10 12:26:42 PM PDT 24	41197380 ps
T1258	/workspace/coverage/cover_reg_top/16.uart_tl_errors.1983564278			Mar 10 12:21:05 PM PDT 24	Mar 10 12:21:06 PM PDT 24	213428718 ps

Test location	/workspace/coverage/default/10.uart_noise_filter.783300949
Short name	T3
Test name
Test status
Simulation time	87942593766 ps
CPU time	157.27 seconds
Started	Mar 10 12:49:54 PM PDT 24
Finished	Mar 10 12:52:32 PM PDT 24
Peak memory	200220 kb
Host	smart-220dc444-1cac-40ac-a2f2-a9844b65c528
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783300949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.783300949
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_stress_all_with_rand_reset.4011888942
Short name	T11
Test name
Test status
Simulation time	353607519124 ps
CPU time	482.54 seconds
Started	Mar 10 12:52:01 PM PDT 24
Finished	Mar 10 01:00:04 PM PDT 24
Peak memory	216848 kb
Host	smart-5bd60b07-97f9-4cb3-bce8-21bc9046c76a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011888942 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4011888942
Directory	/workspace/23.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.uart_long_xfer_wo_dly.4001956560
Short name	T5
Test name
Test status
Simulation time	234479736535 ps
CPU time	1456.19 seconds
Started	Mar 10 12:51:16 PM PDT 24
Finished	Mar 10 01:15:33 PM PDT 24
Peak memory	200084 kb
Host	smart-fe7d7f76-9051-42c9-a4fb-c2d8813878cd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4001956560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4001956560
Directory	/workspace/18.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_stress_all.2373765307
Short name	T22
Test name
Test status
Simulation time	444730129364 ps
CPU time	269.93 seconds
Started	Mar 10 12:55:22 PM PDT 24
Finished	Mar 10 12:59:52 PM PDT 24
Peak memory	200152 kb
Host	smart-f00662d8-6559-4002-9224-b927858d2a9b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373765307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2373765307
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/13.uart_stress_all.2362523693
Short name	T13
Test name
Test status
Simulation time	585250125901 ps
CPU time	2322.54 seconds
Started	Mar 10 12:50:28 PM PDT 24
Finished	Mar 10 01:29:11 PM PDT 24
Peak memory	200160 kb
Host	smart-4529bc7a-f65c-4af7-a702-5d1e14b4cca6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362523693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2362523693
Directory	/workspace/13.uart_stress_all/latest

Test location	/workspace/coverage/default/19.uart_stress_all.1655165241
Short name	T119
Test name
Test status
Simulation time	275836912473 ps
CPU time	446.91 seconds
Started	Mar 10 12:51:24 PM PDT 24
Finished	Mar 10 12:58:51 PM PDT 24
Peak memory	200240 kb
Host	smart-9cfa7547-a500-4ebc-ad4b-5fd7b411318d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655165241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1655165241
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_stress_all.360824387
Short name	T28
Test name
Test status
Simulation time	36901132052 ps
CPU time	1659.49 seconds
Started	Mar 10 12:50:34 PM PDT 24
Finished	Mar 10 01:18:14 PM PDT 24
Peak memory	200084 kb
Host	smart-1eef84e9-d99d-437e-bfda-ae433d164d93
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360824387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.360824387
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_stress_all_with_rand_reset.2877294848
Short name	T34
Test name
Test status
Simulation time	117454090127 ps
CPU time	574.45 seconds
Started	Mar 10 12:55:43 PM PDT 24
Finished	Mar 10 01:05:20 PM PDT 24
Peak memory	216620 kb
Host	smart-d0034155-fd80-4271-bb5f-37f0a2218512
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877294848 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2877294848
Directory	/workspace/46.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.3274095547
Short name	T14
Test name
Test status
Simulation time	86355938897 ps
CPU time	84.51 seconds
Started	Mar 10 12:49:02 PM PDT 24
Finished	Mar 10 12:50:27 PM PDT 24
Peak memory	200152 kb
Host	smart-c4866879-4cef-464d-84e6-0646895bbcc4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274095547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3274095547
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_stress_all.3698072997
Short name	T343
Test name
Test status
Simulation time	437609511889 ps
CPU time	314.21 seconds
Started	Mar 10 12:49:48 PM PDT 24
Finished	Mar 10 12:55:02 PM PDT 24
Peak memory	200132 kb
Host	smart-ac36a583-3b3a-4ddc-a99b-efa984578385
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698072997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3698072997
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/38.uart_stress_all.102694675
Short name	T314
Test name
Test status
Simulation time	244458696843 ps
CPU time	178.64 seconds
Started	Mar 10 12:54:26 PM PDT 24
Finished	Mar 10 12:57:25 PM PDT 24
Peak memory	200092 kb
Host	smart-f1731934-d0cf-4fb5-825a-a1e985820abc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102694675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.102694675
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_alert_test.3426666708
Short name	T7
Test name
Test status
Simulation time	42084364 ps
CPU time	0.56 seconds
Started	Mar 10 12:48:14 PM PDT 24
Finished	Mar 10 12:48:15 PM PDT 24
Peak memory	195468 kb
Host	smart-dd52c2d5-81f9-45ba-b2e8-97061aa36be5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426666708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3426666708
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.1863190301
Short name	T94
Test name
Test status
Simulation time	73683997 ps
CPU time	0.83 seconds
Started	Mar 10 12:48:08 PM PDT 24
Finished	Mar 10 12:48:10 PM PDT 24
Peak memory	217364 kb
Host	smart-b6a2cd38-2387-4968-8b19-03182cbcd985
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863190301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1863190301
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.4001278666
Short name	T63
Test name
Test status
Simulation time	14431052 ps
CPU time	0.61 seconds
Started	Mar 10 12:22:26 PM PDT 24
Finished	Mar 10 12:22:27 PM PDT 24
Peak memory	195724 kb
Host	smart-a3ff1b39-c114-4971-801f-85c454d5e708
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001278666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4001278666
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/default/31.uart_stress_all_with_rand_reset.1663497903
Short name	T38
Test name
Test status
Simulation time	1380575612501 ps
CPU time	644.16 seconds
Started	Mar 10 12:53:16 PM PDT 24
Finished	Mar 10 01:04:00 PM PDT 24
Peak memory	224896 kb
Host	smart-dea5e3b7-7dad-48ce-aa2a-5c528c7c5b72
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663497903 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1663497903
Directory	/workspace/31.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.uart_stress_all.3966934706
Short name	T106
Test name
Test status
Simulation time	37939741812 ps
CPU time	281.22 seconds
Started	Mar 10 12:52:53 PM PDT 24
Finished	Mar 10 12:57:34 PM PDT 24
Peak memory	200176 kb
Host	smart-ce305c8a-a34f-4571-be4a-f1434894e5e9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966934706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3966934706
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.1742358676
Short name	T310
Test name
Test status
Simulation time	38877609831 ps
CPU time	64.63 seconds
Started	Mar 10 12:57:57 PM PDT 24
Finished	Mar 10 12:59:02 PM PDT 24
Peak memory	200068 kb
Host	smart-52450141-f159-407f-bd08-6f1bef1d0483
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742358676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1742358676
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_stress_all.240603040
Short name	T15
Test name
Test status
Simulation time	447754013758 ps
CPU time	1202.21 seconds
Started	Mar 10 12:51:15 PM PDT 24
Finished	Mar 10 01:11:18 PM PDT 24
Peak memory	200160 kb
Host	smart-e5f82e54-c568-47d8-8522-b4699eec1786
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240603040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.240603040
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3011644232
Short name	T83
Test name
Test status
Simulation time	1177475563 ps
CPU time	1.28 seconds
Started	Mar 10 12:27:37 PM PDT 24
Finished	Mar 10 12:27:39 PM PDT 24
Peak memory	199256 kb
Host	smart-3f94c511-0a3d-4dbf-90c1-e72c407a217a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011644232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3011644232
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.2777684641
Short name	T121
Test name
Test status
Simulation time	22544046221 ps
CPU time	26.34 seconds
Started	Mar 10 12:57:51 PM PDT 24
Finished	Mar 10 12:58:18 PM PDT 24
Peak memory	200056 kb
Host	smart-62b04951-92fa-4b99-9542-f9deaba7d943
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777684641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2777684641
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_stress_all.859344062
Short name	T113
Test name
Test status
Simulation time	228350817897 ps
CPU time	849.94 seconds
Started	Mar 10 12:48:48 PM PDT 24
Finished	Mar 10 01:02:58 PM PDT 24
Peak memory	200060 kb
Host	smart-e5407b42-2155-4460-81ff-0d4ad935da01
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859344062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.859344062
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.3733253325
Short name	T169
Test name
Test status
Simulation time	56586853859 ps
CPU time	99.3 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 12:58:11 PM PDT 24
Peak memory	200136 kb
Host	smart-ead94810-5677-481f-acfe-225eb70316a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733253325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3733253325
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.2330111171
Short name	T77
Test name
Test status
Simulation time	231119656255 ps
CPU time	359.97 seconds
Started	Mar 10 12:57:23 PM PDT 24
Finished	Mar 10 01:03:23 PM PDT 24
Peak memory	200096 kb
Host	smart-7dc6c5a1-9a47-45b4-8634-45fde2b43341
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330111171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2330111171
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_stress_all_with_rand_reset.2869635524
Short name	T25
Test name
Test status
Simulation time	78095615489 ps
CPU time	226.11 seconds
Started	Mar 10 12:49:30 PM PDT 24
Finished	Mar 10 12:53:17 PM PDT 24
Peak memory	216820 kb
Host	smart-075d2b7b-40ce-41a7-be6f-8f9acbe2b05b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869635524 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2869635524
Directory	/workspace/7.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.271611555
Short name	T68
Test name
Test status
Simulation time	52202987 ps
CPU time	0.82 seconds
Started	Mar 10 12:32:05 PM PDT 24
Finished	Mar 10 12:32:07 PM PDT 24
Peak memory	195584 kb
Host	smart-f8b34897-ed1d-4032-a252-caa96e65e764
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271611555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.271611555
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/default/49.uart_stress_all.3747667121
Short name	T298
Test name
Test status
Simulation time	73756814620 ps
CPU time	365.47 seconds
Started	Mar 10 12:56:09 PM PDT 24
Finished	Mar 10 01:02:15 PM PDT 24
Peak memory	200076 kb
Host	smart-73f3922e-9e91-4174-8844-7615626c513c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747667121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3747667121
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_stress_all.394622016
Short name	T168
Test name
Test status
Simulation time	175847111273 ps
CPU time	417.51 seconds
Started	Mar 10 12:48:14 PM PDT 24
Finished	Mar 10 12:55:12 PM PDT 24
Peak memory	199976 kb
Host	smart-811d6a09-9581-436a-a6af-6281ac9f8297
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394622016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.394622016
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.2101874654
Short name	T146
Test name
Test status
Simulation time	131029927465 ps
CPU time	31.83 seconds
Started	Mar 10 12:59:06 PM PDT 24
Finished	Mar 10 12:59:38 PM PDT 24
Peak memory	199680 kb
Host	smart-affcb7ba-5aa6-4d31-8ed7-ac81c8269bdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101874654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2101874654
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_stress_all_with_rand_reset.1833557862
Short name	T278
Test name
Test status
Simulation time	369820767034 ps
CPU time	979.83 seconds
Started	Mar 10 12:56:23 PM PDT 24
Finished	Mar 10 01:12:43 PM PDT 24
Peak memory	225028 kb
Host	smart-0457657a-1f88-4963-8277-59aad18d5dad
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833557862 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1833557862
Directory	/workspace/59.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.3657070133
Short name	T151
Test name
Test status
Simulation time	188234847461 ps
CPU time	24.61 seconds
Started	Mar 10 12:53:44 PM PDT 24
Finished	Mar 10 12:54:09 PM PDT 24
Peak memory	200084 kb
Host	smart-c5ec5d00-edd0-4906-9f9f-32aa2c797e72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657070133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3657070133
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_stress_all.1590077131
Short name	T158
Test name
Test status
Simulation time	364900777540 ps
CPU time	1849.46 seconds
Started	Mar 10 12:53:37 PM PDT 24
Finished	Mar 10 01:24:27 PM PDT 24
Peak memory	209452 kb
Host	smart-3c2e4cbd-c347-4cb5-9aa8-885a6fd28206
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590077131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1590077131
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/66.uart_stress_all_with_rand_reset.953199588
Short name	T36
Test name
Test status
Simulation time	405357061430 ps
CPU time	1163.65 seconds
Started	Mar 10 01:00:30 PM PDT 24
Finished	Mar 10 01:19:54 PM PDT 24
Peak memory	225364 kb
Host	smart-ebb12c1a-21b9-4145-8e11-14c3fb925a51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953199588 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.953199588
Directory	/workspace/66.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3566399855
Short name	T81
Test name
Test status
Simulation time	105000161 ps
CPU time	1.26 seconds
Started	Mar 10 12:22:52 PM PDT 24
Finished	Mar 10 12:22:54 PM PDT 24
Peak memory	198128 kb
Host	smart-70207651-f9d3-4d09-b2ec-8745765a29e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566399855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3566399855
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.1488989697
Short name	T152
Test name
Test status
Simulation time	8636671103 ps
CPU time	15.76 seconds
Started	Mar 10 12:58:56 PM PDT 24
Finished	Mar 10 12:59:11 PM PDT 24
Peak memory	199964 kb
Host	smart-6c4e4082-c670-4942-bbdb-86919cccbe7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488989697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1488989697
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.1684770296
Short name	T133
Test name
Test status
Simulation time	68090557332 ps
CPU time	72.84 seconds
Started	Mar 10 12:59:10 PM PDT 24
Finished	Mar 10 01:00:23 PM PDT 24
Peak memory	200152 kb
Host	smart-1d0132d5-b03f-4c0d-95f4-bea3ef1c8031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684770296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1684770296
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_stress_all.189735830
Short name	T321
Test name
Test status
Simulation time	542045483594 ps
CPU time	292.2 seconds
Started	Mar 10 12:54:06 PM PDT 24
Finished	Mar 10 12:58:59 PM PDT 24
Peak memory	200084 kb
Host	smart-a6cb4332-e041-4041-bdaf-c245fc83f4c0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189735830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.189735830
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.4029355003
Short name	T6
Test name
Test status
Simulation time	57560797301 ps
CPU time	25.03 seconds
Started	Mar 10 12:49:18 PM PDT 24
Finished	Mar 10 12:49:43 PM PDT 24
Peak memory	200208 kb
Host	smart-af02aca2-17a6-4cf6-83a4-6420cca29324
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029355003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4029355003
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.2524883750
Short name	T328
Test name
Test status
Simulation time	145803611670 ps
CPU time	27.75 seconds
Started	Mar 10 12:56:42 PM PDT 24
Finished	Mar 10 12:57:10 PM PDT 24
Peak memory	200096 kb
Host	smart-ae1fe2ae-7a00-4d71-afd5-3508b2b6b5da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524883750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2524883750
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.2992792742
Short name	T241
Test name
Test status
Simulation time	139243177875 ps
CPU time	58.12 seconds
Started	Mar 10 12:57:29 PM PDT 24
Finished	Mar 10 12:58:27 PM PDT 24
Peak memory	200164 kb
Host	smart-d3ec5f22-1987-4aca-80fa-f1536e920ad2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992792742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2992792742
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.858565799
Short name	T740
Test name
Test status
Simulation time	24618636003 ps
CPU time	60.74 seconds
Started	Mar 10 12:51:41 PM PDT 24
Finished	Mar 10 12:52:42 PM PDT 24
Peak memory	200160 kb
Host	smart-199a78e8-2a57-463d-8884-3b9b4fdac3cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858565799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.858565799
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.998656075
Short name	T118
Test name
Test status
Simulation time	79678404523 ps
CPU time	67.22 seconds
Started	Mar 10 12:59:11 PM PDT 24
Finished	Mar 10 01:00:18 PM PDT 24
Peak memory	200208 kb
Host	smart-28934b6f-d905-4f7d-848c-9e0edcdc2ea4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998656075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.998656075
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.56950973
Short name	T304
Test name
Test status
Simulation time	250202242742 ps
CPU time	87.03 seconds
Started	Mar 10 12:59:21 PM PDT 24
Finished	Mar 10 01:00:48 PM PDT 24
Peak memory	199748 kb
Host	smart-e5b46076-9d91-478a-8b81-b239ceab0119
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56950973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.56950973
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.1607772345
Short name	T233
Test name
Test status
Simulation time	330581445774 ps
CPU time	28.94 seconds
Started	Mar 10 01:00:30 PM PDT 24
Finished	Mar 10 01:00:59 PM PDT 24
Peak memory	199596 kb
Host	smart-e1f719d9-87db-4669-b7b9-86c98a2f1c05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607772345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1607772345
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.167424719
Short name	T200
Test name
Test status
Simulation time	25948855429 ps
CPU time	44.06 seconds
Started	Mar 10 12:57:34 PM PDT 24
Finished	Mar 10 12:58:18 PM PDT 24
Peak memory	200128 kb
Host	smart-a96efb8e-9301-4a29-80c7-55c52a28c594
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167424719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.167424719
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.2264759325
Short name	T243
Test name
Test status
Simulation time	104232126961 ps
CPU time	18 seconds
Started	Mar 10 12:58:15 PM PDT 24
Finished	Mar 10 12:58:33 PM PDT 24
Peak memory	200116 kb
Host	smart-ec94660f-5553-428a-8adf-f315e3611d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264759325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2264759325
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.4235510652
Short name	T1053
Test name
Test status
Simulation time	57437033806 ps
CPU time	87.86 seconds
Started	Mar 10 12:58:29 PM PDT 24
Finished	Mar 10 12:59:57 PM PDT 24
Peak memory	200068 kb
Host	smart-06c84e95-f70e-41d2-bb0c-be0fb85a3c01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235510652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4235510652
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.872477182
Short name	T246
Test name
Test status
Simulation time	44939858309 ps
CPU time	39.37 seconds
Started	Mar 10 12:59:16 PM PDT 24
Finished	Mar 10 12:59:56 PM PDT 24
Peak memory	200056 kb
Host	smart-3fa87ffa-0d42-40cf-a375-f88d393188de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872477182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.872477182
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.2224912349
Short name	T149
Test name
Test status
Simulation time	110572660813 ps
CPU time	137.3 seconds
Started	Mar 10 12:59:38 PM PDT 24
Finished	Mar 10 01:01:55 PM PDT 24
Peak memory	200060 kb
Host	smart-22df5336-54e4-4452-9824-ba8c60fb60ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224912349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2224912349
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.1661406458
Short name	T221
Test name
Test status
Simulation time	42601456192 ps
CPU time	77.73 seconds
Started	Mar 10 12:54:56 PM PDT 24
Finished	Mar 10 12:56:13 PM PDT 24
Peak memory	200008 kb
Host	smart-e818ea51-18a1-4729-9e83-0f5f2baeb997
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661406458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1661406458
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/50.uart_stress_all_with_rand_reset.717647923
Short name	T53
Test name
Test status
Simulation time	356866457669 ps
CPU time	834.11 seconds
Started	Mar 10 12:56:12 PM PDT 24
Finished	Mar 10 01:10:06 PM PDT 24
Peak memory	231044 kb
Host	smart-9cac78c4-3904-4ebb-91da-7479eb25a2be
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717647923 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.717647923
Directory	/workspace/50.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.2636888585
Short name	T382
Test name
Test status
Simulation time	115815559076 ps
CPU time	94.48 seconds
Started	Mar 10 12:48:08 PM PDT 24
Finished	Mar 10 12:49:43 PM PDT 24
Peak memory	199940 kb
Host	smart-ab0ca4c5-bf14-4109-b8e8-863d9b7e32fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636888585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2636888585
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.2439147514
Short name	T232
Test name
Test status
Simulation time	60075635057 ps
CPU time	97.97 seconds
Started	Mar 10 12:57:29 PM PDT 24
Finished	Mar 10 12:59:07 PM PDT 24
Peak memory	200112 kb
Host	smart-a5722b95-677c-4773-ba4f-951bd0b6f616
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439147514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2439147514
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.1658486334
Short name	T370
Test name
Test status
Simulation time	48539340310 ps
CPU time	22.13 seconds
Started	Mar 10 12:57:31 PM PDT 24
Finished	Mar 10 12:57:54 PM PDT 24
Peak memory	199924 kb
Host	smart-58eee3fe-06a1-4cff-bb91-8342ebb72fd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658486334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1658486334
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/172.uart_fifo_reset.2802971550
Short name	T116
Test name
Test status
Simulation time	123582079239 ps
CPU time	33.36 seconds
Started	Mar 10 12:58:19 PM PDT 24
Finished	Mar 10 12:58:53 PM PDT 24
Peak memory	199492 kb
Host	smart-2b97dae8-103b-4ab8-991a-f58e517c6b3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802971550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2802971550
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.3374859149
Short name	T302
Test name
Test status
Simulation time	46113195598 ps
CPU time	25.55 seconds
Started	Mar 10 12:58:36 PM PDT 24
Finished	Mar 10 12:59:02 PM PDT 24
Peak memory	200088 kb
Host	smart-3161e15c-b2e7-43cc-bbc8-9d1c67856c42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374859149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3374859149
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.3115279553
Short name	T334
Test name
Test status
Simulation time	184772096331 ps
CPU time	77.82 seconds
Started	Mar 10 12:58:40 PM PDT 24
Finished	Mar 10 12:59:58 PM PDT 24
Peak memory	200156 kb
Host	smart-f2d2dba9-c89d-44b0-9944-6bc15fe6a3f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3115279553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3115279553
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.3031103453
Short name	T229
Test name
Test status
Simulation time	206151018162 ps
CPU time	133.97 seconds
Started	Mar 10 12:58:57 PM PDT 24
Finished	Mar 10 01:01:11 PM PDT 24
Peak memory	200096 kb
Host	smart-58d0e7ca-c1a8-4e1d-92d2-5cbcbc6d1f4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031103453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3031103453
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.853875379
Short name	T291
Test name
Test status
Simulation time	31456179470 ps
CPU time	54.77 seconds
Started	Mar 10 12:59:29 PM PDT 24
Finished	Mar 10 01:00:24 PM PDT 24
Peak memory	200120 kb
Host	smart-11442b40-89dd-4f81-97d0-6db140dcffe8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853875379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.853875379
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.2861293197
Short name	T206
Test name
Test status
Simulation time	128699559551 ps
CPU time	65.43 seconds
Started	Mar 10 12:59:38 PM PDT 24
Finished	Mar 10 01:00:43 PM PDT 24
Peak memory	200076 kb
Host	smart-e38ddb23-8742-49da-8e00-ced1cdb325a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861293197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2861293197
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_stress_all.1902796451
Short name	T78
Test name
Test status
Simulation time	75947243180 ps
CPU time	297 seconds
Started	Mar 10 12:49:29 PM PDT 24
Finished	Mar 10 12:54:27 PM PDT 24
Peak memory	200068 kb
Host	smart-ebdda58e-ea75-414b-a165-8d8db0c8767c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902796451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1902796451
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.3326009514
Short name	T115
Test name
Test status
Simulation time	92371900617 ps
CPU time	81.93 seconds
Started	Mar 10 12:47:50 PM PDT 24
Finished	Mar 10 12:49:12 PM PDT 24
Peak memory	199860 kb
Host	smart-3168d4dd-d933-49c9-b7e3-8d64f49f0c8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326009514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3326009514
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_stress_all_with_rand_reset.3457504582
Short name	T353
Test name
Test status
Simulation time	10692974090 ps
CPU time	101.17 seconds
Started	Mar 10 12:48:14 PM PDT 24
Finished	Mar 10 12:49:55 PM PDT 24
Peak memory	208556 kb
Host	smart-19f8568d-6b28-42f2-b259-ae53ae6cc490
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457504582 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3457504582
Directory	/workspace/1.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.154555023
Short name	T203
Test name
Test status
Simulation time	12338812058 ps
CPU time	19.6 seconds
Started	Mar 10 12:57:28 PM PDT 24
Finished	Mar 10 12:57:47 PM PDT 24
Peak memory	200164 kb
Host	smart-4b99202e-1b9b-44f8-bcf6-d1b6806548af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154555023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.154555023
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.2665998237
Short name	T223
Test name
Test status
Simulation time	23703589539 ps
CPU time	11.46 seconds
Started	Mar 10 12:57:27 PM PDT 24
Finished	Mar 10 12:57:38 PM PDT 24
Peak memory	200128 kb
Host	smart-7b98c9f6-12cb-44db-acfa-75400eb743ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665998237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2665998237
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.3888548626
Short name	T297
Test name
Test status
Simulation time	18074681040 ps
CPU time	27.44 seconds
Started	Mar 10 12:57:32 PM PDT 24
Finished	Mar 10 12:57:59 PM PDT 24
Peak memory	200160 kb
Host	smart-0446f60e-8f79-4249-9afb-a9e29643748b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888548626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3888548626
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.574357079
Short name	T368
Test name
Test status
Simulation time	54697965105 ps
CPU time	90.75 seconds
Started	Mar 10 12:57:57 PM PDT 24
Finished	Mar 10 12:59:28 PM PDT 24
Peak memory	200128 kb
Host	smart-30d9830d-90b2-4be4-b552-7b9b59dd8909
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574357079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.574357079
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.1815121684
Short name	T217
Test name
Test status
Simulation time	76518611571 ps
CPU time	28.04 seconds
Started	Mar 10 12:58:03 PM PDT 24
Finished	Mar 10 12:58:31 PM PDT 24
Peak memory	200100 kb
Host	smart-e14e98c6-947c-4e6f-bc75-1de98f972672
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815121684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1815121684
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.4104219135
Short name	T352
Test name
Test status
Simulation time	100440071465 ps
CPU time	24.84 seconds
Started	Mar 10 12:50:38 PM PDT 24
Finished	Mar 10 12:51:03 PM PDT 24
Peak memory	200004 kb
Host	smart-87c4fc03-c03a-4a1f-92be-968ec11b2db6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104219135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4104219135
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.2652571693
Short name	T188
Test name
Test status
Simulation time	149135130484 ps
CPU time	64.25 seconds
Started	Mar 10 12:58:11 PM PDT 24
Finished	Mar 10 12:59:15 PM PDT 24
Peak memory	200080 kb
Host	smart-acfedb61-3055-4da1-80f8-0a852259722b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652571693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2652571693
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_fifo_reset.2725346396
Short name	T282
Test name
Test status
Simulation time	38442261445 ps
CPU time	16.06 seconds
Started	Mar 10 12:50:59 PM PDT 24
Finished	Mar 10 12:51:16 PM PDT 24
Peak memory	199072 kb
Host	smart-4203ae6a-c87a-461b-b91a-48a8711c56fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725346396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2725346396
Directory	/workspace/17.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.1638246208
Short name	T142
Test name
Test status
Simulation time	11735560453 ps
CPU time	58.21 seconds
Started	Mar 10 12:58:26 PM PDT 24
Finished	Mar 10 12:59:24 PM PDT 24
Peak memory	200100 kb
Host	smart-5a2d6ca7-eb0d-41e9-8cc9-e6d5c545c027
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638246208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1638246208
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.3784699453
Short name	T42
Test name
Test status
Simulation time	58663467331 ps
CPU time	19.11 seconds
Started	Mar 10 12:58:40 PM PDT 24
Finished	Mar 10 12:59:00 PM PDT 24
Peak memory	200104 kb
Host	smart-d41446fb-9b97-4992-b5ea-520ed587dcdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784699453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3784699453
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.625700100
Short name	T193
Test name
Test status
Simulation time	24032467031 ps
CPU time	42.16 seconds
Started	Mar 10 12:58:54 PM PDT 24
Finished	Mar 10 12:59:36 PM PDT 24
Peak memory	200124 kb
Host	smart-8d565fbe-5d1d-40a7-95e1-f59c4d1ad536
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625700100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.625700100
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_stress_all.3604946721
Short name	T1072
Test name
Test status
Simulation time	471115304781 ps
CPU time	395.58 seconds
Started	Mar 10 12:52:01 PM PDT 24
Finished	Mar 10 12:58:37 PM PDT 24
Peak memory	200148 kb
Host	smart-6887ab03-2bc2-4458-b874-9eb402023c9b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604946721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3604946721
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.4005501164
Short name	T371
Test name
Test status
Simulation time	139550032723 ps
CPU time	19.15 seconds
Started	Mar 10 12:59:10 PM PDT 24
Finished	Mar 10 12:59:29 PM PDT 24
Peak memory	200128 kb
Host	smart-e487c878-1fec-4819-b446-79ab4e16e655
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005501164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4005501164
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/274.uart_fifo_reset.609516034
Short name	T202
Test name
Test status
Simulation time	24762639089 ps
CPU time	22.23 seconds
Started	Mar 10 12:59:39 PM PDT 24
Finished	Mar 10 01:00:01 PM PDT 24
Peak memory	199112 kb
Host	smart-1b171d45-20b9-4398-b9b3-dc1751f07e5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609516034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.609516034
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_stress_all_with_rand_reset.3300555065
Short name	T339
Test name
Test status
Simulation time	58906212699 ps
CPU time	482.52 seconds
Started	Mar 10 12:54:28 PM PDT 24
Finished	Mar 10 01:02:31 PM PDT 24
Peak memory	216600 kb
Host	smart-3bb2c5d5-2076-4109-aa28-3272c37651f3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300555065 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3300555065
Directory	/workspace/39.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.2072412940
Short name	T342
Test name
Test status
Simulation time	203553483249 ps
CPU time	37.18 seconds
Started	Mar 10 12:55:28 PM PDT 24
Finished	Mar 10 12:56:06 PM PDT 24
Peak memory	200028 kb
Host	smart-c162a9ff-5268-41a5-81eb-c6be934a7151
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072412940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2072412940
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_stress_all_with_rand_reset.450016762
Short name	T341
Test name
Test status
Simulation time	73319727470 ps
CPU time	226.41 seconds
Started	Mar 10 12:56:27 PM PDT 24
Finished	Mar 10 01:00:13 PM PDT 24
Peak memory	215748 kb
Host	smart-dbedb090-d908-434d-bf41-3fb430afba86
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450016762 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.450016762
Directory	/workspace/64.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.3632403746
Short name	T166
Test name
Test status
Simulation time	88772684985 ps
CPU time	133.57 seconds
Started	Mar 10 12:56:56 PM PDT 24
Finished	Mar 10 12:59:10 PM PDT 24
Peak memory	199288 kb
Host	smart-d638263f-2879-473b-b56e-6f84a37d8ed8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632403746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3632403746
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3889728707
Short name	T375
Test name
Test status
Simulation time	159091885 ps
CPU time	1.25 seconds
Started	Mar 10 12:24:01 PM PDT 24
Finished	Mar 10 12:24:02 PM PDT 24
Peak memory	199452 kb
Host	smart-041a8fb5-ed83-4bdf-8f8a-69da1d3b77bb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889728707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3889728707
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_stress_all.1862705969
Short name	T355
Test name
Test status
Simulation time	268654624235 ps
CPU time	359.24 seconds
Started	Mar 10 12:48:03 PM PDT 24
Finished	Mar 10 12:54:04 PM PDT 24
Peak memory	200108 kb
Host	smart-c3409d12-1d90-4d02-892f-4aa8a44c62da
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862705969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1862705969
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.216941005
Short name	T252
Test name
Test status
Simulation time	121680602261 ps
CPU time	41.72 seconds
Started	Mar 10 12:49:53 PM PDT 24
Finished	Mar 10 12:50:35 PM PDT 24
Peak memory	200172 kb
Host	smart-6aef1cef-a1ed-4236-8d21-b9a482ea3063
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216941005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.216941005
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.544686464
Short name	T279
Test name
Test status
Simulation time	152363066863 ps
CPU time	157.73 seconds
Started	Mar 10 12:49:50 PM PDT 24
Finished	Mar 10 12:52:27 PM PDT 24
Peak memory	199252 kb
Host	smart-b2b54cd6-cb5d-4ace-8c63-84f68778e4d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=544686464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.544686464
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.273878554
Short name	T120
Test name
Test status
Simulation time	16080119168 ps
CPU time	23.28 seconds
Started	Mar 10 12:57:23 PM PDT 24
Finished	Mar 10 12:57:46 PM PDT 24
Peak memory	199872 kb
Host	smart-b9e60112-4c66-4460-876d-ed88c139652d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273878554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.273878554
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.2397285944
Short name	T344
Test name
Test status
Simulation time	103632182811 ps
CPU time	28.34 seconds
Started	Mar 10 12:57:26 PM PDT 24
Finished	Mar 10 12:57:54 PM PDT 24
Peak memory	200084 kb
Host	smart-0e427929-e05b-48bc-b097-418c68bb420d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397285944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2397285944
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.1714459591
Short name	T161
Test name
Test status
Simulation time	64794313116 ps
CPU time	43.84 seconds
Started	Mar 10 12:57:31 PM PDT 24
Finished	Mar 10 12:58:15 PM PDT 24
Peak memory	200108 kb
Host	smart-1ec5c7d0-44cc-4a23-b0e3-f39236cff347
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714459591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1714459591
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.2721793846
Short name	T269
Test name
Test status
Simulation time	95598663229 ps
CPU time	27.84 seconds
Started	Mar 10 12:57:56 PM PDT 24
Finished	Mar 10 12:58:24 PM PDT 24
Peak memory	200164 kb
Host	smart-1acc5f84-1059-435f-810e-807a0845c662
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721793846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2721793846
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.3912532589
Short name	T985
Test name
Test status
Simulation time	18756632828 ps
CPU time	28.54 seconds
Started	Mar 10 12:58:03 PM PDT 24
Finished	Mar 10 12:58:31 PM PDT 24
Peak memory	200080 kb
Host	smart-4fc708b9-9ca4-4ace-9ed7-304db6ee8852
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912532589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3912532589
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.2299838956
Short name	T260
Test name
Test status
Simulation time	34168184483 ps
CPU time	51.32 seconds
Started	Mar 10 12:50:48 PM PDT 24
Finished	Mar 10 12:51:39 PM PDT 24
Peak memory	200148 kb
Host	smart-404a993a-ecf4-4d41-90ba-da1a00d7de0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299838956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2299838956
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.1080888710
Short name	T358
Test name
Test status
Simulation time	48255369038 ps
CPU time	19.76 seconds
Started	Mar 10 12:58:19 PM PDT 24
Finished	Mar 10 12:58:40 PM PDT 24
Peak memory	200176 kb
Host	smart-fc51e928-3379-4b2d-973d-983955fa2939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080888710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1080888710
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.1221664581
Short name	T114
Test name
Test status
Simulation time	83231154644 ps
CPU time	81.95 seconds
Started	Mar 10 12:58:23 PM PDT 24
Finished	Mar 10 12:59:45 PM PDT 24
Peak memory	200052 kb
Host	smart-35490bda-c406-42fc-b539-056942230b6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221664581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1221664581
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_stress_all_with_rand_reset.4228159395
Short name	T58
Test name
Test status
Simulation time	869650131480 ps
CPU time	550.5 seconds
Started	Mar 10 12:51:24 PM PDT 24
Finished	Mar 10 01:00:35 PM PDT 24
Peak memory	216668 kb
Host	smart-3ecf3765-dff0-4643-b20a-cd71d7f9f3d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228159395 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4228159395
Directory	/workspace/19.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.1438503159
Short name	T277
Test name
Test status
Simulation time	134776271806 ps
CPU time	212.33 seconds
Started	Mar 10 12:58:34 PM PDT 24
Finished	Mar 10 01:02:07 PM PDT 24
Peak memory	199336 kb
Host	smart-535fed58-9ee5-47d3-b9c6-0ff6bbd4ee43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438503159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1438503159
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.2467510026
Short name	T299
Test name
Test status
Simulation time	188815141681 ps
CPU time	64.09 seconds
Started	Mar 10 12:58:40 PM PDT 24
Finished	Mar 10 12:59:45 PM PDT 24
Peak memory	200100 kb
Host	smart-8dbb34c5-d3c9-4936-9dcc-703136512a6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467510026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2467510026
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.2307193128
Short name	T280
Test name
Test status
Simulation time	59458438119 ps
CPU time	10.15 seconds
Started	Mar 10 12:59:01 PM PDT 24
Finished	Mar 10 12:59:11 PM PDT 24
Peak memory	200084 kb
Host	smart-1739255c-d208-4a97-a4e0-221a20835ba1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307193128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2307193128
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.637861142
Short name	T312
Test name
Test status
Simulation time	43623852347 ps
CPU time	16.79 seconds
Started	Mar 10 12:59:11 PM PDT 24
Finished	Mar 10 12:59:28 PM PDT 24
Peak memory	199232 kb
Host	smart-0c63b6a5-318e-43c0-9bfc-37c01602084f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637861142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.637861142
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.3697407363
Short name	T212
Test name
Test status
Simulation time	177921403809 ps
CPU time	26.92 seconds
Started	Mar 10 12:59:16 PM PDT 24
Finished	Mar 10 12:59:43 PM PDT 24
Peak memory	200152 kb
Host	smart-c35cb5bc-b42e-4c5e-be2f-efed9d672cfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697407363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3697407363
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.2252324662
Short name	T281
Test name
Test status
Simulation time	165085728081 ps
CPU time	334.22 seconds
Started	Mar 10 12:52:15 PM PDT 24
Finished	Mar 10 12:57:50 PM PDT 24
Peak memory	200108 kb
Host	smart-e0731fa2-0f7f-4529-8088-fe80374b0c96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252324662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2252324662
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.1365829161
Short name	T337
Test name
Test status
Simulation time	49624364487 ps
CPU time	17.92 seconds
Started	Mar 10 12:59:15 PM PDT 24
Finished	Mar 10 12:59:33 PM PDT 24
Peak memory	200076 kb
Host	smart-25dd0d4a-46a9-4861-b5c0-77929cd070e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365829161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1365829161
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_stress_all.2818421059
Short name	T315
Test name
Test status
Simulation time	253271615069 ps
CPU time	1793.14 seconds
Started	Mar 10 12:52:31 PM PDT 24
Finished	Mar 10 01:22:25 PM PDT 24
Peak memory	200124 kb
Host	smart-430cd420-ad0a-4332-a0d7-d09fe5c6afcb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818421059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2818421059
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.997019074
Short name	T356
Test name
Test status
Simulation time	101344286991 ps
CPU time	81.75 seconds
Started	Mar 10 12:59:29 PM PDT 24
Finished	Mar 10 01:00:51 PM PDT 24
Peak memory	200136 kb
Host	smart-00613ae3-76d5-4459-8c6f-42a26d75528e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997019074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.997019074
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.257407353
Short name	T21
Test name
Test status
Simulation time	217304252305 ps
CPU time	90.31 seconds
Started	Mar 10 12:52:32 PM PDT 24
Finished	Mar 10 12:54:03 PM PDT 24
Peak memory	200120 kb
Host	smart-9a274e08-1071-409c-9dcc-35e84a17a708
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257407353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.257407353
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.2491868673
Short name	T351
Test name
Test status
Simulation time	251945320336 ps
CPU time	106.37 seconds
Started	Mar 10 12:59:36 PM PDT 24
Finished	Mar 10 01:01:22 PM PDT 24
Peak memory	200024 kb
Host	smart-bc8af97f-128a-4989-a09b-58181120320c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491868673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2491868673
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.527649385
Short name	T274
Test name
Test status
Simulation time	7789862556 ps
CPU time	13.16 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 12:59:55 PM PDT 24
Peak memory	198104 kb
Host	smart-5e8e9329-7ba8-4a83-b7e8-455957329d47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=527649385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.527649385
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.1431260680
Short name	T348
Test name
Test status
Simulation time	14900439314 ps
CPU time	25.88 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 01:00:09 PM PDT 24
Peak memory	199604 kb
Host	smart-9a55c846-78b0-455b-9ce8-ae83b08e8214
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431260680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1431260680
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.1826160549
Short name	T333
Test name
Test status
Simulation time	39807777094 ps
CPU time	63.04 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 01:00:45 PM PDT 24
Peak memory	199992 kb
Host	smart-e70224a6-3779-4bd2-83ec-d0b644b6f827
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826160549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1826160549
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.1104800867
Short name	T354
Test name
Test status
Simulation time	53825798466 ps
CPU time	84.31 seconds
Started	Mar 10 12:53:22 PM PDT 24
Finished	Mar 10 12:54:47 PM PDT 24
Peak memory	200040 kb
Host	smart-da76d149-7e8e-4d0b-a9ce-0cb8e13091fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104800867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1104800867
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_stress_all.810678295
Short name	T257
Test name
Test status
Simulation time	278577479999 ps
CPU time	228.48 seconds
Started	Mar 10 12:53:49 PM PDT 24
Finished	Mar 10 12:57:38 PM PDT 24
Peak memory	200264 kb
Host	smart-26b9673e-12d9-45af-b35e-13e29872c749
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810678295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.810678295
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/37.uart_stress_all.3014695505
Short name	T275
Test name
Test status
Simulation time	282640635935 ps
CPU time	1034.55 seconds
Started	Mar 10 12:54:12 PM PDT 24
Finished	Mar 10 01:11:26 PM PDT 24
Peak memory	208436 kb
Host	smart-ded97a27-6772-4aca-b40d-c8abe28e4300
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014695505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3014695505
Directory	/workspace/37.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.3914744919
Short name	T323
Test name
Test status
Simulation time	161710185277 ps
CPU time	57.48 seconds
Started	Mar 10 12:48:52 PM PDT 24
Finished	Mar 10 12:49:50 PM PDT 24
Peak memory	199936 kb
Host	smart-d566d5ac-4adf-401f-9cc3-87348dc6f791
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3914744919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3914744919
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.4147505853
Short name	T366
Test name
Test status
Simulation time	85510411920 ps
CPU time	17.92 seconds
Started	Mar 10 12:54:46 PM PDT 24
Finished	Mar 10 12:55:04 PM PDT 24
Peak memory	199232 kb
Host	smart-8896eec9-fa84-45fe-8969-129e37b639cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147505853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4147505853
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_stress_all.2716848588
Short name	T218
Test name
Test status
Simulation time	229164267499 ps
CPU time	1189.49 seconds
Started	Mar 10 12:55:09 PM PDT 24
Finished	Mar 10 01:14:59 PM PDT 24
Peak memory	200080 kb
Host	smart-b54caf88-1b9e-4d66-ba62-637f78ab1410
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716848588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2716848588
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.3574237140
Short name	T363
Test name
Test status
Simulation time	147761681572 ps
CPU time	23.66 seconds
Started	Mar 10 12:55:50 PM PDT 24
Finished	Mar 10 12:56:14 PM PDT 24
Peak memory	200196 kb
Host	smart-5d741614-433c-4d0f-a9d1-0c2e64229931
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574237140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3574237140
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_stress_all_with_rand_reset.2370238533
Short name	T338
Test name
Test status
Simulation time	88060016478 ps
CPU time	432.33 seconds
Started	Mar 10 12:55:55 PM PDT 24
Finished	Mar 10 01:03:07 PM PDT 24
Peak memory	215592 kb
Host	smart-60f3f93c-17ba-4079-af93-bc16eb34c30f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370238533 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2370238533
Directory	/workspace/47.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.uart_stress_all_with_rand_reset.3276189573
Short name	T39
Test name
Test status
Simulation time	234705863753 ps
CPU time	311.91 seconds
Started	Mar 10 12:56:10 PM PDT 24
Finished	Mar 10 01:01:22 PM PDT 24
Peak memory	210860 kb
Host	smart-10589fed-1087-407c-b86b-32bbe9be1580
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276189573 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3276189573
Directory	/workspace/49.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.3002655005
Short name	T8
Test name
Test status
Simulation time	45653458640 ps
CPU time	55.27 seconds
Started	Mar 10 12:56:34 PM PDT 24
Finished	Mar 10 12:57:29 PM PDT 24
Peak memory	200124 kb
Host	smart-8e6624c7-47fa-48f3-98c7-2655a37c4cc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002655005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3002655005
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.349316877
Short name	T66
Test name
Test status
Simulation time	58578500 ps
CPU time	2.08 seconds
Started	Mar 10 12:24:19 PM PDT 24
Finished	Mar 10 12:24:22 PM PDT 24
Peak memory	197348 kb
Host	smart-07b574ca-be02-4c9d-af25-71d49f5d4110
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349316877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.349316877
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3874958399
Short name	T1249
Test name
Test status
Simulation time	18512559 ps
CPU time	0.61 seconds
Started	Mar 10 12:20:40 PM PDT 24
Finished	Mar 10 12:20:41 PM PDT 24
Peak memory	195776 kb
Host	smart-f27299b6-ba1f-4369-a73f-24f29e355701
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874958399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3874958399
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.47847198
Short name	T1204
Test name
Test status
Simulation time	22787660 ps
CPU time	0.79 seconds
Started	Mar 10 12:20:11 PM PDT 24
Finished	Mar 10 12:20:13 PM PDT 24
Peak memory	197412 kb
Host	smart-6567560e-fa25-49e7-9a4b-d77f5be96280
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47847198 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.47847198
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.2622702175
Short name	T71
Test name
Test status
Simulation time	22197153 ps
CPU time	0.58 seconds
Started	Mar 10 12:24:38 PM PDT 24
Finished	Mar 10 12:24:39 PM PDT 24
Peak memory	195660 kb
Host	smart-d4af8fc3-5585-4c14-a2ae-3d847647fa21
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622702175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2622702175
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.1187829652
Short name	T1167
Test name
Test status
Simulation time	45793417 ps
CPU time	0.56 seconds
Started	Mar 10 12:24:38 PM PDT 24
Finished	Mar 10 12:24:39 PM PDT 24
Peak memory	194612 kb
Host	smart-9355ff9a-96e9-45e4-af3f-679c44d5e276
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187829652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1187829652
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1050055463
Short name	T1178
Test name
Test status
Simulation time	55797245 ps
CPU time	0.62 seconds
Started	Mar 10 12:20:26 PM PDT 24
Finished	Mar 10 12:20:27 PM PDT 24
Peak memory	195648 kb
Host	smart-702973e8-146a-4676-bf63-15293aee5bb5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050055463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.1050055463
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.4047092037
Short name	T1202
Test name
Test status
Simulation time	28451663 ps
CPU time	1.21 seconds
Started	Mar 10 12:24:38 PM PDT 24
Finished	Mar 10 12:24:39 PM PDT 24
Peak memory	200240 kb
Host	smart-0319db0d-f00b-4740-8f6f-ce09e2418cec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047092037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4047092037
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3767436846
Short name	T1129
Test name
Test status
Simulation time	140160952 ps
CPU time	0.69 seconds
Started	Mar 10 12:22:38 PM PDT 24
Finished	Mar 10 12:22:39 PM PDT 24
Peak memory	194032 kb
Host	smart-e9f960d8-e51f-4968-b900-78f3249fab21
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767436846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3767436846
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2935609099
Short name	T1244
Test name
Test status
Simulation time	507664938 ps
CPU time	2.53 seconds
Started	Mar 10 12:17:56 PM PDT 24
Finished	Mar 10 12:17:59 PM PDT 24
Peak memory	198000 kb
Host	smart-32de6de1-50e3-4a5c-bf69-d320060f8eed
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935609099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2935609099
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.534864662
Short name	T1239
Test name
Test status
Simulation time	24833027 ps
CPU time	0.61 seconds
Started	Mar 10 12:22:57 PM PDT 24
Finished	Mar 10 12:22:57 PM PDT 24
Peak memory	195712 kb
Host	smart-a1236cd7-3b91-4f42-a518-7718bd1ef23f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534864662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.534864662
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3258154188
Short name	T1174
Test name
Test status
Simulation time	36369335 ps
CPU time	1.05 seconds
Started	Mar 10 12:22:57 PM PDT 24
Finished	Mar 10 12:22:58 PM PDT 24
Peak memory	200112 kb
Host	smart-50ab88f8-feb0-4da9-aaeb-b123f01a321a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258154188 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3258154188
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.3326951609
Short name	T1217
Test name
Test status
Simulation time	55216112 ps
CPU time	0.64 seconds
Started	Mar 10 12:18:28 PM PDT 24
Finished	Mar 10 12:18:29 PM PDT 24
Peak memory	195984 kb
Host	smart-2cc42f06-08c2-44f6-ab60-28871fadc62c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326951609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3326951609
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.2466363028
Short name	T1168
Test name
Test status
Simulation time	15813833 ps
CPU time	0.6 seconds
Started	Mar 10 12:33:02 PM PDT 24
Finished	Mar 10 12:33:04 PM PDT 24
Peak memory	193796 kb
Host	smart-049cf6e0-f3f8-4713-951f-6cbde7a9799a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466363028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2466363028
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1393062813
Short name	T1196
Test name
Test status
Simulation time	61434534 ps
CPU time	0.63 seconds
Started	Mar 10 12:22:56 PM PDT 24
Finished	Mar 10 12:22:57 PM PDT 24
Peak memory	195712 kb
Host	smart-406c6531-e55c-4b36-8a4e-c3d9dac76a41
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393062813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.1393062813
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.3262962723
Short name	T1133
Test name
Test status
Simulation time	487842018 ps
CPU time	2.2 seconds
Started	Mar 10 12:20:26 PM PDT 24
Finished	Mar 10 12:20:28 PM PDT 24
Peak memory	200212 kb
Host	smart-3ff06306-ef45-4b6d-8061-dfd7d2f9dd9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262962723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3262962723
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2343232470
Short name	T91
Test name
Test status
Simulation time	185172250 ps
CPU time	1.02 seconds
Started	Mar 10 12:18:02 PM PDT 24
Finished	Mar 10 12:18:04 PM PDT 24
Peak memory	199244 kb
Host	smart-9fc8066f-b3e6-4cca-83cc-a51dc5c4f38c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343232470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2343232470
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1534469251
Short name	T1151
Test name
Test status
Simulation time	20965925 ps
CPU time	0.72 seconds
Started	Mar 10 12:20:52 PM PDT 24
Finished	Mar 10 12:20:54 PM PDT 24
Peak memory	197672 kb
Host	smart-7ba46365-d795-4a90-85f6-1f7b28be9897
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534469251 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1534469251
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.3755743388
Short name	T1220
Test name
Test status
Simulation time	11989853 ps
CPU time	0.57 seconds
Started	Mar 10 12:20:54 PM PDT 24
Finished	Mar 10 12:20:57 PM PDT 24
Peak memory	194900 kb
Host	smart-053a1916-5dcb-47c6-8573-4c8087ebe7f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755743388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3755743388
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.146709659
Short name	T76
Test name
Test status
Simulation time	31274772 ps
CPU time	0.68 seconds
Started	Mar 10 12:24:26 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	193784 kb
Host	smart-aff9a947-7807-4c69-b993-005a926046f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146709659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr _outstanding.146709659
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.3218280089
Short name	T1149
Test name
Test status
Simulation time	41347897 ps
CPU time	1.07 seconds
Started	Mar 10 12:20:48 PM PDT 24
Finished	Mar 10 12:20:51 PM PDT 24
Peak memory	200540 kb
Host	smart-5cf4141e-15aa-46ce-92a0-c6e5684896de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218280089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3218280089
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3225227959
Short name	T1153
Test name
Test status
Simulation time	92914421 ps
CPU time	1.2 seconds
Started	Mar 10 12:21:16 PM PDT 24
Finished	Mar 10 12:21:17 PM PDT 24
Peak memory	199832 kb
Host	smart-d70747c0-6aa7-4a12-8412-a5a680ade0ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225227959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3225227959
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2934426283
Short name	T1125
Test name
Test status
Simulation time	54809421 ps
CPU time	0.71 seconds
Started	Mar 10 12:20:59 PM PDT 24
Finished	Mar 10 12:21:00 PM PDT 24
Peak memory	197848 kb
Host	smart-9f9dd4d0-414f-4d34-8e95-7ab40b64dfa3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934426283 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2934426283
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.2363045763
Short name	T70
Test name
Test status
Simulation time	31788965 ps
CPU time	0.57 seconds
Started	Mar 10 12:23:28 PM PDT 24
Finished	Mar 10 12:23:29 PM PDT 24
Peak memory	195712 kb
Host	smart-ca427342-c4a1-492e-8fb1-4e8fefc5948d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363045763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2363045763
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.1111979983
Short name	T1130
Test name
Test status
Simulation time	12573655 ps
CPU time	0.63 seconds
Started	Mar 10 12:21:21 PM PDT 24
Finished	Mar 10 12:21:22 PM PDT 24
Peak memory	194568 kb
Host	smart-ad8f1f03-d61c-4e8c-b2fa-d780ed1290e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111979983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1111979983
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.282489995
Short name	T73
Test name
Test status
Simulation time	49787751 ps
CPU time	0.65 seconds
Started	Mar 10 12:21:20 PM PDT 24
Finished	Mar 10 12:21:21 PM PDT 24
Peak memory	196000 kb
Host	smart-17d5be2d-e35c-4198-8458-bce14e00f645
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282489995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr _outstanding.282489995
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.2557105006
Short name	T1144
Test name
Test status
Simulation time	149907753 ps
CPU time	1.62 seconds
Started	Mar 10 12:22:25 PM PDT 24
Finished	Mar 10 12:22:27 PM PDT 24
Peak memory	200268 kb
Host	smart-ddb5de5c-8ae6-42cb-bad0-a31a0de4d345
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557105006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2557105006
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4989541
Short name	T84
Test name
Test status
Simulation time	80382127 ps
CPU time	1.23 seconds
Started	Mar 10 12:21:21 PM PDT 24
Finished	Mar 10 12:21:22 PM PDT 24
Peak memory	199352 kb
Host	smart-667b32b7-9b81-4a86-8753-565f12059f0d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4989541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4989541
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2702235844
Short name	T1132
Test name
Test status
Simulation time	21554241 ps
CPU time	0.95 seconds
Started	Mar 10 12:24:32 PM PDT 24
Finished	Mar 10 12:24:33 PM PDT 24
Peak memory	200112 kb
Host	smart-3b989977-5969-401f-ac00-598a63bfd762
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702235844 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2702235844
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.3009636339
Short name	T1233
Test name
Test status
Simulation time	83639967 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:32 PM PDT 24
Finished	Mar 10 12:24:33 PM PDT 24
Peak memory	195712 kb
Host	smart-8150eb4f-1ba0-4b63-bcf8-4e38e2f00ef5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009636339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3009636339
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.180145121
Short name	T1146
Test name
Test status
Simulation time	40918726 ps
CPU time	0.53 seconds
Started	Mar 10 12:24:32 PM PDT 24
Finished	Mar 10 12:24:33 PM PDT 24
Peak memory	194668 kb
Host	smart-3d3d83d2-f3c8-4274-be18-0557b71642d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180145121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.180145121
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3485984498
Short name	T74
Test name
Test status
Simulation time	40829281 ps
CPU time	0.65 seconds
Started	Mar 10 12:22:52 PM PDT 24
Finished	Mar 10 12:22:53 PM PDT 24
Peak memory	194492 kb
Host	smart-1410d362-3477-4f4f-a311-9d1d0fc7c659
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485984498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.3485984498
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.404164711
Short name	T1159
Test name
Test status
Simulation time	66259481 ps
CPU time	1.54 seconds
Started	Mar 10 12:23:20 PM PDT 24
Finished	Mar 10 12:23:22 PM PDT 24
Peak memory	200388 kb
Host	smart-6b00611a-510f-4429-84c6-1a79dd6340bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404164711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.404164711
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2091352167
Short name	T1250
Test name
Test status
Simulation time	181136470 ps
CPU time	0.91 seconds
Started	Mar 10 12:24:32 PM PDT 24
Finished	Mar 10 12:24:33 PM PDT 24
Peak memory	198976 kb
Host	smart-bfbb5609-23d4-4177-90b1-5978c9340b60
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091352167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2091352167
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.615024644
Short name	T1139
Test name
Test status
Simulation time	90509942 ps
CPU time	0.75 seconds
Started	Mar 10 12:23:09 PM PDT 24
Finished	Mar 10 12:23:10 PM PDT 24
Peak memory	199868 kb
Host	smart-4e85aa1c-8965-4022-85d4-a4fba9a39be9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615024644 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.615024644
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.3955423684
Short name	T1137
Test name
Test status
Simulation time	57907997 ps
CPU time	0.58 seconds
Started	Mar 10 12:23:09 PM PDT 24
Finished	Mar 10 12:23:10 PM PDT 24
Peak memory	195660 kb
Host	smart-b492e983-9126-4b44-8545-352e4a003139
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955423684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3955423684
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.3575767178
Short name	T1148
Test name
Test status
Simulation time	36715531 ps
CPU time	0.59 seconds
Started	Mar 10 12:24:15 PM PDT 24
Finished	Mar 10 12:24:16 PM PDT 24
Peak memory	193468 kb
Host	smart-0089f78b-9551-4a4a-b750-3eeb1d750992
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575767178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3575767178
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1340411101
Short name	T1240
Test name
Test status
Simulation time	45894576 ps
CPU time	0.69 seconds
Started	Mar 10 12:24:32 PM PDT 24
Finished	Mar 10 12:24:33 PM PDT 24
Peak memory	197120 kb
Host	smart-84fad29c-22ef-4469-9309-34f107eed2e9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340411101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.1340411101
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.1916496669
Short name	T1212
Test name
Test status
Simulation time	40080527 ps
CPU time	2.09 seconds
Started	Mar 10 12:23:09 PM PDT 24
Finished	Mar 10 12:23:11 PM PDT 24
Peak memory	200244 kb
Host	smart-b6cb4aad-a3d8-409c-8e78-670e052302b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916496669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1916496669
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3302030016
Short name	T1205
Test name
Test status
Simulation time	66755373 ps
CPU time	0.66 seconds
Started	Mar 10 12:24:23 PM PDT 24
Finished	Mar 10 12:24:24 PM PDT 24
Peak memory	197024 kb
Host	smart-6c428089-0cbd-454b-a990-9f863898937c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302030016 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3302030016
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.3165734863
Short name	T60
Test name
Test status
Simulation time	45404784 ps
CPU time	0.56 seconds
Started	Mar 10 12:32:53 PM PDT 24
Finished	Mar 10 12:32:54 PM PDT 24
Peak memory	195844 kb
Host	smart-9c0c190f-df0b-4f63-a24c-5ab905fe0ccd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165734863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3165734863
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.3210148650
Short name	T1226
Test name
Test status
Simulation time	19894821 ps
CPU time	0.55 seconds
Started	Mar 10 12:21:21 PM PDT 24
Finished	Mar 10 12:21:21 PM PDT 24
Peak memory	194568 kb
Host	smart-b2d0aa26-4801-4c2e-b6d0-8661ce29521a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210148650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3210148650
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.329428723
Short name	T1251
Test name
Test status
Simulation time	32053636 ps
CPU time	0.75 seconds
Started	Mar 10 12:21:06 PM PDT 24
Finished	Mar 10 12:21:07 PM PDT 24
Peak memory	197136 kb
Host	smart-b9f02dd1-c655-4949-89ac-cbf29034335d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329428723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr _outstanding.329428723
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3585969981
Short name	T1246
Test name
Test status
Simulation time	30007209 ps
CPU time	1.06 seconds
Started	Mar 10 12:24:32 PM PDT 24
Finished	Mar 10 12:24:34 PM PDT 24
Peak memory	200260 kb
Host	smart-6a11ea85-ea4f-4b02-8fe8-84aac93401c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585969981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3585969981
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.903114672
Short name	T1237
Test name
Test status
Simulation time	47280137 ps
CPU time	0.93 seconds
Started	Mar 10 12:23:09 PM PDT 24
Finished	Mar 10 12:23:10 PM PDT 24
Peak memory	199252 kb
Host	smart-400b7c02-447f-47c0-914c-0c7ab3e57c6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903114672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.903114672
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.172009728
Short name	T1184
Test name
Test status
Simulation time	119869234 ps
CPU time	1.29 seconds
Started	Mar 10 12:21:08 PM PDT 24
Finished	Mar 10 12:21:10 PM PDT 24
Peak memory	200524 kb
Host	smart-58c1c8fb-ac2c-4d30-ae36-b7ea55981a07
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172009728 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.172009728
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.1556594739
Short name	T1245
Test name
Test status
Simulation time	51116573 ps
CPU time	0.6 seconds
Started	Mar 10 12:21:17 PM PDT 24
Finished	Mar 10 12:21:17 PM PDT 24
Peak memory	195720 kb
Host	smart-ceef6d95-8803-4b2d-b3ef-ee8893ddac62
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556594739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1556594739
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.1500620302
Short name	T1207
Test name
Test status
Simulation time	139894190 ps
CPU time	0.55 seconds
Started	Mar 10 12:21:29 PM PDT 24
Finished	Mar 10 12:21:30 PM PDT 24
Peak memory	195100 kb
Host	smart-c289b96a-64fb-4788-973f-521184641967
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500620302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1500620302
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4266336925
Short name	T1161
Test name
Test status
Simulation time	121944874 ps
CPU time	0.71 seconds
Started	Mar 10 12:21:38 PM PDT 24
Finished	Mar 10 12:21:39 PM PDT 24
Peak memory	195992 kb
Host	smart-c385b229-f979-479d-98ca-aa3c18a951ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266336925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.4266336925
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.1173765991
Short name	T1230
Test name
Test status
Simulation time	106844531 ps
CPU time	1.77 seconds
Started	Mar 10 12:21:06 PM PDT 24
Finished	Mar 10 12:21:08 PM PDT 24
Peak memory	200324 kb
Host	smart-e718399e-8338-43fd-bf8f-be748ce52ae6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173765991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1173765991
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.97589608
Short name	T89
Test name
Test status
Simulation time	154313612 ps
CPU time	0.86 seconds
Started	Mar 10 12:23:29 PM PDT 24
Finished	Mar 10 12:23:30 PM PDT 24
Peak memory	198772 kb
Host	smart-effcd6fa-1de2-4816-8673-792578bc434d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97589608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.97589608
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1040849684
Short name	T1169
Test name
Test status
Simulation time	105723458 ps
CPU time	0.96 seconds
Started	Mar 10 12:21:29 PM PDT 24
Finished	Mar 10 12:21:30 PM PDT 24
Peak memory	200544 kb
Host	smart-145b7511-7b7f-4e07-a38c-7897d3422456
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040849684 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1040849684
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.1957933123
Short name	T1171
Test name
Test status
Simulation time	45642160 ps
CPU time	0.62 seconds
Started	Mar 10 12:21:38 PM PDT 24
Finished	Mar 10 12:21:38 PM PDT 24
Peak memory	195724 kb
Host	smart-ad3c88a1-e333-402c-bfc8-76274b7fa008
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957933123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1957933123
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.599539283
Short name	T1163
Test name
Test status
Simulation time	28684596 ps
CPU time	0.54 seconds
Started	Mar 10 12:21:28 PM PDT 24
Finished	Mar 10 12:21:29 PM PDT 24
Peak memory	194720 kb
Host	smart-241b57ae-243e-40e8-9e1d-ca5f227a8d3d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599539283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.599539283
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1723874987
Short name	T75
Test name
Test status
Simulation time	15025770 ps
CPU time	0.68 seconds
Started	Mar 10 12:24:42 PM PDT 24
Finished	Mar 10 12:24:43 PM PDT 24
Peak memory	197096 kb
Host	smart-aae9b537-b531-4889-b075-316d37a6ace2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723874987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.1723874987
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.1983564278
Short name	T1258
Test name
Test status
Simulation time	213428718 ps
CPU time	1.22 seconds
Started	Mar 10 12:21:05 PM PDT 24
Finished	Mar 10 12:21:06 PM PDT 24
Peak memory	200376 kb
Host	smart-c9f3e52e-ba69-4b6f-b9d7-55e728daf68e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983564278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1983564278
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4045233485
Short name	T82
Test name
Test status
Simulation time	735815243 ps
CPU time	0.87 seconds
Started	Mar 10 12:27:34 PM PDT 24
Finished	Mar 10 12:27:36 PM PDT 24
Peak memory	199092 kb
Host	smart-f5387aa4-9fc8-4e77-b283-e59d53dc6969
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045233485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.4045233485
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.465927466
Short name	T1162
Test name
Test status
Simulation time	26136185 ps
CPU time	0.79 seconds
Started	Mar 10 12:26:23 PM PDT 24
Finished	Mar 10 12:26:25 PM PDT 24
Peak memory	198656 kb
Host	smart-9aa14b34-9c80-4bd7-b3de-3d8022686118
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465927466 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.465927466
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.117578560
Short name	T62
Test name
Test status
Simulation time	18793713 ps
CPU time	0.58 seconds
Started	Mar 10 12:27:40 PM PDT 24
Finished	Mar 10 12:27:41 PM PDT 24
Peak memory	195748 kb
Host	smart-0c6c5174-ea9b-4dec-ab37-d4a1ab2cd86c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117578560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.117578560
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.400073528
Short name	T1208
Test name
Test status
Simulation time	17275687 ps
CPU time	0.6 seconds
Started	Mar 10 12:21:15 PM PDT 24
Finished	Mar 10 12:21:16 PM PDT 24
Peak memory	195100 kb
Host	smart-ad246819-eea2-4d1f-a8e7-fe2d92c2bbb2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400073528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.400073528
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3246524039
Short name	T1215
Test name
Test status
Simulation time	114123247 ps
CPU time	0.67 seconds
Started	Mar 10 12:24:27 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	195752 kb
Host	smart-5fcb0b12-819a-4419-80c9-d42ded861caa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246524039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.3246524039
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.3973549829
Short name	T1209
Test name
Test status
Simulation time	149441212 ps
CPU time	1.53 seconds
Started	Mar 10 12:21:55 PM PDT 24
Finished	Mar 10 12:21:57 PM PDT 24
Peak memory	200296 kb
Host	smart-b173b687-7437-4511-b2bb-c2f5b97c1d1e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973549829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3973549829
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3945469696
Short name	T374
Test name
Test status
Simulation time	97551427 ps
CPU time	1.4 seconds
Started	Mar 10 12:27:38 PM PDT 24
Finished	Mar 10 12:27:39 PM PDT 24
Peak memory	199392 kb
Host	smart-ed2c200a-870e-4c88-8d37-d1f346b02627
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945469696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3945469696
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2526521020
Short name	T1134
Test name
Test status
Simulation time	89719541 ps
CPU time	0.74 seconds
Started	Mar 10 12:21:20 PM PDT 24
Finished	Mar 10 12:21:21 PM PDT 24
Peak memory	198952 kb
Host	smart-0cab143f-e34f-46dd-a461-177afbb3f9c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526521020 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2526521020
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.3315550120
Short name	T1179
Test name
Test status
Simulation time	69315273 ps
CPU time	0.59 seconds
Started	Mar 10 12:26:43 PM PDT 24
Finished	Mar 10 12:26:44 PM PDT 24
Peak memory	195740 kb
Host	smart-caf3e54b-3b27-42fe-b019-1dbafddeabaf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315550120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3315550120
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.1355230942
Short name	T1185
Test name
Test status
Simulation time	14470984 ps
CPU time	0.6 seconds
Started	Mar 10 12:23:36 PM PDT 24
Finished	Mar 10 12:23:37 PM PDT 24
Peak memory	194644 kb
Host	smart-cb8833ce-3c11-4c25-9a21-330f99d59f7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355230942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1355230942
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.934860082
Short name	T1257
Test name
Test status
Simulation time	41197380 ps
CPU time	0.62 seconds
Started	Mar 10 12:26:41 PM PDT 24
Finished	Mar 10 12:26:42 PM PDT 24
Peak memory	194780 kb
Host	smart-66d16bcd-0d4b-4cf9-b003-11790a101414
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934860082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr _outstanding.934860082
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.365084155
Short name	T1235
Test name
Test status
Simulation time	508776346 ps
CPU time	2.24 seconds
Started	Mar 10 12:21:24 PM PDT 24
Finished	Mar 10 12:21:26 PM PDT 24
Peak memory	200556 kb
Host	smart-e71a62ea-b6fc-4408-aa19-145cd232d672
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365084155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.365084155
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1753255715
Short name	T86
Test name
Test status
Simulation time	53530219 ps
CPU time	0.98 seconds
Started	Mar 10 12:27:37 PM PDT 24
Finished	Mar 10 12:27:38 PM PDT 24
Peak memory	199088 kb
Host	smart-f87c0a3d-e974-4136-8fef-70f811bd6988
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753255715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1753255715
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4228472224
Short name	T1241
Test name
Test status
Simulation time	99824875 ps
CPU time	0.81 seconds
Started	Mar 10 12:24:27 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	199868 kb
Host	smart-589ce14f-7799-4783-a17f-3429d4981e38
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228472224 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4228472224
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.2515640216
Short name	T1254
Test name
Test status
Simulation time	16478009 ps
CPU time	0.6 seconds
Started	Mar 10 12:24:27 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	195676 kb
Host	smart-31928521-6b81-4e9d-ba8c-dceeb51a5c99
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515640216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2515640216
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.3956036519
Short name	T1213
Test name
Test status
Simulation time	77655516 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:37 PM PDT 24
Finished	Mar 10 12:24:38 PM PDT 24
Peak memory	193864 kb
Host	smart-ef980224-2729-492c-bb37-eaee99876a65
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956036519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3956036519
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1879093094
Short name	T1221
Test name
Test status
Simulation time	27601714 ps
CPU time	0.79 seconds
Started	Mar 10 12:21:21 PM PDT 24
Finished	Mar 10 12:21:22 PM PDT 24
Peak memory	197212 kb
Host	smart-db32f579-8e81-489f-840b-78e6b1ffba6f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879093094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.1879093094
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.1470672175
Short name	T1131
Test name
Test status
Simulation time	149088826 ps
CPU time	2.02 seconds
Started	Mar 10 12:21:24 PM PDT 24
Finished	Mar 10 12:21:26 PM PDT 24
Peak memory	200520 kb
Host	smart-b896fbe0-c431-405b-b7a3-a178615374a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470672175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1470672175
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.594882365
Short name	T80
Test name
Test status
Simulation time	37512076 ps
CPU time	1 seconds
Started	Mar 10 12:21:29 PM PDT 24
Finished	Mar 10 12:21:30 PM PDT 24
Peak memory	199128 kb
Host	smart-b8dd4eaf-2c48-4dea-a837-f81f1f122374
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594882365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.594882365
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3893033450
Short name	T1164
Test name
Test status
Simulation time	39989053 ps
CPU time	0.78 seconds
Started	Mar 10 12:24:12 PM PDT 24
Finished	Mar 10 12:24:13 PM PDT 24
Peak memory	194068 kb
Host	smart-53b6b2e3-cfa5-4450-a3dd-7851a0c052a7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893033450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3893033450
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1302545266
Short name	T1173
Test name
Test status
Simulation time	687006065 ps
CPU time	2.38 seconds
Started	Mar 10 12:24:43 PM PDT 24
Finished	Mar 10 12:24:47 PM PDT 24
Peak memory	197828 kb
Host	smart-c17cd701-f646-4e3e-b9f3-2c6f51a9c35a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302545266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1302545266
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.109791847
Short name	T1150
Test name
Test status
Simulation time	38183521 ps
CPU time	0.63 seconds
Started	Mar 10 12:19:23 PM PDT 24
Finished	Mar 10 12:19:25 PM PDT 24
Peak memory	195940 kb
Host	smart-f42a9615-edd2-47e8-bf15-b1d5de738afc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109791847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.109791847
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.758563714
Short name	T1227
Test name
Test status
Simulation time	24328961 ps
CPU time	0.79 seconds
Started	Mar 10 12:32:53 PM PDT 24
Finished	Mar 10 12:32:53 PM PDT 24
Peak memory	199288 kb
Host	smart-ffa8654d-186e-4091-840e-896ed001049d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758563714 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.758563714
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.3790439180
Short name	T1216
Test name
Test status
Simulation time	12377729 ps
CPU time	0.63 seconds
Started	Mar 10 12:33:45 PM PDT 24
Finished	Mar 10 12:33:46 PM PDT 24
Peak memory	195800 kb
Host	smart-dd07f778-f3f4-4d18-a71e-48b1a276fdfe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790439180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3790439180
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.1442176037
Short name	T1214
Test name
Test status
Simulation time	32105915 ps
CPU time	0.63 seconds
Started	Mar 10 12:21:03 PM PDT 24
Finished	Mar 10 12:21:04 PM PDT 24
Peak memory	194556 kb
Host	smart-47db0186-2113-432d-b6e7-623a20f915af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442176037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1442176037
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2275578145
Short name	T1242
Test name
Test status
Simulation time	16674543 ps
CPU time	0.66 seconds
Started	Mar 10 12:24:26 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	193816 kb
Host	smart-09d557d9-1931-44b4-b7d1-ca413356e633
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275578145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.2275578145
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.4073449423
Short name	T1147
Test name
Test status
Simulation time	472359346 ps
CPU time	2.47 seconds
Started	Mar 10 12:26:22 PM PDT 24
Finished	Mar 10 12:26:26 PM PDT 24
Peak memory	198596 kb
Host	smart-c4634c30-449a-4d81-bfc4-3646075fa3e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073449423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4073449423
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.1038649558
Short name	T1127
Test name
Test status
Simulation time	14334989 ps
CPU time	0.65 seconds
Started	Mar 10 12:23:58 PM PDT 24
Finished	Mar 10 12:23:59 PM PDT 24
Peak memory	193556 kb
Host	smart-fa0d026b-82c0-4067-b5ea-5e4162ed40ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038649558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1038649558
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.3502623811
Short name	T1126
Test name
Test status
Simulation time	98094140 ps
CPU time	0.6 seconds
Started	Mar 10 12:21:24 PM PDT 24
Finished	Mar 10 12:21:25 PM PDT 24
Peak memory	194852 kb
Host	smart-ae157f41-2576-490d-aa5b-5d46464009bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502623811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3502623811
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.3936488205
Short name	T1187
Test name
Test status
Simulation time	18653358 ps
CPU time	0.56 seconds
Started	Mar 10 12:33:10 PM PDT 24
Finished	Mar 10 12:33:11 PM PDT 24
Peak memory	194760 kb
Host	smart-1a241a88-2e87-44d9-9de2-b10d9937a6b4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936488205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3936488205
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.2855917446
Short name	T1154
Test name
Test status
Simulation time	46478868 ps
CPU time	0.54 seconds
Started	Mar 10 12:24:11 PM PDT 24
Finished	Mar 10 12:24:12 PM PDT 24
Peak memory	193660 kb
Host	smart-6fe69936-9fdd-4b72-8a24-8c7a05a829ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855917446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2855917446
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.2574219541
Short name	T1201
Test name
Test status
Simulation time	40285457 ps
CPU time	0.64 seconds
Started	Mar 10 12:23:58 PM PDT 24
Finished	Mar 10 12:23:59 PM PDT 24
Peak memory	193700 kb
Host	smart-e3bf629a-6208-40cc-aa16-4e2cd69276fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574219541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2574219541
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1469412559
Short name	T1145
Test name
Test status
Simulation time	35654887 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:27 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	194616 kb
Host	smart-72849b48-61cb-46af-9d90-f8c8783bfbf9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469412559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1469412559
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.873132350
Short name	T1138
Test name
Test status
Simulation time	38308671 ps
CPU time	0.53 seconds
Started	Mar 10 12:24:27 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	194620 kb
Host	smart-1c456217-fd33-4475-a042-ef57282060d5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873132350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.873132350
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.2353054161
Short name	T1243
Test name
Test status
Simulation time	21576146 ps
CPU time	0.56 seconds
Started	Mar 10 12:24:27 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	194620 kb
Host	smart-ccd7f750-b7fc-44b7-86e5-1c3c3d54b17e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353054161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2353054161
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.2762086600
Short name	T1256
Test name
Test status
Simulation time	13782245 ps
CPU time	0.57 seconds
Started	Mar 10 12:24:11 PM PDT 24
Finished	Mar 10 12:24:12 PM PDT 24
Peak memory	193132 kb
Host	smart-176fb6ae-7ae5-4462-b401-31e25fdb80db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762086600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2762086600
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.2894345854
Short name	T1193
Test name
Test status
Simulation time	52293704 ps
CPU time	0.58 seconds
Started	Mar 10 12:21:29 PM PDT 24
Finished	Mar 10 12:21:30 PM PDT 24
Peak memory	194736 kb
Host	smart-4a3b332b-9536-4e72-a3b6-384846365a0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894345854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2894345854
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3341239117
Short name	T1195
Test name
Test status
Simulation time	35518310 ps
CPU time	0.69 seconds
Started	Mar 10 12:23:58 PM PDT 24
Finished	Mar 10 12:23:59 PM PDT 24
Peak memory	195672 kb
Host	smart-eea807f9-ec2c-4018-8dd8-621f799df8d1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341239117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3341239117
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2939689381
Short name	T1175
Test name
Test status
Simulation time	171696600 ps
CPU time	2.53 seconds
Started	Mar 10 12:27:05 PM PDT 24
Finished	Mar 10 12:27:08 PM PDT 24
Peak memory	196708 kb
Host	smart-e97bbc6c-20cd-4698-9aed-a37779ef7988
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939689381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2939689381
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3143551591
Short name	T1143
Test name
Test status
Simulation time	74023085 ps
CPU time	0.58 seconds
Started	Mar 10 12:24:12 PM PDT 24
Finished	Mar 10 12:24:13 PM PDT 24
Peak memory	193764 kb
Host	smart-82957088-6f3a-458a-8af3-792d83aac193
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143551591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3143551591
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.86369356
Short name	T1170
Test name
Test status
Simulation time	247775466 ps
CPU time	0.67 seconds
Started	Mar 10 12:20:39 PM PDT 24
Finished	Mar 10 12:20:39 PM PDT 24
Peak memory	197716 kb
Host	smart-744c0bc0-1cde-48dd-97a2-683363d53431
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86369356 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.86369356
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.388382033
Short name	T69
Test name
Test status
Simulation time	42378410 ps
CPU time	0.64 seconds
Started	Mar 10 12:21:19 PM PDT 24
Finished	Mar 10 12:21:20 PM PDT 24
Peak memory	195804 kb
Host	smart-89f33cd8-8821-484f-be9a-a53dd0cf8617
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388382033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.388382033
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.3815072871
Short name	T1177
Test name
Test status
Simulation time	13862976 ps
CPU time	0.56 seconds
Started	Mar 10 12:24:13 PM PDT 24
Finished	Mar 10 12:24:14 PM PDT 24
Peak memory	194604 kb
Host	smart-1b02bf27-6c38-4cb8-a07d-1ffd97a76244
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815072871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3815072871
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1398553809
Short name	T1189
Test name
Test status
Simulation time	29976066 ps
CPU time	0.8 seconds
Started	Mar 10 12:33:55 PM PDT 24
Finished	Mar 10 12:33:57 PM PDT 24
Peak memory	197252 kb
Host	smart-0ad00aa3-059e-4335-841c-659a81a8b8c4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398553809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.1398553809
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.485337239
Short name	T1135
Test name
Test status
Simulation time	79746438 ps
CPU time	2.18 seconds
Started	Mar 10 12:32:59 PM PDT 24
Finished	Mar 10 12:33:01 PM PDT 24
Peak memory	200332 kb
Host	smart-8cd0bdeb-0c0b-4d80-a6d3-1bf0d8651b05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485337239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.485337239
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1533756623
Short name	T1238
Test name
Test status
Simulation time	185533334 ps
CPU time	0.95 seconds
Started	Mar 10 12:24:27 PM PDT 24
Finished	Mar 10 12:24:28 PM PDT 24
Peak memory	198984 kb
Host	smart-47240a0a-d675-445e-9423-ba9c3be02491
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533756623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1533756623
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.3584069319
Short name	T1197
Test name
Test status
Simulation time	14053939 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:06 PM PDT 24
Finished	Mar 10 12:24:07 PM PDT 24
Peak memory	194588 kb
Host	smart-4dd68a7c-e23a-40ac-bca5-f5d849160681
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584069319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3584069319
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.1389126478
Short name	T1200
Test name
Test status
Simulation time	17903742 ps
CPU time	0.57 seconds
Started	Mar 10 12:24:06 PM PDT 24
Finished	Mar 10 12:24:07 PM PDT 24
Peak memory	194588 kb
Host	smart-bf49069f-0b89-437d-a815-9435218eba90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389126478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1389126478
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.3433825423
Short name	T1182
Test name
Test status
Simulation time	23945487 ps
CPU time	0.61 seconds
Started	Mar 10 12:27:30 PM PDT 24
Finished	Mar 10 12:27:30 PM PDT 24
Peak memory	194708 kb
Host	smart-26bc2cb2-9a66-48c0-9e8d-155a7a3b4658
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433825423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3433825423
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.4223281594
Short name	T1136
Test name
Test status
Simulation time	15285266 ps
CPU time	0.57 seconds
Started	Mar 10 12:24:06 PM PDT 24
Finished	Mar 10 12:24:07 PM PDT 24
Peak memory	194376 kb
Host	smart-aa299819-ae86-4a4e-9cf6-d7d4a78b532f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223281594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4223281594
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.50626995
Short name	T1141
Test name
Test status
Simulation time	16247334 ps
CPU time	0.57 seconds
Started	Mar 10 12:24:06 PM PDT 24
Finished	Mar 10 12:24:07 PM PDT 24
Peak memory	194388 kb
Host	smart-64d135a1-aabf-4901-afa6-a46d7638d560
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50626995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.50626995
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.1081092541
Short name	T1158
Test name
Test status
Simulation time	10831026 ps
CPU time	0.6 seconds
Started	Mar 10 12:24:06 PM PDT 24
Finished	Mar 10 12:24:07 PM PDT 24
Peak memory	194588 kb
Host	smart-a61abb16-3d33-45d5-826a-7a48b4c50ef3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081092541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1081092541
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.1070790395
Short name	T1232
Test name
Test status
Simulation time	157934286 ps
CPU time	0.55 seconds
Started	Mar 10 12:27:33 PM PDT 24
Finished	Mar 10 12:27:34 PM PDT 24
Peak memory	194708 kb
Host	smart-32fe5a73-874c-406b-ae95-47ef64c8535c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070790395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1070790395
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.861003451
Short name	T1206
Test name
Test status
Simulation time	23102889 ps
CPU time	0.58 seconds
Started	Mar 10 12:21:29 PM PDT 24
Finished	Mar 10 12:21:30 PM PDT 24
Peak memory	194712 kb
Host	smart-1d1457cf-9331-4374-8065-95cf068d67be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861003451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.861003451
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.505491469
Short name	T1253
Test name
Test status
Simulation time	33394531 ps
CPU time	0.52 seconds
Started	Mar 10 12:27:20 PM PDT 24
Finished	Mar 10 12:27:22 PM PDT 24
Peak memory	194680 kb
Host	smart-0524ed2b-2584-4fcf-99a3-2851fb57c514
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505491469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.505491469
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.1950184011
Short name	T1225
Test name
Test status
Simulation time	80050686 ps
CPU time	0.62 seconds
Started	Mar 10 12:23:55 PM PDT 24
Finished	Mar 10 12:23:57 PM PDT 24
Peak memory	193040 kb
Host	smart-08ad762a-9b6e-4fb7-9ca1-873e130ca178
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950184011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1950184011
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1926095536
Short name	T1142
Test name
Test status
Simulation time	58188716 ps
CPU time	0.65 seconds
Started	Mar 10 12:33:57 PM PDT 24
Finished	Mar 10 12:33:58 PM PDT 24
Peak memory	195128 kb
Host	smart-17e846ae-60a0-44c4-a255-dcc48a15340c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926095536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1926095536
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3045265104
Short name	T1248
Test name
Test status
Simulation time	134079584 ps
CPU time	1.59 seconds
Started	Mar 10 12:21:32 PM PDT 24
Finished	Mar 10 12:21:34 PM PDT 24
Peak memory	198000 kb
Host	smart-7469afb1-f3f7-44f6-a715-8facb345febd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045265104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3045265104
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2100274335
Short name	T1234
Test name
Test status
Simulation time	1043798722 ps
CPU time	1.3 seconds
Started	Mar 10 12:33:43 PM PDT 24
Finished	Mar 10 12:33:45 PM PDT 24
Peak memory	195872 kb
Host	smart-3b839387-b57a-4fc0-81c9-190ce8454e3a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100274335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2100274335
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2182730385
Short name	T1236
Test name
Test status
Simulation time	45596189 ps
CPU time	1.06 seconds
Started	Mar 10 12:26:40 PM PDT 24
Finished	Mar 10 12:26:41 PM PDT 24
Peak memory	200352 kb
Host	smart-0c0d5eda-fe06-4558-a84d-97ca530fb166
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182730385 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2182730385
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.526310478
Short name	T67
Test name
Test status
Simulation time	13922678 ps
CPU time	0.62 seconds
Started	Mar 10 12:33:47 PM PDT 24
Finished	Mar 10 12:33:48 PM PDT 24
Peak memory	195796 kb
Host	smart-65404fd5-93bd-4ae2-b7f9-b6222e66f119
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526310478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.526310478
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.2946314535
Short name	T1211
Test name
Test status
Simulation time	23238527 ps
CPU time	0.59 seconds
Started	Mar 10 12:33:50 PM PDT 24
Finished	Mar 10 12:33:51 PM PDT 24
Peak memory	194668 kb
Host	smart-f5e24c99-c395-40cb-be1a-23e89e10effc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946314535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2946314535
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.135913307
Short name	T1190
Test name
Test status
Simulation time	25382452 ps
CPU time	0.7 seconds
Started	Mar 10 12:21:21 PM PDT 24
Finished	Mar 10 12:21:22 PM PDT 24
Peak memory	196120 kb
Host	smart-a2b67ea0-5948-486c-80e9-2b85417a1f1e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135913307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_ outstanding.135913307
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.1598963612
Short name	T1192
Test name
Test status
Simulation time	165315227 ps
CPU time	1.53 seconds
Started	Mar 10 12:32:22 PM PDT 24
Finished	Mar 10 12:32:24 PM PDT 24
Peak memory	200264 kb
Host	smart-5e4df668-98c2-4843-a699-56f4de5b5d2b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598963612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1598963612
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2607883826
Short name	T1194
Test name
Test status
Simulation time	194276808 ps
CPU time	0.94 seconds
Started	Mar 10 12:27:03 PM PDT 24
Finished	Mar 10 12:27:09 PM PDT 24
Peak memory	199116 kb
Host	smart-cfed25a6-40bb-4f88-b6c9-bdda046eae04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607883826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2607883826
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.3094205736
Short name	T1219
Test name
Test status
Simulation time	15659090 ps
CPU time	0.57 seconds
Started	Mar 10 12:24:11 PM PDT 24
Finished	Mar 10 12:24:12 PM PDT 24
Peak memory	194548 kb
Host	smart-1b1cadfa-1885-4fa2-96dc-916aecc20842
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094205736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3094205736
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.3035859850
Short name	T1183
Test name
Test status
Simulation time	63163425 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:10 PM PDT 24
Finished	Mar 10 12:24:11 PM PDT 24
Peak memory	194620 kb
Host	smart-e0c01aec-891f-42e4-af25-ff7be663c952
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035859850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3035859850
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.2224134634
Short name	T1199
Test name
Test status
Simulation time	49453903 ps
CPU time	0.56 seconds
Started	Mar 10 12:21:38 PM PDT 24
Finished	Mar 10 12:21:39 PM PDT 24
Peak memory	194504 kb
Host	smart-dcfcdfbd-5249-44e5-bfc6-078aa7cf4f56
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224134634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2224134634
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.3650284444
Short name	T1157
Test name
Test status
Simulation time	27113234 ps
CPU time	0.69 seconds
Started	Mar 10 12:21:36 PM PDT 24
Finished	Mar 10 12:21:37 PM PDT 24
Peak memory	194664 kb
Host	smart-654dc64e-0966-47ab-8cda-1910362f368a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650284444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3650284444
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.1345501223
Short name	T1210
Test name
Test status
Simulation time	16305426 ps
CPU time	0.61 seconds
Started	Mar 10 12:24:11 PM PDT 24
Finished	Mar 10 12:24:12 PM PDT 24
Peak memory	194516 kb
Host	smart-c41a5491-6404-475d-970b-4f9dd610963d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345501223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1345501223
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.2387528347
Short name	T1247
Test name
Test status
Simulation time	42323717 ps
CPU time	0.56 seconds
Started	Mar 10 12:21:46 PM PDT 24
Finished	Mar 10 12:21:48 PM PDT 24
Peak memory	194716 kb
Host	smart-4b3e8f66-ac91-42d3-943f-2f12bded37ea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387528347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2387528347
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.1039201884
Short name	T1155
Test name
Test status
Simulation time	20648382 ps
CPU time	0.58 seconds
Started	Mar 10 12:24:11 PM PDT 24
Finished	Mar 10 12:24:12 PM PDT 24
Peak memory	194624 kb
Host	smart-d93ec96a-9958-4a2a-83be-03ce46a9e9e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039201884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1039201884
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.3471802365
Short name	T1223
Test name
Test status
Simulation time	13470155 ps
CPU time	0.57 seconds
Started	Mar 10 12:21:33 PM PDT 24
Finished	Mar 10 12:21:34 PM PDT 24
Peak memory	194720 kb
Host	smart-87f85ec9-c6b5-4765-a0c2-5144cb43da78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471802365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3471802365
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.1437719807
Short name	T1152
Test name
Test status
Simulation time	23497865 ps
CPU time	0.63 seconds
Started	Mar 10 12:23:55 PM PDT 24
Finished	Mar 10 12:23:57 PM PDT 24
Peak memory	193032 kb
Host	smart-3e5702de-a308-4ce4-b1dd-f82f057b1122
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437719807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1437719807
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.502215251
Short name	T1181
Test name
Test status
Simulation time	19848465 ps
CPU time	0.57 seconds
Started	Mar 10 12:21:34 PM PDT 24
Finished	Mar 10 12:21:34 PM PDT 24
Peak memory	194704 kb
Host	smart-2b9ec4b6-1a96-433c-a24c-95989cd6b172
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502215251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.502215251
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.358249238
Short name	T1191
Test name
Test status
Simulation time	32281828 ps
CPU time	0.62 seconds
Started	Mar 10 12:24:23 PM PDT 24
Finished	Mar 10 12:24:24 PM PDT 24
Peak memory	197812 kb
Host	smart-a8c814e4-c61e-4b9f-8c1e-d7de8804ba90
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358249238 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.358249238
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.4147789627
Short name	T1255
Test name
Test status
Simulation time	38690387 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:24 PM PDT 24
Finished	Mar 10 12:24:25 PM PDT 24
Peak memory	195724 kb
Host	smart-1235d26e-ca31-42bd-91ed-6d32359944be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147789627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4147789627
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.2636507099
Short name	T1172
Test name
Test status
Simulation time	53949317 ps
CPU time	0.55 seconds
Started	Mar 10 12:23:25 PM PDT 24
Finished	Mar 10 12:23:26 PM PDT 24
Peak memory	194684 kb
Host	smart-68f99bc5-2396-41fa-bae5-56d563c7241e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636507099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2636507099
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3202078485
Short name	T1198
Test name
Test status
Simulation time	41982872 ps
CPU time	0.75 seconds
Started	Mar 10 12:26:22 PM PDT 24
Finished	Mar 10 12:26:24 PM PDT 24
Peak memory	195080 kb
Host	smart-d4f871a7-d07a-4e45-83bf-ed4f9686cf41
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202078485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.3202078485
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.968966756
Short name	T1160
Test name
Test status
Simulation time	102249502 ps
CPU time	1.81 seconds
Started	Mar 10 12:23:10 PM PDT 24
Finished	Mar 10 12:23:12 PM PDT 24
Peak memory	200188 kb
Host	smart-ac5eb958-60e4-4f2e-a2b7-882d1ef84af1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968966756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.968966756
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4116294194
Short name	T90
Test name
Test status
Simulation time	146252637 ps
CPU time	0.93 seconds
Started	Mar 10 12:18:18 PM PDT 24
Finished	Mar 10 12:18:19 PM PDT 24
Peak memory	199060 kb
Host	smart-0b48c2c4-197d-4ce5-89da-4e1fd2eaf3fa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116294194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4116294194
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1408198895
Short name	T1186
Test name
Test status
Simulation time	30264769 ps
CPU time	0.82 seconds
Started	Mar 10 12:33:10 PM PDT 24
Finished	Mar 10 12:33:11 PM PDT 24
Peak memory	200136 kb
Host	smart-45e3fe2f-119a-4103-b7eb-a4910a30810b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408198895 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1408198895
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.1375977280
Short name	T61
Test name
Test status
Simulation time	61561082 ps
CPU time	0.56 seconds
Started	Mar 10 12:29:35 PM PDT 24
Finished	Mar 10 12:29:35 PM PDT 24
Peak memory	195808 kb
Host	smart-50739547-8cfc-4c96-9361-2aebab83765e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375977280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1375977280
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.3213999827
Short name	T1218
Test name
Test status
Simulation time	28677209 ps
CPU time	0.59 seconds
Started	Mar 10 12:21:03 PM PDT 24
Finished	Mar 10 12:21:04 PM PDT 24
Peak memory	194404 kb
Host	smart-d4df03da-5aed-4bc3-88af-ffa134208d27
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213999827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3213999827
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1493321064
Short name	T72
Test name
Test status
Simulation time	28357305 ps
CPU time	0.72 seconds
Started	Mar 10 12:20:06 PM PDT 24
Finished	Mar 10 12:20:07 PM PDT 24
Peak memory	197160 kb
Host	smart-097593b7-7cce-4840-a16b-da5ecaa5392e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493321064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.1493321064
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.3457575335
Short name	T1128
Test name
Test status
Simulation time	68793362 ps
CPU time	1.44 seconds
Started	Mar 10 12:24:11 PM PDT 24
Finished	Mar 10 12:24:13 PM PDT 24
Peak memory	198716 kb
Host	smart-d54e5c08-124f-41b0-942e-3b0160ef1561
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457575335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3457575335
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3122720790
Short name	T88
Test name
Test status
Simulation time	60614548 ps
CPU time	0.96 seconds
Started	Mar 10 12:21:03 PM PDT 24
Finished	Mar 10 12:21:04 PM PDT 24
Peak memory	198840 kb
Host	smart-f5da04c4-8c87-41a9-82ea-cc568e87a827
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122720790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3122720790
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2639515710
Short name	T1252
Test name
Test status
Simulation time	27425994 ps
CPU time	1.19 seconds
Started	Mar 10 12:20:48 PM PDT 24
Finished	Mar 10 12:20:50 PM PDT 24
Peak memory	200304 kb
Host	smart-c3ce6f6c-1a7f-4dfa-a69c-9ffa4de2f668
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639515710 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2639515710
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.3262886280
Short name	T65
Test name
Test status
Simulation time	46970515 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:24 PM PDT 24
Finished	Mar 10 12:24:24 PM PDT 24
Peak memory	195740 kb
Host	smart-0c571130-1757-4c33-a515-dfdef41c77f9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262886280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3262886280
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.3870319846
Short name	T1228
Test name
Test status
Simulation time	16161256 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:23 PM PDT 24
Finished	Mar 10 12:24:24 PM PDT 24
Peak memory	194652 kb
Host	smart-770f5c06-97e2-4308-8d92-ea4abc808f6b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870319846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3870319846
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4215986815
Short name	T1180
Test name
Test status
Simulation time	153964939 ps
CPU time	0.65 seconds
Started	Mar 10 12:19:05 PM PDT 24
Finished	Mar 10 12:19:06 PM PDT 24
Peak memory	195748 kb
Host	smart-81c7fbaf-6cc5-49a8-a5db-37a9ede6a2af
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215986815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.4215986815
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.237699586
Short name	T1203
Test name
Test status
Simulation time	42602667 ps
CPU time	1.07 seconds
Started	Mar 10 12:24:28 PM PDT 24
Finished	Mar 10 12:24:29 PM PDT 24
Peak memory	200040 kb
Host	smart-47185810-0ce6-42f5-88e1-dc1f1372e801
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237699586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.237699586
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3096033933
Short name	T87
Test name
Test status
Simulation time	273488172 ps
CPU time	1.28 seconds
Started	Mar 10 12:24:12 PM PDT 24
Finished	Mar 10 12:24:14 PM PDT 24
Peak memory	197616 kb
Host	smart-86f57202-570e-4e99-b2c1-2fc261826470
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096033933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3096033933
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1862572752
Short name	T1165
Test name
Test status
Simulation time	18935032 ps
CPU time	0.85 seconds
Started	Mar 10 12:19:52 PM PDT 24
Finished	Mar 10 12:19:53 PM PDT 24
Peak memory	200180 kb
Host	smart-5481e912-d35c-4ed4-92ed-9ef5878a12e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862572752 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1862572752
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.4230066214
Short name	T1229
Test name
Test status
Simulation time	25344120 ps
CPU time	0.58 seconds
Started	Mar 10 12:33:53 PM PDT 24
Finished	Mar 10 12:33:54 PM PDT 24
Peak memory	195740 kb
Host	smart-e474a777-287f-4aa4-bf21-c71cbf001c24
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230066214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.4230066214
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.2177369647
Short name	T1176
Test name
Test status
Simulation time	14937970 ps
CPU time	0.59 seconds
Started	Mar 10 12:27:30 PM PDT 24
Finished	Mar 10 12:27:31 PM PDT 24
Peak memory	194608 kb
Host	smart-021ac0a1-f57c-4075-b54c-2dd242499c53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177369647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2177369647
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4115657525
Short name	T1166
Test name
Test status
Simulation time	90391516 ps
CPU time	0.62 seconds
Started	Mar 10 12:27:06 PM PDT 24
Finished	Mar 10 12:27:06 PM PDT 24
Peak memory	194280 kb
Host	smart-f0b74ebf-00ec-497d-811c-633a366f075b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115657525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.4115657525
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.887768983
Short name	T1231
Test name
Test status
Simulation time	118971538 ps
CPU time	1.49 seconds
Started	Mar 10 12:29:34 PM PDT 24
Finished	Mar 10 12:29:35 PM PDT 24
Peak memory	200436 kb
Host	smart-3de853fc-a191-4a48-8dc8-e9b67dfb7c47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887768983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.887768983
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4233853325
Short name	T1224
Test name
Test status
Simulation time	113569339 ps
CPU time	1.27 seconds
Started	Mar 10 12:24:23 PM PDT 24
Finished	Mar 10 12:24:25 PM PDT 24
Peak memory	199372 kb
Host	smart-cb698ecf-29a3-431f-b4b0-2322e7861004
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233853325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4233853325
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2609175421
Short name	T1156
Test name
Test status
Simulation time	12849896 ps
CPU time	0.66 seconds
Started	Mar 10 12:24:57 PM PDT 24
Finished	Mar 10 12:24:58 PM PDT 24
Peak memory	198108 kb
Host	smart-0353801b-726e-4248-9ff5-6e2df0068f15
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609175421 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2609175421
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.1937152073
Short name	T64
Test name
Test status
Simulation time	40942919 ps
CPU time	0.58 seconds
Started	Mar 10 12:24:01 PM PDT 24
Finished	Mar 10 12:24:01 PM PDT 24
Peak memory	195672 kb
Host	smart-9962f02f-929f-4fb5-b667-9c9e3551c2a1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937152073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1937152073
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.38472590
Short name	T1188
Test name
Test status
Simulation time	18878720 ps
CPU time	0.55 seconds
Started	Mar 10 12:24:56 PM PDT 24
Finished	Mar 10 12:24:58 PM PDT 24
Peak memory	194672 kb
Host	smart-6c54f4bf-b45f-4f5e-8809-f82d3cf1e66c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38472590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.38472590
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.799422850
Short name	T1222
Test name
Test status
Simulation time	177110528 ps
CPU time	0.74 seconds
Started	Mar 10 12:33:54 PM PDT 24
Finished	Mar 10 12:33:55 PM PDT 24
Peak memory	196252 kb
Host	smart-6be974a6-eaff-49af-8341-88f1e26d2fd3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799422850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_ outstanding.799422850
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.1973515290
Short name	T1140
Test name
Test status
Simulation time	318359258 ps
CPU time	1.35 seconds
Started	Mar 10 12:33:53 PM PDT 24
Finished	Mar 10 12:33:56 PM PDT 24
Peak memory	200312 kb
Host	smart-5f43d8f4-2512-4e15-9310-fa4a4589f306
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973515290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1973515290
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3871458350
Short name	T85
Test name
Test status
Simulation time	93325002 ps
CPU time	1.28 seconds
Started	Mar 10 12:24:57 PM PDT 24
Finished	Mar 10 12:24:59 PM PDT 24
Peak memory	199468 kb
Host	smart-aacbd070-6097-4eb1-a946-f611d644240a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871458350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3871458350
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_alert_test.4095213164
Short name	T509
Test name
Test status
Simulation time	13769187 ps
CPU time	0.57 seconds
Started	Mar 10 12:48:02 PM PDT 24
Finished	Mar 10 12:48:05 PM PDT 24
Peak memory	195500 kb
Host	smart-685f9f23-1b63-43a7-865a-4ec2950e3b38
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095213164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.4095213164
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.2932519306
Short name	T927
Test name
Test status
Simulation time	9961422901 ps
CPU time	17.21 seconds
Started	Mar 10 12:47:50 PM PDT 24
Finished	Mar 10 12:48:07 PM PDT 24
Peak memory	199692 kb
Host	smart-7ae04990-bcac-4e7f-94b2-98d322080237
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932519306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2932519306
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.1106890837
Short name	T851
Test name
Test status
Simulation time	24206807147 ps
CPU time	37.65 seconds
Started	Mar 10 12:47:50 PM PDT 24
Finished	Mar 10 12:48:28 PM PDT 24
Peak memory	200124 kb
Host	smart-ad655e8f-c4ae-481c-b436-565b5040c4be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106890837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1106890837
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_intr.2807441926
Short name	T584
Test name
Test status
Simulation time	19084441731 ps
CPU time	35.37 seconds
Started	Mar 10 12:47:50 PM PDT 24
Finished	Mar 10 12:48:25 PM PDT 24
Peak memory	199560 kb
Host	smart-677f0ee6-f0ad-42ab-8bc7-455595772269
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807441926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2807441926
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.3100059064
Short name	T677
Test name
Test status
Simulation time	50740275824 ps
CPU time	414.59 seconds
Started	Mar 10 12:48:03 PM PDT 24
Finished	Mar 10 12:54:59 PM PDT 24
Peak memory	200200 kb
Host	smart-738ae36f-7de9-49a5-bf73-0568afba7a47
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3100059064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3100059064
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/0.uart_loopback.1503400028
Short name	T720
Test name
Test status
Simulation time	6925623541 ps
CPU time	20.25 seconds
Started	Mar 10 12:47:58 PM PDT 24
Finished	Mar 10 12:48:18 PM PDT 24
Peak memory	199388 kb
Host	smart-b43999f0-672a-4121-ade5-59cd9c825d4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503400028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1503400028
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.3754617621
Short name	T393
Test name
Test status
Simulation time	64837582944 ps
CPU time	55.2 seconds
Started	Mar 10 12:47:56 PM PDT 24
Finished	Mar 10 12:48:52 PM PDT 24
Peak memory	200068 kb
Host	smart-2b4d211f-86b8-4fb3-9f11-7e13945b3b1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754617621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3754617621
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.2505685488
Short name	T384
Test name
Test status
Simulation time	38130017059 ps
CPU time	1832.59 seconds
Started	Mar 10 12:48:03 PM PDT 24
Finished	Mar 10 01:18:37 PM PDT 24
Peak memory	200088 kb
Host	smart-96c6e91c-1c73-49d9-a256-089ccf18ef81
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2505685488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2505685488
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.707015005
Short name	T534
Test name
Test status
Simulation time	6687606864 ps
CPU time	32.52 seconds
Started	Mar 10 12:47:50 PM PDT 24
Finished	Mar 10 12:48:23 PM PDT 24
Peak memory	198704 kb
Host	smart-fa68ec10-e84e-4735-9db4-31d7fe363150
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=707015005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.707015005
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.705088944
Short name	T577
Test name
Test status
Simulation time	73448801070 ps
CPU time	22.06 seconds
Started	Mar 10 12:47:58 PM PDT 24
Finished	Mar 10 12:48:20 PM PDT 24
Peak memory	200200 kb
Host	smart-b5fd9840-213d-41d1-aabe-4afaca9ecc3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705088944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.705088944
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.1356315731
Short name	T890
Test name
Test status
Simulation time	3333508578 ps
CPU time	2.14 seconds
Started	Mar 10 12:47:57 PM PDT 24
Finished	Mar 10 12:47:59 PM PDT 24
Peak memory	195916 kb
Host	smart-9cd60af3-fd12-47c4-bc46-0505102741aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356315731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1356315731
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_smoke.1608009866
Short name	T421
Test name
Test status
Simulation time	1022801268 ps
CPU time	1.23 seconds
Started	Mar 10 12:47:52 PM PDT 24
Finished	Mar 10 12:47:53 PM PDT 24
Peak memory	198036 kb
Host	smart-04e895c6-75cb-4e2d-8ede-fc321635cbc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608009866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1608009866
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_stress_all_with_rand_reset.487921051
Short name	T35
Test name
Test status
Simulation time	225004085444 ps
CPU time	679.59 seconds
Started	Mar 10 12:48:08 PM PDT 24
Finished	Mar 10 12:59:29 PM PDT 24
Peak memory	216588 kb
Host	smart-7fbc3850-07cd-45c7-8d7a-2e7e62a55138
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487921051 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.487921051
Directory	/workspace/0.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.2220744034
Short name	T1096
Test name
Test status
Simulation time	538841589 ps
CPU time	1.81 seconds
Started	Mar 10 12:47:58 PM PDT 24
Finished	Mar 10 12:47:59 PM PDT 24
Peak memory	198288 kb
Host	smart-a1d44892-221a-4f65-921c-699408f2e0c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220744034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2220744034
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.1411348663
Short name	T647
Test name
Test status
Simulation time	25678758174 ps
CPU time	47.3 seconds
Started	Mar 10 12:47:51 PM PDT 24
Finished	Mar 10 12:48:38 PM PDT 24
Peak memory	200000 kb
Host	smart-78998e70-fcc4-48f3-a7a1-c0981bf6836a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411348663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1411348663
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.2608752413
Short name	T4
Test name
Test status
Simulation time	39792612990 ps
CPU time	19.68 seconds
Started	Mar 10 12:48:08 PM PDT 24
Finished	Mar 10 12:48:29 PM PDT 24
Peak memory	200168 kb
Host	smart-afaee00a-d9de-4ff3-a0e2-4f95dedd7417
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608752413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2608752413
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.2556706628
Short name	T1029
Test name
Test status
Simulation time	149845741223 ps
CPU time	220.43 seconds
Started	Mar 10 12:48:09 PM PDT 24
Finished	Mar 10 12:51:50 PM PDT 24
Peak memory	200088 kb
Host	smart-e45f0fec-ed16-470d-b6d6-b8f99233eacb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556706628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2556706628
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.1208681427
Short name	T531
Test name
Test status
Simulation time	61803450296 ps
CPU time	26.02 seconds
Started	Mar 10 12:48:08 PM PDT 24
Finished	Mar 10 12:48:35 PM PDT 24
Peak memory	198084 kb
Host	smart-73ede938-da11-4ccf-893e-d9ec478f2264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208681427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1208681427
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_intr.2791634109
Short name	T814
Test name
Test status
Simulation time	1091406807878 ps
CPU time	1860.4 seconds
Started	Mar 10 12:48:08 PM PDT 24
Finished	Mar 10 01:19:10 PM PDT 24
Peak memory	198652 kb
Host	smart-1727c254-e2fd-4179-9da4-4df03dee4520
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791634109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2791634109
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.2939303042
Short name	T529
Test name
Test status
Simulation time	97866119888 ps
CPU time	280.76 seconds
Started	Mar 10 12:48:15 PM PDT 24
Finished	Mar 10 12:52:55 PM PDT 24
Peak memory	200116 kb
Host	smart-7b05dd7b-c81f-4a59-8ef2-443312c34a20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2939303042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2939303042
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.2826961160
Short name	T602
Test name
Test status
Simulation time	4267431033 ps
CPU time	2.06 seconds
Started	Mar 10 12:48:13 PM PDT 24
Finished	Mar 10 12:48:15 PM PDT 24
Peak memory	198696 kb
Host	smart-d15215b4-fb2c-4db5-8d05-acfc16fbe0e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826961160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2826961160
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_perf.1066007988
Short name	T691
Test name
Test status
Simulation time	21172239345 ps
CPU time	127.93 seconds
Started	Mar 10 12:48:13 PM PDT 24
Finished	Mar 10 12:50:21 PM PDT 24
Peak memory	200072 kb
Host	smart-1c630de8-5e23-4119-97f5-798a9e91630f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1066007988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1066007988
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.702719613
Short name	T525
Test name
Test status
Simulation time	4759930785 ps
CPU time	34.92 seconds
Started	Mar 10 12:48:10 PM PDT 24
Finished	Mar 10 12:48:45 PM PDT 24
Peak memory	198564 kb
Host	smart-d4ac8dab-4b58-4b88-9d5a-cd6aa83f8e58
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=702719613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.702719613
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.3433730192
Short name	T714
Test name
Test status
Simulation time	13738372369 ps
CPU time	11.64 seconds
Started	Mar 10 12:48:14 PM PDT 24
Finished	Mar 10 12:48:26 PM PDT 24
Peak memory	199312 kb
Host	smart-469070fd-bf08-458b-bb0d-0d525a7590bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433730192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3433730192
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.2944815377
Short name	T805
Test name
Test status
Simulation time	3938125982 ps
CPU time	7.2 seconds
Started	Mar 10 12:48:09 PM PDT 24
Finished	Mar 10 12:48:16 PM PDT 24
Peak memory	195936 kb
Host	smart-7838fbbb-2985-465c-8fc8-4273c4eebb86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944815377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2944815377
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.3407082418
Short name	T30
Test name
Test status
Simulation time	34366435 ps
CPU time	0.77 seconds
Started	Mar 10 12:48:14 PM PDT 24
Finished	Mar 10 12:48:15 PM PDT 24
Peak memory	217384 kb
Host	smart-bf057c40-c668-4440-a71f-edf199a9f61c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407082418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3407082418
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/1.uart_smoke.1454592575
Short name	T743
Test name
Test status
Simulation time	347481868 ps
CPU time	1.27 seconds
Started	Mar 10 12:48:03 PM PDT 24
Finished	Mar 10 12:48:06 PM PDT 24
Peak memory	199088 kb
Host	smart-e26608b3-3ceb-4a3b-85b1-68d87a3225e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454592575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1454592575
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.3354901326
Short name	T830
Test name
Test status
Simulation time	674430443 ps
CPU time	2.12 seconds
Started	Mar 10 12:48:13 PM PDT 24
Finished	Mar 10 12:48:15 PM PDT 24
Peak memory	198484 kb
Host	smart-424f0f74-3dff-41a8-b68f-7286274659d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354901326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3354901326
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.792180553
Short name	T796
Test name
Test status
Simulation time	14914968223 ps
CPU time	16.75 seconds
Started	Mar 10 12:48:08 PM PDT 24
Finished	Mar 10 12:48:26 PM PDT 24
Peak memory	200056 kb
Host	smart-7c23490a-6aa9-4793-9d2f-6257448b963c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792180553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.792180553
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_alert_test.2023979456
Short name	T1112
Test name
Test status
Simulation time	21784601 ps
CPU time	0.56 seconds
Started	Mar 10 12:50:01 PM PDT 24
Finished	Mar 10 12:50:03 PM PDT 24
Peak memory	195372 kb
Host	smart-e2568472-a770-4ad4-a8ac-e248f7e6e67d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023979456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2023979456
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.40834863
Short name	T225
Test name
Test status
Simulation time	4263500686 ps
CPU time	7.67 seconds
Started	Mar 10 12:49:56 PM PDT 24
Finished	Mar 10 12:50:06 PM PDT 24
Peak memory	199496 kb
Host	smart-85ab8036-2e90-44d7-bd1c-9b83cba5155f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40834863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.40834863
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_intr.1606297844
Short name	T1007
Test name
Test status
Simulation time	182624888168 ps
CPU time	102.69 seconds
Started	Mar 10 12:49:56 PM PDT 24
Finished	Mar 10 12:51:39 PM PDT 24
Peak memory	200116 kb
Host	smart-1f59d567-8b81-48af-bf08-40753c49ca7d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606297844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1606297844
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.1046294967
Short name	T931
Test name
Test status
Simulation time	138610520054 ps
CPU time	613.59 seconds
Started	Mar 10 12:50:01 PM PDT 24
Finished	Mar 10 01:00:16 PM PDT 24
Peak memory	199956 kb
Host	smart-6aa06a6c-78ae-4932-a197-91fafd0afabd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1046294967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1046294967
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.2143357991
Short name	T843
Test name
Test status
Simulation time	4637616266 ps
CPU time	4.79 seconds
Started	Mar 10 12:50:02 PM PDT 24
Finished	Mar 10 12:50:08 PM PDT 24
Peak memory	198272 kb
Host	smart-abf2158c-df3c-4007-bd83-de5e25d93789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143357991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2143357991
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_perf.3651348616
Short name	T1089
Test name
Test status
Simulation time	11982695070 ps
CPU time	588.67 seconds
Started	Mar 10 12:50:03 PM PDT 24
Finished	Mar 10 12:59:53 PM PDT 24
Peak memory	200140 kb
Host	smart-c7e1b418-6079-4921-8a92-f859490c55d9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3651348616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3651348616
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.552638626
Short name	T861
Test name
Test status
Simulation time	3136155897 ps
CPU time	20.95 seconds
Started	Mar 10 12:49:56 PM PDT 24
Finished	Mar 10 12:50:18 PM PDT 24
Peak memory	198156 kb
Host	smart-39a98e07-2d56-4225-aa17-b816e8a61194
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=552638626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.552638626
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.2647985125
Short name	T359
Test name
Test status
Simulation time	141550425088 ps
CPU time	53.41 seconds
Started	Mar 10 12:49:56 PM PDT 24
Finished	Mar 10 12:50:49 PM PDT 24
Peak memory	200004 kb
Host	smart-bfa9ee97-5a4f-40fe-baa0-e9612d066802
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647985125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2647985125
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.4120495583
Short name	T1041
Test name
Test status
Simulation time	4065856579 ps
CPU time	2.01 seconds
Started	Mar 10 12:49:55 PM PDT 24
Finished	Mar 10 12:49:57 PM PDT 24
Peak memory	195744 kb
Host	smart-e0a227cb-b02e-4178-80a4-a14149cbc951
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120495583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.4120495583
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.2980938683
Short name	T776
Test name
Test status
Simulation time	273003290 ps
CPU time	1.29 seconds
Started	Mar 10 12:49:52 PM PDT 24
Finished	Mar 10 12:49:53 PM PDT 24
Peak memory	198124 kb
Host	smart-10e84204-6aee-43b5-9286-956d6adbd7b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980938683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2980938683
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_stress_all.1209627923
Short name	T628
Test name
Test status
Simulation time	577338342520 ps
CPU time	778.8 seconds
Started	Mar 10 12:50:01 PM PDT 24
Finished	Mar 10 01:03:01 PM PDT 24
Peak memory	215900 kb
Host	smart-3d03f948-57bd-4553-8aee-5b5911161743
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209627923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1209627923
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.536884999
Short name	T599
Test name
Test status
Simulation time	5624975912 ps
CPU time	1.96 seconds
Started	Mar 10 12:49:56 PM PDT 24
Finished	Mar 10 12:49:58 PM PDT 24
Peak memory	199244 kb
Host	smart-6de814d9-3315-48f6-bd70-f8ead71fc187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536884999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.536884999
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.1943411166
Short name	T409
Test name
Test status
Simulation time	45873057145 ps
CPU time	40.54 seconds
Started	Mar 10 12:49:50 PM PDT 24
Finished	Mar 10 12:50:31 PM PDT 24
Peak memory	200040 kb
Host	smart-83ca4e91-7642-45b2-8c03-7dc6723cc0c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943411166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1943411166
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.3654976780
Short name	T153
Test name
Test status
Simulation time	36760124452 ps
CPU time	11.96 seconds
Started	Mar 10 12:57:21 PM PDT 24
Finished	Mar 10 12:57:33 PM PDT 24
Peak memory	200160 kb
Host	smart-80ddf562-a11b-4e84-aa97-900a6fcede12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654976780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3654976780
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.3211163088
Short name	T902
Test name
Test status
Simulation time	85172846299 ps
CPU time	162.67 seconds
Started	Mar 10 12:57:21 PM PDT 24
Finished	Mar 10 01:00:03 PM PDT 24
Peak memory	200196 kb
Host	smart-5ea71e40-603f-4b8e-bfc0-145d45f0d18e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211163088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3211163088
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.2632830630
Short name	T259
Test name
Test status
Simulation time	8845741808 ps
CPU time	14.36 seconds
Started	Mar 10 12:57:27 PM PDT 24
Finished	Mar 10 12:57:41 PM PDT 24
Peak memory	200068 kb
Host	smart-563e86a5-8133-4dba-af4a-a8fcc5ef66ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632830630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2632830630
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.624728333
Short name	T669
Test name
Test status
Simulation time	232966828912 ps
CPU time	191.37 seconds
Started	Mar 10 12:57:28 PM PDT 24
Finished	Mar 10 01:00:39 PM PDT 24
Peak memory	200104 kb
Host	smart-ceeac7d6-c023-45bf-a217-dda647fbc5f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624728333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.624728333
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.2823146285
Short name	T454
Test name
Test status
Simulation time	18194622 ps
CPU time	0.55 seconds
Started	Mar 10 12:50:13 PM PDT 24
Finished	Mar 10 12:50:14 PM PDT 24
Peak memory	194460 kb
Host	smart-bc5bcc91-2004-4907-a3cd-0ce3163f22a9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823146285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2823146285
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.380498132
Short name	T1015
Test name
Test status
Simulation time	34261173182 ps
CPU time	69.78 seconds
Started	Mar 10 12:50:01 PM PDT 24
Finished	Mar 10 12:51:13 PM PDT 24
Peak memory	200168 kb
Host	smart-bd98dd92-1565-4751-ba97-1e01072942d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380498132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.380498132
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.666523945
Short name	T301
Test name
Test status
Simulation time	163533560315 ps
CPU time	71.04 seconds
Started	Mar 10 12:50:03 PM PDT 24
Finished	Mar 10 12:51:15 PM PDT 24
Peak memory	200016 kb
Host	smart-3453717b-434a-4298-87d9-810f1b0cf609
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666523945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.666523945
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.1686294053
Short name	T182
Test name
Test status
Simulation time	14358726977 ps
CPU time	12.2 seconds
Started	Mar 10 12:50:07 PM PDT 24
Finished	Mar 10 12:50:20 PM PDT 24
Peak memory	200136 kb
Host	smart-b18a35cc-ef28-410c-b937-ffbbeb6e57e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686294053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1686294053
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_intr.2503242107
Short name	T757
Test name
Test status
Simulation time	208619880582 ps
CPU time	354.47 seconds
Started	Mar 10 12:50:08 PM PDT 24
Finished	Mar 10 12:56:03 PM PDT 24
Peak memory	200108 kb
Host	smart-66b4bcf7-810a-4090-8e0f-733f7010b9de
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503242107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2503242107
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.2904274755
Short name	T447
Test name
Test status
Simulation time	134449922791 ps
CPU time	405.85 seconds
Started	Mar 10 12:50:11 PM PDT 24
Finished	Mar 10 12:56:57 PM PDT 24
Peak memory	200044 kb
Host	smart-56a3cd92-e56b-469e-9add-c513bba76a41
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2904274755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2904274755
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.705204353
Short name	T772
Test name
Test status
Simulation time	9669279239 ps
CPU time	9.45 seconds
Started	Mar 10 12:50:13 PM PDT 24
Finished	Mar 10 12:50:22 PM PDT 24
Peak memory	199084 kb
Host	smart-9607f533-7a34-4591-9fbc-b351a5e4223e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705204353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.705204353
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.3907447878
Short name	T226
Test name
Test status
Simulation time	86843785545 ps
CPU time	183.53 seconds
Started	Mar 10 12:50:08 PM PDT 24
Finished	Mar 10 12:53:12 PM PDT 24
Peak memory	198700 kb
Host	smart-ede0b2a2-2154-49ba-9b4e-a5931b2d8527
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3907447878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3907447878
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.2783508425
Short name	T401
Test name
Test status
Simulation time	1976941245 ps
CPU time	60.89 seconds
Started	Mar 10 12:50:15 PM PDT 24
Finished	Mar 10 12:51:16 PM PDT 24
Peak memory	200020 kb
Host	smart-b3dc377b-2752-4208-8c1e-f54138b05c18
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2783508425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2783508425
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.2041289043
Short name	T1055
Test name
Test status
Simulation time	6734438838 ps
CPU time	61.4 seconds
Started	Mar 10 12:50:08 PM PDT 24
Finished	Mar 10 12:51:10 PM PDT 24
Peak memory	198796 kb
Host	smart-2d0e81bf-ca76-4b22-bfa0-c43e93cc775f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2041289043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2041289043
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.3345932757
Short name	T946
Test name
Test status
Simulation time	98989385218 ps
CPU time	41.44 seconds
Started	Mar 10 12:50:11 PM PDT 24
Finished	Mar 10 12:50:52 PM PDT 24
Peak memory	199936 kb
Host	smart-8cbd0780-2827-474f-a064-171e82be0ef6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345932757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3345932757
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.4093536019
Short name	T483
Test name
Test status
Simulation time	52224191359 ps
CPU time	43.64 seconds
Started	Mar 10 12:50:06 PM PDT 24
Finished	Mar 10 12:50:50 PM PDT 24
Peak memory	195612 kb
Host	smart-2873fb4b-e382-4553-9952-68a4c9dd1c9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093536019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4093536019
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.2124250719
Short name	T1056
Test name
Test status
Simulation time	648751552 ps
CPU time	2.76 seconds
Started	Mar 10 12:50:01 PM PDT 24
Finished	Mar 10 12:50:04 PM PDT 24
Peak memory	198896 kb
Host	smart-5517622f-032c-4abe-8bac-bee343984d37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124250719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2124250719
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all.228978518
Short name	T713
Test name
Test status
Simulation time	221732961965 ps
CPU time	389.99 seconds
Started	Mar 10 12:50:14 PM PDT 24
Finished	Mar 10 12:56:44 PM PDT 24
Peak memory	200116 kb
Host	smart-d111a05e-b854-46f6-b47a-2f3812825307
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228978518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.228978518
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.2162398594
Short name	T1109
Test name
Test status
Simulation time	7888212364 ps
CPU time	9.44 seconds
Started	Mar 10 12:50:08 PM PDT 24
Finished	Mar 10 12:50:18 PM PDT 24
Peak memory	199184 kb
Host	smart-005f65c5-6843-45a3-9a89-1ac806a7a5e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162398594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2162398594
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.2149769237
Short name	T655
Test name
Test status
Simulation time	92681622391 ps
CPU time	186.71 seconds
Started	Mar 10 12:50:03 PM PDT 24
Finished	Mar 10 12:53:11 PM PDT 24
Peak memory	200096 kb
Host	smart-779c499b-fdd7-42f2-93d8-111105f977e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2149769237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2149769237
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.1610902115
Short name	T841
Test name
Test status
Simulation time	70323220101 ps
CPU time	27.34 seconds
Started	Mar 10 12:57:32 PM PDT 24
Finished	Mar 10 12:57:59 PM PDT 24
Peak memory	199584 kb
Host	smart-29630028-149d-438d-8269-ee2aa5e434a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1610902115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1610902115
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.1266946727
Short name	T1123
Test name
Test status
Simulation time	27656173697 ps
CPU time	43.86 seconds
Started	Mar 10 12:57:31 PM PDT 24
Finished	Mar 10 12:58:15 PM PDT 24
Peak memory	200136 kb
Host	smart-cc53a32c-9620-40eb-84c3-23efb232ad74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266946727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1266946727
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.2833412742
Short name	T949
Test name
Test status
Simulation time	187190687380 ps
CPU time	308.28 seconds
Started	Mar 10 12:57:31 PM PDT 24
Finished	Mar 10 01:02:39 PM PDT 24
Peak memory	200064 kb
Host	smart-c034da6f-8b13-485a-a36b-71d1f9a703d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833412742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2833412742
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.2884809583
Short name	T1118
Test name
Test status
Simulation time	277433851051 ps
CPU time	452.43 seconds
Started	Mar 10 12:57:32 PM PDT 24
Finished	Mar 10 01:05:05 PM PDT 24
Peak memory	200096 kb
Host	smart-27328fb5-f25b-4b4a-9c85-a143bd5528d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884809583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2884809583
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.3202000594
Short name	T760
Test name
Test status
Simulation time	38142429056 ps
CPU time	59.17 seconds
Started	Mar 10 12:57:36 PM PDT 24
Finished	Mar 10 12:58:35 PM PDT 24
Peak memory	200076 kb
Host	smart-e4542fad-77d3-42f5-930d-97f51b7f9379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202000594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3202000594
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.1612069560
Short name	T754
Test name
Test status
Simulation time	15432978 ps
CPU time	0.55 seconds
Started	Mar 10 12:50:25 PM PDT 24
Finished	Mar 10 12:50:25 PM PDT 24
Peak memory	195460 kb
Host	smart-755cbd8f-4386-4ea6-b0e2-1b687b39d6d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612069560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1612069560
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.2682629511
Short name	T1104
Test name
Test status
Simulation time	443106289586 ps
CPU time	48.03 seconds
Started	Mar 10 12:50:14 PM PDT 24
Finished	Mar 10 12:51:02 PM PDT 24
Peak memory	200176 kb
Host	smart-fcfcd4c3-c0d3-4c4f-ba73-fcdfa936f740
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682629511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2682629511
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.3895336521
Short name	T207
Test name
Test status
Simulation time	14952319289 ps
CPU time	25.41 seconds
Started	Mar 10 12:50:24 PM PDT 24
Finished	Mar 10 12:50:50 PM PDT 24
Peak memory	199160 kb
Host	smart-24fca4d3-4f4d-486d-929b-191f33da7b46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895336521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3895336521
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.1915279758
Short name	T305
Test name
Test status
Simulation time	105215744627 ps
CPU time	46.87 seconds
Started	Mar 10 12:50:24 PM PDT 24
Finished	Mar 10 12:51:11 PM PDT 24
Peak memory	199936 kb
Host	smart-a2a2ea56-92df-469d-9b5b-afb7767f08c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915279758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1915279758
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_intr.58084791
Short name	T953
Test name
Test status
Simulation time	531116328690 ps
CPU time	580.75 seconds
Started	Mar 10 12:50:19 PM PDT 24
Finished	Mar 10 01:00:00 PM PDT 24
Peak memory	200112 kb
Host	smart-816c6a15-2eb8-4cf4-a68d-54bde275bb52
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58084791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.58084791
Directory	/workspace/12.uart_intr/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.4189718165
Short name	T435
Test name
Test status
Simulation time	147797362173 ps
CPU time	130.26 seconds
Started	Mar 10 12:50:24 PM PDT 24
Finished	Mar 10 12:52:34 PM PDT 24
Peak memory	200168 kb
Host	smart-3dc2201d-811a-40c8-aa58-f483a7e49dc0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4189718165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.4189718165
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_loopback.661829266
Short name	T439
Test name
Test status
Simulation time	2874205688 ps
CPU time	6.77 seconds
Started	Mar 10 12:50:16 PM PDT 24
Finished	Mar 10 12:50:23 PM PDT 24
Peak memory	198696 kb
Host	smart-8ab16d19-31ba-411b-a9f6-f590099c7464
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661829266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.661829266
Directory	/workspace/12.uart_loopback/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.2143019713
Short name	T418
Test name
Test status
Simulation time	42117358532 ps
CPU time	24.62 seconds
Started	Mar 10 12:50:18 PM PDT 24
Finished	Mar 10 12:50:43 PM PDT 24
Peak memory	199408 kb
Host	smart-50342dab-6358-4a4c-a8e5-f365a49261d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143019713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2143019713
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.262774707
Short name	T555
Test name
Test status
Simulation time	15890741788 ps
CPU time	61.37 seconds
Started	Mar 10 12:50:18 PM PDT 24
Finished	Mar 10 12:51:20 PM PDT 24
Peak memory	200144 kb
Host	smart-fed34815-440b-4a78-b31c-b60b0cdd59dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=262774707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.262774707
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.3261354776
Short name	T467
Test name
Test status
Simulation time	3512609656 ps
CPU time	30.62 seconds
Started	Mar 10 12:50:20 PM PDT 24
Finished	Mar 10 12:50:50 PM PDT 24
Peak memory	198124 kb
Host	smart-65492dda-3177-4b65-8d5f-2b3248a1d6cf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3261354776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3261354776
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.335152527
Short name	T617
Test name
Test status
Simulation time	239531554058 ps
CPU time	124.69 seconds
Started	Mar 10 12:50:19 PM PDT 24
Finished	Mar 10 12:52:23 PM PDT 24
Peak memory	199792 kb
Host	smart-8b76bb9d-90c0-49db-87e9-8e0781ad91ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335152527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.335152527
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.3237558837
Short name	T414
Test name
Test status
Simulation time	3918551749 ps
CPU time	2.16 seconds
Started	Mar 10 12:50:18 PM PDT 24
Finished	Mar 10 12:50:20 PM PDT 24
Peak memory	195852 kb
Host	smart-af9dfffc-849d-4949-90ed-e19f188999a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237558837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3237558837
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.1621259523
Short name	T569
Test name
Test status
Simulation time	430824796 ps
CPU time	2.33 seconds
Started	Mar 10 12:50:15 PM PDT 24
Finished	Mar 10 12:50:17 PM PDT 24
Peak memory	198792 kb
Host	smart-2ed24e35-9cf4-458f-9e91-75b9381b72d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621259523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1621259523
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_stress_all.1972845604
Short name	T527
Test name
Test status
Simulation time	24282498097 ps
CPU time	192.19 seconds
Started	Mar 10 12:50:23 PM PDT 24
Finished	Mar 10 12:53:36 PM PDT 24
Peak memory	200132 kb
Host	smart-6c334c72-55a3-4bc2-b9c4-834d70f1cd1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972845604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1972845604
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.1548146197
Short name	T412
Test name
Test status
Simulation time	1850299523 ps
CPU time	2.32 seconds
Started	Mar 10 12:50:17 PM PDT 24
Finished	Mar 10 12:50:20 PM PDT 24
Peak memory	197964 kb
Host	smart-33fcfa9e-656a-4eab-8387-223005671205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548146197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1548146197
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.745426974
Short name	T492
Test name
Test status
Simulation time	48923330967 ps
CPU time	86.88 seconds
Started	Mar 10 12:50:11 PM PDT 24
Finished	Mar 10 12:51:38 PM PDT 24
Peak memory	200080 kb
Host	smart-b3a5adbe-8e54-4443-a40e-4334ea84c782
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745426974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.745426974
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.601264260
Short name	T148
Test name
Test status
Simulation time	14116788889 ps
CPU time	5.44 seconds
Started	Mar 10 12:57:38 PM PDT 24
Finished	Mar 10 12:57:44 PM PDT 24
Peak memory	197932 kb
Host	smart-ce9a6597-5bc9-4322-86e6-5b0d0a7610c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601264260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.601264260
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.112172253
Short name	T916
Test name
Test status
Simulation time	130568259137 ps
CPU time	213.48 seconds
Started	Mar 10 12:57:38 PM PDT 24
Finished	Mar 10 01:01:12 PM PDT 24
Peak memory	200108 kb
Host	smart-1db61170-daf7-4205-bb49-7fcd190dbda4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112172253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.112172253
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.3066378715
Short name	T192
Test name
Test status
Simulation time	151328582753 ps
CPU time	139.07 seconds
Started	Mar 10 12:57:37 PM PDT 24
Finished	Mar 10 12:59:56 PM PDT 24
Peak memory	200140 kb
Host	smart-93f97fc3-a771-4b8d-9880-3ff8c26bb7a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066378715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3066378715
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.464726055
Short name	T284
Test name
Test status
Simulation time	58829370447 ps
CPU time	89.58 seconds
Started	Mar 10 12:57:42 PM PDT 24
Finished	Mar 10 12:59:11 PM PDT 24
Peak memory	200148 kb
Host	smart-798e34a4-077f-4383-b042-a55b1add7c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464726055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.464726055
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.2365827445
Short name	T653
Test name
Test status
Simulation time	18847883408 ps
CPU time	21.48 seconds
Started	Mar 10 12:57:42 PM PDT 24
Finished	Mar 10 12:58:04 PM PDT 24
Peak memory	199856 kb
Host	smart-2543ce46-3fc0-4422-8fc3-68a55b8f444e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365827445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2365827445
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.4150402986
Short name	T1004
Test name
Test status
Simulation time	2080933503 ps
CPU time	4.29 seconds
Started	Mar 10 12:57:40 PM PDT 24
Finished	Mar 10 12:57:44 PM PDT 24
Peak memory	198448 kb
Host	smart-39524d3e-3d9d-4741-91ab-d578dd41c5f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150402986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4150402986
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.338157339
Short name	T209
Test name
Test status
Simulation time	70091195176 ps
CPU time	31.23 seconds
Started	Mar 10 12:57:40 PM PDT 24
Finished	Mar 10 12:58:12 PM PDT 24
Peak memory	199796 kb
Host	smart-158cde0e-bf2c-4414-ab03-c7d2e6f771d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338157339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.338157339
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.2441682302
Short name	T210
Test name
Test status
Simulation time	28467414148 ps
CPU time	12.69 seconds
Started	Mar 10 12:57:43 PM PDT 24
Finished	Mar 10 12:57:57 PM PDT 24
Peak memory	200020 kb
Host	smart-235dbacb-b63f-4e9f-be2e-d3ac0f400e53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441682302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2441682302
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.2678191953
Short name	T49
Test name
Test status
Simulation time	99995741854 ps
CPU time	168.81 seconds
Started	Mar 10 12:57:42 PM PDT 24
Finished	Mar 10 01:00:30 PM PDT 24
Peak memory	200044 kb
Host	smart-a3ea505e-45c5-444a-9ccc-2eddd1f51dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678191953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2678191953
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.3112589968
Short name	T185
Test name
Test status
Simulation time	126943890741 ps
CPU time	209.43 seconds
Started	Mar 10 12:57:47 PM PDT 24
Finished	Mar 10 01:01:17 PM PDT 24
Peak memory	200076 kb
Host	smart-d293708e-faf0-41d2-bd4f-c562e60d4b16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112589968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3112589968
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_alert_test.1040445216
Short name	T521
Test name
Test status
Simulation time	27841827 ps
CPU time	0.54 seconds
Started	Mar 10 12:50:28 PM PDT 24
Finished	Mar 10 12:50:28 PM PDT 24
Peak memory	195508 kb
Host	smart-8e48bab4-bf0a-4d8a-be40-bcb3d04c5e9a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040445216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1040445216
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.4207479815
Short name	T906
Test name
Test status
Simulation time	191705713710 ps
CPU time	74.79 seconds
Started	Mar 10 12:50:22 PM PDT 24
Finished	Mar 10 12:51:37 PM PDT 24
Peak memory	200068 kb
Host	smart-8217d376-5722-4a8e-94cb-fdbcb743e4fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4207479815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.4207479815
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.4284144496
Short name	T695
Test name
Test status
Simulation time	104083409230 ps
CPU time	203.54 seconds
Started	Mar 10 12:50:24 PM PDT 24
Finished	Mar 10 12:53:48 PM PDT 24
Peak memory	200056 kb
Host	smart-63248525-177f-49b8-b52e-da196e04fd28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284144496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4284144496
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.2633925233
Short name	T825
Test name
Test status
Simulation time	57758654345 ps
CPU time	143.27 seconds
Started	Mar 10 12:50:24 PM PDT 24
Finished	Mar 10 12:52:47 PM PDT 24
Peak memory	200040 kb
Host	smart-f3f76444-b21f-4f94-8d72-78ae91f7ffb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633925233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2633925233
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.1808160339
Short name	T1036
Test name
Test status
Simulation time	61680124543 ps
CPU time	99.83 seconds
Started	Mar 10 12:50:25 PM PDT 24
Finished	Mar 10 12:52:05 PM PDT 24
Peak memory	200200 kb
Host	smart-c2d216dd-51f4-48c6-b3b1-385c525d165d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808160339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1808160339
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.2314901947
Short name	T385
Test name
Test status
Simulation time	72987816435 ps
CPU time	289.23 seconds
Started	Mar 10 12:50:27 PM PDT 24
Finished	Mar 10 12:55:17 PM PDT 24
Peak memory	200160 kb
Host	smart-a76ae8fb-77aa-4bfa-86b5-16448bb4296a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2314901947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2314901947
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/13.uart_loopback.1479994136
Short name	T736
Test name
Test status
Simulation time	950334357 ps
CPU time	0.89 seconds
Started	Mar 10 12:50:25 PM PDT 24
Finished	Mar 10 12:50:26 PM PDT 24
Peak memory	196388 kb
Host	smart-52544d42-4837-4d6e-89d7-a39a845d9dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479994136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1479994136
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.2651912543
Short name	T652
Test name
Test status
Simulation time	32774704368 ps
CPU time	32.64 seconds
Started	Mar 10 12:50:27 PM PDT 24
Finished	Mar 10 12:50:59 PM PDT 24
Peak memory	197968 kb
Host	smart-15238bf3-820a-4dab-9b5a-636b315016fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2651912543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2651912543
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.3678516907
Short name	T895
Test name
Test status
Simulation time	12544171182 ps
CPU time	326.84 seconds
Started	Mar 10 12:50:24 PM PDT 24
Finished	Mar 10 12:55:51 PM PDT 24
Peak memory	200096 kb
Host	smart-c4195530-65ee-432d-9b5d-931582a6341d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3678516907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3678516907
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.3561631812
Short name	T716
Test name
Test status
Simulation time	6731993112 ps
CPU time	9.82 seconds
Started	Mar 10 12:50:25 PM PDT 24
Finished	Mar 10 12:50:35 PM PDT 24
Peak memory	198924 kb
Host	smart-36ae93d7-c84b-4660-8cbb-bfecbe4c40b1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3561631812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3561631812
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.1505680742
Short name	T496
Test name
Test status
Simulation time	42745238897 ps
CPU time	35.53 seconds
Started	Mar 10 12:50:25 PM PDT 24
Finished	Mar 10 12:51:01 PM PDT 24
Peak memory	200160 kb
Host	smart-ebe97e85-67a1-4830-9245-23081173d707
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505680742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1505680742
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.3725231814
Short name	T1060
Test name
Test status
Simulation time	6740569771 ps
CPU time	11.27 seconds
Started	Mar 10 12:50:26 PM PDT 24
Finished	Mar 10 12:50:37 PM PDT 24
Peak memory	195956 kb
Host	smart-6f7cbb57-a40a-45e0-9631-77a491e6ebaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725231814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3725231814
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.1997674426
Short name	T1121
Test name
Test status
Simulation time	250110720 ps
CPU time	1.33 seconds
Started	Mar 10 12:50:25 PM PDT 24
Finished	Mar 10 12:50:26 PM PDT 24
Peak memory	198212 kb
Host	smart-c29f54df-8195-40b6-9818-8490764271f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997674426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1997674426
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_stress_all_with_rand_reset.2453000062
Short name	T59
Test name
Test status
Simulation time	28800861587 ps
CPU time	178.45 seconds
Started	Mar 10 12:50:28 PM PDT 24
Finished	Mar 10 12:53:27 PM PDT 24
Peak memory	216856 kb
Host	smart-7758ab48-9457-4f00-aef0-f74a38756843
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453000062 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2453000062
Directory	/workspace/13.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.279677303
Short name	T646
Test name
Test status
Simulation time	6115832743 ps
CPU time	20.24 seconds
Started	Mar 10 12:50:27 PM PDT 24
Finished	Mar 10 12:50:47 PM PDT 24
Peak memory	199896 kb
Host	smart-1d3abeb7-42a7-431c-aad6-71149350a1a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279677303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.279677303
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.4129486162
Short name	T522
Test name
Test status
Simulation time	13335776935 ps
CPU time	15.96 seconds
Started	Mar 10 12:50:25 PM PDT 24
Finished	Mar 10 12:50:41 PM PDT 24
Peak memory	200108 kb
Host	smart-202397ae-1d9d-4d8d-939f-1cb1c7af5521
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129486162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4129486162
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.1551620274
Short name	T905
Test name
Test status
Simulation time	40732248991 ps
CPU time	57.26 seconds
Started	Mar 10 12:57:46 PM PDT 24
Finished	Mar 10 12:58:43 PM PDT 24
Peak memory	200056 kb
Host	smart-ff004dab-7782-46e8-8e7c-ee4011deb206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551620274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1551620274
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.2089440275
Short name	T1005
Test name
Test status
Simulation time	97337613216 ps
CPU time	149.89 seconds
Started	Mar 10 12:57:45 PM PDT 24
Finished	Mar 10 01:00:15 PM PDT 24
Peak memory	199672 kb
Host	smart-31a8d791-824b-4179-b96b-f5b020ae3b97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089440275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2089440275
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.2169630757
Short name	T1057
Test name
Test status
Simulation time	120716389783 ps
CPU time	63.45 seconds
Started	Mar 10 12:57:45 PM PDT 24
Finished	Mar 10 12:58:49 PM PDT 24
Peak memory	200132 kb
Host	smart-ff5b4f32-6e85-4c99-bae3-7d71686499ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169630757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2169630757
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.2569775580
Short name	T306
Test name
Test status
Simulation time	10300533089 ps
CPU time	18.49 seconds
Started	Mar 10 12:57:50 PM PDT 24
Finished	Mar 10 12:58:09 PM PDT 24
Peak memory	199728 kb
Host	smart-396b78fa-6b0a-4dde-a26c-136ad3eb6ce6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569775580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2569775580
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.1818051023
Short name	T170
Test name
Test status
Simulation time	179937583052 ps
CPU time	262.92 seconds
Started	Mar 10 12:57:53 PM PDT 24
Finished	Mar 10 01:02:16 PM PDT 24
Peak memory	200104 kb
Host	smart-e714fc24-6e31-4bf2-9692-1471f8256f49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818051023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1818051023
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.1604835638
Short name	T970
Test name
Test status
Simulation time	18844042244 ps
CPU time	13.95 seconds
Started	Mar 10 12:57:52 PM PDT 24
Finished	Mar 10 12:58:06 PM PDT 24
Peak memory	200140 kb
Host	smart-690c732a-d0c5-426d-963a-60e2d1178c45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604835638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1604835638
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.1220318580
Short name	T1013
Test name
Test status
Simulation time	52582259138 ps
CPU time	13.25 seconds
Started	Mar 10 12:57:50 PM PDT 24
Finished	Mar 10 12:58:04 PM PDT 24
Peak memory	200056 kb
Host	smart-b435850f-351f-4b35-a30e-6527d298f6fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220318580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1220318580
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.419795091
Short name	T322
Test name
Test status
Simulation time	17957855992 ps
CPU time	31.32 seconds
Started	Mar 10 12:57:50 PM PDT 24
Finished	Mar 10 12:58:22 PM PDT 24
Peak memory	200076 kb
Host	smart-75744351-2eb5-40fe-b3e4-b89746dfb983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419795091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.419795091
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.920523931
Short name	T959
Test name
Test status
Simulation time	31545790796 ps
CPU time	14.35 seconds
Started	Mar 10 12:57:58 PM PDT 24
Finished	Mar 10 12:58:12 PM PDT 24
Peak memory	200080 kb
Host	smart-a741029f-0239-4443-aa5b-84544c240e0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920523931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.920523931
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.4256812685
Short name	T541
Test name
Test status
Simulation time	18566765 ps
CPU time	0.56 seconds
Started	Mar 10 12:50:38 PM PDT 24
Finished	Mar 10 12:50:39 PM PDT 24
Peak memory	195484 kb
Host	smart-79e39098-409c-4205-8241-b2b3b24151c4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256812685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4256812685
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.1191138578
Short name	T183
Test name
Test status
Simulation time	167457894351 ps
CPU time	105.07 seconds
Started	Mar 10 12:50:26 PM PDT 24
Finished	Mar 10 12:52:12 PM PDT 24
Peak memory	200156 kb
Host	smart-89035993-722b-4f38-9203-b2e2a547ea33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191138578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1191138578
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.2156527313
Short name	T671
Test name
Test status
Simulation time	75415389456 ps
CPU time	83.85 seconds
Started	Mar 10 12:50:30 PM PDT 24
Finished	Mar 10 12:51:54 PM PDT 24
Peak memory	200084 kb
Host	smart-6509c936-e3cf-4e67-bc93-9113db6b7d3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156527313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2156527313
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.1184608045
Short name	T173
Test name
Test status
Simulation time	36120691455 ps
CPU time	29.31 seconds
Started	Mar 10 12:50:31 PM PDT 24
Finished	Mar 10 12:51:00 PM PDT 24
Peak memory	200032 kb
Host	smart-ca7ba9be-4ecc-4384-ade0-e403cf2e40ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184608045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1184608045
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.4135288180
Short name	T441
Test name
Test status
Simulation time	67363839657 ps
CPU time	59.59 seconds
Started	Mar 10 12:50:35 PM PDT 24
Finished	Mar 10 12:51:35 PM PDT 24
Peak memory	199912 kb
Host	smart-8074bcf7-4dfb-4626-be71-9b43df606232
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135288180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4135288180
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.3395777131
Short name	T466
Test name
Test status
Simulation time	92751595485 ps
CPU time	339.7 seconds
Started	Mar 10 12:50:32 PM PDT 24
Finished	Mar 10 12:56:12 PM PDT 24
Peak memory	200060 kb
Host	smart-f840f5b4-f620-40ca-a2c8-f206e7f5bdd0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3395777131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3395777131
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.2270042209
Short name	T528
Test name
Test status
Simulation time	3902112721 ps
CPU time	2.59 seconds
Started	Mar 10 12:50:34 PM PDT 24
Finished	Mar 10 12:50:36 PM PDT 24
Peak memory	199052 kb
Host	smart-7bc16a7e-1b02-4374-9436-94c275d0c7d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270042209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2270042209
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.2932891968
Short name	T1042
Test name
Test status
Simulation time	68517223006 ps
CPU time	103.1 seconds
Started	Mar 10 12:50:33 PM PDT 24
Finished	Mar 10 12:52:17 PM PDT 24
Peak memory	198980 kb
Host	smart-42e46873-c870-4dd7-b8f8-f1bb5276ad9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932891968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2932891968
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_perf.3417172477
Short name	T909
Test name
Test status
Simulation time	21249822664 ps
CPU time	1022.18 seconds
Started	Mar 10 12:50:35 PM PDT 24
Finished	Mar 10 01:07:37 PM PDT 24
Peak memory	200032 kb
Host	smart-316d6dc9-2011-479c-81be-54890df04970
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3417172477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3417172477
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.9879662
Short name	T480
Test name
Test status
Simulation time	5067623094 ps
CPU time	26.41 seconds
Started	Mar 10 12:50:33 PM PDT 24
Finished	Mar 10 12:50:59 PM PDT 24
Peak memory	198908 kb
Host	smart-f6066f8e-1aac-4b73-8ae9-56c7f6a50a58
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=9879662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.9879662
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.3333091073
Short name	T231
Test name
Test status
Simulation time	73159836239 ps
CPU time	110.03 seconds
Started	Mar 10 12:50:33 PM PDT 24
Finished	Mar 10 12:52:23 PM PDT 24
Peak memory	200032 kb
Host	smart-09426c5c-9ced-4558-8932-408264dc1548
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333091073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3333091073
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.2676645080
Short name	T477
Test name
Test status
Simulation time	7069005785 ps
CPU time	4.05 seconds
Started	Mar 10 12:50:33 PM PDT 24
Finished	Mar 10 12:50:37 PM PDT 24
Peak memory	195952 kb
Host	smart-dee2fc78-7895-4b24-831b-3af20fc1566c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676645080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2676645080
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.3768599426
Short name	T1044
Test name
Test status
Simulation time	108803319 ps
CPU time	0.89 seconds
Started	Mar 10 12:50:28 PM PDT 24
Finished	Mar 10 12:50:29 PM PDT 24
Peak memory	196748 kb
Host	smart-18305a03-d9ca-4e43-8b92-3a378be5f1cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768599426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3768599426
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.3232566761
Short name	T18
Test name
Test status
Simulation time	2516417902 ps
CPU time	2.2 seconds
Started	Mar 10 12:50:35 PM PDT 24
Finished	Mar 10 12:50:37 PM PDT 24
Peak memory	198320 kb
Host	smart-798b904c-6c98-47b6-9fab-707bf9dd544d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232566761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3232566761
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.207798636
Short name	T386
Test name
Test status
Simulation time	64372206995 ps
CPU time	74.9 seconds
Started	Mar 10 12:50:28 PM PDT 24
Finished	Mar 10 12:51:43 PM PDT 24
Peak memory	200036 kb
Host	smart-9f6503ee-f49c-45ec-a92a-1032f81aafea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207798636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.207798636
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.2543978519
Short name	T815
Test name
Test status
Simulation time	189020993831 ps
CPU time	78.06 seconds
Started	Mar 10 12:57:57 PM PDT 24
Finished	Mar 10 12:59:15 PM PDT 24
Peak memory	200140 kb
Host	smart-6ff1ed90-95a7-407a-887e-c51829fd7984
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543978519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2543978519
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.1129809990
Short name	T196
Test name
Test status
Simulation time	83532953094 ps
CPU time	63.27 seconds
Started	Mar 10 12:57:57 PM PDT 24
Finished	Mar 10 12:59:00 PM PDT 24
Peak memory	200112 kb
Host	smart-15e4c098-cacf-446c-8583-4288fc850c66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129809990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1129809990
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.2636790623
Short name	T197
Test name
Test status
Simulation time	127320760106 ps
CPU time	133.67 seconds
Started	Mar 10 12:58:02 PM PDT 24
Finished	Mar 10 01:00:16 PM PDT 24
Peak memory	200032 kb
Host	smart-18db6509-001e-410e-bc59-75be9c2f82c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636790623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2636790623
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.3747575380
Short name	T1077
Test name
Test status
Simulation time	12539637185 ps
CPU time	23.98 seconds
Started	Mar 10 12:58:02 PM PDT 24
Finished	Mar 10 12:58:26 PM PDT 24
Peak memory	200108 kb
Host	smart-0c71684d-4660-4a91-85a9-c465326f0d4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747575380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3747575380
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.2632941458
Short name	T530
Test name
Test status
Simulation time	19163494898 ps
CPU time	15.66 seconds
Started	Mar 10 12:58:03 PM PDT 24
Finished	Mar 10 12:58:18 PM PDT 24
Peak memory	197872 kb
Host	smart-20af66c5-79ad-428d-bc5c-2a95ec24d63d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632941458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2632941458
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.917591809
Short name	T821
Test name
Test status
Simulation time	11746825 ps
CPU time	0.57 seconds
Started	Mar 10 12:50:48 PM PDT 24
Finished	Mar 10 12:50:49 PM PDT 24
Peak memory	195492 kb
Host	smart-32efa19f-f688-41f1-a432-07dbf39854ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917591809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.917591809
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.4171009002
Short name	T184
Test name
Test status
Simulation time	105926453117 ps
CPU time	26.78 seconds
Started	Mar 10 12:50:38 PM PDT 24
Finished	Mar 10 12:51:05 PM PDT 24
Peak memory	200124 kb
Host	smart-a3193fe0-4711-4dbf-a061-a0b5d60d1434
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171009002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4171009002
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.922228526
Short name	T727
Test name
Test status
Simulation time	74725689016 ps
CPU time	33.01 seconds
Started	Mar 10 12:50:39 PM PDT 24
Finished	Mar 10 12:51:12 PM PDT 24
Peak memory	199996 kb
Host	smart-f812fd31-5e5c-4bab-b959-664f5aaf2e2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922228526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.922228526
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/15.uart_intr.3102686713
Short name	T423
Test name
Test status
Simulation time	24536780724 ps
CPU time	10.39 seconds
Started	Mar 10 12:50:44 PM PDT 24
Finished	Mar 10 12:50:54 PM PDT 24
Peak memory	196640 kb
Host	smart-a143e734-6d5c-4493-86fd-ea8b1156692f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102686713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3102686713
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.1248050467
Short name	T402
Test name
Test status
Simulation time	112742026821 ps
CPU time	558.68 seconds
Started	Mar 10 12:50:45 PM PDT 24
Finished	Mar 10 01:00:03 PM PDT 24
Peak memory	200044 kb
Host	smart-ec3f09f4-b713-4b2e-a88b-e0f37bae4613
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1248050467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1248050467
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.875523171
Short name	T892
Test name
Test status
Simulation time	45137855424 ps
CPU time	43.43 seconds
Started	Mar 10 12:50:44 PM PDT 24
Finished	Mar 10 12:51:28 PM PDT 24
Peak memory	199796 kb
Host	smart-ce61741b-b56d-4ae4-9525-846d93989ecd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875523171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.875523171
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_perf.1037195212
Short name	T1116
Test name
Test status
Simulation time	2263574832 ps
CPU time	133.85 seconds
Started	Mar 10 12:50:42 PM PDT 24
Finished	Mar 10 12:52:56 PM PDT 24
Peak memory	199452 kb
Host	smart-1dad4fd8-8706-4aca-ab3f-bc70de916674
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1037195212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1037195212
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.1293441097
Short name	T1103
Test name
Test status
Simulation time	4233440317 ps
CPU time	32.47 seconds
Started	Mar 10 12:50:39 PM PDT 24
Finished	Mar 10 12:51:11 PM PDT 24
Peak memory	198076 kb
Host	smart-d9bf5f9e-b1d1-4fda-9954-31fc9b4f258f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1293441097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1293441097
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.2161405880
Short name	T903
Test name
Test status
Simulation time	24479223766 ps
CPU time	36.13 seconds
Started	Mar 10 12:50:43 PM PDT 24
Finished	Mar 10 12:51:19 PM PDT 24
Peak memory	199328 kb
Host	smart-cd885edc-f95f-4b0f-bf77-f2a4525102c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2161405880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2161405880
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.357186835
Short name	T894
Test name
Test status
Simulation time	2207844152 ps
CPU time	4.09 seconds
Started	Mar 10 12:50:45 PM PDT 24
Finished	Mar 10 12:50:49 PM PDT 24
Peak memory	195688 kb
Host	smart-8257889f-fac6-4bf5-86cf-aa03a2955c86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357186835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.357186835
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.3064137111
Short name	T511
Test name
Test status
Simulation time	722981370 ps
CPU time	1.23 seconds
Started	Mar 10 12:50:39 PM PDT 24
Finished	Mar 10 12:50:40 PM PDT 24
Peak memory	197872 kb
Host	smart-c993a3d0-a244-4bc1-9f88-b97e5ddedaf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064137111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3064137111
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_stress_all.1964144642
Short name	T189
Test name
Test status
Simulation time	39215839448 ps
CPU time	116.47 seconds
Started	Mar 10 12:50:47 PM PDT 24
Finished	Mar 10 12:52:44 PM PDT 24
Peak memory	200072 kb
Host	smart-b1f69eab-490a-4d1e-92b8-b3814c62ecb2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964144642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1964144642
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.2950722666
Short name	T574
Test name
Test status
Simulation time	1290744216 ps
CPU time	1.49 seconds
Started	Mar 10 12:50:45 PM PDT 24
Finished	Mar 10 12:50:46 PM PDT 24
Peak memory	197248 kb
Host	smart-80ae4e82-f162-4181-9d6a-930ff6075eee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950722666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2950722666
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.1108358656
Short name	T806
Test name
Test status
Simulation time	36811537702 ps
CPU time	58.42 seconds
Started	Mar 10 12:50:38 PM PDT 24
Finished	Mar 10 12:51:37 PM PDT 24
Peak memory	200124 kb
Host	smart-f2aa40c3-714b-470c-ac17-cbd6bcb905de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108358656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1108358656
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.1968967785
Short name	T540
Test name
Test status
Simulation time	8746337869 ps
CPU time	13.71 seconds
Started	Mar 10 12:58:02 PM PDT 24
Finished	Mar 10 12:58:16 PM PDT 24
Peak memory	199964 kb
Host	smart-e4f501b0-96fb-4e92-bf11-0f4e0940aad5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968967785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1968967785
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.1939687436
Short name	T632
Test name
Test status
Simulation time	16262303464 ps
CPU time	29.41 seconds
Started	Mar 10 12:58:01 PM PDT 24
Finished	Mar 10 12:58:31 PM PDT 24
Peak memory	200208 kb
Host	smart-c980903b-f683-4680-9a5f-be2bcc720e54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939687436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1939687436
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.1598726386
Short name	T849
Test name
Test status
Simulation time	39912593287 ps
CPU time	17.94 seconds
Started	Mar 10 12:58:03 PM PDT 24
Finished	Mar 10 12:58:22 PM PDT 24
Peak memory	200096 kb
Host	smart-63e57165-b6b4-42f3-b374-abfa5b0759c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598726386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1598726386
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.1122840533
Short name	T286
Test name
Test status
Simulation time	17564463286 ps
CPU time	7.39 seconds
Started	Mar 10 12:58:09 PM PDT 24
Finished	Mar 10 12:58:16 PM PDT 24
Peak memory	199636 kb
Host	smart-ec4a4c79-9f3b-485b-8043-c278588b99fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122840533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1122840533
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.947545070
Short name	T150
Test name
Test status
Simulation time	38384544605 ps
CPU time	17.2 seconds
Started	Mar 10 12:58:08 PM PDT 24
Finished	Mar 10 12:58:26 PM PDT 24
Peak memory	199824 kb
Host	smart-a6274e6c-c3fc-4ad6-b3b7-77d8caba8ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947545070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.947545070
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.4032902139
Short name	T1032
Test name
Test status
Simulation time	26338271223 ps
CPU time	44.89 seconds
Started	Mar 10 12:58:08 PM PDT 24
Finished	Mar 10 12:58:53 PM PDT 24
Peak memory	199248 kb
Host	smart-bf12e6e5-860e-43b5-9e13-784679f8b805
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032902139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4032902139
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.693897174
Short name	T729
Test name
Test status
Simulation time	63835885413 ps
CPU time	107.23 seconds
Started	Mar 10 12:58:11 PM PDT 24
Finished	Mar 10 12:59:58 PM PDT 24
Peak memory	200096 kb
Host	smart-8233ae05-cf54-4291-b2be-c42037c2fe7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693897174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.693897174
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.1470898222
Short name	T307
Test name
Test status
Simulation time	35226031581 ps
CPU time	53.45 seconds
Started	Mar 10 12:58:13 PM PDT 24
Finished	Mar 10 12:59:07 PM PDT 24
Peak memory	200076 kb
Host	smart-0e1bcf6a-c5b1-4e3d-b8d5-11757ab9a0ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470898222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1470898222
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.301932537
Short name	T215
Test name
Test status
Simulation time	10043614960 ps
CPU time	5.2 seconds
Started	Mar 10 12:58:14 PM PDT 24
Finished	Mar 10 12:58:19 PM PDT 24
Peak memory	199692 kb
Host	smart-f0cd416f-d7e5-4463-a9a1-2c3a887760d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301932537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.301932537
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.1168070869
Short name	T619
Test name
Test status
Simulation time	44576535 ps
CPU time	0.55 seconds
Started	Mar 10 12:51:00 PM PDT 24
Finished	Mar 10 12:51:00 PM PDT 24
Peak memory	195436 kb
Host	smart-995f65a5-bad1-4ffc-8b92-5796344a18ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168070869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1168070869
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.47215937
Short name	T870
Test name
Test status
Simulation time	236069196966 ps
CPU time	267.97 seconds
Started	Mar 10 12:50:46 PM PDT 24
Finished	Mar 10 12:55:14 PM PDT 24
Peak memory	200072 kb
Host	smart-0863fffb-82b0-4ffe-a793-b793d3b85bda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47215937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.47215937
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.984659042
Short name	T907
Test name
Test status
Simulation time	228222747648 ps
CPU time	363.06 seconds
Started	Mar 10 12:50:47 PM PDT 24
Finished	Mar 10 12:56:51 PM PDT 24
Peak memory	200076 kb
Host	smart-f2723dd0-cd41-4fac-a619-f53da8dc79b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984659042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.984659042
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_intr.1793815371
Short name	T542
Test name
Test status
Simulation time	55348075045 ps
CPU time	74.15 seconds
Started	Mar 10 12:50:53 PM PDT 24
Finished	Mar 10 12:52:08 PM PDT 24
Peak memory	200092 kb
Host	smart-fb52c304-96d2-457f-ac85-e4ce3ead01f8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793815371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1793815371
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.2266291308
Short name	T661
Test name
Test status
Simulation time	136436408701 ps
CPU time	238.22 seconds
Started	Mar 10 12:50:54 PM PDT 24
Finished	Mar 10 12:54:53 PM PDT 24
Peak memory	200116 kb
Host	smart-e224e3ce-cdd8-400f-8738-02d2a9acf38c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2266291308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2266291308
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.1346139235
Short name	T692
Test name
Test status
Simulation time	2466355533 ps
CPU time	2.93 seconds
Started	Mar 10 12:50:53 PM PDT 24
Finished	Mar 10 12:50:57 PM PDT 24
Peak memory	195724 kb
Host	smart-83a2c833-b460-44ce-bc75-360b03d5d8f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346139235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1346139235
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.2572594480
Short name	T446
Test name
Test status
Simulation time	155960364572 ps
CPU time	19.28 seconds
Started	Mar 10 12:50:53 PM PDT 24
Finished	Mar 10 12:51:13 PM PDT 24
Peak memory	197548 kb
Host	smart-92de617f-331a-45be-9c75-0bee957ee82f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572594480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2572594480
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.1815147965
Short name	T494
Test name
Test status
Simulation time	5558993695 ps
CPU time	312.63 seconds
Started	Mar 10 12:50:53 PM PDT 24
Finished	Mar 10 12:56:06 PM PDT 24
Peak memory	199664 kb
Host	smart-e8313a36-41f6-45bb-ac2b-1944c0ec41a1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1815147965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1815147965
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.1329870731
Short name	T581
Test name
Test status
Simulation time	6796482344 ps
CPU time	58.87 seconds
Started	Mar 10 12:50:53 PM PDT 24
Finished	Mar 10 12:51:51 PM PDT 24
Peak memory	198900 kb
Host	smart-8309d9e2-8213-4abe-9636-5bcef6af4d0e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1329870731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1329870731
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.3544060796
Short name	T383
Test name
Test status
Simulation time	21766077320 ps
CPU time	50.82 seconds
Started	Mar 10 12:50:54 PM PDT 24
Finished	Mar 10 12:51:45 PM PDT 24
Peak memory	199960 kb
Host	smart-e4fa9ee8-e877-45b9-8b0b-bd1f488d8a50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544060796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3544060796
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.3761548896
Short name	T919
Test name
Test status
Simulation time	37609314736 ps
CPU time	30.51 seconds
Started	Mar 10 12:50:53 PM PDT 24
Finished	Mar 10 12:51:24 PM PDT 24
Peak memory	195848 kb
Host	smart-24739c40-e124-4765-a5ce-122e54233859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761548896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3761548896
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.1156286386
Short name	T708
Test name
Test status
Simulation time	251866675 ps
CPU time	1.39 seconds
Started	Mar 10 12:50:50 PM PDT 24
Finished	Mar 10 12:50:51 PM PDT 24
Peak memory	198012 kb
Host	smart-cfcd09b0-f8c6-400b-8115-26bc4cd3d9e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156286386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1156286386
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_stress_all.696230573
Short name	T176
Test name
Test status
Simulation time	57974293093 ps
CPU time	250.07 seconds
Started	Mar 10 12:50:58 PM PDT 24
Finished	Mar 10 12:55:08 PM PDT 24
Peak memory	200056 kb
Host	smart-903e621f-231b-493b-ac0e-8ba4be762af4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696230573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.696230573
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.2179200951
Short name	T453
Test name
Test status
Simulation time	6907122923 ps
CPU time	10.22 seconds
Started	Mar 10 12:50:53 PM PDT 24
Finished	Mar 10 12:51:03 PM PDT 24
Peak memory	200072 kb
Host	smart-4bd23382-55ca-448e-a1ba-31b99fd8c5e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179200951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2179200951
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.3191092664
Short name	T524
Test name
Test status
Simulation time	16639882049 ps
CPU time	30.25 seconds
Started	Mar 10 12:50:48 PM PDT 24
Finished	Mar 10 12:51:19 PM PDT 24
Peak memory	200008 kb
Host	smart-603ad0b8-caf9-4e37-be9c-576c0471fbba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191092664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3191092664
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.1540458828
Short name	T759
Test name
Test status
Simulation time	30793992484 ps
CPU time	50.03 seconds
Started	Mar 10 12:58:14 PM PDT 24
Finished	Mar 10 12:59:04 PM PDT 24
Peak memory	200080 kb
Host	smart-00c11943-9463-465a-9891-e9de1459938d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540458828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1540458828
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.2341334788
Short name	T236
Test name
Test status
Simulation time	125993287725 ps
CPU time	196.04 seconds
Started	Mar 10 12:58:13 PM PDT 24
Finished	Mar 10 01:01:30 PM PDT 24
Peak memory	200168 kb
Host	smart-49aa8910-390d-4dd1-9490-a4fb695ed8fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341334788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2341334788
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.979825368
Short name	T111
Test name
Test status
Simulation time	195328003306 ps
CPU time	50.34 seconds
Started	Mar 10 12:58:13 PM PDT 24
Finished	Mar 10 12:59:04 PM PDT 24
Peak memory	199964 kb
Host	smart-8e6edb62-1ae3-4e2e-8a6a-f2161db24364
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979825368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.979825368
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.4207496267
Short name	T144
Test name
Test status
Simulation time	38662757255 ps
CPU time	41.49 seconds
Started	Mar 10 12:58:13 PM PDT 24
Finished	Mar 10 12:58:55 PM PDT 24
Peak memory	200016 kb
Host	smart-f9ea1bc7-f933-4d93-a3f6-21735947c08a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4207496267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4207496267
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.2196184098
Short name	T156
Test name
Test status
Simulation time	41732890060 ps
CPU time	19.85 seconds
Started	Mar 10 12:58:14 PM PDT 24
Finished	Mar 10 12:58:34 PM PDT 24
Peak memory	200080 kb
Host	smart-a58ee9fb-908e-4add-ada1-9dfe3e95499c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196184098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2196184098
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.1398901250
Short name	T294
Test name
Test status
Simulation time	26186254636 ps
CPU time	44.82 seconds
Started	Mar 10 12:58:17 PM PDT 24
Finished	Mar 10 12:59:03 PM PDT 24
Peak memory	200136 kb
Host	smart-670b8bde-3898-484f-8983-97c9339b352f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398901250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1398901250
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.2087257190
Short name	T1115
Test name
Test status
Simulation time	11664945774 ps
CPU time	18.02 seconds
Started	Mar 10 12:58:18 PM PDT 24
Finished	Mar 10 12:58:36 PM PDT 24
Peak memory	199640 kb
Host	smart-279ccc23-a211-409a-be4e-20250a162799
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087257190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2087257190
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.2805179829
Short name	T1002
Test name
Test status
Simulation time	39586432246 ps
CPU time	25.58 seconds
Started	Mar 10 12:58:18 PM PDT 24
Finished	Mar 10 12:58:44 PM PDT 24
Peak memory	199988 kb
Host	smart-ca5bbbb7-7c62-4bed-b4ae-a8c91271b5b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805179829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2805179829
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.1633444540
Short name	T873
Test name
Test status
Simulation time	33513389814 ps
CPU time	28.98 seconds
Started	Mar 10 12:58:19 PM PDT 24
Finished	Mar 10 12:58:49 PM PDT 24
Peak memory	199868 kb
Host	smart-7aa81521-6a44-4f6b-ace5-192036f95c57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633444540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1633444540
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.2191877808
Short name	T606
Test name
Test status
Simulation time	30477364 ps
CPU time	0.54 seconds
Started	Mar 10 12:51:05 PM PDT 24
Finished	Mar 10 12:51:05 PM PDT 24
Peak memory	194400 kb
Host	smart-293e73eb-09dd-46db-9e6c-f68c99bb408e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191877808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2191877808
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.4123298300
Short name	T976
Test name
Test status
Simulation time	130447272719 ps
CPU time	101.99 seconds
Started	Mar 10 12:51:00 PM PDT 24
Finished	Mar 10 12:52:42 PM PDT 24
Peak memory	200136 kb
Host	smart-db311c77-a911-4c24-a67c-fd80f9c9873c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123298300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.4123298300
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.1601234583
Short name	T332
Test name
Test status
Simulation time	195150424605 ps
CPU time	57.85 seconds
Started	Mar 10 12:50:59 PM PDT 24
Finished	Mar 10 12:51:58 PM PDT 24
Peak memory	199696 kb
Host	smart-d4daf368-128d-4e7f-ba78-9ef529916cdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601234583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1601234583
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_intr.4189446420
Short name	T631
Test name
Test status
Simulation time	35403953746 ps
CPU time	68.78 seconds
Started	Mar 10 12:50:59 PM PDT 24
Finished	Mar 10 12:52:08 PM PDT 24
Peak memory	199812 kb
Host	smart-075bb910-9238-4944-9688-314660888a41
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189446420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.4189446420
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.3684091797
Short name	T993
Test name
Test status
Simulation time	96581741964 ps
CPU time	266.52 seconds
Started	Mar 10 12:51:07 PM PDT 24
Finished	Mar 10 12:55:33 PM PDT 24
Peak memory	200208 kb
Host	smart-a493f899-326b-4dbb-be66-9f66b06101b6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3684091797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3684091797
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.1246690755
Short name	T752
Test name
Test status
Simulation time	56952863 ps
CPU time	0.71 seconds
Started	Mar 10 12:51:07 PM PDT 24
Finished	Mar 10 12:51:08 PM PDT 24
Peak memory	195460 kb
Host	smart-2f68e527-5ade-49e1-bcf9-91eb7dfe30fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246690755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1246690755
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.2272959011
Short name	T594
Test name
Test status
Simulation time	106495497649 ps
CPU time	42.43 seconds
Started	Mar 10 12:50:59 PM PDT 24
Finished	Mar 10 12:51:42 PM PDT 24
Peak memory	198040 kb
Host	smart-144ce87e-b26a-4934-8e09-55a21a44092c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272959011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2272959011
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.1579182829
Short name	T95
Test name
Test status
Simulation time	9590007253 ps
CPU time	166.68 seconds
Started	Mar 10 12:51:05 PM PDT 24
Finished	Mar 10 12:53:52 PM PDT 24
Peak memory	200076 kb
Host	smart-86ad5354-9e75-43ef-8795-56060f1d375a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1579182829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1579182829
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.2535677635
Short name	T615
Test name
Test status
Simulation time	1286641270 ps
CPU time	1.12 seconds
Started	Mar 10 12:50:58 PM PDT 24
Finished	Mar 10 12:51:00 PM PDT 24
Peak memory	195452 kb
Host	smart-d3e5a611-5727-4695-955b-5f6412f2d615
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2535677635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2535677635
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.4263511589
Short name	T347
Test name
Test status
Simulation time	490505255892 ps
CPU time	48.42 seconds
Started	Mar 10 12:51:05 PM PDT 24
Finished	Mar 10 12:51:53 PM PDT 24
Peak memory	200080 kb
Host	smart-f0adf2a9-367d-4d5d-bb60-2460173d42d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263511589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4263511589
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.4192210082
Short name	T27
Test name
Test status
Simulation time	3222544613 ps
CPU time	3.1 seconds
Started	Mar 10 12:50:57 PM PDT 24
Finished	Mar 10 12:51:01 PM PDT 24
Peak memory	195620 kb
Host	smart-a854fbe8-2c1f-4cba-94ac-2cd6bef557a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192210082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4192210082
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.2532336664
Short name	T567
Test name
Test status
Simulation time	11097363135 ps
CPU time	30.76 seconds
Started	Mar 10 12:50:58 PM PDT 24
Finished	Mar 10 12:51:30 PM PDT 24
Peak memory	199972 kb
Host	smart-c5072c9d-450c-485a-ac64-b3568d3a3228
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532336664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2532336664
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_stress_all.2569984720
Short name	T897
Test name
Test status
Simulation time	134638978014 ps
CPU time	284.69 seconds
Started	Mar 10 12:51:06 PM PDT 24
Finished	Mar 10 12:55:51 PM PDT 24
Peak memory	200104 kb
Host	smart-77ad92fb-9a4b-4b8d-ae06-6501f57d79fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569984720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2569984720
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/17.uart_stress_all_with_rand_reset.2773960995
Short name	T989
Test name
Test status
Simulation time	19002501950 ps
CPU time	230.44 seconds
Started	Mar 10 12:51:04 PM PDT 24
Finished	Mar 10 12:54:55 PM PDT 24
Peak memory	210760 kb
Host	smart-c0fffe89-4cfd-4e67-be3b-6549f1da4562
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773960995 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2773960995
Directory	/workspace/17.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.1787241980
Short name	T921
Test name
Test status
Simulation time	597587945 ps
CPU time	2.3 seconds
Started	Mar 10 12:51:05 PM PDT 24
Finished	Mar 10 12:51:07 PM PDT 24
Peak memory	198224 kb
Host	smart-c0ae900d-99c6-4080-8a51-34b17a2b1792
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787241980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1787241980
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.225811115
Short name	T826
Test name
Test status
Simulation time	10408839792 ps
CPU time	9.64 seconds
Started	Mar 10 12:50:59 PM PDT 24
Finished	Mar 10 12:51:09 PM PDT 24
Peak memory	199972 kb
Host	smart-3ccbab11-5fb9-45db-a7fb-18c41bf26448
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225811115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.225811115
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.1348253819
Short name	T300
Test name
Test status
Simulation time	35920430703 ps
CPU time	17.55 seconds
Started	Mar 10 12:58:18 PM PDT 24
Finished	Mar 10 12:58:36 PM PDT 24
Peak memory	199976 kb
Host	smart-da09af7d-93a8-425b-9241-837ec3130ed1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348253819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1348253819
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.2388918025
Short name	T878
Test name
Test status
Simulation time	16618293116 ps
CPU time	27.75 seconds
Started	Mar 10 12:58:18 PM PDT 24
Finished	Mar 10 12:58:46 PM PDT 24
Peak memory	199736 kb
Host	smart-b51a5f45-b77d-433b-84b7-bde776f4e30c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388918025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2388918025
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.1605902508
Short name	T40
Test name
Test status
Simulation time	11200213510 ps
CPU time	9.76 seconds
Started	Mar 10 12:58:18 PM PDT 24
Finished	Mar 10 12:58:29 PM PDT 24
Peak memory	200108 kb
Host	smart-235b4f1d-1a67-41af-8361-195437a6cefa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605902508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1605902508
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.2392251324
Short name	T857
Test name
Test status
Simulation time	131566768014 ps
CPU time	213.89 seconds
Started	Mar 10 12:58:23 PM PDT 24
Finished	Mar 10 01:01:57 PM PDT 24
Peak memory	200152 kb
Host	smart-b7b0d3ba-e101-472f-8478-514008e733c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2392251324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2392251324
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.1141014872
Short name	T1049
Test name
Test status
Simulation time	11350156176 ps
CPU time	10.24 seconds
Started	Mar 10 12:58:24 PM PDT 24
Finished	Mar 10 12:58:34 PM PDT 24
Peak memory	200108 kb
Host	smart-5d4a090e-fa14-43c2-8a27-b091c9d4f342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141014872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1141014872
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.1333550538
Short name	T171
Test name
Test status
Simulation time	55160482309 ps
CPU time	41.85 seconds
Started	Mar 10 12:58:25 PM PDT 24
Finished	Mar 10 12:59:07 PM PDT 24
Peak memory	200200 kb
Host	smart-1a78941c-e7cc-423a-a4e3-548dc800f87c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333550538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1333550538
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.1257034324
Short name	T130
Test name
Test status
Simulation time	180457886060 ps
CPU time	59.66 seconds
Started	Mar 10 12:58:27 PM PDT 24
Finished	Mar 10 12:59:27 PM PDT 24
Peak memory	200112 kb
Host	smart-857f554b-5387-4fcf-add3-c039c11c934e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257034324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1257034324
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_alert_test.3004239269
Short name	T819
Test name
Test status
Simulation time	11588657 ps
CPU time	0.57 seconds
Started	Mar 10 12:51:15 PM PDT 24
Finished	Mar 10 12:51:16 PM PDT 24
Peak memory	194536 kb
Host	smart-c04fbcda-1a92-4b3e-a286-03a0aa35709f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004239269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3004239269
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.4197785839
Short name	T629
Test name
Test status
Simulation time	20933178165 ps
CPU time	19.37 seconds
Started	Mar 10 12:51:03 PM PDT 24
Finished	Mar 10 12:51:23 PM PDT 24
Peak memory	200016 kb
Host	smart-0b62280c-2419-48b2-b8b9-05bc228d6454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197785839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.4197785839
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.1712590737
Short name	T1022
Test name
Test status
Simulation time	131617830908 ps
CPU time	206.37 seconds
Started	Mar 10 12:51:05 PM PDT 24
Finished	Mar 10 12:54:31 PM PDT 24
Peak memory	200024 kb
Host	smart-0fce2766-a754-44df-b204-eba9a0581d7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712590737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1712590737
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.2729440566
Short name	T201
Test name
Test status
Simulation time	21696920327 ps
CPU time	10.34 seconds
Started	Mar 10 12:51:11 PM PDT 24
Finished	Mar 10 12:51:22 PM PDT 24
Peak memory	199688 kb
Host	smart-1e907859-9e60-4cbf-9230-66456982b7f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729440566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2729440566
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_intr.304281284
Short name	T422
Test name
Test status
Simulation time	7220632338 ps
CPU time	9.19 seconds
Started	Mar 10 12:51:12 PM PDT 24
Finished	Mar 10 12:51:22 PM PDT 24
Peak memory	195776 kb
Host	smart-63400147-ce56-4b31-a9ab-a85d2d5d1b96
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304281284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.304281284
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_loopback.2086224242
Short name	T476
Test name
Test status
Simulation time	9466075341 ps
CPU time	7.8 seconds
Started	Mar 10 12:51:10 PM PDT 24
Finished	Mar 10 12:51:19 PM PDT 24
Peak memory	198892 kb
Host	smart-889c59e9-235f-4604-a6d5-67561bc654db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086224242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2086224242
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.33261903
Short name	T885
Test name
Test status
Simulation time	22555657332 ps
CPU time	27.45 seconds
Started	Mar 10 12:51:09 PM PDT 24
Finished	Mar 10 12:51:37 PM PDT 24
Peak memory	198172 kb
Host	smart-fc6b4a13-662d-49d6-816b-8e3a71e69df9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33261903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.33261903
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.1668089484
Short name	T410
Test name
Test status
Simulation time	27752026875 ps
CPU time	1468.11 seconds
Started	Mar 10 12:51:16 PM PDT 24
Finished	Mar 10 01:15:44 PM PDT 24
Peak memory	200212 kb
Host	smart-e5ab1c71-22d9-4cf9-8e76-b3f4d55ddab0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1668089484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1668089484
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.142737567
Short name	T738
Test name
Test status
Simulation time	2736382441 ps
CPU time	7.33 seconds
Started	Mar 10 12:51:09 PM PDT 24
Finished	Mar 10 12:51:16 PM PDT 24
Peak memory	198728 kb
Host	smart-9daeebf5-0b6a-4c90-9bdb-16e118d8b953
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=142737567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.142737567
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.4148499219
Short name	T345
Test name
Test status
Simulation time	16130530612 ps
CPU time	14.98 seconds
Started	Mar 10 12:51:12 PM PDT 24
Finished	Mar 10 12:51:28 PM PDT 24
Peak memory	199976 kb
Host	smart-d25ffc2d-4896-4f5f-af3a-82d7a2db7df1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148499219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.4148499219
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.3249732769
Short name	T1008
Test name
Test status
Simulation time	4122296501 ps
CPU time	1.79 seconds
Started	Mar 10 12:51:11 PM PDT 24
Finished	Mar 10 12:51:13 PM PDT 24
Peak memory	195860 kb
Host	smart-223f157c-a108-4129-9bf0-ae33e415e1cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249732769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3249732769
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.3988551292
Short name	T434
Test name
Test status
Simulation time	86499550 ps
CPU time	0.97 seconds
Started	Mar 10 12:51:05 PM PDT 24
Finished	Mar 10 12:51:06 PM PDT 24
Peak memory	197636 kb
Host	smart-3a54ade9-ebfe-4a39-8f35-0d1d9b80d5bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988551292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3988551292
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.567406064
Short name	T767
Test name
Test status
Simulation time	852674531 ps
CPU time	3.35 seconds
Started	Mar 10 12:51:11 PM PDT 24
Finished	Mar 10 12:51:15 PM PDT 24
Peak memory	198588 kb
Host	smart-890d11f0-ffdb-402b-84a4-5f4e3dd17551
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567406064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.567406064
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.1463215161
Short name	T1076
Test name
Test status
Simulation time	58036699707 ps
CPU time	38.48 seconds
Started	Mar 10 12:51:07 PM PDT 24
Finished	Mar 10 12:51:45 PM PDT 24
Peak memory	200204 kb
Host	smart-3ca64133-9646-4ddd-a162-2d4d9f941cff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463215161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1463215161
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.1400955535
Short name	T898
Test name
Test status
Simulation time	119877227477 ps
CPU time	84.45 seconds
Started	Mar 10 12:58:26 PM PDT 24
Finished	Mar 10 12:59:51 PM PDT 24
Peak memory	200116 kb
Host	smart-54c8ec74-0b0f-4cb1-9435-4409e4844b03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400955535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1400955535
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.1807096539
Short name	T917
Test name
Test status
Simulation time	35111257434 ps
CPU time	25.57 seconds
Started	Mar 10 12:58:25 PM PDT 24
Finished	Mar 10 12:58:51 PM PDT 24
Peak memory	199736 kb
Host	smart-a6125563-eabc-4141-ab5c-ebf2b165a3f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807096539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1807096539
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.3723738876
Short name	T865
Test name
Test status
Simulation time	43094117554 ps
CPU time	15.68 seconds
Started	Mar 10 12:58:25 PM PDT 24
Finished	Mar 10 12:58:41 PM PDT 24
Peak memory	199720 kb
Host	smart-813db760-d69a-4e13-9c27-b813e6f13552
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723738876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3723738876
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.280305946
Short name	T258
Test name
Test status
Simulation time	13720971334 ps
CPU time	22.61 seconds
Started	Mar 10 12:58:24 PM PDT 24
Finished	Mar 10 12:58:47 PM PDT 24
Peak memory	200124 kb
Host	smart-9a9129ab-193c-4f11-a31c-3dd80829f922
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280305946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.280305946
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.1441178257
Short name	T955
Test name
Test status
Simulation time	20474824733 ps
CPU time	18.23 seconds
Started	Mar 10 12:58:27 PM PDT 24
Finished	Mar 10 12:58:45 PM PDT 24
Peak memory	200160 kb
Host	smart-53c19b20-11dc-4ba1-ae5a-fb3e8cac35fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441178257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1441178257
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.3008342138
Short name	T820
Test name
Test status
Simulation time	7544576530 ps
CPU time	11.52 seconds
Started	Mar 10 12:58:29 PM PDT 24
Finished	Mar 10 12:58:41 PM PDT 24
Peak memory	199812 kb
Host	smart-88824b64-eacf-43da-b753-0241ba6d0f43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008342138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3008342138
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.2468275656
Short name	T863
Test name
Test status
Simulation time	27891610318 ps
CPU time	22.02 seconds
Started	Mar 10 12:58:29 PM PDT 24
Finished	Mar 10 12:58:51 PM PDT 24
Peak memory	200108 kb
Host	smart-c0aa3891-f649-4a50-9d95-6f494cbf13b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468275656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2468275656
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.3980835146
Short name	T264
Test name
Test status
Simulation time	14488835405 ps
CPU time	22.17 seconds
Started	Mar 10 12:58:28 PM PDT 24
Finished	Mar 10 12:58:50 PM PDT 24
Peak memory	200084 kb
Host	smart-748237eb-7a19-4386-808c-edec57fea0e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980835146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3980835146
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.1421567719
Short name	T1006
Test name
Test status
Simulation time	15761240 ps
CPU time	0.55 seconds
Started	Mar 10 12:51:24 PM PDT 24
Finished	Mar 10 12:51:25 PM PDT 24
Peak memory	195444 kb
Host	smart-7910a724-de83-44e8-bf1b-366337dbf07b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421567719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1421567719
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.2014457249
Short name	T452
Test name
Test status
Simulation time	30365381022 ps
CPU time	56.84 seconds
Started	Mar 10 12:51:17 PM PDT 24
Finished	Mar 10 12:52:14 PM PDT 24
Peak memory	200144 kb
Host	smart-3bf530e8-152a-4021-ae6d-1cc637664e97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014457249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2014457249
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.4016583300
Short name	T134
Test name
Test status
Simulation time	54430954630 ps
CPU time	33.91 seconds
Started	Mar 10 12:51:16 PM PDT 24
Finished	Mar 10 12:51:50 PM PDT 24
Peak memory	199764 kb
Host	smart-182b206a-4e18-4257-8a63-1148f1d4945d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016583300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4016583300
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.3454702167
Short name	T247
Test name
Test status
Simulation time	76163980518 ps
CPU time	55.23 seconds
Started	Mar 10 12:51:21 PM PDT 24
Finished	Mar 10 12:52:16 PM PDT 24
Peak memory	200228 kb
Host	smart-ffa36fac-5ea6-4185-b95c-383219bf0dac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454702167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3454702167
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_intr.4136241748
Short name	T1111
Test name
Test status
Simulation time	98531022480 ps
CPU time	168.51 seconds
Started	Mar 10 12:51:21 PM PDT 24
Finished	Mar 10 12:54:10 PM PDT 24
Peak memory	200164 kb
Host	smart-b615b906-0c08-4147-b3af-de37ed435f23
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136241748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4136241748
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.2942634201
Short name	T778
Test name
Test status
Simulation time	141593976378 ps
CPU time	240.8 seconds
Started	Mar 10 12:51:25 PM PDT 24
Finished	Mar 10 12:55:26 PM PDT 24
Peak memory	200204 kb
Host	smart-3ae0e292-2c30-4f4c-97ac-07107c01979e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2942634201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2942634201
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/19.uart_loopback.1854797533
Short name	T26
Test name
Test status
Simulation time	3428830877 ps
CPU time	2.37 seconds
Started	Mar 10 12:51:24 PM PDT 24
Finished	Mar 10 12:51:27 PM PDT 24
Peak memory	198856 kb
Host	smart-932f1730-0e37-4437-9aab-788023b1b284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854797533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1854797533
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.1835980133
Short name	T592
Test name
Test status
Simulation time	96655617020 ps
CPU time	207.77 seconds
Started	Mar 10 12:51:23 PM PDT 24
Finished	Mar 10 12:54:51 PM PDT 24
Peak memory	208528 kb
Host	smart-ef50cc74-5e92-439c-99e7-5b3083ad72d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835980133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1835980133
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/19.uart_perf.3810543137
Short name	T663
Test name
Test status
Simulation time	23458189654 ps
CPU time	1381.37 seconds
Started	Mar 10 12:51:25 PM PDT 24
Finished	Mar 10 01:14:27 PM PDT 24
Peak memory	200032 kb
Host	smart-f6fd72ec-5d8c-48aa-b197-1e7ae6e74cb9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3810543137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3810543137
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.345261552
Short name	T523
Test name
Test status
Simulation time	2677808828 ps
CPU time	5.6 seconds
Started	Mar 10 12:51:22 PM PDT 24
Finished	Mar 10 12:51:28 PM PDT 24
Peak memory	198128 kb
Host	smart-3c1e5b8a-3f7a-49a3-b999-f48682e7393a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=345261552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.345261552
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.335041518
Short name	T360
Test name
Test status
Simulation time	17345394316 ps
CPU time	28.18 seconds
Started	Mar 10 12:51:25 PM PDT 24
Finished	Mar 10 12:51:54 PM PDT 24
Peak memory	200068 kb
Host	smart-da6fa91b-81bb-43b7-8862-0c97e6195e97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335041518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.335041518
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.1926929654
Short name	T969
Test name
Test status
Simulation time	49300625849 ps
CPU time	7.7 seconds
Started	Mar 10 12:51:23 PM PDT 24
Finished	Mar 10 12:51:31 PM PDT 24
Peak memory	195548 kb
Host	smart-4c77da34-9a78-4c22-8f22-da7422ad7dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926929654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1926929654
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.1342015313
Short name	T665
Test name
Test status
Simulation time	700036263 ps
CPU time	2.01 seconds
Started	Mar 10 12:51:16 PM PDT 24
Finished	Mar 10 12:51:18 PM PDT 24
Peak memory	198444 kb
Host	smart-3802d8e4-3329-4d9e-81d0-043114bcb17f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342015313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1342015313
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.3087202555
Short name	T913
Test name
Test status
Simulation time	1100969717 ps
CPU time	3.14 seconds
Started	Mar 10 12:51:24 PM PDT 24
Finished	Mar 10 12:51:28 PM PDT 24
Peak memory	199436 kb
Host	smart-a93edec1-869f-415b-82ef-f132b82a742e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087202555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3087202555
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.1450839888
Short name	T662
Test name
Test status
Simulation time	162538843851 ps
CPU time	251.1 seconds
Started	Mar 10 12:51:15 PM PDT 24
Finished	Mar 10 12:55:27 PM PDT 24
Peak memory	200132 kb
Host	smart-7015b50e-eb7a-46d0-a2e3-3d38c1d9ac49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450839888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1450839888
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.3808959625
Short name	T987
Test name
Test status
Simulation time	84152874158 ps
CPU time	32.28 seconds
Started	Mar 10 12:58:35 PM PDT 24
Finished	Mar 10 12:59:08 PM PDT 24
Peak memory	199116 kb
Host	smart-ee301dd4-b02b-40f3-b9a3-d38125e99bc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808959625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3808959625
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.4069011025
Short name	T1113
Test name
Test status
Simulation time	114747034293 ps
CPU time	42.08 seconds
Started	Mar 10 12:58:34 PM PDT 24
Finished	Mar 10 12:59:16 PM PDT 24
Peak memory	200100 kb
Host	smart-a01fb7a1-2b30-4ce5-ac49-e2075765d6da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4069011025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4069011025
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.1444969425
Short name	T311
Test name
Test status
Simulation time	101222201453 ps
CPU time	48.52 seconds
Started	Mar 10 12:58:35 PM PDT 24
Finished	Mar 10 12:59:24 PM PDT 24
Peak memory	200136 kb
Host	smart-7081c4de-df8f-4290-acd6-60670d09b79b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444969425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1444969425
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.1914166389
Short name	T329
Test name
Test status
Simulation time	258458392041 ps
CPU time	36.57 seconds
Started	Mar 10 12:58:40 PM PDT 24
Finished	Mar 10 12:59:17 PM PDT 24
Peak memory	199772 kb
Host	smart-77374b8e-fd34-405c-8856-c58493092822
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914166389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1914166389
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.1697550716
Short name	T981
Test name
Test status
Simulation time	54950098171 ps
CPU time	22.04 seconds
Started	Mar 10 12:58:40 PM PDT 24
Finished	Mar 10 12:59:02 PM PDT 24
Peak memory	199660 kb
Host	smart-cb092be6-f59c-4f0f-9fd9-5d3b4ad28a0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697550716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1697550716
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.2694641595
Short name	T292
Test name
Test status
Simulation time	67164485071 ps
CPU time	25.89 seconds
Started	Mar 10 12:58:40 PM PDT 24
Finished	Mar 10 12:59:06 PM PDT 24
Peak memory	200220 kb
Host	smart-104aeb31-b77d-4dbc-adaa-eab6703147e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694641595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2694641595
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.2709120469
Short name	T887
Test name
Test status
Simulation time	19942089 ps
CPU time	0.53 seconds
Started	Mar 10 12:48:30 PM PDT 24
Finished	Mar 10 12:48:31 PM PDT 24
Peak memory	195420 kb
Host	smart-05ec035c-8ddd-4260-b207-26fd862e36d3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709120469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2709120469
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.1740520560
Short name	T124
Test name
Test status
Simulation time	269064881163 ps
CPU time	82.93 seconds
Started	Mar 10 12:48:19 PM PDT 24
Finished	Mar 10 12:49:42 PM PDT 24
Peak memory	200084 kb
Host	smart-6e56501e-12a1-4fd3-8f2e-ea110efa2e72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740520560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1740520560
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.3305870244
Short name	T265
Test name
Test status
Simulation time	116680202522 ps
CPU time	51.3 seconds
Started	Mar 10 12:48:21 PM PDT 24
Finished	Mar 10 12:49:13 PM PDT 24
Peak memory	200032 kb
Host	smart-229a75c6-00d6-4ce2-b7c6-e8325d4d9899
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305870244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3305870244
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.1276193437
Short name	T270
Test name
Test status
Simulation time	39844742234 ps
CPU time	65.67 seconds
Started	Mar 10 12:48:21 PM PDT 24
Finished	Mar 10 12:49:27 PM PDT 24
Peak memory	199840 kb
Host	smart-3c4c4ad9-3ffe-47eb-aad4-ea09f15b5bcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276193437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1276193437
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_intr.2351319742
Short name	T866
Test name
Test status
Simulation time	73575594016 ps
CPU time	23.34 seconds
Started	Mar 10 12:48:19 PM PDT 24
Finished	Mar 10 12:48:44 PM PDT 24
Peak memory	198760 kb
Host	smart-0f4420e6-521c-41d1-ac3f-8454a12237c8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351319742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2351319742
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.1521365584
Short name	T575
Test name
Test status
Simulation time	120059711546 ps
CPU time	223.7 seconds
Started	Mar 10 12:48:26 PM PDT 24
Finished	Mar 10 12:52:09 PM PDT 24
Peak memory	200160 kb
Host	smart-f7494afe-6cb2-409e-84b3-acb51568e289
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1521365584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1521365584
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.411595568
Short name	T433
Test name
Test status
Simulation time	7480575761 ps
CPU time	2.44 seconds
Started	Mar 10 12:48:24 PM PDT 24
Finished	Mar 10 12:48:27 PM PDT 24
Peak memory	197664 kb
Host	smart-84056601-aa5d-4fe3-af45-89c614a35c1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411595568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.411595568
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.786046052
Short name	T995
Test name
Test status
Simulation time	166294728635 ps
CPU time	73.18 seconds
Started	Mar 10 12:48:23 PM PDT 24
Finished	Mar 10 12:49:37 PM PDT 24
Peak memory	198924 kb
Host	smart-d54b38b2-3bf9-45a8-92a0-2c15c8813182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786046052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.786046052
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.637050034
Short name	T1079
Test name
Test status
Simulation time	17979369947 ps
CPU time	487.1 seconds
Started	Mar 10 12:48:26 PM PDT 24
Finished	Mar 10 12:56:33 PM PDT 24
Peak memory	200108 kb
Host	smart-fba19132-4222-481c-a306-ac995524c4ec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=637050034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.637050034
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.2618755092
Short name	T459
Test name
Test status
Simulation time	2533860997 ps
CPU time	3.25 seconds
Started	Mar 10 12:48:20 PM PDT 24
Finished	Mar 10 12:48:24 PM PDT 24
Peak memory	198604 kb
Host	smart-c0e223e3-72f9-46bf-8bb5-76dcce6d07c3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2618755092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2618755092
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.1510784502
Short name	T350
Test name
Test status
Simulation time	23028990865 ps
CPU time	14.8 seconds
Started	Mar 10 12:48:25 PM PDT 24
Finished	Mar 10 12:48:40 PM PDT 24
Peak memory	200140 kb
Host	smart-058773b4-94a3-4612-a011-a16da17a1f1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510784502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1510784502
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.2283758658
Short name	T443
Test name
Test status
Simulation time	4962282928 ps
CPU time	4.07 seconds
Started	Mar 10 12:48:25 PM PDT 24
Finished	Mar 10 12:48:29 PM PDT 24
Peak memory	195844 kb
Host	smart-91b0bc7d-ab44-4ee7-803e-208d959eb30c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283758658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2283758658
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.2142694927
Short name	T32
Test name
Test status
Simulation time	52845429 ps
CPU time	0.8 seconds
Started	Mar 10 12:48:32 PM PDT 24
Finished	Mar 10 12:48:34 PM PDT 24
Peak memory	217268 kb
Host	smart-eb01abaf-9f9d-4e19-9d6e-5bde01c1d763
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142694927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2142694927
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/2.uart_smoke.1670301518
Short name	T827
Test name
Test status
Simulation time	515236126 ps
CPU time	1.41 seconds
Started	Mar 10 12:48:19 PM PDT 24
Finished	Mar 10 12:48:22 PM PDT 24
Peak memory	199860 kb
Host	smart-c8ab779b-1a28-4109-b1ae-0422a855d126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670301518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1670301518
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_stress_all.2850267444
Short name	T1064
Test name
Test status
Simulation time	293646042116 ps
CPU time	159.78 seconds
Started	Mar 10 12:48:30 PM PDT 24
Finished	Mar 10 12:51:11 PM PDT 24
Peak memory	215836 kb
Host	smart-9c217909-995b-4299-a006-9ffcb398cdf3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850267444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2850267444
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.3500650780
Short name	T512
Test name
Test status
Simulation time	6516445203 ps
CPU time	10.6 seconds
Started	Mar 10 12:48:26 PM PDT 24
Finished	Mar 10 12:48:37 PM PDT 24
Peak memory	199808 kb
Host	smart-e34ffd44-6a75-476e-9dda-7c88162f34fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500650780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3500650780
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.3170205529
Short name	T893
Test name
Test status
Simulation time	22300954468 ps
CPU time	35.73 seconds
Started	Mar 10 12:48:19 PM PDT 24
Finished	Mar 10 12:48:55 PM PDT 24
Peak memory	200044 kb
Host	smart-01e48d27-3c0a-4901-b52f-01888e8266da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170205529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3170205529
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_alert_test.3425723457
Short name	T1080
Test name
Test status
Simulation time	15115697 ps
CPU time	0.57 seconds
Started	Mar 10 12:51:36 PM PDT 24
Finished	Mar 10 12:51:37 PM PDT 24
Peak memory	195548 kb
Host	smart-a463b538-774d-40d2-9551-2b83ccd4364f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425723457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3425723457
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.4137136908
Short name	T1023
Test name
Test status
Simulation time	161385865806 ps
CPU time	107.37 seconds
Started	Mar 10 12:51:26 PM PDT 24
Finished	Mar 10 12:53:15 PM PDT 24
Peak memory	200168 kb
Host	smart-aba632a4-db67-450c-b421-5eabb66c0363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137136908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4137136908
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.1336588711
Short name	T1051
Test name
Test status
Simulation time	99179064232 ps
CPU time	15.33 seconds
Started	Mar 10 12:51:30 PM PDT 24
Finished	Mar 10 12:51:46 PM PDT 24
Peak memory	200076 kb
Host	smart-f701670a-98ab-4083-a74a-3b13fd16acca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336588711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1336588711
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.3568596582
Short name	T162
Test name
Test status
Simulation time	20094130396 ps
CPU time	17.59 seconds
Started	Mar 10 12:51:31 PM PDT 24
Finished	Mar 10 12:51:49 PM PDT 24
Peak memory	199800 kb
Host	smart-31fcfb85-18ba-4ee9-88c5-0e868679832b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568596582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3568596582
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_intr.3986597863
Short name	T1021
Test name
Test status
Simulation time	42362538008 ps
CPU time	73.83 seconds
Started	Mar 10 12:51:35 PM PDT 24
Finished	Mar 10 12:52:50 PM PDT 24
Peak memory	199132 kb
Host	smart-1a7f8069-5364-4d85-8251-5148daacbf16
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986597863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3986597863
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.1932488998
Short name	T387
Test name
Test status
Simulation time	41430669443 ps
CPU time	184.56 seconds
Started	Mar 10 12:51:35 PM PDT 24
Finished	Mar 10 12:54:41 PM PDT 24
Peak memory	199856 kb
Host	smart-a394bef0-8a69-40ab-bc5a-b6c81846e5ae
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1932488998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1932488998
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.3641601759
Short name	T795
Test name
Test status
Simulation time	46578459 ps
CPU time	0.63 seconds
Started	Mar 10 12:51:35 PM PDT 24
Finished	Mar 10 12:51:37 PM PDT 24
Peak memory	195428 kb
Host	smart-c2d6a3a3-3977-458f-b982-ff9fe58c2de8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641601759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3641601759
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.3872346164
Short name	T539
Test name
Test status
Simulation time	24437201974 ps
CPU time	40.53 seconds
Started	Mar 10 12:51:35 PM PDT 24
Finished	Mar 10 12:52:17 PM PDT 24
Peak memory	198840 kb
Host	smart-51cb7dd5-02a8-4576-80b1-98c18d086844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872346164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3872346164
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.2621703865
Short name	T768
Test name
Test status
Simulation time	5183390529 ps
CPU time	115.32 seconds
Started	Mar 10 12:51:37 PM PDT 24
Finished	Mar 10 12:53:33 PM PDT 24
Peak memory	200084 kb
Host	smart-ca126704-6360-401d-8ec9-393e8664a0f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2621703865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2621703865
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.3359194223
Short name	T732
Test name
Test status
Simulation time	5022366172 ps
CPU time	35.35 seconds
Started	Mar 10 12:51:31 PM PDT 24
Finished	Mar 10 12:52:08 PM PDT 24
Peak memory	198860 kb
Host	smart-25249699-a254-4012-a073-c61d4a97422f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3359194223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3359194223
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.3328600661
Short name	T733
Test name
Test status
Simulation time	136618751834 ps
CPU time	237.07 seconds
Started	Mar 10 12:51:34 PM PDT 24
Finished	Mar 10 12:55:33 PM PDT 24
Peak memory	200160 kb
Host	smart-600fb69e-4716-4c09-8d6f-d428d206cb14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328600661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3328600661
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.13994707
Short name	T1063
Test name
Test status
Simulation time	4482794843 ps
CPU time	1.12 seconds
Started	Mar 10 12:51:35 PM PDT 24
Finished	Mar 10 12:51:38 PM PDT 24
Peak memory	195948 kb
Host	smart-fa88844d-9c89-4bd2-9fed-8e12bb5dd95b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13994707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.13994707
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.1740788132
Short name	T901
Test name
Test status
Simulation time	527325862 ps
CPU time	1.28 seconds
Started	Mar 10 12:51:26 PM PDT 24
Finished	Mar 10 12:51:29 PM PDT 24
Peak memory	198320 kb
Host	smart-1c086bb3-52db-4beb-b5bf-15c642816bf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740788132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1740788132
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.100598203
Short name	T739
Test name
Test status
Simulation time	320281949603 ps
CPU time	1162.39 seconds
Started	Mar 10 12:51:36 PM PDT 24
Finished	Mar 10 01:11:00 PM PDT 24
Peak memory	208560 kb
Host	smart-b2e3f5a2-d138-4988-a376-b125143239fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100598203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.100598203
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_stress_all_with_rand_reset.1331385705
Short name	T791
Test name
Test status
Simulation time	69379187992 ps
CPU time	177.13 seconds
Started	Mar 10 12:51:35 PM PDT 24
Finished	Mar 10 12:54:34 PM PDT 24
Peak memory	215984 kb
Host	smart-0e75454f-ec16-457a-96e3-9ea84c5d2f45
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331385705 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1331385705
Directory	/workspace/20.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.4287176739
Short name	T588
Test name
Test status
Simulation time	947111849 ps
CPU time	1.57 seconds
Started	Mar 10 12:51:36 PM PDT 24
Finished	Mar 10 12:51:39 PM PDT 24
Peak memory	196576 kb
Host	smart-6798ec09-aece-452c-ad78-551030790aa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287176739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4287176739
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.1042169672
Short name	T723
Test name
Test status
Simulation time	18419305319 ps
CPU time	13.86 seconds
Started	Mar 10 12:51:27 PM PDT 24
Finished	Mar 10 12:51:42 PM PDT 24
Peak memory	196156 kb
Host	smart-a8df2424-aa03-491f-8ff4-97a32e9bcb31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042169672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1042169672
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.1073840032
Short name	T237
Test name
Test status
Simulation time	110616675318 ps
CPU time	17.96 seconds
Started	Mar 10 12:58:41 PM PDT 24
Finished	Mar 10 12:58:59 PM PDT 24
Peak memory	200088 kb
Host	smart-069458a7-6457-41c5-b9c9-d75aa134164d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073840032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1073840032
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.3253195243
Short name	T1030
Test name
Test status
Simulation time	133425968252 ps
CPU time	31.06 seconds
Started	Mar 10 12:58:43 PM PDT 24
Finished	Mar 10 12:59:15 PM PDT 24
Peak memory	199468 kb
Host	smart-10a095f2-c28c-490c-a031-441e42b3d974
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253195243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3253195243
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.1003046191
Short name	T254
Test name
Test status
Simulation time	31983816862 ps
CPU time	50.49 seconds
Started	Mar 10 12:58:44 PM PDT 24
Finished	Mar 10 12:59:35 PM PDT 24
Peak memory	200120 kb
Host	smart-6299996e-1e8f-40be-b0c3-d0662ec38a21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003046191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1003046191
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.3848764295
Short name	T872
Test name
Test status
Simulation time	20101607533 ps
CPU time	35.87 seconds
Started	Mar 10 12:58:43 PM PDT 24
Finished	Mar 10 12:59:20 PM PDT 24
Peak memory	200068 kb
Host	smart-af0a8543-5c44-466f-af50-1f27c55f7105
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848764295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3848764295
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.2117460482
Short name	T228
Test name
Test status
Simulation time	229414139766 ps
CPU time	401.1 seconds
Started	Mar 10 12:58:51 PM PDT 24
Finished	Mar 10 01:05:32 PM PDT 24
Peak memory	200032 kb
Host	smart-cae34fa9-6b0d-4383-b7e6-ea1a9ddf99df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117460482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2117460482
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.1623717212
Short name	T136
Test name
Test status
Simulation time	54168819300 ps
CPU time	21.47 seconds
Started	Mar 10 12:58:50 PM PDT 24
Finished	Mar 10 12:59:12 PM PDT 24
Peak memory	199848 kb
Host	smart-e43d0fb4-6c62-4735-b2c1-e09292e99589
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623717212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1623717212
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.441852479
Short name	T503
Test name
Test status
Simulation time	56410843959 ps
CPU time	35.82 seconds
Started	Mar 10 12:58:49 PM PDT 24
Finished	Mar 10 12:59:25 PM PDT 24
Peak memory	200192 kb
Host	smart-ef963b93-6b7f-44a7-80d1-dee167a932e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441852479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.441852479
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.1138000785
Short name	T220
Test name
Test status
Simulation time	57501616459 ps
CPU time	92.21 seconds
Started	Mar 10 12:58:49 PM PDT 24
Finished	Mar 10 01:00:22 PM PDT 24
Peak memory	200124 kb
Host	smart-8f6319ce-d87c-4f8f-98d4-8c95b80d3ab0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138000785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1138000785
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.3760722876
Short name	T990
Test name
Test status
Simulation time	15543936653 ps
CPU time	27.28 seconds
Started	Mar 10 12:58:50 PM PDT 24
Finished	Mar 10 12:59:17 PM PDT 24
Peak memory	199696 kb
Host	smart-687286f7-6129-4c96-b164-2fb8d23972ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760722876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3760722876
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.2127891469
Short name	T445
Test name
Test status
Simulation time	20565220 ps
CPU time	0.54 seconds
Started	Mar 10 12:51:48 PM PDT 24
Finished	Mar 10 12:51:49 PM PDT 24
Peak memory	195464 kb
Host	smart-477078c7-05c7-42f6-885b-bb1fd711d4f1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127891469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2127891469
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.3819862033
Short name	T288
Test name
Test status
Simulation time	150701978091 ps
CPU time	18.63 seconds
Started	Mar 10 12:51:35 PM PDT 24
Finished	Mar 10 12:51:55 PM PDT 24
Peak memory	200008 kb
Host	smart-43e78a55-0d98-4c46-9619-ac72c68c17a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819862033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3819862033
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.1087609885
Short name	T367
Test name
Test status
Simulation time	210125293832 ps
CPU time	30.19 seconds
Started	Mar 10 12:51:40 PM PDT 24
Finished	Mar 10 12:52:10 PM PDT 24
Peak memory	200124 kb
Host	smart-8fcf4c65-9ff6-41b5-b4cf-93bdbedfd585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087609885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1087609885
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_intr.2316425597
Short name	T900
Test name
Test status
Simulation time	121043699833 ps
CPU time	109.04 seconds
Started	Mar 10 12:51:40 PM PDT 24
Finished	Mar 10 12:53:29 PM PDT 24
Peak memory	200076 kb
Host	smart-b61f8828-652e-4dec-b5f8-a9f38818c241
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316425597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2316425597
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.2122636786
Short name	T585
Test name
Test status
Simulation time	288041953718 ps
CPU time	271.21 seconds
Started	Mar 10 12:51:46 PM PDT 24
Finished	Mar 10 12:56:17 PM PDT 24
Peak memory	200148 kb
Host	smart-e57db1c1-5a21-48d0-b3da-1f7b08cb0a67
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2122636786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2122636786
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.3852465965
Short name	T1062
Test name
Test status
Simulation time	1493958880 ps
CPU time	2.33 seconds
Started	Mar 10 12:51:40 PM PDT 24
Finished	Mar 10 12:51:43 PM PDT 24
Peak memory	197284 kb
Host	smart-a3ef3145-6d8c-46be-b587-7096e6623e38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852465965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3852465965
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.190629111
Short name	T109
Test name
Test status
Simulation time	27077788130 ps
CPU time	25.75 seconds
Started	Mar 10 12:51:41 PM PDT 24
Finished	Mar 10 12:52:07 PM PDT 24
Peak memory	198460 kb
Host	smart-ac1fd375-7e7c-44d7-a4f8-e33bb399391d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190629111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.190629111
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_perf.805008732
Short name	T717
Test name
Test status
Simulation time	6736559520 ps
CPU time	86.09 seconds
Started	Mar 10 12:51:42 PM PDT 24
Finished	Mar 10 12:53:08 PM PDT 24
Peak memory	199816 kb
Host	smart-3131ec83-60e1-4a1a-86b6-8605724a0e5d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=805008732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.805008732
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.2176498128
Short name	T596
Test name
Test status
Simulation time	2226657568 ps
CPU time	3.28 seconds
Started	Mar 10 12:51:39 PM PDT 24
Finished	Mar 10 12:51:42 PM PDT 24
Peak memory	197904 kb
Host	smart-2bbe2582-32da-4b98-b4f5-0ff4f3f3af6c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2176498128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2176498128
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.4280061436
Short name	T1038
Test name
Test status
Simulation time	43079956629 ps
CPU time	16.33 seconds
Started	Mar 10 12:51:40 PM PDT 24
Finished	Mar 10 12:51:57 PM PDT 24
Peak memory	199156 kb
Host	smart-fe1d150e-73ca-45ab-90d5-c58e24eb547f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280061436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4280061436
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.1072715225
Short name	T837
Test name
Test status
Simulation time	2917120966 ps
CPU time	5.27 seconds
Started	Mar 10 12:51:39 PM PDT 24
Finished	Mar 10 12:51:45 PM PDT 24
Peak memory	195544 kb
Host	smart-8a679786-991e-4e28-8648-b7f70ba581b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072715225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1072715225
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.1614140467
Short name	T945
Test name
Test status
Simulation time	10577632565 ps
CPU time	39.9 seconds
Started	Mar 10 12:51:39 PM PDT 24
Finished	Mar 10 12:52:19 PM PDT 24
Peak memory	199828 kb
Host	smart-138236bd-1161-4397-b937-a6a526145e58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614140467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1614140467
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_stress_all.2702037952
Short name	T107
Test name
Test status
Simulation time	7141909244 ps
CPU time	13.69 seconds
Started	Mar 10 12:51:46 PM PDT 24
Finished	Mar 10 12:52:00 PM PDT 24
Peak memory	199900 kb
Host	smart-fe46f707-f9b9-4d40-8fb7-f11df33e014a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702037952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2702037952
Directory	/workspace/21.uart_stress_all/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.1495362587
Short name	T1094
Test name
Test status
Simulation time	1435100569 ps
CPU time	2.34 seconds
Started	Mar 10 12:51:40 PM PDT 24
Finished	Mar 10 12:51:42 PM PDT 24
Peak memory	198344 kb
Host	smart-31343915-f153-44e9-9322-2762d73ac230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495362587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1495362587
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.4182182543
Short name	T755
Test name
Test status
Simulation time	96576957872 ps
CPU time	115.79 seconds
Started	Mar 10 12:51:39 PM PDT 24
Finished	Mar 10 12:53:35 PM PDT 24
Peak memory	200076 kb
Host	smart-a872472b-5820-4a44-bb60-884e202a8535
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182182543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.4182182543
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.3466357867
Short name	T51
Test name
Test status
Simulation time	33932490252 ps
CPU time	65.73 seconds
Started	Mar 10 12:58:49 PM PDT 24
Finished	Mar 10 12:59:55 PM PDT 24
Peak memory	200008 kb
Host	smart-1dfc4ff6-3e28-4a70-8abd-5bcca32fc4de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466357867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3466357867
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.2510142718
Short name	T96
Test name
Test status
Simulation time	85110733934 ps
CPU time	129.56 seconds
Started	Mar 10 12:58:54 PM PDT 24
Finished	Mar 10 01:01:04 PM PDT 24
Peak memory	200036 kb
Host	smart-15d6d67b-f516-420a-a8b3-55bcfb22e4ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510142718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2510142718
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.1006148023
Short name	T227
Test name
Test status
Simulation time	17827888146 ps
CPU time	11.35 seconds
Started	Mar 10 12:58:54 PM PDT 24
Finished	Mar 10 12:59:06 PM PDT 24
Peak memory	200072 kb
Host	smart-3ec1ce3c-2dba-4b3e-973a-d9d79e906eed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006148023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1006148023
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.2755218111
Short name	T999
Test name
Test status
Simulation time	6124568383 ps
CPU time	10.39 seconds
Started	Mar 10 12:58:56 PM PDT 24
Finished	Mar 10 12:59:06 PM PDT 24
Peak memory	197708 kb
Host	smart-0173521b-1284-4360-808a-20d0d41bca17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755218111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2755218111
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.454017055
Short name	T276
Test name
Test status
Simulation time	49700982848 ps
CPU time	21.44 seconds
Started	Mar 10 12:58:56 PM PDT 24
Finished	Mar 10 12:59:17 PM PDT 24
Peak memory	200112 kb
Host	smart-3f782a86-0898-44b8-8976-2604edba3648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454017055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.454017055
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.169073326
Short name	T244
Test name
Test status
Simulation time	31814515603 ps
CPU time	51.25 seconds
Started	Mar 10 12:58:56 PM PDT 24
Finished	Mar 10 12:59:47 PM PDT 24
Peak memory	200136 kb
Host	smart-af86dd1b-c1cb-447b-8667-d930be62054c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169073326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.169073326
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.1292218425
Short name	T208
Test name
Test status
Simulation time	172758186665 ps
CPU time	66.68 seconds
Started	Mar 10 12:58:54 PM PDT 24
Finished	Mar 10 01:00:01 PM PDT 24
Peak memory	199976 kb
Host	smart-7bb6cce7-4fad-40b2-be40-e76b0e3c5b27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292218425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1292218425
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.667433041
Short name	T868
Test name
Test status
Simulation time	37128037 ps
CPU time	0.56 seconds
Started	Mar 10 12:51:58 PM PDT 24
Finished	Mar 10 12:51:59 PM PDT 24
Peak memory	195416 kb
Host	smart-0fdc7dbc-32df-403f-bf98-2564fb5cff77
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667433041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.667433041
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.1582720963
Short name	T802
Test name
Test status
Simulation time	67433690894 ps
CPU time	27.93 seconds
Started	Mar 10 12:51:46 PM PDT 24
Finished	Mar 10 12:52:14 PM PDT 24
Peak memory	200020 kb
Host	smart-34c1df44-1bfe-4b88-bde3-fdeb4a7de604
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582720963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1582720963
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.2579252759
Short name	T635
Test name
Test status
Simulation time	160308600468 ps
CPU time	247.59 seconds
Started	Mar 10 12:51:46 PM PDT 24
Finished	Mar 10 12:55:54 PM PDT 24
Peak memory	199092 kb
Host	smart-d59e4abe-fccd-4abf-8e8b-672e87f04d01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579252759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2579252759
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.1983603019
Short name	T641
Test name
Test status
Simulation time	59542648975 ps
CPU time	115.06 seconds
Started	Mar 10 12:51:46 PM PDT 24
Finished	Mar 10 12:53:42 PM PDT 24
Peak memory	200140 kb
Host	smart-a603fc48-7489-4a5c-ab6e-b7d4409d4c64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983603019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1983603019
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.507479505
Short name	T961
Test name
Test status
Simulation time	94725355963 ps
CPU time	174.32 seconds
Started	Mar 10 12:51:52 PM PDT 24
Finished	Mar 10 12:54:47 PM PDT 24
Peak memory	199620 kb
Host	smart-85db86ee-66d1-4baf-8b31-b976a8ec7a09
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507479505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.507479505
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.1481049033
Short name	T576
Test name
Test status
Simulation time	237241989811 ps
CPU time	161.54 seconds
Started	Mar 10 12:51:51 PM PDT 24
Finished	Mar 10 12:54:32 PM PDT 24
Peak memory	200108 kb
Host	smart-6159761b-d397-4ad2-a106-9e6274b1251e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1481049033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1481049033
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.3149975903
Short name	T881
Test name
Test status
Simulation time	2578368789 ps
CPU time	5.1 seconds
Started	Mar 10 12:51:53 PM PDT 24
Finished	Mar 10 12:51:58 PM PDT 24
Peak memory	197592 kb
Host	smart-af347f26-d345-49b8-a793-65d043f0eeed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149975903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3149975903
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.1516040154
Short name	T625
Test name
Test status
Simulation time	50829624024 ps
CPU time	82.75 seconds
Started	Mar 10 12:51:51 PM PDT 24
Finished	Mar 10 12:53:14 PM PDT 24
Peak memory	198288 kb
Host	smart-e3f0e0a2-bdfb-4746-8714-c7edfb4b7832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516040154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1516040154
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.523227325
Short name	T823
Test name
Test status
Simulation time	10205550945 ps
CPU time	622.17 seconds
Started	Mar 10 12:51:52 PM PDT 24
Finished	Mar 10 01:02:14 PM PDT 24
Peak memory	199664 kb
Host	smart-0da314d2-40b1-4c4b-8edb-fe9801039357
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=523227325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.523227325
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.427690465
Short name	T620
Test name
Test status
Simulation time	4643547728 ps
CPU time	8.77 seconds
Started	Mar 10 12:51:46 PM PDT 24
Finished	Mar 10 12:51:55 PM PDT 24
Peak memory	198440 kb
Host	smart-9a105b89-b61e-4ae9-8a7a-28bcf26c1d2f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=427690465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.427690465
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.1483076318
Short name	T263
Test name
Test status
Simulation time	199517782442 ps
CPU time	42.06 seconds
Started	Mar 10 12:51:51 PM PDT 24
Finished	Mar 10 12:52:33 PM PDT 24
Peak memory	199192 kb
Host	smart-a129e60b-56ee-41ff-b01e-49cfbe77acb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483076318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1483076318
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.191616509
Short name	T785
Test name
Test status
Simulation time	51417756813 ps
CPU time	21.47 seconds
Started	Mar 10 12:51:51 PM PDT 24
Finished	Mar 10 12:52:13 PM PDT 24
Peak memory	195856 kb
Host	smart-1793aa8c-f134-4931-8e2d-97f2072516a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191616509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.191616509
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.365894609
Short name	T1
Test name
Test status
Simulation time	521042056 ps
CPU time	1.66 seconds
Started	Mar 10 12:51:48 PM PDT 24
Finished	Mar 10 12:51:50 PM PDT 24
Peak memory	197952 kb
Host	smart-d24069ac-2ee4-437c-922f-342fa0f08b48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365894609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.365894609
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_stress_all.1406153715
Short name	T761
Test name
Test status
Simulation time	531231061865 ps
CPU time	898.61 seconds
Started	Mar 10 12:51:51 PM PDT 24
Finished	Mar 10 01:06:50 PM PDT 24
Peak memory	200160 kb
Host	smart-7a271032-5e4e-4a93-87c7-fbac7f1d733e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406153715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1406153715
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/22.uart_stress_all_with_rand_reset.4062027409
Short name	T104
Test name
Test status
Simulation time	94617527372 ps
CPU time	514.57 seconds
Started	Mar 10 12:51:51 PM PDT 24
Finished	Mar 10 01:00:25 PM PDT 24
Peak memory	225056 kb
Host	smart-14c4072d-f0d6-4ee6-9896-2ee10522648b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062027409 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4062027409
Directory	/workspace/22.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.1489809691
Short name	T44
Test name
Test status
Simulation time	931534561 ps
CPU time	3.2 seconds
Started	Mar 10 12:51:52 PM PDT 24
Finished	Mar 10 12:51:55 PM PDT 24
Peak memory	198532 kb
Host	smart-1da81c77-c023-42f3-9c8c-b3be7e796dcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489809691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1489809691
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.3084775418
Short name	T420
Test name
Test status
Simulation time	10968249187 ps
CPU time	18.56 seconds
Started	Mar 10 12:51:46 PM PDT 24
Finished	Mar 10 12:52:05 PM PDT 24
Peak memory	199816 kb
Host	smart-7d84ba9a-a3a6-4738-bd79-576e2d553b98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084775418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3084775418
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.801886515
Short name	T797
Test name
Test status
Simulation time	61197548090 ps
CPU time	36.29 seconds
Started	Mar 10 12:58:55 PM PDT 24
Finished	Mar 10 12:59:32 PM PDT 24
Peak memory	200104 kb
Host	smart-2e116a5b-f876-4ec4-b824-b967a43e80e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801886515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.801886515
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.3431146988
Short name	T325
Test name
Test status
Simulation time	75506540579 ps
CPU time	32.35 seconds
Started	Mar 10 12:58:56 PM PDT 24
Finished	Mar 10 12:59:28 PM PDT 24
Peak memory	200148 kb
Host	smart-74075ba1-9d37-4327-ac1e-7865339bfb40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431146988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3431146988
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.3169128586
Short name	T309
Test name
Test status
Simulation time	26466811457 ps
CPU time	30.33 seconds
Started	Mar 10 12:58:58 PM PDT 24
Finished	Mar 10 12:59:28 PM PDT 24
Peak memory	200152 kb
Host	smart-4e786b4f-87fd-4033-b3d5-d540ca5d8b5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3169128586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3169128586
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.816223255
Short name	T394
Test name
Test status
Simulation time	56752472940 ps
CPU time	25.24 seconds
Started	Mar 10 12:58:58 PM PDT 24
Finished	Mar 10 12:59:23 PM PDT 24
Peak memory	200148 kb
Host	smart-7ba83e7b-822a-414d-b6f3-04cc1320f1e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816223255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.816223255
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.2706967330
Short name	T862
Test name
Test status
Simulation time	83227170110 ps
CPU time	43.31 seconds
Started	Mar 10 12:59:01 PM PDT 24
Finished	Mar 10 12:59:44 PM PDT 24
Peak memory	199708 kb
Host	smart-73959e1a-49f3-48af-b54d-d3849b8de2db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706967330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2706967330
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.1225792083
Short name	T330
Test name
Test status
Simulation time	20569480499 ps
CPU time	34.54 seconds
Started	Mar 10 12:59:00 PM PDT 24
Finished	Mar 10 12:59:34 PM PDT 24
Peak memory	199820 kb
Host	smart-1b17dfe9-5fb0-4ae0-8ef1-06c15836cf6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225792083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1225792083
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.3057389989
Short name	T560
Test name
Test status
Simulation time	18606473338 ps
CPU time	31.08 seconds
Started	Mar 10 12:58:57 PM PDT 24
Finished	Mar 10 12:59:28 PM PDT 24
Peak memory	200080 kb
Host	smart-8cdd5736-4766-4970-a9bc-368b999c52ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057389989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3057389989
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.2322641753
Short name	T674
Test name
Test status
Simulation time	196467749931 ps
CPU time	269.21 seconds
Started	Mar 10 12:58:58 PM PDT 24
Finished	Mar 10 01:03:28 PM PDT 24
Peak memory	200112 kb
Host	smart-6a5e3c62-de6e-4102-ba4f-ab96fdf41473
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322641753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2322641753
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.1208255819
Short name	T174
Test name
Test status
Simulation time	42781624329 ps
CPU time	17.76 seconds
Started	Mar 10 12:58:58 PM PDT 24
Finished	Mar 10 12:59:16 PM PDT 24
Peak memory	200096 kb
Host	smart-e65e9622-9de0-433f-a4fa-ca8943f0bab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208255819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1208255819
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_alert_test.174864968
Short name	T997
Test name
Test status
Simulation time	12101398 ps
CPU time	0.56 seconds
Started	Mar 10 12:52:03 PM PDT 24
Finished	Mar 10 12:52:03 PM PDT 24
Peak memory	195432 kb
Host	smart-b10327f7-c5a6-4d04-9b4f-0c4bea3e3fdd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174864968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.174864968
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.275543175
Short name	T937
Test name
Test status
Simulation time	29535823559 ps
CPU time	40.97 seconds
Started	Mar 10 12:51:59 PM PDT 24
Finished	Mar 10 12:52:40 PM PDT 24
Peak memory	200080 kb
Host	smart-2647cd67-685f-4244-925e-35bda5c16f15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275543175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.275543175
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.4023333996
Short name	T464
Test name
Test status
Simulation time	138407846711 ps
CPU time	41.48 seconds
Started	Mar 10 12:51:57 PM PDT 24
Finished	Mar 10 12:52:38 PM PDT 24
Peak memory	200068 kb
Host	smart-2cc64c72-6da9-4a65-9384-0bf83f382a83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023333996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4023333996
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.2450120309
Short name	T415
Test name
Test status
Simulation time	242844133198 ps
CPU time	62.82 seconds
Started	Mar 10 12:51:57 PM PDT 24
Finished	Mar 10 12:53:00 PM PDT 24
Peak memory	200124 kb
Host	smart-52a3f6c3-f24a-45bf-a2db-d6ba7b53f7a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450120309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2450120309
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_intr.2124206501
Short name	T948
Test name
Test status
Simulation time	66744363355 ps
CPU time	29.32 seconds
Started	Mar 10 12:51:57 PM PDT 24
Finished	Mar 10 12:52:26 PM PDT 24
Peak memory	199184 kb
Host	smart-f50efb85-7127-44b8-8c77-408b24782d4a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124206501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2124206501
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.152042383
Short name	T828
Test name
Test status
Simulation time	103687940325 ps
CPU time	250.68 seconds
Started	Mar 10 12:52:01 PM PDT 24
Finished	Mar 10 12:56:11 PM PDT 24
Peak memory	200156 kb
Host	smart-f8a50731-ce56-4e76-8724-3d72457740c9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=152042383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.152042383
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.3545019574
Short name	T884
Test name
Test status
Simulation time	4978120417 ps
CPU time	3.05 seconds
Started	Mar 10 12:52:03 PM PDT 24
Finished	Mar 10 12:52:07 PM PDT 24
Peak memory	199628 kb
Host	smart-db155e1d-9bd7-4fac-a8d2-776708044213
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545019574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3545019574
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.1000013137
Short name	T704
Test name
Test status
Simulation time	39645600848 ps
CPU time	18.25 seconds
Started	Mar 10 12:51:57 PM PDT 24
Finished	Mar 10 12:52:15 PM PDT 24
Peak memory	194796 kb
Host	smart-b69535e2-377b-4ebe-a59d-ae2276da715a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000013137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1000013137
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_perf.3270157081
Short name	T396
Test name
Test status
Simulation time	12961454997 ps
CPU time	243.07 seconds
Started	Mar 10 12:52:02 PM PDT 24
Finished	Mar 10 12:56:05 PM PDT 24
Peak memory	200136 kb
Host	smart-1e98193a-08f5-4196-af21-e2a2e672f51d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3270157081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3270157081
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.1578460266
Short name	T489
Test name
Test status
Simulation time	5155361969 ps
CPU time	13.22 seconds
Started	Mar 10 12:51:57 PM PDT 24
Finished	Mar 10 12:52:10 PM PDT 24
Peak memory	198868 kb
Host	smart-f7107809-9ec9-4206-97e9-29da380b7ebc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1578460266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1578460266
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.3214918563
Short name	T165
Test name
Test status
Simulation time	13452209735 ps
CPU time	22.16 seconds
Started	Mar 10 12:52:01 PM PDT 24
Finished	Mar 10 12:52:24 PM PDT 24
Peak memory	199244 kb
Host	smart-6210015f-77a9-424d-82ad-dcc552f72d51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214918563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3214918563
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.3952079497
Short name	T444
Test name
Test status
Simulation time	1592953562 ps
CPU time	3.25 seconds
Started	Mar 10 12:52:01 PM PDT 24
Finished	Mar 10 12:52:05 PM PDT 24
Peak memory	195568 kb
Host	smart-42c3c824-6803-405a-97d4-da8c2216b715
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952079497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3952079497
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.2960617849
Short name	T400
Test name
Test status
Simulation time	793311915 ps
CPU time	1.19 seconds
Started	Mar 10 12:51:58 PM PDT 24
Finished	Mar 10 12:51:59 PM PDT 24
Peak memory	198112 kb
Host	smart-eb6755a8-31bd-4fd7-a9b4-373262913ed7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960617849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2960617849
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.2382713999
Short name	T794
Test name
Test status
Simulation time	7724672156 ps
CPU time	10.59 seconds
Started	Mar 10 12:52:00 PM PDT 24
Finished	Mar 10 12:52:11 PM PDT 24
Peak memory	198800 kb
Host	smart-2541a4e2-df22-4713-b407-5c99e5921844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382713999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2382713999
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.2485447196
Short name	T973
Test name
Test status
Simulation time	62700433071 ps
CPU time	33.97 seconds
Started	Mar 10 12:51:57 PM PDT 24
Finished	Mar 10 12:52:31 PM PDT 24
Peak memory	200020 kb
Host	smart-9f6d819e-dba7-4ccf-b0d6-7ac21b1cff48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485447196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2485447196
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.4075370454
Short name	T108
Test name
Test status
Simulation time	195198609640 ps
CPU time	56.22 seconds
Started	Mar 10 12:59:06 PM PDT 24
Finished	Mar 10 01:00:02 PM PDT 24
Peak memory	200100 kb
Host	smart-c8ca86d8-9122-4e42-86a1-a6d883b6750d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075370454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4075370454
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.3885505111
Short name	T724
Test name
Test status
Simulation time	160385531293 ps
CPU time	142.69 seconds
Started	Mar 10 12:59:04 PM PDT 24
Finished	Mar 10 01:01:27 PM PDT 24
Peak memory	200004 kb
Host	smart-36fdb3c2-9208-4cc6-b660-a233f3ead698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885505111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3885505111
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.794678743
Short name	T922
Test name
Test status
Simulation time	152865516319 ps
CPU time	72.48 seconds
Started	Mar 10 12:59:06 PM PDT 24
Finished	Mar 10 01:00:18 PM PDT 24
Peak memory	200176 kb
Host	smart-2f929256-495f-4a4a-b18d-5f6be0859ea7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=794678743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.794678743
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.2067283425
Short name	T1011
Test name
Test status
Simulation time	9292907080 ps
CPU time	13.98 seconds
Started	Mar 10 12:59:05 PM PDT 24
Finished	Mar 10 12:59:19 PM PDT 24
Peak memory	197412 kb
Host	smart-ef9369cf-6d7f-4c73-bbff-6ec67390e557
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067283425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2067283425
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.2180879727
Short name	T1052
Test name
Test status
Simulation time	13443250218 ps
CPU time	18.03 seconds
Started	Mar 10 12:59:06 PM PDT 24
Finished	Mar 10 12:59:24 PM PDT 24
Peak memory	199876 kb
Host	smart-ad528272-0916-4426-9261-d93c957b3d33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180879727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2180879727
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.4169425024
Short name	T256
Test name
Test status
Simulation time	41626370712 ps
CPU time	17.54 seconds
Started	Mar 10 12:59:10 PM PDT 24
Finished	Mar 10 12:59:28 PM PDT 24
Peak memory	199956 kb
Host	smart-bbdcd86d-5f34-4aa8-9e71-9a7b4666f5e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169425024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4169425024
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.2109480350
Short name	T285
Test name
Test status
Simulation time	28753299251 ps
CPU time	12.59 seconds
Started	Mar 10 12:59:12 PM PDT 24
Finished	Mar 10 12:59:24 PM PDT 24
Peak memory	199736 kb
Host	smart-55b9c90a-9ca1-4a43-af05-979c304cfee7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2109480350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2109480350
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.4035058156
Short name	T578
Test name
Test status
Simulation time	19663802 ps
CPU time	0.56 seconds
Started	Mar 10 12:52:19 PM PDT 24
Finished	Mar 10 12:52:20 PM PDT 24
Peak memory	195376 kb
Host	smart-0fc85ba2-6b96-4cea-ac1b-5a129df1ae5e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035058156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4035058156
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.2349961566
Short name	T513
Test name
Test status
Simulation time	11663404360 ps
CPU time	14.94 seconds
Started	Mar 10 12:52:08 PM PDT 24
Finished	Mar 10 12:52:23 PM PDT 24
Peak memory	199760 kb
Host	smart-0de97ba6-92f4-4efc-a0f5-e442c98acda3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349961566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2349961566
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.3186135329
Short name	T250
Test name
Test status
Simulation time	344501237456 ps
CPU time	35.75 seconds
Started	Mar 10 12:52:08 PM PDT 24
Finished	Mar 10 12:52:44 PM PDT 24
Peak memory	200072 kb
Host	smart-8f0e22ea-07e9-4d7e-85de-0270b3ff713a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186135329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3186135329
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.1765693288
Short name	T1107
Test name
Test status
Simulation time	251417697853 ps
CPU time	107.21 seconds
Started	Mar 10 12:52:06 PM PDT 24
Finished	Mar 10 12:53:53 PM PDT 24
Peak memory	199380 kb
Host	smart-39b0aff9-c552-440d-82e2-1940e8695337
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765693288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1765693288
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_intr.1578878400
Short name	T1031
Test name
Test status
Simulation time	31390359509 ps
CPU time	13.4 seconds
Started	Mar 10 12:52:18 PM PDT 24
Finished	Mar 10 12:52:32 PM PDT 24
Peak memory	198412 kb
Host	smart-bb2c1c02-f77b-41c4-852b-6e5fc4b85ea7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578878400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1578878400
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.1320628537
Short name	T1039
Test name
Test status
Simulation time	134724206947 ps
CPU time	1377.23 seconds
Started	Mar 10 12:52:12 PM PDT 24
Finished	Mar 10 01:15:10 PM PDT 24
Peak memory	200072 kb
Host	smart-65134947-0e1a-491e-96cd-d127b4f8911c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1320628537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1320628537
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/24.uart_loopback.3754354013
Short name	T644
Test name
Test status
Simulation time	7719390308 ps
CPU time	5.93 seconds
Started	Mar 10 12:52:14 PM PDT 24
Finished	Mar 10 12:52:20 PM PDT 24
Peak memory	198700 kb
Host	smart-dfb26527-9cf9-4897-890c-9e88ed64eefb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754354013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3754354013
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.4294479433
Short name	T520
Test name
Test status
Simulation time	31432833252 ps
CPU time	21.9 seconds
Started	Mar 10 12:52:13 PM PDT 24
Finished	Mar 10 12:52:35 PM PDT 24
Peak memory	199024 kb
Host	smart-e938c0ec-da5b-495b-8f93-6ba0393f5a4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294479433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4294479433
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.1182823980
Short name	T648
Test name
Test status
Simulation time	16517629841 ps
CPU time	231.48 seconds
Started	Mar 10 12:52:14 PM PDT 24
Finished	Mar 10 12:56:05 PM PDT 24
Peak memory	200076 kb
Host	smart-18b068b3-e938-4cba-bf6d-aecd73001ab5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1182823980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1182823980
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.3940344251
Short name	T751
Test name
Test status
Simulation time	3547520592 ps
CPU time	12.74 seconds
Started	Mar 10 12:52:11 PM PDT 24
Finished	Mar 10 12:52:24 PM PDT 24
Peak memory	197968 kb
Host	smart-d6ffe9db-ef0e-4956-9ec0-02c27e6689ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3940344251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3940344251
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.3064475388
Short name	T771
Test name
Test status
Simulation time	20044260694 ps
CPU time	23.14 seconds
Started	Mar 10 12:52:11 PM PDT 24
Finished	Mar 10 12:52:34 PM PDT 24
Peak memory	197296 kb
Host	smart-8bd3033f-5c2d-4bba-b81a-fd8a5c7fb43d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064475388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3064475388
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.3317734727
Short name	T1018
Test name
Test status
Simulation time	3118402550 ps
CPU time	2.95 seconds
Started	Mar 10 12:52:12 PM PDT 24
Finished	Mar 10 12:52:15 PM PDT 24
Peak memory	195832 kb
Host	smart-80ead43f-96e4-4916-a84d-33607fba982d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317734727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3317734727
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.1516694296
Short name	T1073
Test name
Test status
Simulation time	5520589810 ps
CPU time	11.18 seconds
Started	Mar 10 12:52:02 PM PDT 24
Finished	Mar 10 12:52:13 PM PDT 24
Peak memory	200116 kb
Host	smart-cd0e0101-1681-435b-ae86-c1e13b7a65a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516694296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1516694296
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all.3471736908
Short name	T556
Test name
Test status
Simulation time	262710624259 ps
CPU time	213.75 seconds
Started	Mar 10 12:52:13 PM PDT 24
Finished	Mar 10 12:55:47 PM PDT 24
Peak memory	208576 kb
Host	smart-77c50580-797d-4f70-a87c-5b31156685c1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471736908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3471736908
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/24.uart_stress_all_with_rand_reset.1789581704
Short name	T33
Test name
Test status
Simulation time	18302376869 ps
CPU time	224.58 seconds
Started	Mar 10 12:52:11 PM PDT 24
Finished	Mar 10 12:55:55 PM PDT 24
Peak memory	216572 kb
Host	smart-5a842b33-9bcc-4e1e-98fb-08b1e8047d25
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789581704 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1789581704
Directory	/workspace/24.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.2172656341
Short name	T721
Test name
Test status
Simulation time	7239824153 ps
CPU time	17.01 seconds
Started	Mar 10 12:52:13 PM PDT 24
Finished	Mar 10 12:52:30 PM PDT 24
Peak memory	199044 kb
Host	smart-a7925ce7-a05d-428a-bcdd-1031bda63e01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172656341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2172656341
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.938906947
Short name	T43
Test name
Test status
Simulation time	23052893218 ps
CPU time	42.26 seconds
Started	Mar 10 12:52:03 PM PDT 24
Finished	Mar 10 12:52:46 PM PDT 24
Peak memory	200088 kb
Host	smart-5c45d868-05ab-41cf-bdff-00f7f203b40e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938906947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.938906947
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.3002744111
Short name	T135
Test name
Test status
Simulation time	115433306677 ps
CPU time	94.3 seconds
Started	Mar 10 12:59:11 PM PDT 24
Finished	Mar 10 01:00:45 PM PDT 24
Peak memory	199092 kb
Host	smart-63d0f43f-8de2-4e06-a0a6-1c6b5f60ceb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002744111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3002744111
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.82023458
Short name	T235
Test name
Test status
Simulation time	91694785127 ps
CPU time	152.27 seconds
Started	Mar 10 12:59:11 PM PDT 24
Finished	Mar 10 01:01:44 PM PDT 24
Peak memory	200128 kb
Host	smart-74d880d9-7a71-4e87-8886-e188bd210e10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82023458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.82023458
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.1434599475
Short name	T879
Test name
Test status
Simulation time	13930494759 ps
CPU time	26.93 seconds
Started	Mar 10 12:59:11 PM PDT 24
Finished	Mar 10 12:59:38 PM PDT 24
Peak memory	200080 kb
Host	smart-9381a33a-2b2a-4d0d-89e6-2a4016a20db5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434599475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1434599475
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.4033057709
Short name	T137
Test name
Test status
Simulation time	25996212566 ps
CPU time	13.36 seconds
Started	Mar 10 12:59:12 PM PDT 24
Finished	Mar 10 12:59:25 PM PDT 24
Peak memory	200116 kb
Host	smart-e00ba981-5f05-42f3-ac2e-0aa2bc32a2bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033057709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4033057709
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.57153781
Short name	T506
Test name
Test status
Simulation time	60809166977 ps
CPU time	20.98 seconds
Started	Mar 10 12:59:16 PM PDT 24
Finished	Mar 10 12:59:37 PM PDT 24
Peak memory	200136 kb
Host	smart-26447868-f84f-4a38-91fe-79ded4ad6c1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57153781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.57153781
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.1664816176
Short name	T97
Test name
Test status
Simulation time	15994442725 ps
CPU time	27.22 seconds
Started	Mar 10 12:59:19 PM PDT 24
Finished	Mar 10 12:59:46 PM PDT 24
Peak memory	200120 kb
Host	smart-7a6be45f-6e59-4a19-983d-f99386557ffb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664816176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1664816176
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.699991041
Short name	T469
Test name
Test status
Simulation time	33190598 ps
CPU time	0.53 seconds
Started	Mar 10 12:52:21 PM PDT 24
Finished	Mar 10 12:52:22 PM PDT 24
Peak memory	194580 kb
Host	smart-8f9a7f55-c5d7-4dc5-8b3a-3a4d1d31c44d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699991041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.699991041
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.2516689429
Short name	T688
Test name
Test status
Simulation time	103268540171 ps
CPU time	153.13 seconds
Started	Mar 10 12:52:22 PM PDT 24
Finished	Mar 10 12:54:55 PM PDT 24
Peak memory	200016 kb
Host	smart-ef77e6b3-1212-4e53-84ab-fed1aa8b2c09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516689429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2516689429
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.1959256988
Short name	T744
Test name
Test status
Simulation time	96295768968 ps
CPU time	31.49 seconds
Started	Mar 10 12:52:21 PM PDT 24
Finished	Mar 10 12:52:53 PM PDT 24
Peak memory	200032 kb
Host	smart-1256c784-c5ea-410e-ba3a-04664dcb5f3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959256988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1959256988
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/25.uart_intr.3320555001
Short name	T908
Test name
Test status
Simulation time	583965112562 ps
CPU time	1143.39 seconds
Started	Mar 10 12:52:18 PM PDT 24
Finished	Mar 10 01:11:22 PM PDT 24
Peak memory	200092 kb
Host	smart-7f9ce908-f20d-4e41-a53a-c2bc3ef0b944
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320555001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3320555001
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.2321977685
Short name	T1074
Test name
Test status
Simulation time	88308574390 ps
CPU time	142.96 seconds
Started	Mar 10 12:52:21 PM PDT 24
Finished	Mar 10 12:54:44 PM PDT 24
Peak memory	200120 kb
Host	smart-73a97219-a258-4fd2-aee6-d79d90a0843a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2321977685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2321977685
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/25.uart_loopback.2593590469
Short name	T915
Test name
Test status
Simulation time	5019190574 ps
CPU time	3.95 seconds
Started	Mar 10 12:52:22 PM PDT 24
Finished	Mar 10 12:52:26 PM PDT 24
Peak memory	199320 kb
Host	smart-457c563a-2388-411d-8af4-4d5d273e64e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593590469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2593590469
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.4232457533
Short name	T793
Test name
Test status
Simulation time	55731426520 ps
CPU time	27.93 seconds
Started	Mar 10 12:52:16 PM PDT 24
Finished	Mar 10 12:52:45 PM PDT 24
Peak memory	197956 kb
Host	smart-6b9a33f6-4b74-414b-91a4-aabb7bdc5906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232457533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.4232457533
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.1533474637
Short name	T566
Test name
Test status
Simulation time	8048253907 ps
CPU time	372.97 seconds
Started	Mar 10 12:52:22 PM PDT 24
Finished	Mar 10 12:58:35 PM PDT 24
Peak memory	199944 kb
Host	smart-5644e52c-2c3e-4fbd-bc58-113db8859ddb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1533474637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1533474637
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.612494591
Short name	T455
Test name
Test status
Simulation time	5991740746 ps
CPU time	64.69 seconds
Started	Mar 10 12:52:22 PM PDT 24
Finished	Mar 10 12:53:27 PM PDT 24
Peak memory	198912 kb
Host	smart-7ab6ab59-5628-4aa2-afb7-ebd6199d2b32
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=612494591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.612494591
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.3628644406
Short name	T818
Test name
Test status
Simulation time	43274771096 ps
CPU time	18.19 seconds
Started	Mar 10 12:52:22 PM PDT 24
Finished	Mar 10 12:52:40 PM PDT 24
Peak memory	199268 kb
Host	smart-855e7c76-970f-4453-b76e-75146bd8d9da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628644406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3628644406
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.1410265891
Short name	T532
Test name
Test status
Simulation time	730694232 ps
CPU time	0.94 seconds
Started	Mar 10 12:52:17 PM PDT 24
Finished	Mar 10 12:52:18 PM PDT 24
Peak memory	195568 kb
Host	smart-2721ac23-60d9-48cc-a78c-f37f358dbb3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410265891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1410265891
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/25.uart_smoke.664498989
Short name	T804
Test name
Test status
Simulation time	5360665416 ps
CPU time	31.96 seconds
Started	Mar 10 12:52:11 PM PDT 24
Finished	Mar 10 12:52:43 PM PDT 24
Peak memory	199940 kb
Host	smart-cbd4ca97-0f20-4c8c-ba42-5f54c56eca6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664498989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.664498989
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_stress_all.1912070550
Short name	T681
Test name
Test status
Simulation time	182926862775 ps
CPU time	478.36 seconds
Started	Mar 10 12:52:24 PM PDT 24
Finished	Mar 10 01:00:22 PM PDT 24
Peak memory	200108 kb
Host	smart-1087dbcf-87f3-4d56-8763-0fadadecb1d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912070550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1912070550
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.1908448470
Short name	T564
Test name
Test status
Simulation time	6789414985 ps
CPU time	17.89 seconds
Started	Mar 10 12:52:21 PM PDT 24
Finished	Mar 10 12:52:39 PM PDT 24
Peak memory	199064 kb
Host	smart-188e2c8c-224c-4052-babb-c8a2b5214ce5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908448470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1908448470
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.2997152908
Short name	T788
Test name
Test status
Simulation time	233014060978 ps
CPU time	99.06 seconds
Started	Mar 10 12:52:27 PM PDT 24
Finished	Mar 10 12:54:06 PM PDT 24
Peak memory	200060 kb
Host	smart-8c214a3b-a9a9-47aa-80c9-aea48519f0a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997152908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2997152908
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.940455636
Short name	T127
Test name
Test status
Simulation time	78244691978 ps
CPU time	81.54 seconds
Started	Mar 10 12:59:17 PM PDT 24
Finished	Mar 10 01:00:38 PM PDT 24
Peak memory	200092 kb
Host	smart-e0d3c5d1-d41f-4325-8683-5cd10bf03c99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940455636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.940455636
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.4137741349
Short name	T392
Test name
Test status
Simulation time	91313816403 ps
CPU time	34.69 seconds
Started	Mar 10 12:59:21 PM PDT 24
Finished	Mar 10 12:59:56 PM PDT 24
Peak memory	199896 kb
Host	smart-a599b240-ded4-4326-85d1-4cdcac48e58a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137741349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4137741349
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.3551253473
Short name	T251
Test name
Test status
Simulation time	21337198591 ps
CPU time	37.72 seconds
Started	Mar 10 12:59:23 PM PDT 24
Finished	Mar 10 01:00:01 PM PDT 24
Peak memory	200040 kb
Host	smart-97ad4fe1-d484-445d-8bc2-b14cd6e5176b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551253473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3551253473
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.1840249708
Short name	T991
Test name
Test status
Simulation time	4882623200 ps
CPU time	8.3 seconds
Started	Mar 10 12:59:22 PM PDT 24
Finished	Mar 10 12:59:30 PM PDT 24
Peak memory	199640 kb
Host	smart-4e1d29ee-512b-4d73-8b95-ede0a6b884d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840249708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1840249708
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.327907291
Short name	T545
Test name
Test status
Simulation time	36329896297 ps
CPU time	39.31 seconds
Started	Mar 10 12:59:23 PM PDT 24
Finished	Mar 10 01:00:02 PM PDT 24
Peak memory	199836 kb
Host	smart-6f35cfbd-ea6a-45dd-a109-e45ec2b0a7ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327907291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.327907291
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.265243963
Short name	T462
Test name
Test status
Simulation time	44086228961 ps
CPU time	33.5 seconds
Started	Mar 10 12:59:20 PM PDT 24
Finished	Mar 10 12:59:54 PM PDT 24
Peak memory	197624 kb
Host	smart-c3c6fbba-ddf7-4a43-810a-aad7480dc0b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265243963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.265243963
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.2122351105
Short name	T224
Test name
Test status
Simulation time	560151386908 ps
CPU time	44.83 seconds
Started	Mar 10 12:59:21 PM PDT 24
Finished	Mar 10 01:00:06 PM PDT 24
Peak memory	200092 kb
Host	smart-26a7b8e9-af84-4d73-b046-2d19050721ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122351105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2122351105
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.3749521915
Short name	T178
Test name
Test status
Simulation time	109161888703 ps
CPU time	36.7 seconds
Started	Mar 10 12:59:21 PM PDT 24
Finished	Mar 10 12:59:58 PM PDT 24
Peak memory	200088 kb
Host	smart-8b0618b8-bcd9-4b82-854e-42ad561b45e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749521915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3749521915
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.1329556925
Short name	T718
Test name
Test status
Simulation time	34455932 ps
CPU time	0.54 seconds
Started	Mar 10 12:52:32 PM PDT 24
Finished	Mar 10 12:52:33 PM PDT 24
Peak memory	194412 kb
Host	smart-ed0734cb-7f46-4ee0-a068-c88c066bc800
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329556925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1329556925
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.1113462779
Short name	T950
Test name
Test status
Simulation time	113768397960 ps
CPU time	53.65 seconds
Started	Mar 10 12:52:21 PM PDT 24
Finished	Mar 10 12:53:15 PM PDT 24
Peak memory	200076 kb
Host	smart-34ac73b1-6fc5-4b0f-b750-dadd621685bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113462779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1113462779
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.329450439
Short name	T336
Test name
Test status
Simulation time	54336349948 ps
CPU time	79.67 seconds
Started	Mar 10 12:52:26 PM PDT 24
Finished	Mar 10 12:53:46 PM PDT 24
Peak memory	199828 kb
Host	smart-b527e5d7-56ea-4318-9557-52dc33b625d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329450439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.329450439
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.681558601
Short name	T883
Test name
Test status
Simulation time	32493791555 ps
CPU time	24.56 seconds
Started	Mar 10 12:52:25 PM PDT 24
Finished	Mar 10 12:52:50 PM PDT 24
Peak memory	200156 kb
Host	smart-8173f84e-b2f0-489d-8d84-7f428b11ff53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681558601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.681558601
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_intr.1193954757
Short name	T636
Test name
Test status
Simulation time	28633373048 ps
CPU time	54.93 seconds
Started	Mar 10 12:52:26 PM PDT 24
Finished	Mar 10 12:53:21 PM PDT 24
Peak memory	199428 kb
Host	smart-2cb799d5-e1c6-4007-af32-1a3b837dd8c5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193954757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1193954757
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.2489150723
Short name	T886
Test name
Test status
Simulation time	101034357418 ps
CPU time	418.07 seconds
Started	Mar 10 12:52:32 PM PDT 24
Finished	Mar 10 12:59:30 PM PDT 24
Peak memory	200072 kb
Host	smart-2756d47a-cbb2-4635-9a10-6c5cc848260a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2489150723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2489150723
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.1101460628
Short name	T463
Test name
Test status
Simulation time	10984309930 ps
CPU time	18.27 seconds
Started	Mar 10 12:52:29 PM PDT 24
Finished	Mar 10 12:52:48 PM PDT 24
Peak memory	198480 kb
Host	smart-877ff477-ce31-4d75-96a1-45dfb7aa2e56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101460628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1101460628
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.1751094926
Short name	T764
Test name
Test status
Simulation time	61152528834 ps
CPU time	93.23 seconds
Started	Mar 10 12:52:27 PM PDT 24
Finished	Mar 10 12:54:00 PM PDT 24
Peak memory	200324 kb
Host	smart-bba0bd5c-270e-4c1a-ab49-407876de13b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751094926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1751094926
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/26.uart_perf.2737459856
Short name	T505
Test name
Test status
Simulation time	25047733477 ps
CPU time	263.54 seconds
Started	Mar 10 12:52:31 PM PDT 24
Finished	Mar 10 12:56:55 PM PDT 24
Peak memory	200060 kb
Host	smart-1c04d94d-2c78-4e68-9d37-e446a869f3bb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2737459856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2737459856
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.4019625506
Short name	T552
Test name
Test status
Simulation time	5589686190 ps
CPU time	44.12 seconds
Started	Mar 10 12:52:30 PM PDT 24
Finished	Mar 10 12:53:15 PM PDT 24
Peak memory	198944 kb
Host	smart-8626493e-6fc7-4193-9503-904c8ec6a102
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4019625506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4019625506
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.2760454261
Short name	T17
Test name
Test status
Simulation time	26886321131 ps
CPU time	37.39 seconds
Started	Mar 10 12:52:25 PM PDT 24
Finished	Mar 10 12:53:03 PM PDT 24
Peak memory	200172 kb
Host	smart-486ac913-f678-42e5-a6f3-da957a36c303
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760454261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2760454261
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.3552261493
Short name	T803
Test name
Test status
Simulation time	4818463895 ps
CPU time	2.5 seconds
Started	Mar 10 12:52:28 PM PDT 24
Finished	Mar 10 12:52:32 PM PDT 24
Peak memory	195976 kb
Host	smart-1cf9cdea-f481-4ff7-857c-25165c4bd65b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552261493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3552261493
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.209464311
Short name	T984
Test name
Test status
Simulation time	491126985 ps
CPU time	1.11 seconds
Started	Mar 10 12:52:27 PM PDT 24
Finished	Mar 10 12:52:29 PM PDT 24
Peak memory	197816 kb
Host	smart-2792d385-16b0-4bbc-92fe-7ecb16309e54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209464311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.209464311
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all_with_rand_reset.385061911
Short name	T929
Test name
Test status
Simulation time	70441437205 ps
CPU time	576.72 seconds
Started	Mar 10 12:52:29 PM PDT 24
Finished	Mar 10 01:02:06 PM PDT 24
Peak memory	216556 kb
Host	smart-304871eb-9414-4ac5-98ee-cce5efd37c00
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385061911 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.385061911
Directory	/workspace/26.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.2177563027
Short name	T550
Test name
Test status
Simulation time	910319633 ps
CPU time	1.48 seconds
Started	Mar 10 12:52:26 PM PDT 24
Finished	Mar 10 12:52:27 PM PDT 24
Peak memory	198560 kb
Host	smart-fc8b2c46-87c8-453f-98ae-fbe42d758166
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2177563027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2177563027
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.3705970099
Short name	T538
Test name
Test status
Simulation time	73931354755 ps
CPU time	33.68 seconds
Started	Mar 10 12:52:21 PM PDT 24
Finished	Mar 10 12:52:55 PM PDT 24
Peak memory	200128 kb
Host	smart-6f364739-6ac3-4419-9a3b-8eb392037df5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705970099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3705970099
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.1669658537
Short name	T253
Test name
Test status
Simulation time	55629427042 ps
CPU time	17.39 seconds
Started	Mar 10 12:59:27 PM PDT 24
Finished	Mar 10 12:59:45 PM PDT 24
Peak memory	200084 kb
Host	smart-6dc882b2-6d20-4e9f-b8d4-73fd6795523e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669658537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1669658537
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.1150889374
Short name	T699
Test name
Test status
Simulation time	53287908487 ps
CPU time	14.49 seconds
Started	Mar 10 12:59:30 PM PDT 24
Finished	Mar 10 12:59:44 PM PDT 24
Peak memory	199620 kb
Host	smart-75b35c90-8c33-4376-9106-da08ea4f3970
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150889374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1150889374
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.1197431079
Short name	T725
Test name
Test status
Simulation time	59314560534 ps
CPU time	48.01 seconds
Started	Mar 10 12:59:30 PM PDT 24
Finished	Mar 10 01:00:18 PM PDT 24
Peak memory	200076 kb
Host	smart-54b585f4-0cab-4329-937c-a1c1965bc9bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197431079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1197431079
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/263.uart_fifo_reset.780976049
Short name	T186
Test name
Test status
Simulation time	177318069907 ps
CPU time	80.42 seconds
Started	Mar 10 12:59:29 PM PDT 24
Finished	Mar 10 01:00:50 PM PDT 24
Peak memory	199724 kb
Host	smart-f6ac16bc-066d-40e3-80b8-9e4ed4ea846b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780976049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.780976049
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.2459734894
Short name	T649
Test name
Test status
Simulation time	190488798931 ps
CPU time	81.31 seconds
Started	Mar 10 12:59:34 PM PDT 24
Finished	Mar 10 01:00:56 PM PDT 24
Peak memory	200152 kb
Host	smart-d22e8f15-e358-4288-b7f1-19ee5146f549
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459734894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2459734894
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.3820536945
Short name	T147
Test name
Test status
Simulation time	190477395238 ps
CPU time	153.53 seconds
Started	Mar 10 12:59:33 PM PDT 24
Finished	Mar 10 01:02:07 PM PDT 24
Peak memory	200180 kb
Host	smart-3b0434fc-65f9-438a-b6bd-14d4a92c3472
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820536945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3820536945
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.86274146
Short name	T160
Test name
Test status
Simulation time	77753865110 ps
CPU time	63.76 seconds
Started	Mar 10 12:59:32 PM PDT 24
Finished	Mar 10 01:00:36 PM PDT 24
Peak memory	200096 kb
Host	smart-ee7a37fd-fcb6-4dc5-bd26-07fc4306c130
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86274146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.86274146
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.1313234437
Short name	T988
Test name
Test status
Simulation time	115206833193 ps
CPU time	47.77 seconds
Started	Mar 10 12:59:36 PM PDT 24
Finished	Mar 10 01:00:24 PM PDT 24
Peak memory	199648 kb
Host	smart-cd79256f-12eb-40f2-aae0-453b9d5661b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313234437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1313234437
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.865948712
Short name	T747
Test name
Test status
Simulation time	13515938 ps
CPU time	0.57 seconds
Started	Mar 10 12:52:44 PM PDT 24
Finished	Mar 10 12:52:45 PM PDT 24
Peak memory	195500 kb
Host	smart-3bfa6004-0a48-4560-929c-925f9c410215
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865948712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.865948712
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.1107933041
Short name	T98
Test name
Test status
Simulation time	16327129982 ps
CPU time	27 seconds
Started	Mar 10 12:52:31 PM PDT 24
Finished	Mar 10 12:52:59 PM PDT 24
Peak memory	198724 kb
Host	smart-5e3b975e-f4fa-4e25-8924-2b838a2a75d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107933041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1107933041
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.551592075
Short name	T191
Test name
Test status
Simulation time	137453921733 ps
CPU time	88.14 seconds
Started	Mar 10 12:52:37 PM PDT 24
Finished	Mar 10 12:54:06 PM PDT 24
Peak memory	200136 kb
Host	smart-5486b3ec-aba8-4485-a7c8-337a87d44a8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551592075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.551592075
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_intr.2312585211
Short name	T715
Test name
Test status
Simulation time	77577437628 ps
CPU time	31.84 seconds
Started	Mar 10 12:52:36 PM PDT 24
Finished	Mar 10 12:53:08 PM PDT 24
Peak memory	200068 kb
Host	smart-dca9086a-1fe2-4fee-84cb-d8ccfe2c2af9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312585211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2312585211
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.718201780
Short name	T967
Test name
Test status
Simulation time	97827232047 ps
CPU time	263.92 seconds
Started	Mar 10 12:52:43 PM PDT 24
Finished	Mar 10 12:57:07 PM PDT 24
Peak memory	200080 kb
Host	smart-addcc1b5-6cc8-49a3-99e1-bfdee64819c3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=718201780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.718201780
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.2286202069
Short name	T966
Test name
Test status
Simulation time	12265896690 ps
CPU time	8.88 seconds
Started	Mar 10 12:52:43 PM PDT 24
Finished	Mar 10 12:52:53 PM PDT 24
Peak memory	200044 kb
Host	smart-409df416-f055-4c83-8a75-0046a8b2931e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286202069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2286202069
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.981661228
Short name	T1040
Test name
Test status
Simulation time	101416891691 ps
CPU time	51.81 seconds
Started	Mar 10 12:52:37 PM PDT 24
Finished	Mar 10 12:53:29 PM PDT 24
Peak memory	198312 kb
Host	smart-5a9b7eb8-84d3-4805-b4c0-dc3f59837cf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981661228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.981661228
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.3719449657
Short name	T746
Test name
Test status
Simulation time	11279581620 ps
CPU time	161.56 seconds
Started	Mar 10 12:52:44 PM PDT 24
Finished	Mar 10 12:55:27 PM PDT 24
Peak memory	200192 kb
Host	smart-a92402ef-55eb-4460-99eb-f39f44f07345
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3719449657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3719449657
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.561194245
Short name	T696
Test name
Test status
Simulation time	4636498052 ps
CPU time	37.33 seconds
Started	Mar 10 12:52:37 PM PDT 24
Finished	Mar 10 12:53:15 PM PDT 24
Peak memory	198400 kb
Host	smart-61a0f2c4-dd32-46d6-b652-b205160ccab5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=561194245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.561194245
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.2202842214
Short name	T640
Test name
Test status
Simulation time	37723860911 ps
CPU time	16.78 seconds
Started	Mar 10 12:52:42 PM PDT 24
Finished	Mar 10 12:52:59 PM PDT 24
Peak memory	198672 kb
Host	smart-8c9e0319-d579-4263-9775-082535218394
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202842214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2202842214
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.612476843
Short name	T518
Test name
Test status
Simulation time	3869276024 ps
CPU time	2.29 seconds
Started	Mar 10 12:52:36 PM PDT 24
Finished	Mar 10 12:52:38 PM PDT 24
Peak memory	195928 kb
Host	smart-0563f033-d509-488f-b1ef-086e44677d9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612476843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.612476843
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.3545740909
Short name	T622
Test name
Test status
Simulation time	506053710 ps
CPU time	1.58 seconds
Started	Mar 10 12:52:35 PM PDT 24
Finished	Mar 10 12:52:37 PM PDT 24
Peak memory	198212 kb
Host	smart-64f1eeb7-acf2-420e-9183-4452cd7f71cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545740909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3545740909
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all.1926857926
Short name	T590
Test name
Test status
Simulation time	439939435222 ps
CPU time	46.63 seconds
Started	Mar 10 12:52:41 PM PDT 24
Finished	Mar 10 12:53:28 PM PDT 24
Peak memory	200136 kb
Host	smart-6b65c2ef-e937-41a8-bd65-aeb900d2d7f0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926857926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1926857926
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.848224760
Short name	T992
Test name
Test status
Simulation time	994397443 ps
CPU time	1.49 seconds
Started	Mar 10 12:52:44 PM PDT 24
Finished	Mar 10 12:52:46 PM PDT 24
Peak memory	198036 kb
Host	smart-5f757355-60b1-4ac5-bf0a-152e9c1d71b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848224760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.848224760
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.1192519374
Short name	T488
Test name
Test status
Simulation time	44646833022 ps
CPU time	7.51 seconds
Started	Mar 10 12:52:30 PM PDT 24
Finished	Mar 10 12:52:38 PM PDT 24
Peak memory	196896 kb
Host	smart-f7a9d5e5-1d5b-48b9-9133-fc96bdf751b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192519374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1192519374
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.264152517
Short name	T214
Test name
Test status
Simulation time	214044402916 ps
CPU time	59.6 seconds
Started	Mar 10 12:59:36 PM PDT 24
Finished	Mar 10 01:00:36 PM PDT 24
Peak memory	200072 kb
Host	smart-a38ca2f8-42ca-4861-a687-28e74cf9fb6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264152517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.264152517
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.3942189863
Short name	T962
Test name
Test status
Simulation time	85650533549 ps
CPU time	143.65 seconds
Started	Mar 10 12:59:33 PM PDT 24
Finished	Mar 10 01:01:57 PM PDT 24
Peak memory	199564 kb
Host	smart-56ec5fb6-c175-4780-a31d-cc6b7484e3ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942189863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3942189863
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.3041377380
Short name	T198
Test name
Test status
Simulation time	37147636893 ps
CPU time	33.32 seconds
Started	Mar 10 12:59:33 PM PDT 24
Finished	Mar 10 01:00:07 PM PDT 24
Peak memory	200084 kb
Host	smart-1fb07d62-6b05-4777-8eee-3d9c604a6063
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041377380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3041377380
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.1985616826
Short name	T19
Test name
Test status
Simulation time	64551434498 ps
CPU time	54.62 seconds
Started	Mar 10 12:59:37 PM PDT 24
Finished	Mar 10 01:00:31 PM PDT 24
Peak memory	200204 kb
Host	smart-5948e5fb-bf9e-47f1-94e4-3019ba9058db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985616826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1985616826
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.1166381850
Short name	T262
Test name
Test status
Simulation time	31275573111 ps
CPU time	33.83 seconds
Started	Mar 10 12:59:36 PM PDT 24
Finished	Mar 10 01:00:10 PM PDT 24
Peak memory	200136 kb
Host	smart-45fae130-8f54-447a-9b1d-dca79b5986da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166381850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1166381850
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.2166423962
Short name	T974
Test name
Test status
Simulation time	22322865163 ps
CPU time	9.05 seconds
Started	Mar 10 12:59:37 PM PDT 24
Finished	Mar 10 12:59:46 PM PDT 24
Peak memory	200036 kb
Host	smart-d2aa8ee5-8efb-48e0-9c80-110ddb3444f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166423962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2166423962
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.1214085531
Short name	T295
Test name
Test status
Simulation time	73002887403 ps
CPU time	65.02 seconds
Started	Mar 10 12:59:37 PM PDT 24
Finished	Mar 10 01:00:42 PM PDT 24
Peak memory	200196 kb
Host	smart-b1cccf81-8af3-44aa-b2f5-70f1452e95e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214085531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1214085531
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.1590203906
Short name	T568
Test name
Test status
Simulation time	44684663 ps
CPU time	0.56 seconds
Started	Mar 10 12:52:54 PM PDT 24
Finished	Mar 10 12:52:55 PM PDT 24
Peak memory	195504 kb
Host	smart-82d879dd-0e7c-445e-a98a-926b0404cbd6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590203906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1590203906
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.2652623786
Short name	T390
Test name
Test status
Simulation time	204283446392 ps
CPU time	362.06 seconds
Started	Mar 10 12:52:42 PM PDT 24
Finished	Mar 10 12:58:45 PM PDT 24
Peak memory	200084 kb
Host	smart-7e80448e-05ba-4c16-ada3-866210fc2dba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652623786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2652623786
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.2423734265
Short name	T960
Test name
Test status
Simulation time	90907721651 ps
CPU time	53.75 seconds
Started	Mar 10 12:52:42 PM PDT 24
Finished	Mar 10 12:53:37 PM PDT 24
Peak memory	200056 kb
Host	smart-5614845f-e537-416e-a66f-27948faaa472
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423734265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2423734265
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.527277470
Short name	T501
Test name
Test status
Simulation time	28837649150 ps
CPU time	24.48 seconds
Started	Mar 10 12:52:48 PM PDT 24
Finished	Mar 10 12:53:13 PM PDT 24
Peak memory	200144 kb
Host	smart-75ffab77-d903-457d-a137-b957497ebb15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=527277470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.527277470
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.1750320862
Short name	T431
Test name
Test status
Simulation time	51245740674 ps
CPU time	42.05 seconds
Started	Mar 10 12:52:51 PM PDT 24
Finished	Mar 10 12:53:33 PM PDT 24
Peak memory	197260 kb
Host	smart-8c5da415-8018-40cd-883e-e23b4d0ba5b3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750320862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1750320862
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.4222723245
Short name	T930
Test name
Test status
Simulation time	96783325395 ps
CPU time	652.24 seconds
Started	Mar 10 12:52:46 PM PDT 24
Finished	Mar 10 01:03:38 PM PDT 24
Peak memory	200052 kb
Host	smart-bb3e2766-26eb-4160-a892-80d9c6055147
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4222723245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4222723245
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.2091351616
Short name	T600
Test name
Test status
Simulation time	1150371045 ps
CPU time	2.78 seconds
Started	Mar 10 12:52:47 PM PDT 24
Finished	Mar 10 12:52:50 PM PDT 24
Peak memory	195668 kb
Host	smart-227381ff-8a3d-4c18-8ca5-212d78b8f3ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091351616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2091351616
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.3667124671
Short name	T651
Test name
Test status
Simulation time	60443293207 ps
CPU time	25.81 seconds
Started	Mar 10 12:52:45 PM PDT 24
Finished	Mar 10 12:53:11 PM PDT 24
Peak memory	199884 kb
Host	smart-3968b184-9eda-4047-b21c-eea8ecbec8a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667124671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3667124671
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.4067941839
Short name	T977
Test name
Test status
Simulation time	21937521030 ps
CPU time	1151.09 seconds
Started	Mar 10 12:52:51 PM PDT 24
Finished	Mar 10 01:12:02 PM PDT 24
Peak memory	200140 kb
Host	smart-d03e2dd3-7ec7-4c0a-a086-5d88cf57d0ec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4067941839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4067941839
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.2135993042
Short name	T493
Test name
Test status
Simulation time	5540906011 ps
CPU time	4.35 seconds
Started	Mar 10 12:52:51 PM PDT 24
Finished	Mar 10 12:52:55 PM PDT 24
Peak memory	198808 kb
Host	smart-b7da8784-3a7f-4547-ad1e-33598d8191d5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2135993042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2135993042
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.3606067840
Short name	T181
Test name
Test status
Simulation time	105356067176 ps
CPU time	128.9 seconds
Started	Mar 10 12:52:46 PM PDT 24
Finished	Mar 10 12:54:55 PM PDT 24
Peak memory	198484 kb
Host	smart-84679862-acf2-4679-b313-1434018f0792
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606067840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3606067840
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.552700631
Short name	T933
Test name
Test status
Simulation time	40097903552 ps
CPU time	59.36 seconds
Started	Mar 10 12:52:48 PM PDT 24
Finished	Mar 10 12:53:47 PM PDT 24
Peak memory	195856 kb
Host	smart-7c267367-b194-493f-95a1-1ee0947d6474
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552700631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.552700631
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.2222768580
Short name	T1070
Test name
Test status
Simulation time	290185338 ps
CPU time	1.22 seconds
Started	Mar 10 12:52:41 PM PDT 24
Finished	Mar 10 12:52:43 PM PDT 24
Peak memory	198160 kb
Host	smart-f840526e-5059-4aba-aac8-5dff2f956eae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222768580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2222768580
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.697601150
Short name	T544
Test name
Test status
Simulation time	819303536 ps
CPU time	3.11 seconds
Started	Mar 10 12:52:47 PM PDT 24
Finished	Mar 10 12:52:51 PM PDT 24
Peak memory	198096 kb
Host	smart-333aede7-dadb-47f8-a9b7-492cb37575d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697601150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.697601150
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.2417678216
Short name	T172
Test name
Test status
Simulation time	349116770551 ps
CPU time	92.31 seconds
Started	Mar 10 12:52:43 PM PDT 24
Finished	Mar 10 12:54:17 PM PDT 24
Peak memory	200068 kb
Host	smart-999e2bcf-08af-4a8b-ac87-578a57b8a445
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417678216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2417678216
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.1682826422
Short name	T924
Test name
Test status
Simulation time	203500638286 ps
CPU time	29.19 seconds
Started	Mar 10 12:59:36 PM PDT 24
Finished	Mar 10 01:00:05 PM PDT 24
Peak memory	200036 kb
Host	smart-a6c3a81f-eb3d-48f2-8a9c-97a1d40dcf7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682826422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1682826422
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.1864600002
Short name	T287
Test name
Test status
Simulation time	152865095706 ps
CPU time	225.2 seconds
Started	Mar 10 12:59:39 PM PDT 24
Finished	Mar 10 01:03:24 PM PDT 24
Peak memory	199888 kb
Host	smart-87855fba-959d-4ced-bf2b-54025ed93163
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864600002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1864600002
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.4212187247
Short name	T1091
Test name
Test status
Simulation time	121266038586 ps
CPU time	108.87 seconds
Started	Mar 10 12:59:45 PM PDT 24
Finished	Mar 10 01:01:34 PM PDT 24
Peak memory	200136 kb
Host	smart-de07386c-6fb8-47c3-ac82-c261c42852cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212187247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4212187247
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.3807906767
Short name	T957
Test name
Test status
Simulation time	50290422923 ps
CPU time	70.9 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 01:00:54 PM PDT 24
Peak memory	200092 kb
Host	smart-06f1248f-8155-40a4-9f86-d6da96717df0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807906767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3807906767
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.2887207100
Short name	T854
Test name
Test status
Simulation time	154096899558 ps
CPU time	59.51 seconds
Started	Mar 10 12:59:43 PM PDT 24
Finished	Mar 10 01:00:43 PM PDT 24
Peak memory	199816 kb
Host	smart-73ac34f3-1a37-4ab2-b942-e5cf9303f257
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2887207100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2887207100
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.40916580
Short name	T222
Test name
Test status
Simulation time	113198070694 ps
CPU time	53.38 seconds
Started	Mar 10 12:59:41 PM PDT 24
Finished	Mar 10 01:00:35 PM PDT 24
Peak memory	200080 kb
Host	smart-bbcd690d-8e3a-48a6-8a81-18f8d4fe535e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40916580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.40916580
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.4105327980
Short name	T1020
Test name
Test status
Simulation time	40171584442 ps
CPU time	48.37 seconds
Started	Mar 10 12:59:51 PM PDT 24
Finished	Mar 10 01:00:40 PM PDT 24
Peak memory	200004 kb
Host	smart-0673e886-90b1-4123-bdcb-f130399a9367
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105327980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4105327980
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.241166638
Short name	T572
Test name
Test status
Simulation time	19370802 ps
CPU time	0.54 seconds
Started	Mar 10 12:53:06 PM PDT 24
Finished	Mar 10 12:53:07 PM PDT 24
Peak memory	195460 kb
Host	smart-d3c22b28-7211-4e49-a36b-a0b59665cbfc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241166638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.241166638
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.191921910
Short name	T561
Test name
Test status
Simulation time	23649623075 ps
CPU time	35.67 seconds
Started	Mar 10 12:52:53 PM PDT 24
Finished	Mar 10 12:53:29 PM PDT 24
Peak memory	200120 kb
Host	smart-80201b01-f32b-496b-83e0-7b80f4c91218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191921910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.191921910
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.3597173786
Short name	T780
Test name
Test status
Simulation time	11785459572 ps
CPU time	14.48 seconds
Started	Mar 10 12:52:54 PM PDT 24
Finished	Mar 10 12:53:08 PM PDT 24
Peak memory	200076 kb
Host	smart-d75b7e73-03d7-403b-9a61-7fd435fe90b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3597173786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3597173786
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.2542564952
Short name	T164
Test name
Test status
Simulation time	229790549771 ps
CPU time	55.57 seconds
Started	Mar 10 12:52:53 PM PDT 24
Finished	Mar 10 12:53:48 PM PDT 24
Peak memory	200192 kb
Host	smart-3092cd12-9645-489b-adc5-ba9f9d9ebd0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542564952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2542564952
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_intr.436385870
Short name	T871
Test name
Test status
Simulation time	59719179608 ps
CPU time	59.15 seconds
Started	Mar 10 12:52:59 PM PDT 24
Finished	Mar 10 12:53:58 PM PDT 24
Peak memory	200144 kb
Host	smart-4f8d168d-a72c-4b7a-b188-981063b5e023
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436385870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.436385870
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.1257023570
Short name	T1108
Test name
Test status
Simulation time	145057953506 ps
CPU time	1167.75 seconds
Started	Mar 10 12:53:00 PM PDT 24
Finished	Mar 10 01:12:28 PM PDT 24
Peak memory	200072 kb
Host	smart-1fa10ba5-6904-4223-b5fd-7244702ff2e4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1257023570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1257023570
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/29.uart_loopback.588637583
Short name	T769
Test name
Test status
Simulation time	600493456 ps
CPU time	0.72 seconds
Started	Mar 10 12:53:00 PM PDT 24
Finished	Mar 10 12:53:01 PM PDT 24
Peak memory	195344 kb
Host	smart-a2ed49c5-7956-43c2-920b-fb17018dbadb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588637583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.588637583
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.2666035524
Short name	T869
Test name
Test status
Simulation time	241148710501 ps
CPU time	79.9 seconds
Started	Mar 10 12:53:00 PM PDT 24
Finished	Mar 10 12:54:21 PM PDT 24
Peak memory	200284 kb
Host	smart-b55100dc-1a2c-45fc-927d-3a99e18ebf4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666035524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2666035524
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.3423019626
Short name	T789
Test name
Test status
Simulation time	12541201691 ps
CPU time	357.89 seconds
Started	Mar 10 12:52:59 PM PDT 24
Finished	Mar 10 12:58:57 PM PDT 24
Peak memory	200152 kb
Host	smart-6cf379e1-805f-422d-b34d-49667ee622fc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3423019626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3423019626
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.1364483112
Short name	T536
Test name
Test status
Simulation time	3548866291 ps
CPU time	27.44 seconds
Started	Mar 10 12:52:54 PM PDT 24
Finished	Mar 10 12:53:22 PM PDT 24
Peak memory	198700 kb
Host	smart-5c820483-1800-4bff-97c1-a8570117a39b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1364483112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1364483112
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.336293203
Short name	T876
Test name
Test status
Simulation time	44588651883 ps
CPU time	33.7 seconds
Started	Mar 10 12:52:58 PM PDT 24
Finished	Mar 10 12:53:31 PM PDT 24
Peak memory	199736 kb
Host	smart-4de245ea-b3b2-4fa5-ae38-36d1a5980b84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336293203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.336293203
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.1067986946
Short name	T1050
Test name
Test status
Simulation time	1766372191 ps
CPU time	2.05 seconds
Started	Mar 10 12:52:59 PM PDT 24
Finished	Mar 10 12:53:01 PM PDT 24
Peak memory	195416 kb
Host	smart-17d32d1d-9428-43bd-835b-3a832f4c99de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067986946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1067986946
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.1412091963
Short name	T947
Test name
Test status
Simulation time	124511934 ps
CPU time	1.05 seconds
Started	Mar 10 12:52:53 PM PDT 24
Finished	Mar 10 12:52:54 PM PDT 24
Peak memory	198196 kb
Host	smart-5a52d7c4-a8d4-483d-9afa-669b4cf13e24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412091963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1412091963
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.1754185168
Short name	T965
Test name
Test status
Simulation time	163571042122 ps
CPU time	165.39 seconds
Started	Mar 10 12:53:06 PM PDT 24
Finished	Mar 10 12:55:52 PM PDT 24
Peak memory	199740 kb
Host	smart-d11c5980-a405-4718-b7e3-79490d001f3d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754185168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1754185168
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.2190975435
Short name	T397
Test name
Test status
Simulation time	1096665849 ps
CPU time	3.77 seconds
Started	Mar 10 12:52:59 PM PDT 24
Finished	Mar 10 12:53:03 PM PDT 24
Peak memory	198660 kb
Host	smart-fd58f6ec-0593-43a4-a6a6-e5dcf5597d42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190975435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2190975435
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.2201797652
Short name	T389
Test name
Test status
Simulation time	163432279234 ps
CPU time	108.36 seconds
Started	Mar 10 12:52:53 PM PDT 24
Finished	Mar 10 12:54:42 PM PDT 24
Peak memory	200108 kb
Host	smart-a26ef5ce-c7fc-4cfd-bc38-d31e80aa2acc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201797652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2201797652
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.2990151540
Short name	T41
Test name
Test status
Simulation time	65212920434 ps
CPU time	113.09 seconds
Started	Mar 10 12:59:43 PM PDT 24
Finished	Mar 10 01:01:37 PM PDT 24
Peak memory	200168 kb
Host	smart-a9be0f88-fa2c-4f22-8c13-d7f55bc60ad0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990151540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2990151540
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.2900706097
Short name	T195
Test name
Test status
Simulation time	49814503614 ps
CPU time	29.25 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 01:00:12 PM PDT 24
Peak memory	200140 kb
Host	smart-bc710c49-6369-4e92-8faf-6b18fab95835
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900706097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2900706097
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.3540039123
Short name	T125
Test name
Test status
Simulation time	207551304197 ps
CPU time	17.67 seconds
Started	Mar 10 12:59:45 PM PDT 24
Finished	Mar 10 01:00:03 PM PDT 24
Peak memory	200120 kb
Host	smart-0960a5d4-d412-42d8-89b1-53965122908e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540039123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3540039123
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.904431499
Short name	T199
Test name
Test status
Simulation time	141019419909 ps
CPU time	189.79 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 01:02:53 PM PDT 24
Peak memory	200048 kb
Host	smart-fa5badd9-e4fe-48a2-b77e-e9308aadf8a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904431499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.904431499
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.442763003
Short name	T255
Test name
Test status
Simulation time	37370295091 ps
CPU time	63.41 seconds
Started	Mar 10 12:59:43 PM PDT 24
Finished	Mar 10 01:00:46 PM PDT 24
Peak memory	200216 kb
Host	smart-e9b757ec-9391-40c2-a134-339d8cf36947
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442763003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.442763003
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.1189323979
Short name	T411
Test name
Test status
Simulation time	47728717484 ps
CPU time	17.16 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 01:00:00 PM PDT 24
Peak memory	200244 kb
Host	smart-9f08e966-6af1-49b5-8b79-4b13078cb9e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189323979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1189323979
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.2525783635
Short name	T1003
Test name
Test status
Simulation time	30348255166 ps
CPU time	12.64 seconds
Started	Mar 10 12:59:42 PM PDT 24
Finished	Mar 10 12:59:55 PM PDT 24
Peak memory	198232 kb
Host	smart-9863e81a-d9d1-4406-a626-0029d7f72bbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525783635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2525783635
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.3102703922
Short name	T242
Test name
Test status
Simulation time	116893200320 ps
CPU time	115.09 seconds
Started	Mar 10 12:59:43 PM PDT 24
Finished	Mar 10 01:01:39 PM PDT 24
Peak memory	200112 kb
Host	smart-d47f1801-d0c7-4ec8-91e2-50c7fb1b213e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102703922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3102703922
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.1764697321
Short name	T859
Test name
Test status
Simulation time	41202091573 ps
CPU time	40.15 seconds
Started	Mar 10 12:59:48 PM PDT 24
Finished	Mar 10 01:00:28 PM PDT 24
Peak memory	200072 kb
Host	smart-f40d2038-52ee-44af-b612-5877ce7aaa70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764697321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1764697321
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.344153506
Short name	T449
Test name
Test status
Simulation time	51125848 ps
CPU time	0.58 seconds
Started	Mar 10 12:48:47 PM PDT 24
Finished	Mar 10 12:48:47 PM PDT 24
Peak memory	195420 kb
Host	smart-6b04b868-6fbf-4760-a7e7-0e2b631f9bcc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344153506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.344153506
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.3931649054
Short name	T1099
Test name
Test status
Simulation time	32663426914 ps
CPU time	26.43 seconds
Started	Mar 10 12:48:34 PM PDT 24
Finished	Mar 10 12:49:02 PM PDT 24
Peak memory	200072 kb
Host	smart-752f099f-3a4a-4eb6-bf13-3b491dff445c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3931649054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3931649054
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.677754533
Short name	T369
Test name
Test status
Simulation time	82301732934 ps
CPU time	24.67 seconds
Started	Mar 10 12:48:35 PM PDT 24
Finished	Mar 10 12:49:00 PM PDT 24
Peak memory	199120 kb
Host	smart-919f18af-f8f0-4b0c-9e67-f922e6881fbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677754533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.677754533
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.3039823136
Short name	T335
Test name
Test status
Simulation time	92839140948 ps
CPU time	79.02 seconds
Started	Mar 10 12:48:34 PM PDT 24
Finished	Mar 10 12:49:54 PM PDT 24
Peak memory	199284 kb
Host	smart-c4f5b69c-2801-4250-bb67-80c06da8ba80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039823136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3039823136
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_intr.2515703097
Short name	T582
Test name
Test status
Simulation time	27099807978 ps
CPU time	42.96 seconds
Started	Mar 10 12:48:41 PM PDT 24
Finished	Mar 10 12:49:24 PM PDT 24
Peak memory	195628 kb
Host	smart-f79bde26-b4de-4850-aa4c-a0a81caf8e1e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515703097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2515703097
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.2773370358
Short name	T457
Test name
Test status
Simulation time	105718906941 ps
CPU time	903.99 seconds
Started	Mar 10 12:48:48 PM PDT 24
Finished	Mar 10 01:03:52 PM PDT 24
Peak memory	200116 kb
Host	smart-50f952ac-f7fc-4847-9b3e-217242652df7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2773370358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2773370358
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.2435271846
Short name	T964
Test name
Test status
Simulation time	3716734105 ps
CPU time	2.16 seconds
Started	Mar 10 12:48:40 PM PDT 24
Finished	Mar 10 12:48:43 PM PDT 24
Peak memory	198068 kb
Host	smart-6721eb17-2812-4d32-8632-74f35096ae53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435271846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2435271846
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.3531127794
Short name	T697
Test name
Test status
Simulation time	33881158876 ps
CPU time	56.14 seconds
Started	Mar 10 12:48:40 PM PDT 24
Finished	Mar 10 12:49:36 PM PDT 24
Peak memory	199104 kb
Host	smart-cffb49ae-be33-44c1-8425-ab9a7b6dfd9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531127794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3531127794
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.2834074129
Short name	T271
Test name
Test status
Simulation time	24043979665 ps
CPU time	1382.78 seconds
Started	Mar 10 12:48:45 PM PDT 24
Finished	Mar 10 01:11:48 PM PDT 24
Peak memory	200228 kb
Host	smart-5d72aa40-cbf4-427d-bf95-72a837ee81c2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2834074129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2834074129
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.3055245822
Short name	T703
Test name
Test status
Simulation time	3258353439 ps
CPU time	21.4 seconds
Started	Mar 10 12:48:42 PM PDT 24
Finished	Mar 10 12:49:03 PM PDT 24
Peak memory	198624 kb
Host	smart-bfee4f03-061d-47c4-a8b2-bad2950e6065
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3055245822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3055245822
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.420684906
Short name	T159
Test name
Test status
Simulation time	30454510155 ps
CPU time	12.16 seconds
Started	Mar 10 12:48:41 PM PDT 24
Finished	Mar 10 12:48:54 PM PDT 24
Peak memory	197472 kb
Host	smart-64827a4d-b50c-4f1b-9f3a-a66afba44cbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420684906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.420684906
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.1297960903
Short name	T1035
Test name
Test status
Simulation time	2019759769 ps
CPU time	3.63 seconds
Started	Mar 10 12:48:41 PM PDT 24
Finished	Mar 10 12:48:45 PM PDT 24
Peak memory	195504 kb
Host	smart-a8198340-3480-48ef-86c7-31b020aff4b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297960903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1297960903
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.734348588
Short name	T31
Test name
Test status
Simulation time	236146537 ps
CPU time	0.81 seconds
Started	Mar 10 12:48:45 PM PDT 24
Finished	Mar 10 12:48:46 PM PDT 24
Peak memory	217308 kb
Host	smart-a0ea82c3-fb60-4b23-9af9-0b6e57d7044b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734348588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.734348588
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/3.uart_smoke.1068343213
Short name	T867
Test name
Test status
Simulation time	6057454579 ps
CPU time	13.4 seconds
Started	Mar 10 12:48:35 PM PDT 24
Finished	Mar 10 12:48:49 PM PDT 24
Peak memory	199608 kb
Host	smart-90c9cff3-6259-4066-9113-7c33cb8c35d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068343213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1068343213
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.762961767
Short name	T657
Test name
Test status
Simulation time	2113860691 ps
CPU time	1.45 seconds
Started	Mar 10 12:48:42 PM PDT 24
Finished	Mar 10 12:48:43 PM PDT 24
Peak memory	198032 kb
Host	smart-c07948d8-27c4-462d-89d1-706892485a63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762961767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.762961767
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.793340912
Short name	T664
Test name
Test status
Simulation time	128325483718 ps
CPU time	24.93 seconds
Started	Mar 10 12:48:36 PM PDT 24
Finished	Mar 10 12:49:01 PM PDT 24
Peak memory	200152 kb
Host	smart-e5ff5a10-3a3d-43dc-9003-203fdf7a1fa7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793340912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.793340912
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.1075428377
Short name	T437
Test name
Test status
Simulation time	13817802 ps
CPU time	0.54 seconds
Started	Mar 10 12:53:13 PM PDT 24
Finished	Mar 10 12:53:14 PM PDT 24
Peak memory	195444 kb
Host	smart-8c572f8d-2eeb-48c0-b465-ff9e1f01a4cc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075428377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1075428377
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.3828321713
Short name	T293
Test name
Test status
Simulation time	58403487188 ps
CPU time	28.03 seconds
Started	Mar 10 12:53:06 PM PDT 24
Finished	Mar 10 12:53:34 PM PDT 24
Peak memory	200208 kb
Host	smart-9c409f1d-7dc2-4fe2-aac2-cba0cc59a63b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828321713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3828321713
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.3586352078
Short name	T963
Test name
Test status
Simulation time	103046475507 ps
CPU time	28.18 seconds
Started	Mar 10 12:53:07 PM PDT 24
Finished	Mar 10 12:53:35 PM PDT 24
Peak memory	199568 kb
Host	smart-e64e4091-a1f7-4f93-a9f1-7aeebd446613
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586352078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3586352078
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.237894442
Short name	T205
Test name
Test status
Simulation time	65948748289 ps
CPU time	30.19 seconds
Started	Mar 10 12:53:06 PM PDT 24
Finished	Mar 10 12:53:37 PM PDT 24
Peak memory	200112 kb
Host	smart-5c132b73-f71a-4ef0-8f92-59a861faaf76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237894442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.237894442
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_intr.495450003
Short name	T889
Test name
Test status
Simulation time	80627093758 ps
CPU time	40.36 seconds
Started	Mar 10 12:53:06 PM PDT 24
Finished	Mar 10 12:53:46 PM PDT 24
Peak memory	200084 kb
Host	smart-b6d78861-00a0-4606-a16e-f32303887a3a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495450003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.495450003
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.2082294827
Short name	T701
Test name
Test status
Simulation time	99320652877 ps
CPU time	348.26 seconds
Started	Mar 10 12:53:10 PM PDT 24
Finished	Mar 10 12:58:59 PM PDT 24
Peak memory	200108 kb
Host	smart-543eadd2-1294-4506-ae21-74f83688c59b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2082294827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2082294827
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_loopback.1947061863
Short name	T626
Test name
Test status
Simulation time	14651305704 ps
CPU time	23.83 seconds
Started	Mar 10 12:53:11 PM PDT 24
Finished	Mar 10 12:53:35 PM PDT 24
Peak memory	199040 kb
Host	smart-2238936c-5f1c-4877-97a3-56e1b56512cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947061863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1947061863
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.286710494
Short name	T526
Test name
Test status
Simulation time	63237994375 ps
CPU time	238.86 seconds
Started	Mar 10 12:53:12 PM PDT 24
Finished	Mar 10 12:57:11 PM PDT 24
Peak memory	200180 kb
Host	smart-38bbef6b-64e4-43ee-9d4e-0f12fce39787
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286710494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.286710494
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.467173457
Short name	T508
Test name
Test status
Simulation time	2446034064 ps
CPU time	6.78 seconds
Started	Mar 10 12:53:05 PM PDT 24
Finished	Mar 10 12:53:12 PM PDT 24
Peak memory	198132 kb
Host	smart-7243d2f2-f2f9-4442-960b-e490db04c250
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=467173457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.467173457
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.788412534
Short name	T1122
Test name
Test status
Simulation time	106008257360 ps
CPU time	32.81 seconds
Started	Mar 10 12:53:11 PM PDT 24
Finished	Mar 10 12:53:44 PM PDT 24
Peak memory	199356 kb
Host	smart-8d366882-c0af-4e30-b687-6179251e3036
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=788412534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.788412534
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.397061139
Short name	T485
Test name
Test status
Simulation time	23491085272 ps
CPU time	10.21 seconds
Started	Mar 10 12:53:10 PM PDT 24
Finished	Mar 10 12:53:20 PM PDT 24
Peak memory	195760 kb
Host	smart-c9462a7e-b6c3-40e1-845b-e3810e5e094e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397061139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.397061139
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.3154309376
Short name	T1071
Test name
Test status
Simulation time	310533939 ps
CPU time	1.61 seconds
Started	Mar 10 12:53:07 PM PDT 24
Finished	Mar 10 12:53:09 PM PDT 24
Peak memory	198652 kb
Host	smart-a5506e4c-fc3b-414a-bfdd-7342ccccbc70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154309376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3154309376
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all.3940414231
Short name	T167
Test name
Test status
Simulation time	587651618102 ps
CPU time	272.43 seconds
Started	Mar 10 12:53:12 PM PDT 24
Finished	Mar 10 12:57:44 PM PDT 24
Peak memory	200104 kb
Host	smart-35a82528-36b5-4c46-a0f5-c4e285a63473
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940414231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3940414231
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/30.uart_stress_all_with_rand_reset.7639255
Short name	T1086
Test name
Test status
Simulation time	43717352969 ps
CPU time	427.4 seconds
Started	Mar 10 12:53:11 PM PDT 24
Finished	Mar 10 01:00:18 PM PDT 24
Peak memory	215868 kb
Host	smart-4c8c683e-88a4-4467-a7ad-22827efd7331
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7639255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.7639255
Directory	/workspace/30.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.1984748527
Short name	T734
Test name
Test status
Simulation time	6974338403 ps
CPU time	10.51 seconds
Started	Mar 10 12:53:13 PM PDT 24
Finished	Mar 10 12:53:23 PM PDT 24
Peak memory	199564 kb
Host	smart-270b3405-1998-44c0-a8c5-013070422470
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984748527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1984748527
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.1407343403
Short name	T642
Test name
Test status
Simulation time	5107792255 ps
CPU time	3.04 seconds
Started	Mar 10 12:53:08 PM PDT 24
Finished	Mar 10 12:53:11 PM PDT 24
Peak memory	198484 kb
Host	smart-2d197e38-feb8-4038-ad0e-68fc108c6471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407343403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1407343403
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.3624715129
Short name	T698
Test name
Test status
Simulation time	11864227 ps
CPU time	0.56 seconds
Started	Mar 10 12:53:16 PM PDT 24
Finished	Mar 10 12:53:17 PM PDT 24
Peak memory	195432 kb
Host	smart-9b69ff32-c602-433c-8271-fb984ded6101
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624715129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3624715129
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.2918873239
Short name	T899
Test name
Test status
Simulation time	157892841961 ps
CPU time	109.62 seconds
Started	Mar 10 12:53:13 PM PDT 24
Finished	Mar 10 12:55:02 PM PDT 24
Peak memory	200088 kb
Host	smart-e5ba4e2b-0778-46d9-a29e-3e1702402365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918873239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2918873239
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.2903569958
Short name	T320
Test name
Test status
Simulation time	165097984297 ps
CPU time	129.39 seconds
Started	Mar 10 12:53:11 PM PDT 24
Finished	Mar 10 12:55:21 PM PDT 24
Peak memory	200060 kb
Host	smart-350fd884-f05c-4da3-9478-335946cbf667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903569958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2903569958
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.532134128
Short name	T55
Test name
Test status
Simulation time	110996681477 ps
CPU time	47.28 seconds
Started	Mar 10 12:53:09 PM PDT 24
Finished	Mar 10 12:53:57 PM PDT 24
Peak memory	199956 kb
Host	smart-dcf371e8-dfdc-4666-b03a-3535e754d63e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532134128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.532134128
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.3000295893
Short name	T20
Test name
Test status
Simulation time	80579327605 ps
CPU time	20.51 seconds
Started	Mar 10 12:53:13 PM PDT 24
Finished	Mar 10 12:53:33 PM PDT 24
Peak memory	199996 kb
Host	smart-92f25c2d-1536-4ad7-b7a3-9e083bc19e09
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000295893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3000295893
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.1486000399
Short name	T801
Test name
Test status
Simulation time	79923730940 ps
CPU time	350.34 seconds
Started	Mar 10 12:53:17 PM PDT 24
Finished	Mar 10 12:59:08 PM PDT 24
Peak memory	200056 kb
Host	smart-74667627-688d-454a-a00e-5bc89ce7b298
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1486000399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1486000399
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_loopback.1632351878
Short name	T923
Test name
Test status
Simulation time	8505708151 ps
CPU time	6.79 seconds
Started	Mar 10 12:53:18 PM PDT 24
Finished	Mar 10 12:53:25 PM PDT 24
Peak memory	198940 kb
Host	smart-e0fd21b2-817c-4ff2-b603-e18059d998a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632351878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1632351878
Directory	/workspace/31.uart_loopback/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.3753120486
Short name	T839
Test name
Test status
Simulation time	9152744278 ps
CPU time	11.28 seconds
Started	Mar 10 12:53:17 PM PDT 24
Finished	Mar 10 12:53:28 PM PDT 24
Peak memory	197872 kb
Host	smart-c87b3357-c833-414f-96ed-acf5b305c6ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753120486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3753120486
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.178058451
Short name	T856
Test name
Test status
Simulation time	8970042104 ps
CPU time	380.99 seconds
Started	Mar 10 12:53:17 PM PDT 24
Finished	Mar 10 12:59:38 PM PDT 24
Peak memory	200128 kb
Host	smart-1eeb0fc1-ecf4-4069-8faa-8c62226008b1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=178058451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.178058451
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_oversample.1967600437
Short name	T712
Test name
Test status
Simulation time	4131198685 ps
CPU time	2.09 seconds
Started	Mar 10 12:53:12 PM PDT 24
Finished	Mar 10 12:53:14 PM PDT 24
Peak memory	198268 kb
Host	smart-e5b97658-5d44-4e16-91af-6fe432c40fe5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1967600437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1967600437
Directory	/workspace/31.uart_rx_oversample/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.3720675393
Short name	T79
Test name
Test status
Simulation time	43845077424 ps
CPU time	66.69 seconds
Started	Mar 10 12:53:16 PM PDT 24
Finished	Mar 10 12:54:23 PM PDT 24
Peak memory	200048 kb
Host	smart-7efbe0c3-919e-4367-a461-c242b373a1c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720675393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3720675393
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.257657313
Short name	T610
Test name
Test status
Simulation time	2896814673 ps
CPU time	5.33 seconds
Started	Mar 10 12:53:15 PM PDT 24
Finished	Mar 10 12:53:21 PM PDT 24
Peak memory	195724 kb
Host	smart-0caa6b46-e0b3-4993-866e-43da795e6758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257657313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.257657313
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.103997465
Short name	T737
Test name
Test status
Simulation time	746575772 ps
CPU time	1.04 seconds
Started	Mar 10 12:53:12 PM PDT 24
Finished	Mar 10 12:53:13 PM PDT 24
Peak memory	198204 kb
Host	smart-35dfb9f7-cf20-48c7-88c5-b35c0ab26703
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103997465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.103997465
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_stress_all.2554554878
Short name	T912
Test name
Test status
Simulation time	632308568383 ps
CPU time	794.86 seconds
Started	Mar 10 12:53:18 PM PDT 24
Finished	Mar 10 01:06:33 PM PDT 24
Peak memory	200156 kb
Host	smart-6f6915ba-9ab9-41e6-9f38-ba774db7c759
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554554878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2554554878
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.4290419727
Short name	T605
Test name
Test status
Simulation time	1523715360 ps
CPU time	6.42 seconds
Started	Mar 10 12:53:17 PM PDT 24
Finished	Mar 10 12:53:24 PM PDT 24
Peak memory	198648 kb
Host	smart-31ca49bc-53e3-4cae-aa86-258edc7b30ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290419727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.4290419727
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.62204446
Short name	T1110
Test name
Test status
Simulation time	44278373066 ps
CPU time	39.37 seconds
Started	Mar 10 12:53:12 PM PDT 24
Finished	Mar 10 12:53:52 PM PDT 24
Peak memory	200040 kb
Host	smart-d73494bb-ec2f-4bbe-a05e-187f22cb4723
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62204446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.62204446
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.2572899132
Short name	T573
Test name
Test status
Simulation time	11965856 ps
CPU time	0.54 seconds
Started	Mar 10 12:53:31 PM PDT 24
Finished	Mar 10 12:53:31 PM PDT 24
Peak memory	195512 kb
Host	smart-f1824199-2e6c-43fb-ae23-21da5f1b773c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572899132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2572899132
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.748066647
Short name	T316
Test name
Test status
Simulation time	69163394448 ps
CPU time	30.66 seconds
Started	Mar 10 12:53:20 PM PDT 24
Finished	Mar 10 12:53:51 PM PDT 24
Peak memory	200148 kb
Host	smart-fbbbf97c-6040-4c7d-a71b-7560e75cb10a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748066647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.748066647
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.3802916403
Short name	T507
Test name
Test status
Simulation time	289193062843 ps
CPU time	119.42 seconds
Started	Mar 10 12:53:23 PM PDT 24
Finished	Mar 10 12:55:22 PM PDT 24
Peak memory	199168 kb
Host	smart-643c5730-6bc5-4561-81a2-ea35fe6d88d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802916403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3802916403
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.382405637
Short name	T249
Test name
Test status
Simulation time	171081991295 ps
CPU time	140.87 seconds
Started	Mar 10 12:53:22 PM PDT 24
Finished	Mar 10 12:55:43 PM PDT 24
Peak memory	199796 kb
Host	smart-3fc2a373-89ae-46f3-976e-fe0d6d77b6fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382405637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.382405637
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_intr.4249837896
Short name	T808
Test name
Test status
Simulation time	148954023726 ps
CPU time	245.99 seconds
Started	Mar 10 12:53:21 PM PDT 24
Finished	Mar 10 12:57:27 PM PDT 24
Peak memory	199016 kb
Host	smart-c00131c9-6439-435e-a307-a9f2a2634087
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249837896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4249837896
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.2380842216
Short name	T468
Test name
Test status
Simulation time	138911063997 ps
CPU time	738.04 seconds
Started	Mar 10 12:53:29 PM PDT 24
Finished	Mar 10 01:05:47 PM PDT 24
Peak memory	200136 kb
Host	smart-eba259bc-61dc-4030-9a9c-473ee6ed7a69
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2380842216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2380842216
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.4189383122
Short name	T731
Test name
Test status
Simulation time	2826244557 ps
CPU time	2.89 seconds
Started	Mar 10 12:53:23 PM PDT 24
Finished	Mar 10 12:53:26 PM PDT 24
Peak memory	198760 kb
Host	smart-685b3320-945f-4bf5-bca6-94a1adeafeaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189383122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.4189383122
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_noise_filter.3568653327
Short name	T784
Test name
Test status
Simulation time	170443979891 ps
CPU time	214.45 seconds
Started	Mar 10 12:53:22 PM PDT 24
Finished	Mar 10 12:56:57 PM PDT 24
Peak memory	199812 kb
Host	smart-ead67743-2d63-4ef2-9416-26f129cf173b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568653327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3568653327
Directory	/workspace/32.uart_noise_filter/latest

Test location	/workspace/coverage/default/32.uart_perf.3715442709
Short name	T952
Test name
Test status
Simulation time	23880565872 ps
CPU time	1227.45 seconds
Started	Mar 10 12:53:28 PM PDT 24
Finished	Mar 10 01:13:56 PM PDT 24
Peak memory	200148 kb
Host	smart-a152ceaf-37b4-4e63-bb24-0071be93ac6f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3715442709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3715442709
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.1294907272
Short name	T92
Test name
Test status
Simulation time	2325192147 ps
CPU time	4.42 seconds
Started	Mar 10 12:53:23 PM PDT 24
Finished	Mar 10 12:53:27 PM PDT 24
Peak memory	198388 kb
Host	smart-4a9724b0-3ed3-4cec-bf3c-36db7e85cad2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1294907272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1294907272
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.1385318418
Short name	T1017
Test name
Test status
Simulation time	807386693 ps
CPU time	0.98 seconds
Started	Mar 10 12:53:22 PM PDT 24
Finished	Mar 10 12:53:23 PM PDT 24
Peak memory	195544 kb
Host	smart-691d3012-e584-443c-9d7a-0f0990643789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385318418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1385318418
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.3189152692
Short name	T817
Test name
Test status
Simulation time	506260856 ps
CPU time	2.07 seconds
Started	Mar 10 12:53:15 PM PDT 24
Finished	Mar 10 12:53:17 PM PDT 24
Peak memory	197788 kb
Host	smart-1d37b90e-9769-4f46-914e-0a169729b6f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189152692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3189152692
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_stress_all.4118524218
Short name	T24
Test name
Test status
Simulation time	522593480095 ps
CPU time	1012.52 seconds
Started	Mar 10 12:53:29 PM PDT 24
Finished	Mar 10 01:10:22 PM PDT 24
Peak memory	208592 kb
Host	smart-e1e613af-1e14-424b-9cb6-d14057937915
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118524218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.4118524218
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.3644087630
Short name	T935
Test name
Test status
Simulation time	927902484 ps
CPU time	1.87 seconds
Started	Mar 10 12:53:24 PM PDT 24
Finished	Mar 10 12:53:26 PM PDT 24
Peak memory	198528 kb
Host	smart-d73faf77-a2f3-493b-b69e-752b2e175ccc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644087630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3644087630
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.1350160838
Short name	T607
Test name
Test status
Simulation time	26446518080 ps
CPU time	17.23 seconds
Started	Mar 10 12:53:21 PM PDT 24
Finished	Mar 10 12:53:39 PM PDT 24
Peak memory	200104 kb
Host	smart-8f1be157-a552-4392-aec6-6d0618b70573
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350160838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1350160838
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.932848856
Short name	T980
Test name
Test status
Simulation time	41015350 ps
CPU time	0.55 seconds
Started	Mar 10 12:53:39 PM PDT 24
Finished	Mar 10 12:53:39 PM PDT 24
Peak memory	195404 kb
Host	smart-0ed95b20-303d-4633-82c5-50bc30a3326f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932848856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.932848856
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.14724931
Short name	T499
Test name
Test status
Simulation time	68131680579 ps
CPU time	54.12 seconds
Started	Mar 10 12:53:27 PM PDT 24
Finished	Mar 10 12:54:22 PM PDT 24
Peak memory	200140 kb
Host	smart-7c484859-994d-43d4-8795-4e45a6b54c2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14724931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.14724931
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.1372554599
Short name	T296
Test name
Test status
Simulation time	103144067762 ps
CPU time	28.72 seconds
Started	Mar 10 12:53:29 PM PDT 24
Finished	Mar 10 12:53:58 PM PDT 24
Peak memory	199900 kb
Host	smart-11330196-891b-4b16-a762-c045c8b93073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372554599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1372554599
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.3550099510
Short name	T1082
Test name
Test status
Simulation time	9849814637 ps
CPU time	4.79 seconds
Started	Mar 10 12:53:32 PM PDT 24
Finished	Mar 10 12:53:37 PM PDT 24
Peak memory	198136 kb
Host	smart-3e1bfc78-ccbb-4a4f-b8ac-2eccb3aab71d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550099510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3550099510
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.3064789235
Short name	T500
Test name
Test status
Simulation time	45089326628 ps
CPU time	20.64 seconds
Started	Mar 10 12:53:35 PM PDT 24
Finished	Mar 10 12:53:56 PM PDT 24
Peak memory	200052 kb
Host	smart-3e0d0c2d-b5f0-406c-9ad0-221ce5797d8c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064789235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3064789235
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.3819397325
Short name	T882
Test name
Test status
Simulation time	49867237543 ps
CPU time	255.66 seconds
Started	Mar 10 12:53:33 PM PDT 24
Finished	Mar 10 12:57:49 PM PDT 24
Peak memory	200076 kb
Host	smart-588c4c6b-8d1a-4c2b-989b-b70a3eb28c00
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3819397325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3819397325
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.1468712926
Short name	T442
Test name
Test status
Simulation time	9973496494 ps
CPU time	9.76 seconds
Started	Mar 10 12:53:32 PM PDT 24
Finished	Mar 10 12:53:42 PM PDT 24
Peak memory	198640 kb
Host	smart-f337a50b-8f00-4aad-a6b5-9937e6011dd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468712926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1468712926
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.883098670
Short name	T54
Test name
Test status
Simulation time	165812594992 ps
CPU time	84.58 seconds
Started	Mar 10 12:53:32 PM PDT 24
Finished	Mar 10 12:54:57 PM PDT 24
Peak memory	200256 kb
Host	smart-233dac5e-21ac-4b35-97fd-ac842fd072f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883098670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.883098670
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.2684996280
Short name	T844
Test name
Test status
Simulation time	14950509576 ps
CPU time	437.75 seconds
Started	Mar 10 12:53:32 PM PDT 24
Finished	Mar 10 01:00:49 PM PDT 24
Peak memory	200104 kb
Host	smart-7c9710d6-4562-4f2d-a825-aea6b2c57250
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2684996280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2684996280
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.2379638833
Short name	T711
Test name
Test status
Simulation time	6533380742 ps
CPU time	18.36 seconds
Started	Mar 10 12:53:32 PM PDT 24
Finished	Mar 10 12:53:51 PM PDT 24
Peak memory	198384 kb
Host	smart-87b32131-3af0-43f2-aac2-59833783cd5c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2379638833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2379638833
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.632882193
Short name	T187
Test name
Test status
Simulation time	94257704912 ps
CPU time	50.25 seconds
Started	Mar 10 12:53:32 PM PDT 24
Finished	Mar 10 12:54:23 PM PDT 24
Peak memory	200048 kb
Host	smart-66a6f157-1978-452b-8461-eeba48b64e94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632882193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.632882193
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.2343766931
Short name	T56
Test name
Test status
Simulation time	661283568 ps
CPU time	1.66 seconds
Started	Mar 10 12:53:33 PM PDT 24
Finished	Mar 10 12:53:35 PM PDT 24
Peak memory	195544 kb
Host	smart-7ce81ea9-0415-4f65-90be-525235b04343
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343766931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2343766931
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.2449408035
Short name	T783
Test name
Test status
Simulation time	504218230 ps
CPU time	1.36 seconds
Started	Mar 10 12:53:31 PM PDT 24
Finished	Mar 10 12:53:32 PM PDT 24
Peak memory	198228 kb
Host	smart-93cb3e4b-3d68-4d72-85fd-ce17ba0c3bc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2449408035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2449408035
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all_with_rand_reset.1689992352
Short name	T372
Test name
Test status
Simulation time	637455987851 ps
CPU time	1237.51 seconds
Started	Mar 10 12:53:37 PM PDT 24
Finished	Mar 10 01:14:15 PM PDT 24
Peak memory	216672 kb
Host	smart-9ad84a67-b5d7-40aa-bd74-a1e0fbf4288a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689992352 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1689992352
Directory	/workspace/33.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.3032388669
Short name	T1054
Test name
Test status
Simulation time	2156161358 ps
CPU time	2.81 seconds
Started	Mar 10 12:53:33 PM PDT 24
Finished	Mar 10 12:53:35 PM PDT 24
Peak memory	198112 kb
Host	smart-cef34d88-f4ab-4c66-8cb2-f61d3c8d43a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032388669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3032388669
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.1775344586
Short name	T679
Test name
Test status
Simulation time	36964331968 ps
CPU time	15.95 seconds
Started	Mar 10 12:53:29 PM PDT 24
Finished	Mar 10 12:53:45 PM PDT 24
Peak memory	199980 kb
Host	smart-6bc13ddf-3cae-40af-9d71-cbe4568e1d2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775344586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1775344586
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.2443814691
Short name	T838
Test name
Test status
Simulation time	15114504 ps
CPU time	0.59 seconds
Started	Mar 10 12:53:49 PM PDT 24
Finished	Mar 10 12:53:50 PM PDT 24
Peak memory	195504 kb
Host	smart-122aea24-beb9-4602-9dd0-7b57dfa34b26
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443814691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2443814691
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.2071567942
Short name	T941
Test name
Test status
Simulation time	102082152517 ps
CPU time	146.63 seconds
Started	Mar 10 12:53:39 PM PDT 24
Finished	Mar 10 12:56:06 PM PDT 24
Peak memory	200016 kb
Host	smart-f552f8ad-2358-459d-8a04-9afcae3f0276
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071567942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2071567942
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.3207090679
Short name	T547
Test name
Test status
Simulation time	37376020361 ps
CPU time	15.86 seconds
Started	Mar 10 12:53:39 PM PDT 24
Finished	Mar 10 12:53:55 PM PDT 24
Peak memory	198728 kb
Host	smart-590b6dcc-96f9-4616-868d-3c94e5467a43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207090679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3207090679
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_intr.3797471804
Short name	T774
Test name
Test status
Simulation time	718171247303 ps
CPU time	611.77 seconds
Started	Mar 10 12:53:43 PM PDT 24
Finished	Mar 10 01:03:56 PM PDT 24
Peak memory	198516 kb
Host	smart-df72e34a-c6c5-4b5e-89b5-b863af3e7968
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797471804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3797471804
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.53666148
Short name	T470
Test name
Test status
Simulation time	72329228395 ps
CPU time	561.84 seconds
Started	Mar 10 12:53:51 PM PDT 24
Finished	Mar 10 01:03:14 PM PDT 24
Peak memory	200132 kb
Host	smart-47e55bb6-20d4-4d78-ba9b-7396f2013181
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=53666148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.53666148
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.2857364914
Short name	T891
Test name
Test status
Simulation time	7564574331 ps
CPU time	3.7 seconds
Started	Mar 10 12:53:49 PM PDT 24
Finished	Mar 10 12:53:53 PM PDT 24
Peak memory	200048 kb
Host	smart-bd8f03eb-4bc5-4a32-a342-9add8e4bb84e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857364914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2857364914
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.474677846
Short name	T875
Test name
Test status
Simulation time	88160810950 ps
CPU time	185.8 seconds
Started	Mar 10 12:53:47 PM PDT 24
Finished	Mar 10 12:56:52 PM PDT 24
Peak memory	199264 kb
Host	smart-a1a7d9a1-19fe-4006-94ea-8c6ca8458a01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474677846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.474677846
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_perf.492567637
Short name	T562
Test name
Test status
Simulation time	4019472227 ps
CPU time	228.94 seconds
Started	Mar 10 12:53:49 PM PDT 24
Finished	Mar 10 12:57:39 PM PDT 24
Peak memory	200156 kb
Host	smart-02c92cb7-c319-4248-9b4e-0ee89ec85dfe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=492567637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.492567637
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.2975960790
Short name	T779
Test name
Test status
Simulation time	1393466819 ps
CPU time	0.85 seconds
Started	Mar 10 12:53:44 PM PDT 24
Finished	Mar 10 12:53:45 PM PDT 24
Peak memory	197728 kb
Host	smart-0e23c30e-d1d4-4ad7-835a-c3b5db06547b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2975960790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2975960790
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.3728457172
Short name	T373
Test name
Test status
Simulation time	232102682778 ps
CPU time	150.75 seconds
Started	Mar 10 12:53:51 PM PDT 24
Finished	Mar 10 12:56:23 PM PDT 24
Peak memory	200064 kb
Host	smart-aa3293b0-2e69-4de6-ae35-4718246aa122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728457172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3728457172
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.373744672
Short name	T810
Test name
Test status
Simulation time	1797718401 ps
CPU time	3.83 seconds
Started	Mar 10 12:53:44 PM PDT 24
Finished	Mar 10 12:53:48 PM PDT 24
Peak memory	195500 kb
Host	smart-02c278c3-747d-4c30-a0ca-8a28640661a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373744672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.373744672
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.851656450
Short name	T1124
Test name
Test status
Simulation time	664671131 ps
CPU time	2.99 seconds
Started	Mar 10 12:53:39 PM PDT 24
Finished	Mar 10 12:53:42 PM PDT 24
Peak memory	199356 kb
Host	smart-367b2db7-ba54-461f-95eb-7fdd8856799a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851656450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.851656450
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.308025288
Short name	T829
Test name
Test status
Simulation time	1259284814 ps
CPU time	6.76 seconds
Started	Mar 10 12:53:50 PM PDT 24
Finished	Mar 10 12:53:58 PM PDT 24
Peak memory	199996 kb
Host	smart-98d68a03-ede6-4793-9791-e2bbe5e231ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308025288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.308025288
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.71244795
Short name	T391
Test name
Test status
Simulation time	17974758187 ps
CPU time	30.17 seconds
Started	Mar 10 12:53:37 PM PDT 24
Finished	Mar 10 12:54:07 PM PDT 24
Peak memory	199908 kb
Host	smart-7c57ed46-18ec-4c29-abcf-cb1e2126ef9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71244795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.71244795
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.1199190184
Short name	T684
Test name
Test status
Simulation time	39878556 ps
CPU time	0.61 seconds
Started	Mar 10 12:54:02 PM PDT 24
Finished	Mar 10 12:54:03 PM PDT 24
Peak memory	195432 kb
Host	smart-69e83b4b-a043-475d-9a87-5c8227e5e964
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199190184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1199190184
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.2329962755
Short name	T234
Test name
Test status
Simulation time	245141180265 ps
CPU time	106.56 seconds
Started	Mar 10 12:53:50 PM PDT 24
Finished	Mar 10 12:55:37 PM PDT 24
Peak memory	200128 kb
Host	smart-29a10eb4-9967-409e-82a6-f99a91346cc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329962755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2329962755
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.309587506
Short name	T456
Test name
Test status
Simulation time	72499419144 ps
CPU time	33.85 seconds
Started	Mar 10 12:53:52 PM PDT 24
Finished	Mar 10 12:54:26 PM PDT 24
Peak memory	199360 kb
Host	smart-6c9f280d-c610-461a-a05f-2696ef156586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309587506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.309587506
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.142958211
Short name	T1106
Test name
Test status
Simulation time	134308826327 ps
CPU time	112.41 seconds
Started	Mar 10 12:53:50 PM PDT 24
Finished	Mar 10 12:55:43 PM PDT 24
Peak memory	200156 kb
Host	smart-051a8c13-9100-4e0c-a4ae-3724a6abc617
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142958211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.142958211
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/35.uart_intr.1209845536
Short name	T979
Test name
Test status
Simulation time	70405747526 ps
CPU time	37.16 seconds
Started	Mar 10 12:53:52 PM PDT 24
Finished	Mar 10 12:54:30 PM PDT 24
Peak memory	200216 kb
Host	smart-04d11162-d732-4015-927e-87741b28db72
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209845536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1209845536
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.2934565569
Short name	T978
Test name
Test status
Simulation time	107220042433 ps
CPU time	902.78 seconds
Started	Mar 10 12:53:55 PM PDT 24
Finished	Mar 10 01:09:00 PM PDT 24
Peak memory	200180 kb
Host	smart-512663b5-3cd7-4a2f-9f42-9322d4d88696
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2934565569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2934565569
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.2430043775
Short name	T548
Test name
Test status
Simulation time	6763981985 ps
CPU time	7.85 seconds
Started	Mar 10 12:53:57 PM PDT 24
Finished	Mar 10 12:54:05 PM PDT 24
Peak memory	199392 kb
Host	smart-8df66b05-82b1-48d5-bfe7-4a1b972d6438
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430043775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2430043775
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_noise_filter.2373899613
Short name	T481
Test name
Test status
Simulation time	9274142634 ps
CPU time	18.25 seconds
Started	Mar 10 12:53:56 PM PDT 24
Finished	Mar 10 12:54:15 PM PDT 24
Peak memory	198048 kb
Host	smart-735209a8-1e1a-498c-ac6c-c035c6e3e140
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373899613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2373899613
Directory	/workspace/35.uart_noise_filter/latest

Test location	/workspace/coverage/default/35.uart_perf.3150651973
Short name	T938
Test name
Test status
Simulation time	12434470615 ps
CPU time	634.59 seconds
Started	Mar 10 12:53:56 PM PDT 24
Finished	Mar 10 01:04:32 PM PDT 24
Peak memory	200060 kb
Host	smart-78468fce-1266-49fe-b354-8e2b10311d37
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3150651973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3150651973
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.2572969375
Short name	T432
Test name
Test status
Simulation time	2139152544 ps
CPU time	3.47 seconds
Started	Mar 10 12:53:49 PM PDT 24
Finished	Mar 10 12:53:53 PM PDT 24
Peak memory	198272 kb
Host	smart-5fa86d6b-3e29-4597-ac23-9a58a9685e99
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2572969375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2572969375
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.363024008
Short name	T326
Test name
Test status
Simulation time	141939503142 ps
CPU time	57.16 seconds
Started	Mar 10 12:53:59 PM PDT 24
Finished	Mar 10 12:54:57 PM PDT 24
Peak memory	199436 kb
Host	smart-5ee69e82-6846-47b4-b99a-8610a6fa3a02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363024008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.363024008
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.3097623668
Short name	T614
Test name
Test status
Simulation time	6106209925 ps
CPU time	9.58 seconds
Started	Mar 10 12:53:55 PM PDT 24
Finished	Mar 10 12:54:05 PM PDT 24
Peak memory	195876 kb
Host	smart-62149cb7-5037-4f76-bfeb-dd40d4e9ae6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097623668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3097623668
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.2892413281
Short name	T932
Test name
Test status
Simulation time	433267874 ps
CPU time	1.72 seconds
Started	Mar 10 12:53:48 PM PDT 24
Finished	Mar 10 12:53:50 PM PDT 24
Peak memory	198340 kb
Host	smart-0ee8cb50-33e1-4abc-a5ec-aa490f3dde08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892413281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2892413281
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all.864011734
Short name	T650
Test name
Test status
Simulation time	255401801081 ps
CPU time	307.57 seconds
Started	Mar 10 12:54:02 PM PDT 24
Finished	Mar 10 12:59:09 PM PDT 24
Peak memory	200072 kb
Host	smart-0a6e77a6-087f-46e5-8db0-e5ca71ee3f96
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864011734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.864011734
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/35.uart_stress_all_with_rand_reset.2321838121
Short name	T1083
Test name
Test status
Simulation time	196324835839 ps
CPU time	579.12 seconds
Started	Mar 10 12:53:55 PM PDT 24
Finished	Mar 10 01:03:36 PM PDT 24
Peak memory	212300 kb
Host	smart-fd529301-90ed-4493-a57c-7027a7d56232
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321838121 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2321838121
Directory	/workspace/35.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.3679521446
Short name	T792
Test name
Test status
Simulation time	6840874313 ps
CPU time	11.01 seconds
Started	Mar 10 12:53:56 PM PDT 24
Finished	Mar 10 12:54:08 PM PDT 24
Peak memory	199096 kb
Host	smart-4067fe0a-12fd-4c39-9c56-dd74a06af134
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679521446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3679521446
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.3783652376
Short name	T609
Test name
Test status
Simulation time	75690304373 ps
CPU time	109.74 seconds
Started	Mar 10 12:53:51 PM PDT 24
Finished	Mar 10 12:55:41 PM PDT 24
Peak memory	199988 kb
Host	smart-e4dce2cc-3ba0-41a8-a3a4-80c7818c0927
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783652376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3783652376
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.3969692765
Short name	T925
Test name
Test status
Simulation time	18192180 ps
CPU time	0.52 seconds
Started	Mar 10 12:54:08 PM PDT 24
Finished	Mar 10 12:54:09 PM PDT 24
Peak memory	195496 kb
Host	smart-edfb56a5-05a8-425e-b385-323bf97758a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969692765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3969692765
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.3477823882
Short name	T807
Test name
Test status
Simulation time	108311511891 ps
CPU time	48.12 seconds
Started	Mar 10 12:54:00 PM PDT 24
Finished	Mar 10 12:54:49 PM PDT 24
Peak memory	200124 kb
Host	smart-c116067f-886d-4a06-b32d-eabf0230853d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477823882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3477823882
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.1737552248
Short name	T591
Test name
Test status
Simulation time	37686717201 ps
CPU time	42.98 seconds
Started	Mar 10 12:54:01 PM PDT 24
Finished	Mar 10 12:54:44 PM PDT 24
Peak memory	199352 kb
Host	smart-72b8fb27-a27d-49f5-860d-3c445707d8a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737552248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1737552248
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.1755028072
Short name	T1043
Test name
Test status
Simulation time	144539244712 ps
CPU time	66.69 seconds
Started	Mar 10 12:54:05 PM PDT 24
Finished	Mar 10 12:55:12 PM PDT 24
Peak memory	200156 kb
Host	smart-4b432290-062c-47d9-98b1-4e38f4d8fbaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755028072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1755028072
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_intr.4143183703
Short name	T693
Test name
Test status
Simulation time	128574851233 ps
CPU time	232 seconds
Started	Mar 10 12:54:04 PM PDT 24
Finished	Mar 10 12:57:56 PM PDT 24
Peak memory	200016 kb
Host	smart-bb59f5ec-8dbc-414c-82bd-59401ca735fa
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143183703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.4143183703
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.3782694382
Short name	T762
Test name
Test status
Simulation time	82494542734 ps
CPU time	492.44 seconds
Started	Mar 10 12:54:06 PM PDT 24
Finished	Mar 10 01:02:19 PM PDT 24
Peak memory	200120 kb
Host	smart-3d9cae4b-5383-4244-a414-756da717aea7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3782694382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3782694382
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.2840615523
Short name	T1009
Test name
Test status
Simulation time	2120647989 ps
CPU time	4.24 seconds
Started	Mar 10 12:54:01 PM PDT 24
Finished	Mar 10 12:54:05 PM PDT 24
Peak memory	197928 kb
Host	smart-7a6f46b7-8488-4d3a-b4c2-d08461c3f26f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840615523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2840615523
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.4050323627
Short name	T1114
Test name
Test status
Simulation time	36920620494 ps
CPU time	17.22 seconds
Started	Mar 10 12:54:01 PM PDT 24
Finished	Mar 10 12:54:18 PM PDT 24
Peak memory	193692 kb
Host	smart-1abb6acf-b6db-4c86-8906-17285af27950
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050323627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.4050323627
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.1520832300
Short name	T143
Test name
Test status
Simulation time	22598051156 ps
CPU time	307.93 seconds
Started	Mar 10 12:54:06 PM PDT 24
Finished	Mar 10 12:59:14 PM PDT 24
Peak memory	200200 kb
Host	smart-f2467969-cd28-41e0-9694-75104e226ec2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1520832300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1520832300
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.3727238051
Short name	T683
Test name
Test status
Simulation time	2100016195 ps
CPU time	14.11 seconds
Started	Mar 10 12:54:05 PM PDT 24
Finished	Mar 10 12:54:20 PM PDT 24
Peak memory	197780 kb
Host	smart-a2b3f99b-7af2-4197-82ca-f4eb0a841a1d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3727238051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3727238051
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.3405404538
Short name	T267
Test name
Test status
Simulation time	9452666699 ps
CPU time	4.76 seconds
Started	Mar 10 12:54:01 PM PDT 24
Finished	Mar 10 12:54:06 PM PDT 24
Peak memory	198420 kb
Host	smart-84f25e1c-62d3-4c9b-8d4a-aa31f8fb5fa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405404538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3405404538
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.1065580179
Short name	T790
Test name
Test status
Simulation time	39062137142 ps
CPU time	33.99 seconds
Started	Mar 10 12:54:00 PM PDT 24
Finished	Mar 10 12:54:34 PM PDT 24
Peak memory	195668 kb
Host	smart-6401c0ce-5b40-4ca9-b18e-ab23d913530e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065580179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1065580179
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.380394531
Short name	T656
Test name
Test status
Simulation time	251901850 ps
CPU time	1.47 seconds
Started	Mar 10 12:54:02 PM PDT 24
Finished	Mar 10 12:54:04 PM PDT 24
Peak memory	198248 kb
Host	smart-a4126279-e8a0-4f24-87f0-1121f487876b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380394531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.380394531
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all_with_rand_reset.164166656
Short name	T103
Test name
Test status
Simulation time	724007819075 ps
CPU time	389.7 seconds
Started	Mar 10 12:54:05 PM PDT 24
Finished	Mar 10 01:00:35 PM PDT 24
Peak memory	216704 kb
Host	smart-625d777f-88b4-4c65-ba7d-6cef0bb63696
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164166656 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.164166656
Directory	/workspace/36.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.1248468086
Short name	T598
Test name
Test status
Simulation time	7470516537 ps
CPU time	15.14 seconds
Started	Mar 10 12:54:02 PM PDT 24
Finished	Mar 10 12:54:17 PM PDT 24
Peak memory	199144 kb
Host	smart-2aeba398-09da-4aa0-b835-0a8d15d06ae9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248468086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1248468086
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.3148322724
Short name	T852
Test name
Test status
Simulation time	208383633110 ps
CPU time	144.94 seconds
Started	Mar 10 12:54:02 PM PDT 24
Finished	Mar 10 12:56:27 PM PDT 24
Peak memory	200124 kb
Host	smart-43fff68e-8836-47e3-b8bf-b3c88ada9d3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148322724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3148322724
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.167080086
Short name	T678
Test name
Test status
Simulation time	68336312 ps
CPU time	0.55 seconds
Started	Mar 10 12:54:13 PM PDT 24
Finished	Mar 10 12:54:14 PM PDT 24
Peak memory	194436 kb
Host	smart-f7375486-3d6e-42eb-8194-34a177b6f07b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167080086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.167080086
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.2955463264
Short name	T557
Test name
Test status
Simulation time	51232987714 ps
CPU time	20.33 seconds
Started	Mar 10 12:54:07 PM PDT 24
Finished	Mar 10 12:54:27 PM PDT 24
Peak memory	199912 kb
Host	smart-dc197c0b-aaf3-4944-8d29-dc8af61d9156
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955463264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2955463264
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.1726273800
Short name	T519
Test name
Test status
Simulation time	32798189535 ps
CPU time	61.46 seconds
Started	Mar 10 12:54:05 PM PDT 24
Finished	Mar 10 12:55:07 PM PDT 24
Peak memory	200112 kb
Host	smart-57ce3bf5-ebd3-4164-a4bc-bd4660320b1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726273800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1726273800
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.4072102167
Short name	T832
Test name
Test status
Simulation time	108110875018 ps
CPU time	116.55 seconds
Started	Mar 10 12:54:06 PM PDT 24
Finished	Mar 10 12:56:03 PM PDT 24
Peak memory	200048 kb
Host	smart-182154c4-20da-487e-8e92-954acc502ca7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072102167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4072102167
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_intr.4016614201
Short name	T429
Test name
Test status
Simulation time	53633434948 ps
CPU time	23.34 seconds
Started	Mar 10 12:54:07 PM PDT 24
Finished	Mar 10 12:54:30 PM PDT 24
Peak memory	198440 kb
Host	smart-388a68ff-9860-412a-9dd5-ea6eea11e55e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016614201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4016614201
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.3840795713
Short name	T100
Test name
Test status
Simulation time	119676770134 ps
CPU time	581.07 seconds
Started	Mar 10 12:54:13 PM PDT 24
Finished	Mar 10 01:03:55 PM PDT 24
Peak memory	200164 kb
Host	smart-28adc270-872b-4d71-a4f3-7eda34735732
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3840795713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3840795713
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.484732733
Short name	T1069
Test name
Test status
Simulation time	3557033998 ps
CPU time	7.83 seconds
Started	Mar 10 12:54:12 PM PDT 24
Finished	Mar 10 12:54:20 PM PDT 24
Peak memory	198440 kb
Host	smart-85aaa53d-0190-4317-85af-75a872b55c29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484732733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.484732733
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.4161062376
Short name	T658
Test name
Test status
Simulation time	3039594151 ps
CPU time	2 seconds
Started	Mar 10 12:54:07 PM PDT 24
Finished	Mar 10 12:54:09 PM PDT 24
Peak memory	194824 kb
Host	smart-ac1ba327-9fc1-4ec8-bca0-882498dbb91c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161062376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4161062376
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.3205875200
Short name	T1058
Test name
Test status
Simulation time	18154403762 ps
CPU time	744.4 seconds
Started	Mar 10 12:54:12 PM PDT 24
Finished	Mar 10 01:06:36 PM PDT 24
Peak memory	200044 kb
Host	smart-f35b7d8a-9937-41a1-b412-3372ee5ff01c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3205875200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3205875200
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.3528451944
Short name	T586
Test name
Test status
Simulation time	3722220541 ps
CPU time	7.08 seconds
Started	Mar 10 12:54:06 PM PDT 24
Finished	Mar 10 12:54:14 PM PDT 24
Peak memory	198548 kb
Host	smart-ff3f3528-8f14-4c0c-ba89-72d00faa8910
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3528451944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3528451944
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.1009750977
Short name	T190
Test name
Test status
Simulation time	8117978769 ps
CPU time	8.26 seconds
Started	Mar 10 12:54:13 PM PDT 24
Finished	Mar 10 12:54:21 PM PDT 24
Peak memory	199892 kb
Host	smart-1dbdc22d-e8ed-4970-81fb-a4d250febbf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009750977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1009750977
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.1379635927
Short name	T645
Test name
Test status
Simulation time	5647393466 ps
CPU time	3.22 seconds
Started	Mar 10 12:54:07 PM PDT 24
Finished	Mar 10 12:54:10 PM PDT 24
Peak memory	195916 kb
Host	smart-7ebeae9a-78ab-4c9b-a388-b5a52020d74c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379635927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1379635927
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.3059089434
Short name	T406
Test name
Test status
Simulation time	506022734 ps
CPU time	1.24 seconds
Started	Mar 10 12:54:08 PM PDT 24
Finished	Mar 10 12:54:09 PM PDT 24
Peak memory	198288 kb
Host	smart-0728da1f-2cff-439c-bb40-d2a03c6df31b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059089434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3059089434
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.2743600819
Short name	T676
Test name
Test status
Simulation time	1456677298 ps
CPU time	2.47 seconds
Started	Mar 10 12:54:11 PM PDT 24
Finished	Mar 10 12:54:14 PM PDT 24
Peak memory	198588 kb
Host	smart-26a67af8-9d7b-4262-bea0-37fa14ae6f67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743600819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2743600819
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.3401679129
Short name	T730
Test name
Test status
Simulation time	139274460245 ps
CPU time	236.56 seconds
Started	Mar 10 12:54:09 PM PDT 24
Finished	Mar 10 12:58:06 PM PDT 24
Peak memory	200056 kb
Host	smart-c8dae919-ef61-4c59-8dfb-61fd85a1b2ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401679129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3401679129
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.2873682347
Short name	T728
Test name
Test status
Simulation time	27113362 ps
CPU time	0.56 seconds
Started	Mar 10 12:54:24 PM PDT 24
Finished	Mar 10 12:54:25 PM PDT 24
Peak memory	195472 kb
Host	smart-7a588626-bb14-412c-8268-5137542d14d0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873682347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2873682347
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.705001033
Short name	T1046
Test name
Test status
Simulation time	247770835739 ps
CPU time	561.07 seconds
Started	Mar 10 12:54:12 PM PDT 24
Finished	Mar 10 01:03:34 PM PDT 24
Peak memory	200160 kb
Host	smart-f6fd014a-82aa-424c-aadd-45a2653ed556
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705001033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.705001033
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.187840966
Short name	T1045
Test name
Test status
Simulation time	166078703948 ps
CPU time	68.18 seconds
Started	Mar 10 12:54:12 PM PDT 24
Finished	Mar 10 12:55:20 PM PDT 24
Peak memory	200040 kb
Host	smart-c1b57fa1-5902-45d4-ad4c-acdd1a24c932
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187840966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.187840966
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.3683584791
Short name	T735
Test name
Test status
Simulation time	97993553826 ps
CPU time	178.68 seconds
Started	Mar 10 12:54:12 PM PDT 24
Finished	Mar 10 12:57:11 PM PDT 24
Peak memory	200016 kb
Host	smart-477042c2-ace9-4c85-a3ee-8b5d1fc49069
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683584791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3683584791
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_intr.1142097702
Short name	T781
Test name
Test status
Simulation time	17965868009 ps
CPU time	8.83 seconds
Started	Mar 10 12:54:19 PM PDT 24
Finished	Mar 10 12:54:28 PM PDT 24
Peak memory	199008 kb
Host	smart-f272a8e3-9049-46da-a5f3-de3f0ff33f6f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142097702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1142097702
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.3349978092
Short name	T687
Test name
Test status
Simulation time	127398637126 ps
CPU time	641.9 seconds
Started	Mar 10 12:54:23 PM PDT 24
Finished	Mar 10 01:05:05 PM PDT 24
Peak memory	200200 kb
Host	smart-044462f5-e6a0-43ca-965b-0623f51c8876
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3349978092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3349978092
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_loopback.2448508211
Short name	T994
Test name
Test status
Simulation time	5094189855 ps
CPU time	10.86 seconds
Started	Mar 10 12:54:23 PM PDT 24
Finished	Mar 10 12:54:34 PM PDT 24
Peak memory	198568 kb
Host	smart-5f3dadab-6751-40a1-9390-3ffaa5db324b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448508211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2448508211
Directory	/workspace/38.uart_loopback/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.1773713793
Short name	T475
Test name
Test status
Simulation time	21714954011 ps
CPU time	26.98 seconds
Started	Mar 10 12:54:18 PM PDT 24
Finished	Mar 10 12:54:46 PM PDT 24
Peak memory	198852 kb
Host	smart-ad261378-b888-413f-a466-52ca9c7de215
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1773713793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1773713793
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.2171424812
Short name	T612
Test name
Test status
Simulation time	18755778577 ps
CPU time	251.11 seconds
Started	Mar 10 12:54:26 PM PDT 24
Finished	Mar 10 12:58:37 PM PDT 24
Peak memory	200116 kb
Host	smart-05377691-f61d-4ce2-b568-80e59fd01d20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2171424812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2171424812
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_oversample.3444372682
Short name	T487
Test name
Test status
Simulation time	3168237706 ps
CPU time	4.08 seconds
Started	Mar 10 12:54:18 PM PDT 24
Finished	Mar 10 12:54:22 PM PDT 24
Peak memory	198640 kb
Host	smart-2b81a690-09b7-462c-bc85-3314ce14add8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3444372682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3444372682
Directory	/workspace/38.uart_rx_oversample/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.1935391223
Short name	T672
Test name
Test status
Simulation time	50267695676 ps
CPU time	52.64 seconds
Started	Mar 10 12:54:22 PM PDT 24
Finished	Mar 10 12:55:16 PM PDT 24
Peak memory	199964 kb
Host	smart-a10b4d5e-13ba-4733-a6c1-6267a61428d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935391223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1935391223
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.1545275424
Short name	T1100
Test name
Test status
Simulation time	4333420050 ps
CPU time	2.45 seconds
Started	Mar 10 12:54:18 PM PDT 24
Finished	Mar 10 12:54:22 PM PDT 24
Peak memory	195864 kb
Host	smart-d603035c-d579-41ef-9cbf-54237319fde3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545275424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1545275424
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.3649557830
Short name	T809
Test name
Test status
Simulation time	6332170235 ps
CPU time	16.14 seconds
Started	Mar 10 12:54:11 PM PDT 24
Finished	Mar 10 12:54:28 PM PDT 24
Peak memory	199516 kb
Host	smart-a94c45ef-8770-4d3a-9aee-fb84a88dca2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3649557830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3649557830
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.4058350632
Short name	T770
Test name
Test status
Simulation time	6719210930 ps
CPU time	9.82 seconds
Started	Mar 10 12:54:24 PM PDT 24
Finished	Mar 10 12:54:34 PM PDT 24
Peak memory	198952 kb
Host	smart-b821adb6-c431-4431-820f-af40d7295c69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058350632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.4058350632
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.2091702524
Short name	T408
Test name
Test status
Simulation time	31558477813 ps
CPU time	46.34 seconds
Started	Mar 10 12:54:14 PM PDT 24
Finished	Mar 10 12:55:00 PM PDT 24
Peak memory	200172 kb
Host	smart-d3d85d27-5154-4044-9a44-53120a5f2747
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091702524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2091702524
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/default/39.uart_alert_test.1062860166
Short name	T831
Test name
Test status
Simulation time	17655134 ps
CPU time	0.54 seconds
Started	Mar 10 12:54:32 PM PDT 24
Finished	Mar 10 12:54:33 PM PDT 24
Peak memory	195508 kb
Host	smart-2274f3a4-dfe7-4432-b1e6-6f6f6bf77c08
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062860166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1062860166
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.2487702119
Short name	T579
Test name
Test status
Simulation time	46462142404 ps
CPU time	129.53 seconds
Started	Mar 10 12:54:23 PM PDT 24
Finished	Mar 10 12:56:33 PM PDT 24
Peak memory	200068 kb
Host	smart-c826dd04-cb4b-4f05-9bf5-4d75112ac2fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487702119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2487702119
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.2318328459
Short name	T318
Test name
Test status
Simulation time	104299233374 ps
CPU time	56.4 seconds
Started	Mar 10 12:54:24 PM PDT 24
Finished	Mar 10 12:55:20 PM PDT 24
Peak memory	200016 kb
Host	smart-f93ae7c8-2463-435a-8987-4eb66546fe0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318328459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2318328459
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.1174057558
Short name	T117
Test name
Test status
Simulation time	121701378593 ps
CPU time	27.66 seconds
Started	Mar 10 12:54:25 PM PDT 24
Finished	Mar 10 12:54:52 PM PDT 24
Peak memory	200168 kb
Host	smart-ca9106fd-cf76-4646-aaa2-b9dee55889ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174057558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1174057558
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.1564659720
Short name	T484
Test name
Test status
Simulation time	49680615502 ps
CPU time	78.84 seconds
Started	Mar 10 12:54:23 PM PDT 24
Finished	Mar 10 12:55:42 PM PDT 24
Peak memory	197548 kb
Host	smart-7af561f4-dc02-4e6a-8207-bb1a287fa7f2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564659720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1564659720
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.2398838020
Short name	T1010
Test name
Test status
Simulation time	70724558611 ps
CPU time	126.34 seconds
Started	Mar 10 12:54:29 PM PDT 24
Finished	Mar 10 12:56:36 PM PDT 24
Peak memory	200128 kb
Host	smart-55f8c0b6-5923-4a54-ac85-7df456ed17bb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2398838020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2398838020
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/39.uart_loopback.540417717
Short name	T565
Test name
Test status
Simulation time	2775289760 ps
CPU time	2.33 seconds
Started	Mar 10 12:54:29 PM PDT 24
Finished	Mar 10 12:54:31 PM PDT 24
Peak memory	197908 kb
Host	smart-4ed92899-cb71-4e7c-b7df-349c760ac364
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540417717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.540417717
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.2843878283
Short name	T1061
Test name
Test status
Simulation time	51911480537 ps
CPU time	18.75 seconds
Started	Mar 10 12:54:31 PM PDT 24
Finished	Mar 10 12:54:49 PM PDT 24
Peak memory	198780 kb
Host	smart-23116cb2-1ef4-40fd-ab39-f7c26a02f486
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843878283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2843878283
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.3359655487
Short name	T758
Test name
Test status
Simulation time	9587032126 ps
CPU time	119.69 seconds
Started	Mar 10 12:54:28 PM PDT 24
Finished	Mar 10 12:56:28 PM PDT 24
Peak memory	199968 kb
Host	smart-26911046-019a-40dc-b8f9-7b05dd4e3bf6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3359655487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3359655487
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_oversample.1673667058
Short name	T23
Test name
Test status
Simulation time	5014709427 ps
CPU time	10.86 seconds
Started	Mar 10 12:54:23 PM PDT 24
Finished	Mar 10 12:54:34 PM PDT 24
Peak memory	198912 kb
Host	smart-7ab340ae-3a83-475b-aefa-9827e69e6dc5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1673667058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1673667058
Directory	/workspace/39.uart_rx_oversample/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.362945792
Short name	T364
Test name
Test status
Simulation time	53199885656 ps
CPU time	35.6 seconds
Started	Mar 10 12:54:30 PM PDT 24
Finished	Mar 10 12:55:06 PM PDT 24
Peak memory	199756 kb
Host	smart-4fd74b97-8612-484d-8f00-458419c5c1f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362945792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.362945792
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.2354260725
Short name	T1025
Test name
Test status
Simulation time	4655222732 ps
CPU time	2.52 seconds
Started	Mar 10 12:54:28 PM PDT 24
Finished	Mar 10 12:54:31 PM PDT 24
Peak memory	195924 kb
Host	smart-0710e597-0aea-4082-9795-c1ff1dcaeac0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354260725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2354260725
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.1639057799
Short name	T1027
Test name
Test status
Simulation time	5559485914 ps
CPU time	8.28 seconds
Started	Mar 10 12:54:25 PM PDT 24
Finished	Mar 10 12:54:34 PM PDT 24
Peak memory	199960 kb
Host	smart-4876b09f-0190-4501-8a71-a2e046bef251
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639057799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1639057799
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all.4075564332
Short name	T175
Test name
Test status
Simulation time	328530118964 ps
CPU time	49.56 seconds
Started	Mar 10 12:54:29 PM PDT 24
Finished	Mar 10 12:55:18 PM PDT 24
Peak memory	200104 kb
Host	smart-4a135918-6415-4a53-937d-f19a88ca940b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075564332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4075564332
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.4261140413
Short name	T1087
Test name
Test status
Simulation time	6397693148 ps
CPU time	13.79 seconds
Started	Mar 10 12:54:28 PM PDT 24
Finished	Mar 10 12:54:42 PM PDT 24
Peak memory	199076 kb
Host	smart-6d609962-7e5f-43f1-9f57-fe3d383dcc89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261140413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.4261140413
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.3170989327
Short name	T510
Test name
Test status
Simulation time	112269299474 ps
CPU time	221.8 seconds
Started	Mar 10 12:54:24 PM PDT 24
Finished	Mar 10 12:58:06 PM PDT 24
Peak memory	200096 kb
Host	smart-24c8844b-7f0b-46c0-8a57-a9f3f7ae1588
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170989327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3170989327
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.684672161
Short name	T29
Test name
Test status
Simulation time	38446235 ps
CPU time	0.56 seconds
Started	Mar 10 12:48:57 PM PDT 24
Finished	Mar 10 12:48:58 PM PDT 24
Peak memory	194476 kb
Host	smart-de4d5b93-54c3-44df-ad86-af87ec769e53
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684672161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.684672161
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.3066404018
Short name	T750
Test name
Test status
Simulation time	139237796169 ps
CPU time	220.58 seconds
Started	Mar 10 12:48:53 PM PDT 24
Finished	Mar 10 12:52:33 PM PDT 24
Peak memory	200152 kb
Host	smart-c76eb7c4-af36-4624-8e35-f32a629d07c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066404018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3066404018
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.1351669293
Short name	T1119
Test name
Test status
Simulation time	247807655086 ps
CPU time	71.31 seconds
Started	Mar 10 12:48:50 PM PDT 24
Finished	Mar 10 12:50:02 PM PDT 24
Peak memory	200116 kb
Host	smart-b0004920-f7b6-4502-b7a5-b219dd2fbee4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1351669293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1351669293
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.2937667937
Short name	T180
Test name
Test status
Simulation time	79171639539 ps
CPU time	36.8 seconds
Started	Mar 10 12:48:52 PM PDT 24
Finished	Mar 10 12:49:29 PM PDT 24
Peak memory	199936 kb
Host	smart-fcdc825f-d7ca-454c-a39b-81bae5b531d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937667937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2937667937
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_intr.1806654658
Short name	T659
Test name
Test status
Simulation time	23252937319 ps
CPU time	24.41 seconds
Started	Mar 10 12:48:51 PM PDT 24
Finished	Mar 10 12:49:16 PM PDT 24
Peak memory	199760 kb
Host	smart-8e11eaee-5414-4cca-8e9d-31783bd5ca15
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806654658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1806654658
Directory	/workspace/4.uart_intr/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.1885033490
Short name	T1019
Test name
Test status
Simulation time	164998722675 ps
CPU time	283.28 seconds
Started	Mar 10 12:48:57 PM PDT 24
Finished	Mar 10 12:53:40 PM PDT 24
Peak memory	200204 kb
Host	smart-cd2b05e6-aa09-4134-90bb-1b891a221e38
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1885033490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1885033490
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.1841137468
Short name	T888
Test name
Test status
Simulation time	2185428954 ps
CPU time	4.94 seconds
Started	Mar 10 12:48:55 PM PDT 24
Finished	Mar 10 12:49:00 PM PDT 24
Peak memory	197488 kb
Host	smart-fe18141a-2640-4f1b-8167-ff613b8f26f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841137468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1841137468
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.2223325511
Short name	T141
Test name
Test status
Simulation time	136809293056 ps
CPU time	50.74 seconds
Started	Mar 10 12:48:51 PM PDT 24
Finished	Mar 10 12:49:42 PM PDT 24
Peak memory	200244 kb
Host	smart-74e9fcb3-3ec9-4782-8759-80e53c4249b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223325511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2223325511
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.3459542046
Short name	T1120
Test name
Test status
Simulation time	20361034489 ps
CPU time	563.69 seconds
Started	Mar 10 12:48:56 PM PDT 24
Finished	Mar 10 12:58:20 PM PDT 24
Peak memory	200100 kb
Host	smart-b26e5c6f-990f-4612-992f-f4ba8fd8a4ef
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3459542046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3459542046
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_oversample.595177966
Short name	T1085
Test name
Test status
Simulation time	3924558503 ps
CPU time	7.1 seconds
Started	Mar 10 12:48:50 PM PDT 24
Finished	Mar 10 12:48:58 PM PDT 24
Peak memory	198676 kb
Host	smart-563dde1d-615c-4857-a202-48cb6f2787e4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=595177966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.595177966
Directory	/workspace/4.uart_rx_oversample/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.862793189
Short name	T700
Test name
Test status
Simulation time	2575161325 ps
CPU time	4.65 seconds
Started	Mar 10 12:48:50 PM PDT 24
Finished	Mar 10 12:48:55 PM PDT 24
Peak memory	195592 kb
Host	smart-01a0fab4-4a91-4372-b649-2a9be0917e55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862793189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.862793189
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.1664022261
Short name	T93
Test name
Test status
Simulation time	148236714 ps
CPU time	0.82 seconds
Started	Mar 10 12:48:55 PM PDT 24
Finished	Mar 10 12:48:56 PM PDT 24
Peak memory	217448 kb
Host	smart-da34e048-f99f-44f3-a3a8-016799ac77da
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664022261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1664022261
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/4.uart_smoke.2897880502
Short name	T405
Test name
Test status
Simulation time	453097991 ps
CPU time	1.47 seconds
Started	Mar 10 12:48:46 PM PDT 24
Finished	Mar 10 12:48:48 PM PDT 24
Peak memory	197948 kb
Host	smart-29579da6-549a-4360-8117-3016c9cc2999
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897880502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2897880502
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.8537129
Short name	T465
Test name
Test status
Simulation time	300262386711 ps
CPU time	52.23 seconds
Started	Mar 10 12:48:54 PM PDT 24
Finished	Mar 10 12:49:46 PM PDT 24
Peak memory	200096 kb
Host	smart-531377c9-34f7-43da-8e8c-4595a7fc37ec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8537129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.8537129
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.4020665132
Short name	T1081
Test name
Test status
Simulation time	7359404815 ps
CPU time	45.97 seconds
Started	Mar 10 12:48:55 PM PDT 24
Finished	Mar 10 12:49:41 PM PDT 24
Peak memory	199572 kb
Host	smart-407f3910-4949-4dc1-a720-cb4dd1f9584f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020665132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.4020665132
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.3412475940
Short name	T589
Test name
Test status
Simulation time	24732624405 ps
CPU time	39.21 seconds
Started	Mar 10 12:48:48 PM PDT 24
Finished	Mar 10 12:49:28 PM PDT 24
Peak memory	199920 kb
Host	smart-cad572ba-8119-4a7b-a889-15af6d87fd95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412475940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3412475940
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.3889308404
Short name	T846
Test name
Test status
Simulation time	90595823 ps
CPU time	0.53 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:54:49 PM PDT 24
Peak memory	195496 kb
Host	smart-9306f370-1f59-46c7-b5eb-ae215a5f0939
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889308404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3889308404
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.917289313
Short name	T1047
Test name
Test status
Simulation time	59417650567 ps
CPU time	38.17 seconds
Started	Mar 10 12:54:34 PM PDT 24
Finished	Mar 10 12:55:13 PM PDT 24
Peak memory	200072 kb
Host	smart-5c82c7b5-9cd3-4c9a-b127-fd7212b1eca9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917289313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.917289313
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.1895572207
Short name	T847
Test name
Test status
Simulation time	24960148838 ps
CPU time	20.38 seconds
Started	Mar 10 12:54:36 PM PDT 24
Finished	Mar 10 12:54:56 PM PDT 24
Peak memory	200008 kb
Host	smart-fd5272f1-752c-48b0-a1d0-cf540f5466f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895572207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1895572207
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.405328949
Short name	T45
Test name
Test status
Simulation time	133070043856 ps
CPU time	175.15 seconds
Started	Mar 10 12:54:32 PM PDT 24
Finished	Mar 10 12:57:28 PM PDT 24
Peak memory	200208 kb
Host	smart-8293b368-a1d8-4197-b84c-af3b75c1fe17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405328949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.405328949
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.3297887367
Short name	T706
Test name
Test status
Simulation time	34514733554 ps
CPU time	23.23 seconds
Started	Mar 10 12:54:33 PM PDT 24
Finished	Mar 10 12:54:56 PM PDT 24
Peak memory	200140 kb
Host	smart-bf50abf7-3501-4b89-8575-582036e238ca
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297887367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3297887367
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.2995948167
Short name	T613
Test name
Test status
Simulation time	164379654359 ps
CPU time	962.62 seconds
Started	Mar 10 12:54:47 PM PDT 24
Finished	Mar 10 01:10:50 PM PDT 24
Peak memory	200156 kb
Host	smart-3258365c-1cc2-4f05-ac6b-33c5df31ca69
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2995948167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2995948167
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.4135613051
Short name	T864
Test name
Test status
Simulation time	1417478461 ps
CPU time	3.05 seconds
Started	Mar 10 12:54:47 PM PDT 24
Finished	Mar 10 12:54:51 PM PDT 24
Peak memory	195580 kb
Host	smart-380d3c9e-36c0-4555-988d-295eb1fa86b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135613051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4135613051
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.4281128729
Short name	T595
Test name
Test status
Simulation time	32177790086 ps
CPU time	50.4 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:55:38 PM PDT 24
Peak memory	197548 kb
Host	smart-21cb7f1e-cdb4-49df-8ccf-159b40d2248e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281128729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.4281128729
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.2060347760
Short name	T654
Test name
Test status
Simulation time	29995720862 ps
CPU time	795.94 seconds
Started	Mar 10 12:54:47 PM PDT 24
Finished	Mar 10 01:08:03 PM PDT 24
Peak memory	200112 kb
Host	smart-2bc85ab1-b28a-41dd-b6c6-bf4385cca552
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2060347760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2060347760
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.4132938965
Short name	T471
Test name
Test status
Simulation time	2325306229 ps
CPU time	1.17 seconds
Started	Mar 10 12:54:33 PM PDT 24
Finished	Mar 10 12:54:34 PM PDT 24
Peak memory	198196 kb
Host	smart-e1127723-a5dd-4196-9336-bad3102ab8a0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4132938965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4132938965
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.1294681723
Short name	T777
Test name
Test status
Simulation time	2664090480 ps
CPU time	1.96 seconds
Started	Mar 10 12:54:47 PM PDT 24
Finished	Mar 10 12:54:49 PM PDT 24
Peak memory	195672 kb
Host	smart-b976b77b-97e5-4d32-a90b-3de92942f4ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294681723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1294681723
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.3824769307
Short name	T858
Test name
Test status
Simulation time	680759289 ps
CPU time	2.36 seconds
Started	Mar 10 12:54:35 PM PDT 24
Finished	Mar 10 12:54:37 PM PDT 24
Peak memory	199424 kb
Host	smart-99cf2fa7-7b4d-46f0-a1a7-54d18d39559a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3824769307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3824769307
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.3983860282
Short name	T1048
Test name
Test status
Simulation time	105045889735 ps
CPU time	1115.69 seconds
Started	Mar 10 12:54:50 PM PDT 24
Finished	Mar 10 01:13:25 PM PDT 24
Peak memory	208496 kb
Host	smart-91e52dca-0300-495b-828f-d884f607c1a8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983860282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3983860282
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_stress_all_with_rand_reset.778760500
Short name	T376
Test name
Test status
Simulation time	18613304890 ps
CPU time	281.63 seconds
Started	Mar 10 12:54:49 PM PDT 24
Finished	Mar 10 12:59:31 PM PDT 24
Peak memory	208456 kb
Host	smart-6ddb1c58-571c-4df8-8cc1-2c5f6d53b9de
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778760500 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.778760500
Directory	/workspace/40.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.2393937026
Short name	T399
Test name
Test status
Simulation time	850523076 ps
CPU time	1.76 seconds
Started	Mar 10 12:54:46 PM PDT 24
Finished	Mar 10 12:54:48 PM PDT 24
Peak memory	198756 kb
Host	smart-8acb5951-f838-45ae-8f5c-be644ab458e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393937026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2393937026
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.3769491503
Short name	T689
Test name
Test status
Simulation time	29942133411 ps
CPU time	14.5 seconds
Started	Mar 10 12:54:35 PM PDT 24
Finished	Mar 10 12:54:49 PM PDT 24
Peak memory	200080 kb
Host	smart-cc930c1a-7b5b-477c-8924-676bedff7bba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769491503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3769491503
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.2132829581
Short name	T438
Test name
Test status
Simulation time	21398897 ps
CPU time	0.57 seconds
Started	Mar 10 12:54:51 PM PDT 24
Finished	Mar 10 12:54:52 PM PDT 24
Peak memory	195468 kb
Host	smart-52d4bab6-989d-4d6a-b976-e29d2cc21836
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132829581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2132829581
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.4000328955
Short name	T1037
Test name
Test status
Simulation time	193710868362 ps
CPU time	537.07 seconds
Started	Mar 10 12:54:49 PM PDT 24
Finished	Mar 10 01:03:46 PM PDT 24
Peak memory	200064 kb
Host	smart-fc23f9f4-2682-4dda-b926-eb168aada13c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000328955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4000328955
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.1282791128
Short name	T800
Test name
Test status
Simulation time	57668336384 ps
CPU time	41.14 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:55:30 PM PDT 24
Peak memory	198676 kb
Host	smart-39a6fdd7-f5d6-452a-99ea-c366715b9a38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282791128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1282791128
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.3113447227
Short name	T357
Test name
Test status
Simulation time	147358855183 ps
CPU time	111.97 seconds
Started	Mar 10 12:54:49 PM PDT 24
Finished	Mar 10 12:56:41 PM PDT 24
Peak memory	200072 kb
Host	smart-4b445c32-3df5-44df-84c4-bd687caee7c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113447227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3113447227
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/41.uart_intr.3163985532
Short name	T1033
Test name
Test status
Simulation time	320461704718 ps
CPU time	120.74 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:56:49 PM PDT 24
Peak memory	197296 kb
Host	smart-c138b617-c559-44e5-a0b1-4dd5118aae70
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163985532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3163985532
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_long_xfer_wo_dly.428246605
Short name	T472
Test name
Test status
Simulation time	72789611584 ps
CPU time	273.43 seconds
Started	Mar 10 12:54:50 PM PDT 24
Finished	Mar 10 12:59:24 PM PDT 24
Peak memory	200100 kb
Host	smart-3170c959-d2e2-47aa-b411-5d667d328ef1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=428246605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.428246605
Directory	/workspace/41.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/41.uart_loopback.347508242
Short name	T486
Test name
Test status
Simulation time	578105375 ps
CPU time	1.61 seconds
Started	Mar 10 12:54:51 PM PDT 24
Finished	Mar 10 12:54:53 PM PDT 24
Peak memory	196744 kb
Host	smart-0f0dda5c-0ac8-458a-aa2f-3a299995abdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347508242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.347508242
Directory	/workspace/41.uart_loopback/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.672731881
Short name	T1012
Test name
Test status
Simulation time	491792064298 ps
CPU time	53.76 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:55:42 PM PDT 24
Peak memory	200264 kb
Host	smart-6f172a85-4442-4532-9d0b-be98e0fb3332
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672731881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.672731881
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.733147493
Short name	T855
Test name
Test status
Simulation time	2173997405 ps
CPU time	102.33 seconds
Started	Mar 10 12:54:54 PM PDT 24
Finished	Mar 10 12:56:37 PM PDT 24
Peak memory	200132 kb
Host	smart-79ee8000-8d6a-4b3f-a15a-3fa11a6ac2c2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=733147493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.733147493
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.2238775638
Short name	T1026
Test name
Test status
Simulation time	6043943176 ps
CPU time	24.83 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:55:13 PM PDT 24
Peak memory	198840 kb
Host	smart-b9f06c54-bb96-4218-8fb7-cef8c4de77ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2238775638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2238775638
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.1302676871
Short name	T16
Test name
Test status
Simulation time	117589528221 ps
CPU time	157.54 seconds
Started	Mar 10 12:54:47 PM PDT 24
Finished	Mar 10 12:57:25 PM PDT 24
Peak memory	200148 kb
Host	smart-309355f9-bdd8-4348-853a-1feedfae39da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302676871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1302676871
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.171280745
Short name	T1059
Test name
Test status
Simulation time	5303504048 ps
CPU time	2.66 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:54:50 PM PDT 24
Peak memory	196008 kb
Host	smart-39c04181-dd17-42d5-86cf-5eddbbbab6bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171280745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.171280745
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.4257909617
Short name	T440
Test name
Test status
Simulation time	462345735 ps
CPU time	2.01 seconds
Started	Mar 10 12:54:48 PM PDT 24
Finished	Mar 10 12:54:50 PM PDT 24
Peak memory	198536 kb
Host	smart-2d3950cb-3761-4161-aa4e-8c58fc18a647
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257909617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4257909617
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.1592220489
Short name	T1068
Test name
Test status
Simulation time	575418234219 ps
CPU time	177.24 seconds
Started	Mar 10 12:54:52 PM PDT 24
Finished	Mar 10 12:57:50 PM PDT 24
Peak memory	200076 kb
Host	smart-0440996f-c025-4161-91d1-e5dc2091fe29
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592220489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1592220489
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.2489733651
Short name	T680
Test name
Test status
Simulation time	1508411240 ps
CPU time	4.45 seconds
Started	Mar 10 12:54:52 PM PDT 24
Finished	Mar 10 12:54:57 PM PDT 24
Peak memory	198548 kb
Host	smart-cc413ac7-7dd8-42e3-887f-3a164817394b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489733651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2489733651
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.2526141597
Short name	T1084
Test name
Test status
Simulation time	26693050924 ps
CPU time	37.25 seconds
Started	Mar 10 12:54:49 PM PDT 24
Finished	Mar 10 12:55:26 PM PDT 24
Peak memory	200072 kb
Host	smart-405e5354-2fab-4de3-a8a5-72c68685e10d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2526141597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2526141597
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.1689303603
Short name	T458
Test name
Test status
Simulation time	43272066 ps
CPU time	0.59 seconds
Started	Mar 10 12:55:01 PM PDT 24
Finished	Mar 10 12:55:02 PM PDT 24
Peak memory	195512 kb
Host	smart-82955f23-b86c-48f0-895d-c6d4176b7af3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689303603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1689303603
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.180148913
Short name	T245
Test name
Test status
Simulation time	145478189480 ps
CPU time	43.88 seconds
Started	Mar 10 12:54:57 PM PDT 24
Finished	Mar 10 12:55:41 PM PDT 24
Peak memory	200148 kb
Host	smart-4880d7b8-cd54-4107-8b37-0a7b000a2e1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180148913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.180148913
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.3244296117
Short name	T319
Test name
Test status
Simulation time	26879034776 ps
CPU time	45.65 seconds
Started	Mar 10 12:54:58 PM PDT 24
Finished	Mar 10 12:55:43 PM PDT 24
Peak memory	200056 kb
Host	smart-b0c42f6e-fa36-4b7e-930f-e9d0ed0031b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244296117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3244296117
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_intr.1192584195
Short name	T1078
Test name
Test status
Simulation time	1029211736609 ps
CPU time	505.05 seconds
Started	Mar 10 12:54:56 PM PDT 24
Finished	Mar 10 01:03:21 PM PDT 24
Peak memory	199468 kb
Host	smart-343b3a49-ec82-47d0-9789-6de2e5ac508a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192584195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1192584195
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.811413739
Short name	T46
Test name
Test status
Simulation time	87100049902 ps
CPU time	116.52 seconds
Started	Mar 10 12:55:01 PM PDT 24
Finished	Mar 10 12:56:58 PM PDT 24
Peak memory	200064 kb
Host	smart-96113343-0b95-4bbe-9871-8d986b5c16c7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=811413739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.811413739
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.2762053797
Short name	T597
Test name
Test status
Simulation time	6860714016 ps
CPU time	13.97 seconds
Started	Mar 10 12:55:01 PM PDT 24
Finished	Mar 10 12:55:15 PM PDT 24
Peak memory	199964 kb
Host	smart-d8fbf98e-576c-41a1-be52-9e692a592372
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762053797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2762053797
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.3048854363
Short name	T824
Test name
Test status
Simulation time	9260336251 ps
CPU time	13.45 seconds
Started	Mar 10 12:54:57 PM PDT 24
Finished	Mar 10 12:55:10 PM PDT 24
Peak memory	193944 kb
Host	smart-ea7d97f3-f8f4-4d28-bf46-2dc6f47263dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048854363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3048854363
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_perf.524607319
Short name	T787
Test name
Test status
Simulation time	26571525718 ps
CPU time	1416.51 seconds
Started	Mar 10 12:55:00 PM PDT 24
Finished	Mar 10 01:18:37 PM PDT 24
Peak memory	200064 kb
Host	smart-9481ac1c-cd22-4517-bf32-d5fe441c54dd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=524607319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.524607319
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.1119343605
Short name	T430
Test name
Test status
Simulation time	5678861589 ps
CPU time	10.13 seconds
Started	Mar 10 12:54:56 PM PDT 24
Finished	Mar 10 12:55:06 PM PDT 24
Peak memory	198440 kb
Host	smart-4c9f0da4-1934-41a3-b39b-49014a16e53b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1119343605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1119343605
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.2864962920
Short name	T101
Test name
Test status
Simulation time	154196135551 ps
CPU time	60.26 seconds
Started	Mar 10 12:54:55 PM PDT 24
Finished	Mar 10 12:55:55 PM PDT 24
Peak memory	199124 kb
Host	smart-3fd76e8c-4b8b-46a2-99d2-9cb947fe2c1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2864962920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2864962920
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.736942017
Short name	T593
Test name
Test status
Simulation time	4899681011 ps
CPU time	8.76 seconds
Started	Mar 10 12:54:59 PM PDT 24
Finished	Mar 10 12:55:07 PM PDT 24
Peak memory	195916 kb
Host	smart-57f2315d-1a89-4d24-94c8-c928e283be2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736942017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.736942017
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.3573811782
Short name	T850
Test name
Test status
Simulation time	10525114701 ps
CPU time	20.3 seconds
Started	Mar 10 12:54:51 PM PDT 24
Finished	Mar 10 12:55:12 PM PDT 24
Peak memory	200076 kb
Host	smart-2e73a691-b66f-4cd2-adcd-91411e270b64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3573811782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3573811782
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_stress_all.2647314954
Short name	T666
Test name
Test status
Simulation time	92535645361 ps
CPU time	169.68 seconds
Started	Mar 10 12:54:59 PM PDT 24
Finished	Mar 10 12:57:49 PM PDT 24
Peak memory	200192 kb
Host	smart-63c96c22-a8d9-4bbd-9dbb-399a0da15d2e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647314954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2647314954
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/42.uart_stress_all_with_rand_reset.3750399827
Short name	T845
Test name
Test status
Simulation time	67965011220 ps
CPU time	115.76 seconds
Started	Mar 10 12:55:03 PM PDT 24
Finished	Mar 10 12:56:59 PM PDT 24
Peak memory	211188 kb
Host	smart-ac564324-e60c-42d6-9fd7-7dc3283cad82
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750399827 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3750399827
Directory	/workspace/42.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.1478994084
Short name	T419
Test name
Test status
Simulation time	709172511 ps
CPU time	2.31 seconds
Started	Mar 10 12:54:58 PM PDT 24
Finished	Mar 10 12:55:00 PM PDT 24
Peak memory	197904 kb
Host	smart-8559a2d7-a258-4093-86b9-2dcea9dce1a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478994084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1478994084
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.3300495475
Short name	T482
Test name
Test status
Simulation time	37424552362 ps
CPU time	70.48 seconds
Started	Mar 10 12:54:57 PM PDT 24
Finished	Mar 10 12:56:07 PM PDT 24
Peak memory	200132 kb
Host	smart-fdc3e753-25fe-4115-811a-b44fb21e5afb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300495475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3300495475
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.1542337419
Short name	T52
Test name
Test status
Simulation time	52010729 ps
CPU time	0.55 seconds
Started	Mar 10 12:55:06 PM PDT 24
Finished	Mar 10 12:55:07 PM PDT 24
Peak memory	195468 kb
Host	smart-9776bbb8-86fb-4e83-8718-517af0c29424
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542337419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1542337419
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.1691332561
Short name	T634
Test name
Test status
Simulation time	226708089788 ps
CPU time	176.05 seconds
Started	Mar 10 12:55:03 PM PDT 24
Finished	Mar 10 12:58:00 PM PDT 24
Peak memory	200116 kb
Host	smart-51d01c3f-bf80-4db2-a1bc-04e00ab4c4e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1691332561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1691332561
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.1213864708
Short name	T346
Test name
Test status
Simulation time	215870127544 ps
CPU time	336.52 seconds
Started	Mar 10 12:55:03 PM PDT 24
Finished	Mar 10 01:00:40 PM PDT 24
Peak memory	200132 kb
Host	smart-35d8ed4f-babd-4de4-aeda-b1fb823240d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213864708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1213864708
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.1452395022
Short name	T110
Test name
Test status
Simulation time	66066238021 ps
CPU time	49.45 seconds
Started	Mar 10 12:55:09 PM PDT 24
Finished	Mar 10 12:55:58 PM PDT 24
Peak memory	200144 kb
Host	smart-df4707ab-a480-475c-8f2b-a7ed30178292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452395022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1452395022
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.2640961182
Short name	T428
Test name
Test status
Simulation time	87968323763 ps
CPU time	129.01 seconds
Started	Mar 10 12:55:09 PM PDT 24
Finished	Mar 10 12:57:19 PM PDT 24
Peak memory	199724 kb
Host	smart-7a76714d-3185-4f20-8b41-7a1bc3662ba4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640961182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2640961182
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.3388703349
Short name	T667
Test name
Test status
Simulation time	128411189132 ps
CPU time	444.2 seconds
Started	Mar 10 12:55:08 PM PDT 24
Finished	Mar 10 01:02:33 PM PDT 24
Peak memory	200064 kb
Host	smart-49023694-9355-428a-a452-9e63b88f1955
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3388703349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3388703349
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_loopback.3487770461
Short name	T1093
Test name
Test status
Simulation time	10377762518 ps
CPU time	8.16 seconds
Started	Mar 10 12:55:07 PM PDT 24
Finished	Mar 10 12:55:15 PM PDT 24
Peak memory	198628 kb
Host	smart-4ea4c1ca-7fcd-4187-8e03-035a638bb81a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3487770461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3487770461
Directory	/workspace/43.uart_loopback/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.3635701427
Short name	T848
Test name
Test status
Simulation time	132171210209 ps
CPU time	135.6 seconds
Started	Mar 10 12:55:09 PM PDT 24
Finished	Mar 10 12:57:25 PM PDT 24
Peak memory	200224 kb
Host	smart-a559ee79-af3b-493a-80b7-3daaaff51504
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3635701427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3635701427
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.182431062
Short name	T497
Test name
Test status
Simulation time	19532664337 ps
CPU time	324.74 seconds
Started	Mar 10 12:55:06 PM PDT 24
Finished	Mar 10 01:00:31 PM PDT 24
Peak memory	200160 kb
Host	smart-cbf76729-61f2-46eb-96ea-58f6a3547e6d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=182431062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.182431062
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.2883064606
Short name	T546
Test name
Test status
Simulation time	1791796903 ps
CPU time	9.47 seconds
Started	Mar 10 12:55:07 PM PDT 24
Finished	Mar 10 12:55:16 PM PDT 24
Peak memory	197912 kb
Host	smart-66e269d2-a13c-468e-982e-03f3f4d1a8dd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2883064606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2883064606
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.964400941
Short name	T911
Test name
Test status
Simulation time	33345555370 ps
CPU time	50.94 seconds
Started	Mar 10 12:55:08 PM PDT 24
Finished	Mar 10 12:55:59 PM PDT 24
Peak memory	199264 kb
Host	smart-2cdfc0d9-de05-40e2-bffe-c5628bbc3353
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964400941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.964400941
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.2473020642
Short name	T473
Test name
Test status
Simulation time	38873322388 ps
CPU time	11.76 seconds
Started	Mar 10 12:55:09 PM PDT 24
Finished	Mar 10 12:55:20 PM PDT 24
Peak memory	195608 kb
Host	smart-ddf0af3b-c701-4903-9d5a-bc8c6c15f3bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473020642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2473020642
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.1931325914
Short name	T975
Test name
Test status
Simulation time	571080046 ps
CPU time	1.86 seconds
Started	Mar 10 12:55:03 PM PDT 24
Finished	Mar 10 12:55:05 PM PDT 24
Peak memory	198572 kb
Host	smart-a35e72a8-74e6-4019-ae56-9fa2d1a8e3b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931325914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1931325914
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.3626770369
Short name	T417
Test name
Test status
Simulation time	2161179984 ps
CPU time	1.62 seconds
Started	Mar 10 12:55:08 PM PDT 24
Finished	Mar 10 12:55:10 PM PDT 24
Peak memory	198344 kb
Host	smart-ae3531c2-33c8-4655-b56b-1ae386ecfd96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626770369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3626770369
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/43.uart_tx_rx.2625084304
Short name	T749
Test name
Test status
Simulation time	51544032024 ps
CPU time	22.45 seconds
Started	Mar 10 12:55:01 PM PDT 24
Finished	Mar 10 12:55:24 PM PDT 24
Peak memory	199832 kb
Host	smart-04c64c88-fa4d-4d0a-ba95-bce0065ff4ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625084304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2625084304
Directory	/workspace/43.uart_tx_rx/latest

Test location	/workspace/coverage/default/44.uart_alert_test.2012978386
Short name	T450
Test name
Test status
Simulation time	19631606 ps
CPU time	0.55 seconds
Started	Mar 10 12:55:22 PM PDT 24
Finished	Mar 10 12:55:23 PM PDT 24
Peak memory	195468 kb
Host	smart-37d0ea75-f580-4050-88b2-f98fee55864f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012978386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2012978386
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.1859842292
Short name	T765
Test name
Test status
Simulation time	320096538695 ps
CPU time	187.92 seconds
Started	Mar 10 12:55:11 PM PDT 24
Finished	Mar 10 12:58:20 PM PDT 24
Peak memory	199972 kb
Host	smart-216b254d-8c84-416d-ab37-ec2e59e85596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859842292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1859842292
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.335432937
Short name	T361
Test name
Test status
Simulation time	40545118717 ps
CPU time	16.65 seconds
Started	Mar 10 12:55:17 PM PDT 24
Finished	Mar 10 12:55:34 PM PDT 24
Peak memory	199344 kb
Host	smart-c4c091da-9546-4627-88e9-093d2e46b92b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335432937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.335432937
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.154130940
Short name	T261
Test name
Test status
Simulation time	66496341021 ps
CPU time	23.76 seconds
Started	Mar 10 12:55:17 PM PDT 24
Finished	Mar 10 12:55:41 PM PDT 24
Peak memory	200016 kb
Host	smart-300ecb80-ebe0-46f3-908a-7d07110b83ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154130940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.154130940
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.1492337513
Short name	T766
Test name
Test status
Simulation time	52421645914 ps
CPU time	22.5 seconds
Started	Mar 10 12:55:16 PM PDT 24
Finished	Mar 10 12:55:39 PM PDT 24
Peak memory	198404 kb
Host	smart-7da83c9c-4fbf-4758-a74d-646e8f2084cd
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492337513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1492337513
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.2825230324
Short name	T558
Test name
Test status
Simulation time	90614948263 ps
CPU time	272.61 seconds
Started	Mar 10 12:55:21 PM PDT 24
Finished	Mar 10 12:59:54 PM PDT 24
Peak memory	200052 kb
Host	smart-c13dbb51-d22c-466a-bd61-832fba0fd584
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2825230324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2825230324
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.2581305809
Short name	T571
Test name
Test status
Simulation time	6118234100 ps
CPU time	4.01 seconds
Started	Mar 10 12:55:17 PM PDT 24
Finished	Mar 10 12:55:21 PM PDT 24
Peak memory	197028 kb
Host	smart-d6096a4d-ff45-4576-a624-ce2a2e280a3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581305809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2581305809
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.3610058989
Short name	T163
Test name
Test status
Simulation time	8762598801 ps
CPU time	80.37 seconds
Started	Mar 10 12:55:23 PM PDT 24
Finished	Mar 10 12:56:43 PM PDT 24
Peak memory	200220 kb
Host	smart-3cc025d0-e050-4603-849d-5ec8f32ad6a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3610058989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3610058989
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.3098964171
Short name	T515
Test name
Test status
Simulation time	5210658661 ps
CPU time	7.35 seconds
Started	Mar 10 12:55:18 PM PDT 24
Finished	Mar 10 12:55:25 PM PDT 24
Peak memory	198988 kb
Host	smart-db568b09-8238-408b-98fc-00a33d7bcbf7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3098964171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3098964171
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.1637275459
Short name	T340
Test name
Test status
Simulation time	77198357227 ps
CPU time	36.08 seconds
Started	Mar 10 12:55:21 PM PDT 24
Finished	Mar 10 12:55:58 PM PDT 24
Peak memory	199648 kb
Host	smart-7dda9910-f5ea-4681-b837-c76e9847c1f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637275459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1637275459
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.2580061843
Short name	T451
Test name
Test status
Simulation time	3456402641 ps
CPU time	2.45 seconds
Started	Mar 10 12:55:23 PM PDT 24
Finished	Mar 10 12:55:26 PM PDT 24
Peak memory	195956 kb
Host	smart-ec95bbfe-7381-43ea-a10e-2e97774e527a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580061843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2580061843
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.2237892422
Short name	T971
Test name
Test status
Simulation time	120123146 ps
CPU time	0.8 seconds
Started	Mar 10 12:55:10 PM PDT 24
Finished	Mar 10 12:55:11 PM PDT 24
Peak memory	196880 kb
Host	smart-c3c5fb6a-8cda-4c65-8502-30f99c2034b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237892422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2237892422
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_stress_all_with_rand_reset.120395844
Short name	T378
Test name
Test status
Simulation time	18560250969 ps
CPU time	222.43 seconds
Started	Mar 10 12:55:22 PM PDT 24
Finished	Mar 10 12:59:05 PM PDT 24
Peak memory	208468 kb
Host	smart-0d1960fc-e7bd-4ef5-b398-e13323937a8a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120395844 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.120395844
Directory	/workspace/44.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.1353297960
Short name	T1065
Test name
Test status
Simulation time	2639575308 ps
CPU time	2.19 seconds
Started	Mar 10 12:55:23 PM PDT 24
Finished	Mar 10 12:55:26 PM PDT 24
Peak memory	198660 kb
Host	smart-239d8a22-b592-4d8e-bbea-0f95483fed8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353297960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1353297960
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.4099240507
Short name	T1097
Test name
Test status
Simulation time	85497389306 ps
CPU time	53.89 seconds
Started	Mar 10 12:55:11 PM PDT 24
Finished	Mar 10 12:56:06 PM PDT 24
Peak memory	200144 kb
Host	smart-7a267e5f-e438-4f3c-8419-aa8c76df56f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4099240507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4099240507
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.2901073348
Short name	T627
Test name
Test status
Simulation time	32947376 ps
CPU time	0.52 seconds
Started	Mar 10 12:55:31 PM PDT 24
Finished	Mar 10 12:55:32 PM PDT 24
Peak memory	195388 kb
Host	smart-bdb0f9d0-49dd-4d27-a47d-68647d7dd5c8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901073348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2901073348
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.1809329762
Short name	T213
Test name
Test status
Simulation time	125564936467 ps
CPU time	19.98 seconds
Started	Mar 10 12:55:26 PM PDT 24
Finished	Mar 10 12:55:47 PM PDT 24
Peak memory	200156 kb
Host	smart-9b9cbbb4-c440-45fe-9a57-6e8d0d3fc3c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809329762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1809329762
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.1160357193
Short name	T551
Test name
Test status
Simulation time	30080446966 ps
CPU time	11.6 seconds
Started	Mar 10 12:55:22 PM PDT 24
Finished	Mar 10 12:55:33 PM PDT 24
Peak memory	198132 kb
Host	smart-b4019190-e170-4e81-83b9-9428031f93f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160357193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1160357193
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_intr.3282275200
Short name	T670
Test name
Test status
Simulation time	31727023334 ps
CPU time	7.38 seconds
Started	Mar 10 12:55:26 PM PDT 24
Finished	Mar 10 12:55:34 PM PDT 24
Peak memory	198404 kb
Host	smart-11c98acb-f451-45c2-83cf-a525bf7fe373
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282275200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3282275200
Directory	/workspace/45.uart_intr/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.1779410032
Short name	T773
Test name
Test status
Simulation time	150392949568 ps
CPU time	402.99 seconds
Started	Mar 10 12:55:33 PM PDT 24
Finished	Mar 10 01:02:16 PM PDT 24
Peak memory	200088 kb
Host	smart-fbcd676d-8970-4695-ab04-f734f9c5534c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1779410032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1779410032
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.1178680101
Short name	T668
Test name
Test status
Simulation time	10840232812 ps
CPU time	20.25 seconds
Started	Mar 10 12:55:27 PM PDT 24
Finished	Mar 10 12:55:48 PM PDT 24
Peak memory	198260 kb
Host	smart-d2b52b72-2faf-466d-a0fc-04259b51080a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178680101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1178680101
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.2816509285
Short name	T478
Test name
Test status
Simulation time	24263462860 ps
CPU time	38.22 seconds
Started	Mar 10 12:55:28 PM PDT 24
Finished	Mar 10 12:56:06 PM PDT 24
Peak memory	198172 kb
Host	smart-a32ada62-d785-43a5-b69d-b73c1b29e24c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816509285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2816509285
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.1501524908
Short name	T1028
Test name
Test status
Simulation time	20548558159 ps
CPU time	502.58 seconds
Started	Mar 10 12:55:31 PM PDT 24
Finished	Mar 10 01:03:54 PM PDT 24
Peak memory	200092 kb
Host	smart-ed513842-7472-489f-86a6-76757161cc98
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1501524908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1501524908
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_oversample.161813871
Short name	T504
Test name
Test status
Simulation time	3467714479 ps
CPU time	23.34 seconds
Started	Mar 10 12:55:28 PM PDT 24
Finished	Mar 10 12:55:52 PM PDT 24
Peak memory	198076 kb
Host	smart-53c6041f-d874-4c98-abd6-c3f274ded18a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=161813871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.161813871
Directory	/workspace/45.uart_rx_oversample/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.185577086
Short name	T1092
Test name
Test status
Simulation time	55005300073 ps
CPU time	94.6 seconds
Started	Mar 10 12:55:28 PM PDT 24
Finished	Mar 10 12:57:04 PM PDT 24
Peak memory	200048 kb
Host	smart-cefa9def-42f4-45f0-a70c-81a89b4ad32d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185577086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.185577086
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.3417792192
Short name	T639
Test name
Test status
Simulation time	4863281516 ps
CPU time	1.44 seconds
Started	Mar 10 12:55:25 PM PDT 24
Finished	Mar 10 12:55:27 PM PDT 24
Peak memory	196048 kb
Host	smart-5047ee88-a1f0-4cce-b41c-ff145c22e573
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417792192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3417792192
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.3986165313
Short name	T543
Test name
Test status
Simulation time	666139362 ps
CPU time	1.29 seconds
Started	Mar 10 12:55:22 PM PDT 24
Finished	Mar 10 12:55:24 PM PDT 24
Peak memory	198308 kb
Host	smart-f4df16f7-2d42-4029-b87b-9389b6f2da0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986165313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3986165313
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_stress_all.843013913
Short name	T112
Test name
Test status
Simulation time	840274817964 ps
CPU time	91.42 seconds
Started	Mar 10 12:55:33 PM PDT 24
Finished	Mar 10 12:57:05 PM PDT 24
Peak memory	215752 kb
Host	smart-23778b86-a89b-46b9-b47c-83e2234457ff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843013913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.843013913
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.2181347757
Short name	T413
Test name
Test status
Simulation time	2089165587 ps
CPU time	2.01 seconds
Started	Mar 10 12:55:28 PM PDT 24
Finished	Mar 10 12:55:31 PM PDT 24
Peak memory	199476 kb
Host	smart-ad0d51d7-1b5e-4da4-afba-5ecdd9b6399f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181347757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2181347757
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.1021933592
Short name	T920
Test name
Test status
Simulation time	58766674802 ps
CPU time	83.92 seconds
Started	Mar 10 12:55:23 PM PDT 24
Finished	Mar 10 12:56:47 PM PDT 24
Peak memory	200152 kb
Host	smart-57810efa-44cd-40b3-b3c3-2c5ebc976773
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021933592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1021933592
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.1594896134
Short name	T1014
Test name
Test status
Simulation time	35581298 ps
CPU time	0.58 seconds
Started	Mar 10 12:55:43 PM PDT 24
Finished	Mar 10 12:55:46 PM PDT 24
Peak memory	195428 kb
Host	smart-c017e6fc-1310-4dff-b096-bbe45bd53d62
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594896134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1594896134
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.2526584162
Short name	T637
Test name
Test status
Simulation time	203947661657 ps
CPU time	90.98 seconds
Started	Mar 10 12:55:32 PM PDT 24
Finished	Mar 10 12:57:03 PM PDT 24
Peak memory	200100 kb
Host	smart-d0942f0a-d601-47bd-8d7e-d1e7584c82f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2526584162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2526584162
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.1025403829
Short name	T1101
Test name
Test status
Simulation time	69024403984 ps
CPU time	116.49 seconds
Started	Mar 10 12:55:33 PM PDT 24
Finished	Mar 10 12:57:30 PM PDT 24
Peak memory	199868 kb
Host	smart-6b8785f1-618f-4364-8468-f96d4f020ef2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1025403829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1025403829
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.4093611020
Short name	T860
Test name
Test status
Simulation time	9706469706 ps
CPU time	15.16 seconds
Started	Mar 10 12:55:32 PM PDT 24
Finished	Mar 10 12:55:47 PM PDT 24
Peak memory	199584 kb
Host	smart-ac885553-3a43-431c-b414-e9b75e3a6d8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093611020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4093611020
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/default/46.uart_intr.2171900981
Short name	T427
Test name
Test status
Simulation time	112019271608 ps
CPU time	227.08 seconds
Started	Mar 10 12:55:37 PM PDT 24
Finished	Mar 10 12:59:24 PM PDT 24
Peak memory	200032 kb
Host	smart-8fbcf10c-9ceb-4a1f-86bc-d9fc2a8663a7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171900981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2171900981
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.3004905604
Short name	T707
Test name
Test status
Simulation time	104663665315 ps
CPU time	593.63 seconds
Started	Mar 10 12:55:43 PM PDT 24
Finished	Mar 10 01:05:39 PM PDT 24
Peak memory	200192 kb
Host	smart-b25749c0-152d-4633-b5b7-6912d67d847b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3004905604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3004905604
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.3972752114
Short name	T460
Test name
Test status
Simulation time	8648748077 ps
CPU time	6.31 seconds
Started	Mar 10 12:55:38 PM PDT 24
Finished	Mar 10 12:55:45 PM PDT 24
Peak memory	198404 kb
Host	smart-20995aae-116b-4b87-97fb-7a830ec0cc2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972752114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3972752114
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.2398821087
Short name	T132
Test name
Test status
Simulation time	8557005863 ps
CPU time	15.52 seconds
Started	Mar 10 12:55:40 PM PDT 24
Finished	Mar 10 12:55:56 PM PDT 24
Peak memory	194804 kb
Host	smart-8f305c47-27a0-47e1-a7fd-1b8a3537a1eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2398821087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2398821087
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.3391747635
Short name	T853
Test name
Test status
Simulation time	15801601005 ps
CPU time	172.41 seconds
Started	Mar 10 12:55:39 PM PDT 24
Finished	Mar 10 12:58:32 PM PDT 24
Peak memory	200128 kb
Host	smart-a754f1cc-d0b4-469d-95dd-4be0f7c4527c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3391747635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3391747635
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.2009494757
Short name	T982
Test name
Test status
Simulation time	3786356093 ps
CPU time	15.66 seconds
Started	Mar 10 12:55:38 PM PDT 24
Finished	Mar 10 12:55:54 PM PDT 24
Peak memory	198088 kb
Host	smart-9e2e781b-3e81-4a2c-a356-862041b064ef
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2009494757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2009494757
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.1623143435
Short name	T317
Test name
Test status
Simulation time	232956961384 ps
CPU time	96.92 seconds
Started	Mar 10 12:55:39 PM PDT 24
Finished	Mar 10 12:57:17 PM PDT 24
Peak memory	199336 kb
Host	smart-fc2c4b39-6a32-4ddf-af7f-7297d8e7df06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623143435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1623143435
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.774427273
Short name	T968
Test name
Test status
Simulation time	479116982 ps
CPU time	1.36 seconds
Started	Mar 10 12:55:38 PM PDT 24
Finished	Mar 10 12:55:40 PM PDT 24
Peak memory	195436 kb
Host	smart-6aef113b-a328-4d0c-b69d-afcd8f915f1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=774427273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.774427273
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.698193021
Short name	T799
Test name
Test status
Simulation time	309440714 ps
CPU time	1.63 seconds
Started	Mar 10 12:55:32 PM PDT 24
Finished	Mar 10 12:55:34 PM PDT 24
Peak memory	198296 kb
Host	smart-ecbb48e7-2742-475e-ad79-ec08d9468162
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698193021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.698193021
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.3230713919
Short name	T425
Test name
Test status
Simulation time	345566640004 ps
CPU time	603.39 seconds
Started	Mar 10 12:55:45 PM PDT 24
Finished	Mar 10 01:05:49 PM PDT 24
Peak memory	216288 kb
Host	smart-b20c140e-a4c8-4d4d-abb6-494069cf7a8b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230713919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3230713919
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.1912298806
Short name	T914
Test name
Test status
Simulation time	611831059 ps
CPU time	1.35 seconds
Started	Mar 10 12:55:40 PM PDT 24
Finished	Mar 10 12:55:41 PM PDT 24
Peak memory	198076 kb
Host	smart-90c47220-660a-4985-911b-3efd033684ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912298806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1912298806
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.695111971
Short name	T138
Test name
Test status
Simulation time	152434241672 ps
CPU time	110.4 seconds
Started	Mar 10 12:55:33 PM PDT 24
Finished	Mar 10 12:57:23 PM PDT 24
Peak memory	200156 kb
Host	smart-3d5617d5-9265-4bbc-b957-2b58b39646b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695111971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.695111971
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.2541626708
Short name	T2
Test name
Test status
Simulation time	68433107 ps
CPU time	0.55 seconds
Started	Mar 10 12:55:48 PM PDT 24
Finished	Mar 10 12:55:50 PM PDT 24
Peak memory	194428 kb
Host	smart-4481bd94-2567-4474-8918-c5ba433a2190
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541626708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2541626708
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.1086466069
Short name	T474
Test name
Test status
Simulation time	57180079156 ps
CPU time	44.15 seconds
Started	Mar 10 12:55:43 PM PDT 24
Finished	Mar 10 12:56:30 PM PDT 24
Peak memory	200108 kb
Host	smart-b2d447e7-3961-427b-8092-07dbea7da1c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086466069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1086466069
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.3278760651
Short name	T587
Test name
Test status
Simulation time	33883028223 ps
CPU time	14.83 seconds
Started	Mar 10 12:55:43 PM PDT 24
Finished	Mar 10 12:56:00 PM PDT 24
Peak memory	197876 kb
Host	smart-d631bf08-2d3b-4c06-bd82-853298bc63b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278760651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3278760651
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.1530433347
Short name	T996
Test name
Test status
Simulation time	133286047348 ps
CPU time	56.68 seconds
Started	Mar 10 12:55:43 PM PDT 24
Finished	Mar 10 12:56:42 PM PDT 24
Peak memory	200084 kb
Host	smart-819b9d08-4bc3-4c1f-9022-e229b2aa0186
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530433347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1530433347
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/47.uart_intr.3596066151
Short name	T936
Test name
Test status
Simulation time	41036100826 ps
CPU time	19.56 seconds
Started	Mar 10 12:55:44 PM PDT 24
Finished	Mar 10 12:56:05 PM PDT 24
Peak memory	199608 kb
Host	smart-6d0ffe2f-805b-4c73-9528-e2a311ef8f55
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596066151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3596066151
Directory	/workspace/47.uart_intr/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.1140543021
Short name	T958
Test name
Test status
Simulation time	159588962499 ps
CPU time	697.2 seconds
Started	Mar 10 12:55:52 PM PDT 24
Finished	Mar 10 01:07:30 PM PDT 24
Peak memory	200148 kb
Host	smart-677782f0-68a6-4519-9391-f9ae0f69717e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1140543021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1140543021
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_loopback.710289809
Short name	T726
Test name
Test status
Simulation time	6343109887 ps
CPU time	5.6 seconds
Started	Mar 10 12:55:52 PM PDT 24
Finished	Mar 10 12:55:58 PM PDT 24
Peak memory	199216 kb
Host	smart-1a4e7454-85d6-4d8f-977d-55c5ea6ad503
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710289809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.710289809
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.2778337789
Short name	T896
Test name
Test status
Simulation time	57567963764 ps
CPU time	113.31 seconds
Started	Mar 10 12:55:51 PM PDT 24
Finished	Mar 10 12:57:45 PM PDT 24
Peak memory	198692 kb
Host	smart-97258db8-7819-48b6-9212-2ec631b69c24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2778337789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2778337789
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.2685222629
Short name	T194
Test name
Test status
Simulation time	17166042955 ps
CPU time	886.61 seconds
Started	Mar 10 12:55:48 PM PDT 24
Finished	Mar 10 01:10:36 PM PDT 24
Peak memory	200064 kb
Host	smart-76568e0b-208a-4382-a2c5-3e428725616c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2685222629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2685222629
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.3048862690
Short name	T535
Test name
Test status
Simulation time	4375500623 ps
CPU time	8.2 seconds
Started	Mar 10 12:55:43 PM PDT 24
Finished	Mar 10 12:55:54 PM PDT 24
Peak memory	198940 kb
Host	smart-8c9a42a5-1d6a-4c90-9076-85d9f93dd64f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3048862690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3048862690
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.708224820
Short name	T48
Test name
Test status
Simulation time	2913610404 ps
CPU time	3.71 seconds
Started	Mar 10 12:55:50 PM PDT 24
Finished	Mar 10 12:55:54 PM PDT 24
Peak memory	195596 kb
Host	smart-05aba39c-f98a-4fc6-beef-dbf63d6f9359
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=708224820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.708224820
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.2942037736
Short name	T1105
Test name
Test status
Simulation time	936251845 ps
CPU time	2 seconds
Started	Mar 10 12:55:42 PM PDT 24
Finished	Mar 10 12:55:46 PM PDT 24
Peak memory	200032 kb
Host	smart-26b02f1e-685c-4a55-bf55-2d1455231fc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942037736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2942037736
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.887409734
Short name	T514
Test name
Test status
Simulation time	201654012579 ps
CPU time	443.28 seconds
Started	Mar 10 12:55:49 PM PDT 24
Finished	Mar 10 01:03:13 PM PDT 24
Peak memory	208300 kb
Host	smart-66651990-0506-44af-86c8-1c5cae1bb848
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887409734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.887409734
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.1002539069
Short name	T934
Test name
Test status
Simulation time	6957191413 ps
CPU time	25.95 seconds
Started	Mar 10 12:55:50 PM PDT 24
Finished	Mar 10 12:56:16 PM PDT 24
Peak memory	200132 kb
Host	smart-cc4e7958-621c-42b0-80ec-8b03813fc6ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002539069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1002539069
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.952368495
Short name	T954
Test name
Test status
Simulation time	231535126292 ps
CPU time	58.24 seconds
Started	Mar 10 12:55:42 PM PDT 24
Finished	Mar 10 12:56:42 PM PDT 24
Peak memory	200112 kb
Host	smart-af97de8b-af18-4fbf-9e13-c0f64c097283
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952368495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.952368495
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.2318211648
Short name	T798
Test name
Test status
Simulation time	17786095 ps
CPU time	0.54 seconds
Started	Mar 10 12:56:01 PM PDT 24
Finished	Mar 10 12:56:02 PM PDT 24
Peak memory	195436 kb
Host	smart-9e7fb91d-3947-478f-8e06-ad59694fdb76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318211648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2318211648
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.78198549
Short name	T1090
Test name
Test status
Simulation time	40768372536 ps
CPU time	60.88 seconds
Started	Mar 10 12:55:58 PM PDT 24
Finished	Mar 10 12:56:58 PM PDT 24
Peak memory	200164 kb
Host	smart-b1680c2b-ed4d-45a5-b965-14cb6f562380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78198549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.78198549
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.1851695020
Short name	T972
Test name
Test status
Simulation time	35854923880 ps
CPU time	59.42 seconds
Started	Mar 10 12:55:55 PM PDT 24
Finished	Mar 10 12:56:55 PM PDT 24
Peak memory	199060 kb
Host	smart-4ed2a79a-16f9-4adf-90b8-2d5fb11137a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851695020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1851695020
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.112428906
Short name	T745
Test name
Test status
Simulation time	123580071796 ps
CPU time	100.49 seconds
Started	Mar 10 12:55:56 PM PDT 24
Finished	Mar 10 12:57:37 PM PDT 24
Peak memory	200056 kb
Host	smart-400460cb-6119-43bd-a7ca-dd268522b206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112428906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.112428906
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_intr.3267455194
Short name	T840
Test name
Test status
Simulation time	493887603339 ps
CPU time	82.12 seconds
Started	Mar 10 12:55:55 PM PDT 24
Finished	Mar 10 12:57:17 PM PDT 24
Peak memory	198828 kb
Host	smart-354f1d98-d8a9-4267-b27d-8c339eea4ded
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267455194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3267455194
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.3338672376
Short name	T702
Test name
Test status
Simulation time	87002288911 ps
CPU time	420.49 seconds
Started	Mar 10 12:56:00 PM PDT 24
Finished	Mar 10 01:03:01 PM PDT 24
Peak memory	200084 kb
Host	smart-850cc634-15e9-4c5a-a5f8-f759f24d7612
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3338672376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3338672376
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.2484614923
Short name	T99
Test name
Test status
Simulation time	13365639251 ps
CPU time	16.6 seconds
Started	Mar 10 12:56:01 PM PDT 24
Finished	Mar 10 12:56:17 PM PDT 24
Peak memory	200108 kb
Host	smart-97ac7bc0-a90b-4c3f-89a0-98e421768598
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484614923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2484614923
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.3298404490
Short name	T128
Test name
Test status
Simulation time	36943971645 ps
CPU time	19.05 seconds
Started	Mar 10 12:55:56 PM PDT 24
Finished	Mar 10 12:56:15 PM PDT 24
Peak memory	198260 kb
Host	smart-7dab6156-075b-4ca9-9c40-8c7776de9d78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298404490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3298404490
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.729131564
Short name	T690
Test name
Test status
Simulation time	35677632893 ps
CPU time	1846.16 seconds
Started	Mar 10 12:55:59 PM PDT 24
Finished	Mar 10 01:26:46 PM PDT 24
Peak memory	200124 kb
Host	smart-74d011f3-a744-44e5-b2d3-cd98a1aafc54
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=729131564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.729131564
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_oversample.3376524906
Short name	T563
Test name
Test status
Simulation time	3375967562 ps
CPU time	12.51 seconds
Started	Mar 10 12:55:54 PM PDT 24
Finished	Mar 10 12:56:07 PM PDT 24
Peak memory	198740 kb
Host	smart-d1ae0a7b-716a-4e03-bb22-1e160b7ee915
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3376524906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3376524906
Directory	/workspace/48.uart_rx_oversample/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.342484846
Short name	T722
Test name
Test status
Simulation time	141001277436 ps
CPU time	50.59 seconds
Started	Mar 10 12:55:57 PM PDT 24
Finished	Mar 10 12:56:48 PM PDT 24
Peak memory	199696 kb
Host	smart-a2905d29-acd5-4a0e-a3e8-104c60e6fab8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342484846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.342484846
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.4077280615
Short name	T623
Test name
Test status
Simulation time	35497883189 ps
CPU time	25.47 seconds
Started	Mar 10 12:55:55 PM PDT 24
Finished	Mar 10 12:56:21 PM PDT 24
Peak memory	195892 kb
Host	smart-56fa2b98-37f7-4d4c-b05a-29e51fa89561
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077280615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.4077280615
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.3130498945
Short name	T719
Test name
Test status
Simulation time	6289006879 ps
CPU time	17.85 seconds
Started	Mar 10 12:55:54 PM PDT 24
Finished	Mar 10 12:56:12 PM PDT 24
Peak memory	199428 kb
Host	smart-2353bc61-c359-47ad-a9b0-73ec8355b272
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130498945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3130498945
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_stress_all.2007568667
Short name	T122
Test name
Test status
Simulation time	138395153187 ps
CPU time	348.06 seconds
Started	Mar 10 12:55:59 PM PDT 24
Finished	Mar 10 01:01:48 PM PDT 24
Peak memory	200088 kb
Host	smart-4a3d3e43-c022-4970-af7b-44e7b821ece8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007568667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2007568667
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/48.uart_stress_all_with_rand_reset.2590323407
Short name	T12
Test name
Test status
Simulation time	18977048144 ps
CPU time	190.87 seconds
Started	Mar 10 12:56:01 PM PDT 24
Finished	Mar 10 12:59:12 PM PDT 24
Peak memory	216604 kb
Host	smart-3ddee5d9-3a3d-4757-9ad3-b2e441e70bc1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590323407 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2590323407
Directory	/workspace/48.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.2737919230
Short name	T604
Test name
Test status
Simulation time	647031486 ps
CPU time	2.53 seconds
Started	Mar 10 12:55:57 PM PDT 24
Finished	Mar 10 12:56:00 PM PDT 24
Peak memory	198100 kb
Host	smart-a68eb934-6d6a-424d-8cfe-d6778722ccfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737919230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2737919230
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.2831390250
Short name	T549
Test name
Test status
Simulation time	8256407563 ps
CPU time	16.24 seconds
Started	Mar 10 12:55:54 PM PDT 24
Finished	Mar 10 12:56:10 PM PDT 24
Peak memory	200020 kb
Host	smart-a59c6876-0ff6-4cdf-8fbf-78b17bff425c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831390250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2831390250
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.1524703100
Short name	T630
Test name
Test status
Simulation time	13575321 ps
CPU time	0.56 seconds
Started	Mar 10 12:56:12 PM PDT 24
Finished	Mar 10 12:56:13 PM PDT 24
Peak memory	195356 kb
Host	smart-75ec9444-0941-496d-aa7a-b648e197a61f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524703100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1524703100
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.895395013
Short name	T998
Test name
Test status
Simulation time	106165705417 ps
CPU time	39.35 seconds
Started	Mar 10 12:56:03 PM PDT 24
Finished	Mar 10 12:56:43 PM PDT 24
Peak memory	200092 kb
Host	smart-a22a7d76-e61d-464e-a7d9-13083f92eb14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895395013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.895395013
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.1690251474
Short name	T349
Test name
Test status
Simulation time	59380290701 ps
CPU time	95.91 seconds
Started	Mar 10 12:56:02 PM PDT 24
Finished	Mar 10 12:57:38 PM PDT 24
Peak memory	200052 kb
Host	smart-ba1226b7-a467-4bf7-bd64-f9fd22b5863e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1690251474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1690251474
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.3688038190
Short name	T694
Test name
Test status
Simulation time	28067417793 ps
CPU time	18.85 seconds
Started	Mar 10 12:56:00 PM PDT 24
Finished	Mar 10 12:56:19 PM PDT 24
Peak memory	200048 kb
Host	smart-0da91417-a95b-4883-9bd3-1a89f7dd7aa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688038190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3688038190
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_intr.4251216701
Short name	T811
Test name
Test status
Simulation time	74911411641 ps
CPU time	20.68 seconds
Started	Mar 10 12:56:03 PM PDT 24
Finished	Mar 10 12:56:24 PM PDT 24
Peak memory	200012 kb
Host	smart-73a71929-8102-4493-97d4-a2e2f47dc0ef
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251216701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4251216701
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.1621253266
Short name	T833
Test name
Test status
Simulation time	95046689584 ps
CPU time	128.61 seconds
Started	Mar 10 12:56:11 PM PDT 24
Finished	Mar 10 12:58:20 PM PDT 24
Peak memory	200144 kb
Host	smart-36520192-da2d-4bf0-99af-025da1ae15b1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1621253266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1621253266
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/49.uart_loopback.896263570
Short name	T951
Test name
Test status
Simulation time	2937778889 ps
CPU time	2.75 seconds
Started	Mar 10 12:56:06 PM PDT 24
Finished	Mar 10 12:56:09 PM PDT 24
Peak memory	198324 kb
Host	smart-a4319ab3-5b92-4353-9125-7c32990b834a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896263570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.896263570
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.1319508047
Short name	T554
Test name
Test status
Simulation time	13369143753 ps
CPU time	5.47 seconds
Started	Mar 10 12:56:02 PM PDT 24
Finished	Mar 10 12:56:07 PM PDT 24
Peak memory	195728 kb
Host	smart-f8ab9ff0-4bec-4035-8d4e-a81a777bd6d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319508047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1319508047
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.1377320280
Short name	T983
Test name
Test status
Simulation time	33040388834 ps
CPU time	323.49 seconds
Started	Mar 10 12:56:11 PM PDT 24
Finished	Mar 10 01:01:34 PM PDT 24
Peak memory	200228 kb
Host	smart-ab3a68f1-8afd-479c-8f9d-829d8b3edd12
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1377320280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1377320280
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.2077819237
Short name	T756
Test name
Test status
Simulation time	1844907789 ps
CPU time	2.11 seconds
Started	Mar 10 12:56:00 PM PDT 24
Finished	Mar 10 12:56:02 PM PDT 24
Peak memory	198084 kb
Host	smart-2dbdaf68-f0c4-413c-a06d-298be77b522e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2077819237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2077819237
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.222907381
Short name	T742
Test name
Test status
Simulation time	116302966908 ps
CPU time	48.19 seconds
Started	Mar 10 12:56:08 PM PDT 24
Finished	Mar 10 12:56:56 PM PDT 24
Peak memory	199796 kb
Host	smart-185df057-7764-41cb-946f-6ef304569d01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=222907381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.222907381
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.2495968310
Short name	T395
Test name
Test status
Simulation time	61571170106 ps
CPU time	89.04 seconds
Started	Mar 10 12:56:05 PM PDT 24
Finished	Mar 10 12:57:34 PM PDT 24
Peak memory	195744 kb
Host	smart-4c8881e7-8c8d-4e7c-9173-1e5c218467a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495968310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2495968310
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.2749111576
Short name	T621
Test name
Test status
Simulation time	938540731 ps
CPU time	1.18 seconds
Started	Mar 10 12:56:03 PM PDT 24
Finished	Mar 10 12:56:05 PM PDT 24
Peak memory	199128 kb
Host	smart-e5d18648-4f16-438d-89a0-7981982d1475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749111576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2749111576
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.387887932
Short name	T424
Test name
Test status
Simulation time	1192674725 ps
CPU time	2.17 seconds
Started	Mar 10 12:56:08 PM PDT 24
Finished	Mar 10 12:56:10 PM PDT 24
Peak memory	198272 kb
Host	smart-dd00e332-c688-4002-8f18-0cd826d075d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387887932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.387887932
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.1582953010
Short name	T673
Test name
Test status
Simulation time	52245838418 ps
CPU time	79.21 seconds
Started	Mar 10 12:56:00 PM PDT 24
Finished	Mar 10 12:57:19 PM PDT 24
Peak memory	200120 kb
Host	smart-a5442664-5cde-4a04-93f2-edfdd60b7096
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582953010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1582953010
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.267290446
Short name	T1034
Test name
Test status
Simulation time	14630371 ps
CPU time	0.58 seconds
Started	Mar 10 12:49:07 PM PDT 24
Finished	Mar 10 12:49:08 PM PDT 24
Peak memory	195488 kb
Host	smart-0a4d7822-eec3-4242-886b-749b589c9288
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267290446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.267290446
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.2494631356
Short name	T123
Test name
Test status
Simulation time	118980625109 ps
CPU time	153.83 seconds
Started	Mar 10 12:49:01 PM PDT 24
Finished	Mar 10 12:51:35 PM PDT 24
Peak memory	200092 kb
Host	smart-4d1d8e30-73da-4447-a7fe-d3f36435d092
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494631356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2494631356
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.4221487662
Short name	T643
Test name
Test status
Simulation time	137826438650 ps
CPU time	233.62 seconds
Started	Mar 10 12:49:02 PM PDT 24
Finished	Mar 10 12:52:56 PM PDT 24
Peak memory	199720 kb
Host	smart-7d81c52d-085e-4f64-a908-b6a4763ab84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221487662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4221487662
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.2972746469
Short name	T559
Test name
Test status
Simulation time	110324052626 ps
CPU time	87.43 seconds
Started	Mar 10 12:49:02 PM PDT 24
Finished	Mar 10 12:50:30 PM PDT 24
Peak memory	200172 kb
Host	smart-87b072d8-aa7d-44e7-9924-44e108fcf2de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972746469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2972746469
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.915882754
Short name	T603
Test name
Test status
Simulation time	160121049402 ps
CPU time	615.58 seconds
Started	Mar 10 12:49:01 PM PDT 24
Finished	Mar 10 12:59:17 PM PDT 24
Peak memory	200016 kb
Host	smart-a1269bc7-3ff4-4916-9709-1b60cd6b9631
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=915882754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.915882754
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.2698977217
Short name	T1098
Test name
Test status
Simulation time	5727930824 ps
CPU time	4.79 seconds
Started	Mar 10 12:49:02 PM PDT 24
Finished	Mar 10 12:49:07 PM PDT 24
Peak memory	200064 kb
Host	smart-3c7832e1-d47a-4976-86a1-74f4f551123a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698977217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2698977217
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.1652125083
Short name	T918
Test name
Test status
Simulation time	20579723341 ps
CPU time	21.86 seconds
Started	Mar 10 12:49:01 PM PDT 24
Finished	Mar 10 12:49:23 PM PDT 24
Peak memory	198676 kb
Host	smart-4a746217-1cf5-4ede-a12b-d4d2128367f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652125083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1652125083
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.854502947
Short name	T611
Test name
Test status
Simulation time	11092776779 ps
CPU time	122.99 seconds
Started	Mar 10 12:49:03 PM PDT 24
Finished	Mar 10 12:51:07 PM PDT 24
Peak memory	200148 kb
Host	smart-cd94192a-51a8-44b2-a44c-09420da94769
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=854502947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.854502947
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.529594643
Short name	T436
Test name
Test status
Simulation time	3689525122 ps
CPU time	7.37 seconds
Started	Mar 10 12:49:03 PM PDT 24
Finished	Mar 10 12:49:10 PM PDT 24
Peak memory	198528 kb
Host	smart-faa4e6b9-1138-4397-9708-7f456e6bb558
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=529594643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.529594643
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.1678521505
Short name	T928
Test name
Test status
Simulation time	85712308388 ps
CPU time	34.69 seconds
Started	Mar 10 12:49:03 PM PDT 24
Finished	Mar 10 12:49:38 PM PDT 24
Peak memory	199192 kb
Host	smart-42d27cdd-a75f-4bc6-b94c-b7d5e5774bfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678521505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1678521505
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.1700134014
Short name	T1088
Test name
Test status
Simulation time	600429363 ps
CPU time	1.52 seconds
Started	Mar 10 12:49:01 PM PDT 24
Finished	Mar 10 12:49:02 PM PDT 24
Peak memory	195340 kb
Host	smart-e33c3343-cc26-49e6-bb53-400a2a18ae3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700134014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1700134014
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.1986230519
Short name	T786
Test name
Test status
Simulation time	5877425899 ps
CPU time	16.94 seconds
Started	Mar 10 12:48:55 PM PDT 24
Finished	Mar 10 12:49:12 PM PDT 24
Peak memory	198856 kb
Host	smart-8fe02b23-3db9-497d-8529-aee3c3a48a1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986230519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1986230519
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all.4211974071
Short name	T145
Test name
Test status
Simulation time	63430256862 ps
CPU time	57.97 seconds
Started	Mar 10 12:49:02 PM PDT 24
Finished	Mar 10 12:50:00 PM PDT 24
Peak memory	200060 kb
Host	smart-aefb3f19-a449-4c8f-88d4-1e480be6733a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211974071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4211974071
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.269520240
Short name	T986
Test name
Test status
Simulation time	1146556652 ps
CPU time	1.44 seconds
Started	Mar 10 12:49:03 PM PDT 24
Finished	Mar 10 12:49:05 PM PDT 24
Peak memory	198196 kb
Host	smart-2a0583a4-6d2b-4b66-9560-df7b111ca388
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269520240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.269520240
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.1249574105
Short name	T660
Test name
Test status
Simulation time	39180956160 ps
CPU time	45.31 seconds
Started	Mar 10 12:48:56 PM PDT 24
Finished	Mar 10 12:49:41 PM PDT 24
Peak memory	200016 kb
Host	smart-95faa034-49cb-4697-aaec-af2c6853ef16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249574105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1249574105
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.83837908
Short name	T239
Test name
Test status
Simulation time	137505093177 ps
CPU time	75.76 seconds
Started	Mar 10 12:56:12 PM PDT 24
Finished	Mar 10 12:57:28 PM PDT 24
Peak memory	199960 kb
Host	smart-b1635fb7-a5d6-49a7-9bec-b731775ee78d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83837908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.83837908
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.4227980258
Short name	T942
Test name
Test status
Simulation time	117894245032 ps
CPU time	109.09 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 12:58:21 PM PDT 24
Peak memory	200136 kb
Host	smart-381b0f44-3f10-44d2-9186-d82962305b94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4227980258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4227980258
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.4253593813
Short name	T407
Test name
Test status
Simulation time	120833094459 ps
CPU time	28.84 seconds
Started	Mar 10 12:56:17 PM PDT 24
Finished	Mar 10 12:56:45 PM PDT 24
Peak memory	200060 kb
Host	smart-2476abbb-ce5f-4c96-a35b-125bfa34df6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253593813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4253593813
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.3133597074
Short name	T131
Test name
Test status
Simulation time	201597030584 ps
CPU time	315.15 seconds
Started	Mar 10 12:56:17 PM PDT 24
Finished	Mar 10 01:01:32 PM PDT 24
Peak memory	199676 kb
Host	smart-10680c8e-735c-4a56-853c-07a62834d41a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133597074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3133597074
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.3452331553
Short name	T139
Test name
Test status
Simulation time	9791158736 ps
CPU time	15.94 seconds
Started	Mar 10 12:56:17 PM PDT 24
Finished	Mar 10 12:56:33 PM PDT 24
Peak memory	198944 kb
Host	smart-93522ca4-825e-41f8-81b0-d1340b43c99a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452331553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3452331553
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.3400390840
Short name	T140
Test name
Test status
Simulation time	178733975322 ps
CPU time	137.23 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 12:58:49 PM PDT 24
Peak memory	200076 kb
Host	smart-895a465b-ea85-45ac-bd35-466138ecb96e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400390840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3400390840
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/default/55.uart_stress_all_with_rand_reset.486205097
Short name	T377
Test name
Test status
Simulation time	33266949546 ps
CPU time	88.05 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 12:58:00 PM PDT 24
Peak memory	216352 kb
Host	smart-85d58e07-149b-4c01-8139-e44f5ccd9777
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486205097 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.486205097
Directory	/workspace/55.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.736177731
Short name	T248
Test name
Test status
Simulation time	20090596029 ps
CPU time	13.23 seconds
Started	Mar 10 12:56:17 PM PDT 24
Finished	Mar 10 12:56:30 PM PDT 24
Peak memory	199924 kb
Host	smart-8f458f3b-a0bd-4566-9fc1-cd2c3d528016
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736177731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.736177731
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.1380075214
Short name	T10
Test name
Test status
Simulation time	19799977816 ps
CPU time	16.85 seconds
Started	Mar 10 12:56:21 PM PDT 24
Finished	Mar 10 12:56:38 PM PDT 24
Peak memory	199080 kb
Host	smart-db3f1a7c-c96f-4fce-9618-065804300d2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380075214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1380075214
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_stress_all_with_rand_reset.3424424388
Short name	T47
Test name
Test status
Simulation time	82948115187 ps
CPU time	630.04 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 01:07:02 PM PDT 24
Peak memory	225032 kb
Host	smart-ad70ce46-62e8-48cf-a63e-4a2df92eb201
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424424388 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3424424388
Directory	/workspace/58.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.2953140403
Short name	T624
Test name
Test status
Simulation time	196646633029 ps
CPU time	181.25 seconds
Started	Mar 10 12:56:20 PM PDT 24
Finished	Mar 10 12:59:22 PM PDT 24
Peak memory	200132 kb
Host	smart-d27cbd79-d1c9-43e1-84ca-73f6dd655d5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2953140403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2953140403
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.2540702454
Short name	T748
Test name
Test status
Simulation time	12990321 ps
CPU time	0.52 seconds
Started	Mar 10 12:49:19 PM PDT 24
Finished	Mar 10 12:49:20 PM PDT 24
Peak memory	194508 kb
Host	smart-ec239f19-a36a-42c6-8b1c-90c0a6980999
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540702454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2540702454
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.3854985407
Short name	T741
Test name
Test status
Simulation time	27883052971 ps
CPU time	40.27 seconds
Started	Mar 10 12:49:06 PM PDT 24
Finished	Mar 10 12:49:46 PM PDT 24
Peak memory	200108 kb
Host	smart-b967c3af-63be-4708-acb2-05ed47ff707c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854985407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3854985407
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.3866998337
Short name	T240
Test name
Test status
Simulation time	223435016917 ps
CPU time	342.14 seconds
Started	Mar 10 12:49:07 PM PDT 24
Finished	Mar 10 12:54:50 PM PDT 24
Peak memory	199312 kb
Host	smart-a76a18a2-53e8-444d-83e0-db443326f2bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866998337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3866998337
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_fifo_reset.3228786521
Short name	T177
Test name
Test status
Simulation time	66856195926 ps
CPU time	17.12 seconds
Started	Mar 10 12:49:08 PM PDT 24
Finished	Mar 10 12:49:25 PM PDT 24
Peak memory	199588 kb
Host	smart-2b67b86d-fffc-449e-a258-53137acdbcbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228786521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3228786521
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_intr.4257621623
Short name	T426
Test name
Test status
Simulation time	71521522996 ps
CPU time	39.3 seconds
Started	Mar 10 12:49:14 PM PDT 24
Finished	Mar 10 12:49:53 PM PDT 24
Peak memory	199536 kb
Host	smart-cff9bdb2-a374-458e-b76a-ef71064f1790
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257621623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4257621623
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.2432832802
Short name	T490
Test name
Test status
Simulation time	66765272053 ps
CPU time	196.59 seconds
Started	Mar 10 12:49:18 PM PDT 24
Finished	Mar 10 12:52:35 PM PDT 24
Peak memory	200104 kb
Host	smart-61b56e30-1a9b-4fce-9049-e1816fac3e1d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2432832802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2432832802
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.1022708868
Short name	T686
Test name
Test status
Simulation time	7342230681 ps
CPU time	8.27 seconds
Started	Mar 10 12:49:13 PM PDT 24
Finished	Mar 10 12:49:21 PM PDT 24
Peak memory	198432 kb
Host	smart-48082be4-f55f-42dc-b049-292765bc04eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022708868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1022708868
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.1048708714
Short name	T1016
Test name
Test status
Simulation time	7971228916 ps
CPU time	16.11 seconds
Started	Mar 10 12:49:12 PM PDT 24
Finished	Mar 10 12:49:28 PM PDT 24
Peak memory	197280 kb
Host	smart-5e5e2730-2fb2-4852-8e6e-0f9102c23b79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048708714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1048708714
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.1299112721
Short name	T782
Test name
Test status
Simulation time	9674552653 ps
CPU time	508.17 seconds
Started	Mar 10 12:49:19 PM PDT 24
Finished	Mar 10 12:57:47 PM PDT 24
Peak memory	200156 kb
Host	smart-34ede5e9-d7d2-4648-b553-6bed8d0d24ed
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1299112721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1299112721
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.2441231174
Short name	T685
Test name
Test status
Simulation time	5661359676 ps
CPU time	21.08 seconds
Started	Mar 10 12:49:08 PM PDT 24
Finished	Mar 10 12:49:29 PM PDT 24
Peak memory	198864 kb
Host	smart-220a1e77-9b4f-4411-8c01-99f6aa1643c4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2441231174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2441231174
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.2116732471
Short name	T638
Test name
Test status
Simulation time	177500920205 ps
CPU time	71.54 seconds
Started	Mar 10 12:49:12 PM PDT 24
Finished	Mar 10 12:50:24 PM PDT 24
Peak memory	199984 kb
Host	smart-c213af83-2dc3-4f78-82ad-84f2401dc0d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116732471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2116732471
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.4106738662
Short name	T877
Test name
Test status
Simulation time	2689840468 ps
CPU time	1.82 seconds
Started	Mar 10 12:49:13 PM PDT 24
Finished	Mar 10 12:49:15 PM PDT 24
Peak memory	195576 kb
Host	smart-724a063e-4a9c-4741-a111-c6927c1cf96b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106738662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.4106738662
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.2830437049
Short name	T461
Test name
Test status
Simulation time	288833096 ps
CPU time	1.25 seconds
Started	Mar 10 12:49:06 PM PDT 24
Finished	Mar 10 12:49:07 PM PDT 24
Peak memory	197908 kb
Host	smart-7ae35153-a52c-4dd5-89d7-1d6a4576a582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830437049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2830437049
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.4239583373
Short name	T904
Test name
Test status
Simulation time	252694717486 ps
CPU time	246.75 seconds
Started	Mar 10 12:49:19 PM PDT 24
Finished	Mar 10 12:53:26 PM PDT 24
Peak memory	200084 kb
Host	smart-ee249437-7761-4566-97ef-7971abf4fde0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239583373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4239583373
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_stress_all_with_rand_reset.3174901356
Short name	T273
Test name
Test status
Simulation time	45180287601 ps
CPU time	387.2 seconds
Started	Mar 10 12:49:18 PM PDT 24
Finished	Mar 10 12:55:45 PM PDT 24
Peak memory	213912 kb
Host	smart-ba5858c0-49f5-4793-bf5e-ef6aa0ae20d3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174901356 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3174901356
Directory	/workspace/6.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.3466410998
Short name	T498
Test name
Test status
Simulation time	6627536644 ps
CPU time	10.81 seconds
Started	Mar 10 12:49:13 PM PDT 24
Finished	Mar 10 12:49:23 PM PDT 24
Peak memory	199072 kb
Host	smart-f779bd2d-c24e-4aa7-88eb-61972bc9c5b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466410998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3466410998
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.3278507838
Short name	T50
Test name
Test status
Simulation time	38961900589 ps
CPU time	14.8 seconds
Started	Mar 10 12:49:06 PM PDT 24
Finished	Mar 10 12:49:21 PM PDT 24
Peak memory	199888 kb
Host	smart-36458662-92ae-475b-922d-aff99ff866af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278507838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3278507838
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.1284683546
Short name	T179
Test name
Test status
Simulation time	109277133933 ps
CPU time	89.2 seconds
Started	Mar 10 12:56:21 PM PDT 24
Finished	Mar 10 12:57:50 PM PDT 24
Peak memory	200132 kb
Host	smart-d00c132b-4607-4d38-b315-fc6dfff8c599
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284683546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1284683546
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.4059564947
Short name	T238
Test name
Test status
Simulation time	171039733567 ps
CPU time	74.34 seconds
Started	Mar 10 12:56:23 PM PDT 24
Finished	Mar 10 12:57:38 PM PDT 24
Peak memory	200172 kb
Host	smart-2a6b3a12-fbd7-4466-a085-c892874c71e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059564947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4059564947
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/61.uart_stress_all_with_rand_reset.3177367227
Short name	T1024
Test name
Test status
Simulation time	208836816431 ps
CPU time	498.48 seconds
Started	Mar 10 01:00:30 PM PDT 24
Finished	Mar 10 01:08:48 PM PDT 24
Peak memory	215452 kb
Host	smart-2dcad77b-d3f9-4e45-9307-c3bc49d87a05
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177367227 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3177367227
Directory	/workspace/61.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/63.uart_fifo_reset.1794936742
Short name	T129
Test name
Test status
Simulation time	88826670470 ps
CPU time	79.27 seconds
Started	Mar 10 12:56:25 PM PDT 24
Finished	Mar 10 12:57:44 PM PDT 24
Peak memory	200080 kb
Host	smart-f5de48fb-9f87-4bc7-924a-386a79e143d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794936742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1794936742
Directory	/workspace/63.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.3379651044
Short name	T365
Test name
Test status
Simulation time	64200783584 ps
CPU time	52.06 seconds
Started	Mar 10 12:56:28 PM PDT 24
Finished	Mar 10 12:57:20 PM PDT 24
Peak memory	200092 kb
Host	smart-e67eff4e-ca44-4e00-8adc-5ab77ce40bf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379651044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3379651044
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.456855891
Short name	T822
Test name
Test status
Simulation time	15200046455 ps
CPU time	24.99 seconds
Started	Mar 10 01:00:31 PM PDT 24
Finished	Mar 10 01:00:56 PM PDT 24
Peak memory	199460 kb
Host	smart-8149815b-8704-4f14-94d1-26d0cd291587
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456855891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.456855891
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.3415446405
Short name	T1067
Test name
Test status
Simulation time	100733016672 ps
CPU time	42.95 seconds
Started	Mar 10 01:00:30 PM PDT 24
Finished	Mar 10 01:01:14 PM PDT 24
Peak memory	199548 kb
Host	smart-a8e794ba-9741-4166-832b-7c9be89ad759
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415446405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3415446405
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.4150876301
Short name	T290
Test name
Test status
Simulation time	30395518081 ps
CPU time	34.26 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 12:57:07 PM PDT 24
Peak memory	200092 kb
Host	smart-3d5e3eb5-bd27-438c-a70c-db8c48b92072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150876301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4150876301
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/68.uart_stress_all_with_rand_reset.3095583741
Short name	T211
Test name
Test status
Simulation time	25869991035 ps
CPU time	303.9 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 01:01:36 PM PDT 24
Peak memory	212992 kb
Host	smart-342bfe29-e9ca-4cc7-98a8-d53050a88f72
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095583741 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3095583741
Directory	/workspace/68.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.3973170966
Short name	T204
Test name
Test status
Simulation time	143972317950 ps
CPU time	221.77 seconds
Started	Mar 10 12:56:31 PM PDT 24
Finished	Mar 10 01:00:13 PM PDT 24
Peak memory	200096 kb
Host	smart-b839ef21-4d85-43ee-84ce-3f60a65608fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973170966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3973170966
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.3399915362
Short name	T495
Test name
Test status
Simulation time	43321972 ps
CPU time	0.54 seconds
Started	Mar 10 12:49:30 PM PDT 24
Finished	Mar 10 12:49:32 PM PDT 24
Peak memory	195468 kb
Host	smart-40c8033a-98f8-4825-afab-31bb94818838
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399915362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3399915362
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.840220896
Short name	T956
Test name
Test status
Simulation time	109111082611 ps
CPU time	40.5 seconds
Started	Mar 10 12:49:18 PM PDT 24
Finished	Mar 10 12:49:59 PM PDT 24
Peak memory	200048 kb
Host	smart-d55261cb-dc67-40d8-aabf-25935b73bee1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840220896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.840220896
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.2117190567
Short name	T943
Test name
Test status
Simulation time	70826350870 ps
CPU time	27.61 seconds
Started	Mar 10 12:49:19 PM PDT 24
Finished	Mar 10 12:49:47 PM PDT 24
Peak memory	198648 kb
Host	smart-cf34500a-b191-4018-bb64-7ba27f65b0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117190567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2117190567
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_intr.118828206
Short name	T516
Test name
Test status
Simulation time	557591267491 ps
CPU time	127.64 seconds
Started	Mar 10 12:49:24 PM PDT 24
Finished	Mar 10 12:51:32 PM PDT 24
Peak memory	199368 kb
Host	smart-4c68a98e-abcf-43d6-b9ba-b962dab8bb59
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118828206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.118828206
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.629458628
Short name	T403
Test name
Test status
Simulation time	138315877698 ps
CPU time	465.09 seconds
Started	Mar 10 12:49:31 PM PDT 24
Finished	Mar 10 12:57:17 PM PDT 24
Peak memory	200188 kb
Host	smart-62f9b296-366e-4ce9-bf84-9049ba2e9e6d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=629458628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.629458628
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.1303305326
Short name	T601
Test name
Test status
Simulation time	152019954843 ps
CPU time	23.9 seconds
Started	Mar 10 12:49:24 PM PDT 24
Finished	Mar 10 12:49:48 PM PDT 24
Peak memory	200260 kb
Host	smart-c860600a-c207-494a-b654-d3e49bb14fbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303305326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1303305326
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.2979487965
Short name	T763
Test name
Test status
Simulation time	21476690017 ps
CPU time	299.18 seconds
Started	Mar 10 12:49:29 PM PDT 24
Finished	Mar 10 12:54:30 PM PDT 24
Peak memory	200128 kb
Host	smart-be7dd0eb-78e7-44ca-b158-15ee9dee55de
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2979487965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2979487965
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_oversample.4248141333
Short name	T553
Test name
Test status
Simulation time	3626167962 ps
CPU time	9.48 seconds
Started	Mar 10 12:49:24 PM PDT 24
Finished	Mar 10 12:49:34 PM PDT 24
Peak memory	198280 kb
Host	smart-946df537-7c21-458f-b73f-b0eb073a6d80
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4248141333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.4248141333
Directory	/workspace/7.uart_rx_oversample/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.51731171
Short name	T313
Test name
Test status
Simulation time	10491675677 ps
CPU time	15.25 seconds
Started	Mar 10 12:49:24 PM PDT 24
Finished	Mar 10 12:49:39 PM PDT 24
Peak memory	199596 kb
Host	smart-12f2ca0b-64cd-4a82-9c3c-8ac983110839
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51731171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.51731171
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.2549475344
Short name	T570
Test name
Test status
Simulation time	5738023304 ps
CPU time	2.52 seconds
Started	Mar 10 12:49:24 PM PDT 24
Finished	Mar 10 12:49:27 PM PDT 24
Peak memory	195908 kb
Host	smart-d86243dd-60e9-4f24-80cb-85793aa9e1b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549475344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2549475344
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.2306300448
Short name	T398
Test name
Test status
Simulation time	263210509 ps
CPU time	1.77 seconds
Started	Mar 10 12:49:18 PM PDT 24
Finished	Mar 10 12:49:21 PM PDT 24
Peak memory	198932 kb
Host	smart-0d5f7f25-3b43-453b-9d08-3a87fb95c8ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2306300448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2306300448
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.2519242343
Short name	T944
Test name
Test status
Simulation time	873559385 ps
CPU time	1.54 seconds
Started	Mar 10 12:49:23 PM PDT 24
Finished	Mar 10 12:49:25 PM PDT 24
Peak memory	198968 kb
Host	smart-978015fa-eb1e-464d-b8a3-99f76f07d7d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519242343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2519242343
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.1660774874
Short name	T675
Test name
Test status
Simulation time	68180034393 ps
CPU time	35.59 seconds
Started	Mar 10 12:49:18 PM PDT 24
Finished	Mar 10 12:49:54 PM PDT 24
Peak memory	199960 kb
Host	smart-62b0953e-fb9e-4280-b4f1-0b74ea25f1cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660774874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1660774874
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.872343678
Short name	T324
Test name
Test status
Simulation time	9995773411 ps
CPU time	17.47 seconds
Started	Mar 10 12:56:32 PM PDT 24
Finished	Mar 10 12:56:50 PM PDT 24
Peak memory	199872 kb
Host	smart-08608f81-fdc6-4336-9892-8936f0376dd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872343678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.872343678
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.3450824910
Short name	T283
Test name
Test status
Simulation time	86708398541 ps
CPU time	40.35 seconds
Started	Mar 10 12:56:37 PM PDT 24
Finished	Mar 10 12:57:17 PM PDT 24
Peak memory	200132 kb
Host	smart-2e130884-f0bc-4a5e-83bf-33a3f1a512eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450824910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3450824910
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.3017943711
Short name	T705
Test name
Test status
Simulation time	9300651389 ps
CPU time	15.92 seconds
Started	Mar 10 12:56:37 PM PDT 24
Finished	Mar 10 12:56:53 PM PDT 24
Peak memory	200132 kb
Host	smart-d2db73ee-ff47-4797-b38b-784e3e0f87cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017943711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3017943711
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.2243253954
Short name	T216
Test name
Test status
Simulation time	50441486362 ps
CPU time	19.39 seconds
Started	Mar 10 12:56:36 PM PDT 24
Finished	Mar 10 12:56:56 PM PDT 24
Peak memory	199716 kb
Host	smart-0449e21a-26fb-4139-85c3-3da9adde3df1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243253954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2243253954
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.643575115
Short name	T1075
Test name
Test status
Simulation time	38474644931 ps
CPU time	28.94 seconds
Started	Mar 10 12:56:43 PM PDT 24
Finished	Mar 10 12:57:12 PM PDT 24
Peak memory	200124 kb
Host	smart-ec3b4122-e762-435e-97e1-ac875d3f9673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643575115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.643575115
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.4079806737
Short name	T308
Test name
Test status
Simulation time	152878729034 ps
CPU time	250.83 seconds
Started	Mar 10 12:56:41 PM PDT 24
Finished	Mar 10 01:00:53 PM PDT 24
Peak memory	200060 kb
Host	smart-ee469b27-2d8c-44e5-af8c-58793f5cf94e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079806737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4079806737
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.145307413
Short name	T834
Test name
Test status
Simulation time	35425690564 ps
CPU time	17.8 seconds
Started	Mar 10 12:56:42 PM PDT 24
Finished	Mar 10 12:57:01 PM PDT 24
Peak memory	199996 kb
Host	smart-d24777ac-cca6-46fb-82aa-7d009b63646f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145307413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.145307413
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.63867078
Short name	T155
Test name
Test status
Simulation time	40674395727 ps
CPU time	15.63 seconds
Started	Mar 10 12:56:41 PM PDT 24
Finished	Mar 10 12:56:57 PM PDT 24
Peak memory	199292 kb
Host	smart-424c0af9-862e-4aa2-a48f-4f452172910c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63867078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.63867078
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.2085314057
Short name	T126
Test name
Test status
Simulation time	11834516091 ps
CPU time	11.1 seconds
Started	Mar 10 12:56:42 PM PDT 24
Finished	Mar 10 12:56:54 PM PDT 24
Peak memory	200128 kb
Host	smart-7a9a5aad-7063-4e7e-8865-1faa4ccd3294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085314057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2085314057
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.514375068
Short name	T608
Test name
Test status
Simulation time	19666875 ps
CPU time	0.53 seconds
Started	Mar 10 12:49:39 PM PDT 24
Finished	Mar 10 12:49:40 PM PDT 24
Peak memory	195436 kb
Host	smart-918ccd16-380e-4a87-b31f-e3927f0cdcab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514375068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.514375068
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.2445998115
Short name	T1102
Test name
Test status
Simulation time	29908333378 ps
CPU time	15.58 seconds
Started	Mar 10 12:49:34 PM PDT 24
Finished	Mar 10 12:49:50 PM PDT 24
Peak memory	199860 kb
Host	smart-e909f253-ed05-43ad-bfd5-7d379752e5bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445998115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2445998115
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.3404195256
Short name	T388
Test name
Test status
Simulation time	307038078085 ps
CPU time	330.29 seconds
Started	Mar 10 12:49:35 PM PDT 24
Finished	Mar 10 12:55:06 PM PDT 24
Peak memory	200136 kb
Host	smart-eb93e2d9-d889-4544-b97e-34cd49ec909e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404195256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3404195256
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.3071964572
Short name	T940
Test name
Test status
Simulation time	6072013267 ps
CPU time	11.75 seconds
Started	Mar 10 12:49:35 PM PDT 24
Finished	Mar 10 12:49:47 PM PDT 24
Peak memory	200048 kb
Host	smart-2aa2aa29-5a76-4303-9cec-fe853376bac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071964572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3071964572
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.2570207055
Short name	T874
Test name
Test status
Simulation time	47301277745 ps
CPU time	42.97 seconds
Started	Mar 10 12:49:33 PM PDT 24
Finished	Mar 10 12:50:17 PM PDT 24
Peak memory	199272 kb
Host	smart-6f970136-d3a1-4319-a7ed-13cf679cb66c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570207055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2570207055
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.2014780126
Short name	T533
Test name
Test status
Simulation time	66533849974 ps
CPU time	250.86 seconds
Started	Mar 10 12:49:40 PM PDT 24
Finished	Mar 10 12:53:51 PM PDT 24
Peak memory	200100 kb
Host	smart-f5462668-aa74-445e-8510-2dd5896a48dd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2014780126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2014780126
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/8.uart_loopback.2816168805
Short name	T1095
Test name
Test status
Simulation time	1056780858 ps
CPU time	2.66 seconds
Started	Mar 10 12:49:39 PM PDT 24
Finished	Mar 10 12:49:41 PM PDT 24
Peak memory	197020 kb
Host	smart-3941a238-0b30-416e-a320-8ea6ad6826b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816168805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2816168805
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.1637914816
Short name	T842
Test name
Test status
Simulation time	239929789846 ps
CPU time	207.11 seconds
Started	Mar 10 12:49:33 PM PDT 24
Finished	Mar 10 12:53:01 PM PDT 24
Peak memory	200344 kb
Host	smart-b51d3f54-0286-4875-b1c8-ce13bc337136
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637914816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1637914816
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.1491820371
Short name	T835
Test name
Test status
Simulation time	15951232774 ps
CPU time	188.06 seconds
Started	Mar 10 12:49:40 PM PDT 24
Finished	Mar 10 12:52:48 PM PDT 24
Peak memory	200176 kb
Host	smart-f50a92a9-eac8-47ca-8f9b-9b7b4164f1ef
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1491820371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1491820371
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_oversample.554594347
Short name	T880
Test name
Test status
Simulation time	2454062784 ps
CPU time	3.39 seconds
Started	Mar 10 12:49:34 PM PDT 24
Finished	Mar 10 12:49:37 PM PDT 24
Peak memory	198476 kb
Host	smart-3232a457-1e83-4a95-9637-5181925942b7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=554594347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.554594347
Directory	/workspace/8.uart_rx_oversample/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.2370096467
Short name	T362
Test name
Test status
Simulation time	438739311584 ps
CPU time	47.74 seconds
Started	Mar 10 12:49:39 PM PDT 24
Finished	Mar 10 12:50:27 PM PDT 24
Peak memory	199456 kb
Host	smart-3a3ca50b-1f43-4277-afcf-ff42bdcdea66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370096467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2370096467
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.462388040
Short name	T502
Test name
Test status
Simulation time	2868834405 ps
CPU time	4.97 seconds
Started	Mar 10 12:49:35 PM PDT 24
Finished	Mar 10 12:49:40 PM PDT 24
Peak memory	195568 kb
Host	smart-cfe84040-1638-4633-929b-b8a5af3e7fcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462388040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.462388040
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.4090750556
Short name	T404
Test name
Test status
Simulation time	902235736 ps
CPU time	2.21 seconds
Started	Mar 10 12:49:33 PM PDT 24
Finished	Mar 10 12:49:36 PM PDT 24
Peak memory	198764 kb
Host	smart-8ca90436-1dde-4fde-9e14-acfe12928cac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090750556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4090750556
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all_with_rand_reset.691234982
Short name	T105
Test name
Test status
Simulation time	21174113427 ps
CPU time	183.65 seconds
Started	Mar 10 12:49:39 PM PDT 24
Finished	Mar 10 12:52:43 PM PDT 24
Peak memory	216544 kb
Host	smart-49b902eb-0322-4188-a968-38097aa02e60
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691234982 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.691234982
Directory	/workspace/8.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.3296111123
Short name	T448
Test name
Test status
Simulation time	502234183 ps
CPU time	1.8 seconds
Started	Mar 10 12:49:43 PM PDT 24
Finished	Mar 10 12:49:46 PM PDT 24
Peak memory	198048 kb
Host	smart-114bfa0e-3347-415b-9943-d4b85a577cdb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296111123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3296111123
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.2947237409
Short name	T812
Test name
Test status
Simulation time	42465173971 ps
CPU time	35.4 seconds
Started	Mar 10 12:49:34 PM PDT 24
Finished	Mar 10 12:50:10 PM PDT 24
Peak memory	200184 kb
Host	smart-527a9f2c-aaa5-4478-b3cd-b0706b9c18d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947237409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2947237409
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.926529271
Short name	T154
Test name
Test status
Simulation time	32519326240 ps
CPU time	21.97 seconds
Started	Mar 10 12:56:43 PM PDT 24
Finished	Mar 10 12:57:05 PM PDT 24
Peak memory	200156 kb
Host	smart-d5b6bc78-7a5a-469b-9006-0e267750cd8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926529271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.926529271
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/80.uart_stress_all_with_rand_reset.4049602686
Short name	T379
Test name
Test status
Simulation time	910874128044 ps
CPU time	649.6 seconds
Started	Mar 10 01:00:31 PM PDT 24
Finished	Mar 10 01:11:21 PM PDT 24
Peak memory	216256 kb
Host	smart-0581320d-d4fd-400c-9e5f-074a1801ef3b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049602686 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4049602686
Directory	/workspace/80.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.3666077910
Short name	T157
Test name
Test status
Simulation time	187449468565 ps
CPU time	402.66 seconds
Started	Mar 10 12:56:48 PM PDT 24
Finished	Mar 10 01:03:31 PM PDT 24
Peak memory	200140 kb
Host	smart-dcec5639-535e-4b76-8e1f-2505e77a25fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666077910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3666077910
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.356002803
Short name	T753
Test name
Test status
Simulation time	118196403743 ps
CPU time	15.66 seconds
Started	Mar 10 12:56:47 PM PDT 24
Finished	Mar 10 12:57:02 PM PDT 24
Peak memory	200076 kb
Host	smart-a7b8deaf-2abf-4c11-903a-8424de515498
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356002803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.356002803
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_stress_all_with_rand_reset.2823872972
Short name	T1001
Test name
Test status
Simulation time	128852019367 ps
CPU time	399.49 seconds
Started	Mar 10 12:56:46 PM PDT 24
Finished	Mar 10 01:03:26 PM PDT 24
Peak memory	216632 kb
Host	smart-ab8876a5-704e-46ef-967c-d2ee9d505f6d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823872972 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2823872972
Directory	/workspace/82.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.996699639
Short name	T9
Test name
Test status
Simulation time	21670961268 ps
CPU time	34.73 seconds
Started	Mar 10 12:56:47 PM PDT 24
Finished	Mar 10 12:57:22 PM PDT 24
Peak memory	200104 kb
Host	smart-a1b05943-4c5e-4ef9-8969-df8a9a0a05eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996699639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.996699639
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.2649821918
Short name	T102
Test name
Test status
Simulation time	25391111811 ps
CPU time	20.59 seconds
Started	Mar 10 12:56:47 PM PDT 24
Finished	Mar 10 12:57:08 PM PDT 24
Peak memory	199828 kb
Host	smart-02152e68-6e37-4027-90a0-a3f207724bda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2649821918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2649821918
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.3886833022
Short name	T327
Test name
Test status
Simulation time	92011177040 ps
CPU time	38.92 seconds
Started	Mar 10 12:56:51 PM PDT 24
Finished	Mar 10 12:57:30 PM PDT 24
Peak memory	199868 kb
Host	smart-b67093ad-1d05-4d7f-918b-cfdfd4add7bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886833022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3886833022
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.1118917303
Short name	T618
Test name
Test status
Simulation time	39696340778 ps
CPU time	70.73 seconds
Started	Mar 10 12:56:51 PM PDT 24
Finished	Mar 10 12:58:02 PM PDT 24
Peak memory	200144 kb
Host	smart-8846a095-7e33-4d13-b16e-668c83e2250a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118917303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1118917303
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_stress_all_with_rand_reset.1829300418
Short name	T37
Test name
Test status
Simulation time	55647331072 ps
CPU time	872.76 seconds
Started	Mar 10 12:56:53 PM PDT 24
Finished	Mar 10 01:11:27 PM PDT 24
Peak memory	225592 kb
Host	smart-df557264-ce03-4d54-aba6-1daeb68f0422
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829300418 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1829300418
Directory	/workspace/86.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.1385696390
Short name	T479
Test name
Test status
Simulation time	84337776648 ps
CPU time	25.85 seconds
Started	Mar 10 12:56:53 PM PDT 24
Finished	Mar 10 12:57:20 PM PDT 24
Peak memory	200024 kb
Host	smart-a111035a-4989-4fd0-8260-8117774852b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385696390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1385696390
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_stress_all_with_rand_reset.1081791753
Short name	T272
Test name
Test status
Simulation time	22198490532 ps
CPU time	622.59 seconds
Started	Mar 10 12:56:56 PM PDT 24
Finished	Mar 10 01:07:19 PM PDT 24
Peak memory	216508 kb
Host	smart-8f8c1888-99aa-4c43-8dbe-cc8f56e2856f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081791753 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1081791753
Directory	/workspace/87.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.1917784023
Short name	T266
Test name
Test status
Simulation time	115487315887 ps
CPU time	50.7 seconds
Started	Mar 10 12:56:57 PM PDT 24
Finished	Mar 10 12:57:48 PM PDT 24
Peak memory	200124 kb
Host	smart-58f4f79e-b639-403d-a0d7-6e7acfdcbd14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917784023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1917784023
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_stress_all_with_rand_reset.2112933915
Short name	T813
Test name
Test status
Simulation time	129141697967 ps
CPU time	144.6 seconds
Started	Mar 10 12:57:01 PM PDT 24
Finished	Mar 10 12:59:26 PM PDT 24
Peak memory	216812 kb
Host	smart-1951515b-ee82-42a1-a5e0-5fce0811ea14
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112933915 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2112933915
Directory	/workspace/89.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.2208231538
Short name	T710
Test name
Test status
Simulation time	30733312 ps
CPU time	0.58 seconds
Started	Mar 10 12:49:52 PM PDT 24
Finished	Mar 10 12:49:53 PM PDT 24
Peak memory	195448 kb
Host	smart-662a327b-0c8e-4fc4-b7d1-61b25ae0a849
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208231538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2208231538
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.933793766
Short name	T1000
Test name
Test status
Simulation time	40819303100 ps
CPU time	60.26 seconds
Started	Mar 10 12:49:44 PM PDT 24
Finished	Mar 10 12:50:44 PM PDT 24
Peak memory	200104 kb
Host	smart-653dac4f-12f7-46a5-9f3b-141b3b0c1ec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933793766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.933793766
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.1359835542
Short name	T1117
Test name
Test status
Simulation time	23585090178 ps
CPU time	38.91 seconds
Started	Mar 10 12:49:48 PM PDT 24
Finished	Mar 10 12:50:27 PM PDT 24
Peak memory	200048 kb
Host	smart-764a3bac-a9e4-4380-8906-6ff081249062
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359835542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1359835542
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.2982820409
Short name	T926
Test name
Test status
Simulation time	46942331252 ps
CPU time	23.11 seconds
Started	Mar 10 12:49:45 PM PDT 24
Finished	Mar 10 12:50:09 PM PDT 24
Peak memory	200080 kb
Host	smart-d5c49d68-ce79-4904-af3f-d6e5f56d39b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982820409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2982820409
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_intr.105049130
Short name	T633
Test name
Test status
Simulation time	19946633360 ps
CPU time	16.36 seconds
Started	Mar 10 12:49:45 PM PDT 24
Finished	Mar 10 12:50:02 PM PDT 24
Peak memory	196548 kb
Host	smart-92281b05-2d97-4cb2-92e4-114a83705e8f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105049130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.105049130
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.1999194695
Short name	T616
Test name
Test status
Simulation time	73162319321 ps
CPU time	100.49 seconds
Started	Mar 10 12:49:52 PM PDT 24
Finished	Mar 10 12:51:33 PM PDT 24
Peak memory	200024 kb
Host	smart-928ab256-563e-4621-9013-7442e189482f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1999194695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1999194695
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.1777895353
Short name	T537
Test name
Test status
Simulation time	5247663620 ps
CPU time	10.64 seconds
Started	Mar 10 12:49:45 PM PDT 24
Finished	Mar 10 12:49:56 PM PDT 24
Peak memory	198288 kb
Host	smart-6ad3ac11-66cd-400b-9abf-cc70017d1be9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777895353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1777895353
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.2355733736
Short name	T583
Test name
Test status
Simulation time	93232576007 ps
CPU time	29.04 seconds
Started	Mar 10 12:49:45 PM PDT 24
Finished	Mar 10 12:50:14 PM PDT 24
Peak memory	200336 kb
Host	smart-7fbadfc4-dec5-48c9-81b1-c4d8554c98f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355733736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2355733736
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.2859317555
Short name	T682
Test name
Test status
Simulation time	9496171477 ps
CPU time	270.78 seconds
Started	Mar 10 12:49:52 PM PDT 24
Finished	Mar 10 12:54:23 PM PDT 24
Peak memory	200128 kb
Host	smart-117185e3-6e4b-4605-95c2-bfd7df14647e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2859317555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2859317555
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_oversample.3596651280
Short name	T836
Test name
Test status
Simulation time	3243305391 ps
CPU time	28.19 seconds
Started	Mar 10 12:49:46 PM PDT 24
Finished	Mar 10 12:50:15 PM PDT 24
Peak memory	198080 kb
Host	smart-32595cbb-f0b7-487a-806f-bdfccba956d0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3596651280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3596651280
Directory	/workspace/9.uart_rx_oversample/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.890626579
Short name	T580
Test name
Test status
Simulation time	55606355215 ps
CPU time	26.71 seconds
Started	Mar 10 12:49:45 PM PDT 24
Finished	Mar 10 12:50:12 PM PDT 24
Peak memory	200100 kb
Host	smart-31b0a8fa-6a86-4599-819d-417def1cda0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890626579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.890626579
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.286777351
Short name	T939
Test name
Test status
Simulation time	3759340969 ps
CPU time	2.11 seconds
Started	Mar 10 12:49:46 PM PDT 24
Finished	Mar 10 12:49:48 PM PDT 24
Peak memory	195828 kb
Host	smart-2d222dae-16e6-4703-9268-257746293a45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286777351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.286777351
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.997434091
Short name	T416
Test name
Test status
Simulation time	554294789 ps
CPU time	1.55 seconds
Started	Mar 10 12:49:43 PM PDT 24
Finished	Mar 10 12:49:46 PM PDT 24
Peak memory	197932 kb
Host	smart-58953a33-09ba-43ef-98f7-69f16ad247ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997434091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.997434091
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all_with_rand_reset.2751003184
Short name	T381
Test name
Test status
Simulation time	794669370654 ps
CPU time	1379.12 seconds
Started	Mar 10 12:49:51 PM PDT 24
Finished	Mar 10 01:12:50 PM PDT 24
Peak memory	226268 kb
Host	smart-0a1fdc81-d87d-433f-833e-9f99bc303ef6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751003184 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2751003184
Directory	/workspace/9.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.3538692770
Short name	T491
Test name
Test status
Simulation time	8531038677 ps
CPU time	14.86 seconds
Started	Mar 10 12:49:44 PM PDT 24
Finished	Mar 10 12:49:59 PM PDT 24
Peak memory	199620 kb
Host	smart-06dcefcb-cf39-4ca4-8d3c-17d0b6f7a1a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538692770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3538692770
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.2765473412
Short name	T775
Test name
Test status
Simulation time	13707711774 ps
CPU time	13.19 seconds
Started	Mar 10 12:49:43 PM PDT 24
Finished	Mar 10 12:49:57 PM PDT 24
Peak memory	198876 kb
Host	smart-6e6539de-3115-4d33-a47e-8f261a8c4638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765473412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2765473412
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.1767615610
Short name	T230
Test name
Test status
Simulation time	90877899790 ps
CPU time	77.63 seconds
Started	Mar 10 12:57:01 PM PDT 24
Finished	Mar 10 12:58:19 PM PDT 24
Peak memory	200128 kb
Host	smart-74e4570c-6809-40eb-9f66-5107e58accaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767615610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1767615610
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.4001261102
Short name	T57
Test name
Test status
Simulation time	93028662132 ps
CPU time	392.63 seconds
Started	Mar 10 12:57:01 PM PDT 24
Finished	Mar 10 01:03:34 PM PDT 24
Peak memory	216664 kb
Host	smart-b82d4128-f426-446a-9068-f0d87271057d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001261102 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4001261102
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.4014886684
Short name	T1066
Test name
Test status
Simulation time	70445614298 ps
CPU time	37.37 seconds
Started	Mar 10 12:57:02 PM PDT 24
Finished	Mar 10 12:57:39 PM PDT 24
Peak memory	200064 kb
Host	smart-fb3b5cec-d5a7-4e3d-b851-1a04719f283c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014886684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.4014886684
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.629759523
Short name	T709
Test name
Test status
Simulation time	102611404009 ps
CPU time	38.9 seconds
Started	Mar 10 12:57:05 PM PDT 24
Finished	Mar 10 12:57:44 PM PDT 24
Peak memory	200020 kb
Host	smart-11fd190c-1c9f-47ae-aa2d-5f450e57d454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629759523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.629759523
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.2184150420
Short name	T289
Test name
Test status
Simulation time	84500151034 ps
CPU time	36.37 seconds
Started	Mar 10 12:57:07 PM PDT 24
Finished	Mar 10 12:57:44 PM PDT 24
Peak memory	199964 kb
Host	smart-48117855-8bad-443c-960c-2e33d8e56e63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184150420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2184150420
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.602145348
Short name	T816
Test name
Test status
Simulation time	105708843089 ps
CPU time	162.3 seconds
Started	Mar 10 12:57:08 PM PDT 24
Finished	Mar 10 12:59:51 PM PDT 24
Peak memory	200084 kb
Host	smart-9fe2f99c-6816-4a49-accb-563c89beccf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=602145348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.602145348
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_stress_all_with_rand_reset.727096934
Short name	T380
Test name
Test status
Simulation time	112173124578 ps
CPU time	548.63 seconds
Started	Mar 10 12:57:12 PM PDT 24
Finished	Mar 10 01:06:20 PM PDT 24
Peak memory	225008 kb
Host	smart-afb2ec26-bdf4-443b-981e-d59a1bc85f7b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727096934 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.727096934
Directory	/workspace/94.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.2478045941
Short name	T331
Test name
Test status
Simulation time	115298655430 ps
CPU time	32.22 seconds
Started	Mar 10 12:57:11 PM PDT 24
Finished	Mar 10 12:57:43 PM PDT 24
Peak memory	199736 kb
Host	smart-13ad680c-8c9b-4586-bf82-1f75630388b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478045941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2478045941
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.1315365466
Short name	T303
Test name
Test status
Simulation time	109183759696 ps
CPU time	74.94 seconds
Started	Mar 10 12:57:17 PM PDT 24
Finished	Mar 10 12:58:33 PM PDT 24
Peak memory	199716 kb
Host	smart-e4b51bc9-a951-459d-9d33-1aa05c869f17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315365466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1315365466
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.853204754
Short name	T268
Test name
Test status
Simulation time	125210980529 ps
CPU time	307.73 seconds
Started	Mar 10 12:57:16 PM PDT 24
Finished	Mar 10 01:02:24 PM PDT 24
Peak memory	200156 kb
Host	smart-f3c19c7d-a2d9-4c8d-8889-5ae8bddc21ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853204754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.853204754
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.47564318
Short name	T517
Test name
Test status
Simulation time	593461099157 ps
CPU time	110.86 seconds
Started	Mar 10 12:57:17 PM PDT 24
Finished	Mar 10 12:59:09 PM PDT 24
Peak memory	199984 kb
Host	smart-8737156e-559d-4371-81a7-3276ab5535e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47564318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.47564318
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_stress_all_with_rand_reset.4055854936
Short name	T910
Test name
Test status
Simulation time	189597668477 ps
CPU time	360.8 seconds
Started	Mar 10 12:57:24 PM PDT 24
Finished	Mar 10 01:03:25 PM PDT 24
Peak memory	216748 kb
Host	smart-84582d9f-46cb-447c-85c9-e88e0b3f7a34
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055854936 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.4055854936
Directory	/workspace/98.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.4264440878
Short name	T219
Test name
Test status
Simulation time	101143022856 ps
CPU time	43.73 seconds
Started	Mar 10 12:57:22 PM PDT 24
Finished	Mar 10 12:58:05 PM PDT 24
Peak memory	199892 kb
Host	smart-8f42b62b-3cc2-4e05-933d-3d90b439e0a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264440878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4264440878
Directory	/workspace/99.uart_fifo_reset/latest

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