Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55378266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23011043

1

T1

223

T2

227

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73951795	1			T1	418		T2	982		T3	9312
values[0x0]	2106446	1			T1	99		T2	237		T3	5
values[0x1]	2331068	1			T1	99		T2	243		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39144581	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39244728

1

T1

289

T2

521

T3

3085

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	301946	1			T3	81		T4	1		T6	54
valid_sources[0x01]	273947	1			T1	3		T3	25		T4	1
valid_sources[0x02]	301336	1			T3	41		T4	1		T6	27
valid_sources[0x03]	364959	1			T3	17		T6	28		T7	3947
valid_sources[0x04]	294496	1			T3	19		T4	2		T6	37
valid_sources[0x05]	283135	1			T3	37		T6	23		T7	4396
valid_sources[0x06]	358598	1			T1	3		T3	27		T4	2
valid_sources[0x07]	290841	1			T3	31		T6	32		T7	4232
valid_sources[0x08]	302105	1			T3	23		T4	1		T6	30
valid_sources[0x09]	310404	1			T3	33		T4	4		T6	28
valid_sources[0x0a]	300427	1			T1	3		T3	29		T4	2
valid_sources[0x0b]	311744	1			T3	32		T4	3		T6	25
valid_sources[0x0c]	282628	1			T3	42		T4	2		T6	23
valid_sources[0x0d]	277230	1			T3	17		T6	32		T7	3935
valid_sources[0x0e]	300069	1			T3	21		T4	8		T6	39
valid_sources[0x0f]	279155	1			T3	25		T6	45		T7	4138
valid_sources[0x10]	294080	1			T3	38		T4	1		T6	25
valid_sources[0x11]	324636	1			T3	88		T6	29		T7	4045
valid_sources[0x12]	315160	1			T3	43		T6	13		T7	4000
valid_sources[0x13]	291091	1			T1	5		T3	56		T4	6
valid_sources[0x14]	308255	1			T3	65		T6	26		T7	4093
valid_sources[0x15]	328850	1			T3	44		T4	1		T6	25
valid_sources[0x16]	296391	1			T3	63		T6	35		T7	4329
valid_sources[0x17]	333556	1			T3	32		T4	1		T6	33
valid_sources[0x18]	300388	1			T3	28		T4	2		T6	32
valid_sources[0x19]	276542	1			T1	7		T3	87		T6	16
valid_sources[0x1a]	278933	1			T3	37		T4	1		T6	38
valid_sources[0x1b]	300397	1			T3	40		T4	1		T6	22
valid_sources[0x1c]	357414	1			T3	48		T4	1		T6	40
valid_sources[0x1d]	303138	1			T1	9		T3	85		T6	45
valid_sources[0x1e]	286170	1			T3	32		T4	1		T6	29
valid_sources[0x1f]	295322	1			T1	4		T3	21		T5	45
valid_sources[0x20]	291293	1			T3	41		T4	1		T6	24
valid_sources[0x21]	275579	1			T3	41		T4	1		T6	49
valid_sources[0x22]	347058	1			T3	41		T6	34		T7	4352
valid_sources[0x23]	293095	1			T3	36		T4	2		T6	35
valid_sources[0x24]	283278	1			T3	24		T6	29		T7	4176
valid_sources[0x25]	289870	1			T3	35		T4	3		T6	41
valid_sources[0x26]	311180	1			T3	43		T6	39		T7	4232
valid_sources[0x27]	280541	1			T1	5		T3	28		T6	20
valid_sources[0x28]	291908	1			T3	34		T6	37		T7	4209
valid_sources[0x29]	290885	1			T1	4		T3	3		T4	5
valid_sources[0x2a]	285743	1			T1	2		T3	73		T4	1
valid_sources[0x2b]	289259	1			T3	32		T6	48		T7	4016
valid_sources[0x2c]	295604	1			T1	51		T3	41		T6	25
valid_sources[0x2d]	298875	1			T3	22		T6	28		T7	4123
valid_sources[0x2e]	300453	1			T1	3		T3	15		T4	1
valid_sources[0x2f]	331651	1			T3	93		T4	2		T6	43
valid_sources[0x30]	296169	1			T3	57		T6	40		T7	4171
valid_sources[0x31]	284457	1			T1	14		T3	52		T6	36
valid_sources[0x32]	329184	1			T3	56		T6	27		T7	4200
valid_sources[0x33]	304499	1			T3	24		T6	17		T7	4083
valid_sources[0x34]	296361	1			T3	37		T6	42		T7	4013
valid_sources[0x35]	293615	1			T1	1		T3	21		T6	31
valid_sources[0x36]	285052	1			T3	33		T4	1		T6	26
valid_sources[0x37]	296872	1			T3	14		T4	2		T6	47
valid_sources[0x38]	320359	1			T3	46		T4	6		T6	24
valid_sources[0x39]	306792	1			T3	42		T4	1		T6	31
valid_sources[0x3a]	281268	1			T3	58		T4	2		T6	43
valid_sources[0x3b]	313411	1			T3	64		T6	34		T7	4086
valid_sources[0x3c]	309145	1			T3	34		T4	1		T6	28
valid_sources[0x3d]	327217	1			T3	36		T4	3		T6	33
valid_sources[0x3e]	283879	1			T3	15		T6	27		T7	3964
valid_sources[0x3f]	372664	1			T3	24		T6	47		T7	4063
valid_sources[0x40]	279083	1			T3	15		T4	1		T6	22
valid_sources[0x41]	292994	1			T3	27		T4	1		T6	25
valid_sources[0x42]	397459	1			T3	31		T4	1		T6	40
valid_sources[0x43]	301925	1			T3	58		T6	43		T7	4287
valid_sources[0x44]	275951	1			T3	19		T6	39		T7	4121
valid_sources[0x45]	291443	1			T1	6		T3	51		T4	2
valid_sources[0x46]	295989	1			T3	39		T6	58		T7	4179
valid_sources[0x47]	302855	1			T3	35		T6	48		T7	4060
valid_sources[0x48]	273902	1			T1	33		T3	32		T6	27
valid_sources[0x49]	304003	1			T3	34		T4	3		T6	24
valid_sources[0x4a]	280234	1			T3	27		T6	43		T7	4173
valid_sources[0x4b]	315401	1			T1	11		T3	33		T4	4
valid_sources[0x4c]	326386	1			T3	24		T4	2		T6	39
valid_sources[0x4d]	509463	1			T3	49		T4	3		T6	40
valid_sources[0x4e]	303318	1			T3	16		T4	1		T6	30
valid_sources[0x4f]	310888	1			T3	25		T4	1		T6	33
valid_sources[0x50]	294126	1			T3	28		T6	13		T7	4263
valid_sources[0x51]	275030	1			T3	34		T4	1		T6	43
valid_sources[0x52]	344307	1			T1	5		T3	65		T4	1
valid_sources[0x53]	281048	1			T3	37		T4	1		T6	34
valid_sources[0x54]	290834	1			T1	1		T3	15		T6	24
valid_sources[0x55]	285435	1			T3	30		T4	1		T6	65
valid_sources[0x56]	308964	1			T3	53		T6	28		T7	4290
valid_sources[0x57]	288027	1			T3	61		T6	35		T7	4078
valid_sources[0x58]	290144	1			T3	11		T4	1		T6	56
valid_sources[0x59]	297045	1			T3	26		T4	2		T6	54
valid_sources[0x5a]	351946	1			T1	7		T3	32		T6	29
valid_sources[0x5b]	297114	1			T3	38		T6	21		T7	4369
valid_sources[0x5c]	300578	1			T3	44		T4	1		T6	30
valid_sources[0x5d]	281121	1			T3	40		T6	37		T7	4309
valid_sources[0x5e]	298184	1			T1	15		T3	29		T6	27
valid_sources[0x5f]	355720	1			T3	9		T4	1		T6	42
valid_sources[0x60]	301881	1			T1	16		T3	43		T4	1
valid_sources[0x61]	295900	1			T1	2		T3	39		T4	1
valid_sources[0x62]	301973	1			T3	58		T6	37		T7	3967
valid_sources[0x63]	305936	1			T1	13		T3	37		T4	2
valid_sources[0x64]	362675	1			T3	56		T4	1		T6	15
valid_sources[0x65]	323507	1			T3	27		T6	31		T7	4191
valid_sources[0x66]	302223	1			T3	36		T6	35		T7	4161
valid_sources[0x67]	326654	1			T3	53		T4	1		T6	47
valid_sources[0x68]	309524	1			T1	26		T3	19		T4	1
valid_sources[0x69]	310463	1			T3	48		T4	3		T6	47
valid_sources[0x6a]	299913	1			T3	19		T4	2		T6	38
valid_sources[0x6b]	305866	1			T2	1		T3	42		T4	1
valid_sources[0x6c]	306579	1			T3	29		T6	28		T7	4334
valid_sources[0x6d]	304681	1			T3	51		T4	1		T6	35
valid_sources[0x6e]	290242	1			T1	5		T3	28		T6	39
valid_sources[0x6f]	417877	1			T3	21		T4	1		T6	29
valid_sources[0x70]	274762	1			T3	39		T4	1		T6	32
valid_sources[0x71]	288538	1			T3	39		T6	31		T7	4210
valid_sources[0x72]	278963	1			T3	20		T4	4		T6	34
valid_sources[0x73]	287584	1			T3	17		T4	3		T6	38
valid_sources[0x74]	279132	1			T1	3		T3	8		T6	28
valid_sources[0x75]	353312	1			T3	38		T6	46		T7	3925
valid_sources[0x76]	300216	1			T3	43		T6	23		T7	4349
valid_sources[0x77]	294649	1			T3	35		T6	15		T7	4196
valid_sources[0x78]	314571	1			T1	38		T3	41		T4	4
valid_sources[0x79]	293465	1			T3	15		T4	1		T6	27
valid_sources[0x7a]	313026	1			T3	34		T6	50		T7	4228
valid_sources[0x7b]	294893	1			T3	69		T4	1		T6	27
valid_sources[0x7c]	289397	1			T1	7		T3	41		T4	1
valid_sources[0x7d]	281145	1			T3	38		T6	26		T7	4114
valid_sources[0x7e]	286003	1			T3	15		T4	5		T6	28
valid_sources[0x7f]	302400	1			T3	54		T4	4		T6	48
valid_sources[0x80]	277399	1			T3	25		T4	1		T6	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19289176

1

T1

165

T2

96

T3

6

values[0x0]

all_enables

biggest_size

1886158

1

T1

37

T2

82

T3

1

values[0x1]

all_enables

biggest_size

1835709

1

T1

21

T2

49

T3

3