Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5966519	0	0
ctrl_rd_A	2147483647	142143	0	0
intr_enable_rd_A	2147483647	124507	0	0
ovrd_rd_A	2147483647	138628	0	0
timeout_ctrl_rd_A	2147483647	140173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5966519	0	0
T11	851934	240799	0	0
T12	0	250145	0	0
T15	219686	55527	0	0
T24	0	87827	0	0
T26	0	177917	0	0
T38	0	64497	0	0
T39	0	88108	0	0
T40	0	167156	0	0
T41	0	397563	0	0
T42	0	69565	0	0
T43	47346	0	0	0
T44	154235	0	0	0
T45	793518	0	0	0
T46	905490	0	0	0
T47	766949	0	0	0
T48	189085	0	0	0
T49	780315	0	0	0
T50	382808	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	142143	0	0
T12	0	27089	0	0
T15	219686	6026	0	0
T16	390023	0	0	0
T26	0	10817	0	0
T38	0	7417	0	0
T48	189085	0	0	0
T49	780315	0	0	0
T50	382808	0	0	0
T58	0	6157	0	0
T72	0	5969	0	0
T111	0	10342	0	0
T112	0	3192	0	0
T113	0	4348	0	0
T114	0	14882	0	0
T115	693166	0	0	0
T116	501557	0	0	0
T117	107729	0	0	0
T118	176787	0	0	0
T119	678681	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	124507	0	0
T12	0	23907	0	0
T15	219686	5040	0	0
T16	390023	0	0	0
T26	0	9324	0	0
T38	0	6654	0	0
T48	189085	0	0	0
T49	780315	0	0	0
T50	382808	0	0	0
T58	0	5149	0	0
T72	0	5657	0	0
T111	0	8841	0	0
T112	0	2723	0	0
T113	0	3617	0	0
T115	693166	0	0	0
T116	501557	0	0	0
T117	107729	0	0	0
T118	176787	0	0	0
T119	678681	0	0	0
T120	0	15	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	138628	0	0
T12	0	27031	0	0
T15	219686	5992	0	0
T16	390023	0	0	0
T26	0	10852	0	0
T38	0	7705	0	0
T48	189085	0	0	0
T49	780315	0	0	0
T50	382808	0	0	0
T58	0	5929	0	0
T72	0	5706	0	0
T111	0	9862	0	0
T112	0	2949	0	0
T113	0	4016	0	0
T114	0	14958	0	0
T115	693166	0	0	0
T116	501557	0	0	0
T117	107729	0	0	0
T118	176787	0	0	0
T119	678681	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	140173	0	0
T12	0	27509	0	0
T15	219686	6088	0	0
T16	390023	0	0	0
T26	0	10817	0	0
T38	0	7553	0	0
T48	189085	0	0	0
T49	780315	0	0	0
T50	382808	0	0	0
T58	0	5992	0	0
T72	0	5904	0	0
T111	0	10081	0	0
T112	0	3192	0	0
T113	0	4419	0	0
T114	0	14294	0	0
T115	693166	0	0	0
T116	501557	0	0	0
T117	107729	0	0	0
T118	176787	0	0	0
T119	678681	0	0	0