Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.89 99.38 97.89 100.00 98.83 100.00 97.27


Total test records in report: 1259
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T1049 /workspace/coverage/default/5.uart_fifo_overflow.1507659221 Mar 12 01:07:00 PM PDT 24 Mar 12 01:10:02 PM PDT 24 116198270265 ps
T1050 /workspace/coverage/default/42.uart_tx_rx.1345038567 Mar 12 01:08:25 PM PDT 24 Mar 12 01:08:33 PM PDT 24 14231049402 ps
T260 /workspace/coverage/default/147.uart_fifo_reset.264606298 Mar 12 01:09:32 PM PDT 24 Mar 12 01:10:04 PM PDT 24 48755509491 ps
T1051 /workspace/coverage/default/8.uart_rx_parity_err.218353140 Mar 12 01:07:09 PM PDT 24 Mar 12 01:07:22 PM PDT 24 15871022160 ps
T1052 /workspace/coverage/default/80.uart_fifo_reset.3745739258 Mar 12 01:09:13 PM PDT 24 Mar 12 01:10:13 PM PDT 24 190711106477 ps
T1053 /workspace/coverage/default/41.uart_fifo_overflow.2234254332 Mar 12 01:08:29 PM PDT 24 Mar 12 01:09:14 PM PDT 24 252211009985 ps
T1054 /workspace/coverage/default/40.uart_loopback.1780356059 Mar 12 01:08:39 PM PDT 24 Mar 12 01:08:44 PM PDT 24 2977731414 ps
T1055 /workspace/coverage/default/22.uart_rx_start_bit_filter.786802389 Mar 12 01:07:42 PM PDT 24 Mar 12 01:07:49 PM PDT 24 4686405504 ps
T1056 /workspace/coverage/default/33.uart_rx_start_bit_filter.2280308246 Mar 12 01:08:05 PM PDT 24 Mar 12 01:08:08 PM PDT 24 4475985726 ps
T1057 /workspace/coverage/default/269.uart_fifo_reset.562472029 Mar 12 01:09:56 PM PDT 24 Mar 12 01:11:05 PM PDT 24 50241644372 ps
T294 /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3411856258 Mar 12 01:09:05 PM PDT 24 Mar 12 01:40:43 PM PDT 24 95239183693 ps
T1058 /workspace/coverage/default/97.uart_fifo_reset.2165503984 Mar 12 01:09:19 PM PDT 24 Mar 12 01:09:41 PM PDT 24 47639709534 ps
T1059 /workspace/coverage/default/12.uart_fifo_full.3829731 Mar 12 01:07:09 PM PDT 24 Mar 12 01:08:03 PM PDT 24 107583341709 ps
T1060 /workspace/coverage/default/90.uart_fifo_reset.3681188904 Mar 12 01:09:14 PM PDT 24 Mar 12 01:09:40 PM PDT 24 54970853539 ps
T1061 /workspace/coverage/default/7.uart_noise_filter.1080060964 Mar 12 01:07:04 PM PDT 24 Mar 12 01:08:27 PM PDT 24 150989764369 ps
T1062 /workspace/coverage/default/33.uart_tx_ovrd.555909496 Mar 12 01:08:04 PM PDT 24 Mar 12 01:08:07 PM PDT 24 652650298 ps
T1063 /workspace/coverage/default/17.uart_fifo_reset.1871075222 Mar 12 01:07:24 PM PDT 24 Mar 12 01:08:01 PM PDT 24 20503698591 ps
T1064 /workspace/coverage/default/34.uart_fifo_full.585029931 Mar 12 01:08:02 PM PDT 24 Mar 12 01:08:56 PM PDT 24 33478716009 ps
T1065 /workspace/coverage/default/32.uart_rx_parity_err.2120430003 Mar 12 01:08:02 PM PDT 24 Mar 12 01:09:03 PM PDT 24 40349209382 ps
T288 /workspace/coverage/default/14.uart_perf.1804792263 Mar 12 01:07:03 PM PDT 24 Mar 12 01:10:34 PM PDT 24 13111112858 ps
T1066 /workspace/coverage/default/20.uart_noise_filter.1059928889 Mar 12 01:07:34 PM PDT 24 Mar 12 01:07:45 PM PDT 24 23230211393 ps
T1067 /workspace/coverage/default/25.uart_tx_rx.2565367390 Mar 12 01:07:51 PM PDT 24 Mar 12 01:10:14 PM PDT 24 63793052424 ps
T1068 /workspace/coverage/default/46.uart_noise_filter.777703329 Mar 12 01:09:00 PM PDT 24 Mar 12 01:10:00 PM PDT 24 138053439245 ps
T1069 /workspace/coverage/default/5.uart_long_xfer_wo_dly.3419781698 Mar 12 01:07:09 PM PDT 24 Mar 12 01:25:14 PM PDT 24 129693989735 ps
T1070 /workspace/coverage/default/259.uart_fifo_reset.3324598959 Mar 12 01:09:54 PM PDT 24 Mar 12 01:10:32 PM PDT 24 286809721414 ps
T1071 /workspace/coverage/default/42.uart_fifo_overflow.3203510882 Mar 12 01:08:28 PM PDT 24 Mar 12 01:09:31 PM PDT 24 140673224906 ps
T1072 /workspace/coverage/default/291.uart_fifo_reset.2629551402 Mar 12 01:10:07 PM PDT 24 Mar 12 01:10:20 PM PDT 24 21627170134 ps
T339 /workspace/coverage/default/50.uart_fifo_reset.598864510 Mar 12 01:09:03 PM PDT 24 Mar 12 01:12:20 PM PDT 24 244592911575 ps
T1073 /workspace/coverage/default/1.uart_rx_parity_err.4065747431 Mar 12 01:06:53 PM PDT 24 Mar 12 01:07:22 PM PDT 24 55828757778 ps
T378 /workspace/coverage/default/29.uart_stress_all.1336979082 Mar 12 01:08:03 PM PDT 24 Mar 12 01:10:43 PM PDT 24 75355128348 ps
T348 /workspace/coverage/default/193.uart_fifo_reset.2076030938 Mar 12 01:09:39 PM PDT 24 Mar 12 01:10:13 PM PDT 24 83319393723 ps
T1074 /workspace/coverage/default/5.uart_intr.2510365549 Mar 12 01:07:02 PM PDT 24 Mar 12 01:07:14 PM PDT 24 32475974852 ps
T1075 /workspace/coverage/default/24.uart_smoke.742820973 Mar 12 01:07:49 PM PDT 24 Mar 12 01:08:11 PM PDT 24 11061033289 ps
T363 /workspace/coverage/default/266.uart_fifo_reset.936540771 Mar 12 01:09:55 PM PDT 24 Mar 12 01:12:33 PM PDT 24 113574165991 ps
T1076 /workspace/coverage/default/37.uart_rx_parity_err.2743528980 Mar 12 01:08:17 PM PDT 24 Mar 12 01:09:07 PM PDT 24 74341351921 ps
T1077 /workspace/coverage/default/19.uart_perf.4090337714 Mar 12 01:07:31 PM PDT 24 Mar 12 01:21:57 PM PDT 24 25456215981 ps
T1078 /workspace/coverage/default/30.uart_smoke.3705481607 Mar 12 01:07:59 PM PDT 24 Mar 12 01:08:01 PM PDT 24 461285620 ps
T1079 /workspace/coverage/default/3.uart_intr.2204109803 Mar 12 01:07:00 PM PDT 24 Mar 12 01:07:16 PM PDT 24 60223358378 ps
T1080 /workspace/coverage/default/37.uart_alert_test.1722389839 Mar 12 01:08:15 PM PDT 24 Mar 12 01:08:17 PM PDT 24 13223026 ps
T1081 /workspace/coverage/default/16.uart_tx_ovrd.261172594 Mar 12 01:07:22 PM PDT 24 Mar 12 01:07:24 PM PDT 24 998311682 ps
T295 /workspace/coverage/default/43.uart_fifo_full.3467223356 Mar 12 01:08:35 PM PDT 24 Mar 12 01:09:39 PM PDT 24 151414763003 ps
T1082 /workspace/coverage/default/75.uart_fifo_reset.856851879 Mar 12 01:09:13 PM PDT 24 Mar 12 01:09:27 PM PDT 24 35198701455 ps
T1083 /workspace/coverage/default/82.uart_fifo_reset.2238009494 Mar 12 01:09:15 PM PDT 24 Mar 12 01:09:35 PM PDT 24 44011877912 ps
T320 /workspace/coverage/default/125.uart_fifo_reset.3030136887 Mar 12 01:09:25 PM PDT 24 Mar 12 01:09:40 PM PDT 24 30176296206 ps
T1084 /workspace/coverage/default/6.uart_rx_start_bit_filter.330047182 Mar 12 01:07:04 PM PDT 24 Mar 12 01:07:08 PM PDT 24 1773887861 ps
T1085 /workspace/coverage/default/36.uart_fifo_reset.3962672084 Mar 12 01:08:08 PM PDT 24 Mar 12 01:08:15 PM PDT 24 11000227495 ps
T1086 /workspace/coverage/default/25.uart_fifo_full.3427719764 Mar 12 01:07:55 PM PDT 24 Mar 12 01:08:22 PM PDT 24 62061397894 ps
T258 /workspace/coverage/default/270.uart_fifo_reset.3577013993 Mar 12 01:09:54 PM PDT 24 Mar 12 01:10:34 PM PDT 24 89518122511 ps
T292 /workspace/coverage/default/26.uart_stress_all.2838860086 Mar 12 01:07:49 PM PDT 24 Mar 12 01:10:33 PM PDT 24 35995395256 ps
T1087 /workspace/coverage/default/180.uart_fifo_reset.4269663471 Mar 12 01:09:34 PM PDT 24 Mar 12 01:10:57 PM PDT 24 88002829805 ps
T1088 /workspace/coverage/default/41.uart_intr.4155562601 Mar 12 01:08:26 PM PDT 24 Mar 12 01:08:30 PM PDT 24 20811138343 ps
T1089 /workspace/coverage/default/29.uart_smoke.1182940667 Mar 12 01:07:47 PM PDT 24 Mar 12 01:07:48 PM PDT 24 307901445 ps
T1090 /workspace/coverage/default/5.uart_tx_ovrd.2721961846 Mar 12 01:06:58 PM PDT 24 Mar 12 01:07:01 PM PDT 24 756591937 ps
T1091 /workspace/coverage/default/254.uart_fifo_reset.2739898508 Mar 12 01:09:54 PM PDT 24 Mar 12 01:10:18 PM PDT 24 49040801582 ps
T1092 /workspace/coverage/default/24.uart_alert_test.834147630 Mar 12 01:07:52 PM PDT 24 Mar 12 01:07:52 PM PDT 24 13347188 ps
T1093 /workspace/coverage/default/28.uart_rx_start_bit_filter.1502290155 Mar 12 01:07:59 PM PDT 24 Mar 12 01:08:16 PM PDT 24 37245637875 ps
T1094 /workspace/coverage/default/95.uart_fifo_reset.911124444 Mar 12 01:09:23 PM PDT 24 Mar 12 01:09:40 PM PDT 24 80816756281 ps
T1095 /workspace/coverage/default/8.uart_noise_filter.3420242832 Mar 12 01:07:06 PM PDT 24 Mar 12 01:08:06 PM PDT 24 41510631694 ps
T1096 /workspace/coverage/default/212.uart_fifo_reset.3623864004 Mar 12 01:09:45 PM PDT 24 Mar 12 01:10:27 PM PDT 24 93479157461 ps
T1097 /workspace/coverage/default/6.uart_alert_test.3154087752 Mar 12 01:07:08 PM PDT 24 Mar 12 01:07:11 PM PDT 24 43576318 ps
T1098 /workspace/coverage/default/23.uart_tx_ovrd.920002561 Mar 12 01:07:53 PM PDT 24 Mar 12 01:08:09 PM PDT 24 7052779386 ps
T1099 /workspace/coverage/default/1.uart_smoke.2329532459 Mar 12 01:06:57 PM PDT 24 Mar 12 01:07:00 PM PDT 24 407367242 ps
T1100 /workspace/coverage/default/11.uart_intr.278720769 Mar 12 01:07:09 PM PDT 24 Mar 12 01:07:48 PM PDT 24 48506816616 ps
T1101 /workspace/coverage/default/59.uart_fifo_reset.1398798891 Mar 12 01:09:01 PM PDT 24 Mar 12 01:09:17 PM PDT 24 18525642700 ps
T1102 /workspace/coverage/default/27.uart_smoke.1775199047 Mar 12 01:07:58 PM PDT 24 Mar 12 01:07:59 PM PDT 24 779667073 ps
T1103 /workspace/coverage/default/169.uart_fifo_reset.2808475498 Mar 12 01:09:38 PM PDT 24 Mar 12 01:10:20 PM PDT 24 22869010539 ps
T1104 /workspace/coverage/default/240.uart_fifo_reset.1611131622 Mar 12 01:09:44 PM PDT 24 Mar 12 01:10:15 PM PDT 24 17044719650 ps
T194 /workspace/coverage/default/138.uart_fifo_reset.29340427 Mar 12 01:09:25 PM PDT 24 Mar 12 01:09:57 PM PDT 24 8579062233 ps
T1105 /workspace/coverage/default/42.uart_long_xfer_wo_dly.1939119885 Mar 12 01:08:36 PM PDT 24 Mar 12 01:19:33 PM PDT 24 104320020172 ps
T1106 /workspace/coverage/default/34.uart_fifo_reset.1826358891 Mar 12 01:08:08 PM PDT 24 Mar 12 01:08:30 PM PDT 24 58142401319 ps
T1107 /workspace/coverage/default/48.uart_stress_all.423914858 Mar 12 01:08:52 PM PDT 24 Mar 12 01:23:55 PM PDT 24 32765944772 ps
T1108 /workspace/coverage/default/146.uart_fifo_reset.396015339 Mar 12 01:09:34 PM PDT 24 Mar 12 01:12:43 PM PDT 24 116970709688 ps
T1109 /workspace/coverage/default/30.uart_stress_all.1980891420 Mar 12 01:07:50 PM PDT 24 Mar 12 01:09:17 PM PDT 24 199214895519 ps
T1110 /workspace/coverage/default/24.uart_tx_rx.4117160651 Mar 12 01:07:45 PM PDT 24 Mar 12 01:07:52 PM PDT 24 3912633229 ps
T1111 /workspace/coverage/default/14.uart_noise_filter.2009146965 Mar 12 01:07:11 PM PDT 24 Mar 12 01:07:29 PM PDT 24 46328001876 ps
T387 /workspace/coverage/default/29.uart_rx_parity_err.1365272395 Mar 12 01:08:01 PM PDT 24 Mar 12 01:08:30 PM PDT 24 243710191672 ps
T1112 /workspace/coverage/default/29.uart_perf.194876130 Mar 12 01:08:03 PM PDT 24 Mar 12 01:24:57 PM PDT 24 34576471153 ps
T1113 /workspace/coverage/default/22.uart_alert_test.55897910 Mar 12 01:07:44 PM PDT 24 Mar 12 01:07:45 PM PDT 24 34606213 ps
T283 /workspace/coverage/default/294.uart_fifo_reset.4183071246 Mar 12 01:10:08 PM PDT 24 Mar 12 01:10:50 PM PDT 24 22914064919 ps
T1114 /workspace/coverage/default/48.uart_rx_parity_err.3173527265 Mar 12 01:08:52 PM PDT 24 Mar 12 01:09:12 PM PDT 24 18972587950 ps
T440 /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3360460552 Mar 12 01:07:07 PM PDT 24 Mar 12 01:14:36 PM PDT 24 37935134227 ps
T1115 /workspace/coverage/default/39.uart_perf.3059329172 Mar 12 01:08:24 PM PDT 24 Mar 12 01:11:38 PM PDT 24 26066265103 ps
T1116 /workspace/coverage/default/3.uart_fifo_full.1320474860 Mar 12 01:07:04 PM PDT 24 Mar 12 01:10:03 PM PDT 24 225668221089 ps
T1117 /workspace/coverage/default/39.uart_tx_ovrd.1490566218 Mar 12 01:08:27 PM PDT 24 Mar 12 01:08:29 PM PDT 24 1096884469 ps
T1118 /workspace/coverage/default/43.uart_tx_ovrd.1978330126 Mar 12 01:08:35 PM PDT 24 Mar 12 01:08:38 PM PDT 24 1473102377 ps
T1119 /workspace/coverage/default/35.uart_rx_parity_err.2787676661 Mar 12 01:08:06 PM PDT 24 Mar 12 01:09:11 PM PDT 24 145527387847 ps
T1120 /workspace/coverage/default/177.uart_fifo_reset.3908672715 Mar 12 01:09:37 PM PDT 24 Mar 12 01:10:21 PM PDT 24 26484814669 ps
T1121 /workspace/coverage/default/168.uart_fifo_reset.1911302619 Mar 12 01:09:35 PM PDT 24 Mar 12 01:10:20 PM PDT 24 96067319697 ps
T1122 /workspace/coverage/default/224.uart_fifo_reset.3063660950 Mar 12 01:09:47 PM PDT 24 Mar 12 01:10:11 PM PDT 24 13137176485 ps
T1123 /workspace/coverage/default/1.uart_rx_start_bit_filter.4116230176 Mar 12 01:07:09 PM PDT 24 Mar 12 01:07:19 PM PDT 24 4501497131 ps
T296 /workspace/coverage/default/234.uart_fifo_reset.1423204598 Mar 12 01:09:44 PM PDT 24 Mar 12 01:09:50 PM PDT 24 7700921732 ps
T1124 /workspace/coverage/default/21.uart_rx_oversample.2112062019 Mar 12 01:07:49 PM PDT 24 Mar 12 01:08:22 PM PDT 24 3799798731 ps
T1125 /workspace/coverage/default/13.uart_alert_test.823337833 Mar 12 01:07:12 PM PDT 24 Mar 12 01:07:15 PM PDT 24 13381971 ps
T1126 /workspace/coverage/default/0.uart_fifo_overflow.3111849135 Mar 12 01:06:42 PM PDT 24 Mar 12 01:06:56 PM PDT 24 9406092301 ps
T1127 /workspace/coverage/cover_reg_top/28.uart_intr_test.674823617 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:53 PM PDT 24 14361547 ps
T60 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.289615060 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:20 PM PDT 24 16785778 ps
T81 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1629083916 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:44 PM PDT 24 13664992 ps
T1128 /workspace/coverage/cover_reg_top/29.uart_intr_test.106314866 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:00 PM PDT 24 38564665 ps
T82 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.79880769 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:34 PM PDT 24 573470879 ps
T1129 /workspace/coverage/cover_reg_top/26.uart_intr_test.4257516074 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:50 PM PDT 24 35556349 ps
T1130 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3689164774 Mar 12 12:29:40 PM PDT 24 Mar 12 12:29:41 PM PDT 24 18818712 ps
T83 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3229888068 Mar 12 12:29:27 PM PDT 24 Mar 12 12:29:33 PM PDT 24 59866735 ps
T1131 /workspace/coverage/cover_reg_top/22.uart_intr_test.1865181150 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 12600685 ps
T91 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1264517987 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 86656292 ps
T1132 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2144295218 Mar 12 12:29:31 PM PDT 24 Mar 12 12:29:32 PM PDT 24 41583978 ps
T1133 /workspace/coverage/cover_reg_top/46.uart_intr_test.4258813167 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 32936650 ps
T1134 /workspace/coverage/cover_reg_top/1.uart_intr_test.1859223949 Mar 12 12:29:12 PM PDT 24 Mar 12 12:29:13 PM PDT 24 25251924 ps
T92 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1670448383 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:15 PM PDT 24 50016378 ps
T67 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1430119356 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:32 PM PDT 24 179984240 ps
T84 /workspace/coverage/cover_reg_top/2.uart_csr_rw.40560810 Mar 12 12:29:29 PM PDT 24 Mar 12 12:29:29 PM PDT 24 30435240 ps
T1135 /workspace/coverage/cover_reg_top/39.uart_intr_test.4183152768 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:57 PM PDT 24 45923000 ps
T1136 /workspace/coverage/cover_reg_top/36.uart_intr_test.3538645749 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 68345581 ps
T1137 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.363439456 Mar 12 12:29:29 PM PDT 24 Mar 12 12:29:31 PM PDT 24 214059442 ps
T1138 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1223093637 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:48 PM PDT 24 326875731 ps
T1139 /workspace/coverage/cover_reg_top/2.uart_intr_test.262947042 Mar 12 12:29:29 PM PDT 24 Mar 12 12:29:30 PM PDT 24 11806736 ps
T1140 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.129357569 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 27383619 ps
T85 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4203187436 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 64791439 ps
T1141 /workspace/coverage/cover_reg_top/44.uart_intr_test.2031433772 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 22971943 ps
T93 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.228354522 Mar 12 12:29:45 PM PDT 24 Mar 12 12:29:46 PM PDT 24 592840305 ps
T1142 /workspace/coverage/cover_reg_top/4.uart_tl_errors.4242720170 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 490655964 ps
T86 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3491848723 Mar 12 12:29:41 PM PDT 24 Mar 12 12:29:42 PM PDT 24 15253598 ps
T1143 /workspace/coverage/cover_reg_top/47.uart_intr_test.2256014593 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:51 PM PDT 24 30245853 ps
T1144 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1994045383 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:52 PM PDT 24 77086458 ps
T1145 /workspace/coverage/cover_reg_top/13.uart_intr_test.4115289329 Mar 12 12:29:43 PM PDT 24 Mar 12 12:29:44 PM PDT 24 25990879 ps
T1146 /workspace/coverage/cover_reg_top/1.uart_tl_errors.178717972 Mar 12 12:29:11 PM PDT 24 Mar 12 12:29:13 PM PDT 24 27412563 ps
T1147 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1874673606 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:51 PM PDT 24 52346692 ps
T1148 /workspace/coverage/cover_reg_top/40.uart_intr_test.1084600051 Mar 12 12:30:05 PM PDT 24 Mar 12 12:30:05 PM PDT 24 39638936 ps
T1149 /workspace/coverage/cover_reg_top/0.uart_intr_test.1832717569 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:18 PM PDT 24 40708549 ps
T61 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1358638444 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:49 PM PDT 24 35289638 ps
T87 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2465844277 Mar 12 12:29:36 PM PDT 24 Mar 12 12:29:37 PM PDT 24 66752667 ps
T1150 /workspace/coverage/cover_reg_top/33.uart_intr_test.2280106155 Mar 12 12:29:39 PM PDT 24 Mar 12 12:29:44 PM PDT 24 20077398 ps
T1151 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3960216128 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:15 PM PDT 24 87722868 ps
T1152 /workspace/coverage/cover_reg_top/17.uart_tl_errors.68287695 Mar 12 12:29:45 PM PDT 24 Mar 12 12:29:46 PM PDT 24 31755357 ps
T62 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1116537490 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 21300401 ps
T63 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3225409287 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:48 PM PDT 24 41086013 ps
T1153 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2604526942 Mar 12 12:29:42 PM PDT 24 Mar 12 12:29:43 PM PDT 24 31375952 ps
T94 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.461676761 Mar 12 12:29:28 PM PDT 24 Mar 12 12:29:29 PM PDT 24 106228569 ps
T1154 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2711332394 Mar 12 12:29:27 PM PDT 24 Mar 12 12:29:29 PM PDT 24 74524637 ps
T1155 /workspace/coverage/cover_reg_top/37.uart_intr_test.3613920816 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 13215232 ps
T391 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3326289125 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:48 PM PDT 24 311690050 ps
T1156 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.296125808 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 47733184 ps
T88 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1644426517 Mar 12 12:29:32 PM PDT 24 Mar 12 12:29:33 PM PDT 24 14785706 ps
T1157 /workspace/coverage/cover_reg_top/15.uart_intr_test.3384444494 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:49 PM PDT 24 31084497 ps
T1158 /workspace/coverage/cover_reg_top/10.uart_csr_rw.347345414 Mar 12 12:29:31 PM PDT 24 Mar 12 12:29:31 PM PDT 24 65703758 ps
T1159 /workspace/coverage/cover_reg_top/11.uart_tl_errors.574620345 Mar 12 12:29:31 PM PDT 24 Mar 12 12:29:32 PM PDT 24 22158951 ps
T1160 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.394885873 Mar 12 12:29:32 PM PDT 24 Mar 12 12:29:33 PM PDT 24 55749175 ps
T1161 /workspace/coverage/cover_reg_top/19.uart_intr_test.771396126 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:48 PM PDT 24 25553359 ps
T1162 /workspace/coverage/cover_reg_top/12.uart_csr_rw.866488508 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 35783186 ps
T1163 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2705742397 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 79076756 ps
T1164 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.112850888 Mar 12 12:29:27 PM PDT 24 Mar 12 12:29:28 PM PDT 24 20307387 ps
T390 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2420968024 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 173061626 ps
T1165 /workspace/coverage/cover_reg_top/30.uart_intr_test.3100121593 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:48 PM PDT 24 16062886 ps
T1166 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3010409487 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:34 PM PDT 24 17164439 ps
T1167 /workspace/coverage/cover_reg_top/35.uart_intr_test.3963118435 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:55 PM PDT 24 24476091 ps
T1168 /workspace/coverage/cover_reg_top/45.uart_intr_test.2463515419 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:50 PM PDT 24 14637036 ps
T1169 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2811337666 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:47 PM PDT 24 25040336 ps
T1170 /workspace/coverage/cover_reg_top/18.uart_intr_test.2400341602 Mar 12 12:30:05 PM PDT 24 Mar 12 12:30:06 PM PDT 24 13721990 ps
T1171 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3686717183 Mar 12 12:29:38 PM PDT 24 Mar 12 12:29:39 PM PDT 24 31520919 ps
T1172 /workspace/coverage/cover_reg_top/14.uart_intr_test.1669860647 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:45 PM PDT 24 16944436 ps
T64 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1246573516 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:46 PM PDT 24 15577991 ps
T1173 /workspace/coverage/cover_reg_top/6.uart_intr_test.3891495437 Mar 12 12:29:29 PM PDT 24 Mar 12 12:29:31 PM PDT 24 38556859 ps
T1174 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3710274225 Mar 12 12:29:32 PM PDT 24 Mar 12 12:29:33 PM PDT 24 19714044 ps
T1175 /workspace/coverage/cover_reg_top/5.uart_intr_test.343113324 Mar 12 12:29:27 PM PDT 24 Mar 12 12:29:28 PM PDT 24 72982883 ps
T1176 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2745808695 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:32 PM PDT 24 879659988 ps
T96 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.659796368 Mar 12 12:29:34 PM PDT 24 Mar 12 12:29:35 PM PDT 24 93125443 ps
T1177 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3583525997 Mar 12 12:29:45 PM PDT 24 Mar 12 12:29:46 PM PDT 24 16831642 ps
T1178 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3030850802 Mar 12 12:29:29 PM PDT 24 Mar 12 12:29:31 PM PDT 24 47538999 ps
T97 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.45231460 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:45 PM PDT 24 111082997 ps
T1179 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1775771250 Mar 12 12:29:43 PM PDT 24 Mar 12 12:29:44 PM PDT 24 26056833 ps
T1180 /workspace/coverage/cover_reg_top/34.uart_intr_test.983300984 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:54 PM PDT 24 13700275 ps
T1181 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3379482290 Mar 12 12:29:38 PM PDT 24 Mar 12 12:29:39 PM PDT 24 69682898 ps
T1182 /workspace/coverage/cover_reg_top/12.uart_intr_test.1011713392 Mar 12 12:29:36 PM PDT 24 Mar 12 12:29:37 PM PDT 24 35450469 ps
T1183 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3625635806 Mar 12 12:29:18 PM PDT 24 Mar 12 12:29:19 PM PDT 24 22047367 ps
T1184 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1716512857 Mar 12 12:29:12 PM PDT 24 Mar 12 12:29:13 PM PDT 24 76000642 ps
T65 /workspace/coverage/cover_reg_top/13.uart_csr_rw.100859908 Mar 12 12:29:38 PM PDT 24 Mar 12 12:29:39 PM PDT 24 34827230 ps
T1185 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2361696852 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:35 PM PDT 24 23346501 ps
T1186 /workspace/coverage/cover_reg_top/7.uart_intr_test.2394875649 Mar 12 12:29:31 PM PDT 24 Mar 12 12:29:32 PM PDT 24 14822435 ps
T1187 /workspace/coverage/cover_reg_top/9.uart_intr_test.1556197008 Mar 12 12:29:45 PM PDT 24 Mar 12 12:29:46 PM PDT 24 30753982 ps
T66 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2102578376 Mar 12 12:29:34 PM PDT 24 Mar 12 12:29:34 PM PDT 24 16257473 ps
T1188 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.301703641 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:34 PM PDT 24 67068868 ps
T1189 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1892679187 Mar 12 12:29:34 PM PDT 24 Mar 12 12:29:34 PM PDT 24 21465224 ps
T1190 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2958166644 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 26058268 ps
T1191 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2099480279 Mar 12 12:29:38 PM PDT 24 Mar 12 12:29:39 PM PDT 24 16109502 ps
T1192 /workspace/coverage/cover_reg_top/32.uart_intr_test.2859738346 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:53 PM PDT 24 164720416 ps
T1193 /workspace/coverage/cover_reg_top/41.uart_intr_test.2862188925 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:54 PM PDT 24 54057851 ps
T1194 /workspace/coverage/cover_reg_top/24.uart_intr_test.874445079 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:57 PM PDT 24 37582626 ps
T1195 /workspace/coverage/cover_reg_top/10.uart_intr_test.3300273605 Mar 12 12:29:38 PM PDT 24 Mar 12 12:29:39 PM PDT 24 24433731 ps
T1196 /workspace/coverage/cover_reg_top/19.uart_tl_errors.4264929631 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:51 PM PDT 24 205366717 ps
T100 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1967781590 Mar 12 12:29:34 PM PDT 24 Mar 12 12:29:35 PM PDT 24 75274063 ps
T1197 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1768722533 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:19 PM PDT 24 214465313 ps
T1198 /workspace/coverage/cover_reg_top/5.uart_tl_errors.4242242134 Mar 12 12:29:29 PM PDT 24 Mar 12 12:29:32 PM PDT 24 32387632 ps
T1199 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1345030884 Mar 12 12:29:28 PM PDT 24 Mar 12 12:29:29 PM PDT 24 12272845 ps
T1200 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3390066013 Mar 12 12:29:36 PM PDT 24 Mar 12 12:29:37 PM PDT 24 34303599 ps
T1201 /workspace/coverage/cover_reg_top/42.uart_intr_test.3332901884 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:51 PM PDT 24 25243685 ps
T1202 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1117778328 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 11394747 ps
T1203 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2167316297 Mar 12 12:29:41 PM PDT 24 Mar 12 12:29:43 PM PDT 24 46283681 ps
T99 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2249399273 Mar 12 12:29:36 PM PDT 24 Mar 12 12:29:38 PM PDT 24 81370843 ps
T1204 /workspace/coverage/cover_reg_top/11.uart_intr_test.1093035312 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:47 PM PDT 24 44131513 ps
T1205 /workspace/coverage/cover_reg_top/25.uart_intr_test.1378647425 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:47 PM PDT 24 33589099 ps
T1206 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2734848631 Mar 12 12:29:32 PM PDT 24 Mar 12 12:29:32 PM PDT 24 74437490 ps
T1207 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.365012206 Mar 12 12:29:27 PM PDT 24 Mar 12 12:29:28 PM PDT 24 14777941 ps
T1208 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1543159865 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:34 PM PDT 24 43420348 ps
T1209 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2176483970 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:51 PM PDT 24 53047282 ps
T1210 /workspace/coverage/cover_reg_top/8.uart_intr_test.1268471016 Mar 12 12:29:29 PM PDT 24 Mar 12 12:29:30 PM PDT 24 41848800 ps
T1211 /workspace/coverage/cover_reg_top/15.uart_tl_errors.878256079 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:46 PM PDT 24 75941477 ps
T1212 /workspace/coverage/cover_reg_top/20.uart_intr_test.1965035626 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:46 PM PDT 24 91246024 ps
T1213 /workspace/coverage/cover_reg_top/9.uart_tl_errors.4276006749 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:46 PM PDT 24 415223451 ps
T1214 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2843279388 Mar 12 12:29:41 PM PDT 24 Mar 12 12:29:42 PM PDT 24 422584082 ps
T1215 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3749937583 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 21275823 ps
T1216 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3197880406 Mar 12 12:29:38 PM PDT 24 Mar 12 12:29:39 PM PDT 24 29190871 ps
T98 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3162420335 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 44109549 ps
T95 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1253141006 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 153117342 ps
T1217 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1143558517 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:47 PM PDT 24 21853173 ps
T1218 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2591416569 Mar 12 12:29:31 PM PDT 24 Mar 12 12:29:32 PM PDT 24 386333166 ps
T1219 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2579578989 Mar 12 12:29:40 PM PDT 24 Mar 12 12:29:42 PM PDT 24 25828099 ps
T1220 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4145783791 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:34 PM PDT 24 129546760 ps
T1221 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.909190469 Mar 12 12:29:40 PM PDT 24 Mar 12 12:29:42 PM PDT 24 39738137 ps
T1222 /workspace/coverage/cover_reg_top/38.uart_intr_test.2293521630 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 62606467 ps
T1223 /workspace/coverage/cover_reg_top/17.uart_intr_test.1588104292 Mar 12 12:30:27 PM PDT 24 Mar 12 12:30:28 PM PDT 24 22010599 ps
T1224 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1839016445 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:16 PM PDT 24 58090054 ps
T1225 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3819140296 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:53 PM PDT 24 66098454 ps
T68 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2133219058 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:45 PM PDT 24 107449661 ps
T1226 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1718754047 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 1073678518 ps
T1227 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3815123642 Mar 12 12:29:36 PM PDT 24 Mar 12 12:29:37 PM PDT 24 111708663 ps
T1228 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2805340800 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:34 PM PDT 24 86597054 ps
T1229 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3209031344 Mar 12 12:29:39 PM PDT 24 Mar 12 12:29:41 PM PDT 24 179843686 ps
T1230 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3643901133 Mar 12 12:29:36 PM PDT 24 Mar 12 12:29:38 PM PDT 24 96800069 ps
T1231 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2758868013 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 54000915 ps
T1232 /workspace/coverage/cover_reg_top/27.uart_intr_test.3711681850 Mar 12 12:29:54 PM PDT 24 Mar 12 12:29:54 PM PDT 24 39635495 ps
T1233 /workspace/coverage/cover_reg_top/43.uart_intr_test.18137465 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:46 PM PDT 24 29279079 ps
T1234 /workspace/coverage/cover_reg_top/49.uart_intr_test.2742725694 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:50 PM PDT 24 23854737 ps
T1235 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3145295342 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:49 PM PDT 24 37804107 ps
T1236 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2068885107 Mar 12 12:29:35 PM PDT 24 Mar 12 12:29:37 PM PDT 24 509872832 ps
T1237 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3241853206 Mar 12 12:29:28 PM PDT 24 Mar 12 12:29:29 PM PDT 24 30431411 ps
T1238 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2973880626 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:51 PM PDT 24 19750667 ps
T1239 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4086617337 Mar 12 12:29:40 PM PDT 24 Mar 12 12:29:41 PM PDT 24 124910274 ps
T79 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2025223691 Mar 12 12:29:35 PM PDT 24 Mar 12 12:29:41 PM PDT 24 30230564 ps
T1240 /workspace/coverage/cover_reg_top/3.uart_intr_test.4033676940 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 53136221 ps
T1241 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3060367746 Mar 12 12:29:32 PM PDT 24 Mar 12 12:29:32 PM PDT 24 12445594 ps
T1242 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3284891060 Mar 12 12:29:42 PM PDT 24 Mar 12 12:29:43 PM PDT 24 49114455 ps
T1243 /workspace/coverage/cover_reg_top/21.uart_intr_test.2078122525 Mar 12 12:29:54 PM PDT 24 Mar 12 12:29:55 PM PDT 24 14413627 ps
T1244 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1567489101 Mar 12 12:29:31 PM PDT 24 Mar 12 12:29:33 PM PDT 24 117137454 ps
T1245 /workspace/coverage/cover_reg_top/31.uart_intr_test.1916261243 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:49 PM PDT 24 39917349 ps
T1246 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1287272229 Mar 12 12:29:34 PM PDT 24 Mar 12 12:29:36 PM PDT 24 76890631 ps
T1247 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3667494148 Mar 12 12:29:40 PM PDT 24 Mar 12 12:29:42 PM PDT 24 538266298 ps
T1248 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2500697085 Mar 12 12:29:26 PM PDT 24 Mar 12 12:29:29 PM PDT 24 485792600 ps
T1249 /workspace/coverage/cover_reg_top/23.uart_intr_test.3999292242 Mar 12 12:29:57 PM PDT 24 Mar 12 12:29:58 PM PDT 24 17607839 ps
T1250 /workspace/coverage/cover_reg_top/13.uart_tl_errors.4145698671 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:32 PM PDT 24 621454986 ps
T1251 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2444509481 Mar 12 12:29:30 PM PDT 24 Mar 12 12:29:31 PM PDT 24 185423353 ps
T1252 /workspace/coverage/cover_reg_top/48.uart_intr_test.1066796305 Mar 12 12:30:01 PM PDT 24 Mar 12 12:30:01 PM PDT 24 29440372 ps
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