Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.89	99.38	97.89	100.00		98.83	100.00	97.27

Total test records in report: 1259

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1253	/workspace/coverage/cover_reg_top/16.uart_intr_test.2907863156			Mar 12 12:29:34 PM PDT 24	Mar 12 12:29:34 PM PDT 24	46251923 ps
T80	/workspace/coverage/cover_reg_top/1.uart_csr_rw.1611532485			Mar 12 12:29:13 PM PDT 24	Mar 12 12:29:14 PM PDT 24	22303745 ps
T69	/workspace/coverage/cover_reg_top/9.uart_csr_rw.1683874363			Mar 12 12:29:30 PM PDT 24	Mar 12 12:29:31 PM PDT 24	42035524 ps
T1254	/workspace/coverage/cover_reg_top/7.uart_csr_rw.2305573694			Mar 12 12:29:53 PM PDT 24	Mar 12 12:29:54 PM PDT 24	14264913 ps
T1255	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4031775896			Mar 12 12:29:51 PM PDT 24	Mar 12 12:29:53 PM PDT 24	138554172 ps
T1256	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.687086201			Mar 12 12:29:31 PM PDT 24	Mar 12 12:29:33 PM PDT 24	87885887 ps
T1257	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3591302474			Mar 12 12:29:30 PM PDT 24	Mar 12 12:29:36 PM PDT 24	23094892 ps
T1258	/workspace/coverage/cover_reg_top/4.uart_intr_test.2229787882			Mar 12 12:29:29 PM PDT 24	Mar 12 12:29:29 PM PDT 24	97712610 ps
T1259	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2906704261			Mar 12 12:29:12 PM PDT 24	Mar 12 12:29:13 PM PDT 24	44055879 ps

Test location	/workspace/coverage/default/6.uart_fifo_reset.3386960926
Short name	T1
Test name
Test status
Simulation time	94510694882 ps
CPU time	76.58 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:08:28 PM PDT 24
Peak memory	199764 kb
Host	smart-c8123ecd-ed51-4858-a929-f99904023e40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386960926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3386960926
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/68.uart_stress_all_with_rand_reset.3825526934
Short name	T11
Test name
Test status
Simulation time	293772533118 ps
CPU time	831.52 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:22:54 PM PDT 24
Peak memory	225024 kb
Host	smart-09217df2-032a-4a7e-83a8-7a9963aa302d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825526934 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3825526934
Directory	/workspace/68.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.1945984781
Short name	T7
Test name
Test status
Simulation time	139301295476 ps
CPU time	1001.85 seconds
Started	Mar 12 01:06:52 PM PDT 24
Finished	Mar 12 01:23:36 PM PDT 24
Peak memory	200076 kb
Host	smart-422516ac-7b33-41f0-8c92-b8ee8daca31c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1945984781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1945984781
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/18.uart_stress_all.1661474174
Short name	T123
Test name
Test status
Simulation time	689716838602 ps
CPU time	826.24 seconds
Started	Mar 12 01:07:39 PM PDT 24
Finished	Mar 12 01:21:26 PM PDT 24
Peak memory	208520 kb
Host	smart-b067cb42-84df-422a-97a5-e2cf66dfd157
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661474174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1661474174
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/default/70.uart_stress_all_with_rand_reset.4281279226
Short name	T12
Test name
Test status
Simulation time	211009916402 ps
CPU time	1026.31 seconds
Started	Mar 12 01:09:05 PM PDT 24
Finished	Mar 12 01:26:13 PM PDT 24
Peak memory	226368 kb
Host	smart-96d07dce-25e2-40fc-a422-ab729e3270e4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281279226 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4281279226
Directory	/workspace/70.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_stress_all.1751240165
Short name	T19
Test name
Test status
Simulation time	401923672270 ps
CPU time	342.28 seconds
Started	Mar 12 01:08:40 PM PDT 24
Finished	Mar 12 01:14:25 PM PDT 24
Peak memory	200136 kb
Host	smart-48706fb3-f3bd-4a8d-abdb-8f30cd142ff2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751240165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1751240165
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_stress_all.3291055815
Short name	T13
Test name
Test status
Simulation time	157686743714 ps
CPU time	91.39 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:09:34 PM PDT 24
Peak memory	200112 kb
Host	smart-474e4089-04ca-492e-8d2b-8b9db8f2b039
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291055815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3291055815
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/2.uart_stress_all.2626128198
Short name	T216
Test name
Test status
Simulation time	209136057623 ps
CPU time	416.43 seconds
Started	Mar 12 01:06:51 PM PDT 24
Finished	Mar 12 01:13:50 PM PDT 24
Peak memory	200356 kb
Host	smart-55bf0b8a-e1c4-4f5b-90ab-689ec07ebef7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626128198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2626128198
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.1915861835
Short name	T35
Test name
Test status
Simulation time	69912496 ps
CPU time	0.96 seconds
Started	Mar 12 01:06:54 PM PDT 24
Finished	Mar 12 01:06:57 PM PDT 24
Peak memory	217420 kb
Host	smart-9a6de37b-c9c7-40f4-8d2c-841634e4f7d8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915861835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1915861835
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/12.uart_stress_all.2447824989
Short name	T31
Test name
Test status
Simulation time	90183992011 ps
CPU time	164.95 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:09:56 PM PDT 24
Peak memory	216740 kb
Host	smart-dd69ac63-61bc-4df0-8c57-f9f2eaf46d94
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447824989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2447824989
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_stress_all.96295297
Short name	T124
Test name
Test status
Simulation time	479548306728 ps
CPU time	209.51 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:10:41 PM PDT 24
Peak memory	200096 kb
Host	smart-0dbda3e4-b2b8-4ea2-a5d0-f8251fc9c804
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96295297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.96295297
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.711017774
Short name	T47
Test name
Test status
Simulation time	76694930341 ps
CPU time	141.58 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:11:24 PM PDT 24
Peak memory	200192 kb
Host	smart-7335ab47-218f-4514-9f3a-a1e1c8f94d10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711017774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.711017774
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_stress_all_with_rand_reset.1250314838
Short name	T40
Test name
Test status
Simulation time	41628771425 ps
CPU time	558.02 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:17:25 PM PDT 24
Peak memory	215964 kb
Host	smart-23373240-3cce-4042-97e3-580de3033e81
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250314838 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1250314838
Directory	/workspace/34.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.uart_intr.100987969
Short name	T408
Test name
Test status
Simulation time	67902102710 ps
CPU time	32.71 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	199888 kb
Host	smart-651db998-1ac9-498a-8d1d-5d86cab1e576
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100987969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.100987969
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.461676761
Short name	T94
Test name
Test status
Simulation time	106228569 ps
CPU time	1.22 seconds
Started	Mar 12 12:29:28 PM PDT 24
Finished	Mar 12 12:29:29 PM PDT 24
Peak memory	199256 kb
Host	smart-8b8d3035-5e35-4f6e-91ac-408daad8ce76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461676761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.461676761
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/56.uart_stress_all_with_rand_reset.1613857501
Short name	T26
Test name
Test status
Simulation time	231245785122 ps
CPU time	587.65 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:18:51 PM PDT 24
Peak memory	224892 kb
Host	smart-c6a5f2d3-7733-457d-9285-54a84c73ed18
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613857501 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1613857501
Directory	/workspace/56.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.uart_alert_test.3503935792
Short name	T483
Test name
Test status
Simulation time	103941496 ps
CPU time	0.58 seconds
Started	Mar 12 01:07:36 PM PDT 24
Finished	Mar 12 01:07:37 PM PDT 24
Peak memory	195488 kb
Host	smart-253ba89e-0da5-4514-bce3-55c728c93a80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503935792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3503935792
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.100859908
Short name	T65
Test name
Test status
Simulation time	34827230 ps
CPU time	0.62 seconds
Started	Mar 12 12:29:38 PM PDT 24
Finished	Mar 12 12:29:39 PM PDT 24
Peak memory	195724 kb
Host	smart-0a9708f4-f5d3-47ec-afe8-c15fa7889fb0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100859908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.100859908
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/default/33.uart_stress_all_with_rand_reset.1143037010
Short name	T24
Test name
Test status
Simulation time	88957889023 ps
CPU time	279.92 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:12:45 PM PDT 24
Peak memory	216608 kb
Host	smart-ef618033-0577-432b-a5cf-589fc2eb8d27
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143037010 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1143037010
Directory	/workspace/33.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.1964131341
Short name	T90
Test name
Test status
Simulation time	130189348353 ps
CPU time	33.91 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:48 PM PDT 24
Peak memory	200100 kb
Host	smart-b3db7756-c710-4be8-adbd-6d30663d3fc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964131341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1964131341
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_stress_all.2592431207
Short name	T18
Test name
Test status
Simulation time	260995336073 ps
CPU time	668.43 seconds
Started	Mar 12 01:06:53 PM PDT 24
Finished	Mar 12 01:18:04 PM PDT 24
Peak memory	200192 kb
Host	smart-81917122-1432-4043-b097-fc3bfc06a3ee
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592431207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2592431207
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.800412353
Short name	T127
Test name
Test status
Simulation time	35566648138 ps
CPU time	38.92 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:10:02 PM PDT 24
Peak memory	200092 kb
Host	smart-cc7719f8-79d8-48d6-88ec-3dbaa20145a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800412353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.800412353
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.573312334
Short name	T134
Test name
Test status
Simulation time	174162573743 ps
CPU time	161.35 seconds
Started	Mar 12 01:09:36 PM PDT 24
Finished	Mar 12 01:12:18 PM PDT 24
Peak memory	200188 kb
Host	smart-1734d3f9-433b-4b34-8b06-5c50f8a29cfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573312334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.573312334
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3491848723
Short name	T86
Test name
Test status
Simulation time	15253598 ps
CPU time	0.68 seconds
Started	Mar 12 12:29:41 PM PDT 24
Finished	Mar 12 12:29:42 PM PDT 24
Peak memory	195032 kb
Host	smart-3a65d4d1-1fba-4b9a-b926-86bdb78d08f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491848723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3491848723
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.24029534
Short name	T337
Test name
Test status
Simulation time	248448469990 ps
CPU time	38.43 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:08:45 PM PDT 24
Peak memory	200052 kb
Host	smart-0401ea33-42af-46ec-bc34-3dd5a8835fad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24029534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.24029534
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.3192372821
Short name	T55
Test name
Test status
Simulation time	78761292660 ps
CPU time	203.8 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:10:36 PM PDT 24
Peak memory	199864 kb
Host	smart-c46b0786-35af-4ba0-9d9e-d14642c2c491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192372821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3192372821
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.1051240308
Short name	T163
Test name
Test status
Simulation time	302131866892 ps
CPU time	30.39 seconds
Started	Mar 12 01:09:39 PM PDT 24
Finished	Mar 12 01:10:09 PM PDT 24
Peak memory	200136 kb
Host	smart-941a5a51-cf56-4fc9-b4ff-949e29f87fde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051240308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1051240308
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_stress_all.1096521191
Short name	T149
Test name
Test status
Simulation time	1016544539811 ps
CPU time	145.37 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:10:16 PM PDT 24
Peak memory	216668 kb
Host	smart-c9abba4a-453c-4ce8-8f8e-2e2cc1765886
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096521191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1096521191
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.2460107084
Short name	T136
Test name
Test status
Simulation time	34617340137 ps
CPU time	28.93 seconds
Started	Mar 12 01:09:22 PM PDT 24
Finished	Mar 12 01:09:51 PM PDT 24
Peak memory	200136 kb
Host	smart-d2bb2ffb-1016-4071-9f2b-797f7d5c6390
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460107084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2460107084
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.1369480771
Short name	T215
Test name
Test status
Simulation time	343349939315 ps
CPU time	40.39 seconds
Started	Mar 12 01:09:56 PM PDT 24
Finished	Mar 12 01:10:37 PM PDT 24
Peak memory	199676 kb
Host	smart-2f415411-24d8-4197-8636-549293350693
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369480771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1369480771
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.2310102518
Short name	T187
Test name
Test status
Simulation time	70428011811 ps
CPU time	74.25 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:09:02 PM PDT 24
Peak memory	199908 kb
Host	smart-7bc102fb-1cdc-4d4d-96d9-f321abc70924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310102518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2310102518
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_noise_filter.3020808907
Short name	T162
Test name
Test status
Simulation time	163738758504 ps
CPU time	219.38 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:10:52 PM PDT 24
Peak memory	199952 kb
Host	smart-331fa566-4a75-4497-ac91-576c4ae7ce64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020808907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3020808907
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.3981471772
Short name	T48
Test name
Test status
Simulation time	19697039287 ps
CPU time	32.64 seconds
Started	Mar 12 01:09:27 PM PDT 24
Finished	Mar 12 01:10:01 PM PDT 24
Peak memory	200124 kb
Host	smart-ca3c2fe6-9d23-4d54-abef-9d014b536078
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981471772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3981471772
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.793832847
Short name	T147
Test name
Test status
Simulation time	186987844286 ps
CPU time	281.58 seconds
Started	Mar 12 01:09:47 PM PDT 24
Finished	Mar 12 01:14:29 PM PDT 24
Peak memory	200124 kb
Host	smart-b2c754a3-4b1a-4991-abd2-e1feb8385081
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793832847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.793832847
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.45231460
Short name	T97
Test name
Test status
Simulation time	111082997 ps
CPU time	1.39 seconds
Started	Mar 12 12:29:44 PM PDT 24
Finished	Mar 12 12:29:45 PM PDT 24
Peak memory	199184 kb
Host	smart-a110bf0f-17a8-484b-920e-6481fef53c10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45231460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.45231460
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.1259733280
Short name	T266
Test name
Test status
Simulation time	27859940562 ps
CPU time	49.73 seconds
Started	Mar 12 01:09:24 PM PDT 24
Finished	Mar 12 01:10:15 PM PDT 24
Peak memory	200008 kb
Host	smart-d0398b0a-af1b-4ace-b678-d92c4fdf3e95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259733280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1259733280
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.1340126327
Short name	T377
Test name
Test status
Simulation time	71334415604 ps
CPU time	102.36 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:11:05 PM PDT 24
Peak memory	200096 kb
Host	smart-901da256-2614-43c4-b420-7e07a5551bf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340126327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1340126327
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.1866716371
Short name	T197
Test name
Test status
Simulation time	69488601037 ps
CPU time	29.97 seconds
Started	Mar 12 01:09:57 PM PDT 24
Finished	Mar 12 01:10:28 PM PDT 24
Peak memory	200076 kb
Host	smart-700b43cc-aaaf-45d9-8b4c-9940d600d088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866716371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1866716371
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.70071276
Short name	T241
Test name
Test status
Simulation time	137151900099 ps
CPU time	60.4 seconds
Started	Mar 12 01:10:09 PM PDT 24
Finished	Mar 12 01:11:10 PM PDT 24
Peak memory	200080 kb
Host	smart-008b860c-2ebd-4b67-aeef-a608cf0759c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70071276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.70071276
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_stress_all.3227538580
Short name	T278
Test name
Test status
Simulation time	304342976191 ps
CPU time	1539.58 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:32:45 PM PDT 24
Peak memory	200096 kb
Host	smart-dad55225-eea1-4783-9534-d9e0fa203021
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227538580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3227538580
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.2905886044
Short name	T219
Test name
Test status
Simulation time	63603455081 ps
CPU time	6.88 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:09:32 PM PDT 24
Peak memory	199844 kb
Host	smart-c9f4fe39-1641-4a80-b943-b508bc5a34ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905886044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2905886044
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.2774549736
Short name	T139
Test name
Test status
Simulation time	27082972796 ps
CPU time	11.39 seconds
Started	Mar 12 01:09:27 PM PDT 24
Finished	Mar 12 01:09:38 PM PDT 24
Peak memory	199864 kb
Host	smart-4e9f1378-181d-47ee-89e6-31d4a27bb7b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774549736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2774549736
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.246235195
Short name	T201
Test name
Test status
Simulation time	121150533635 ps
CPU time	57.4 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:34 PM PDT 24
Peak memory	200140 kb
Host	smart-a9ce58ab-bbdf-448e-af07-b8170809d214
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246235195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.246235195
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.1574232292
Short name	T371
Test name
Test status
Simulation time	79603613718 ps
CPU time	77.39 seconds
Started	Mar 12 01:09:43 PM PDT 24
Finished	Mar 12 01:11:01 PM PDT 24
Peak memory	200132 kb
Host	smart-2ee9d3b1-9518-48fe-9bc4-af6c52611399
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574232292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1574232292
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.3282863006
Short name	T1001
Test name
Test status
Simulation time	11801293573 ps
CPU time	17.36 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:07:55 PM PDT 24
Peak memory	200088 kb
Host	smart-a0cea225-4999-4caa-b8bd-f9359a8e1e98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282863006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3282863006
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_stress_all_with_rand_reset.820207894
Short name	T59
Test name
Test status
Simulation time	290626373942 ps
CPU time	733.46 seconds
Started	Mar 12 01:09:16 PM PDT 24
Finished	Mar 12 01:21:30 PM PDT 24
Peak memory	224976 kb
Host	smart-5cf0963c-293b-443c-84f5-6aebe21e7091
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820207894 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.820207894
Directory	/workspace/81.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.1362541349
Short name	T342
Test name
Test status
Simulation time	125823108213 ps
CPU time	100.88 seconds
Started	Mar 12 01:06:41 PM PDT 24
Finished	Mar 12 01:08:22 PM PDT 24
Peak memory	200108 kb
Host	smart-0fc96f04-8730-4b7b-8506-6a5489d76498
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362541349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1362541349
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.1684858372
Short name	T311
Test name
Test status
Simulation time	38675355081 ps
CPU time	17.7 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:23 PM PDT 24
Peak memory	199920 kb
Host	smart-f8898f72-6cd2-4e99-a0ea-1dd8a2f8e1d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684858372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1684858372
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_stress_all.641782554
Short name	T151
Test name
Test status
Simulation time	178776651813 ps
CPU time	228.08 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:11:01 PM PDT 24
Peak memory	200104 kb
Host	smart-e7e38d2b-9e8a-49a1-b7ef-21a29e8fcb6f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641782554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.641782554
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.3672258914
Short name	T275
Test name
Test status
Simulation time	142508348050 ps
CPU time	116.07 seconds
Started	Mar 12 01:09:14 PM PDT 24
Finished	Mar 12 01:11:10 PM PDT 24
Peak memory	199904 kb
Host	smart-9d50f8bd-8348-4f7d-bbfb-4046a567cf4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672258914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3672258914
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.1509147169
Short name	T293
Test name
Test status
Simulation time	277642613651 ps
CPU time	43.43 seconds
Started	Mar 12 01:09:24 PM PDT 24
Finished	Mar 12 01:10:07 PM PDT 24
Peak memory	200004 kb
Host	smart-599bd5b6-7ae1-42de-93a9-b587ef6de80b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1509147169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1509147169
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.99212068
Short name	T224
Test name
Test status
Simulation time	63091138417 ps
CPU time	24.06 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:09:47 PM PDT 24
Peak memory	200148 kb
Host	smart-83f2e777-6197-4e68-93ae-aea51c8b2312
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99212068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.99212068
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.2276820709
Short name	T257
Test name
Test status
Simulation time	52519201440 ps
CPU time	79.55 seconds
Started	Mar 12 01:07:35 PM PDT 24
Finished	Mar 12 01:08:54 PM PDT 24
Peak memory	200096 kb
Host	smart-3b44e429-0e37-4662-94a6-4a4042e75abd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276820709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2276820709
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.4055062230
Short name	T212
Test name
Test status
Simulation time	81024707300 ps
CPU time	35.44 seconds
Started	Mar 12 01:09:43 PM PDT 24
Finished	Mar 12 01:10:18 PM PDT 24
Peak memory	200080 kb
Host	smart-aa802a3c-a641-4705-ac3a-b8419d505451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055062230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4055062230
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_stress_all_with_rand_reset.3411856258
Short name	T294
Test name
Test status
Simulation time	95239183693 ps
CPU time	1897.69 seconds
Started	Mar 12 01:09:05 PM PDT 24
Finished	Mar 12 01:40:43 PM PDT 24
Peak memory	228960 kb
Host	smart-34aae188-3438-4c19-bf26-d6258d6c8a4b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411856258 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3411856258
Directory	/workspace/57.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.2497792429
Short name	T180
Test name
Test status
Simulation time	262341046873 ps
CPU time	25.32 seconds
Started	Mar 12 01:09:13 PM PDT 24
Finished	Mar 12 01:09:38 PM PDT 24
Peak memory	200144 kb
Host	smart-16d894d2-1679-46cd-aa80-11427b84c682
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497792429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2497792429
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.421202473
Short name	T145
Test name
Test status
Simulation time	43424460997 ps
CPU time	32.11 seconds
Started	Mar 12 01:06:36 PM PDT 24
Finished	Mar 12 01:07:09 PM PDT 24
Peak memory	199572 kb
Host	smart-4380e33d-53de-4a70-8b86-3e79ffbaaeb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421202473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.421202473
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.3934434347
Short name	T229
Test name
Test status
Simulation time	33215134352 ps
CPU time	13.74 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:25 PM PDT 24
Peak memory	199616 kb
Host	smart-008de872-6e85-4b49-9036-96a596551b79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934434347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3934434347
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.3993732449
Short name	T209
Test name
Test status
Simulation time	31670629378 ps
CPU time	25.51 seconds
Started	Mar 12 01:09:15 PM PDT 24
Finished	Mar 12 01:09:41 PM PDT 24
Peak memory	200108 kb
Host	smart-450fe36f-04b1-45cc-8882-ddb5cac554c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993732449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3993732449
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_intr.566904865
Short name	T27
Test name
Test status
Simulation time	63158046583 ps
CPU time	121.62 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:09:13 PM PDT 24
Peak memory	200032 kb
Host	smart-1bd169de-5712-4149-b444-e3865b66c669
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566904865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.566904865
Directory	/workspace/12.uart_intr/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.4222333108
Short name	T251
Test name
Test status
Simulation time	84395375932 ps
CPU time	63.53 seconds
Started	Mar 12 01:09:26 PM PDT 24
Finished	Mar 12 01:10:30 PM PDT 24
Peak memory	198820 kb
Host	smart-0a872a6d-d37c-425c-a734-d82adf72776b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222333108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4222333108
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.4223988136
Short name	T188
Test name
Test status
Simulation time	77835082397 ps
CPU time	36.72 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:14 PM PDT 24
Peak memory	200120 kb
Host	smart-8255183b-04d0-4c77-bf36-21819781df15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223988136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4223988136
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.210165225
Short name	T263
Test name
Test status
Simulation time	111647167223 ps
CPU time	195.1 seconds
Started	Mar 12 01:09:33 PM PDT 24
Finished	Mar 12 01:12:48 PM PDT 24
Peak memory	200056 kb
Host	smart-7ac6e3c0-8649-452a-9d4e-8bea7f859ec3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210165225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.210165225
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.1722771877
Short name	T328
Test name
Test status
Simulation time	91076247516 ps
CPU time	68.79 seconds
Started	Mar 12 01:09:46 PM PDT 24
Finished	Mar 12 01:10:55 PM PDT 24
Peak memory	200124 kb
Host	smart-043a4c93-4548-4321-bd84-943c7ec5543f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722771877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1722771877
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_stress_all.796009377
Short name	T290
Test name
Test status
Simulation time	225597990352 ps
CPU time	209.83 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:11:15 PM PDT 24
Peak memory	208564 kb
Host	smart-6bf941e5-a227-46b0-a5c8-8270dfd53884
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796009377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.796009377
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.3678152260
Short name	T359
Test name
Test status
Simulation time	23297364409 ps
CPU time	38.29 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	199988 kb
Host	smart-4b60bf2d-7065-409f-839a-c7f911fec7fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678152260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3678152260
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.3577644326
Short name	T154
Test name
Test status
Simulation time	79329752033 ps
CPU time	118.87 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:11:53 PM PDT 24
Peak memory	200128 kb
Host	smart-33249587-1e7a-4bec-b3ee-15e7de4b3f57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577644326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3577644326
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.1365272395
Short name	T387
Test name
Test status
Simulation time	243710191672 ps
CPU time	29.41 seconds
Started	Mar 12 01:08:01 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	200076 kb
Host	smart-9a96b99c-76fa-42f4-b3c8-3fec5941c32b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365272395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1365272395
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.499480764
Short name	T382
Test name
Test status
Simulation time	141340793719 ps
CPU time	123.62 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:12:10 PM PDT 24
Peak memory	200148 kb
Host	smart-d0671bc3-6a2e-4109-b5d4-8eeada154cff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499480764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.499480764
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.3103873886
Short name	T222
Test name
Test status
Simulation time	27677009765 ps
CPU time	14.56 seconds
Started	Mar 12 01:06:48 PM PDT 24
Finished	Mar 12 01:07:04 PM PDT 24
Peak memory	200144 kb
Host	smart-2391175e-b0ba-4299-a4f0-157c6196f052
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103873886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3103873886
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.3621435905
Short name	T253
Test name
Test status
Simulation time	129787694698 ps
CPU time	47.5 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:47 PM PDT 24
Peak memory	199884 kb
Host	smart-5df57c32-f0e1-4189-b80f-f40b8b28eaca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621435905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3621435905
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.3367964285
Short name	T261
Test name
Test status
Simulation time	225084759418 ps
CPU time	88.49 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:10:19 PM PDT 24
Peak memory	199596 kb
Host	smart-77c2d8ff-0fc3-496a-beb0-ef566f205061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367964285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3367964285
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2420968024
Short name	T390
Test name
Test status
Simulation time	173061626 ps
CPU time	1.06 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	198812 kb
Host	smart-94ad4866-a90b-47c1-8d3c-aaea04f93245
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420968024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2420968024
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.2929081101
Short name	T297
Test name
Test status
Simulation time	24470230328 ps
CPU time	38.52 seconds
Started	Mar 12 01:07:04 PM PDT 24
Finished	Mar 12 01:07:43 PM PDT 24
Peak memory	200116 kb
Host	smart-594df558-49f7-47f1-8007-4d7fde345872
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929081101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2929081101
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_stress_all_with_rand_reset.3118857723
Short name	T355
Test name
Test status
Simulation time	307680937709 ps
CPU time	771.82 seconds
Started	Mar 12 01:06:54 PM PDT 24
Finished	Mar 12 01:19:48 PM PDT 24
Peak memory	216584 kb
Host	smart-e6e2de3c-2d0b-4dad-843e-fa56c0e15173
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118857723 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3118857723
Directory	/workspace/1.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.1640135841
Short name	T389
Test name
Test status
Simulation time	167096644113 ps
CPU time	79.26 seconds
Started	Mar 12 01:09:15 PM PDT 24
Finished	Mar 12 01:10:35 PM PDT 24
Peak memory	200096 kb
Host	smart-4b6f04cc-ce29-4766-b8df-a698cd4136e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640135841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1640135841
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.1971036674
Short name	T309
Test name
Test status
Simulation time	114684963559 ps
CPU time	128.87 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:11:32 PM PDT 24
Peak memory	200116 kb
Host	smart-6adae981-abae-4191-9cd5-d1c4d42e21c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971036674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1971036674
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.2418356934
Short name	T238
Test name
Test status
Simulation time	6528050079 ps
CPU time	6.54 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:09:29 PM PDT 24
Peak memory	200108 kb
Host	smart-e3a0b14c-6ae7-4d96-8c4b-b7a2ad4d3297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2418356934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2418356934
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.2879967318
Short name	T249
Test name
Test status
Simulation time	243143239195 ps
CPU time	144.52 seconds
Started	Mar 12 01:09:24 PM PDT 24
Finished	Mar 12 01:11:48 PM PDT 24
Peak memory	200068 kb
Host	smart-8db694d1-49ed-4ede-a2a5-c867b9a58497
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879967318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2879967318
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.29340427
Short name	T194
Test name
Test status
Simulation time	8579062233 ps
CPU time	31.75 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:09:57 PM PDT 24
Peak memory	200116 kb
Host	smart-d156a1d6-b422-4fb4-bec9-bb9c0a39e598
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29340427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.29340427
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_perf.1804792263
Short name	T288
Test name
Test status
Simulation time	13111112858 ps
CPU time	210.79 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:10:34 PM PDT 24
Peak memory	199932 kb
Host	smart-22bbaf91-e939-419d-8ca5-26df60923547
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1804792263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1804792263
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.1935310732
Short name	T281
Test name
Test status
Simulation time	36928110986 ps
CPU time	64.14 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:41 PM PDT 24
Peak memory	200052 kb
Host	smart-566eced7-9ffc-43f8-94d5-49d18bc9ee6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935310732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1935310732
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.1361891051
Short name	T302
Test name
Test status
Simulation time	19515405095 ps
CPU time	8.72 seconds
Started	Mar 12 01:07:17 PM PDT 24
Finished	Mar 12 01:07:27 PM PDT 24
Peak memory	199272 kb
Host	smart-a27367cd-2a0e-43c8-a276-fc374b1356e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1361891051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1361891051
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.4072941928
Short name	T129
Test name
Test status
Simulation time	83002604077 ps
CPU time	25.41 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:00 PM PDT 24
Peak memory	199980 kb
Host	smart-d36dd646-cf22-409c-b574-030c6e125712
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072941928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4072941928
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.223298034
Short name	T376
Test name
Test status
Simulation time	266347338052 ps
CPU time	72.61 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:08:49 PM PDT 24
Peak memory	200076 kb
Host	smart-6a79acaa-da83-44aa-b1d8-a6ebda1a3e86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223298034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.223298034
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.1604195673
Short name	T276
Test name
Test status
Simulation time	143909446539 ps
CPU time	275.86 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:12:23 PM PDT 24
Peak memory	200132 kb
Host	smart-4b6c7062-5b8b-42c6-8332-010684e06ac7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604195673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1604195673
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.2266168190
Short name	T298
Test name
Test status
Simulation time	107480810732 ps
CPU time	42.39 seconds
Started	Mar 12 01:07:39 PM PDT 24
Finished	Mar 12 01:08:21 PM PDT 24
Peak memory	199900 kb
Host	smart-889fcf8e-57d9-4443-bd8a-4712a95a7e5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266168190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2266168190
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_stress_all.3845922402
Short name	T227
Test name
Test status
Simulation time	106812454238 ps
CPU time	85.69 seconds
Started	Mar 12 01:07:34 PM PDT 24
Finished	Mar 12 01:09:00 PM PDT 24
Peak memory	200120 kb
Host	smart-2f122cf2-cb14-4a64-8c3f-d548ab06234b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845922402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3845922402
Directory	/workspace/21.uart_stress_all/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.1304062656
Short name	T372
Test name
Test status
Simulation time	186085473423 ps
CPU time	68.9 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:08:47 PM PDT 24
Peak memory	200120 kb
Host	smart-506e33dc-1f5d-4297-81ca-3b9216f0ca78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304062656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1304062656
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_perf.15287227
Short name	T223
Test name
Test status
Simulation time	13624158776 ps
CPU time	172.9 seconds
Started	Mar 12 01:07:46 PM PDT 24
Finished	Mar 12 01:10:39 PM PDT 24
Peak memory	200064 kb
Host	smart-659b2991-ff23-45ce-8754-31cc2ac4b15e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=15287227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.15287227
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.2496128656
Short name	T121
Test name
Test status
Simulation time	15842374768 ps
CPU time	26.55 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:10:11 PM PDT 24
Peak memory	200064 kb
Host	smart-60d30a39-b791-4727-84e4-c9117016500c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496128656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2496128656
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.1423204598
Short name	T296
Test name
Test status
Simulation time	7700921732 ps
CPU time	5.83 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:09:50 PM PDT 24
Peak memory	199480 kb
Host	smart-53797d1b-7910-4139-97aa-55706a5ff75f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423204598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1423204598
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.710669829
Short name	T357
Test name
Test status
Simulation time	191896215256 ps
CPU time	331.93 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:15:26 PM PDT 24
Peak memory	200168 kb
Host	smart-8988f8ac-2475-429c-9682-cf1668935865
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710669829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.710669829
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.777907217
Short name	T161
Test name
Test status
Simulation time	145722063388 ps
CPU time	230.08 seconds
Started	Mar 12 01:09:56 PM PDT 24
Finished	Mar 12 01:13:46 PM PDT 24
Peak memory	199612 kb
Host	smart-4e43031b-0deb-4e78-8e71-72156f9a9f3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777907217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.777907217
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_stress_all.2838860086
Short name	T292
Test name
Test status
Simulation time	35995395256 ps
CPU time	163.45 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:10:33 PM PDT 24
Peak memory	200088 kb
Host	smart-5155aff0-258f-4178-b739-3b633f7d08d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838860086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2838860086
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/263.uart_fifo_reset.2929824923
Short name	T316
Test name
Test status
Simulation time	39718780823 ps
CPU time	18.42 seconds
Started	Mar 12 01:09:59 PM PDT 24
Finished	Mar 12 01:10:17 PM PDT 24
Peak memory	200104 kb
Host	smart-1520e3b3-ed3e-4b0a-b180-5eb6b041b340
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929824923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2929824923
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.1659606932
Short name	T138
Test name
Test status
Simulation time	15122242203 ps
CPU time	22.28 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:17 PM PDT 24
Peak memory	200068 kb
Host	smart-1b43c13e-bb80-4e2a-9529-de931ea44687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659606932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1659606932
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.936540771
Short name	T363
Test name
Test status
Simulation time	113574165991 ps
CPU time	157.72 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:12:33 PM PDT 24
Peak memory	200116 kb
Host	smart-630a9c8e-8d1c-4296-9719-0ebf70b5c87f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936540771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.936540771
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.2583817696
Short name	T358
Test name
Test status
Simulation time	40450351214 ps
CPU time	9.56 seconds
Started	Mar 12 01:10:05 PM PDT 24
Finished	Mar 12 01:10:15 PM PDT 24
Peak memory	199612 kb
Host	smart-c32d6b00-3d6d-4924-b16b-a43862c55988
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583817696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2583817696
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.504251929
Short name	T301
Test name
Test status
Simulation time	46356584500 ps
CPU time	202.12 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:11:22 PM PDT 24
Peak memory	199896 kb
Host	smart-44e04d3a-ed13-40b3-b014-99c95e47141c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=504251929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.504251929
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_perf.1157894810
Short name	T299
Test name
Test status
Simulation time	7617543849 ps
CPU time	346.56 seconds
Started	Mar 12 01:08:04 PM PDT 24
Finished	Mar 12 01:13:51 PM PDT 24
Peak memory	200184 kb
Host	smart-e7d97dbe-b54e-49db-98e7-0fbff92fdd1b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1157894810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1157894810
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.637547002
Short name	T25
Test name
Test status
Simulation time	214360794547 ps
CPU time	82.87 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:09:26 PM PDT 24
Peak memory	200116 kb
Host	smart-ad3ece24-f699-4a23-a241-befcaf3a1d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637547002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.637547002
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.3431515316
Short name	T140
Test name
Test status
Simulation time	194339195091 ps
CPU time	139.9 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:10:37 PM PDT 24
Peak memory	200076 kb
Host	smart-c037c7a2-a4a7-42b1-b6bc-ae7ddbb4ae48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431515316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3431515316
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.4224766347
Short name	T300
Test name
Test status
Simulation time	62045655835 ps
CPU time	30.33 seconds
Started	Mar 12 01:06:58 PM PDT 24
Finished	Mar 12 01:07:28 PM PDT 24
Peak memory	199980 kb
Host	smart-f6545bb9-b384-4159-bbcd-3108920d33f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224766347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4224766347
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.1122739455
Short name	T360
Test name
Test status
Simulation time	54658099510 ps
CPU time	49.11 seconds
Started	Mar 12 01:06:57 PM PDT 24
Finished	Mar 12 01:07:46 PM PDT 24
Peak memory	200092 kb
Host	smart-49a4fe68-361b-48f9-a665-c8b2228d0513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122739455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1122739455
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_perf.3587959940
Short name	T272
Test name
Test status
Simulation time	13426443766 ps
CPU time	775.31 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:21:34 PM PDT 24
Peak memory	200116 kb
Host	smart-38f7c153-fddf-4ee3-9b98-735cdb8d1268
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3587959940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3587959940
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.3467223356
Short name	T295
Test name
Test status
Simulation time	151414763003 ps
CPU time	64.04 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:09:39 PM PDT 24
Peak memory	200112 kb
Host	smart-c834ef49-5e2d-4b17-99fc-5bb5d6f8afd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467223356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3467223356
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_stress_all_with_rand_reset.2922473627
Short name	T438
Test name
Test status
Simulation time	80856906407 ps
CPU time	186.2 seconds
Started	Mar 12 01:08:51 PM PDT 24
Finished	Mar 12 01:11:57 PM PDT 24
Peak memory	208468 kb
Host	smart-a9580c15-8fea-418d-a516-0a589164fda1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922473627 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2922473627
Directory	/workspace/48.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.1125100620
Short name	T324
Test name
Test status
Simulation time	19897247314 ps
CPU time	34.58 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:09:39 PM PDT 24
Peak memory	200040 kb
Host	smart-e3d3f1ae-ff76-4be5-a320-4e7884c1246f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125100620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1125100620
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.3942180198
Short name	T383
Test name
Test status
Simulation time	157917095593 ps
CPU time	81.81 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:10:23 PM PDT 24
Peak memory	200032 kb
Host	smart-822019e7-5505-4897-8ca0-c166bd70f99d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942180198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3942180198
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.3877284470
Short name	T341
Test name
Test status
Simulation time	187003885752 ps
CPU time	21.99 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:24 PM PDT 24
Peak memory	200116 kb
Host	smart-c8401e75-b2ff-4c49-868e-ae0797c33ecf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877284470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3877284470
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.2029575206
Short name	T277
Test name
Test status
Simulation time	122623548072 ps
CPU time	104.9 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:08:50 PM PDT 24
Peak memory	199444 kb
Host	smart-b2338298-26ca-4f7f-a023-496a21b13a2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029575206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2029575206
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_stress_all.4073451309
Short name	T289
Test name
Test status
Simulation time	105731597038 ps
CPU time	367.97 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:13:18 PM PDT 24
Peak memory	200088 kb
Host	smart-ca3a1831-1851-4ec6-a8d8-2c62613de739
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073451309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4073451309
Directory	/workspace/8.uart_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.289615060
Short name	T60
Test name
Test status
Simulation time	16785778 ps
CPU time	0.75 seconds
Started	Mar 12 12:29:19 PM PDT 24
Finished	Mar 12 12:29:20 PM PDT 24
Peak memory	196952 kb
Host	smart-f40e1378-4cd7-4d5c-a42e-7c58ee9d0d70
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289615060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.289615060
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1768722533
Short name	T1197
Test name
Test status
Simulation time	214465313 ps
CPU time	2.27 seconds
Started	Mar 12 12:29:16 PM PDT 24
Finished	Mar 12 12:29:19 PM PDT 24
Peak memory	198184 kb
Host	smart-e8eb07ea-dc3f-4796-a1cb-65a6eb5beb36
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768722533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1768722533
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2906704261
Short name	T1259
Test name
Test status
Simulation time	44055879 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:12 PM PDT 24
Finished	Mar 12 12:29:13 PM PDT 24
Peak memory	195736 kb
Host	smart-144a4e2a-248e-464e-91ac-f7caa3726dd4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906704261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2906704261
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3625635806
Short name	T1183
Test name
Test status
Simulation time	22047367 ps
CPU time	1.02 seconds
Started	Mar 12 12:29:18 PM PDT 24
Finished	Mar 12 12:29:19 PM PDT 24
Peak memory	200156 kb
Host	smart-1c864054-332c-4ad1-918f-952e92523ded
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625635806 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3625635806
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.1117778328
Short name	T1202
Test name
Test status
Simulation time	11394747 ps
CPU time	0.64 seconds
Started	Mar 12 12:29:16 PM PDT 24
Finished	Mar 12 12:29:18 PM PDT 24
Peak memory	195764 kb
Host	smart-43bfc652-34c7-467b-ad4b-60eac7f07f46
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117778328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1117778328
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.1832717569
Short name	T1149
Test name
Test status
Simulation time	40708549 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:17 PM PDT 24
Finished	Mar 12 12:29:18 PM PDT 24
Peak memory	194664 kb
Host	smart-485c0d36-4b9f-45a1-b9c0-33965a6baf5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832717569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1832717569
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.301703641
Short name	T1188
Test name
Test status
Simulation time	67068868 ps
CPU time	0.68 seconds
Started	Mar 12 12:29:33 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	195896 kb
Host	smart-bfe74049-96a4-4576-a880-8a2a7346170c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301703641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_ outstanding.301703641
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.3960216128
Short name	T1151
Test name
Test status
Simulation time	87722868 ps
CPU time	1.86 seconds
Started	Mar 12 12:29:13 PM PDT 24
Finished	Mar 12 12:29:15 PM PDT 24
Peak memory	200364 kb
Host	smart-2e1c45cd-fbe0-499d-a1ee-c355a036910e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960216128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3960216128
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.687086201
Short name	T1256
Test name
Test status
Simulation time	87885887 ps
CPU time	1.43 seconds
Started	Mar 12 12:29:31 PM PDT 24
Finished	Mar 12 12:29:33 PM PDT 24
Peak memory	199520 kb
Host	smart-5ddd93e4-d9b0-456d-8f61-157fc6391876
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687086201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.687086201
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1716512857
Short name	T1184
Test name
Test status
Simulation time	76000642 ps
CPU time	0.8 seconds
Started	Mar 12 12:29:12 PM PDT 24
Finished	Mar 12 12:29:13 PM PDT 24
Peak memory	196788 kb
Host	smart-913e143d-2b3b-4cb5-bc44-dd9e596cd6e2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716512857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1716512857
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1839016445
Short name	T1224
Test name
Test status
Simulation time	58090054 ps
CPU time	2.32 seconds
Started	Mar 12 12:29:14 PM PDT 24
Finished	Mar 12 12:29:16 PM PDT 24
Peak memory	198360 kb
Host	smart-b91ac5b8-580d-46f0-a293-06cd363bfb15
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839016445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1839016445
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.129357569
Short name	T1140
Test name
Test status
Simulation time	27383619 ps
CPU time	0.61 seconds
Started	Mar 12 12:29:15 PM PDT 24
Finished	Mar 12 12:29:17 PM PDT 24
Peak memory	195704 kb
Host	smart-039c3daf-42c5-43c5-8b5f-1d18ba9aa6b0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129357569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.129357569
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3815123642
Short name	T1227
Test name
Test status
Simulation time	111708663 ps
CPU time	0.88 seconds
Started	Mar 12 12:29:36 PM PDT 24
Finished	Mar 12 12:29:37 PM PDT 24
Peak memory	200060 kb
Host	smart-4125c217-e068-4384-bb41-8f4ce2119639
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815123642 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3815123642
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.1611532485
Short name	T80
Test name
Test status
Simulation time	22303745 ps
CPU time	0.65 seconds
Started	Mar 12 12:29:13 PM PDT 24
Finished	Mar 12 12:29:14 PM PDT 24
Peak memory	195864 kb
Host	smart-4eea4559-0793-42f3-af2b-9f88b7c7e2fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611532485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1611532485
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.1859223949
Short name	T1134
Test name
Test status
Simulation time	25251924 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:12 PM PDT 24
Finished	Mar 12 12:29:13 PM PDT 24
Peak memory	194700 kb
Host	smart-90f8852d-2290-479a-a32a-561ae0bfb742
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859223949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1859223949
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2579578989
Short name	T1219
Test name
Test status
Simulation time	25828099 ps
CPU time	0.76 seconds
Started	Mar 12 12:29:40 PM PDT 24
Finished	Mar 12 12:29:42 PM PDT 24
Peak memory	197156 kb
Host	smart-fe81f9ee-6326-4a90-a247-a000c72f4d0a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579578989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.2579578989
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.178717972
Short name	T1146
Test name
Test status
Simulation time	27412563 ps
CPU time	1.38 seconds
Started	Mar 12 12:29:11 PM PDT 24
Finished	Mar 12 12:29:13 PM PDT 24
Peak memory	200392 kb
Host	smart-5c6bde4f-6fe9-44de-b0ee-90068c095d3a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178717972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.178717972
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1670448383
Short name	T92
Test name
Test status
Simulation time	50016378 ps
CPU time	1.01 seconds
Started	Mar 12 12:29:14 PM PDT 24
Finished	Mar 12 12:29:15 PM PDT 24
Peak memory	199120 kb
Host	smart-5d5681a8-f473-42db-ad0b-3ea0d67f6b60
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670448383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1670448383
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.909190469
Short name	T1221
Test name
Test status
Simulation time	39738137 ps
CPU time	0.64 seconds
Started	Mar 12 12:29:40 PM PDT 24
Finished	Mar 12 12:29:42 PM PDT 24
Peak memory	197480 kb
Host	smart-d5e307cb-7150-4c72-bf48-f99fdb9f04ed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909190469 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.909190469
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.347345414
Short name	T1158
Test name
Test status
Simulation time	65703758 ps
CPU time	0.62 seconds
Started	Mar 12 12:29:31 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	195708 kb
Host	smart-0cd622e1-36ab-4ecb-97f5-d8627a492455
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347345414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.347345414
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.3300273605
Short name	T1195
Test name
Test status
Simulation time	24433731 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:38 PM PDT 24
Finished	Mar 12 12:29:39 PM PDT 24
Peak memory	194684 kb
Host	smart-55f1d8df-572f-4d5e-8651-8e3ade025f9c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300273605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3300273605
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3686717183
Short name	T1171
Test name
Test status
Simulation time	31520919 ps
CPU time	0.81 seconds
Started	Mar 12 12:29:38 PM PDT 24
Finished	Mar 12 12:29:39 PM PDT 24
Peak memory	197052 kb
Host	smart-f74c080c-3aa9-42a0-bea7-d37a9d5ec967
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686717183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.3686717183
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.1994045383
Short name	T1144
Test name
Test status
Simulation time	77086458 ps
CPU time	1.16 seconds
Started	Mar 12 12:29:50 PM PDT 24
Finished	Mar 12 12:29:52 PM PDT 24
Peak memory	200448 kb
Host	smart-6d40f77d-bb22-48a4-9cb6-879c88175931
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994045383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1994045383
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1264517987
Short name	T91
Test name
Test status
Simulation time	86656292 ps
CPU time	1.39 seconds
Started	Mar 12 12:29:48 PM PDT 24
Finished	Mar 12 12:29:50 PM PDT 24
Peak memory	199480 kb
Host	smart-bc97083b-4d80-47e2-9773-7d49dc9d017e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264517987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1264517987
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2604526942
Short name	T1153
Test name
Test status
Simulation time	31375952 ps
CPU time	0.84 seconds
Started	Mar 12 12:29:42 PM PDT 24
Finished	Mar 12 12:29:43 PM PDT 24
Peak memory	200128 kb
Host	smart-9d3ca22a-462d-42be-b4db-3e813213782c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604526942 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2604526942
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.2811337666
Short name	T1169
Test name
Test status
Simulation time	25040336 ps
CPU time	0.61 seconds
Started	Mar 12 12:29:46 PM PDT 24
Finished	Mar 12 12:29:47 PM PDT 24
Peak memory	195740 kb
Host	smart-e2912c91-4180-4ea5-b2a4-74ce683c6b21
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811337666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2811337666
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.1093035312
Short name	T1204
Test name
Test status
Simulation time	44131513 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:46 PM PDT 24
Finished	Mar 12 12:29:47 PM PDT 24
Peak memory	194700 kb
Host	smart-1ece4204-1004-4505-99b9-eb9d4ab29e0d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093035312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1093035312
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.574620345
Short name	T1159
Test name
Test status
Simulation time	22158951 ps
CPU time	1.12 seconds
Started	Mar 12 12:29:31 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	200368 kb
Host	smart-0fc2f877-cc5a-4479-8ef5-27d30532c458
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574620345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.574620345
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.296125808
Short name	T1156
Test name
Test status
Simulation time	47733184 ps
CPU time	1.25 seconds
Started	Mar 12 12:29:48 PM PDT 24
Finished	Mar 12 12:29:50 PM PDT 24
Peak memory	200348 kb
Host	smart-2f0e9377-340e-4c3f-af9c-2dae6c4f5549
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296125808 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.296125808
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.866488508
Short name	T1162
Test name
Test status
Simulation time	35783186 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	195696 kb
Host	smart-bf50f5c4-48d1-456f-b36c-4e4790f3cd3a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866488508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.866488508
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.1011713392
Short name	T1182
Test name
Test status
Simulation time	35450469 ps
CPU time	0.59 seconds
Started	Mar 12 12:29:36 PM PDT 24
Finished	Mar 12 12:29:37 PM PDT 24
Peak memory	194724 kb
Host	smart-9ddc6f05-d583-4e33-bdaa-057fff9ea48b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011713392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1011713392
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3060367746
Short name	T1241
Test name
Test status
Simulation time	12445594 ps
CPU time	0.61 seconds
Started	Mar 12 12:29:32 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	195772 kb
Host	smart-a8c2660c-9d4a-4e7b-bf7b-dc184ca30e1b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060367746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.3060367746
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.1874673606
Short name	T1147
Test name
Test status
Simulation time	52346692 ps
CPU time	1.83 seconds
Started	Mar 12 12:29:48 PM PDT 24
Finished	Mar 12 12:29:51 PM PDT 24
Peak memory	200372 kb
Host	smart-842ce7b6-4adc-4b0a-a818-91c6539c1446
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874673606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1874673606
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1253141006
Short name	T95
Test name
Test status
Simulation time	153117342 ps
CPU time	0.95 seconds
Started	Mar 12 12:29:48 PM PDT 24
Finished	Mar 12 12:29:50 PM PDT 24
Peak memory	199116 kb
Host	smart-1dbd542e-2638-488c-8ba3-f867e018feaf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253141006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1253141006
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2361696852
Short name	T1185
Test name
Test status
Simulation time	23346501 ps
CPU time	1.07 seconds
Started	Mar 12 12:29:33 PM PDT 24
Finished	Mar 12 12:29:35 PM PDT 24
Peak memory	200152 kb
Host	smart-fde0ab8f-3a3b-47f5-863b-ba5fc6b98560
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361696852 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2361696852
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.4115289329
Short name	T1145
Test name
Test status
Simulation time	25990879 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:43 PM PDT 24
Finished	Mar 12 12:29:44 PM PDT 24
Peak memory	194676 kb
Host	smart-e1770577-932f-4a40-a6b2-0a858fbf4fcb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115289329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4115289329
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3197880406
Short name	T1216
Test name
Test status
Simulation time	29190871 ps
CPU time	0.77 seconds
Started	Mar 12 12:29:38 PM PDT 24
Finished	Mar 12 12:29:39 PM PDT 24
Peak memory	197156 kb
Host	smart-aa0c21be-5ec4-468e-ab05-16bcbe403347
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197880406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.3197880406
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.4145698671
Short name	T1250
Test name
Test status
Simulation time	621454986 ps
CPU time	2.49 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	200344 kb
Host	smart-91996276-9b5c-4eaf-9e9d-3fb170333687
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145698671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4145698671
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3379482290
Short name	T1181
Test name
Test status
Simulation time	69682898 ps
CPU time	1.39 seconds
Started	Mar 12 12:29:38 PM PDT 24
Finished	Mar 12 12:29:39 PM PDT 24
Peak memory	199476 kb
Host	smart-3e4bf34d-84a7-48b4-997e-426a353a95fa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379482290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3379482290
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3749937583
Short name	T1215
Test name
Test status
Simulation time	21275823 ps
CPU time	0.75 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	199184 kb
Host	smart-07a1d471-ded4-426d-80b4-50b09384d9d7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749937583 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3749937583
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.1644426517
Short name	T88
Test name
Test status
Simulation time	14785706 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:32 PM PDT 24
Finished	Mar 12 12:29:33 PM PDT 24
Peak memory	195728 kb
Host	smart-e8afe34a-2573-4aff-9b4e-b32ebfcef4ce
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644426517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1644426517
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.1669860647
Short name	T1172
Test name
Test status
Simulation time	16944436 ps
CPU time	0.62 seconds
Started	Mar 12 12:29:44 PM PDT 24
Finished	Mar 12 12:29:45 PM PDT 24
Peak memory	194692 kb
Host	smart-d4bdc44b-b469-4d30-88f8-7e2f45b726c2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669860647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1669860647
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3591302474
Short name	T1257
Test name
Test status
Simulation time	23094892 ps
CPU time	0.68 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:36 PM PDT 24
Peak memory	194796 kb
Host	smart-a436e2e3-3ebf-4c11-8771-e6796064210b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591302474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.3591302474
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3209031344
Short name	T1229
Test name
Test status
Simulation time	179843686 ps
CPU time	2.2 seconds
Started	Mar 12 12:29:39 PM PDT 24
Finished	Mar 12 12:29:41 PM PDT 24
Peak memory	200372 kb
Host	smart-f576144a-0386-4be2-b06c-830f5c397393
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209031344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3209031344
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1775771250
Short name	T1179
Test name
Test status
Simulation time	26056833 ps
CPU time	0.77 seconds
Started	Mar 12 12:29:43 PM PDT 24
Finished	Mar 12 12:29:44 PM PDT 24
Peak memory	198848 kb
Host	smart-10e84622-36bc-458b-b7c4-93f6c0ef7176
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775771250 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1775771250
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.2444509481
Short name	T1251
Test name
Test status
Simulation time	185423353 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	195772 kb
Host	smart-fc53b909-c55f-48f6-9863-3fa9d0b9f463
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444509481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2444509481
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.3384444494
Short name	T1157
Test name
Test status
Simulation time	31084497 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:48 PM PDT 24
Finished	Mar 12 12:29:49 PM PDT 24
Peak memory	194700 kb
Host	smart-e6b49364-6539-4fd0-9612-9cbcf44dd86f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384444494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3384444494
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2465844277
Short name	T87
Test name
Test status
Simulation time	66752667 ps
CPU time	0.64 seconds
Started	Mar 12 12:29:36 PM PDT 24
Finished	Mar 12 12:29:37 PM PDT 24
Peak memory	195788 kb
Host	smart-ab2fee43-5a99-4ff4-975c-fc2eef826688
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465844277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.2465844277
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.878256079
Short name	T1211
Test name
Test status
Simulation time	75941477 ps
CPU time	1.73 seconds
Started	Mar 12 12:29:44 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	200368 kb
Host	smart-7be6df05-4f64-4640-be65-1969bd7cdffc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878256079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.878256079
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1718754047
Short name	T1226
Test name
Test status
Simulation time	1073678518 ps
CPU time	1.49 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:53 PM PDT 24
Peak memory	199448 kb
Host	smart-cfbfb25d-f610-4356-a503-5e2a38e0bf97
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718754047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1718754047
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2958166644
Short name	T1190
Test name
Test status
Simulation time	26058268 ps
CPU time	0.81 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	200108 kb
Host	smart-01e057fb-8105-455b-87d7-463d6fdad4ad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958166644 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2958166644
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.1543159865
Short name	T1208
Test name
Test status
Simulation time	43420348 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:33 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	195736 kb
Host	smart-ec05439b-4bf8-4d8f-9995-ccc58e719dd7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543159865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1543159865
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.2907863156
Short name	T1253
Test name
Test status
Simulation time	46251923 ps
CPU time	0.61 seconds
Started	Mar 12 12:29:34 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	194712 kb
Host	smart-3c38ded3-c4f1-4b87-89ee-c05012739b62
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907863156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2907863156
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3229888068
Short name	T83
Test name
Test status
Simulation time	59866735 ps
CPU time	0.62 seconds
Started	Mar 12 12:29:27 PM PDT 24
Finished	Mar 12 12:29:33 PM PDT 24
Peak memory	194832 kb
Host	smart-01c04402-5913-4847-b827-9ffe29b35572
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229888068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.3229888068
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.2711332394
Short name	T1154
Test name
Test status
Simulation time	74524637 ps
CPU time	1.22 seconds
Started	Mar 12 12:29:27 PM PDT 24
Finished	Mar 12 12:29:29 PM PDT 24
Peak memory	200116 kb
Host	smart-b970bb10-4e10-49ba-aa85-64186d94e398
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711332394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2711332394
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3819140296
Short name	T1225
Test name
Test status
Simulation time	66098454 ps
CPU time	0.85 seconds
Started	Mar 12 12:29:52 PM PDT 24
Finished	Mar 12 12:29:53 PM PDT 24
Peak memory	200100 kb
Host	smart-33b783ef-3c1d-4296-8de4-74d2e9367f4e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819140296 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3819140296
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.3010409487
Short name	T1166
Test name
Test status
Simulation time	17164439 ps
CPU time	0.63 seconds
Started	Mar 12 12:29:33 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	195760 kb
Host	smart-1a1e3849-5ae5-4a85-911f-11f64c91341e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010409487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3010409487
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.1588104292
Short name	T1223
Test name
Test status
Simulation time	22010599 ps
CPU time	0.6 seconds
Started	Mar 12 12:30:27 PM PDT 24
Finished	Mar 12 12:30:28 PM PDT 24
Peak memory	194732 kb
Host	smart-f4288b03-b375-47e6-b32e-7ff6506a6bb6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588104292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1588104292
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.394885873
Short name	T1160
Test name
Test status
Simulation time	55749175 ps
CPU time	0.75 seconds
Started	Mar 12 12:29:32 PM PDT 24
Finished	Mar 12 12:29:33 PM PDT 24
Peak memory	196012 kb
Host	smart-376f2921-9aa1-4a8a-9a56-f49b48a1b910
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394885873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr _outstanding.394885873
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.68287695
Short name	T1152
Test name
Test status
Simulation time	31755357 ps
CPU time	0.87 seconds
Started	Mar 12 12:29:45 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	198500 kb
Host	smart-bf171318-38c2-453c-a6a4-288d9bd1e44d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68287695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.68287695
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2805340800
Short name	T1228
Test name
Test status
Simulation time	86597054 ps
CPU time	0.94 seconds
Started	Mar 12 12:29:33 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	198904 kb
Host	smart-d89439f7-e614-4571-b915-45540b3c4465
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805340800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2805340800
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2176483970
Short name	T1209
Test name
Test status
Simulation time	53047282 ps
CPU time	0.9 seconds
Started	Mar 12 12:29:49 PM PDT 24
Finished	Mar 12 12:29:51 PM PDT 24
Peak memory	200100 kb
Host	smart-dd2c117f-2924-4691-94c8-89b59084442d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176483970 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2176483970
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.1358638444
Short name	T61
Test name
Test status
Simulation time	35289638 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:47 PM PDT 24
Finished	Mar 12 12:29:49 PM PDT 24
Peak memory	195760 kb
Host	smart-a031dcd1-3d4b-4374-b29f-1733cf89fcb1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358638444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1358638444
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.2400341602
Short name	T1170
Test name
Test status
Simulation time	13721990 ps
CPU time	0.57 seconds
Started	Mar 12 12:30:05 PM PDT 24
Finished	Mar 12 12:30:06 PM PDT 24
Peak memory	194768 kb
Host	smart-7d1cf543-60d8-42f4-881a-bb6f936fca4d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400341602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2400341602
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3284891060
Short name	T1242
Test name
Test status
Simulation time	49114455 ps
CPU time	0.62 seconds
Started	Mar 12 12:29:42 PM PDT 24
Finished	Mar 12 12:29:43 PM PDT 24
Peak memory	195812 kb
Host	smart-d367749a-ce93-4c41-b3fa-92b5c9018e99
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284891060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.3284891060
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.1223093637
Short name	T1138
Test name
Test status
Simulation time	326875731 ps
CPU time	1.72 seconds
Started	Mar 12 12:29:46 PM PDT 24
Finished	Mar 12 12:29:48 PM PDT 24
Peak memory	200448 kb
Host	smart-311ca1bb-6569-49c4-a6a4-b2d4698a719e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223093637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1223093637
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3667494148
Short name	T1247
Test name
Test status
Simulation time	538266298 ps
CPU time	1.46 seconds
Started	Mar 12 12:29:40 PM PDT 24
Finished	Mar 12 12:29:42 PM PDT 24
Peak memory	199452 kb
Host	smart-12ed4f90-7272-49b5-80ba-a315846657a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667494148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3667494148
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2099480279
Short name	T1191
Test name
Test status
Simulation time	16109502 ps
CPU time	0.71 seconds
Started	Mar 12 12:29:38 PM PDT 24
Finished	Mar 12 12:29:39 PM PDT 24
Peak memory	197992 kb
Host	smart-9885ca44-509e-4373-b4e2-cfad058e9d59
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099480279 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2099480279
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.2025223691
Short name	T79
Test name
Test status
Simulation time	30230564 ps
CPU time	0.65 seconds
Started	Mar 12 12:29:35 PM PDT 24
Finished	Mar 12 12:29:41 PM PDT 24
Peak memory	195908 kb
Host	smart-1821ba5f-b2a8-45a5-a6ad-d7a150d9f3b6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025223691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2025223691
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.771396126
Short name	T1161
Test name
Test status
Simulation time	25553359 ps
CPU time	0.55 seconds
Started	Mar 12 12:29:47 PM PDT 24
Finished	Mar 12 12:29:48 PM PDT 24
Peak memory	194684 kb
Host	smart-c5b29145-b934-4435-863d-44835717aa99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771396126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.771396126
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2973880626
Short name	T1238
Test name
Test status
Simulation time	19750667 ps
CPU time	0.66 seconds
Started	Mar 12 12:29:50 PM PDT 24
Finished	Mar 12 12:29:51 PM PDT 24
Peak memory	195896 kb
Host	smart-db86b9a9-aa97-4203-8723-e73d93dee1b8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973880626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.2973880626
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.4264929631
Short name	T1196
Test name
Test status
Simulation time	205366717 ps
CPU time	1.25 seconds
Started	Mar 12 12:29:49 PM PDT 24
Finished	Mar 12 12:29:51 PM PDT 24
Peak memory	200280 kb
Host	smart-9471917c-971f-4b36-9732-798bbb8605ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264929631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.4264929631
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4031775896
Short name	T1255
Test name
Test status
Simulation time	138554172 ps
CPU time	1.32 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:53 PM PDT 24
Peak memory	199424 kb
Host	smart-ac19594d-2e40-437a-8af5-b523df968a22
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031775896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4031775896
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2133219058
Short name	T68
Test name
Test status
Simulation time	107449661 ps
CPU time	0.68 seconds
Started	Mar 12 12:29:44 PM PDT 24
Finished	Mar 12 12:29:45 PM PDT 24
Peak memory	195700 kb
Host	smart-b47e6a17-5bf3-4d41-ba59-a00fdd5df33b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133219058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2133219058
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2500697085
Short name	T1248
Test name
Test status
Simulation time	485792600 ps
CPU time	2.71 seconds
Started	Mar 12 12:29:26 PM PDT 24
Finished	Mar 12 12:29:29 PM PDT 24
Peak memory	197884 kb
Host	smart-e56be8d7-eb69-4674-9546-808ac40113c5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500697085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2500697085
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3225409287
Short name	T63
Test name
Test status
Simulation time	41086013 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:47 PM PDT 24
Finished	Mar 12 12:29:48 PM PDT 24
Peak memory	195760 kb
Host	smart-ca81d732-3601-4a9d-9fa1-43e7f2e6fc8a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225409287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3225409287
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3689164774
Short name	T1130
Test name
Test status
Simulation time	18818712 ps
CPU time	0.76 seconds
Started	Mar 12 12:29:40 PM PDT 24
Finished	Mar 12 12:29:41 PM PDT 24
Peak memory	200080 kb
Host	smart-7e01dbaa-2cd0-4245-8d58-5724b76f351e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689164774 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3689164774
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.40560810
Short name	T84
Test name
Test status
Simulation time	30435240 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:29 PM PDT 24
Peak memory	195808 kb
Host	smart-9e327122-364c-42d1-ad6f-d7fb2ea8dce8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.40560810
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.262947042
Short name	T1139
Test name
Test status
Simulation time	11806736 ps
CPU time	0.61 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:30 PM PDT 24
Peak memory	194728 kb
Host	smart-f8721d28-f1b6-4d2b-a160-034fa59c8d67
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262947042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.262947042
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4145783791
Short name	T1220
Test name
Test status
Simulation time	129546760 ps
CPU time	0.78 seconds
Started	Mar 12 12:29:33 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	196304 kb
Host	smart-5c8b35d6-1731-4fa1-8ae0-48ef1c8bc997
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145783791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.4145783791
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2068885107
Short name	T1236
Test name
Test status
Simulation time	509872832 ps
CPU time	2.1 seconds
Started	Mar 12 12:29:35 PM PDT 24
Finished	Mar 12 12:29:37 PM PDT 24
Peak memory	200352 kb
Host	smart-c60739b6-57fe-4f3c-926e-a1272844648d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068885107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2068885107
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2758868013
Short name	T1231
Test name
Test status
Simulation time	54000915 ps
CPU time	0.98 seconds
Started	Mar 12 12:29:48 PM PDT 24
Finished	Mar 12 12:29:50 PM PDT 24
Peak memory	198864 kb
Host	smart-24458d82-5103-4421-9a4f-ae7368d1bca0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758868013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2758868013
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.1965035626
Short name	T1212
Test name
Test status
Simulation time	91246024 ps
CPU time	0.59 seconds
Started	Mar 12 12:29:46 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	194724 kb
Host	smart-2cb7a79a-75d9-45d9-a71e-bd44a8498ea0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965035626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1965035626
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.2078122525
Short name	T1243
Test name
Test status
Simulation time	14413627 ps
CPU time	0.63 seconds
Started	Mar 12 12:29:54 PM PDT 24
Finished	Mar 12 12:29:55 PM PDT 24
Peak memory	194712 kb
Host	smart-8175b853-e7c8-4577-a22b-5cf599f21d1a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078122525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2078122525
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.1865181150
Short name	T1131
Test name
Test status
Simulation time	12600685 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:52 PM PDT 24
Peak memory	194696 kb
Host	smart-18bab9d3-b4d9-47cb-b5ba-2dbd456868fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865181150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1865181150
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.3999292242
Short name	T1249
Test name
Test status
Simulation time	17607839 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:57 PM PDT 24
Finished	Mar 12 12:29:58 PM PDT 24
Peak memory	194764 kb
Host	smart-cfe423ed-755b-4d98-bb90-428ee459babe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999292242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3999292242
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.874445079
Short name	T1194
Test name
Test status
Simulation time	37582626 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:56 PM PDT 24
Finished	Mar 12 12:29:57 PM PDT 24
Peak memory	194756 kb
Host	smart-c8c7fca4-af08-4704-9dbc-2be1f1aa1164
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874445079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.874445079
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1378647425
Short name	T1205
Test name
Test status
Simulation time	33589099 ps
CPU time	0.62 seconds
Started	Mar 12 12:29:46 PM PDT 24
Finished	Mar 12 12:29:47 PM PDT 24
Peak memory	194824 kb
Host	smart-ff0b2940-8e1f-4cf3-8db6-b42787b5f0e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378647425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1378647425
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.4257516074
Short name	T1129
Test name
Test status
Simulation time	35556349 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:49 PM PDT 24
Finished	Mar 12 12:29:50 PM PDT 24
Peak memory	194620 kb
Host	smart-7946e299-4625-4c1a-aacb-2d98cdc4a239
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257516074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4257516074
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.3711681850
Short name	T1232
Test name
Test status
Simulation time	39635495 ps
CPU time	0.59 seconds
Started	Mar 12 12:29:54 PM PDT 24
Finished	Mar 12 12:29:54 PM PDT 24
Peak memory	194712 kb
Host	smart-ebc63f74-a63f-4629-bbc1-3a77f13acd3c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711681850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3711681850
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.674823617
Short name	T1127
Test name
Test status
Simulation time	14361547 ps
CPU time	0.54 seconds
Started	Mar 12 12:29:53 PM PDT 24
Finished	Mar 12 12:29:53 PM PDT 24
Peak memory	194708 kb
Host	smart-0690a721-4d90-4348-8f4b-0121e45beaeb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674823617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.674823617
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.106314866
Short name	T1128
Test name
Test status
Simulation time	38564665 ps
CPU time	0.55 seconds
Started	Mar 12 12:30:00 PM PDT 24
Finished	Mar 12 12:30:00 PM PDT 24
Peak memory	194772 kb
Host	smart-b8ff0387-5074-4946-bc9c-495c6e377ae8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106314866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.106314866
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.363439456
Short name	T1137
Test name
Test status
Simulation time	214059442 ps
CPU time	0.68 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	194840 kb
Host	smart-bf1e288f-537f-4055-ab3d-bd1103d91842
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363439456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.363439456
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1430119356
Short name	T67
Test name
Test status
Simulation time	179984240 ps
CPU time	2.29 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	198104 kb
Host	smart-fab2a41d-0626-444e-9cbf-b11b3189f6b7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430119356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1430119356
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.365012206
Short name	T1207
Test name
Test status
Simulation time	14777941 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:27 PM PDT 24
Finished	Mar 12 12:29:28 PM PDT 24
Peak memory	195708 kb
Host	smart-39f03c96-e4d3-4102-ac76-b18a3b615066
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365012206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.365012206
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3030850802
Short name	T1178
Test name
Test status
Simulation time	47538999 ps
CPU time	1.14 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	200328 kb
Host	smart-94a47945-a343-4cd9-b928-36f359246769
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030850802 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3030850802
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.1116537490
Short name	T62
Test name
Test status
Simulation time	21300401 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	195776 kb
Host	smart-609f0a65-4dc2-4132-94e4-9a4597c09048
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116537490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1116537490
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.4033676940
Short name	T1240
Test name
Test status
Simulation time	53136221 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	194660 kb
Host	smart-5734d5e0-a102-4e4e-b311-6bef869653ec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033676940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4033676940
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2591416569
Short name	T1218
Test name
Test status
Simulation time	386333166 ps
CPU time	0.74 seconds
Started	Mar 12 12:29:31 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	197040 kb
Host	smart-6d0b2e20-46e7-4531-9436-bf2f56bccff3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591416569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.2591416569
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.3643901133
Short name	T1230
Test name
Test status
Simulation time	96800069 ps
CPU time	1.56 seconds
Started	Mar 12 12:29:36 PM PDT 24
Finished	Mar 12 12:29:38 PM PDT 24
Peak memory	200456 kb
Host	smart-b6d4a0ec-b014-4cda-9ae7-f785803a3d52
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643901133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3643901133
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1967781590
Short name	T100
Test name
Test status
Simulation time	75274063 ps
CPU time	1.42 seconds
Started	Mar 12 12:29:34 PM PDT 24
Finished	Mar 12 12:29:35 PM PDT 24
Peak memory	199420 kb
Host	smart-e0350505-07e5-4ff6-8c6d-533f0354a323
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967781590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1967781590
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.3100121593
Short name	T1165
Test name
Test status
Simulation time	16062886 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:47 PM PDT 24
Finished	Mar 12 12:29:48 PM PDT 24
Peak memory	194748 kb
Host	smart-cc1eacc9-572d-435e-a2aa-f29d9d94e2ce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100121593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3100121593
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.1916261243
Short name	T1245
Test name
Test status
Simulation time	39917349 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:48 PM PDT 24
Finished	Mar 12 12:29:49 PM PDT 24
Peak memory	194668 kb
Host	smart-18b708d3-a98c-43da-b0e0-9c6d1b128558
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916261243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1916261243
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.2859738346
Short name	T1192
Test name
Test status
Simulation time	164720416 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:52 PM PDT 24
Finished	Mar 12 12:29:53 PM PDT 24
Peak memory	194720 kb
Host	smart-2d126d18-4a09-4211-ae0f-e114d1ec54ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859738346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2859738346
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.2280106155
Short name	T1150
Test name
Test status
Simulation time	20077398 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:39 PM PDT 24
Finished	Mar 12 12:29:44 PM PDT 24
Peak memory	194792 kb
Host	smart-78ad44b1-bdf1-4b99-a064-dc56665f6a57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280106155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2280106155
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.983300984
Short name	T1180
Test name
Test status
Simulation time	13700275 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:53 PM PDT 24
Finished	Mar 12 12:29:54 PM PDT 24
Peak memory	194772 kb
Host	smart-9c19ec9e-a839-4482-be5a-854be45f37ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983300984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.983300984
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.3963118435
Short name	T1167
Test name
Test status
Simulation time	24476091 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:55 PM PDT 24
Finished	Mar 12 12:29:55 PM PDT 24
Peak memory	194768 kb
Host	smart-2aed8914-3856-4eb1-989e-17c4cf0350d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963118435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3963118435
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.3538645749
Short name	T1136
Test name
Test status
Simulation time	68345581 ps
CPU time	0.54 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:52 PM PDT 24
Peak memory	194764 kb
Host	smart-3f2cd97e-0610-46dd-8d69-9aba6923ce97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538645749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3538645749
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.3613920816
Short name	T1155
Test name
Test status
Simulation time	13215232 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:53 PM PDT 24
Peak memory	194768 kb
Host	smart-6737b981-5208-4e82-ac36-9e36054b73b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613920816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3613920816
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.2293521630
Short name	T1222
Test name
Test status
Simulation time	62606467 ps
CPU time	0.59 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:52 PM PDT 24
Peak memory	194700 kb
Host	smart-5e597f71-b672-4d20-a803-60ed3f67548f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293521630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2293521630
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.4183152768
Short name	T1135
Test name
Test status
Simulation time	45923000 ps
CPU time	0.54 seconds
Started	Mar 12 12:29:56 PM PDT 24
Finished	Mar 12 12:29:57 PM PDT 24
Peak memory	194768 kb
Host	smart-4948d7d3-cf4b-4f40-825c-eea20b2447a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183152768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4183152768
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.112850888
Short name	T1164
Test name
Test status
Simulation time	20307387 ps
CPU time	0.64 seconds
Started	Mar 12 12:29:27 PM PDT 24
Finished	Mar 12 12:29:28 PM PDT 24
Peak memory	195044 kb
Host	smart-5a93a0be-e609-4dd1-b40e-ae9e138a16af
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112850888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.112850888
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2745808695
Short name	T1176
Test name
Test status
Simulation time	879659988 ps
CPU time	1.52 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	198172 kb
Host	smart-3f142ca9-af05-4bd2-a627-101bd63545a3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745808695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2745808695
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2102578376
Short name	T66
Test name
Test status
Simulation time	16257473 ps
CPU time	0.63 seconds
Started	Mar 12 12:29:34 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	195760 kb
Host	smart-fa2695e1-9858-481c-99ea-49c62dc7eb75
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102578376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2102578376
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4086617337
Short name	T1239
Test name
Test status
Simulation time	124910274 ps
CPU time	0.92 seconds
Started	Mar 12 12:29:40 PM PDT 24
Finished	Mar 12 12:29:41 PM PDT 24
Peak memory	200160 kb
Host	smart-6eb79c0b-e249-41b4-851f-460630c54c9a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086617337 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4086617337
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.1629083916
Short name	T81
Test name
Test status
Simulation time	13664992 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:44 PM PDT 24
Finished	Mar 12 12:29:44 PM PDT 24
Peak memory	195408 kb
Host	smart-d5365df8-db56-46d1-8e8c-33db059487b7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629083916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1629083916
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.2229787882
Short name	T1258
Test name
Test status
Simulation time	97712610 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:29 PM PDT 24
Peak memory	194704 kb
Host	smart-e6e956c8-b0b0-4af9-858c-6a8bbe6146cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229787882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2229787882
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2734848631
Short name	T1206
Test name
Test status
Simulation time	74437490 ps
CPU time	0.64 seconds
Started	Mar 12 12:29:32 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	195768 kb
Host	smart-ec52d5db-3c76-4e7c-ae34-10ad44ebeb95
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734848631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.2734848631
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.4242720170
Short name	T1142
Test name
Test status
Simulation time	490655964 ps
CPU time	1.32 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	200288 kb
Host	smart-9cea51c9-ada4-4d1c-bb4a-4d4f36659efd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242720170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4242720170
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2249399273
Short name	T99
Test name
Test status
Simulation time	81370843 ps
CPU time	1.3 seconds
Started	Mar 12 12:29:36 PM PDT 24
Finished	Mar 12 12:29:38 PM PDT 24
Peak memory	199492 kb
Host	smart-77898841-12e8-4b58-9034-9c3a1b1e00d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249399273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2249399273
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.1084600051
Short name	T1148
Test name
Test status
Simulation time	39638936 ps
CPU time	0.59 seconds
Started	Mar 12 12:30:05 PM PDT 24
Finished	Mar 12 12:30:05 PM PDT 24
Peak memory	194768 kb
Host	smart-b51f3191-7dc2-4e7c-9304-fc7089441348
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084600051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1084600051
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.2862188925
Short name	T1193
Test name
Test status
Simulation time	54057851 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:53 PM PDT 24
Finished	Mar 12 12:29:54 PM PDT 24
Peak memory	194768 kb
Host	smart-dbece1c2-3baa-4780-b72d-d5af9f5873f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862188925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2862188925
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.3332901884
Short name	T1201
Test name
Test status
Simulation time	25243685 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:50 PM PDT 24
Finished	Mar 12 12:29:51 PM PDT 24
Peak memory	194680 kb
Host	smart-ae0fcdab-3212-4a05-bb8f-1e10ca5d7820
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332901884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3332901884
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.18137465
Short name	T1233
Test name
Test status
Simulation time	29279079 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:46 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	194696 kb
Host	smart-22e62403-6cc3-4247-b130-622a97a3f96b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18137465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.18137465
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.2031433772
Short name	T1141
Test name
Test status
Simulation time	22971943 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:52 PM PDT 24
Peak memory	194664 kb
Host	smart-4c300e62-cf2f-4b4e-8725-8f83c3d12fff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031433772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2031433772
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.2463515419
Short name	T1168
Test name
Test status
Simulation time	14637036 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:49 PM PDT 24
Finished	Mar 12 12:29:50 PM PDT 24
Peak memory	194792 kb
Host	smart-1853e99b-dbf2-47a0-9156-ecfb2ba3d99b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463515419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2463515419
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.4258813167
Short name	T1133
Test name
Test status
Simulation time	32936650 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:51 PM PDT 24
Finished	Mar 12 12:29:52 PM PDT 24
Peak memory	194660 kb
Host	smart-355c2666-530c-41e2-9a1e-4b69fc15a991
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258813167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4258813167
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.2256014593
Short name	T1143
Test name
Test status
Simulation time	30245853 ps
CPU time	0.57 seconds
Started	Mar 12 12:29:50 PM PDT 24
Finished	Mar 12 12:29:51 PM PDT 24
Peak memory	194716 kb
Host	smart-cb08278f-2d57-48fe-865e-9ed7103a75f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256014593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2256014593
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.1066796305
Short name	T1252
Test name
Test status
Simulation time	29440372 ps
CPU time	0.55 seconds
Started	Mar 12 12:30:01 PM PDT 24
Finished	Mar 12 12:30:01 PM PDT 24
Peak memory	194768 kb
Host	smart-463756e1-b686-44b5-a75b-1f7b2d189608
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066796305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1066796305
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.2742725694
Short name	T1234
Test name
Test status
Simulation time	23854737 ps
CPU time	0.6 seconds
Started	Mar 12 12:29:49 PM PDT 24
Finished	Mar 12 12:29:50 PM PDT 24
Peak memory	194664 kb
Host	smart-820158a3-3086-45b7-971f-a6615e76e8c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742725694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2742725694
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2167316297
Short name	T1203
Test name
Test status
Simulation time	46283681 ps
CPU time	1.32 seconds
Started	Mar 12 12:29:41 PM PDT 24
Finished	Mar 12 12:29:43 PM PDT 24
Peak memory	200308 kb
Host	smart-319d21a9-a000-4118-9889-9243a4ca48fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167316297 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2167316297
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.1345030884
Short name	T1199
Test name
Test status
Simulation time	12272845 ps
CPU time	0.59 seconds
Started	Mar 12 12:29:28 PM PDT 24
Finished	Mar 12 12:29:29 PM PDT 24
Peak memory	195900 kb
Host	smart-8f041ae4-100b-440f-8226-0b82f04a0b1f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345030884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1345030884
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.343113324
Short name	T1175
Test name
Test status
Simulation time	72982883 ps
CPU time	0.59 seconds
Started	Mar 12 12:29:27 PM PDT 24
Finished	Mar 12 12:29:28 PM PDT 24
Peak memory	194780 kb
Host	smart-2b422ef3-3fec-484e-9cad-ffa937751997
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343113324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.343113324
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3241853206
Short name	T1237
Test name
Test status
Simulation time	30431411 ps
CPU time	0.66 seconds
Started	Mar 12 12:29:28 PM PDT 24
Finished	Mar 12 12:29:29 PM PDT 24
Peak memory	196228 kb
Host	smart-b0dccd9b-c7f9-42a0-8b2e-53b9f78aedf3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241853206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.3241853206
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.4242242134
Short name	T1198
Test name
Test status
Simulation time	32387632 ps
CPU time	1.76 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	200412 kb
Host	smart-8882cf97-a08d-4c53-bb30-c7ced8e3347c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242242134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4242242134
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.659796368
Short name	T96
Test name
Test status
Simulation time	93125443 ps
CPU time	0.92 seconds
Started	Mar 12 12:29:34 PM PDT 24
Finished	Mar 12 12:29:35 PM PDT 24
Peak memory	198952 kb
Host	smart-b674679f-624b-4b7a-9f07-2440b786e759
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659796368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.659796368
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3390066013
Short name	T1200
Test name
Test status
Simulation time	34303599 ps
CPU time	0.96 seconds
Started	Mar 12 12:29:36 PM PDT 24
Finished	Mar 12 12:29:37 PM PDT 24
Peak memory	200112 kb
Host	smart-17fded8e-4a84-48d3-9c26-11bc604752b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390066013 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3390066013
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.1246573516
Short name	T64
Test name
Test status
Simulation time	15577991 ps
CPU time	0.67 seconds
Started	Mar 12 12:29:44 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	195744 kb
Host	smart-8c73a575-78ff-4c93-a67b-7b4b9a75d387
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246573516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1246573516
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.3891495437
Short name	T1173
Test name
Test status
Simulation time	38556859 ps
CPU time	0.58 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	194716 kb
Host	smart-7d106d8f-4c02-4059-a016-d6c1796f9134
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891495437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3891495437
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4203187436
Short name	T85
Test name
Test status
Simulation time	64791439 ps
CPU time	0.66 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	195948 kb
Host	smart-6d3997bb-d248-44c5-9a0f-f8b15c3d648f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203187436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.4203187436
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.1567489101
Short name	T1244
Test name
Test status
Simulation time	117137454 ps
CPU time	1.58 seconds
Started	Mar 12 12:29:31 PM PDT 24
Finished	Mar 12 12:29:33 PM PDT 24
Peak memory	200404 kb
Host	smart-af6ea09c-9765-4f01-be0f-9b9496ffb1c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567489101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1567489101
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2843279388
Short name	T1214
Test name
Test status
Simulation time	422584082 ps
CPU time	0.9 seconds
Started	Mar 12 12:29:41 PM PDT 24
Finished	Mar 12 12:29:42 PM PDT 24
Peak memory	199044 kb
Host	smart-a63af5a3-447b-413f-a2ae-f851451227a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843279388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2843279388
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2144295218
Short name	T1132
Test name
Test status
Simulation time	41583978 ps
CPU time	1.09 seconds
Started	Mar 12 12:29:31 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	200332 kb
Host	smart-b46df6fe-6e9e-4ff0-8b26-5d9d0d3f6d5d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144295218 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2144295218
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.2305573694
Short name	T1254
Test name
Test status
Simulation time	14264913 ps
CPU time	0.61 seconds
Started	Mar 12 12:29:53 PM PDT 24
Finished	Mar 12 12:29:54 PM PDT 24
Peak memory	195764 kb
Host	smart-3ef1028d-52c3-4329-94a3-96e74224e8d7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305573694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2305573694
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.2394875649
Short name	T1186
Test name
Test status
Simulation time	14822435 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:31 PM PDT 24
Finished	Mar 12 12:29:32 PM PDT 24
Peak memory	194720 kb
Host	smart-0806e2cd-fb2b-447d-8a15-0b7daabfe928
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394875649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2394875649
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1892679187
Short name	T1189
Test name
Test status
Simulation time	21465224 ps
CPU time	0.67 seconds
Started	Mar 12 12:29:34 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	195736 kb
Host	smart-60fc9efd-d17c-4ab8-993a-2b48b390a0b2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892679187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.1892679187
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.3145295342
Short name	T1235
Test name
Test status
Simulation time	37804107 ps
CPU time	1.39 seconds
Started	Mar 12 12:29:47 PM PDT 24
Finished	Mar 12 12:29:49 PM PDT 24
Peak memory	200320 kb
Host	smart-660ae88a-b3c0-40c9-aa35-b9dd695fded2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145295342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3145295342
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3162420335
Short name	T98
Test name
Test status
Simulation time	44109549 ps
CPU time	0.97 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	199116 kb
Host	smart-43811ab5-e2d3-4bb6-ba5f-743361c60c74
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162420335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3162420335
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3710274225
Short name	T1174
Test name
Test status
Simulation time	19714044 ps
CPU time	0.79 seconds
Started	Mar 12 12:29:32 PM PDT 24
Finished	Mar 12 12:29:33 PM PDT 24
Peak memory	200144 kb
Host	smart-695be55c-a4cf-4448-a305-228e6e9a9de0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710274225 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3710274225
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.3583525997
Short name	T1177
Test name
Test status
Simulation time	16831642 ps
CPU time	0.62 seconds
Started	Mar 12 12:29:45 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	195760 kb
Host	smart-790341d3-dd1d-41db-81da-09897e340f8c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583525997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3583525997
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.1268471016
Short name	T1210
Test name
Test status
Simulation time	41848800 ps
CPU time	0.56 seconds
Started	Mar 12 12:29:29 PM PDT 24
Finished	Mar 12 12:29:30 PM PDT 24
Peak memory	194704 kb
Host	smart-0ea9aa8c-6516-4ddd-a0a2-b19a86b16849
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268471016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1268471016
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.79880769
Short name	T82
Test name
Test status
Simulation time	573470879 ps
CPU time	0.75 seconds
Started	Mar 12 12:29:33 PM PDT 24
Finished	Mar 12 12:29:34 PM PDT 24
Peak memory	196908 kb
Host	smart-340566e9-ad6d-47e6-a4ad-8febf7bbc093
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79880769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_o utstanding.79880769
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.1287272229
Short name	T1246
Test name
Test status
Simulation time	76890631 ps
CPU time	1.85 seconds
Started	Mar 12 12:29:34 PM PDT 24
Finished	Mar 12 12:29:36 PM PDT 24
Peak memory	200380 kb
Host	smart-e441125b-fc66-44cc-9937-4b289dd54a5f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287272229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1287272229
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.228354522
Short name	T93
Test name
Test status
Simulation time	592840305 ps
CPU time	1.1 seconds
Started	Mar 12 12:29:45 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	198988 kb
Host	smart-973557cc-24b6-4fa5-a5cf-6efb39d45277
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228354522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.228354522
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2705742397
Short name	T1163
Test name
Test status
Simulation time	79076756 ps
CPU time	0.74 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	198848 kb
Host	smart-8c9deb21-3e1f-4deb-8e3a-ade741d68ef1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705742397 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2705742397
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.1683874363
Short name	T69
Test name
Test status
Simulation time	42035524 ps
CPU time	0.61 seconds
Started	Mar 12 12:29:30 PM PDT 24
Finished	Mar 12 12:29:31 PM PDT 24
Peak memory	195708 kb
Host	smart-0cf477c8-e8d8-42be-b81e-3caa3797e737
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683874363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1683874363
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.1556197008
Short name	T1187
Test name
Test status
Simulation time	30753982 ps
CPU time	0.59 seconds
Started	Mar 12 12:29:45 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	194824 kb
Host	smart-603f54e6-b3e8-4d96-8d08-4f7a0be49ee5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556197008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1556197008
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1143558517
Short name	T1217
Test name
Test status
Simulation time	21853173 ps
CPU time	0.69 seconds
Started	Mar 12 12:29:46 PM PDT 24
Finished	Mar 12 12:29:47 PM PDT 24
Peak memory	195796 kb
Host	smart-5d2e657f-ca15-4d10-8c14-7d6895013ea9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143558517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.1143558517
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.4276006749
Short name	T1213
Test name
Test status
Simulation time	415223451 ps
CPU time	2.11 seconds
Started	Mar 12 12:29:44 PM PDT 24
Finished	Mar 12 12:29:46 PM PDT 24
Peak memory	200348 kb
Host	smart-3b4d684a-aebd-48bc-959a-a06f032d4504
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276006749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.4276006749
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3326289125
Short name	T391
Test name
Test status
Simulation time	311690050 ps
CPU time	1.52 seconds
Started	Mar 12 12:29:47 PM PDT 24
Finished	Mar 12 12:29:48 PM PDT 24
Peak memory	199576 kb
Host	smart-75b40d93-062a-474a-81ca-25d87967021c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326289125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3326289125
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_alert_test.4294390749
Short name	T686
Test name
Test status
Simulation time	16262588 ps
CPU time	0.62 seconds
Started	Mar 12 01:06:55 PM PDT 24
Finished	Mar 12 01:06:57 PM PDT 24
Peak memory	195544 kb
Host	smart-c7ffda0e-085d-4d1f-929c-5f05ddb5dc8e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294390749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.4294390749
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.3111849135
Short name	T1126
Test name
Test status
Simulation time	9406092301 ps
CPU time	13.8 seconds
Started	Mar 12 01:06:42 PM PDT 24
Finished	Mar 12 01:06:56 PM PDT 24
Peak memory	197992 kb
Host	smart-bc7c4513-84b7-4451-8ff8-e5ad7b2db2da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111849135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3111849135
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_intr.1163677533
Short name	T508
Test name
Test status
Simulation time	26309744469 ps
CPU time	11.14 seconds
Started	Mar 12 01:06:34 PM PDT 24
Finished	Mar 12 01:06:46 PM PDT 24
Peak memory	197296 kb
Host	smart-ad7e21db-747d-4222-a3d9-62267a4a97c6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163677533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1163677533
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_loopback.1119102239
Short name	T1014
Test name
Test status
Simulation time	8181926874 ps
CPU time	6.67 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:19 PM PDT 24
Peak memory	199420 kb
Host	smart-f11886bf-61bf-4f44-b2f6-b0d550a3d06f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119102239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1119102239
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.1921365253
Short name	T426
Test name
Test status
Simulation time	30731101102 ps
CPU time	28.37 seconds
Started	Mar 12 01:06:38 PM PDT 24
Finished	Mar 12 01:07:07 PM PDT 24
Peak memory	198712 kb
Host	smart-c71eaff9-1fbf-4b5c-8bd4-6310dfdcac5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921365253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1921365253
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.1405096954
Short name	T534
Test name
Test status
Simulation time	9646435478 ps
CPU time	493.66 seconds
Started	Mar 12 01:06:48 PM PDT 24
Finished	Mar 12 01:15:03 PM PDT 24
Peak memory	200076 kb
Host	smart-80e1175e-a755-4424-889a-857bc1dd0f56
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1405096954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1405096954
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.558782571
Short name	T794
Test name
Test status
Simulation time	1790069988 ps
CPU time	4.63 seconds
Started	Mar 12 01:06:32 PM PDT 24
Finished	Mar 12 01:06:37 PM PDT 24
Peak memory	197752 kb
Host	smart-cf0232c1-6886-4d06-9a32-16fafd68adcd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=558782571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.558782571
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.1259055983
Short name	T807
Test name
Test status
Simulation time	59585338733 ps
CPU time	21.18 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:26 PM PDT 24
Peak memory	198072 kb
Host	smart-84c20a38-cb89-4d04-bf91-b5aa2d55bc30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259055983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1259055983
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.2639525831
Short name	T518
Test name
Test status
Simulation time	6231496113 ps
CPU time	5.79 seconds
Started	Mar 12 01:07:01 PM PDT 24
Finished	Mar 12 01:07:07 PM PDT 24
Peak memory	195892 kb
Host	smart-d9583865-7e39-4007-9a96-6391707bdea5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639525831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2639525831
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.2526447832
Short name	T36
Test name
Test status
Simulation time	65991530 ps
CPU time	0.77 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:04 PM PDT 24
Peak memory	217428 kb
Host	smart-91f4bc9c-e01c-49a0-9892-f5673bfffef7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526447832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2526447832
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/default/0.uart_smoke.340956911
Short name	T690
Test name
Test status
Simulation time	5752816335 ps
CPU time	9.12 seconds
Started	Mar 12 01:06:34 PM PDT 24
Finished	Mar 12 01:06:44 PM PDT 24
Peak memory	199196 kb
Host	smart-b71b9dff-269a-4a8e-ad19-1c556bc6277c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340956911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.340956911
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.1282868417
Short name	T527
Test name
Test status
Simulation time	1270646880 ps
CPU time	3.62 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:07 PM PDT 24
Peak memory	198076 kb
Host	smart-815e5f1b-a730-4465-85d7-9a25f1ab0726
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282868417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1282868417
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.619549544
Short name	T874
Test name
Test status
Simulation time	34351455565 ps
CPU time	15.12 seconds
Started	Mar 12 01:06:40 PM PDT 24
Finished	Mar 12 01:06:56 PM PDT 24
Peak memory	200128 kb
Host	smart-36c17b6d-4e8f-41d4-afa4-3811d75df82d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=619549544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.619549544
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/1.uart_alert_test.3380244724
Short name	T545
Test name
Test status
Simulation time	14058205 ps
CPU time	0.59 seconds
Started	Mar 12 01:06:53 PM PDT 24
Finished	Mar 12 01:06:56 PM PDT 24
Peak memory	195496 kb
Host	smart-91d73388-41a1-4801-84f1-4f1e7a72be5a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380244724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3380244724
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.3131071768
Short name	T394
Test name
Test status
Simulation time	184912091683 ps
CPU time	212.64 seconds
Started	Mar 12 01:06:47 PM PDT 24
Finished	Mar 12 01:10:20 PM PDT 24
Peak memory	200160 kb
Host	smart-7920a735-abdd-44ec-9022-d422941b834e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131071768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3131071768
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.376137080
Short name	T713
Test name
Test status
Simulation time	192831525710 ps
CPU time	307.18 seconds
Started	Mar 12 01:06:51 PM PDT 24
Finished	Mar 12 01:11:58 PM PDT 24
Peak memory	199060 kb
Host	smart-f654ce68-33b8-4ca6-945e-516ad46542dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376137080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.376137080
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_intr.724992347
Short name	T926
Test name
Test status
Simulation time	139178457880 ps
CPU time	226.36 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:10:46 PM PDT 24
Peak memory	196612 kb
Host	smart-51634915-e977-482d-84a4-1dedd766d0f9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724992347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.724992347
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.868291645
Short name	T575
Test name
Test status
Simulation time	133040519042 ps
CPU time	411.54 seconds
Started	Mar 12 01:06:49 PM PDT 24
Finished	Mar 12 01:13:41 PM PDT 24
Peak memory	200188 kb
Host	smart-79888361-e0d0-4224-9aa3-17f4f45c1951
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=868291645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.868291645
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.4078413653
Short name	T44
Test name
Test status
Simulation time	3954751842 ps
CPU time	5.42 seconds
Started	Mar 12 01:06:50 PM PDT 24
Finished	Mar 12 01:06:55 PM PDT 24
Peak memory	198300 kb
Host	smart-2e53127f-8ea6-40db-a936-224e502fbfda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078413653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.4078413653
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.555455882
Short name	T519
Test name
Test status
Simulation time	47195249241 ps
CPU time	26.39 seconds
Started	Mar 12 01:06:46 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	198976 kb
Host	smart-46ba2dbe-f47e-47ce-9792-ba59be9a0555
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555455882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.555455882
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/1.uart_perf.3650858939
Short name	T801
Test name
Test status
Simulation time	16340928102 ps
CPU time	241.64 seconds
Started	Mar 12 01:06:53 PM PDT 24
Finished	Mar 12 01:10:55 PM PDT 24
Peak memory	200072 kb
Host	smart-b679d99a-59be-41b2-8911-68caa72f0a6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3650858939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3650858939
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.2926471085
Short name	T76
Test name
Test status
Simulation time	6293920536 ps
CPU time	14.11 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:25 PM PDT 24
Peak memory	199048 kb
Host	smart-73b3b5dc-c0c8-4f34-bd01-e725a639749c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2926471085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2926471085
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.4065747431
Short name	T1073
Test name
Test status
Simulation time	55828757778 ps
CPU time	28.01 seconds
Started	Mar 12 01:06:53 PM PDT 24
Finished	Mar 12 01:07:22 PM PDT 24
Peak memory	198660 kb
Host	smart-64232d56-9949-4ffe-949e-9f1aec545345
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065747431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4065747431
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.4116230176
Short name	T1123
Test name
Test status
Simulation time	4501497131 ps
CPU time	7.85 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:19 PM PDT 24
Peak memory	195928 kb
Host	smart-322a1bef-3039-4eba-ac5d-ce2c2ecb19d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116230176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4116230176
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.664720137
Short name	T101
Test name
Test status
Simulation time	247188531 ps
CPU time	0.9 seconds
Started	Mar 12 01:07:01 PM PDT 24
Finished	Mar 12 01:07:02 PM PDT 24
Peak memory	217504 kb
Host	smart-9df3c8c4-1930-4e22-aa9a-5445e54df9d7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664720137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.664720137
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/1.uart_smoke.2329532459
Short name	T1099
Test name
Test status
Simulation time	407367242 ps
CPU time	2.21 seconds
Started	Mar 12 01:06:57 PM PDT 24
Finished	Mar 12 01:07:00 PM PDT 24
Peak memory	198440 kb
Host	smart-f76de0cf-2567-4bb2-a975-c0eca22c796b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329532459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2329532459
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_stress_all.719629568
Short name	T972
Test name
Test status
Simulation time	80136156560 ps
CPU time	169.43 seconds
Started	Mar 12 01:07:02 PM PDT 24
Finished	Mar 12 01:09:52 PM PDT 24
Peak memory	200060 kb
Host	smart-fbd37258-8514-4e8c-8376-1a0f0ccf6458
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719629568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.719629568
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.3465716422
Short name	T822
Test name
Test status
Simulation time	6435912241 ps
CPU time	16.73 seconds
Started	Mar 12 01:06:50 PM PDT 24
Finished	Mar 12 01:07:07 PM PDT 24
Peak memory	199560 kb
Host	smart-cbbea7a3-c4bd-4ac5-939f-e692ccd22558
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465716422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3465716422
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.3563460804
Short name	T932
Test name
Test status
Simulation time	20291380036 ps
CPU time	30.53 seconds
Started	Mar 12 01:06:58 PM PDT 24
Finished	Mar 12 01:07:29 PM PDT 24
Peak memory	200112 kb
Host	smart-46956e12-7616-42b9-9f6b-a18d9a161925
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3563460804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3563460804
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_alert_test.3184041978
Short name	T1010
Test name
Test status
Simulation time	13102570 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:11 PM PDT 24
Peak memory	195500 kb
Host	smart-0992ea99-028f-404e-a489-b49db2770ee0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184041978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3184041978
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.3231765136
Short name	T207
Test name
Test status
Simulation time	157859687379 ps
CPU time	290.11 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:12:02 PM PDT 24
Peak memory	199976 kb
Host	smart-9e79fb54-fdd7-41cf-a52a-2cbc2b4c0208
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231765136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3231765136
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.4066130281
Short name	T167
Test name
Test status
Simulation time	17990220215 ps
CPU time	13.64 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:18 PM PDT 24
Peak memory	199780 kb
Host	smart-ac2beb8e-ac6b-4534-96ff-c27a15230656
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066130281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4066130281
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_intr.3531161817
Short name	T955
Test name
Test status
Simulation time	104168950474 ps
CPU time	68.85 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:08:20 PM PDT 24
Peak memory	200076 kb
Host	smart-a74d3934-0882-4be4-85b2-e57148ad2d24
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531161817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3531161817
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.4169944496
Short name	T420
Test name
Test status
Simulation time	81864708996 ps
CPU time	410.81 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:14:02 PM PDT 24
Peak memory	200088 kb
Host	smart-0b2fca0b-ad53-4a02-8467-048b7cddafa7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4169944496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4169944496
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.871009202
Short name	T509
Test name
Test status
Simulation time	12719725752 ps
CPU time	10.26 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:21 PM PDT 24
Peak memory	199204 kb
Host	smart-6dce44f0-8cb7-48ba-ab18-03407db81af4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871009202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.871009202
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_perf.2556279688
Short name	T948
Test name
Test status
Simulation time	9389573654 ps
CPU time	250.13 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:11:24 PM PDT 24
Peak memory	200100 kb
Host	smart-da8b8f4f-0a70-428d-a21d-8adc69fc9aee
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2556279688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2556279688
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.466295447
Short name	T684
Test name
Test status
Simulation time	4119840098 ps
CPU time	12.64 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:23 PM PDT 24
Peak memory	198532 kb
Host	smart-a01010e4-7e95-4e18-979d-96587b7d6585
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=466295447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.466295447
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.905792712
Short name	T542
Test name
Test status
Simulation time	34845554236 ps
CPU time	60.87 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:08:12 PM PDT 24
Peak memory	200108 kb
Host	smart-50d091d9-238a-4e11-8517-d905348a745c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905792712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.905792712
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.2890074161
Short name	T1022
Test name
Test status
Simulation time	691510355 ps
CPU time	1.15 seconds
Started	Mar 12 01:07:12 PM PDT 24
Finished	Mar 12 01:07:15 PM PDT 24
Peak memory	195440 kb
Host	smart-300bed17-88ae-4677-b76f-0ca05d5fd591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890074161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2890074161
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.2680771191
Short name	T500
Test name
Test status
Simulation time	5381082305 ps
CPU time	6.87 seconds
Started	Mar 12 01:07:04 PM PDT 24
Finished	Mar 12 01:07:11 PM PDT 24
Peak memory	199480 kb
Host	smart-bbaf121f-7410-4d5d-87ee-2a4a2f941274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680771191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2680771191
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_stress_all.390275857
Short name	T828
Test name
Test status
Simulation time	91753073873 ps
CPU time	513.05 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:15:45 PM PDT 24
Peak memory	200080 kb
Host	smart-fc621ae4-27cf-4cf8-9e74-5402aaa74f65
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390275857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.390275857
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_stress_all_with_rand_reset.2545558843
Short name	T38
Test name
Test status
Simulation time	29258025252 ps
CPU time	385.06 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:13:38 PM PDT 24
Peak memory	216540 kb
Host	smart-3ad39d79-47f0-43b6-a04a-f732f52fce91
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545558843 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2545558843
Directory	/workspace/10.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.4029332323
Short name	T506
Test name
Test status
Simulation time	984914745 ps
CPU time	2.31 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:13 PM PDT 24
Peak memory	198340 kb
Host	smart-b1a6cebc-94a6-4a0b-bb4d-bf9c10866c9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029332323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4029332323
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.34277323
Short name	T75
Test name
Test status
Simulation time	9698600443 ps
CPU time	15.08 seconds
Started	Mar 12 01:09:16 PM PDT 24
Finished	Mar 12 01:09:31 PM PDT 24
Peak memory	199944 kb
Host	smart-f822e059-09ff-4b42-9bb8-de24f090b478
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34277323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.34277323
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.2036677901
Short name	T338
Test name
Test status
Simulation time	116072432628 ps
CPU time	90.65 seconds
Started	Mar 12 01:09:16 PM PDT 24
Finished	Mar 12 01:10:47 PM PDT 24
Peak memory	200044 kb
Host	smart-37d04ceb-4906-46e0-81f1-b1e8176d72ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036677901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2036677901
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.2225446710
Short name	T265
Test name
Test status
Simulation time	254234284839 ps
CPU time	96 seconds
Started	Mar 12 01:09:11 PM PDT 24
Finished	Mar 12 01:10:49 PM PDT 24
Peak memory	200032 kb
Host	smart-6418de74-2509-46ec-a316-64b883a38c54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225446710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2225446710
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.4279180359
Short name	T247
Test name
Test status
Simulation time	86615671057 ps
CPU time	36.94 seconds
Started	Mar 12 01:09:19 PM PDT 24
Finished	Mar 12 01:09:56 PM PDT 24
Peak memory	199792 kb
Host	smart-c17477c3-ea6c-4822-9bdc-2e11c5a66295
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279180359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4279180359
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.776102035
Short name	T246
Test name
Test status
Simulation time	130883546958 ps
CPU time	52.27 seconds
Started	Mar 12 01:09:13 PM PDT 24
Finished	Mar 12 01:10:05 PM PDT 24
Peak memory	200136 kb
Host	smart-dd3c654b-3c16-40c0-8158-75bafb4d426f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=776102035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.776102035
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.759622579
Short name	T658
Test name
Test status
Simulation time	9408461964 ps
CPU time	16.22 seconds
Started	Mar 12 01:09:13 PM PDT 24
Finished	Mar 12 01:09:29 PM PDT 24
Peak memory	200080 kb
Host	smart-8a804527-adbd-44c3-b8da-19e112ce9ffe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759622579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.759622579
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.4003356766
Short name	T174
Test name
Test status
Simulation time	79035116923 ps
CPU time	36.79 seconds
Started	Mar 12 01:09:15 PM PDT 24
Finished	Mar 12 01:09:53 PM PDT 24
Peak memory	199996 kb
Host	smart-f931d48d-c633-4b76-843b-34514bc203f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003356766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4003356766
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.1652944558
Short name	T330
Test name
Test status
Simulation time	37448002392 ps
CPU time	64.21 seconds
Started	Mar 12 01:09:14 PM PDT 24
Finished	Mar 12 01:10:18 PM PDT 24
Peak memory	200152 kb
Host	smart-0cb51f5c-cba6-4e7f-927b-bdc24005e532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652944558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1652944558
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.1243465160
Short name	T183
Test name
Test status
Simulation time	22810016130 ps
CPU time	17.52 seconds
Started	Mar 12 01:09:15 PM PDT 24
Finished	Mar 12 01:09:33 PM PDT 24
Peak memory	198324 kb
Host	smart-d0b1d9eb-66cb-4e1b-a8fd-605e0a26fc6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243465160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1243465160
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.4113454811
Short name	T960
Test name
Test status
Simulation time	54776923 ps
CPU time	0.53 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:07:01 PM PDT 24
Peak memory	195496 kb
Host	smart-cf958b58-ce07-4023-964b-6d65f4f7b9ad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113454811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4113454811
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.2786819448
Short name	T1045
Test name
Test status
Simulation time	27035760819 ps
CPU time	22.78 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:34 PM PDT 24
Peak memory	199896 kb
Host	smart-e419ebb0-2bda-40ec-902e-cb1aec79e1ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786819448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2786819448
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.2664994817
Short name	T670
Test name
Test status
Simulation time	36858246394 ps
CPU time	63.3 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	200080 kb
Host	smart-e630eec5-44d5-44de-819a-d85a4910ce65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664994817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2664994817
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_intr.278720769
Short name	T1100
Test name
Test status
Simulation time	48506816616 ps
CPU time	36.02 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:48 PM PDT 24
Peak memory	200080 kb
Host	smart-cef8f169-e9bc-4404-91fb-c060b45e7f4b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278720769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.278720769
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.3993993173
Short name	T574
Test name
Test status
Simulation time	144562127456 ps
CPU time	336.07 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:12:47 PM PDT 24
Peak memory	200112 kb
Host	smart-5748d69b-2b8c-46e6-a9f6-51c3d16df1b8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3993993173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3993993173
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.1657387004
Short name	T628
Test name
Test status
Simulation time	8621982837 ps
CPU time	3.58 seconds
Started	Mar 12 01:07:17 PM PDT 24
Finished	Mar 12 01:07:21 PM PDT 24
Peak memory	198480 kb
Host	smart-a076b17c-8dd2-4406-b2a1-f57a296b4a54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657387004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1657387004
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.2423249376
Short name	T531
Test name
Test status
Simulation time	323010652613 ps
CPU time	60.93 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	200524 kb
Host	smart-135a7874-01fb-45e9-9839-42cd659b74f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423249376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2423249376
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.373160123
Short name	T1043
Test name
Test status
Simulation time	9451906825 ps
CPU time	250.58 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:11:16 PM PDT 24
Peak memory	200160 kb
Host	smart-0fec3f4e-9f81-4bf6-893a-34f9c0a17dce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=373160123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.373160123
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.2975978385
Short name	T16
Test name
Test status
Simulation time	3900255848 ps
CPU time	31.34 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:43 PM PDT 24
Peak memory	198376 kb
Host	smart-5767872f-137a-435a-ba6e-a31f81f03ca9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2975978385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2975978385
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.3934028410
Short name	T369
Test name
Test status
Simulation time	28538751786 ps
CPU time	22.48 seconds
Started	Mar 12 01:07:12 PM PDT 24
Finished	Mar 12 01:07:37 PM PDT 24
Peak memory	200060 kb
Host	smart-d932236e-3079-42f3-845c-eb8aee3d34ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934028410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3934028410
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.21113854
Short name	T837
Test name
Test status
Simulation time	2268936099 ps
CPU time	2.34 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	195684 kb
Host	smart-427e6275-47a5-4a61-9a9e-52fb4daab89e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21113854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.21113854
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.2338058182
Short name	T398
Test name
Test status
Simulation time	522248630 ps
CPU time	1.14 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	197984 kb
Host	smart-41f63da5-bc87-4741-b45b-d968f731143f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338058182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2338058182
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all_with_rand_reset.4216623572
Short name	T435
Test name
Test status
Simulation time	78861923063 ps
CPU time	901.5 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:22:15 PM PDT 24
Peak memory	224980 kb
Host	smart-6593d108-b148-4843-a64f-8a8079dcf0b8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216623572 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.4216623572
Directory	/workspace/11.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.207591842
Short name	T606
Test name
Test status
Simulation time	1054849214 ps
CPU time	2.17 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	198284 kb
Host	smart-a2449bf4-c77f-4e4f-a2e9-1ffc1f326bfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207591842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.207591842
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.2834077403
Short name	T395
Test name
Test status
Simulation time	76735471878 ps
CPU time	128.14 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:09:20 PM PDT 24
Peak memory	200132 kb
Host	smart-93c0a9e3-5aa4-49fd-9615-5fc0a211aa59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834077403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2834077403
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.1365219526
Short name	T908
Test name
Test status
Simulation time	18461280777 ps
CPU time	14.57 seconds
Started	Mar 12 01:09:15 PM PDT 24
Finished	Mar 12 01:09:30 PM PDT 24
Peak memory	199428 kb
Host	smart-01209752-e9f8-41a8-a658-d6ae33d75b9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365219526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1365219526
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.481642316
Short name	T729
Test name
Test status
Simulation time	32335419476 ps
CPU time	62.05 seconds
Started	Mar 12 01:09:17 PM PDT 24
Finished	Mar 12 01:10:20 PM PDT 24
Peak memory	200028 kb
Host	smart-c7e24f27-71c5-4a45-89a0-103a9e0ad57c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481642316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.481642316
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.2406518029
Short name	T173
Test name
Test status
Simulation time	18979729650 ps
CPU time	16.9 seconds
Started	Mar 12 01:09:17 PM PDT 24
Finished	Mar 12 01:09:35 PM PDT 24
Peak memory	199092 kb
Host	smart-a695064d-3850-47a7-a5ab-05d338dbb4da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406518029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2406518029
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.2605905258
Short name	T322
Test name
Test status
Simulation time	397150091472 ps
CPU time	32.61 seconds
Started	Mar 12 01:09:14 PM PDT 24
Finished	Mar 12 01:09:47 PM PDT 24
Peak memory	200020 kb
Host	smart-eb765316-5a15-48e1-a1c8-cb9de1842437
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605905258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2605905258
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.192612861
Short name	T106
Test name
Test status
Simulation time	86293248276 ps
CPU time	128.22 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:11:31 PM PDT 24
Peak memory	199964 kb
Host	smart-d95a462e-b82e-45e4-a0a2-5b72658788f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192612861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.192612861
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.3828327786
Short name	T689
Test name
Test status
Simulation time	22966469517 ps
CPU time	10.29 seconds
Started	Mar 12 01:09:24 PM PDT 24
Finished	Mar 12 01:09:34 PM PDT 24
Peak memory	200100 kb
Host	smart-72294dae-cd34-429b-b0c3-86f3e4bfd7c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828327786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3828327786
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.905935939
Short name	T957
Test name
Test status
Simulation time	32902509 ps
CPU time	0.56 seconds
Started	Mar 12 01:07:20 PM PDT 24
Finished	Mar 12 01:07:20 PM PDT 24
Peak memory	195516 kb
Host	smart-12f11e6a-9394-4d9a-8613-646285748900
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905935939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.905935939
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.3829731
Short name	T1059
Test name
Test status
Simulation time	107583341709 ps
CPU time	51.51 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:08:03 PM PDT 24
Peak memory	200068 kb
Host	smart-b6791b86-7777-48b4-956f-54c8f47e5ca3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3829731
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.4277752389
Short name	T862
Test name
Test status
Simulation time	12890492752 ps
CPU time	11.28 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:23 PM PDT 24
Peak memory	198136 kb
Host	smart-fdf8412f-c520-4f20-b5b5-f6d42ac19ea7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277752389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4277752389
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.2171599682
Short name	T733
Test name
Test status
Simulation time	81726597248 ps
CPU time	79.32 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	200104 kb
Host	smart-2f02df3d-bd37-4c58-b193-9a979c094de4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2171599682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2171599682
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.2355818221
Short name	T856
Test name
Test status
Simulation time	53508535627 ps
CPU time	202.73 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:10:28 PM PDT 24
Peak memory	200132 kb
Host	smart-851b9866-7d2a-47c5-bc83-1fd45874e4ef
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2355818221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2355818221
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_loopback.4251222157
Short name	T968
Test name
Test status
Simulation time	1746854955 ps
CPU time	2 seconds
Started	Mar 12 01:07:26 PM PDT 24
Finished	Mar 12 01:07:28 PM PDT 24
Peak memory	195560 kb
Host	smart-178076dd-5626-4395-83cb-2743480c8d89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251222157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4251222157
Directory	/workspace/12.uart_loopback/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.3231344241
Short name	T907
Test name
Test status
Simulation time	37319408923 ps
CPU time	61.02 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:08:13 PM PDT 24
Peak memory	198180 kb
Host	smart-024cc607-a68f-4119-85db-7ee0aa4c02a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231344241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3231344241
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.3580478290
Short name	T268
Test name
Test status
Simulation time	10328564533 ps
CPU time	221.82 seconds
Started	Mar 12 01:07:25 PM PDT 24
Finished	Mar 12 01:11:07 PM PDT 24
Peak memory	200120 kb
Host	smart-283ccb40-3370-4daa-9e78-67890aae6407
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3580478290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3580478290
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.2595844927
Short name	T520
Test name
Test status
Simulation time	6412931853 ps
CPU time	9.77 seconds
Started	Mar 12 01:06:59 PM PDT 24
Finished	Mar 12 01:07:10 PM PDT 24
Peak memory	198260 kb
Host	smart-e9b772f3-3e03-47c5-b0ce-effb8be0c295
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2595844927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2595844927
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.1626890825
Short name	T349
Test name
Test status
Simulation time	127704109088 ps
CPU time	89.58 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:08:42 PM PDT 24
Peak memory	200092 kb
Host	smart-a98c7809-4ecc-4f6c-9b08-d8a2f78155a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626890825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1626890825
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.396931581
Short name	T850
Test name
Test status
Simulation time	45820764583 ps
CPU time	77.72 seconds
Started	Mar 12 01:07:12 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	195584 kb
Host	smart-61b77958-2a91-4e03-9f91-824da8cbe477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396931581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.396931581
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.2110046186
Short name	T589
Test name
Test status
Simulation time	913612877 ps
CPU time	1.4 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:13 PM PDT 24
Peak memory	198244 kb
Host	smart-4a505519-21b9-4cc6-8e01-9d175fc41014
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110046186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2110046186
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.451138380
Short name	T905
Test name
Test status
Simulation time	14082212231 ps
CPU time	24.69 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:36 PM PDT 24
Peak memory	199844 kb
Host	smart-aae8752b-598a-41df-8d23-47f4421525e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451138380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.451138380
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.3504538510
Short name	T406
Test name
Test status
Simulation time	152253821389 ps
CPU time	175.31 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:09:59 PM PDT 24
Peak memory	200032 kb
Host	smart-d411d36c-baff-4ce4-b712-fb199ee90461
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504538510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3504538510
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.2341300907
Short name	T624
Test name
Test status
Simulation time	30382535079 ps
CPU time	13.87 seconds
Started	Mar 12 01:09:24 PM PDT 24
Finished	Mar 12 01:09:39 PM PDT 24
Peak memory	200136 kb
Host	smart-d6991a09-ab52-46cd-9a43-e8b19579ff72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341300907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2341300907
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.2256718118
Short name	T630
Test name
Test status
Simulation time	13113109317 ps
CPU time	20.8 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:09:44 PM PDT 24
Peak memory	199464 kb
Host	smart-133e7939-141a-48e0-87b7-c23a71344ecf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256718118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2256718118
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.1510042594
Short name	T802
Test name
Test status
Simulation time	79891314883 ps
CPU time	30.75 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:09:56 PM PDT 24
Peak memory	199608 kb
Host	smart-e82ce8d9-7fd4-43be-9450-29778a5e65b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510042594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1510042594
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.3030136887
Short name	T320
Test name
Test status
Simulation time	30176296206 ps
CPU time	14.14 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:09:40 PM PDT 24
Peak memory	199992 kb
Host	smart-3f2e7f3b-1667-48e1-9faf-c217ae318c09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030136887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3030136887
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.4271218150
Short name	T331
Test name
Test status
Simulation time	61036386111 ps
CPU time	24.69 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:09:50 PM PDT 24
Peak memory	200092 kb
Host	smart-de029f03-3793-4c33-971b-706b5843ac89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271218150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4271218150
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.3430458593
Short name	T239
Test name
Test status
Simulation time	21120856090 ps
CPU time	40.42 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:10:05 PM PDT 24
Peak memory	200044 kb
Host	smart-14123631-be50-4134-b04a-c5377f2c7f9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430458593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3430458593
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_alert_test.823337833
Short name	T1125
Test name
Test status
Simulation time	13381971 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:12 PM PDT 24
Finished	Mar 12 01:07:15 PM PDT 24
Peak memory	195540 kb
Host	smart-55a13882-b13b-4282-a0f9-272c0aba6491
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823337833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.823337833
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.1268779135
Short name	T721
Test name
Test status
Simulation time	313112994418 ps
CPU time	166.37 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:09:58 PM PDT 24
Peak memory	200124 kb
Host	smart-5b7af52f-c354-4d1d-8d06-2e9993c55386
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268779135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1268779135
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.81320864
Short name	T839
Test name
Test status
Simulation time	89528916922 ps
CPU time	28.15 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:39 PM PDT 24
Peak memory	199868 kb
Host	smart-76eae577-0266-4798-9082-0b5096a19995
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81320864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.81320864
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.583454906
Short name	T599
Test name
Test status
Simulation time	270437848631 ps
CPU time	63.8 seconds
Started	Mar 12 01:07:20 PM PDT 24
Finished	Mar 12 01:08:24 PM PDT 24
Peak memory	199732 kb
Host	smart-fcadd980-2300-4b56-a667-7470f49a28ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583454906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.583454906
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.1189374880
Short name	T614
Test name
Test status
Simulation time	14356089455 ps
CPU time	12.8 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:24 PM PDT 24
Peak memory	199532 kb
Host	smart-db4f55f3-d49d-4123-8b00-4ede89d91e30
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189374880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1189374880
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.110156738
Short name	T522
Test name
Test status
Simulation time	90095346765 ps
CPU time	915.41 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:22:25 PM PDT 24
Peak memory	200040 kb
Host	smart-e4d0c7a7-36c8-483b-b2ce-7b7e9f7750d4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=110156738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.110156738
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/13.uart_loopback.1296228597
Short name	T487
Test name
Test status
Simulation time	207563935 ps
CPU time	0.87 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	196532 kb
Host	smart-0bb99025-d073-46ac-8220-34fdea786220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296228597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1296228597
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.698377422
Short name	T561
Test name
Test status
Simulation time	163459082849 ps
CPU time	86.75 seconds
Started	Mar 12 01:07:12 PM PDT 24
Finished	Mar 12 01:08:41 PM PDT 24
Peak memory	199404 kb
Host	smart-f6060cb5-617b-4492-9ed8-2a10bb0eadd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698377422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.698377422
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.2287506594
Short name	T554
Test name
Test status
Simulation time	21847733736 ps
CPU time	1125.5 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:25:56 PM PDT 24
Peak memory	200096 kb
Host	smart-90e90e4f-82a7-4b59-8b24-b39122ec0c34
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2287506594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2287506594
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.1786218609
Short name	T650
Test name
Test status
Simulation time	1797483007 ps
CPU time	4.7 seconds
Started	Mar 12 01:07:11 PM PDT 24
Finished	Mar 12 01:07:18 PM PDT 24
Peak memory	198136 kb
Host	smart-5d728fdb-6f7e-4751-9435-420448dad638
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1786218609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1786218609
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.2044831608
Short name	T380
Test name
Test status
Simulation time	17038843892 ps
CPU time	12.53 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:24 PM PDT 24
Peak memory	198520 kb
Host	smart-2d6d464b-313d-4bbd-9629-afb403cbc7ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044831608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2044831608
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.2103266948
Short name	T116
Test name
Test status
Simulation time	35825895249 ps
CPU time	9.03 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:20 PM PDT 24
Peak memory	195708 kb
Host	smart-7dad55d3-1195-4e34-8d88-b4dca431af88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2103266948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2103266948
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.248421024
Short name	T748
Test name
Test status
Simulation time	506157762 ps
CPU time	2.55 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:15 PM PDT 24
Peak memory	199844 kb
Host	smart-d6037b2c-27cb-4c7a-a4d2-57a5d7295902
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248421024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.248421024
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_stress_all.1128057289
Short name	T448
Test name
Test status
Simulation time	622785782906 ps
CPU time	464.74 seconds
Started	Mar 12 01:07:20 PM PDT 24
Finished	Mar 12 01:15:05 PM PDT 24
Peak memory	215992 kb
Host	smart-53e107dc-278b-49a2-a7e0-5178ee53ed74
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128057289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1128057289
Directory	/workspace/13.uart_stress_all/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.2450382691
Short name	T403
Test name
Test status
Simulation time	1481767029 ps
CPU time	2.05 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	198448 kb
Host	smart-73942927-89e8-475e-8b97-dd62f2a0d1af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450382691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2450382691
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.8999758
Short name	T830
Test name
Test status
Simulation time	37302803175 ps
CPU time	23.17 seconds
Started	Mar 12 01:07:11 PM PDT 24
Finished	Mar 12 01:07:37 PM PDT 24
Peak memory	198840 kb
Host	smart-7d3820de-f13b-4784-b06e-3f8c92258a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8999758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.8999758
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.1978859749
Short name	T682
Test name
Test status
Simulation time	8686951286 ps
CPU time	13.77 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:09:37 PM PDT 24
Peak memory	198416 kb
Host	smart-a9bcbe01-fef6-438b-b511-09771b705681
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978859749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1978859749
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.968692421
Short name	T175
Test name
Test status
Simulation time	123701560171 ps
CPU time	97.24 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:11:02 PM PDT 24
Peak memory	199896 kb
Host	smart-b2d50136-1ea4-43ee-a690-d0bba91ef711
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968692421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.968692421
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.3934145661
Short name	T285
Test name
Test status
Simulation time	17003456069 ps
CPU time	12.48 seconds
Started	Mar 12 01:09:22 PM PDT 24
Finished	Mar 12 01:09:35 PM PDT 24
Peak memory	199380 kb
Host	smart-c492d20b-4140-4d05-9e65-a802c80f5131
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934145661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3934145661
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.2722418093
Short name	T990
Test name
Test status
Simulation time	60973441558 ps
CPU time	26.72 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:09:52 PM PDT 24
Peak memory	199972 kb
Host	smart-e9fec6db-9b62-4a89-8678-0c177cd5be5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722418093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2722418093
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.4194567619
Short name	T144
Test name
Test status
Simulation time	217907755843 ps
CPU time	343.69 seconds
Started	Mar 12 01:09:29 PM PDT 24
Finished	Mar 12 01:15:13 PM PDT 24
Peak memory	200060 kb
Host	smart-e1186e06-720b-4038-bfba-fb7761dca3b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194567619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4194567619
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.3900727754
Short name	T691
Test name
Test status
Simulation time	21405548 ps
CPU time	0.56 seconds
Started	Mar 12 01:07:17 PM PDT 24
Finished	Mar 12 01:07:19 PM PDT 24
Peak memory	195520 kb
Host	smart-74431b01-c684-4b96-ade8-d34b25b5cd47
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900727754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3900727754
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.3106086503
Short name	T364
Test name
Test status
Simulation time	282093854467 ps
CPU time	74.44 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:08:26 PM PDT 24
Peak memory	200068 kb
Host	smart-89456175-2cfd-4793-941d-4fcfe28b4e1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3106086503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3106086503
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.3218607541
Short name	T536
Test name
Test status
Simulation time	57305130283 ps
CPU time	28.21 seconds
Started	Mar 12 01:07:11 PM PDT 24
Finished	Mar 12 01:07:42 PM PDT 24
Peak memory	199316 kb
Host	smart-08535da9-8ec1-4233-bb44-8d3b66851ae8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218607541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3218607541
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.879422919
Short name	T256
Test name
Test status
Simulation time	61147345910 ps
CPU time	88.09 seconds
Started	Mar 12 01:07:14 PM PDT 24
Finished	Mar 12 01:08:43 PM PDT 24
Peak memory	200044 kb
Host	smart-dc5f84a6-dbdf-4d22-9175-29191d8f127d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879422919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.879422919
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.2105973781
Short name	T959
Test name
Test status
Simulation time	28318153047 ps
CPU time	20.46 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:32 PM PDT 24
Peak memory	197576 kb
Host	smart-1a9d7c57-e5fd-4de1-92ff-7df7f2dc42cd
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105973781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2105973781
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.818719993
Short name	T460
Test name
Test status
Simulation time	233385295477 ps
CPU time	225.16 seconds
Started	Mar 12 01:07:19 PM PDT 24
Finished	Mar 12 01:11:04 PM PDT 24
Peak memory	200096 kb
Host	smart-0bb750d2-ad7e-445a-b42c-8cc573df8b54
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=818719993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.818719993
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.2205591543
Short name	T751
Test name
Test status
Simulation time	9102957512 ps
CPU time	15.98 seconds
Started	Mar 12 01:07:20 PM PDT 24
Finished	Mar 12 01:07:36 PM PDT 24
Peak memory	198584 kb
Host	smart-e6e4d1b9-00a2-465f-ae79-2ed15734e96e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205591543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2205591543
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.2009146965
Short name	T1111
Test name
Test status
Simulation time	46328001876 ps
CPU time	15.87 seconds
Started	Mar 12 01:07:11 PM PDT 24
Finished	Mar 12 01:07:29 PM PDT 24
Peak memory	198120 kb
Host	smart-cc0a75b1-417c-43a9-a02d-e6ab0fd069dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009146965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2009146965
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.695076821
Short name	T902
Test name
Test status
Simulation time	4650690633 ps
CPU time	10.41 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:22 PM PDT 24
Peak memory	199004 kb
Host	smart-5efd79e7-2cb3-4bcc-806f-135790b79c4c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=695076821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.695076821
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.1116448060
Short name	T332
Test name
Test status
Simulation time	57723220810 ps
CPU time	80.67 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	200092 kb
Host	smart-b2347cf1-dec1-43c7-ae40-0da23f68c677
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116448060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1116448060
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.3893213921
Short name	T927
Test name
Test status
Simulation time	6883573684 ps
CPU time	1.31 seconds
Started	Mar 12 01:07:14 PM PDT 24
Finished	Mar 12 01:07:16 PM PDT 24
Peak memory	195888 kb
Host	smart-4ba6805c-60a3-45be-93cd-18e1d0b58f8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893213921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3893213921
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.180201365
Short name	T577
Test name
Test status
Simulation time	473759871 ps
CPU time	1.19 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:13 PM PDT 24
Peak memory	198164 kb
Host	smart-0ddab8ed-bcfe-4645-91e1-bf2543f8060e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180201365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.180201365
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.123917723
Short name	T698
Test name
Test status
Simulation time	1733731796 ps
CPU time	2.44 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:16 PM PDT 24
Peak memory	198188 kb
Host	smart-369e5aed-d82a-4aac-b066-afe33aaf7f11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123917723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.123917723
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.3277298484
Short name	T572
Test name
Test status
Simulation time	31688384959 ps
CPU time	49.27 seconds
Started	Mar 12 01:07:25 PM PDT 24
Finished	Mar 12 01:08:15 PM PDT 24
Peak memory	199868 kb
Host	smart-1a928390-3b7f-4f8b-9d1f-40579d3a61b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277298484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3277298484
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.1710433918
Short name	T228
Test name
Test status
Simulation time	25540283691 ps
CPU time	37.83 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:10:03 PM PDT 24
Peak memory	200112 kb
Host	smart-0e96bf33-e627-4a4e-80c6-8e57eb359588
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710433918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1710433918
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.2949473160
Short name	T225
Test name
Test status
Simulation time	20931698075 ps
CPU time	38.5 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:10:01 PM PDT 24
Peak memory	200092 kb
Host	smart-7e1603fb-93b6-40dc-bae5-90ce41fc7e63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949473160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2949473160
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.1699887239
Short name	T929
Test name
Test status
Simulation time	51434700085 ps
CPU time	64.46 seconds
Started	Mar 12 01:09:24 PM PDT 24
Finished	Mar 12 01:10:29 PM PDT 24
Peak memory	200164 kb
Host	smart-49723200-36c5-4892-bcd4-055a9d1407c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699887239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1699887239
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.3821162844
Short name	T705
Test name
Test status
Simulation time	118902347736 ps
CPU time	116.96 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:11:20 PM PDT 24
Peak memory	200008 kb
Host	smart-df5e4ea8-1890-477e-9c80-9cfb2a750270
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821162844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3821162844
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.1816658657
Short name	T673
Test name
Test status
Simulation time	128902465991 ps
CPU time	53.07 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:10:19 PM PDT 24
Peak memory	200156 kb
Host	smart-babbc8c2-3953-4a04-9b20-485f860e18da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816658657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1816658657
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.396015339
Short name	T1108
Test name
Test status
Simulation time	116970709688 ps
CPU time	189.16 seconds
Started	Mar 12 01:09:34 PM PDT 24
Finished	Mar 12 01:12:43 PM PDT 24
Peak memory	200104 kb
Host	smart-b1dd2c07-34fc-4656-8141-c4d4bda5c00a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396015339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.396015339
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.264606298
Short name	T260
Test name
Test status
Simulation time	48755509491 ps
CPU time	31.93 seconds
Started	Mar 12 01:09:32 PM PDT 24
Finished	Mar 12 01:10:04 PM PDT 24
Peak memory	199816 kb
Host	smart-47244503-5a07-4dee-820c-dc5df1a1606e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264606298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.264606298
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.3130821577
Short name	T956
Test name
Test status
Simulation time	27353847464 ps
CPU time	22.2 seconds
Started	Mar 12 01:09:33 PM PDT 24
Finished	Mar 12 01:09:56 PM PDT 24
Peak memory	200116 kb
Host	smart-096ef8e3-f24e-44e1-a8ba-40b82929560c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130821577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3130821577
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.963537273
Short name	T816
Test name
Test status
Simulation time	13713407 ps
CPU time	0.56 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:07:37 PM PDT 24
Peak memory	195540 kb
Host	smart-b680baad-0538-4519-aab3-71ba3e7682c7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963537273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.963537273
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.2116438985
Short name	T560
Test name
Test status
Simulation time	136894260661 ps
CPU time	107.45 seconds
Started	Mar 12 01:07:13 PM PDT 24
Finished	Mar 12 01:09:02 PM PDT 24
Peak memory	200196 kb
Host	smart-5801558c-f70d-4df0-a705-582927b429d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116438985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2116438985
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.686605050
Short name	T327
Test name
Test status
Simulation time	11663372374 ps
CPU time	25.77 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:39 PM PDT 24
Peak memory	199488 kb
Host	smart-85be3c26-9c85-46a9-b33d-ed54f34f0a0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686605050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.686605050
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_intr.2386021935
Short name	T23
Test name
Test status
Simulation time	97658977700 ps
CPU time	45.56 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:58 PM PDT 24
Peak memory	200136 kb
Host	smart-572adbf5-2acb-40bb-a632-4ce573ef3051
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386021935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2386021935
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.3713785750
Short name	T991
Test name
Test status
Simulation time	75902881280 ps
CPU time	102.13 seconds
Started	Mar 12 01:07:30 PM PDT 24
Finished	Mar 12 01:09:13 PM PDT 24
Peak memory	200100 kb
Host	smart-c1ad0dde-32e0-4b87-8c21-0cd7fcb6f7de
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3713785750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3713785750
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_loopback.2241403976
Short name	T612
Test name
Test status
Simulation time	5199669300 ps
CPU time	3.01 seconds
Started	Mar 12 01:07:17 PM PDT 24
Finished	Mar 12 01:07:24 PM PDT 24
Peak memory	197528 kb
Host	smart-15d3dc69-9459-4277-a481-b2e2a0225d5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241403976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2241403976
Directory	/workspace/15.uart_loopback/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.4259632596
Short name	T490
Test name
Test status
Simulation time	44738158029 ps
CPU time	17.88 seconds
Started	Mar 12 01:07:31 PM PDT 24
Finished	Mar 12 01:07:49 PM PDT 24
Peak memory	195764 kb
Host	smart-f4306834-9a0e-4b26-9072-51843393f3e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259632596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4259632596
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_perf.968814446
Short name	T707
Test name
Test status
Simulation time	24599891982 ps
CPU time	188.98 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:10:47 PM PDT 24
Peak memory	200092 kb
Host	smart-806b4ebe-f9f3-4e23-9622-f7481fae0efe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=968814446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.968814446
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.2456586635
Short name	T17
Test name
Test status
Simulation time	4593147561 ps
CPU time	35.77 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:48 PM PDT 24
Peak memory	198868 kb
Host	smart-ad39caa1-4473-4f4d-9e7a-07e2804a0338
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2456586635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2456586635
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.2834157339
Short name	T1046
Test name
Test status
Simulation time	181913552585 ps
CPU time	52.97 seconds
Started	Mar 12 01:07:33 PM PDT 24
Finished	Mar 12 01:08:27 PM PDT 24
Peak memory	200088 kb
Host	smart-6cb56b69-b159-4128-831b-fe239033ea39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834157339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2834157339
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.748359686
Short name	T805
Test name
Test status
Simulation time	42122086121 ps
CPU time	17.15 seconds
Started	Mar 12 01:07:39 PM PDT 24
Finished	Mar 12 01:07:56 PM PDT 24
Peak memory	195732 kb
Host	smart-176633a1-65f0-4e57-bbd1-7971f1d085de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748359686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.748359686
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.86288303
Short name	T611
Test name
Test status
Simulation time	6347466211 ps
CPU time	6.24 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	198884 kb
Host	smart-de6fd27a-0704-4faf-86b3-deccf3af5165
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86288303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.86288303
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_stress_all.2693289695
Short name	T744
Test name
Test status
Simulation time	157980520081 ps
CPU time	474.28 seconds
Started	Mar 12 01:07:27 PM PDT 24
Finished	Mar 12 01:15:22 PM PDT 24
Peak memory	200084 kb
Host	smart-2c0e0a1c-dd45-4d44-a5f8-6d60acd98cb1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693289695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2693289695
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/15.uart_stress_all_with_rand_reset.1721070215
Short name	T42
Test name
Test status
Simulation time	72398007463 ps
CPU time	208.24 seconds
Started	Mar 12 01:07:17 PM PDT 24
Finished	Mar 12 01:10:47 PM PDT 24
Peak memory	208512 kb
Host	smart-64bd5800-eb2b-49c5-858a-339231df6853
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721070215 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1721070215
Directory	/workspace/15.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.1037596193
Short name	T633
Test name
Test status
Simulation time	1736205540 ps
CPU time	2.04 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:07:48 PM PDT 24
Peak memory	198340 kb
Host	smart-39535e08-8ad9-4965-96b2-7ae6d84043d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037596193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1037596193
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.48583522
Short name	T181
Test name
Test status
Simulation time	11314185547 ps
CPU time	24.93 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:37 PM PDT 24
Peak memory	200128 kb
Host	smart-a18181f1-accf-45c3-adcb-d7b23b665f56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48583522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.48583522
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.4233213577
Short name	T166
Test name
Test status
Simulation time	35239073397 ps
CPU time	16.14 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:09:53 PM PDT 24
Peak memory	200004 kb
Host	smart-323322cb-be2c-40e4-9788-c4779ef215e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233213577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.4233213577
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.1710434069
Short name	T200
Test name
Test status
Simulation time	37382719445 ps
CPU time	54.46 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:10:32 PM PDT 24
Peak memory	200092 kb
Host	smart-cdc2c350-24c9-40be-bf78-17b0c498ae27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710434069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1710434069
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.452788503
Short name	T282
Test name
Test status
Simulation time	31901017546 ps
CPU time	13.95 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:09:52 PM PDT 24
Peak memory	198752 kb
Host	smart-fd15e20f-8703-4fd2-bd76-ca23ce9f1ad2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452788503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.452788503
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.1535829755
Short name	T937
Test name
Test status
Simulation time	82105349152 ps
CPU time	28.53 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:06 PM PDT 24
Peak memory	197880 kb
Host	smart-d6fd8638-c99a-4e66-b322-7707d8dd8453
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535829755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1535829755
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.265859111
Short name	T609
Test name
Test status
Simulation time	91501097225 ps
CPU time	33.12 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:09 PM PDT 24
Peak memory	200096 kb
Host	smart-7db044cc-4c6e-4641-8edc-2bfc0a5e8ca5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265859111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.265859111
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.1532232545
Short name	T130
Test name
Test status
Simulation time	42481962774 ps
CPU time	31.45 seconds
Started	Mar 12 01:09:39 PM PDT 24
Finished	Mar 12 01:10:11 PM PDT 24
Peak memory	200116 kb
Host	smart-3500b32f-b620-40a6-9fca-ff3c40a8b3a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532232545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1532232545
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.3834707354
Short name	T870
Test name
Test status
Simulation time	91676851369 ps
CPU time	144.48 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:12:01 PM PDT 24
Peak memory	200132 kb
Host	smart-0eb5d795-bd74-4c6d-8304-e8ac85bff43a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834707354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3834707354
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.2254981108
Short name	T133
Test name
Test status
Simulation time	19001734268 ps
CPU time	32.45 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:08 PM PDT 24
Peak memory	200088 kb
Host	smart-c353714d-551a-4447-8814-74e6696051c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254981108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2254981108
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.2054615271
Short name	T361
Test name
Test status
Simulation time	31710973068 ps
CPU time	25.89 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:03 PM PDT 24
Peak memory	199856 kb
Host	smart-961d2759-ffe3-47d3-8bc9-90f0e293d466
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054615271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2054615271
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.5007535
Short name	T747
Test name
Test status
Simulation time	12378761 ps
CPU time	0.53 seconds
Started	Mar 12 01:07:20 PM PDT 24
Finished	Mar 12 01:07:21 PM PDT 24
Peak memory	194696 kb
Host	smart-d005dc21-885c-4ca2-bc5c-e590abdd242d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5007535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.5007535
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.889923014
Short name	T652
Test name
Test status
Simulation time	34230793162 ps
CPU time	48.06 seconds
Started	Mar 12 01:07:29 PM PDT 24
Finished	Mar 12 01:08:19 PM PDT 24
Peak memory	199680 kb
Host	smart-f3aa8da2-a49f-402b-84d9-ea51567e5dd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889923014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.889923014
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.2882560484
Short name	T274
Test name
Test status
Simulation time	182199014156 ps
CPU time	153.34 seconds
Started	Mar 12 01:07:33 PM PDT 24
Finished	Mar 12 01:10:06 PM PDT 24
Peak memory	199652 kb
Host	smart-c84a3942-0b18-4b8f-b4cc-4f79a19f368f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882560484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2882560484
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_intr.3512679425
Short name	T712
Test name
Test status
Simulation time	32293382224 ps
CPU time	40.39 seconds
Started	Mar 12 01:07:16 PM PDT 24
Finished	Mar 12 01:07:58 PM PDT 24
Peak memory	199600 kb
Host	smart-246828e4-8ff5-4375-a4b9-1c0fd0654f14
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512679425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3512679425
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.2331590133
Short name	T858
Test name
Test status
Simulation time	151575470982 ps
CPU time	299.67 seconds
Started	Mar 12 01:07:32 PM PDT 24
Finished	Mar 12 01:12:32 PM PDT 24
Peak memory	200144 kb
Host	smart-5bc6ecf1-1574-4803-8bd2-0af34307388c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2331590133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2331590133
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.1852306654
Short name	T940
Test name
Test status
Simulation time	5347807884 ps
CPU time	6.01 seconds
Started	Mar 12 01:07:24 PM PDT 24
Finished	Mar 12 01:07:30 PM PDT 24
Peak memory	198904 kb
Host	smart-e6bba51e-2fc4-4e30-9db9-17200281742c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852306654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1852306654
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.2576094880
Short name	T1024
Test name
Test status
Simulation time	30791523276 ps
CPU time	23.56 seconds
Started	Mar 12 01:07:26 PM PDT 24
Finished	Mar 12 01:07:50 PM PDT 24
Peak memory	198700 kb
Host	smart-1bb0fa98-810f-4d0d-ae11-3392050f9307
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576094880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2576094880
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.1631953341
Short name	T844
Test name
Test status
Simulation time	18596869010 ps
CPU time	534.61 seconds
Started	Mar 12 01:07:17 PM PDT 24
Finished	Mar 12 01:16:12 PM PDT 24
Peak memory	200000 kb
Host	smart-0ef90434-9426-4a25-8a50-df939a1e9495
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1631953341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1631953341
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.4034714536
Short name	T799
Test name
Test status
Simulation time	1603882851 ps
CPU time	2.01 seconds
Started	Mar 12 01:07:43 PM PDT 24
Finished	Mar 12 01:07:45 PM PDT 24
Peak memory	197764 kb
Host	smart-d0f5380c-b21e-4a63-a100-a3a418ad8cc2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4034714536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.4034714536
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.227547785
Short name	T429
Test name
Test status
Simulation time	250884927726 ps
CPU time	58.62 seconds
Started	Mar 12 01:07:35 PM PDT 24
Finished	Mar 12 01:08:34 PM PDT 24
Peak memory	200100 kb
Host	smart-86763fcd-7361-40c9-8737-19dc1e12c07c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227547785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.227547785
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.687141608
Short name	T425
Test name
Test status
Simulation time	30294000790 ps
CPU time	22.39 seconds
Started	Mar 12 01:07:26 PM PDT 24
Finished	Mar 12 01:07:49 PM PDT 24
Peak memory	195892 kb
Host	smart-0b61e77b-3ba3-41c6-ba91-1da41db86b05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687141608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.687141608
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.182069958
Short name	T417
Test name
Test status
Simulation time	5381915050 ps
CPU time	8.39 seconds
Started	Mar 12 01:07:24 PM PDT 24
Finished	Mar 12 01:07:32 PM PDT 24
Peak memory	199444 kb
Host	smart-09229df0-2200-4c93-967a-481c49bfbe8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182069958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.182069958
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_stress_all.3267343318
Short name	T666
Test name
Test status
Simulation time	170515254077 ps
CPU time	318.18 seconds
Started	Mar 12 01:07:27 PM PDT 24
Finished	Mar 12 01:12:46 PM PDT 24
Peak memory	200072 kb
Host	smart-644d8466-8cf1-4ade-bb73-019781438c1a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267343318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3267343318
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_stress_all_with_rand_reset.4091782994
Short name	T58
Test name
Test status
Simulation time	31141239116 ps
CPU time	307.75 seconds
Started	Mar 12 01:07:18 PM PDT 24
Finished	Mar 12 01:12:26 PM PDT 24
Peak memory	215948 kb
Host	smart-3b89128d-b4f4-4e0c-89a9-04b8e2ff87c3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091782994 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.4091782994
Directory	/workspace/16.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.261172594
Short name	T1081
Test name
Test status
Simulation time	998311682 ps
CPU time	1.91 seconds
Started	Mar 12 01:07:22 PM PDT 24
Finished	Mar 12 01:07:24 PM PDT 24
Peak memory	198980 kb
Host	smart-b9743068-07c3-4a45-95fb-4960aa18cc94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=261172594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.261172594
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.2280023364
Short name	T897
Test name
Test status
Simulation time	27441801018 ps
CPU time	45.02 seconds
Started	Mar 12 01:07:25 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	200120 kb
Host	smart-3b7566f3-b2e5-4bca-90bd-3b31ad5f0a4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280023364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2280023364
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.3186213202
Short name	T160
Test name
Test status
Simulation time	225273082265 ps
CPU time	109.01 seconds
Started	Mar 12 01:09:34 PM PDT 24
Finished	Mar 12 01:11:23 PM PDT 24
Peak memory	200124 kb
Host	smart-4480accd-2ea0-4dc9-bc1b-5467d170f800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186213202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3186213202
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.334046168
Short name	T351
Test name
Test status
Simulation time	7223479971 ps
CPU time	11.7 seconds
Started	Mar 12 01:09:33 PM PDT 24
Finished	Mar 12 01:09:45 PM PDT 24
Peak memory	199272 kb
Host	smart-deca470c-4034-416e-8938-9847c77cebe9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=334046168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.334046168
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.2113155462
Short name	T1042
Test name
Test status
Simulation time	112325538507 ps
CPU time	54.53 seconds
Started	Mar 12 01:09:33 PM PDT 24
Finished	Mar 12 01:10:28 PM PDT 24
Peak memory	200112 kb
Host	smart-cd248924-902e-4717-be78-adc485372a8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113155462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2113155462
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.1081631638
Short name	T722
Test name
Test status
Simulation time	71576432188 ps
CPU time	17.06 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:09:54 PM PDT 24
Peak memory	198892 kb
Host	smart-b55546f1-8a90-4e18-a57b-b67cdc836436
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081631638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1081631638
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.1347956077
Short name	T210
Test name
Test status
Simulation time	33239486437 ps
CPU time	20.97 seconds
Started	Mar 12 01:09:36 PM PDT 24
Finished	Mar 12 01:09:57 PM PDT 24
Peak memory	200120 kb
Host	smart-64f71436-a34b-407d-ad79-85043bef7a59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347956077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1347956077
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.3429134037
Short name	T262
Test name
Test status
Simulation time	45208568971 ps
CPU time	20.28 seconds
Started	Mar 12 01:09:39 PM PDT 24
Finished	Mar 12 01:10:00 PM PDT 24
Peak memory	199536 kb
Host	smart-85346f7f-d479-46f6-bd83-874b1e7b0a16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429134037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3429134037
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.2466149824
Short name	T512
Test name
Test status
Simulation time	17334502890 ps
CPU time	13.9 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:09:52 PM PDT 24
Peak memory	199528 kb
Host	smart-d1b883a8-383e-4d03-86b2-e36791a1c964
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466149824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2466149824
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.1911302619
Short name	T1121
Test name
Test status
Simulation time	96067319697 ps
CPU time	43.99 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:20 PM PDT 24
Peak memory	200104 kb
Host	smart-78339be9-39b3-4034-8dc1-4d7a82697350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1911302619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1911302619
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.2808475498
Short name	T1103
Test name
Test status
Simulation time	22869010539 ps
CPU time	42.58 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:10:20 PM PDT 24
Peak memory	200004 kb
Host	smart-49604c9c-1eb5-44fc-affc-ff2f8cb61fc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808475498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2808475498
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.2633108419
Short name	T834
Test name
Test status
Simulation time	12886114 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:25 PM PDT 24
Finished	Mar 12 01:07:26 PM PDT 24
Peak memory	194484 kb
Host	smart-e2f919ee-41b8-4e72-b946-1cd02ddbeda4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633108419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2633108419
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.475556067
Short name	T118
Test name
Test status
Simulation time	18415992468 ps
CPU time	29.27 seconds
Started	Mar 12 01:07:35 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	200056 kb
Host	smart-a646e34a-a71a-408e-afab-ea82eb59191b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475556067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.475556067
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.2668119631
Short name	T284
Test name
Test status
Simulation time	148936910199 ps
CPU time	206.43 seconds
Started	Mar 12 01:07:16 PM PDT 24
Finished	Mar 12 01:10:43 PM PDT 24
Peak memory	199248 kb
Host	smart-a2177df0-49d1-45ee-adc7-e2849c94e513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668119631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2668119631
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_fifo_reset.1871075222
Short name	T1063
Test name
Test status
Simulation time	20503698591 ps
CPU time	36.85 seconds
Started	Mar 12 01:07:24 PM PDT 24
Finished	Mar 12 01:08:01 PM PDT 24
Peak memory	200048 kb
Host	smart-28708f29-606c-460a-a125-39a2581f1fb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871075222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1871075222
Directory	/workspace/17.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_intr.3434246821
Short name	T954
Test name
Test status
Simulation time	28208625392 ps
CPU time	20.73 seconds
Started	Mar 12 01:07:25 PM PDT 24
Finished	Mar 12 01:07:46 PM PDT 24
Peak memory	200148 kb
Host	smart-97050dd8-5eed-49ea-b671-d24e0632e6c9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434246821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3434246821
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.1721425222
Short name	T50
Test name
Test status
Simulation time	239255310971 ps
CPU time	573.92 seconds
Started	Mar 12 01:07:34 PM PDT 24
Finished	Mar 12 01:17:08 PM PDT 24
Peak memory	200180 kb
Host	smart-5f1bae35-0ebe-48ab-afbe-c9de3b40ba12
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1721425222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1721425222
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.363272278
Short name	T456
Test name
Test status
Simulation time	6836105474 ps
CPU time	5.75 seconds
Started	Mar 12 01:07:24 PM PDT 24
Finished	Mar 12 01:07:29 PM PDT 24
Peak memory	198400 kb
Host	smart-9b6ba331-d61a-43e2-a58c-f51ff6113bc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363272278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.363272278
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.3531734364
Short name	T889
Test name
Test status
Simulation time	85276061234 ps
CPU time	100.6 seconds
Started	Mar 12 01:07:31 PM PDT 24
Finished	Mar 12 01:09:12 PM PDT 24
Peak memory	200172 kb
Host	smart-97472f98-7363-4873-a373-51be13b8e84b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531734364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3531734364
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.3270105185
Short name	T155
Test name
Test status
Simulation time	17392315691 ps
CPU time	114.71 seconds
Started	Mar 12 01:07:42 PM PDT 24
Finished	Mar 12 01:09:37 PM PDT 24
Peak memory	200080 kb
Host	smart-da4d03b6-299c-40e9-bca7-9614513e7d43
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3270105185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3270105185
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.3676322322
Short name	T864
Test name
Test status
Simulation time	1714679790 ps
CPU time	1.89 seconds
Started	Mar 12 01:07:21 PM PDT 24
Finished	Mar 12 01:07:24 PM PDT 24
Peak memory	197772 kb
Host	smart-2b2b5d9e-bc6e-40a7-92fb-b6a36777102d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3676322322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3676322322
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.1704125332
Short name	T319
Test name
Test status
Simulation time	113941097331 ps
CPU time	170.02 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:10:39 PM PDT 24
Peak memory	199640 kb
Host	smart-b6848eef-0473-474b-bc7e-49a755f5715d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704125332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1704125332
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.74468669
Short name	T962
Test name
Test status
Simulation time	5743722758 ps
CPU time	6.52 seconds
Started	Mar 12 01:07:18 PM PDT 24
Finished	Mar 12 01:07:25 PM PDT 24
Peak memory	195892 kb
Host	smart-9c99d04e-bf69-4af3-8438-1f855ac675af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74468669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.74468669
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.4209527429
Short name	T780
Test name
Test status
Simulation time	6052247753 ps
CPU time	18.41 seconds
Started	Mar 12 01:07:28 PM PDT 24
Finished	Mar 12 01:07:47 PM PDT 24
Peak memory	199480 kb
Host	smart-c5662888-7b2f-410a-8951-c8aef1972a7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209527429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4209527429
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_stress_all.3231065040
Short name	T220
Test name
Test status
Simulation time	126725303615 ps
CPU time	715.22 seconds
Started	Mar 12 01:07:28 PM PDT 24
Finished	Mar 12 01:19:24 PM PDT 24
Peak memory	200164 kb
Host	smart-6222272c-9bbf-48c1-bbe8-f811b4a3a497
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231065040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3231065040
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.2524441843
Short name	T810
Test name
Test status
Simulation time	627324170 ps
CPU time	2.7 seconds
Started	Mar 12 01:07:32 PM PDT 24
Finished	Mar 12 01:07:36 PM PDT 24
Peak memory	198704 kb
Host	smart-58fead51-ed13-42d3-bd0d-d08071478f1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524441843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2524441843
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.1112012329
Short name	T895
Test name
Test status
Simulation time	88041578587 ps
CPU time	117.36 seconds
Started	Mar 12 01:07:16 PM PDT 24
Finished	Mar 12 01:09:14 PM PDT 24
Peak memory	200140 kb
Host	smart-cf6712c9-73e9-4d82-b94a-b788bda6254a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112012329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1112012329
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.1032252419
Short name	T255
Test name
Test status
Simulation time	434770204418 ps
CPU time	36.07 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:11 PM PDT 24
Peak memory	200152 kb
Host	smart-10d143c3-492f-4845-a63c-f5c80c28a344
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032252419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1032252419
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.3091643845
Short name	T329
Test name
Test status
Simulation time	32569357546 ps
CPU time	54.99 seconds
Started	Mar 12 01:09:34 PM PDT 24
Finished	Mar 12 01:10:29 PM PDT 24
Peak memory	200136 kb
Host	smart-5a5d7796-17e0-4f29-a8e3-0929dbb96cfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091643845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3091643845
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/172.uart_fifo_reset.1316481264
Short name	T131
Test name
Test status
Simulation time	7355207020 ps
CPU time	12.82 seconds
Started	Mar 12 01:09:36 PM PDT 24
Finished	Mar 12 01:09:49 PM PDT 24
Peak memory	199008 kb
Host	smart-7b915316-80f1-497a-9689-8da5778a8cdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316481264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1316481264
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.1491099027
Short name	T892
Test name
Test status
Simulation time	136056084461 ps
CPU time	17.39 seconds
Started	Mar 12 01:09:33 PM PDT 24
Finished	Mar 12 01:09:51 PM PDT 24
Peak memory	200124 kb
Host	smart-b33b813f-7056-416c-aa1b-020c34754959
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491099027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1491099027
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.1642217093
Short name	T156
Test name
Test status
Simulation time	136810349399 ps
CPU time	31.16 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:10:09 PM PDT 24
Peak memory	199840 kb
Host	smart-426816e7-e83e-4598-8348-58fce64068bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642217093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1642217093
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.2261040549
Short name	T184
Test name
Test status
Simulation time	16050807071 ps
CPU time	26.98 seconds
Started	Mar 12 01:09:32 PM PDT 24
Finished	Mar 12 01:09:59 PM PDT 24
Peak memory	199924 kb
Host	smart-cb5ce646-fc40-445c-8823-1d34760035f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261040549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2261040549
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.1596313475
Short name	T310
Test name
Test status
Simulation time	12865232720 ps
CPU time	12.28 seconds
Started	Mar 12 01:09:36 PM PDT 24
Finished	Mar 12 01:09:49 PM PDT 24
Peak memory	199676 kb
Host	smart-1df539c0-0ab2-4516-bc62-3e7605768faf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596313475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1596313475
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.3908672715
Short name	T1120
Test name
Test status
Simulation time	26484814669 ps
CPU time	43.92 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:21 PM PDT 24
Peak memory	200180 kb
Host	smart-8a2988c8-9f0f-431f-b833-4679e96c0161
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908672715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3908672715
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.926793960
Short name	T1032
Test name
Test status
Simulation time	79031398368 ps
CPU time	30.72 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:10:09 PM PDT 24
Peak memory	199840 kb
Host	smart-a549e40a-5ed2-404d-8579-ab0b7892e9ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926793960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.926793960
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.331592795
Short name	T232
Test name
Test status
Simulation time	24675972663 ps
CPU time	44.17 seconds
Started	Mar 12 01:09:32 PM PDT 24
Finished	Mar 12 01:10:16 PM PDT 24
Peak memory	200144 kb
Host	smart-d1c9ef2c-115f-4d4e-a91e-99351a89486b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331592795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.331592795
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_alert_test.4062693091
Short name	T847
Test name
Test status
Simulation time	36923469 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:35 PM PDT 24
Finished	Mar 12 01:07:36 PM PDT 24
Peak memory	194480 kb
Host	smart-e981b166-7f0a-4d35-a48c-658ba9938375
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062693091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4062693091
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.3055792879
Short name	T893
Test name
Test status
Simulation time	92810468957 ps
CPU time	10.88 seconds
Started	Mar 12 01:07:16 PM PDT 24
Finished	Mar 12 01:07:32 PM PDT 24
Peak memory	198840 kb
Host	smart-054de8ae-160f-4fbc-92bb-2992961d7c63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055792879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3055792879
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.2518264295
Short name	T973
Test name
Test status
Simulation time	109247429389 ps
CPU time	118.17 seconds
Started	Mar 12 01:07:29 PM PDT 24
Finished	Mar 12 01:09:29 PM PDT 24
Peak memory	200168 kb
Host	smart-0d6f3e17-1a2f-4676-bcb7-69ef820a617d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518264295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2518264295
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.3598167050
Short name	T208
Test name
Test status
Simulation time	21586081754 ps
CPU time	17.79 seconds
Started	Mar 12 01:07:22 PM PDT 24
Finished	Mar 12 01:07:40 PM PDT 24
Peak memory	199108 kb
Host	smart-691c4e52-4ce3-468d-89fa-e5ba19b0329f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598167050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3598167050
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_intr.320366950
Short name	T693
Test name
Test status
Simulation time	22115695672 ps
CPU time	7.14 seconds
Started	Mar 12 01:07:23 PM PDT 24
Finished	Mar 12 01:07:31 PM PDT 24
Peak memory	196968 kb
Host	smart-b1334f57-7471-403b-9b0a-6125328ba80b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320366950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.320366950
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_long_xfer_wo_dly.2392947987
Short name	T655
Test name
Test status
Simulation time	99560769648 ps
CPU time	250.31 seconds
Started	Mar 12 01:07:31 PM PDT 24
Finished	Mar 12 01:11:42 PM PDT 24
Peak memory	200092 kb
Host	smart-8e917df3-bef3-4a82-a852-b3ecfee08392
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2392947987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2392947987
Directory	/workspace/18.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/18.uart_loopback.229285373
Short name	T489
Test name
Test status
Simulation time	5280404979 ps
CPU time	6.22 seconds
Started	Mar 12 01:07:18 PM PDT 24
Finished	Mar 12 01:07:25 PM PDT 24
Peak memory	198284 kb
Host	smart-d04035f9-ee50-479b-b76c-0fa443196e55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229285373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.229285373
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.205169082
Short name	T1009
Test name
Test status
Simulation time	115697212927 ps
CPU time	51.08 seconds
Started	Mar 12 01:07:36 PM PDT 24
Finished	Mar 12 01:08:28 PM PDT 24
Peak memory	199316 kb
Host	smart-357c5ff0-4bce-47cd-b0c8-416aa5262aad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205169082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.205169082
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.4291842692
Short name	T484
Test name
Test status
Simulation time	11551757350 ps
CPU time	272.36 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:12:09 PM PDT 24
Peak memory	200172 kb
Host	smart-b1d08fdd-0f4a-49d7-a24a-5f04e7626772
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4291842692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4291842692
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.4006871261
Short name	T71
Test name
Test status
Simulation time	6100780227 ps
CPU time	49.76 seconds
Started	Mar 12 01:07:27 PM PDT 24
Finished	Mar 12 01:08:17 PM PDT 24
Peak memory	198932 kb
Host	smart-bf19ff8e-5663-4b72-b62c-99daae7f0cfa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4006871261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4006871261
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.279356670
Short name	T678
Test name
Test status
Simulation time	37685359869 ps
CPU time	15.69 seconds
Started	Mar 12 01:07:34 PM PDT 24
Finished	Mar 12 01:07:50 PM PDT 24
Peak memory	198260 kb
Host	smart-6ab979a6-52c1-43cd-8d24-121d7dfa652f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279356670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.279356670
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.1504991896
Short name	T412
Test name
Test status
Simulation time	2275403611 ps
CPU time	1.13 seconds
Started	Mar 12 01:07:29 PM PDT 24
Finished	Mar 12 01:07:32 PM PDT 24
Peak memory	195588 kb
Host	smart-560f81d0-6e5f-4d68-9ec8-a27596df5b8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504991896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1504991896
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.716527911
Short name	T463
Test name
Test status
Simulation time	281421776 ps
CPU time	1.08 seconds
Started	Mar 12 01:07:42 PM PDT 24
Finished	Mar 12 01:07:43 PM PDT 24
Peak memory	198072 kb
Host	smart-e66d718b-5803-4a49-aada-5d3060eeadfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716527911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.716527911
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_stress_all_with_rand_reset.3550982208
Short name	T757
Test name
Test status
Simulation time	41898104647 ps
CPU time	585.89 seconds
Started	Mar 12 01:07:21 PM PDT 24
Finished	Mar 12 01:17:08 PM PDT 24
Peak memory	215792 kb
Host	smart-3151a9a8-fda3-44f3-87b2-636906153bc8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550982208 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3550982208
Directory	/workspace/18.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.659806797
Short name	T903
Test name
Test status
Simulation time	1944821053 ps
CPU time	1.53 seconds
Started	Mar 12 01:07:29 PM PDT 24
Finished	Mar 12 01:07:32 PM PDT 24
Peak memory	197816 kb
Host	smart-d4925d9f-8135-408c-955d-c0fdacd22a47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659806797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.659806797
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.1461506333
Short name	T159
Test name
Test status
Simulation time	37734592424 ps
CPU time	15.28 seconds
Started	Mar 12 01:07:36 PM PDT 24
Finished	Mar 12 01:07:51 PM PDT 24
Peak memory	200048 kb
Host	smart-af217c9a-1308-4bcc-aa28-472556da0951
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461506333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1461506333
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.4269663471
Short name	T1087
Test name
Test status
Simulation time	88002829805 ps
CPU time	82.77 seconds
Started	Mar 12 01:09:34 PM PDT 24
Finished	Mar 12 01:10:57 PM PDT 24
Peak memory	200108 kb
Host	smart-f42a4450-7be9-4620-933e-fe8097951696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269663471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.4269663471
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.937831759
Short name	T769
Test name
Test status
Simulation time	57730152887 ps
CPU time	41.28 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:17 PM PDT 24
Peak memory	199660 kb
Host	smart-1c265643-868f-4c16-b582-3ee3073ac1b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937831759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.937831759
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.4015383918
Short name	T930
Test name
Test status
Simulation time	63858962931 ps
CPU time	102.78 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:11:20 PM PDT 24
Peak memory	199352 kb
Host	smart-cca97f75-0439-4609-a973-3bccb3200d67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015383918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4015383918
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.2716331771
Short name	T169
Test name
Test status
Simulation time	91738048947 ps
CPU time	156.14 seconds
Started	Mar 12 01:09:34 PM PDT 24
Finished	Mar 12 01:12:10 PM PDT 24
Peak memory	200044 kb
Host	smart-10e1485a-476f-4eff-8f52-4159f0f858d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716331771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2716331771
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.948555647
Short name	T270
Test name
Test status
Simulation time	97007773842 ps
CPU time	49.86 seconds
Started	Mar 12 01:09:36 PM PDT 24
Finished	Mar 12 01:10:26 PM PDT 24
Peak memory	200104 kb
Host	smart-4a08bf30-9773-4166-9c85-4dc297196e81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948555647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.948555647
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.251521802
Short name	T884
Test name
Test status
Simulation time	25028154984 ps
CPU time	17.71 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:09:53 PM PDT 24
Peak memory	200100 kb
Host	smart-0a98c4a6-f3dc-42db-a82c-cd8724c5327b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251521802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.251521802
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.338009874
Short name	T994
Test name
Test status
Simulation time	87649465664 ps
CPU time	64.61 seconds
Started	Mar 12 01:09:32 PM PDT 24
Finished	Mar 12 01:10:37 PM PDT 24
Peak memory	200060 kb
Host	smart-7b4df452-58ee-4ab1-a413-aca7709c8efa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338009874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.338009874
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.4255121708
Short name	T164
Test name
Test status
Simulation time	22182326341 ps
CPU time	36.39 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:14 PM PDT 24
Peak memory	198368 kb
Host	smart-18aa5c7a-fcbf-4266-be8b-1f7c2492ff2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255121708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4255121708
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.1100487053
Short name	T596
Test name
Test status
Simulation time	20264092 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:30 PM PDT 24
Finished	Mar 12 01:07:31 PM PDT 24
Peak memory	195464 kb
Host	smart-d6d722f9-bc56-4760-8d1f-16547b33b5cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100487053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1100487053
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.3312843058
Short name	T199
Test name
Test status
Simulation time	117176725135 ps
CPU time	43.27 seconds
Started	Mar 12 01:07:30 PM PDT 24
Finished	Mar 12 01:08:14 PM PDT 24
Peak memory	200192 kb
Host	smart-d9196e72-33f9-4a04-9bb2-ec9151f23dad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312843058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3312843058
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.1461636489
Short name	T758
Test name
Test status
Simulation time	157148714902 ps
CPU time	200.18 seconds
Started	Mar 12 01:07:29 PM PDT 24
Finished	Mar 12 01:10:51 PM PDT 24
Peak memory	200144 kb
Host	smart-c5802074-da26-44a8-a253-446b65a5b1a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461636489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1461636489
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.1685457909
Short name	T190
Test name
Test status
Simulation time	45641692832 ps
CPU time	44.09 seconds
Started	Mar 12 01:07:33 PM PDT 24
Finished	Mar 12 01:08:17 PM PDT 24
Peak memory	199092 kb
Host	smart-ef91b828-479a-4b48-b7db-fd404ccea259
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685457909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1685457909
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_intr.353425296
Short name	T475
Test name
Test status
Simulation time	5908546298 ps
CPU time	5.23 seconds
Started	Mar 12 01:07:39 PM PDT 24
Finished	Mar 12 01:07:44 PM PDT 24
Peak memory	195580 kb
Host	smart-f619533a-3507-4742-a981-a8c1ec42e3c9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353425296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.353425296
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.166571695
Short name	T752
Test name
Test status
Simulation time	70082859941 ps
CPU time	595.23 seconds
Started	Mar 12 01:07:30 PM PDT 24
Finished	Mar 12 01:17:26 PM PDT 24
Peak memory	200088 kb
Host	smart-3aeb3d6d-3315-4742-99e3-2f5ea4ac24fc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=166571695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.166571695
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/19.uart_loopback.3977875570
Short name	T820
Test name
Test status
Simulation time	4047970931 ps
CPU time	4.42 seconds
Started	Mar 12 01:07:32 PM PDT 24
Finished	Mar 12 01:07:37 PM PDT 24
Peak memory	196940 kb
Host	smart-7e8acf9d-7964-471a-9fd6-aa6f0b5a1e6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977875570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3977875570
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.4276213809
Short name	T623
Test name
Test status
Simulation time	53562982078 ps
CPU time	96.44 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:09:21 PM PDT 24
Peak memory	199088 kb
Host	smart-70722f1f-01ec-4236-b540-14a4a5b2b8aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276213809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4276213809
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/19.uart_perf.4090337714
Short name	T1077
Test name
Test status
Simulation time	25456215981 ps
CPU time	865.35 seconds
Started	Mar 12 01:07:31 PM PDT 24
Finished	Mar 12 01:21:57 PM PDT 24
Peak memory	200096 kb
Host	smart-b0a451fc-0fd0-4f62-b207-d38ae6aae788
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4090337714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4090337714
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.3600622885
Short name	T853
Test name
Test status
Simulation time	2106974641 ps
CPU time	11.46 seconds
Started	Mar 12 01:07:39 PM PDT 24
Finished	Mar 12 01:07:50 PM PDT 24
Peak memory	197640 kb
Host	smart-3bad0f6d-af6c-47b4-b5a0-3a4c0344976c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3600622885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3600622885
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.2584128254
Short name	T597
Test name
Test status
Simulation time	5423750818 ps
CPU time	4.23 seconds
Started	Mar 12 01:07:39 PM PDT 24
Finished	Mar 12 01:07:43 PM PDT 24
Peak memory	195856 kb
Host	smart-341676db-eab9-450c-926e-ac92aef656c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584128254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2584128254
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.412022204
Short name	T891
Test name
Test status
Simulation time	6199747831 ps
CPU time	12.1 seconds
Started	Mar 12 01:07:35 PM PDT 24
Finished	Mar 12 01:07:47 PM PDT 24
Peak memory	198768 kb
Host	smart-ea777376-c770-4e38-a4fa-c1bb25d9d960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412022204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.412022204
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_stress_all.200911763
Short name	T933
Test name
Test status
Simulation time	360807334037 ps
CPU time	963.1 seconds
Started	Mar 12 01:07:30 PM PDT 24
Finished	Mar 12 01:23:34 PM PDT 24
Peak memory	208496 kb
Host	smart-1299c1d2-2183-47b4-8062-8c89676cc6fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200911763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.200911763
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.3518892368
Short name	T526
Test name
Test status
Simulation time	1490631764 ps
CPU time	1.95 seconds
Started	Mar 12 01:07:24 PM PDT 24
Finished	Mar 12 01:07:26 PM PDT 24
Peak memory	197904 kb
Host	smart-0fa6fe5e-495f-4df3-a4ad-5c138f282a83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3518892368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3518892368
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.3083582421
Short name	T505
Test name
Test status
Simulation time	40333675428 ps
CPU time	107.22 seconds
Started	Mar 12 01:07:31 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	200064 kb
Host	smart-458ce970-7a31-47e8-a369-6c1afc6e82da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083582421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3083582421
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.2031859038
Short name	T54
Test name
Test status
Simulation time	92079778179 ps
CPU time	34.3 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:09 PM PDT 24
Peak memory	200152 kb
Host	smart-a4b60b19-0e60-4f6f-8ed1-80d35e348ec8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031859038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2031859038
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.510970084
Short name	T671
Test name
Test status
Simulation time	114462931651 ps
CPU time	20.95 seconds
Started	Mar 12 01:09:40 PM PDT 24
Finished	Mar 12 01:10:02 PM PDT 24
Peak memory	199992 kb
Host	smart-0f3845eb-2bf2-446b-b072-c120b19e8db8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510970084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.510970084
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.3830050449
Short name	T259
Test name
Test status
Simulation time	16468093818 ps
CPU time	16.06 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:09:52 PM PDT 24
Peak memory	200100 kb
Host	smart-e750ecba-2e35-4f74-8131-af906e859f67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830050449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3830050449
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.2076030938
Short name	T348
Test name
Test status
Simulation time	83319393723 ps
CPU time	33.77 seconds
Started	Mar 12 01:09:39 PM PDT 24
Finished	Mar 12 01:10:13 PM PDT 24
Peak memory	200052 kb
Host	smart-ed47ba85-bc2f-446e-9774-f36ee9d6e16a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076030938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2076030938
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.1544334779
Short name	T143
Test name
Test status
Simulation time	221562669712 ps
CPU time	101.55 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:11:17 PM PDT 24
Peak memory	199760 kb
Host	smart-9bb3c3f2-4500-4359-9d13-c8da84c01d1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544334779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1544334779
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.1521056181
Short name	T148
Test name
Test status
Simulation time	17996446879 ps
CPU time	26.57 seconds
Started	Mar 12 01:09:39 PM PDT 24
Finished	Mar 12 01:10:05 PM PDT 24
Peak memory	200136 kb
Host	smart-154d4fde-7abf-4f3a-8626-0b16631c6364
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1521056181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1521056181
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.1123916987
Short name	T170
Test name
Test status
Simulation time	43152625458 ps
CPU time	62.77 seconds
Started	Mar 12 01:09:36 PM PDT 24
Finished	Mar 12 01:10:39 PM PDT 24
Peak memory	199696 kb
Host	smart-8cfabf4d-64d2-4577-af06-51f1b9d59760
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123916987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1123916987
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.2298237109
Short name	T728
Test name
Test status
Simulation time	50890168235 ps
CPU time	83.4 seconds
Started	Mar 12 01:09:36 PM PDT 24
Finished	Mar 12 01:10:59 PM PDT 24
Peak memory	200124 kb
Host	smart-8b76edec-a216-4dfd-b70b-c5d3ebbece38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298237109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2298237109
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.3900348255
Short name	T785
Test name
Test status
Simulation time	45583381 ps
CPU time	0.63 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:06 PM PDT 24
Peak memory	195504 kb
Host	smart-0af27685-4ea9-4e6c-beca-d265ab3a9f6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900348255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3900348255
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.2280511950
Short name	T737
Test name
Test status
Simulation time	79206380222 ps
CPU time	39.42 seconds
Started	Mar 12 01:06:48 PM PDT 24
Finished	Mar 12 01:07:29 PM PDT 24
Peak memory	200080 kb
Host	smart-ffe442e8-4da4-461a-b31e-dd8746b4522d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280511950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2280511950
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.3854226584
Short name	T245
Test name
Test status
Simulation time	198183779945 ps
CPU time	283.46 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:11:49 PM PDT 24
Peak memory	200132 kb
Host	smart-02e6d64a-c6cd-4aa0-9d22-12e3d4554958
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854226584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3854226584
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.2733064432
Short name	T193
Test name
Test status
Simulation time	162873587236 ps
CPU time	96.71 seconds
Started	Mar 12 01:06:49 PM PDT 24
Finished	Mar 12 01:08:26 PM PDT 24
Peak memory	200104 kb
Host	smart-d3d7b413-a64c-4c6d-9554-c2de185f8e91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733064432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2733064432
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_intr.1711797636
Short name	T449
Test name
Test status
Simulation time	56027551127 ps
CPU time	47.53 seconds
Started	Mar 12 01:06:54 PM PDT 24
Finished	Mar 12 01:07:43 PM PDT 24
Peak memory	198868 kb
Host	smart-c4dc96a4-bc2e-42b6-ac54-a120832de27a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711797636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1711797636
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.3176679175
Short name	T915
Test name
Test status
Simulation time	178019791287 ps
CPU time	313.92 seconds
Started	Mar 12 01:06:48 PM PDT 24
Finished	Mar 12 01:12:03 PM PDT 24
Peak memory	200124 kb
Host	smart-83838986-7630-4ba5-8e1a-551b4223e643
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3176679175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3176679175
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.2149473562
Short name	T869
Test name
Test status
Simulation time	360015586 ps
CPU time	0.69 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:05 PM PDT 24
Peak memory	195464 kb
Host	smart-10d34e7e-ece7-4f79-93ad-f8d49ff2a8ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2149473562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2149473562
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.2899268431
Short name	T304
Test name
Test status
Simulation time	6604213223 ps
CPU time	6.03 seconds
Started	Mar 12 01:06:57 PM PDT 24
Finished	Mar 12 01:07:03 PM PDT 24
Peak memory	198024 kb
Host	smart-cebce0db-be47-4b47-aea3-d32b25e286d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899268431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2899268431
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.1552576392
Short name	T198
Test name
Test status
Simulation time	15713748510 ps
CPU time	419.48 seconds
Started	Mar 12 01:06:54 PM PDT 24
Finished	Mar 12 01:13:56 PM PDT 24
Peak memory	200100 kb
Host	smart-d578a5f7-6350-4d27-b99d-2b45098d33ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1552576392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1552576392
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.1659052615
Short name	T718
Test name
Test status
Simulation time	4586950129 ps
CPU time	10.28 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:07:10 PM PDT 24
Peak memory	198936 kb
Host	smart-7977c1fc-51cd-43bb-9f5e-fcca0c76485e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1659052615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1659052615
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.683241914
Short name	T404
Test name
Test status
Simulation time	325158995393 ps
CPU time	155.47 seconds
Started	Mar 12 01:06:58 PM PDT 24
Finished	Mar 12 01:09:34 PM PDT 24
Peak memory	200084 kb
Host	smart-ed182bff-88db-4f5e-aa58-48db0f89a1bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683241914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.683241914
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.3220161653
Short name	T981
Test name
Test status
Simulation time	5462582820 ps
CPU time	2.66 seconds
Started	Mar 12 01:06:50 PM PDT 24
Finished	Mar 12 01:06:53 PM PDT 24
Peak memory	195840 kb
Host	smart-cf25e3af-12be-424a-8fbd-ee21e1d55c97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220161653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3220161653
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.3863531374
Short name	T102
Test name
Test status
Simulation time	707422781 ps
CPU time	0.87 seconds
Started	Mar 12 01:06:54 PM PDT 24
Finished	Mar 12 01:06:57 PM PDT 24
Peak memory	217516 kb
Host	smart-53a110e3-2ca4-42cb-8e4d-4898b1b2a77a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863531374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3863531374
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/2.uart_smoke.1492350890
Short name	T694
Test name
Test status
Simulation time	737594945 ps
CPU time	1.34 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:13 PM PDT 24
Peak memory	198976 kb
Host	smart-73631a08-160e-4d8d-9cac-602447d29f13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492350890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1492350890
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_stress_all_with_rand_reset.1470909378
Short name	T1019
Test name
Test status
Simulation time	45598260930 ps
CPU time	528.28 seconds
Started	Mar 12 01:06:53 PM PDT 24
Finished	Mar 12 01:15:43 PM PDT 24
Peak memory	216796 kb
Host	smart-249fef6d-574b-42cd-a21f-79f9010d5324
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470909378 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1470909378
Directory	/workspace/2.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.3780380217
Short name	T1038
Test name
Test status
Simulation time	680455507 ps
CPU time	1.94 seconds
Started	Mar 12 01:07:01 PM PDT 24
Finished	Mar 12 01:07:03 PM PDT 24
Peak memory	197996 kb
Host	smart-c4e2dee9-9d05-464c-8116-527ebb1b5678
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780380217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3780380217
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.773601210
Short name	T936
Test name
Test status
Simulation time	74329393099 ps
CPU time	24.12 seconds
Started	Mar 12 01:06:53 PM PDT 24
Finished	Mar 12 01:07:19 PM PDT 24
Peak memory	200052 kb
Host	smart-bd4d431b-4727-43c6-ab4c-a45307251339
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773601210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.773601210
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.1301363453
Short name	T607
Test name
Test status
Simulation time	32544575548 ps
CPU time	28.32 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:08:05 PM PDT 24
Peak memory	199920 kb
Host	smart-179f3591-8da1-4b72-ac7d-f375876fdb28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1301363453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1301363453
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.3656209191
Short name	T879
Test name
Test status
Simulation time	133287980243 ps
CPU time	183.09 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:10:53 PM PDT 24
Peak memory	200104 kb
Host	smart-245ca8fc-0be2-4179-801f-4537f38d8fef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656209191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3656209191
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.2711945763
Short name	T218
Test name
Test status
Simulation time	210237111752 ps
CPU time	371.65 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:13:59 PM PDT 24
Peak memory	200144 kb
Host	smart-74d42e76-6634-4b7b-8e6f-3c93dea2770d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711945763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2711945763
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_intr.3648628894
Short name	T969
Test name
Test status
Simulation time	41150290979 ps
CPU time	44.34 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:08:21 PM PDT 24
Peak memory	199340 kb
Host	smart-982e4903-8dc0-4cdd-a406-e8297835bcf1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648628894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3648628894
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.4100360494
Short name	T525
Test name
Test status
Simulation time	114702915246 ps
CPU time	282.85 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:12:30 PM PDT 24
Peak memory	200064 kb
Host	smart-7c503d0e-49cd-4704-819e-fec593331379
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4100360494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4100360494
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.1948250100
Short name	T944
Test name
Test status
Simulation time	7865676522 ps
CPU time	4.6 seconds
Started	Mar 12 01:07:46 PM PDT 24
Finished	Mar 12 01:07:51 PM PDT 24
Peak memory	199288 kb
Host	smart-b8e35516-8e09-4552-8f26-e6477547bc7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948250100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1948250100
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.1059928889
Short name	T1066
Test name
Test status
Simulation time	23230211393 ps
CPU time	11.09 seconds
Started	Mar 12 01:07:34 PM PDT 24
Finished	Mar 12 01:07:45 PM PDT 24
Peak memory	198600 kb
Host	smart-447be293-4ec8-4d50-927d-3c10ee33172d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059928889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1059928889
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.4163371987
Short name	T692
Test name
Test status
Simulation time	5920941009 ps
CPU time	357.37 seconds
Started	Mar 12 01:07:31 PM PDT 24
Finished	Mar 12 01:13:28 PM PDT 24
Peak memory	199760 kb
Host	smart-4ee71691-e85d-4a0e-9492-ea4d1f75f309
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4163371987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4163371987
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.311955016
Short name	T840
Test name
Test status
Simulation time	3167070992 ps
CPU time	19.56 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:08:10 PM PDT 24
Peak memory	197644 kb
Host	smart-07b564e5-6b5d-441f-bdcd-8b876cad5ae4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=311955016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.311955016
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.1887909385
Short name	T719
Test name
Test status
Simulation time	2070538843 ps
CPU time	1.5 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:08:37 PM PDT 24
Peak memory	195384 kb
Host	smart-a19bdd19-ba6c-4fbe-971a-9cfa4a779fc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887909385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1887909385
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.1658897017
Short name	T687
Test name
Test status
Simulation time	330085303 ps
CPU time	1.2 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:07:49 PM PDT 24
Peak memory	198148 kb
Host	smart-039a2b2b-f1f6-4048-b5cf-2a91dc448515
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658897017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1658897017
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.1893419417
Short name	T397
Test name
Test status
Simulation time	268414895182 ps
CPU time	134.29 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:09:52 PM PDT 24
Peak memory	216216 kb
Host	smart-cc28527f-8fa9-4f13-88f9-852118bc6403
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893419417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1893419417
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.3783767118
Short name	T848
Test name
Test status
Simulation time	1571263527 ps
CPU time	2.2 seconds
Started	Mar 12 01:07:41 PM PDT 24
Finished	Mar 12 01:07:43 PM PDT 24
Peak memory	199008 kb
Host	smart-fd234d65-c33b-431e-985c-80b32505f4e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783767118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3783767118
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.2521804112
Short name	T1040
Test name
Test status
Simulation time	14965798409 ps
CPU time	10.17 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:07:48 PM PDT 24
Peak memory	199968 kb
Host	smart-59553140-3dae-4c56-9c32-2a93f14cdbe5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521804112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2521804112
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.4293097473
Short name	T317
Test name
Test status
Simulation time	206183509064 ps
CPU time	34.88 seconds
Started	Mar 12 01:09:41 PM PDT 24
Finished	Mar 12 01:10:16 PM PDT 24
Peak memory	200044 kb
Host	smart-fd68d951-3fe0-45e1-9679-276bfefc4d4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293097473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4293097473
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.1661815067
Short name	T868
Test name
Test status
Simulation time	116703139905 ps
CPU time	47.88 seconds
Started	Mar 12 01:09:41 PM PDT 24
Finished	Mar 12 01:10:29 PM PDT 24
Peak memory	200032 kb
Host	smart-db082ee8-b145-47f1-8ddf-d8f68667af7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661815067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1661815067
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.813037985
Short name	T366
Test name
Test status
Simulation time	12238190777 ps
CPU time	22.32 seconds
Started	Mar 12 01:09:41 PM PDT 24
Finished	Mar 12 01:10:03 PM PDT 24
Peak memory	200108 kb
Host	smart-8b2b3ff4-125d-4f82-9eae-815a80fef011
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813037985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.813037985
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.3486996600
Short name	T244
Test name
Test status
Simulation time	21338949104 ps
CPU time	37.15 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:10:15 PM PDT 24
Peak memory	199412 kb
Host	smart-5ace1b0f-7dc3-4f6c-8dfe-c2a721d6d770
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486996600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3486996600
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.1063335460
Short name	T346
Test name
Test status
Simulation time	151911625890 ps
CPU time	59.5 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:37 PM PDT 24
Peak memory	200016 kb
Host	smart-81de9fa4-cc3f-4c38-b5b3-7bc598ad0392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063335460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1063335460
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.1530139478
Short name	T887
Test name
Test status
Simulation time	33954972427 ps
CPU time	30.9 seconds
Started	Mar 12 01:09:34 PM PDT 24
Finished	Mar 12 01:10:05 PM PDT 24
Peak memory	200180 kb
Host	smart-4e6ce07a-c1f2-4f10-96a1-073adb378bef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530139478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1530139478
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.2081818414
Short name	T243
Test name
Test status
Simulation time	28938888939 ps
CPU time	26.82 seconds
Started	Mar 12 01:09:38 PM PDT 24
Finished	Mar 12 01:10:04 PM PDT 24
Peak memory	199812 kb
Host	smart-19c47445-0e89-4364-b0d2-b0db76cfd394
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081818414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2081818414
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.1696046201
Short name	T203
Test name
Test status
Simulation time	133361693412 ps
CPU time	58.13 seconds
Started	Mar 12 01:09:35 PM PDT 24
Finished	Mar 12 01:10:33 PM PDT 24
Peak memory	199616 kb
Host	smart-54ddfe57-a020-4fe1-9daa-870c90e581d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696046201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1696046201
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.3100208215
Short name	T226
Test name
Test status
Simulation time	95361828342 ps
CPU time	74.42 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:51 PM PDT 24
Peak memory	199744 kb
Host	smart-3e9c0582-0660-4154-9c09-f86b97a25c02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100208215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3100208215
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.3670016424
Short name	T555
Test name
Test status
Simulation time	26818233713 ps
CPU time	43.16 seconds
Started	Mar 12 01:09:37 PM PDT 24
Finished	Mar 12 01:10:20 PM PDT 24
Peak memory	199500 kb
Host	smart-11865c2b-d473-4277-a83c-5f7f8aee8d3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670016424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3670016424
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.63094251
Short name	T453
Test name
Test status
Simulation time	41402045 ps
CPU time	0.56 seconds
Started	Mar 12 01:07:44 PM PDT 24
Finished	Mar 12 01:07:45 PM PDT 24
Peak memory	195552 kb
Host	smart-8fd10684-facc-46a3-b2a2-e1538a4bcc7b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63094251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.63094251
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.2124020262
Short name	T759
Test name
Test status
Simulation time	75856662015 ps
CPU time	159.82 seconds
Started	Mar 12 01:07:41 PM PDT 24
Finished	Mar 12 01:10:21 PM PDT 24
Peak memory	200096 kb
Host	smart-531174d7-2f95-483c-b799-7db010fda4c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124020262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2124020262
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.3323429411
Short name	T381
Test name
Test status
Simulation time	19596669598 ps
CPU time	10.84 seconds
Started	Mar 12 01:07:48 PM PDT 24
Finished	Mar 12 01:07:59 PM PDT 24
Peak memory	200156 kb
Host	smart-7516440a-1b4b-4a40-ba9b-cd9d9ad49d49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323429411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3323429411
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_intr.32625741
Short name	T774
Test name
Test status
Simulation time	57631105554 ps
CPU time	38.95 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:08:17 PM PDT 24
Peak memory	199680 kb
Host	smart-eb4c72bb-d396-4adc-8e8b-577eeb85911f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32625741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.32625741
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.1466762428
Short name	T925
Test name
Test status
Simulation time	81834585288 ps
CPU time	336.46 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:13:13 PM PDT 24
Peak memory	200080 kb
Host	smart-66a54fed-6378-42de-a554-e956d1c99a93
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1466762428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1466762428
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.2442299776
Short name	T669
Test name
Test status
Simulation time	9817297147 ps
CPU time	12.02 seconds
Started	Mar 12 01:07:42 PM PDT 24
Finished	Mar 12 01:07:54 PM PDT 24
Peak memory	199468 kb
Host	smart-bf86121c-2405-4d31-a955-95b0d1954051
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442299776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2442299776
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.2769767440
Short name	T488
Test name
Test status
Simulation time	136485273371 ps
CPU time	60.36 seconds
Started	Mar 12 01:07:46 PM PDT 24
Finished	Mar 12 01:08:47 PM PDT 24
Peak memory	199372 kb
Host	smart-68f006b2-5549-46d3-9607-6e84d7438ce0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769767440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2769767440
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_perf.339156335
Short name	T604
Test name
Test status
Simulation time	1130675792 ps
CPU time	58.28 seconds
Started	Mar 12 01:07:31 PM PDT 24
Finished	Mar 12 01:08:29 PM PDT 24
Peak memory	199972 kb
Host	smart-6c1ec798-1df7-4443-b9fc-b49bcf4b2572
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=339156335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.339156335
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.2112062019
Short name	T1124
Test name
Test status
Simulation time	3799798731 ps
CPU time	33.65 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:08:22 PM PDT 24
Peak memory	198684 kb
Host	smart-d40b9295-83db-4670-9cde-5d61a5d33f33
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2112062019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2112062019
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.779526513
Short name	T634
Test name
Test status
Simulation time	52436832892 ps
CPU time	77.54 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:08:55 PM PDT 24
Peak memory	200180 kb
Host	smart-92e2938f-3462-4864-b17a-226c2dd44244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779526513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.779526513
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.627658404
Short name	T841
Test name
Test status
Simulation time	27958621561 ps
CPU time	11.28 seconds
Started	Mar 12 01:07:53 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	195580 kb
Host	smart-cc5ad85f-c7ad-48f9-b6c2-ee21cab134c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627658404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.627658404
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.1623307458
Short name	T467
Test name
Test status
Simulation time	303562526 ps
CPU time	1.31 seconds
Started	Mar 12 01:07:40 PM PDT 24
Finished	Mar 12 01:07:41 PM PDT 24
Peak memory	198296 kb
Host	smart-90242270-55b9-4348-abbf-30848898d797
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623307458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1623307458
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.3991480067
Short name	T720
Test name
Test status
Simulation time	2020242423 ps
CPU time	2.19 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:07:52 PM PDT 24
Peak memory	198372 kb
Host	smart-422c7609-a3e6-4fb5-a1a6-c45451f737d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3991480067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3991480067
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.3489699865
Short name	T538
Test name
Test status
Simulation time	46624205577 ps
CPU time	24.37 seconds
Started	Mar 12 01:07:39 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	199924 kb
Host	smart-47a1512f-6f7b-4938-bd6e-b47270fba392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489699865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3489699865
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.3684806666
Short name	T541
Test name
Test status
Simulation time	18289337594 ps
CPU time	31.38 seconds
Started	Mar 12 01:09:45 PM PDT 24
Finished	Mar 12 01:10:16 PM PDT 24
Peak memory	200108 kb
Host	smart-ce37d681-3037-4864-a618-02070cad0a67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3684806666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3684806666
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.3623864004
Short name	T1096
Test name
Test status
Simulation time	93479157461 ps
CPU time	42.64 seconds
Started	Mar 12 01:09:45 PM PDT 24
Finished	Mar 12 01:10:27 PM PDT 24
Peak memory	199820 kb
Host	smart-75b782ba-059c-493c-bc56-910feda07b3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3623864004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3623864004
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.2300930812
Short name	T838
Test name
Test status
Simulation time	131686625565 ps
CPU time	61.41 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:10:46 PM PDT 24
Peak memory	200108 kb
Host	smart-d7950ac2-c887-496a-b6d4-33729717673c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300930812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2300930812
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.663201434
Short name	T993
Test name
Test status
Simulation time	31698768844 ps
CPU time	18.57 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:10:03 PM PDT 24
Peak memory	199820 kb
Host	smart-cc799399-1846-4fa2-ad1c-0732daa49ae4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663201434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.663201434
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.3210779209
Short name	T1033
Test name
Test status
Simulation time	9819265909 ps
CPU time	17.15 seconds
Started	Mar 12 01:09:46 PM PDT 24
Finished	Mar 12 01:10:04 PM PDT 24
Peak memory	199804 kb
Host	smart-a93502aa-1021-4f94-b93b-1b0835be7512
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210779209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3210779209
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.2983894096
Short name	T906
Test name
Test status
Simulation time	83325969921 ps
CPU time	66.51 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:10:51 PM PDT 24
Peak memory	200084 kb
Host	smart-ab7f22f2-77f3-4f39-8872-1e4de7ac59b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983894096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2983894096
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.3458978572
Short name	T481
Test name
Test status
Simulation time	31277218053 ps
CPU time	50.19 seconds
Started	Mar 12 01:09:49 PM PDT 24
Finished	Mar 12 01:10:39 PM PDT 24
Peak memory	199092 kb
Host	smart-25dd70fe-856d-4d6d-ba79-65377c0ffa3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458978572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3458978572
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.55897910
Short name	T1113
Test name
Test status
Simulation time	34606213 ps
CPU time	0.54 seconds
Started	Mar 12 01:07:44 PM PDT 24
Finished	Mar 12 01:07:45 PM PDT 24
Peak memory	194572 kb
Host	smart-e6b28a1d-eb70-4522-8ddc-b563222a1968
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55897910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.55897910
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.4142356250
Short name	T863
Test name
Test status
Simulation time	261958205875 ps
CPU time	114.65 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:09:39 PM PDT 24
Peak memory	200144 kb
Host	smart-dc9281a5-ba2a-4860-b4cb-46676aac67ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142356250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4142356250
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.3392277335
Short name	T306
Test name
Test status
Simulation time	107433394700 ps
CPU time	41.95 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:08:28 PM PDT 24
Peak memory	200080 kb
Host	smart-4548569a-ffc2-40b3-b66e-4d00aebdff2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392277335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3392277335
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.2227677207
Short name	T494
Test name
Test status
Simulation time	364800613262 ps
CPU time	559.81 seconds
Started	Mar 12 01:07:46 PM PDT 24
Finished	Mar 12 01:17:06 PM PDT 24
Peak memory	198124 kb
Host	smart-a8252487-b1c1-4ba5-8817-77946e98d04f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227677207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2227677207
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.3199210348
Short name	T393
Test name
Test status
Simulation time	113530504941 ps
CPU time	369.9 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:13:55 PM PDT 24
Peak memory	200100 kb
Host	smart-23c1e910-caab-488a-aba2-181e7041f248
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3199210348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3199210348
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.1052345509
Short name	T558
Test name
Test status
Simulation time	10782601024 ps
CPU time	5.58 seconds
Started	Mar 12 01:07:32 PM PDT 24
Finished	Mar 12 01:07:38 PM PDT 24
Peak memory	199116 kb
Host	smart-48206ccd-2182-484e-9eba-33b2dbc85794
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052345509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1052345509
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.872964871
Short name	T788
Test name
Test status
Simulation time	28971942677 ps
CPU time	92.88 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:09:10 PM PDT 24
Peak memory	198212 kb
Host	smart-ef71f94e-c931-4386-bc54-c032de3d9f29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872964871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.872964871
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.2184215941
Short name	T546
Test name
Test status
Simulation time	13433689194 ps
CPU time	367.97 seconds
Started	Mar 12 01:07:37 PM PDT 24
Finished	Mar 12 01:13:45 PM PDT 24
Peak memory	200080 kb
Host	smart-5abae1b7-5457-4144-b3f4-48811e8d365a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2184215941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2184215941
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.154955939
Short name	T770
Test name
Test status
Simulation time	4983995085 ps
CPU time	9.95 seconds
Started	Mar 12 01:07:36 PM PDT 24
Finished	Mar 12 01:07:46 PM PDT 24
Peak memory	198376 kb
Host	smart-72de7e54-f44f-491c-a9ec-b7cc1e67830a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=154955939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.154955939
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.1725302247
Short name	T992
Test name
Test status
Simulation time	61802103817 ps
CPU time	102.75 seconds
Started	Mar 12 01:07:29 PM PDT 24
Finished	Mar 12 01:09:12 PM PDT 24
Peak memory	200112 kb
Host	smart-b4502640-ec0c-4d5a-ab34-49daf44678b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725302247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1725302247
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.786802389
Short name	T1055
Test name
Test status
Simulation time	4686405504 ps
CPU time	7.18 seconds
Started	Mar 12 01:07:42 PM PDT 24
Finished	Mar 12 01:07:49 PM PDT 24
Peak memory	195988 kb
Host	smart-8437ac36-4044-463d-9839-43d2ff345bb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786802389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.786802389
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.1936629306
Short name	T617
Test name
Test status
Simulation time	274259018 ps
CPU time	1.15 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:07:50 PM PDT 24
Peak memory	197888 kb
Host	smart-a85b02ca-00c9-47f2-88b7-8486e12d6499
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936629306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1936629306
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_stress_all.1910734292
Short name	T913
Test name
Test status
Simulation time	211049209797 ps
CPU time	718.99 seconds
Started	Mar 12 01:07:36 PM PDT 24
Finished	Mar 12 01:19:35 PM PDT 24
Peak memory	208376 kb
Host	smart-8330b546-d486-4d1b-9f60-93f2eb572629
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910734292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1910734292
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.387585700
Short name	T846
Test name
Test status
Simulation time	330241740 ps
CPU time	1.4 seconds
Started	Mar 12 01:07:34 PM PDT 24
Finished	Mar 12 01:07:35 PM PDT 24
Peak memory	197440 kb
Host	smart-f7de60ff-4be8-4baf-af7a-78bd4c8595b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387585700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.387585700
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.3092470610
Short name	T641
Test name
Test status
Simulation time	70295646079 ps
CPU time	54.54 seconds
Started	Mar 12 01:07:33 PM PDT 24
Finished	Mar 12 01:08:28 PM PDT 24
Peak memory	200096 kb
Host	smart-a4a7014b-1a78-43cd-be1a-bf3b73d5abc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3092470610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3092470610
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.2317127048
Short name	T77
Test name
Test status
Simulation time	87060251101 ps
CPU time	28.73 seconds
Started	Mar 12 01:09:45 PM PDT 24
Finished	Mar 12 01:10:14 PM PDT 24
Peak memory	198812 kb
Host	smart-293f94d3-1022-4695-80a6-950579bbe126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317127048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2317127048
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.2345636615
Short name	T89
Test name
Test status
Simulation time	29952322980 ps
CPU time	41.26 seconds
Started	Mar 12 01:09:43 PM PDT 24
Finished	Mar 12 01:10:25 PM PDT 24
Peak memory	199976 kb
Host	smart-9ff3005c-60e9-4aca-b19e-2aec57b140c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345636615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2345636615
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.1677419735
Short name	T158
Test name
Test status
Simulation time	144219305762 ps
CPU time	114.93 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:11:39 PM PDT 24
Peak memory	199604 kb
Host	smart-71338052-d3c6-4aa4-bb76-767e14950140
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677419735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1677419735
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.3063660950
Short name	T1122
Test name
Test status
Simulation time	13137176485 ps
CPU time	23.28 seconds
Started	Mar 12 01:09:47 PM PDT 24
Finished	Mar 12 01:10:11 PM PDT 24
Peak memory	200108 kb
Host	smart-a976a046-fb76-40b4-a6d9-1ca17ae5e74f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063660950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3063660950
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.383529086
Short name	T313
Test name
Test status
Simulation time	42573357097 ps
CPU time	9.28 seconds
Started	Mar 12 01:09:45 PM PDT 24
Finished	Mar 12 01:09:54 PM PDT 24
Peak memory	200116 kb
Host	smart-aced5ba6-04ba-4d72-8217-f137b816c837
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383529086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.383529086
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.525563337
Short name	T217
Test name
Test status
Simulation time	114717344439 ps
CPU time	214.73 seconds
Started	Mar 12 01:09:53 PM PDT 24
Finished	Mar 12 01:13:29 PM PDT 24
Peak memory	199984 kb
Host	smart-b5029cbb-9e7d-4efa-9799-6782b9abc01d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525563337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.525563337
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.1839658619
Short name	T878
Test name
Test status
Simulation time	27839562565 ps
CPU time	43.04 seconds
Started	Mar 12 01:09:52 PM PDT 24
Finished	Mar 12 01:10:36 PM PDT 24
Peak memory	200048 kb
Host	smart-fb4d80f0-2d0d-4485-992d-d893aa0a217c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839658619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1839658619
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.2379585917
Short name	T185
Test name
Test status
Simulation time	39024502415 ps
CPU time	62.96 seconds
Started	Mar 12 01:09:49 PM PDT 24
Finished	Mar 12 01:10:52 PM PDT 24
Peak memory	199880 kb
Host	smart-47b460ff-abac-4fa6-91a1-423793500c0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2379585917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2379585917
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.2882426876
Short name	T734
Test name
Test status
Simulation time	131483257839 ps
CPU time	110.21 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:11:35 PM PDT 24
Peak memory	200020 kb
Host	smart-e998e5bd-17ce-4d14-9db3-a3938792e906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882426876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2882426876
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_alert_test.3523388885
Short name	T754
Test name
Test status
Simulation time	38320279 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:07:56 PM PDT 24
Peak memory	195500 kb
Host	smart-672e283d-d8fd-49ee-88a0-a7aea88cd6e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523388885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3523388885
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.1227858470
Short name	T568
Test name
Test status
Simulation time	85773017860 ps
CPU time	134.88 seconds
Started	Mar 12 01:07:34 PM PDT 24
Finished	Mar 12 01:09:49 PM PDT 24
Peak memory	200048 kb
Host	smart-1b6f750f-3ab4-4a59-96a6-0d4871524563
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227858470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1227858470
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.389652281
Short name	T168
Test name
Test status
Simulation time	51556165655 ps
CPU time	89.7 seconds
Started	Mar 12 01:07:41 PM PDT 24
Finished	Mar 12 01:09:11 PM PDT 24
Peak memory	199064 kb
Host	smart-21f68d1c-ac49-49f4-b251-ba965978e0fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389652281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.389652281
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_intr.2281890855
Short name	T967
Test name
Test status
Simulation time	116501778880 ps
CPU time	98.7 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:09:17 PM PDT 24
Peak memory	200080 kb
Host	smart-4e19f9fa-f814-4e02-96e3-d57c52f6c78a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281890855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2281890855
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.1464299637
Short name	T1008
Test name
Test status
Simulation time	112548408103 ps
CPU time	234.8 seconds
Started	Mar 12 01:07:44 PM PDT 24
Finished	Mar 12 01:11:39 PM PDT 24
Peak memory	200112 kb
Host	smart-f8387620-606f-4c4a-a1f0-3bac46959807
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1464299637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1464299637
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.4028938945
Short name	T458
Test name
Test status
Simulation time	3128389514 ps
CPU time	2.46 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:07:56 PM PDT 24
Peak memory	197676 kb
Host	smart-1ac68172-50a2-4f2b-9fd2-16c12ef1c93d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028938945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4028938945
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.2589975762
Short name	T587
Test name
Test status
Simulation time	91357259070 ps
CPU time	81.33 seconds
Started	Mar 12 01:07:44 PM PDT 24
Finished	Mar 12 01:09:05 PM PDT 24
Peak memory	199560 kb
Host	smart-75dc913e-fda0-4235-bf8d-0b68ff7532d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589975762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2589975762
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.1371286505
Short name	T966
Test name
Test status
Simulation time	1734345258 ps
CPU time	1.41 seconds
Started	Mar 12 01:07:38 PM PDT 24
Finished	Mar 12 01:07:40 PM PDT 24
Peak memory	198040 kb
Host	smart-a24a1efe-cf79-42e3-b447-157b182f064f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1371286505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1371286505
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.574815076
Short name	T811
Test name
Test status
Simulation time	204097984630 ps
CPU time	76.63 seconds
Started	Mar 12 01:07:54 PM PDT 24
Finished	Mar 12 01:09:11 PM PDT 24
Peak memory	200120 kb
Host	smart-ed31eb97-c398-45ab-ac30-9c287cd82651
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574815076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.574815076
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.1170659618
Short name	T775
Test name
Test status
Simulation time	3627463421 ps
CPU time	2.2 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:07:57 PM PDT 24
Peak memory	195856 kb
Host	smart-d01b1719-c422-485a-ab9f-e954de615496
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170659618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1170659618
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.1970858300
Short name	T880
Test name
Test status
Simulation time	740043065 ps
CPU time	1.82 seconds
Started	Mar 12 01:07:41 PM PDT 24
Finished	Mar 12 01:07:43 PM PDT 24
Peak memory	197840 kb
Host	smart-f071dde1-5b2c-487d-9b52-163bcd74b179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970858300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1970858300
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_stress_all_with_rand_reset.2256370710
Short name	T78
Test name
Test status
Simulation time	30023272564 ps
CPU time	174.44 seconds
Started	Mar 12 01:07:51 PM PDT 24
Finished	Mar 12 01:10:45 PM PDT 24
Peak memory	216268 kb
Host	smart-fcca88ce-2dbe-4eb2-b9b3-80acf4e76136
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256370710 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2256370710
Directory	/workspace/23.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.920002561
Short name	T1098
Test name
Test status
Simulation time	7052779386 ps
CPU time	16.26 seconds
Started	Mar 12 01:07:53 PM PDT 24
Finished	Mar 12 01:08:09 PM PDT 24
Peak memory	199616 kb
Host	smart-b453cccb-5ef4-4b9a-accb-8905084234e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920002561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.920002561
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.3998011150
Short name	T964
Test name
Test status
Simulation time	183915058578 ps
CPU time	116.84 seconds
Started	Mar 12 01:07:43 PM PDT 24
Finished	Mar 12 01:09:40 PM PDT 24
Peak memory	200076 kb
Host	smart-903b12a5-6068-4e1e-b553-43492c998efb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998011150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3998011150
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.4131253616
Short name	T192
Test name
Test status
Simulation time	228149950407 ps
CPU time	127.12 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:11:52 PM PDT 24
Peak memory	200136 kb
Host	smart-6ae4cf82-dc4a-485a-988c-9b0718c337ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131253616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4131253616
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.1378936744
Short name	T242
Test name
Test status
Simulation time	24685670155 ps
CPU time	12.33 seconds
Started	Mar 12 01:09:50 PM PDT 24
Finished	Mar 12 01:10:02 PM PDT 24
Peak memory	199700 kb
Host	smart-14fdcb35-11aa-40aa-9d15-2fbaaf1d23c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1378936744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1378936744
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.1414836171
Short name	T236
Test name
Test status
Simulation time	86434310766 ps
CPU time	15.3 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:10:00 PM PDT 24
Peak memory	200112 kb
Host	smart-966c5561-24cc-421e-a7ab-54a670bb5018
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414836171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1414836171
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.2343159406
Short name	T883
Test name
Test status
Simulation time	129151888031 ps
CPU time	49 seconds
Started	Mar 12 01:09:49 PM PDT 24
Finished	Mar 12 01:10:38 PM PDT 24
Peak memory	199896 kb
Host	smart-e2828972-ffc8-4a78-9ea6-9cd926f35049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343159406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2343159406
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.900985513
Short name	T566
Test name
Test status
Simulation time	13979637852 ps
CPU time	21.82 seconds
Started	Mar 12 01:09:52 PM PDT 24
Finished	Mar 12 01:10:15 PM PDT 24
Peak memory	199636 kb
Host	smart-53776cd2-c3c6-4286-9dc6-373198addc88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900985513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.900985513
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.211373066
Short name	T978
Test name
Test status
Simulation time	17123189764 ps
CPU time	15.32 seconds
Started	Mar 12 01:09:45 PM PDT 24
Finished	Mar 12 01:10:00 PM PDT 24
Peak memory	199904 kb
Host	smart-7b59b58f-8668-4381-9ea7-7ba26224b890
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211373066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.211373066
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.3283296682
Short name	T334
Test name
Test status
Simulation time	93592801130 ps
CPU time	22.23 seconds
Started	Mar 12 01:09:50 PM PDT 24
Finished	Mar 12 01:10:13 PM PDT 24
Peak memory	199976 kb
Host	smart-2a852170-0ae0-4e29-b68d-3560ec87130c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283296682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3283296682
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.4276557496
Short name	T899
Test name
Test status
Simulation time	105993739658 ps
CPU time	19.63 seconds
Started	Mar 12 01:09:45 PM PDT 24
Finished	Mar 12 01:10:04 PM PDT 24
Peak memory	200036 kb
Host	smart-d98863db-8bee-4ccc-9670-e5190461ed0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276557496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4276557496
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.834147630
Short name	T1092
Test name
Test status
Simulation time	13347188 ps
CPU time	0.54 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:07:52 PM PDT 24
Peak memory	195508 kb
Host	smart-21f713f8-ee75-4e51-abbd-4efe77cb4688
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834147630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.834147630
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.1337231606
Short name	T465
Test name
Test status
Simulation time	81509014674 ps
CPU time	33.86 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:08:24 PM PDT 24
Peak memory	200056 kb
Host	smart-9e45a490-cd3f-4894-a53c-cbc7dfe33723
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337231606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1337231606
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.853702309
Short name	T742
Test name
Test status
Simulation time	14684668845 ps
CPU time	17.29 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:08:14 PM PDT 24
Peak memory	198912 kb
Host	smart-6e9e31ed-7c02-4e3e-a777-62f38cfb0ce4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853702309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.853702309
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.1089838200
Short name	T786
Test name
Test status
Simulation time	71860337291 ps
CPU time	56.1 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:08:41 PM PDT 24
Peak memory	199656 kb
Host	smart-a05fb12d-f18b-4651-a73e-7836368352bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089838200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1089838200
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_intr.3316258933
Short name	T445
Test name
Test status
Simulation time	108873250211 ps
CPU time	64.22 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:09:00 PM PDT 24
Peak memory	199980 kb
Host	smart-be531355-0519-4b09-a750-54528521d3b2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316258933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3316258933
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.3809135887
Short name	T885
Test name
Test status
Simulation time	115926471659 ps
CPU time	283.52 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:12:37 PM PDT 24
Peak memory	200132 kb
Host	smart-d2d59f3d-a082-4d12-bc2d-0355f5504643
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3809135887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3809135887
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/24.uart_loopback.355794996
Short name	T1005
Test name
Test status
Simulation time	2670187144 ps
CPU time	6.15 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:07:55 PM PDT 24
Peak memory	199644 kb
Host	smart-388dbad0-cc02-4cc2-8c75-86a01badb083
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355794996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.355794996
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.1393079069
Short name	T648
Test name
Test status
Simulation time	113129023979 ps
CPU time	110.09 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:09:40 PM PDT 24
Peak memory	208360 kb
Host	smart-4c10d349-5417-4a44-988e-fcd036f98e94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393079069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1393079069
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.2132884383
Short name	T537
Test name
Test status
Simulation time	21539660394 ps
CPU time	941.95 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:23:34 PM PDT 24
Peak memory	200096 kb
Host	smart-7b8f9f42-711b-4fac-8c45-aaa429e5d0fb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2132884383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2132884383
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.1714456615
Short name	T676
Test name
Test status
Simulation time	3578825826 ps
CPU time	29.55 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:08:15 PM PDT 24
Peak memory	198744 kb
Host	smart-1de58a9c-5247-4bb4-a3e2-bb10dc02f689
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1714456615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1714456615
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.3298370131
Short name	T150
Test name
Test status
Simulation time	65598946663 ps
CPU time	115.08 seconds
Started	Mar 12 01:07:51 PM PDT 24
Finished	Mar 12 01:09:46 PM PDT 24
Peak memory	199188 kb
Host	smart-fd084d7e-f847-4151-9665-e71210212939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298370131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3298370131
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.989755813
Short name	T594
Test name
Test status
Simulation time	32435232173 ps
CPU time	12.29 seconds
Started	Mar 12 01:07:53 PM PDT 24
Finished	Mar 12 01:08:05 PM PDT 24
Peak memory	195956 kb
Host	smart-8f51a256-6dbc-4bd1-9cb9-8e72570db5bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989755813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.989755813
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.742820973
Short name	T1075
Test name
Test status
Simulation time	11061033289 ps
CPU time	22.06 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	199132 kb
Host	smart-ebacf075-e840-4667-b61c-15b4fc4bc815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742820973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.742820973
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all.3902801062
Short name	T407
Test name
Test status
Simulation time	71850903139 ps
CPU time	175.65 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:10:43 PM PDT 24
Peak memory	200028 kb
Host	smart-3e3bb3eb-cba0-456b-a5dd-7cd113093b43
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902801062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3902801062
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.1823358989
Short name	T431
Test name
Test status
Simulation time	6638828011 ps
CPU time	8.12 seconds
Started	Mar 12 01:08:01 PM PDT 24
Finished	Mar 12 01:08:09 PM PDT 24
Peak memory	199368 kb
Host	smart-9e977703-aa84-4858-95bd-b758b361796e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823358989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1823358989
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.4117160651
Short name	T1110
Test name
Test status
Simulation time	3912633229 ps
CPU time	6.91 seconds
Started	Mar 12 01:07:45 PM PDT 24
Finished	Mar 12 01:07:52 PM PDT 24
Peak memory	195908 kb
Host	smart-ac1500fd-0c45-43ef-9147-2febd6884ec5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117160651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4117160651
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.1611131622
Short name	T1104
Test name
Test status
Simulation time	17044719650 ps
CPU time	30.36 seconds
Started	Mar 12 01:09:44 PM PDT 24
Finished	Mar 12 01:10:15 PM PDT 24
Peak memory	199972 kb
Host	smart-3a3f9c51-c0d6-4e31-9932-6b7728fc9edb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611131622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1611131622
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.1119980510
Short name	T125
Test name
Test status
Simulation time	34463446359 ps
CPU time	25.45 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:10:21 PM PDT 24
Peak memory	200048 kb
Host	smart-79c7dc87-abf7-445d-9489-c776fee55597
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119980510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1119980510
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.3691713776
Short name	T1015
Test name
Test status
Simulation time	37946918419 ps
CPU time	82.5 seconds
Started	Mar 12 01:09:56 PM PDT 24
Finished	Mar 12 01:11:19 PM PDT 24
Peak memory	200024 kb
Host	smart-2cb2ddc4-a2e2-4c1d-822e-b27c10764848
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691713776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3691713776
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.991864424
Short name	T108
Test name
Test status
Simulation time	62116832473 ps
CPU time	87.9 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:11:22 PM PDT 24
Peak memory	199400 kb
Host	smart-2f3a6723-4269-4d19-a24a-34166c0156b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=991864424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.991864424
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.2714175534
Short name	T189
Test name
Test status
Simulation time	43141740665 ps
CPU time	32.31 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:10:28 PM PDT 24
Peak memory	200040 kb
Host	smart-19d60a61-208d-4866-bd7b-167b93bef0a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714175534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2714175534
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.2268049981
Short name	T53
Test name
Test status
Simulation time	89465593293 ps
CPU time	59.68 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:55 PM PDT 24
Peak memory	200104 kb
Host	smart-622ece3e-cdea-471e-9ecc-f64a2cfac40d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268049981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2268049981
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.2223394239
Short name	T789
Test name
Test status
Simulation time	93907387804 ps
CPU time	63.14 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:57 PM PDT 24
Peak memory	200120 kb
Host	smart-5b35146e-e8be-4267-a201-94d547498222
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223394239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2223394239
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.1145043946
Short name	T307
Test name
Test status
Simulation time	25480990657 ps
CPU time	33.56 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:10:30 PM PDT 24
Peak memory	199940 kb
Host	smart-6b613e20-3519-4d97-bca5-d83166e2ab89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145043946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1145043946
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.271939924
Short name	T32
Test name
Test status
Simulation time	21437307 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:51 PM PDT 24
Finished	Mar 12 01:07:52 PM PDT 24
Peak memory	195508 kb
Host	smart-6e02f3f7-35ba-4b1f-916b-efe03ef763ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271939924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.271939924
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.3427719764
Short name	T1086
Test name
Test status
Simulation time	62061397894 ps
CPU time	26.6 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:08:22 PM PDT 24
Peak memory	200096 kb
Host	smart-a2edbefc-3d3b-4036-bbf4-21ff94fff691
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427719764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3427719764
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.475846260
Short name	T1048
Test name
Test status
Simulation time	74296591263 ps
CPU time	39.64 seconds
Started	Mar 12 01:07:48 PM PDT 24
Finished	Mar 12 01:08:28 PM PDT 24
Peak memory	200060 kb
Host	smart-a0fc8255-e7bf-4f71-b7b7-40f3f44514d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475846260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.475846260
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_intr.3060705922
Short name	T457
Test name
Test status
Simulation time	18938312626 ps
CPU time	8.29 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:07:58 PM PDT 24
Peak memory	197792 kb
Host	smart-fe3df314-197f-4993-bc49-6616bfa3fb3e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060705922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3060705922
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.320290877
Short name	T503
Test name
Test status
Simulation time	139528925004 ps
CPU time	356.5 seconds
Started	Mar 12 01:07:51 PM PDT 24
Finished	Mar 12 01:13:47 PM PDT 24
Peak memory	200072 kb
Host	smart-458e92bb-4023-4de2-a52d-18379d813bec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=320290877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.320290877
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/25.uart_loopback.1933344111
Short name	T495
Test name
Test status
Simulation time	7692865853 ps
CPU time	12.85 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	198104 kb
Host	smart-fdd88fce-0aa6-42bb-b022-53e5eb4897b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933344111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1933344111
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.2425880350
Short name	T513
Test name
Test status
Simulation time	84702452553 ps
CPU time	300.42 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:12:50 PM PDT 24
Peak memory	199204 kb
Host	smart-eea6fb8b-772f-4c45-b553-8d149eb55d70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425880350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2425880350
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.697927420
Short name	T985
Test name
Test status
Simulation time	8451800856 ps
CPU time	494.02 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:16:09 PM PDT 24
Peak memory	199992 kb
Host	smart-43acc936-76a2-4495-96cc-9fccbb269545
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=697927420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.697927420
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.3422439191
Short name	T732
Test name
Test status
Simulation time	1583598304 ps
CPU time	1.85 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:07:51 PM PDT 24
Peak memory	198136 kb
Host	smart-31f5378a-3c4b-4e19-9af1-abf769aa3863
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3422439191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3422439191
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.339586842
Short name	T365
Test name
Test status
Simulation time	41950469661 ps
CPU time	61.63 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:08:57 PM PDT 24
Peak memory	199944 kb
Host	smart-ed617f42-cfd1-42e2-95ce-202605c6ff3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339586842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.339586842
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.2332353173
Short name	T809
Test name
Test status
Simulation time	3485479252 ps
CPU time	3.51 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:07:55 PM PDT 24
Peak memory	195828 kb
Host	smart-247d7eef-4f24-4999-b9b5-73acd6b4fba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332353173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2332353173
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/25.uart_smoke.1199442856
Short name	T510
Test name
Test status
Simulation time	6284519819 ps
CPU time	12.92 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	199672 kb
Host	smart-b16a45fa-ef0f-4c48-afcb-7ffd5aab4c4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1199442856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1199442856
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.2385930052
Short name	T792
Test name
Test status
Simulation time	2048666828 ps
CPU time	2.55 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:01 PM PDT 24
Peak memory	198520 kb
Host	smart-3dc22798-99aa-42e7-b70f-cdfafeccb6dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385930052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2385930052
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.2565367390
Short name	T1067
Test name
Test status
Simulation time	63793052424 ps
CPU time	142.87 seconds
Started	Mar 12 01:07:51 PM PDT 24
Finished	Mar 12 01:10:14 PM PDT 24
Peak memory	200080 kb
Host	smart-b3fa445c-8cd7-4d98-8018-bd81390c36c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565367390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2565367390
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.2756004951
Short name	T221
Test name
Test status
Simulation time	15019413839 ps
CPU time	6.5 seconds
Started	Mar 12 01:09:57 PM PDT 24
Finished	Mar 12 01:10:04 PM PDT 24
Peak memory	199984 kb
Host	smart-748f7874-a3e0-406c-af4b-0e15f3663fe7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756004951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2756004951
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.3304099129
Short name	T665
Test name
Test status
Simulation time	18647452535 ps
CPU time	18.14 seconds
Started	Mar 12 01:09:57 PM PDT 24
Finished	Mar 12 01:10:15 PM PDT 24
Peak memory	200088 kb
Host	smart-876a3ccb-0307-4dcb-9c21-16fee118392c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304099129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3304099129
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.2739898508
Short name	T1091
Test name
Test status
Simulation time	49040801582 ps
CPU time	22.89 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:18 PM PDT 24
Peak memory	199780 kb
Host	smart-3ab9e32b-4ef4-412e-ab61-455d0dd64fdb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739898508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2739898508
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.2630601544
Short name	T934
Test name
Test status
Simulation time	69793689642 ps
CPU time	58.08 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:10:53 PM PDT 24
Peak memory	200124 kb
Host	smart-e9b93d49-19da-4641-94dd-55541a49931b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630601544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2630601544
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.2944141899
Short name	T950
Test name
Test status
Simulation time	118362021127 ps
CPU time	176.15 seconds
Started	Mar 12 01:09:56 PM PDT 24
Finished	Mar 12 01:12:53 PM PDT 24
Peak memory	200104 kb
Host	smart-23f83aeb-15fd-487a-8d2f-d4abe0cbeddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944141899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2944141899
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.2029140899
Short name	T318
Test name
Test status
Simulation time	35157436885 ps
CPU time	21.24 seconds
Started	Mar 12 01:09:57 PM PDT 24
Finished	Mar 12 01:10:19 PM PDT 24
Peak memory	200088 kb
Host	smart-57093031-a1a0-468e-99fc-2c99ee49d90a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029140899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2029140899
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.506205622
Short name	T912
Test name
Test status
Simulation time	67375665903 ps
CPU time	31.19 seconds
Started	Mar 12 01:09:56 PM PDT 24
Finished	Mar 12 01:10:27 PM PDT 24
Peak memory	200068 kb
Host	smart-7d8dabd1-2354-46a4-b323-8e4c6b3685fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506205622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.506205622
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.3324598959
Short name	T1070
Test name
Test status
Simulation time	286809721414 ps
CPU time	37.48 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:32 PM PDT 24
Peak memory	200128 kb
Host	smart-e0ff6d15-76fc-4736-8cb1-6a594fc29a09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324598959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3324598959
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.1891416773
Short name	T529
Test name
Test status
Simulation time	14607221 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:07:58 PM PDT 24
Peak memory	195548 kb
Host	smart-68e1a19f-de1c-43c4-a2a4-d12239f2fa61
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891416773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1891416773
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.3922253985
Short name	T784
Test name
Test status
Simulation time	48708157726 ps
CPU time	21.98 seconds
Started	Mar 12 01:07:46 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	199808 kb
Host	smart-3700d3b2-fa3e-413e-a34d-42f394fefe09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922253985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3922253985
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.3933220234
Short name	T354
Test name
Test status
Simulation time	61731190462 ps
CPU time	60.84 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:08:58 PM PDT 24
Peak memory	199476 kb
Host	smart-441a88c4-51ab-4382-94aa-f0eac6842b5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933220234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3933220234
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.3079061798
Short name	T206
Test name
Test status
Simulation time	20168927672 ps
CPU time	31.82 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:08:27 PM PDT 24
Peak memory	199976 kb
Host	smart-e7cb41d3-4c12-4f69-8ac6-7feb61cc9f94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079061798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3079061798
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_intr.3790971647
Short name	T855
Test name
Test status
Simulation time	78679131258 ps
CPU time	39.46 seconds
Started	Mar 12 01:07:51 PM PDT 24
Finished	Mar 12 01:08:31 PM PDT 24
Peak memory	200048 kb
Host	smart-b687315e-5f66-4427-a2e1-595767c97c9d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790971647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3790971647
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.2245214742
Short name	T808
Test name
Test status
Simulation time	85908456125 ps
CPU time	407.23 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:14:40 PM PDT 24
Peak memory	200164 kb
Host	smart-c69bbe07-3595-4bef-99be-a3ce45c31675
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2245214742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2245214742
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.3907218480
Short name	T980
Test name
Test status
Simulation time	1416756680 ps
CPU time	1.33 seconds
Started	Mar 12 01:08:01 PM PDT 24
Finished	Mar 12 01:08:02 PM PDT 24
Peak memory	195632 kb
Host	smart-9221fa9c-e5b7-4480-980c-488cca6ebced
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3907218480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3907218480
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.3350104925
Short name	T434
Test name
Test status
Simulation time	57025061996 ps
CPU time	18.33 seconds
Started	Mar 12 01:08:01 PM PDT 24
Finished	Mar 12 01:08:19 PM PDT 24
Peak memory	197216 kb
Host	smart-cd2b5301-d4a2-474a-b18c-109a126db663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350104925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3350104925
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/26.uart_perf.3992479259
Short name	T419
Test name
Test status
Simulation time	10181558586 ps
CPU time	150.8 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:10:27 PM PDT 24
Peak memory	200136 kb
Host	smart-fab0b754-7a75-4ac3-ba8c-976a2f2e883e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3992479259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3992479259
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.703967755
Short name	T791
Test name
Test status
Simulation time	3397854309 ps
CPU time	29.27 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:08:26 PM PDT 24
Peak memory	198692 kb
Host	smart-900264d6-c05e-4341-8a67-0177bc0c2689
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=703967755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.703967755
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.3818356204
Short name	T347
Test name
Test status
Simulation time	142502952283 ps
CPU time	55.35 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:08:52 PM PDT 24
Peak memory	200048 kb
Host	smart-fcc58e5c-bca1-49a9-93d4-512495338041
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818356204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3818356204
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.3505300339
Short name	T909
Test name
Test status
Simulation time	2327626755 ps
CPU time	1.62 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:07:50 PM PDT 24
Peak memory	195688 kb
Host	smart-6b70de6a-b526-4913-90f2-31958ab72b70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505300339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3505300339
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.2940455682
Short name	T703
Test name
Test status
Simulation time	749004754 ps
CPU time	1.53 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:07:58 PM PDT 24
Peak memory	198644 kb
Host	smart-6e5b653e-459e-4268-8f49-fdcf5a917c19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940455682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2940455682
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all_with_rand_reset.950085737
Short name	T442
Test name
Test status
Simulation time	496208738466 ps
CPU time	1176.09 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:27:26 PM PDT 24
Peak memory	232500 kb
Host	smart-73de8376-8750-4ced-bdaf-acbc1d73a72b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950085737 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.950085737
Directory	/workspace/26.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.3468684911
Short name	T74
Test name
Test status
Simulation time	6479887314 ps
CPU time	16.17 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:08:13 PM PDT 24
Peak memory	199652 kb
Host	smart-397a8361-6771-4d73-80bb-949e8f1ae0de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468684911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3468684911
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.1215202354
Short name	T474
Test name
Test status
Simulation time	28187979076 ps
CPU time	44.9 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:47 PM PDT 24
Peak memory	199988 kb
Host	smart-90333586-eb78-477e-abdb-b68b8934cfa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215202354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1215202354
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.1325371488
Short name	T279
Test name
Test status
Simulation time	127638293455 ps
CPU time	53.61 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:48 PM PDT 24
Peak memory	200176 kb
Host	smart-aa8d6270-889f-4b35-83b3-78088a669d8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325371488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1325371488
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.3546884083
Short name	T314
Test name
Test status
Simulation time	144877472234 ps
CPU time	126.97 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:12:02 PM PDT 24
Peak memory	200140 kb
Host	smart-d6d48a3d-d3c9-4f83-af6c-f29da74a4d99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546884083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3546884083
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.486268388
Short name	T984
Test name
Test status
Simulation time	111524383427 ps
CPU time	111.62 seconds
Started	Mar 12 01:09:56 PM PDT 24
Finished	Mar 12 01:11:48 PM PDT 24
Peak memory	200108 kb
Host	smart-594a18a9-dd54-4b00-a7f1-5e7d0292281b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486268388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.486268388
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.1176480034
Short name	T132
Test name
Test status
Simulation time	35899346102 ps
CPU time	16.38 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:10:12 PM PDT 24
Peak memory	200148 kb
Host	smart-53e0452b-52a7-4d16-ac27-8ba7e6742327
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176480034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1176480034
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.4293718992
Short name	T137
Test name
Test status
Simulation time	147963996725 ps
CPU time	44.19 seconds
Started	Mar 12 01:09:58 PM PDT 24
Finished	Mar 12 01:10:43 PM PDT 24
Peak memory	199308 kb
Host	smart-47e31f02-283a-42ee-a510-bd87aafb7b6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293718992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4293718992
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.2655455534
Short name	T336
Test name
Test status
Simulation time	113554368956 ps
CPU time	46.63 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:41 PM PDT 24
Peak memory	200024 kb
Host	smart-6fe8324f-c4ad-40b2-82b5-5f48a5fc99dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655455534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2655455534
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.562472029
Short name	T1057
Test name
Test status
Simulation time	50241644372 ps
CPU time	69 seconds
Started	Mar 12 01:09:56 PM PDT 24
Finished	Mar 12 01:11:05 PM PDT 24
Peak memory	199972 kb
Host	smart-e4c2802f-9b02-4dfb-b6ce-6867e23342a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562472029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.562472029
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.2220014007
Short name	T620
Test name
Test status
Simulation time	40884064 ps
CPU time	0.54 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:07:55 PM PDT 24
Peak memory	195460 kb
Host	smart-88e0d57e-82bd-4d6b-a0b9-5ab4409fbe84
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220014007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2220014007
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.4164985572
Short name	T901
Test name
Test status
Simulation time	49519407709 ps
CPU time	24.81 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:08:14 PM PDT 24
Peak memory	200132 kb
Host	smart-604d2633-4531-4f70-b65f-78ea498638f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164985572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4164985572
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.176377482
Short name	T681
Test name
Test status
Simulation time	118234820486 ps
CPU time	193.47 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:11:02 PM PDT 24
Peak memory	200120 kb
Host	smart-a7686b1a-1ff8-4d06-a2ea-ee7458799176
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176377482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.176377482
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/27.uart_intr.2619558529
Short name	T970
Test name
Test status
Simulation time	51614998091 ps
CPU time	37.11 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:36 PM PDT 24
Peak memory	200060 kb
Host	smart-d9b11349-27c8-4abb-ab0d-f2c2ecafecce
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619558529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2619558529
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.893520602
Short name	T580
Test name
Test status
Simulation time	73957149067 ps
CPU time	514.7 seconds
Started	Mar 12 01:07:51 PM PDT 24
Finished	Mar 12 01:16:26 PM PDT 24
Peak memory	200080 kb
Host	smart-e6ae553e-aae4-43da-9c88-33da4d362a9f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=893520602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.893520602
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.4284290063
Short name	T961
Test name
Test status
Simulation time	1317173581 ps
CPU time	2.4 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:07:56 PM PDT 24
Peak memory	198284 kb
Host	smart-faf365c1-3d6f-4f21-b08d-455af92c25bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284290063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.4284290063
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.2235754124
Short name	T941
Test name
Test status
Simulation time	93577595205 ps
CPU time	49.45 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:08:48 PM PDT 24
Peak memory	208568 kb
Host	smart-b3b4f0e7-5ea5-4126-ac49-70bdbe0b754a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235754124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2235754124
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.54639673
Short name	T699
Test name
Test status
Simulation time	1958040613 ps
CPU time	85.43 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:09:24 PM PDT 24
Peak memory	199812 kb
Host	smart-174444b9-a42e-49bd-9357-fb39419bb9f2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=54639673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.54639673
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.1048798327
Short name	T659
Test name
Test status
Simulation time	4949450583 ps
CPU time	2.6 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:07:56 PM PDT 24
Peak memory	198892 kb
Host	smart-4f074bfa-a1c4-4f22-b77b-bb866c4bc9cb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1048798327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1048798327
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.3460052782
Short name	T654
Test name
Test status
Simulation time	206857775421 ps
CPU time	278.59 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:12:37 PM PDT 24
Peak memory	199216 kb
Host	smart-297b1e37-085a-45d0-994b-5e88b1fa9b35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460052782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3460052782
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.3403781164
Short name	T745
Test name
Test status
Simulation time	30059244814 ps
CPU time	12.83 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:08:02 PM PDT 24
Peak memory	195552 kb
Host	smart-e9fd0532-f401-4c67-96c8-d70f34a04971
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403781164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3403781164
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.1775199047
Short name	T1102
Test name
Test status
Simulation time	779667073 ps
CPU time	1.23 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:07:59 PM PDT 24
Peak memory	198832 kb
Host	smart-e302a537-c2f8-49e5-87e3-0fb3d93d8ef5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775199047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1775199047
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all.3567520431
Short name	T373
Test name
Test status
Simulation time	632490777977 ps
CPU time	590.33 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:17:48 PM PDT 24
Peak memory	208540 kb
Host	smart-924f3de5-296c-4e7b-a32e-f9399c6be1fc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567520431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3567520431
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.3260565856
Short name	T923
Test name
Test status
Simulation time	6686039623 ps
CPU time	28.26 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:08:18 PM PDT 24
Peak memory	199848 kb
Host	smart-b3833bae-a6e5-47d5-805f-d50abcb3583b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260565856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3260565856
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.194338551
Short name	T502
Test name
Test status
Simulation time	107569259827 ps
CPU time	99.27 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:09:41 PM PDT 24
Peak memory	200136 kb
Host	smart-20bcc8cd-e392-4cf7-aaa3-556196a2e430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194338551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.194338551
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.3577013993
Short name	T258
Test name
Test status
Simulation time	89518122511 ps
CPU time	39.41 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:34 PM PDT 24
Peak memory	199860 kb
Host	smart-9ad2310f-1b8e-44ec-98a3-99d62ab5d75d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577013993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3577013993
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.3701469047
Short name	T323
Test name
Test status
Simulation time	167078381708 ps
CPU time	66 seconds
Started	Mar 12 01:09:55 PM PDT 24
Finished	Mar 12 01:11:01 PM PDT 24
Peak memory	200100 kb
Host	smart-727360cf-cf06-48d0-b9b1-ba12c2dbe4a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701469047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3701469047
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.1991345139
Short name	T711
Test name
Test status
Simulation time	108602969515 ps
CPU time	23.48 seconds
Started	Mar 12 01:09:58 PM PDT 24
Finished	Mar 12 01:10:22 PM PDT 24
Peak memory	199156 kb
Host	smart-7b31c5b5-1602-4369-828e-ab296a224d95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991345139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1991345139
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/274.uart_fifo_reset.1729416409
Short name	T559
Test name
Test status
Simulation time	7541072410 ps
CPU time	12.47 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:07 PM PDT 24
Peak memory	199148 kb
Host	smart-1bf68b4b-93a3-4a1e-976b-29936d966909
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729416409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1729416409
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.452808603
Short name	T234
Test name
Test status
Simulation time	12971291359 ps
CPU time	22.19 seconds
Started	Mar 12 01:09:54 PM PDT 24
Finished	Mar 12 01:10:16 PM PDT 24
Peak memory	199696 kb
Host	smart-a8418d81-3613-4b14-ad9d-5e024545643b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452808603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.452808603
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.1514202746
Short name	T146
Test name
Test status
Simulation time	12770185374 ps
CPU time	5.39 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:10:11 PM PDT 24
Peak memory	198804 kb
Host	smart-7e5ae51c-7a92-48f4-8af4-02265074ade6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514202746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1514202746
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.2100035602
Short name	T8
Test name
Test status
Simulation time	23920602861 ps
CPU time	16.43 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:10:23 PM PDT 24
Peak memory	200132 kb
Host	smart-30a12be7-52aa-427b-aee3-bba16e48ff36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100035602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2100035602
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.766822714
Short name	T157
Test name
Test status
Simulation time	20330795356 ps
CPU time	32.71 seconds
Started	Mar 12 01:10:08 PM PDT 24
Finished	Mar 12 01:10:41 PM PDT 24
Peak memory	200088 kb
Host	smart-6a64b5a5-df78-42e2-a51f-b999d1c3802b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766822714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.766822714
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.1537838835
Short name	T873
Test name
Test status
Simulation time	44829917 ps
CPU time	0.57 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:07:48 PM PDT 24
Peak memory	195556 kb
Host	smart-0afeccd9-5744-4821-8e0e-c9cc79ad1ceb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537838835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1537838835
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.617096921
Short name	T945
Test name
Test status
Simulation time	36807947864 ps
CPU time	69.91 seconds
Started	Mar 12 01:07:54 PM PDT 24
Finished	Mar 12 01:09:05 PM PDT 24
Peak memory	200096 kb
Host	smart-9aadbfd0-9ccb-4ecf-a92a-cdb8d09bb6ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617096921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.617096921
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.2221244542
Short name	T849
Test name
Test status
Simulation time	221890301989 ps
CPU time	521.43 seconds
Started	Mar 12 01:08:00 PM PDT 24
Finished	Mar 12 01:16:42 PM PDT 24
Peak memory	200000 kb
Host	smart-7efb9229-2737-4309-a646-52481d6da20b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221244542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2221244542
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.1382294087
Short name	T235
Test name
Test status
Simulation time	128907586758 ps
CPU time	47.98 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:08:38 PM PDT 24
Peak memory	200004 kb
Host	smart-6eb37372-c342-4fe9-829a-ee48966b87d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382294087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1382294087
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.1895472368
Short name	T947
Test name
Test status
Simulation time	80826868159 ps
CPU time	113.78 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:09:44 PM PDT 24
Peak memory	200032 kb
Host	smart-055aac58-dd45-4398-b289-93909e4981f3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895472368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1895472368
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.485225377
Short name	T914
Test name
Test status
Simulation time	42575434031 ps
CPU time	271.65 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:12:21 PM PDT 24
Peak memory	200004 kb
Host	smart-febc345c-707e-45a3-8b41-4f3bbea497ba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=485225377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.485225377
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.553474702
Short name	T826
Test name
Test status
Simulation time	4462332949 ps
CPU time	3.3 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:07:58 PM PDT 24
Peak memory	197716 kb
Host	smart-7fc7722a-7333-47bf-9206-d8360ff51878
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553474702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.553474702
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.239763817
Short name	T1011
Test name
Test status
Simulation time	26322053870 ps
CPU time	38.67 seconds
Started	Mar 12 01:07:53 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	197356 kb
Host	smart-d115ee66-1031-4ffb-b8b9-ca1055a806b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=239763817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.239763817
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.191108647
Short name	T865
Test name
Test status
Simulation time	1104758784 ps
CPU time	52.48 seconds
Started	Mar 12 01:07:48 PM PDT 24
Finished	Mar 12 01:08:41 PM PDT 24
Peak memory	200012 kb
Host	smart-7175105a-4e04-4693-9c84-c8f758a66e80
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=191108647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.191108647
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.2461141274
Short name	T557
Test name
Test status
Simulation time	4425599996 ps
CPU time	8.23 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	198900 kb
Host	smart-ba612d10-321a-4984-86ba-b5baf40d5527
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2461141274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2461141274
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.1914657259
Short name	T321
Test name
Test status
Simulation time	73258819251 ps
CPU time	128.21 seconds
Started	Mar 12 01:07:54 PM PDT 24
Finished	Mar 12 01:10:03 PM PDT 24
Peak memory	200144 kb
Host	smart-f78f901a-50d0-4af7-8ec0-7fd121e16a96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914657259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1914657259
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.1502290155
Short name	T1093
Test name
Test status
Simulation time	37245637875 ps
CPU time	16.6 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:16 PM PDT 24
Peak memory	195612 kb
Host	smart-ddcee488-5757-4869-b273-ee452bac231b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502290155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1502290155
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.1744114531
Short name	T997
Test name
Test status
Simulation time	743714101 ps
CPU time	1.56 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:07:52 PM PDT 24
Peak memory	198452 kb
Host	smart-67b49559-fdb5-4658-8cbf-72a740816ecd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744114531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1744114531
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_stress_all.3379490052
Short name	T340
Test name
Test status
Simulation time	400746963722 ps
CPU time	557.22 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:17:07 PM PDT 24
Peak memory	200088 kb
Host	smart-08cd946f-b2cc-4204-a41f-1479cd773dc7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379490052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3379490052
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.3294500784
Short name	T1013
Test name
Test status
Simulation time	6963589392 ps
CPU time	9.07 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:08:07 PM PDT 24
Peak memory	198956 kb
Host	smart-94c5ea44-dcba-4582-aa7b-8242f3497ee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294500784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3294500784
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.353471371
Short name	T459
Test name
Test status
Simulation time	1743950998 ps
CPU time	3.08 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:07:56 PM PDT 24
Peak memory	196800 kb
Host	smart-7136eaa1-ed05-43ef-88bb-523c3cfb0839
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353471371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.353471371
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.219013826
Short name	T1031
Test name
Test status
Simulation time	91180696512 ps
CPU time	132.12 seconds
Started	Mar 12 01:10:07 PM PDT 24
Finished	Mar 12 01:12:19 PM PDT 24
Peak memory	200068 kb
Host	smart-0fbc96e2-5535-42c2-a615-6b76aa571d5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219013826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.219013826
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.3784765062
Short name	T1023
Test name
Test status
Simulation time	8014538130 ps
CPU time	14.55 seconds
Started	Mar 12 01:10:04 PM PDT 24
Finished	Mar 12 01:10:19 PM PDT 24
Peak memory	199372 kb
Host	smart-179fcacb-38e6-4ab4-b8f4-3e1bb21a38e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784765062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3784765062
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.2034851666
Short name	T872
Test name
Test status
Simulation time	45855786211 ps
CPU time	33 seconds
Started	Mar 12 01:10:07 PM PDT 24
Finished	Mar 12 01:10:40 PM PDT 24
Peak memory	200184 kb
Host	smart-eb18a860-5292-4f08-bfae-0a78524a4629
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034851666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2034851666
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.3776520319
Short name	T45
Test name
Test status
Simulation time	7935210757 ps
CPU time	13.86 seconds
Started	Mar 12 01:10:05 PM PDT 24
Finished	Mar 12 01:10:20 PM PDT 24
Peak memory	198896 kb
Host	smart-52baf672-e52f-41ba-9ced-90e2f93cfbda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776520319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3776520319
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.4071779428
Short name	T1018
Test name
Test status
Simulation time	26950775810 ps
CPU time	13.3 seconds
Started	Mar 12 01:10:07 PM PDT 24
Finished	Mar 12 01:10:21 PM PDT 24
Peak memory	198080 kb
Host	smart-8faf49aa-0e3f-4963-8f4b-5908f4fe9ffe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071779428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4071779428
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.3779119786
Short name	T683
Test name
Test status
Simulation time	20451689479 ps
CPU time	134.87 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:12:21 PM PDT 24
Peak memory	200088 kb
Host	smart-e55adfd9-d7f6-4f69-bd40-c247e9e4a33f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779119786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3779119786
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.1678060567
Short name	T1029
Test name
Test status
Simulation time	102342087035 ps
CPU time	45.69 seconds
Started	Mar 12 01:10:05 PM PDT 24
Finished	Mar 12 01:10:51 PM PDT 24
Peak memory	200160 kb
Host	smart-e653336f-4f70-4b42-a637-4832738f5e25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678060567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1678060567
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.3241062747
Short name	T165
Test name
Test status
Simulation time	127026936761 ps
CPU time	66.23 seconds
Started	Mar 12 01:10:07 PM PDT 24
Finished	Mar 12 01:11:14 PM PDT 24
Peak memory	199780 kb
Host	smart-c62d08ee-0674-490b-bc96-49f297ebe7cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241062747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3241062747
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.3580424096
Short name	T946
Test name
Test status
Simulation time	171294620770 ps
CPU time	38.38 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:10:44 PM PDT 24
Peak memory	200132 kb
Host	smart-12fd5768-20c6-4e70-81d9-262d34762dd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580424096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3580424096
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.370091433
Short name	T6
Test name
Test status
Simulation time	19620788426 ps
CPU time	21.46 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:10:27 PM PDT 24
Peak memory	199980 kb
Host	smart-55e900cb-3361-4ddf-bdd1-8bfdceac4021
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=370091433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.370091433
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.1148001402
Short name	T917
Test name
Test status
Simulation time	38268851 ps
CPU time	0.54 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:00 PM PDT 24
Peak memory	195536 kb
Host	smart-b88206a2-1abb-4688-8f39-d6d793c6bc28
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148001402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1148001402
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.2167023747
Short name	T668
Test name
Test status
Simulation time	64032717511 ps
CPU time	104.27 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:09:47 PM PDT 24
Peak memory	200104 kb
Host	smart-ef26dae1-d1f6-4591-b9c6-feb4c463b012
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167023747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2167023747
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.943090235
Short name	T386
Test name
Test status
Simulation time	74871524640 ps
CPU time	68.52 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:09:06 PM PDT 24
Peak memory	200204 kb
Host	smart-1bdb2adb-a50d-448c-b1a7-6d0f17a11d39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943090235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.943090235
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.3520666122
Short name	T963
Test name
Test status
Simulation time	153209875230 ps
CPU time	150.18 seconds
Started	Mar 12 01:08:04 PM PDT 24
Finished	Mar 12 01:10:34 PM PDT 24
Peak memory	200056 kb
Host	smart-f01229b6-3a18-4bc0-80ba-14863d2cde4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520666122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3520666122
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_intr.454215129
Short name	T761
Test name
Test status
Simulation time	10250251328 ps
CPU time	8.05 seconds
Started	Mar 12 01:07:52 PM PDT 24
Finished	Mar 12 01:08:01 PM PDT 24
Peak memory	196480 kb
Host	smart-a3d1b1df-7e8b-4fd3-9ec6-b05fef590d49
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454215129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.454215129
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_loopback.2617676071
Short name	T464
Test name
Test status
Simulation time	3652553257 ps
CPU time	4.3 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:08:01 PM PDT 24
Peak memory	198312 kb
Host	smart-e2b350bb-6361-4a49-8be3-a015a502a58d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617676071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2617676071
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.3035408572
Short name	T535
Test name
Test status
Simulation time	38348726309 ps
CPU time	33.75 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:37 PM PDT 24
Peak memory	198544 kb
Host	smart-5e767399-133a-4fd9-9007-4a25f3467d50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035408572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3035408572
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.194876130
Short name	T1112
Test name
Test status
Simulation time	34576471153 ps
CPU time	1013.64 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:24:57 PM PDT 24
Peak memory	200128 kb
Host	smart-e3377046-cd81-41b2-9e15-0772974291e8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=194876130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.194876130
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.2276462805
Short name	T753
Test name
Test status
Simulation time	1907823416 ps
CPU time	9.01 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:08:05 PM PDT 24
Peak memory	198248 kb
Host	smart-1d3250ee-8b58-4b32-a50a-00a70eb0588f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2276462805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2276462805
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.2289459595
Short name	T491
Test name
Test status
Simulation time	5588974383 ps
CPU time	4.81 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	195864 kb
Host	smart-e29c4234-ecc7-420e-9306-b6867c991d99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289459595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2289459595
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.1182940667
Short name	T1089
Test name
Test status
Simulation time	307901445 ps
CPU time	1.23 seconds
Started	Mar 12 01:07:47 PM PDT 24
Finished	Mar 12 01:07:48 PM PDT 24
Peak memory	198424 kb
Host	smart-bde271fa-3011-4d14-9cc5-61fb3de73da9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182940667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1182940667
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.1336979082
Short name	T378
Test name
Test status
Simulation time	75355128348 ps
CPU time	160 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:10:43 PM PDT 24
Peak memory	200160 kb
Host	smart-6a2c5245-6438-4437-8b69-973e391f89b1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336979082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1336979082
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_stress_all_with_rand_reset.1626558662
Short name	T72
Test name
Test status
Simulation time	79511735966 ps
CPU time	219.59 seconds
Started	Mar 12 01:08:00 PM PDT 24
Finished	Mar 12 01:11:40 PM PDT 24
Peak memory	216016 kb
Host	smart-0d199324-b951-4f28-967a-88969c20355a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626558662 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1626558662
Directory	/workspace/29.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.2895402828
Short name	T831
Test name
Test status
Simulation time	2273464651 ps
CPU time	1.98 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	199328 kb
Host	smart-79cdfb5a-3036-4cf0-ac05-49057b470b2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895402828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2895402828
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.2032272224
Short name	T860
Test name
Test status
Simulation time	51873330864 ps
CPU time	26.62 seconds
Started	Mar 12 01:07:49 PM PDT 24
Finished	Mar 12 01:08:16 PM PDT 24
Peak memory	200132 kb
Host	smart-5b6a8ea0-be0c-4d80-9270-8c176199966d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032272224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2032272224
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.3227418238
Short name	T248
Test name
Test status
Simulation time	67247383850 ps
CPU time	118.28 seconds
Started	Mar 12 01:10:08 PM PDT 24
Finished	Mar 12 01:12:07 PM PDT 24
Peak memory	200048 kb
Host	smart-3a542037-d45b-4a68-b73c-acabee7006e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227418238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3227418238
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.2629551402
Short name	T1072
Test name
Test status
Simulation time	21627170134 ps
CPU time	11.61 seconds
Started	Mar 12 01:10:07 PM PDT 24
Finished	Mar 12 01:10:20 PM PDT 24
Peak memory	200148 kb
Host	smart-d01c36a0-fe31-42a7-9b21-e56f36f53dcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629551402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2629551402
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.1776813477
Short name	T312
Test name
Test status
Simulation time	21421618312 ps
CPU time	21.36 seconds
Started	Mar 12 01:10:10 PM PDT 24
Finished	Mar 12 01:10:31 PM PDT 24
Peak memory	199880 kb
Host	smart-45097031-057c-4b2e-b2f7-0ed4db4db514
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776813477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1776813477
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.4112660834
Short name	T635
Test name
Test status
Simulation time	50876938247 ps
CPU time	30.13 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:10:36 PM PDT 24
Peak memory	200084 kb
Host	smart-ea58a02b-7ab7-4778-9244-1e4d158e4f9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112660834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4112660834
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.4183071246
Short name	T283
Test name
Test status
Simulation time	22914064919 ps
CPU time	41.23 seconds
Started	Mar 12 01:10:08 PM PDT 24
Finished	Mar 12 01:10:50 PM PDT 24
Peak memory	199880 kb
Host	smart-848ca594-c787-4ff7-a93c-b58efd45f65d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183071246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4183071246
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.1631363884
Short name	T280
Test name
Test status
Simulation time	12404393715 ps
CPU time	10.86 seconds
Started	Mar 12 01:10:07 PM PDT 24
Finished	Mar 12 01:10:19 PM PDT 24
Peak memory	199244 kb
Host	smart-118d9d04-a869-4cad-b88c-980f6e7504c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631363884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1631363884
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.4252827032
Short name	T1017
Test name
Test status
Simulation time	25375276323 ps
CPU time	20.17 seconds
Started	Mar 12 01:10:09 PM PDT 24
Finished	Mar 12 01:10:29 PM PDT 24
Peak memory	200028 kb
Host	smart-ed089754-606f-44a6-a8dc-0768aed750f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252827032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.4252827032
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.4089742095
Short name	T335
Test name
Test status
Simulation time	147660508791 ps
CPU time	39.77 seconds
Started	Mar 12 01:10:06 PM PDT 24
Finished	Mar 12 01:10:46 PM PDT 24
Peak memory	199904 kb
Host	smart-b90007bc-f21a-446e-b755-d881bc29aa4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089742095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4089742095
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.4226693713
Short name	T616
Test name
Test status
Simulation time	19558456 ps
CPU time	0.59 seconds
Started	Mar 12 01:06:57 PM PDT 24
Finished	Mar 12 01:06:57 PM PDT 24
Peak memory	195560 kb
Host	smart-27693239-322f-476e-8bd6-f41de4c5f0eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226693713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4226693713
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.1320474860
Short name	T1116
Test name
Test status
Simulation time	225668221089 ps
CPU time	178.82 seconds
Started	Mar 12 01:07:04 PM PDT 24
Finished	Mar 12 01:10:03 PM PDT 24
Peak memory	200116 kb
Host	smart-27c0d7fb-51ab-4ea6-b3ac-9cb0fd341a7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320474860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1320474860
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.1336135362
Short name	T392
Test name
Test status
Simulation time	38289232141 ps
CPU time	59.71 seconds
Started	Mar 12 01:06:52 PM PDT 24
Finished	Mar 12 01:07:53 PM PDT 24
Peak memory	199440 kb
Host	smart-f2573f1a-dca8-4cbc-87ea-774d017041b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336135362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1336135362
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/3.uart_intr.2204109803
Short name	T1079
Test name
Test status
Simulation time	60223358378 ps
CPU time	15.98 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:07:16 PM PDT 24
Peak memory	199184 kb
Host	smart-98b05da4-cb78-4056-9763-dd4099662ff0
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204109803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2204109803
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.1054098054
Short name	T516
Test name
Test status
Simulation time	69777637074 ps
CPU time	635.29 seconds
Started	Mar 12 01:06:54 PM PDT 24
Finished	Mar 12 01:17:31 PM PDT 24
Peak memory	200136 kb
Host	smart-2a9565b5-0f6a-42f8-acfb-5dc97444bf39
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1054098054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1054098054
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.1204358702
Short name	T656
Test name
Test status
Simulation time	9758418108 ps
CPU time	8.15 seconds
Started	Mar 12 01:07:11 PM PDT 24
Finished	Mar 12 01:07:21 PM PDT 24
Peak memory	200024 kb
Host	smart-de8d82d9-fd34-4cb8-8f36-f7f8e440f088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204358702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1204358702
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.465572878
Short name	T427
Test name
Test status
Simulation time	89413554668 ps
CPU time	41.55 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:47 PM PDT 24
Peak memory	198536 kb
Host	smart-7cae9d03-4fe4-4ea5-ac0d-caeecc6aa6f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465572878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.465572878
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.1662591158
Short name	T875
Test name
Test status
Simulation time	14196173221 ps
CPU time	680.7 seconds
Started	Mar 12 01:06:45 PM PDT 24
Finished	Mar 12 01:18:06 PM PDT 24
Peak memory	200092 kb
Host	smart-f237d398-530b-40d9-82d2-9e7d6ff4f048
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1662591158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1662591158
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.3746681584
Short name	T675
Test name
Test status
Simulation time	3895111322 ps
CPU time	4.18 seconds
Started	Mar 12 01:06:57 PM PDT 24
Finished	Mar 12 01:07:02 PM PDT 24
Peak memory	198656 kb
Host	smart-be0483ad-5848-432a-aa77-b46051c0eec6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3746681584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3746681584
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.4104711951
Short name	T374
Test name
Test status
Simulation time	37550620367 ps
CPU time	16.64 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:22 PM PDT 24
Peak memory	200192 kb
Host	smart-853b8fe9-096f-4136-a8df-53cfebb8367a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104711951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4104711951
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.1186254899
Short name	T702
Test name
Test status
Simulation time	6457727226 ps
CPU time	3.22 seconds
Started	Mar 12 01:06:52 PM PDT 24
Finished	Mar 12 01:06:57 PM PDT 24
Peak memory	195824 kb
Host	smart-06c5e436-43ac-4d48-a358-bb08c48c029e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186254899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1186254899
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_smoke.2126538233
Short name	T626
Test name
Test status
Simulation time	125365514 ps
CPU time	1.13 seconds
Started	Mar 12 01:06:54 PM PDT 24
Finished	Mar 12 01:06:57 PM PDT 24
Peak memory	198028 kb
Host	smart-33267a9b-091f-483f-9a67-95e00936d23e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126538233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2126538233
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.4006746907
Short name	T414
Test name
Test status
Simulation time	2045861181 ps
CPU time	3.48 seconds
Started	Mar 12 01:06:51 PM PDT 24
Finished	Mar 12 01:06:55 PM PDT 24
Peak memory	198536 kb
Host	smart-8a1b743d-7f0c-4927-a23e-9869e60c3875
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006746907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4006746907
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.3053336549
Short name	T706
Test name
Test status
Simulation time	43423695700 ps
CPU time	31.17 seconds
Started	Mar 12 01:06:55 PM PDT 24
Finished	Mar 12 01:07:27 PM PDT 24
Peak memory	200120 kb
Host	smart-794acdc1-1f31-4a68-9045-43c338f17edf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053336549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3053336549
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.536946224
Short name	T1007
Test name
Test status
Simulation time	12109293 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:07:55 PM PDT 24
Peak memory	195544 kb
Host	smart-38ed823e-2556-47f2-b811-37a287411d1f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536946224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.536946224
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.3615654395
Short name	T350
Test name
Test status
Simulation time	109792198847 ps
CPU time	51.07 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:08:49 PM PDT 24
Peak memory	200128 kb
Host	smart-65594bce-b375-4c81-900c-a862f615112d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615654395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3615654395
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_intr.2018709314
Short name	T695
Test name
Test status
Simulation time	171112448013 ps
CPU time	133.64 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:10:16 PM PDT 24
Peak memory	200128 kb
Host	smart-47bbf7b7-d65d-4865-941e-ff64a27f4ed7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018709314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2018709314
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.1027532666
Short name	T958
Test name
Test status
Simulation time	112169504264 ps
CPU time	591.41 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:17:54 PM PDT 24
Peak memory	200136 kb
Host	smart-cda4769a-e122-43b5-a542-aff024798dc8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1027532666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1027532666
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_loopback.1088483274
Short name	T730
Test name
Test status
Simulation time	5788578196 ps
CPU time	2.53 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	199104 kb
Host	smart-d2e50ed1-95cd-4e9c-b560-d5dc75f6f7a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1088483274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1088483274
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.1025583181
Short name	T639
Test name
Test status
Simulation time	47024347681 ps
CPU time	87.03 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:09:31 PM PDT 24
Peak memory	198316 kb
Host	smart-048f2509-2398-4ef4-abe8-078bb4e4f35d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1025583181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1025583181
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_perf.3265026765
Short name	T825
Test name
Test status
Simulation time	11004057305 ps
CPU time	471.85 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:15:54 PM PDT 24
Peak memory	200132 kb
Host	smart-c382359e-daee-4cf3-8c4a-4e8083c358f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3265026765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3265026765
Directory	/workspace/30.uart_perf/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.563726072
Short name	T812
Test name
Test status
Simulation time	5414054283 ps
CPU time	26.88 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:08:23 PM PDT 24
Peak memory	198432 kb
Host	smart-8dcd3ee9-a807-4a89-bad7-c5c09ef041ea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=563726072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.563726072
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.44338939
Short name	T405
Test name
Test status
Simulation time	52814264735 ps
CPU time	92.36 seconds
Started	Mar 12 01:07:55 PM PDT 24
Finished	Mar 12 01:09:28 PM PDT 24
Peak memory	200064 kb
Host	smart-fb264f21-ff2d-4e27-9c4a-80d15d22a4ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44338939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.44338939
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.2224547444
Short name	T601
Test name
Test status
Simulation time	560794115 ps
CPU time	1.35 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:05 PM PDT 24
Peak memory	195460 kb
Host	smart-4637fe2b-eb14-4581-b47d-318391691197
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224547444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2224547444
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.3705481607
Short name	T1078
Test name
Test status
Simulation time	461285620 ps
CPU time	1.82 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:01 PM PDT 24
Peak memory	199412 kb
Host	smart-4a06ca41-4200-4a39-acba-d0b947c7d76a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705481607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3705481607
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all.1980891420
Short name	T1109
Test name
Test status
Simulation time	199214895519 ps
CPU time	87.22 seconds
Started	Mar 12 01:07:50 PM PDT 24
Finished	Mar 12 01:09:17 PM PDT 24
Peak memory	199952 kb
Host	smart-a49db41d-78c5-4ba3-bc1b-992d4953e466
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980891420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1980891420
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.67214777
Short name	T21
Test name
Test status
Simulation time	6712377599 ps
CPU time	13.27 seconds
Started	Mar 12 01:08:00 PM PDT 24
Finished	Mar 12 01:08:14 PM PDT 24
Peak memory	199544 kb
Host	smart-03093adb-1a86-4693-af06-a92cc7ccdd31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67214777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.67214777
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.2284730146
Short name	T657
Test name
Test status
Simulation time	98847452237 ps
CPU time	78.67 seconds
Started	Mar 12 01:07:53 PM PDT 24
Finished	Mar 12 01:09:13 PM PDT 24
Peak memory	200132 kb
Host	smart-c9650ebc-def8-4ad7-bc0e-ef7ef076fdbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284730146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2284730146
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.1097439865
Short name	T591
Test name
Test status
Simulation time	13815601 ps
CPU time	0.64 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:03 PM PDT 24
Peak memory	195528 kb
Host	smart-2240918c-47da-4727-9b77-914fa0ea4d5a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097439865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1097439865
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.351002072
Short name	T898
Test name
Test status
Simulation time	163517792863 ps
CPU time	117.91 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:09:55 PM PDT 24
Peak memory	200104 kb
Host	smart-e7afe9b8-9f3e-4e76-953e-80a934e97534
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351002072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.351002072
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.4197124104
Short name	T851
Test name
Test status
Simulation time	18606456133 ps
CPU time	29.29 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	199040 kb
Host	smart-5a863cbe-abd8-4fac-a53a-1017b2c7aafb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197124104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4197124104
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.3062209359
Short name	T142
Test name
Test status
Simulation time	33709414033 ps
CPU time	54.56 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:58 PM PDT 24
Peak memory	200100 kb
Host	smart-65ac583f-f663-42df-b44a-3c490691ca1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062209359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3062209359
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.1131270009
Short name	T953
Test name
Test status
Simulation time	14145271302 ps
CPU time	21.42 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:08:19 PM PDT 24
Peak memory	196632 kb
Host	smart-01ca9107-cb4f-4153-b98b-212fa3c46924
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131270009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1131270009
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.2973618665
Short name	T584
Test name
Test status
Simulation time	94383356128 ps
CPU time	623.75 seconds
Started	Mar 12 01:08:11 PM PDT 24
Finished	Mar 12 01:18:35 PM PDT 24
Peak memory	200180 kb
Host	smart-93996c1e-b9c2-41e4-bb0b-67d656c42d72
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2973618665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2973618665
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_loopback.1258043910
Short name	T918
Test name
Test status
Simulation time	9836203480 ps
CPU time	3.59 seconds
Started	Mar 12 01:08:00 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	199260 kb
Host	smart-f1278704-d0e6-4b63-b1d9-2daa32b06402
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258043910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1258043910
Directory	/workspace/31.uart_loopback/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.2027331243
Short name	T583
Test name
Test status
Simulation time	75255298052 ps
CPU time	66.9 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:09:10 PM PDT 24
Peak memory	200068 kb
Host	smart-51aaae6f-3b6d-485a-9c02-c8f857f3ba18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027331243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2027331243
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.1577038786
Short name	T573
Test name
Test status
Simulation time	20960847069 ps
CPU time	103.46 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:09:42 PM PDT 24
Peak memory	200080 kb
Host	smart-165b2419-512c-485d-8336-ee11f6321204
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1577038786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1577038786
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_oversample.2464473465
Short name	T852
Test name
Test status
Simulation time	4244740168 ps
CPU time	9.83 seconds
Started	Mar 12 01:07:56 PM PDT 24
Finished	Mar 12 01:08:06 PM PDT 24
Peak memory	198912 kb
Host	smart-98b564de-3bdc-41d2-8b95-79c65c64bfa5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2464473465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2464473465
Directory	/workspace/31.uart_rx_oversample/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.4091473607
Short name	T240
Test name
Test status
Simulation time	249777793879 ps
CPU time	50.57 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:50 PM PDT 24
Peak memory	199608 kb
Host	smart-af1f6711-6694-4e93-bdb7-d9b55d9817db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091473607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.4091473607
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.625378194
Short name	T517
Test name
Test status
Simulation time	36271003621 ps
CPU time	56.54 seconds
Started	Mar 12 01:07:57 PM PDT 24
Finished	Mar 12 01:08:54 PM PDT 24
Peak memory	195908 kb
Host	smart-21e7dbf8-bf7f-4a1c-a2dd-5086bdf121da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625378194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.625378194
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.3886581146
Short name	T762
Test name
Test status
Simulation time	629696357 ps
CPU time	1.54 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:05 PM PDT 24
Peak memory	197968 kb
Host	smart-483be58f-381c-41f1-a1b2-6a7d2d279856
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886581146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3886581146
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.2132641093
Short name	T781
Test name
Test status
Simulation time	3759438926 ps
CPU time	1.73 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	199520 kb
Host	smart-9cb5c495-a2af-46b6-895f-588a41dab2a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132641093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2132641093
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.2187460660
Short name	T779
Test name
Test status
Simulation time	96364412541 ps
CPU time	47.99 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:50 PM PDT 24
Peak memory	200096 kb
Host	smart-0312fea0-294a-437c-8023-764961858c23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187460660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2187460660
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.138399459
Short name	T452
Test name
Test status
Simulation time	20969212 ps
CPU time	0.6 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	194492 kb
Host	smart-6371138f-f77c-46b3-8f87-6eeb30bf1a02
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138399459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.138399459
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.3865076864
Short name	T396
Test name
Test status
Simulation time	118397916322 ps
CPU time	97.95 seconds
Started	Mar 12 01:08:01 PM PDT 24
Finished	Mar 12 01:09:39 PM PDT 24
Peak memory	200152 kb
Host	smart-7fc9bf03-243f-4958-96c6-d6abcd3798b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865076864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3865076864
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.3943634726
Short name	T579
Test name
Test status
Simulation time	42421948516 ps
CPU time	16.82 seconds
Started	Mar 12 01:08:11 PM PDT 24
Finished	Mar 12 01:08:29 PM PDT 24
Peak memory	199824 kb
Host	smart-b5f4f664-2330-4dbe-9c91-8d343e9e33fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943634726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3943634726
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.1878370823
Short name	T237
Test name
Test status
Simulation time	5747679868 ps
CPU time	3.22 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:08:01 PM PDT 24
Peak memory	200008 kb
Host	smart-3d1c3af2-227e-441b-99a1-9a6c62ca962b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878370823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1878370823
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.2430608990
Short name	T939
Test name
Test status
Simulation time	73632365973 ps
CPU time	345.34 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:13:53 PM PDT 24
Peak memory	200072 kb
Host	smart-79c14b1b-a147-4b36-ba83-a2ae71745af8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2430608990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2430608990
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.3739514452
Short name	T700
Test name
Test status
Simulation time	5765048954 ps
CPU time	9.12 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:16 PM PDT 24
Peak memory	200076 kb
Host	smart-60aea19a-bccb-4c38-97a8-3dfead51f3da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739514452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3739514452
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_noise_filter.611008409
Short name	T1037
Test name
Test status
Simulation time	51406191505 ps
CPU time	86.23 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:09:32 PM PDT 24
Peak memory	199680 kb
Host	smart-b051703f-ecf4-429a-8a37-b5f38a24f38c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611008409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.611008409
Directory	/workspace/32.uart_noise_filter/latest

Test location	/workspace/coverage/default/32.uart_perf.3686814596
Short name	T478
Test name
Test status
Simulation time	12649482812 ps
CPU time	120.26 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:10:17 PM PDT 24
Peak memory	200152 kb
Host	smart-93db58d0-0c4b-435d-b896-402d23b957c3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3686814596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3686814596
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.2497289428
Short name	T1036
Test name
Test status
Simulation time	6165796759 ps
CPU time	47.6 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:47 PM PDT 24
Peak memory	198948 kb
Host	smart-b5edb2bf-8362-41d2-995e-67797ddcda20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2497289428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2497289428
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.2120430003
Short name	T1065
Test name
Test status
Simulation time	40349209382 ps
CPU time	61.13 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:09:03 PM PDT 24
Peak memory	199180 kb
Host	smart-409d5325-eba7-449c-b21e-00a8972d3ec2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120430003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2120430003
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.1775941416
Short name	T598
Test name
Test status
Simulation time	2872592253 ps
CPU time	5.12 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:04 PM PDT 24
Peak memory	195680 kb
Host	smart-09d2668c-d90b-4a15-a139-f586168ed2a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775941416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1775941416
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.246677421
Short name	T73
Test name
Test status
Simulation time	5542085434 ps
CPU time	9.81 seconds
Started	Mar 12 01:07:58 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	199972 kb
Host	smart-dcc8d7dd-dcbc-4055-98ba-852c0a952b11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246677421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.246677421
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_stress_all.2995514172
Short name	T911
Test name
Test status
Simulation time	475473429359 ps
CPU time	1825.05 seconds
Started	Mar 12 01:08:10 PM PDT 24
Finished	Mar 12 01:38:36 PM PDT 24
Peak memory	200128 kb
Host	smart-804150db-403e-4030-ad77-94745c291d84
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995514172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2995514172
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.1889581338
Short name	T455
Test name
Test status
Simulation time	818955986 ps
CPU time	2.86 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:10 PM PDT 24
Peak memory	198432 kb
Host	smart-31c8686a-03ad-4fe2-b358-568d6d268369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889581338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1889581338
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.1044477413
Short name	T928
Test name
Test status
Simulation time	29111429578 ps
CPU time	10.62 seconds
Started	Mar 12 01:08:11 PM PDT 24
Finished	Mar 12 01:08:22 PM PDT 24
Peak memory	195992 kb
Host	smart-61e58d35-914a-43c6-86cc-991df72e9ea4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044477413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1044477413
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.893988891
Short name	T976
Test name
Test status
Simulation time	77655714 ps
CPU time	0.55 seconds
Started	Mar 12 01:08:09 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	195524 kb
Host	smart-afdb7222-f7b0-4574-ada2-3008dd8487bb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893988891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.893988891
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.979417541
Short name	T214
Test name
Test status
Simulation time	115294891407 ps
CPU time	28.19 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:08:33 PM PDT 24
Peak memory	200088 kb
Host	smart-cb5de2c6-e240-4115-9515-bf951ebbc5f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979417541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.979417541
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.1745433633
Short name	T798
Test name
Test status
Simulation time	16109810345 ps
CPU time	6.92 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:08:12 PM PDT 24
Peak memory	197796 kb
Host	smart-8660c358-a8da-4cd5-8d79-89a97e9df9b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1745433633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1745433633
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.3548078817
Short name	T182
Test name
Test status
Simulation time	127320119309 ps
CPU time	26.13 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	199980 kb
Host	smart-7f5bc716-0bee-4b2c-a917-8204736ae2b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548078817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3548078817
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.3184656249
Short name	T638
Test name
Test status
Simulation time	3717501599 ps
CPU time	3.49 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:17 PM PDT 24
Peak memory	196712 kb
Host	smart-ac6ac064-c4d2-43d8-9aae-e276d0d3ff36
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184656249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3184656249
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.3240915197
Short name	T731
Test name
Test status
Simulation time	167850461975 ps
CPU time	305.18 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:13:08 PM PDT 24
Peak memory	200052 kb
Host	smart-878098bf-b3ed-440f-bcfa-aa00958f4097
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3240915197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3240915197
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.2562866390
Short name	T511
Test name
Test status
Simulation time	3752708841 ps
CPU time	4.59 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	198968 kb
Host	smart-140cf9e3-2af4-4931-b2eb-f0cf1de74d9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562866390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2562866390
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.3662004945
Short name	T952
Test name
Test status
Simulation time	43330801721 ps
CPU time	73.58 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	199792 kb
Host	smart-2873c6cd-e572-4189-9aa7-b5856335649c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662004945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3662004945
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.887628505
Short name	T877
Test name
Test status
Simulation time	31984174605 ps
CPU time	1659.07 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:35:45 PM PDT 24
Peak memory	200092 kb
Host	smart-77d781ff-0911-4947-8a54-3a678da0d7d3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=887628505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.887628505
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.3571323508
Short name	T832
Test name
Test status
Simulation time	5647143775 ps
CPU time	24.31 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	198944 kb
Host	smart-8ad185a2-cfdf-4806-96ec-1f93cec70a9f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3571323508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3571323508
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.2249400496
Short name	T803
Test name
Test status
Simulation time	77245056899 ps
CPU time	62.24 seconds
Started	Mar 12 01:08:11 PM PDT 24
Finished	Mar 12 01:09:15 PM PDT 24
Peak memory	199384 kb
Host	smart-2402cd67-9dba-4f77-8053-39463557c165
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249400496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2249400496
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.2280308246
Short name	T1056
Test name
Test status
Simulation time	4475985726 ps
CPU time	2.38 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	195844 kb
Host	smart-3aa3d3b0-72b8-4a13-b529-387674ede2b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280308246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2280308246
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.1846101598
Short name	T3
Test name
Test status
Simulation time	5682166840 ps
CPU time	9.17 seconds
Started	Mar 12 01:08:10 PM PDT 24
Finished	Mar 12 01:08:20 PM PDT 24
Peak memory	200112 kb
Host	smart-14ef9c93-6782-4938-a7bf-e3a1cc420021
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846101598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1846101598
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all.4126496919
Short name	T854
Test name
Test status
Simulation time	249983240699 ps
CPU time	1012.99 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:24:55 PM PDT 24
Peak memory	200124 kb
Host	smart-13a2680b-75f3-4a85-8b86-a98177ea5a82
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126496919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4126496919
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.555909496
Short name	T1062
Test name
Test status
Simulation time	652650298 ps
CPU time	3.05 seconds
Started	Mar 12 01:08:04 PM PDT 24
Finished	Mar 12 01:08:07 PM PDT 24
Peak memory	198564 kb
Host	smart-ea687507-014b-42bc-84b8-dca35197d104
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555909496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.555909496
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.192823570
Short name	T433
Test name
Test status
Simulation time	88249515017 ps
CPU time	32.14 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:34 PM PDT 24
Peak memory	200192 kb
Host	smart-c44eba6b-36ea-4725-bb76-e3bba54c40c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192823570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.192823570
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.3727496610
Short name	T544
Test name
Test status
Simulation time	15460961 ps
CPU time	0.55 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	195472 kb
Host	smart-43674518-793e-4739-a808-9cef0252b6ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727496610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3727496610
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.585029931
Short name	T1064
Test name
Test status
Simulation time	33478716009 ps
CPU time	53.85 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:56 PM PDT 24
Peak memory	200180 kb
Host	smart-5d7013be-989e-4b09-8937-69e307ae6ef3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585029931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.585029931
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.2325190641
Short name	T919
Test name
Test status
Simulation time	167581835623 ps
CPU time	140.39 seconds
Started	Mar 12 01:08:08 PM PDT 24
Finished	Mar 12 01:10:29 PM PDT 24
Peak memory	200124 kb
Host	smart-22e2b46c-28aa-440b-81e6-75e63d2d8659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2325190641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2325190641
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.1826358891
Short name	T1106
Test name
Test status
Simulation time	58142401319 ps
CPU time	20.76 seconds
Started	Mar 12 01:08:08 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	200100 kb
Host	smart-c9cad1e4-8f4f-4c09-905c-89dfebe1f73f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826358891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1826358891
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_intr.3921216918
Short name	T627
Test name
Test status
Simulation time	10061054719 ps
CPU time	27.01 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:34 PM PDT 24
Peak memory	200104 kb
Host	smart-1eb1eef8-fa9e-4c3e-9c50-e8498edd8fbd
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921216918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3921216918
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.2353382810
Short name	T569
Test name
Test status
Simulation time	53947656771 ps
CPU time	119.02 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:10:04 PM PDT 24
Peak memory	199928 kb
Host	smart-a3d4b764-2e0f-419e-9110-18efc4631806
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2353382810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2353382810
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.757792171
Short name	T600
Test name
Test status
Simulation time	8750339220 ps
CPU time	14.62 seconds
Started	Mar 12 01:08:10 PM PDT 24
Finished	Mar 12 01:08:25 PM PDT 24
Peak memory	199272 kb
Host	smart-1f5d0e43-4312-4fcd-bb64-9fb1e5ddef9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=757792171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.757792171
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.2158532712
Short name	T411
Test name
Test status
Simulation time	16993904330 ps
CPU time	15.13 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:18 PM PDT 24
Peak memory	194800 kb
Host	smart-7162a3a9-0da8-485b-a400-890d3352a90c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158532712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2158532712
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.156593811
Short name	T1034
Test name
Test status
Simulation time	4607329187 ps
CPU time	9.53 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:23 PM PDT 24
Peak memory	198916 kb
Host	smart-bd269db2-9849-4c42-8a93-ae6aa6a1f48e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=156593811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.156593811
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.3751641230
Short name	T103
Test name
Test status
Simulation time	29401407397 ps
CPU time	45.11 seconds
Started	Mar 12 01:08:08 PM PDT 24
Finished	Mar 12 01:08:53 PM PDT 24
Peak memory	198716 kb
Host	smart-a261b9ff-5ff6-43ad-9f62-0cfe1d09476c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751641230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3751641230
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.4054942
Short name	T986
Test name
Test status
Simulation time	43197336502 ps
CPU time	65.82 seconds
Started	Mar 12 01:08:00 PM PDT 24
Finished	Mar 12 01:09:06 PM PDT 24
Peak memory	195604 kb
Host	smart-7f19e493-7037-458e-ae7f-40a9891b03bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4054942
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.893017769
Short name	T881
Test name
Test status
Simulation time	721334132 ps
CPU time	1.18 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	198420 kb
Host	smart-0034ad53-ec18-4fa4-8a5d-f7340e8fc0ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=893017769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.893017769
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_stress_all.429357620
Short name	T57
Test name
Test status
Simulation time	800573162334 ps
CPU time	668.14 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:19:13 PM PDT 24
Peak memory	200132 kb
Host	smart-7c349e87-93e3-4ee1-9dc3-f03215abf83b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429357620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.429357620
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.2374667282
Short name	T43
Test name
Test status
Simulation time	1076044642 ps
CPU time	2.68 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:10 PM PDT 24
Peak memory	198452 kb
Host	smart-54e9fc46-e058-4d6a-b8aa-c14ff26e5b8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374667282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2374667282
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.3165496461
Short name	T717
Test name
Test status
Simulation time	44281298372 ps
CPU time	27.47 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	200088 kb
Host	smart-a3f39673-e15d-40d1-a97a-e07f6f353a40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165496461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3165496461
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.214759886
Short name	T924
Test name
Test status
Simulation time	13282716 ps
CPU time	0.55 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:08:07 PM PDT 24
Peak memory	195544 kb
Host	smart-afef06ee-f461-4d75-a392-db1332713766
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214759886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.214759886
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.1906049983
Short name	T122
Test name
Test status
Simulation time	150860599813 ps
CPU time	35.1 seconds
Started	Mar 12 01:07:59 PM PDT 24
Finished	Mar 12 01:08:34 PM PDT 24
Peak memory	200096 kb
Host	smart-4505b9c6-3914-4134-b104-496a867821ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906049983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1906049983
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_intr.2244217472
Short name	T766
Test name
Test status
Simulation time	75579002214 ps
CPU time	34.78 seconds
Started	Mar 12 01:08:09 PM PDT 24
Finished	Mar 12 01:08:45 PM PDT 24
Peak memory	200040 kb
Host	smart-50a46561-16e2-4c78-85f0-2d1e56cee0a9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244217472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2244217472
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.1208383644
Short name	T935
Test name
Test status
Simulation time	346887222348 ps
CPU time	407.38 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:14:54 PM PDT 24
Peak memory	200144 kb
Host	smart-30fd337d-59c6-4b69-b8a0-67f870008126
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1208383644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1208383644
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.2036716564
Short name	T28
Test name
Test status
Simulation time	10722797715 ps
CPU time	10.44 seconds
Started	Mar 12 01:08:02 PM PDT 24
Finished	Mar 12 01:08:13 PM PDT 24
Peak memory	198044 kb
Host	smart-5d67a770-2d14-4fd9-a72e-4e20441820d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036716564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2036716564
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_noise_filter.3592227802
Short name	T152
Test name
Test status
Simulation time	64590225287 ps
CPU time	90.76 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:09:36 PM PDT 24
Peak memory	198412 kb
Host	smart-627fddd4-d602-4568-b134-439f7d406b16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592227802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3592227802
Directory	/workspace/35.uart_noise_filter/latest

Test location	/workspace/coverage/default/35.uart_perf.1321663358
Short name	T793
Test name
Test status
Simulation time	24610510417 ps
CPU time	150.51 seconds
Started	Mar 12 01:08:01 PM PDT 24
Finished	Mar 12 01:10:32 PM PDT 24
Peak memory	200120 kb
Host	smart-1efe216b-b364-454d-8719-82326547763e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1321663358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1321663358
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.98410777
Short name	T704
Test name
Test status
Simulation time	1690267364 ps
CPU time	9.1 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:08:14 PM PDT 24
Peak memory	198292 kb
Host	smart-ce9ea6a3-919e-4302-83c4-6870746df0d7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=98410777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.98410777
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.2787676661
Short name	T1119
Test name
Test status
Simulation time	145527387847 ps
CPU time	64.83 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:09:11 PM PDT 24
Peak memory	199996 kb
Host	smart-0b064128-c084-4b3b-9a87-db0bce533898
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2787676661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2787676661
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.1615997415
Short name	T685
Test name
Test status
Simulation time	3471368467 ps
CPU time	6.42 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:13 PM PDT 24
Peak memory	195860 kb
Host	smart-41588fd0-6444-40fd-bc85-3e06e4f83842
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615997415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1615997415
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.4090202658
Short name	T674
Test name
Test status
Simulation time	5563851277 ps
CPU time	5.58 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:08:12 PM PDT 24
Peak memory	199388 kb
Host	smart-30b67a39-c115-4fca-83a1-c44cb71ba9a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090202658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4090202658
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all.380069531
Short name	T213
Test name
Test status
Simulation time	752564248874 ps
CPU time	330.15 seconds
Started	Mar 12 01:08:09 PM PDT 24
Finished	Mar 12 01:13:40 PM PDT 24
Peak memory	200064 kb
Host	smart-e8a9926e-0e0e-4e80-bbe7-dd37ded30a73
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380069531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.380069531
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/35.uart_stress_all_with_rand_reset.771711414
Short name	T710
Test name
Test status
Simulation time	152500114476 ps
CPU time	1304.05 seconds
Started	Mar 12 01:08:05 PM PDT 24
Finished	Mar 12 01:29:50 PM PDT 24
Peak memory	216660 kb
Host	smart-c1b00742-ea51-40e4-9a90-23dcd02e32b9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771711414 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.771711414
Directory	/workspace/35.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.827361952
Short name	T615
Test name
Test status
Simulation time	6906279469 ps
CPU time	16.9 seconds
Started	Mar 12 01:08:03 PM PDT 24
Finished	Mar 12 01:08:20 PM PDT 24
Peak memory	199644 kb
Host	smart-299942e6-2d22-4507-b014-0a30cbcc9602
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827361952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.827361952
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.965504977
Short name	T651
Test name
Test status
Simulation time	25937745628 ps
CPU time	19.75 seconds
Started	Mar 12 01:08:04 PM PDT 24
Finished	Mar 12 01:08:24 PM PDT 24
Peak memory	199244 kb
Host	smart-171d7ddc-1d7e-4c1f-b350-f69572779be7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965504977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.965504977
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.930367933
Short name	T499
Test name
Test status
Simulation time	39507366 ps
CPU time	0.53 seconds
Started	Mar 12 01:08:15 PM PDT 24
Finished	Mar 12 01:08:17 PM PDT 24
Peak memory	194608 kb
Host	smart-61e95df3-39d6-41bc-a8b9-1d1c6b45806f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930367933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.930367933
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.253746729
Short name	T524
Test name
Test status
Simulation time	198590350747 ps
CPU time	325.18 seconds
Started	Mar 12 01:08:06 PM PDT 24
Finished	Mar 12 01:13:32 PM PDT 24
Peak memory	200112 kb
Host	smart-e659005e-e639-4953-aa79-88f9faea3291
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253746729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.253746729
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.2261081128
Short name	T104
Test name
Test status
Simulation time	193790622110 ps
CPU time	278.23 seconds
Started	Mar 12 01:08:10 PM PDT 24
Finished	Mar 12 01:12:49 PM PDT 24
Peak memory	200184 kb
Host	smart-0269782f-b13c-43ef-9f30-1df41505db2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261081128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2261081128
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.3962672084
Short name	T1085
Test name
Test status
Simulation time	11000227495 ps
CPU time	5.28 seconds
Started	Mar 12 01:08:08 PM PDT 24
Finished	Mar 12 01:08:15 PM PDT 24
Peak memory	199648 kb
Host	smart-47cf836d-852a-4331-85ae-832785d789c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962672084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3962672084
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_intr.1812624866
Short name	T1047
Test name
Test status
Simulation time	55518226397 ps
CPU time	118.79 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:10:15 PM PDT 24
Peak memory	200148 kb
Host	smart-1bfd38ae-2d47-40c2-a121-734bb9a244d9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812624866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1812624866
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.2329228468
Short name	T743
Test name
Test status
Simulation time	96266195311 ps
CPU time	108.35 seconds
Started	Mar 12 01:08:12 PM PDT 24
Finished	Mar 12 01:10:02 PM PDT 24
Peak memory	200120 kb
Host	smart-93a06bb5-5420-4dad-bb4b-d386fde32f3b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2329228468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2329228468
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.3599073124
Short name	T29
Test name
Test status
Simulation time	1254486910 ps
CPU time	0.78 seconds
Started	Mar 12 01:08:11 PM PDT 24
Finished	Mar 12 01:08:13 PM PDT 24
Peak memory	195668 kb
Host	smart-5fa47580-13ba-4eb0-abb3-724044985bfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599073124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3599073124
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.2628011827
Short name	T211
Test name
Test status
Simulation time	58513531034 ps
CPU time	104.6 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:10:00 PM PDT 24
Peak memory	200108 kb
Host	smart-fcab3812-6c07-452a-892c-a6232c43ede7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628011827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2628011827
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.3010224072
Short name	T423
Test name
Test status
Simulation time	16435760911 ps
CPU time	232.23 seconds
Started	Mar 12 01:08:15 PM PDT 24
Finished	Mar 12 01:12:09 PM PDT 24
Peak memory	200116 kb
Host	smart-edd9c0a5-3084-4b28-a53f-1e07e0bbf9b3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3010224072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3010224072
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.3685534959
Short name	T514
Test name
Test status
Simulation time	3231054829 ps
CPU time	12.09 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:26 PM PDT 24
Peak memory	198288 kb
Host	smart-c2b00148-a634-4baf-a22d-788db1ae68c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3685534959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3685534959
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.2253989454
Short name	T790
Test name
Test status
Simulation time	255928897836 ps
CPU time	35.64 seconds
Started	Mar 12 01:08:12 PM PDT 24
Finished	Mar 12 01:08:48 PM PDT 24
Peak memory	200144 kb
Host	smart-4040ff26-728a-4fff-8460-cc50e1c25835
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253989454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2253989454
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.1989262630
Short name	T821
Test name
Test status
Simulation time	43336122262 ps
CPU time	16.66 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	195664 kb
Host	smart-6c05672d-65a7-4546-83d8-06a3715a26fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989262630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1989262630
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.3779523230
Short name	T859
Test name
Test status
Simulation time	301385604 ps
CPU time	1.15 seconds
Started	Mar 12 01:08:07 PM PDT 24
Finished	Mar 12 01:08:08 PM PDT 24
Peak memory	198164 kb
Host	smart-8c17c79d-54fa-40e4-9052-1cb640aa7126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779523230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3779523230
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all.199211954
Short name	T750
Test name
Test status
Simulation time	356992661591 ps
CPU time	1242.8 seconds
Started	Mar 12 01:08:17 PM PDT 24
Finished	Mar 12 01:29:02 PM PDT 24
Peak memory	199912 kb
Host	smart-5991922f-37fb-475e-9ec4-7a4ad9a9d584
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199211954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.199211954
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/36.uart_stress_all_with_rand_reset.2148337867
Short name	T975
Test name
Test status
Simulation time	27004122683 ps
CPU time	164.36 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:10:59 PM PDT 24
Peak memory	216180 kb
Host	smart-6edbecd0-9ae8-4f6c-89e0-a571653145ab
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148337867 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2148337867
Directory	/workspace/36.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.2148024345
Short name	T109
Test name
Test status
Simulation time	9678686550 ps
CPU time	6.16 seconds
Started	Mar 12 01:08:18 PM PDT 24
Finished	Mar 12 01:08:25 PM PDT 24
Peak memory	200156 kb
Host	smart-99021106-f2fc-44f2-8160-dabb7870d886
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148024345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2148024345
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.3423576822
Short name	T471
Test name
Test status
Simulation time	228641415777 ps
CPU time	55.42 seconds
Started	Mar 12 01:08:11 PM PDT 24
Finished	Mar 12 01:09:08 PM PDT 24
Peak memory	200124 kb
Host	smart-7dee5969-d5da-495a-b59f-b79059687e95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423576822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3423576822
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.1722389839
Short name	T1080
Test name
Test status
Simulation time	13223026 ps
CPU time	0.55 seconds
Started	Mar 12 01:08:15 PM PDT 24
Finished	Mar 12 01:08:17 PM PDT 24
Peak memory	195548 kb
Host	smart-261b1ff0-c795-4735-b7a2-9942b07ec475
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722389839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1722389839
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.1428782971
Short name	T602
Test name
Test status
Simulation time	243372502333 ps
CPU time	34.54 seconds
Started	Mar 12 01:08:15 PM PDT 24
Finished	Mar 12 01:08:51 PM PDT 24
Peak memory	200100 kb
Host	smart-f678cf55-118b-49c2-a6ec-d48e7069e691
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428782971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1428782971
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.2905325810
Short name	T179
Test name
Test status
Simulation time	180638288254 ps
CPU time	275.13 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:12:52 PM PDT 24
Peak memory	200108 kb
Host	smart-0cf15167-0537-41c1-bcd7-92de89921aa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905325810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2905325810
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.1201376937
Short name	T333
Test name
Test status
Simulation time	117389695402 ps
CPU time	30 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:45 PM PDT 24
Peak memory	200188 kb
Host	smart-c0e0780b-4f3a-4ce6-ad53-04e0f1e915ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201376937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1201376937
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_intr.1807979943
Short name	T543
Test name
Test status
Simulation time	102224313736 ps
CPU time	38.16 seconds
Started	Mar 12 01:08:19 PM PDT 24
Finished	Mar 12 01:08:57 PM PDT 24
Peak memory	200100 kb
Host	smart-172cfd68-55b2-4adb-8026-57bd085bf2e4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807979943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1807979943
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.2764327667
Short name	T777
Test name
Test status
Simulation time	63643769705 ps
CPU time	360.59 seconds
Started	Mar 12 01:08:17 PM PDT 24
Finished	Mar 12 01:14:20 PM PDT 24
Peak memory	200092 kb
Host	smart-3b275974-2ca9-47db-9aa1-c59ef97b9246
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2764327667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2764327667
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.1176384608
Short name	T610
Test name
Test status
Simulation time	1942437225 ps
CPU time	1.65 seconds
Started	Mar 12 01:08:23 PM PDT 24
Finished	Mar 12 01:08:25 PM PDT 24
Peak memory	198432 kb
Host	smart-5e2cf387-58c9-476c-ab53-a35079bfa6b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176384608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1176384608
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.551668849
Short name	T951
Test name
Test status
Simulation time	155611733172 ps
CPU time	85.01 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:09:42 PM PDT 24
Peak memory	208528 kb
Host	smart-f3a7b47e-c4d4-4dbe-a5f0-a139d7d9884e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551668849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.551668849
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.2522457362
Short name	T819
Test name
Test status
Simulation time	6906980292 ps
CPU time	278.73 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:12:54 PM PDT 24
Peak memory	200080 kb
Host	smart-d5256f9a-e4da-426c-b3db-c3a6de2c0cac
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2522457362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2522457362
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.908306485
Short name	T472
Test name
Test status
Simulation time	1820209908 ps
CPU time	1.96 seconds
Started	Mar 12 01:08:17 PM PDT 24
Finished	Mar 12 01:08:19 PM PDT 24
Peak memory	198120 kb
Host	smart-878e39de-21d2-4f12-807e-fbb463d067b4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=908306485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.908306485
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.2743528980
Short name	T1076
Test name
Test status
Simulation time	74341351921 ps
CPU time	49.68 seconds
Started	Mar 12 01:08:17 PM PDT 24
Finished	Mar 12 01:09:07 PM PDT 24
Peak memory	199532 kb
Host	smart-379d0b84-6e9d-4a16-a0a7-ad44682b1bf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743528980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2743528980
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.2131220189
Short name	T593
Test name
Test status
Simulation time	1536399797 ps
CPU time	3.07 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:08:20 PM PDT 24
Peak memory	195460 kb
Host	smart-0010897c-90c4-469e-80ef-b296e75c9077
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131220189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2131220189
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.3847836972
Short name	T1002
Test name
Test status
Simulation time	6213897717 ps
CPU time	33.37 seconds
Started	Mar 12 01:08:17 PM PDT 24
Finished	Mar 12 01:08:52 PM PDT 24
Peak memory	198696 kb
Host	smart-c8e9060d-0442-4be8-92dd-394024bcbf3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847836972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3847836972
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_stress_all.2541592015
Short name	T787
Test name
Test status
Simulation time	290739392292 ps
CPU time	952.54 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:24:09 PM PDT 24
Peak memory	200136 kb
Host	smart-76b1246f-bb34-4bc3-a74b-46250b577c99
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541592015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2541592015
Directory	/workspace/37.uart_stress_all/latest

Test location	/workspace/coverage/default/37.uart_stress_all_with_rand_reset.1131371508
Short name	T437
Test name
Test status
Simulation time	103039960944 ps
CPU time	343.86 seconds
Started	Mar 12 01:08:19 PM PDT 24
Finished	Mar 12 01:14:03 PM PDT 24
Peak memory	226356 kb
Host	smart-1d1e6ffd-99a4-43d6-9334-6a752b7bd3d3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131371508 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1131371508
Directory	/workspace/37.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.2693828158
Short name	T857
Test name
Test status
Simulation time	874011837 ps
CPU time	2.38 seconds
Started	Mar 12 01:08:19 PM PDT 24
Finished	Mar 12 01:08:21 PM PDT 24
Peak memory	198224 kb
Host	smart-c130872d-e70a-49cf-be1e-c9c0085bb6cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693828158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2693828158
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.2815189739
Short name	T983
Test name
Test status
Simulation time	43229218247 ps
CPU time	72.59 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:09:29 PM PDT 24
Peak memory	200140 kb
Host	smart-9dc857fa-e846-461b-83c5-dc669c3aa711
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815189739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2815189739
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.2950758438
Short name	T521
Test name
Test status
Simulation time	14121095 ps
CPU time	0.56 seconds
Started	Mar 12 01:08:18 PM PDT 24
Finished	Mar 12 01:08:20 PM PDT 24
Peak memory	195512 kb
Host	smart-bca705f0-6718-48b9-93fa-7ac2aed21150
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950758438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2950758438
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.43951247
Short name	T795
Test name
Test status
Simulation time	109354057296 ps
CPU time	193.58 seconds
Started	Mar 12 01:08:17 PM PDT 24
Finished	Mar 12 01:11:33 PM PDT 24
Peak memory	200096 kb
Host	smart-b9033d18-60cc-43fa-8ac4-f5d2123259be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43951247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.43951247
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.2228415298
Short name	T605
Test name
Test status
Simulation time	31175838998 ps
CPU time	26.76 seconds
Started	Mar 12 01:08:17 PM PDT 24
Finished	Mar 12 01:08:44 PM PDT 24
Peak memory	199868 kb
Host	smart-3891ea9f-2d3c-482b-884a-1299df5c8af4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228415298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2228415298
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_intr.2097250771
Short name	T622
Test name
Test status
Simulation time	33837890212 ps
CPU time	8.21 seconds
Started	Mar 12 01:08:18 PM PDT 24
Finished	Mar 12 01:08:27 PM PDT 24
Peak memory	200092 kb
Host	smart-5f0d2428-9fbe-40d0-95e1-8e1cf3c4bf99
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097250771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2097250771
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.1591133731
Short name	T480
Test name
Test status
Simulation time	127823897466 ps
CPU time	182.82 seconds
Started	Mar 12 01:08:18 PM PDT 24
Finished	Mar 12 01:11:22 PM PDT 24
Peak memory	199896 kb
Host	smart-6223665a-5d58-4603-a057-2243e1f6bfe3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1591133731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1591133731
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_loopback.2153605233
Short name	T451
Test name
Test status
Simulation time	1426890774 ps
CPU time	1.93 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:08:19 PM PDT 24
Peak memory	195560 kb
Host	smart-f2844884-9eb7-459a-bc03-cd055b181dbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153605233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2153605233
Directory	/workspace/38.uart_loopback/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.1243081860
Short name	T46
Test name
Test status
Simulation time	9632626172 ps
CPU time	17.17 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:08:34 PM PDT 24
Peak memory	198256 kb
Host	smart-15496656-ba47-439c-8c4d-f4bd2332bd36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243081860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1243081860
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.2653544838
Short name	T470
Test name
Test status
Simulation time	16159568017 ps
CPU time	214.37 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:11:56 PM PDT 24
Peak memory	200192 kb
Host	smart-e3c3188a-3b3d-4de1-a35c-353eda1e01c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2653544838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2653544838
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_oversample.2254472089
Short name	T664
Test name
Test status
Simulation time	6706257018 ps
CPU time	30.77 seconds
Started	Mar 12 01:08:15 PM PDT 24
Finished	Mar 12 01:08:48 PM PDT 24
Peak memory	198372 kb
Host	smart-a8821b9a-3e1a-40ae-958a-73a97068821e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2254472089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2254472089
Directory	/workspace/38.uart_rx_oversample/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.3221493327
Short name	T353
Test name
Test status
Simulation time	215142107272 ps
CPU time	82.09 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:09:39 PM PDT 24
Peak memory	200108 kb
Host	smart-dfdf9bc6-6f24-4d74-a883-cd420fd1e622
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221493327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3221493327
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.2730313474
Short name	T515
Test name
Test status
Simulation time	39504922182 ps
CPU time	19.05 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:08:36 PM PDT 24
Peak memory	195516 kb
Host	smart-61360b9d-37c3-46d0-9590-92e9ca76f1e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730313474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2730313474
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.1046699052
Short name	T1039
Test name
Test status
Simulation time	697799393 ps
CPU time	1.89 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:17 PM PDT 24
Peak memory	197876 kb
Host	smart-3a42414d-8589-468e-88e5-842f913a71c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046699052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1046699052
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_stress_all.2847883523
Short name	T368
Test name
Test status
Simulation time	497291530900 ps
CPU time	125.05 seconds
Started	Mar 12 01:08:12 PM PDT 24
Finished	Mar 12 01:10:18 PM PDT 24
Peak memory	200064 kb
Host	smart-1de20e87-dde5-4ef8-bff6-d863ff8fe0a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847883523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2847883523
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/38.uart_stress_all_with_rand_reset.1007149511
Short name	T441
Test name
Test status
Simulation time	41423624248 ps
CPU time	409.98 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:15:05 PM PDT 24
Peak memory	216800 kb
Host	smart-51558134-adfb-497a-96eb-587ac58127d9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007149511 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1007149511
Directory	/workspace/38.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.2482696089
Short name	T649
Test name
Test status
Simulation time	7047451054 ps
CPU time	16.51 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	199384 kb
Host	smart-a4ed6907-ff2c-4961-83d9-c7331b7d8565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482696089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2482696089
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.3523037301
Short name	T49
Test name
Test status
Simulation time	31212679361 ps
CPU time	17.41 seconds
Started	Mar 12 01:08:15 PM PDT 24
Finished	Mar 12 01:08:34 PM PDT 24
Peak memory	199972 kb
Host	smart-f3b743ee-6cb8-4f8d-8eba-ff5cc5772457
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523037301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3523037301
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/default/39.uart_alert_test.1554091402
Short name	T34
Test name
Test status
Simulation time	10987263 ps
CPU time	0.58 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:08:41 PM PDT 24
Peak memory	195536 kb
Host	smart-cfc5a170-dad3-4d75-88fe-4fb5b377fd21
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554091402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1554091402
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.984519829
Short name	T402
Test name
Test status
Simulation time	79955666877 ps
CPU time	32.54 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:08:50 PM PDT 24
Peak memory	199616 kb
Host	smart-cf8b6212-de43-4aa5-a1e4-df8cb111ae99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984519829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.984519829
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.1448213181
Short name	T344
Test name
Test status
Simulation time	176773518767 ps
CPU time	71.14 seconds
Started	Mar 12 01:08:14 PM PDT 24
Finished	Mar 12 01:09:28 PM PDT 24
Peak memory	200168 kb
Host	smart-48e0a454-2efe-4de6-be83-d53fbf6bb045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448213181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1448213181
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.378912071
Short name	T709
Test name
Test status
Simulation time	134533908999 ps
CPU time	103.81 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:10:01 PM PDT 24
Peak memory	199796 kb
Host	smart-207f34a6-8e4e-4f12-a5aa-10d1c6cdc3bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378912071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.378912071
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.2403400752
Short name	T653
Test name
Test status
Simulation time	57309490989 ps
CPU time	15.5 seconds
Started	Mar 12 01:08:34 PM PDT 24
Finished	Mar 12 01:08:49 PM PDT 24
Peak memory	200124 kb
Host	smart-7703f3e6-d24c-4eb3-9ae4-4d7570a5cc7c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403400752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2403400752
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.1335245017
Short name	T547
Test name
Test status
Simulation time	126063622527 ps
CPU time	205.04 seconds
Started	Mar 12 01:08:27 PM PDT 24
Finished	Mar 12 01:11:53 PM PDT 24
Peak memory	200144 kb
Host	smart-54d99f16-c395-4317-892f-d76727adef17
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1335245017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1335245017
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/39.uart_loopback.1887135984
Short name	T4
Test name
Test status
Simulation time	2047595686 ps
CPU time	1.22 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:08:27 PM PDT 24
Peak memory	196916 kb
Host	smart-8be47228-6614-43c4-b6ed-59aacf8a3f34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887135984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1887135984
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.840564735
Short name	T105
Test name
Test status
Simulation time	131574532623 ps
CPU time	53.54 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	208468 kb
Host	smart-e9d6156a-7b9f-434a-990b-ec17313322f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840564735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.840564735
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.3059329172
Short name	T1115
Test name
Test status
Simulation time	26066265103 ps
CPU time	193.46 seconds
Started	Mar 12 01:08:24 PM PDT 24
Finished	Mar 12 01:11:38 PM PDT 24
Peak memory	200128 kb
Host	smart-16ec6043-e586-43eb-a5b8-d3153e8dec90
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3059329172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3059329172
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_oversample.1384343629
Short name	T565
Test name
Test status
Simulation time	3278187250 ps
CPU time	17.96 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:08:44 PM PDT 24
Peak memory	198640 kb
Host	smart-62dbbd27-33df-4a84-bd59-361af42a0028
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1384343629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1384343629
Directory	/workspace/39.uart_rx_oversample/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.717820778
Short name	T965
Test name
Test status
Simulation time	192800463178 ps
CPU time	76.98 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:09:42 PM PDT 24
Peak memory	200064 kb
Host	smart-32c31969-fbab-4737-90de-cd2f1d31fa6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717820778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.717820778
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.3429968128
Short name	T70
Test name
Test status
Simulation time	32182894182 ps
CPU time	49.42 seconds
Started	Mar 12 01:08:27 PM PDT 24
Finished	Mar 12 01:09:16 PM PDT 24
Peak memory	195568 kb
Host	smart-08ed71bb-5713-40ca-ad57-8c2309708578
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429968128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3429968128
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.2770796403
Short name	T943
Test name
Test status
Simulation time	452720940 ps
CPU time	2.61 seconds
Started	Mar 12 01:08:16 PM PDT 24
Finished	Mar 12 01:08:20 PM PDT 24
Peak memory	198932 kb
Host	smart-325c98b1-c076-495d-a9a0-f5e67046da61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770796403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2770796403
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all.3779747393
Short name	T663
Test name
Test status
Simulation time	97250846985 ps
CPU time	232.23 seconds
Started	Mar 12 01:08:28 PM PDT 24
Finished	Mar 12 01:12:20 PM PDT 24
Peak memory	200072 kb
Host	smart-68356dc8-deba-403d-87f3-813da1f8d7da
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779747393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3779747393
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/39.uart_stress_all_with_rand_reset.3282585130
Short name	T827
Test name
Test status
Simulation time	218188847154 ps
CPU time	370.32 seconds
Started	Mar 12 01:08:33 PM PDT 24
Finished	Mar 12 01:14:44 PM PDT 24
Peak memory	216620 kb
Host	smart-769a2325-0a63-4e7c-8777-fc50e2a2c24b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282585130 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3282585130
Directory	/workspace/39.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.1490566218
Short name	T1117
Test name
Test status
Simulation time	1096884469 ps
CPU time	2.22 seconds
Started	Mar 12 01:08:27 PM PDT 24
Finished	Mar 12 01:08:29 PM PDT 24
Peak memory	197932 kb
Host	smart-3d3a6cf4-8422-4be1-9c87-7a2a89567a0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490566218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1490566218
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.556656393
Short name	T582
Test name
Test status
Simulation time	135484040209 ps
CPU time	48.79 seconds
Started	Mar 12 01:08:13 PM PDT 24
Finished	Mar 12 01:09:04 PM PDT 24
Peak memory	200112 kb
Host	smart-04234e2c-89dc-407c-8e62-bc0f35f29fb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556656393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.556656393
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.2044914572
Short name	T776
Test name
Test status
Simulation time	57823793 ps
CPU time	0.56 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	195544 kb
Host	smart-d17e810f-1dd0-40b5-b6de-4b91a8dc6f93
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044914572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2044914572
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.245187202
Short name	T735
Test name
Test status
Simulation time	112076428956 ps
CPU time	51.11 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:55 PM PDT 24
Peak memory	200036 kb
Host	smart-e18629dd-6650-4722-8da1-bef69b0b5098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245187202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.245187202
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_intr.2210290582
Short name	T444
Test name
Test status
Simulation time	210487909553 ps
CPU time	324.29 seconds
Started	Mar 12 01:06:56 PM PDT 24
Finished	Mar 12 01:12:21 PM PDT 24
Peak memory	198008 kb
Host	smart-99882345-8385-41d1-a4e0-469fb6c40621
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210290582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2210290582
Directory	/workspace/4.uart_intr/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.3396489279
Short name	T291
Test name
Test status
Simulation time	172256130822 ps
CPU time	1002.88 seconds
Started	Mar 12 01:06:51 PM PDT 24
Finished	Mar 12 01:23:34 PM PDT 24
Peak memory	200092 kb
Host	smart-512772b5-9fa5-4fe3-a135-5479c677487d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3396489279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3396489279
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.3725391965
Short name	T586
Test name
Test status
Simulation time	10768637871 ps
CPU time	11.11 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	199868 kb
Host	smart-efb035db-9f55-42de-b5bf-4bd6447681ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725391965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3725391965
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.3823104240
Short name	T640
Test name
Test status
Simulation time	142602171370 ps
CPU time	71.3 seconds
Started	Mar 12 01:06:52 PM PDT 24
Finished	Mar 12 01:08:05 PM PDT 24
Peak memory	199404 kb
Host	smart-f522173b-6a7e-4f18-92b2-41ac0c3c2468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823104240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3823104240
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.2731692958
Short name	T755
Test name
Test status
Simulation time	30254732653 ps
CPU time	402.01 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:13:53 PM PDT 24
Peak memory	200172 kb
Host	smart-b2c0a29c-4dae-4b1d-95e9-87be761b56d1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2731692958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2731692958
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_oversample.3836643773
Short name	T523
Test name
Test status
Simulation time	4593671716 ps
CPU time	16.13 seconds
Started	Mar 12 01:07:02 PM PDT 24
Finished	Mar 12 01:07:19 PM PDT 24
Peak memory	198356 kb
Host	smart-6ad9f873-ef11-4b90-802d-300a747e4d92
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3836643773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3836643773
Directory	/workspace/4.uart_rx_oversample/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.1372275621
Short name	T592
Test name
Test status
Simulation time	29184590481 ps
CPU time	47.77 seconds
Started	Mar 12 01:06:58 PM PDT 24
Finished	Mar 12 01:07:46 PM PDT 24
Peak memory	199224 kb
Host	smart-8a853eda-c289-499f-9e6b-63946ce9a9df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372275621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1372275621
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.2482574091
Short name	T876
Test name
Test status
Simulation time	3722632961 ps
CPU time	6.18 seconds
Started	Mar 12 01:06:56 PM PDT 24
Finished	Mar 12 01:07:03 PM PDT 24
Peak memory	195980 kb
Host	smart-de104ba9-b7c9-474c-a60c-bb64a4f25a88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482574091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2482574091
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.2051302805
Short name	T37
Test name
Test status
Simulation time	112586508 ps
CPU time	0.83 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	217488 kb
Host	smart-c36c95be-ff80-4842-b51c-71400769e2dd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051302805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2051302805
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/4.uart_smoke.1536764169
Short name	T1030
Test name
Test status
Simulation time	950459873 ps
CPU time	1.88 seconds
Started	Mar 12 01:06:58 PM PDT 24
Finished	Mar 12 01:07:00 PM PDT 24
Peak memory	199908 kb
Host	smart-16282895-a623-484f-9890-09fcc589db2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536764169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1536764169
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.2353897662
Short name	T1028
Test name
Test status
Simulation time	216013796024 ps
CPU time	371.48 seconds
Started	Mar 12 01:06:47 PM PDT 24
Finished	Mar 12 01:13:00 PM PDT 24
Peak memory	200180 kb
Host	smart-062d6860-2d4a-4bad-9313-2274e56e2b2b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353897662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2353897662
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.3625380247
Short name	T552
Test name
Test status
Simulation time	740566634 ps
CPU time	2.66 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	198280 kb
Host	smart-845d335a-cac1-4e87-a75d-eb34fb462504
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625380247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3625380247
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.3213559378
Short name	T904
Test name
Test status
Simulation time	72186520094 ps
CPU time	61.42 seconds
Started	Mar 12 01:06:51 PM PDT 24
Finished	Mar 12 01:07:52 PM PDT 24
Peak memory	200120 kb
Host	smart-81489a27-d359-4782-bf46-b207acb0c8b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213559378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3213559378
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.3348199285
Short name	T1025
Test name
Test status
Simulation time	35826735 ps
CPU time	0.54 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:08:27 PM PDT 24
Peak memory	194420 kb
Host	smart-94bf8c35-77b8-4f54-9849-ce75ceb53330
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348199285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3348199285
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.1585429606
Short name	T286
Test name
Test status
Simulation time	87166274491 ps
CPU time	70.9 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:09:37 PM PDT 24
Peak memory	200120 kb
Host	smart-9affbf17-41ce-417f-8155-b06dda050046
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585429606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1585429606
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.4287398125
Short name	T768
Test name
Test status
Simulation time	63915856350 ps
CPU time	145.11 seconds
Started	Mar 12 01:08:32 PM PDT 24
Finished	Mar 12 01:10:57 PM PDT 24
Peak memory	200132 kb
Host	smart-1a28b66a-9329-42e4-be5f-7c7a6ff37e49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287398125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4287398125
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.3531791470
Short name	T269
Test name
Test status
Simulation time	391118326215 ps
CPU time	37.56 seconds
Started	Mar 12 01:08:30 PM PDT 24
Finished	Mar 12 01:09:08 PM PDT 24
Peak memory	200136 kb
Host	smart-4afeda65-422f-4107-b9d5-235ccbfba422
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531791470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3531791470
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.1497050915
Short name	T995
Test name
Test status
Simulation time	626295179747 ps
CPU time	244.07 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:12:42 PM PDT 24
Peak memory	199556 kb
Host	smart-39ad96c3-ceea-4cad-8203-acb13afc8b2e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497050915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1497050915
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.1181393205
Short name	T882
Test name
Test status
Simulation time	70528288795 ps
CPU time	96.05 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:10:02 PM PDT 24
Peak memory	200100 kb
Host	smart-26f78791-13a9-480c-954b-a8c526d288dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1181393205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1181393205
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.1780356059
Short name	T1054
Test name
Test status
Simulation time	2977731414 ps
CPU time	2.24 seconds
Started	Mar 12 01:08:39 PM PDT 24
Finished	Mar 12 01:08:44 PM PDT 24
Peak memory	197024 kb
Host	smart-ab208734-7d17-433a-aa7c-c626656399bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780356059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1780356059
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.1332877383
Short name	T725
Test name
Test status
Simulation time	25926500077 ps
CPU time	15.61 seconds
Started	Mar 12 01:08:33 PM PDT 24
Finished	Mar 12 01:08:49 PM PDT 24
Peak memory	199100 kb
Host	smart-40ada3fd-092e-457b-b1ed-0c11b800ed5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332877383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1332877383
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.2976066969
Short name	T469
Test name
Test status
Simulation time	21613764912 ps
CPU time	283.27 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:13:09 PM PDT 24
Peak memory	200060 kb
Host	smart-06198820-911e-463d-8b77-29294a276abd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2976066969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2976066969
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.3805420042
Short name	T782
Test name
Test status
Simulation time	2858081566 ps
CPU time	9.81 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:08:35 PM PDT 24
Peak memory	198636 kb
Host	smart-eb2d4267-8f3a-4607-aa16-40a8b41918dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3805420042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3805420042
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.2895455593
Short name	T375
Test name
Test status
Simulation time	536874243850 ps
CPU time	56.11 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:09:22 PM PDT 24
Peak memory	200124 kb
Host	smart-9dca2073-058a-480a-bf6d-2915fd5253cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895455593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2895455593
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.852294243
Short name	T632
Test name
Test status
Simulation time	5288868450 ps
CPU time	1.65 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:08:26 PM PDT 24
Peak memory	195964 kb
Host	smart-e0d4300d-2830-4c51-bb20-e570fdc42764
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852294243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.852294243
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.903672107
Short name	T485
Test name
Test status
Simulation time	652755583 ps
CPU time	2.05 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:08:28 PM PDT 24
Peak memory	199252 kb
Host	smart-3ab3ae08-d759-49c5-a102-8fd299ee46b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903672107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.903672107
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.1625109095
Short name	T824
Test name
Test status
Simulation time	1014063709143 ps
CPU time	843.31 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:22:30 PM PDT 24
Peak memory	200128 kb
Host	smart-2a82a8d8-04c5-4f0b-976d-e571bd61ca96
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625109095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1625109095
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.3088352101
Short name	T590
Test name
Test status
Simulation time	7340417062 ps
CPU time	18.2 seconds
Started	Mar 12 01:08:32 PM PDT 24
Finished	Mar 12 01:08:51 PM PDT 24
Peak memory	199136 kb
Host	smart-0a65d7d3-260f-4931-86ed-a775f680ac72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088352101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3088352101
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.4202809259
Short name	T493
Test name
Test status
Simulation time	125782469050 ps
CPU time	251.27 seconds
Started	Mar 12 01:08:24 PM PDT 24
Finished	Mar 12 01:12:36 PM PDT 24
Peak memory	200052 kb
Host	smart-d07ed267-94b8-4c7c-b4c6-c98247cf875a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202809259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4202809259
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.2660838900
Short name	T660
Test name
Test status
Simulation time	26130961 ps
CPU time	0.58 seconds
Started	Mar 12 01:08:34 PM PDT 24
Finished	Mar 12 01:08:35 PM PDT 24
Peak memory	195484 kb
Host	smart-83d8dcad-8703-45b6-affc-f3d01a97fc37
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660838900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2660838900
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.3045041945
Short name	T422
Test name
Test status
Simulation time	124885185639 ps
CPU time	144.5 seconds
Started	Mar 12 01:08:24 PM PDT 24
Finished	Mar 12 01:10:49 PM PDT 24
Peak memory	200156 kb
Host	smart-748222e2-ee12-41aa-88f3-4727e0b4cf17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3045041945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3045041945
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.2234254332
Short name	T1053
Test name
Test status
Simulation time	252211009985 ps
CPU time	44.65 seconds
Started	Mar 12 01:08:29 PM PDT 24
Finished	Mar 12 01:09:14 PM PDT 24
Peak memory	199660 kb
Host	smart-7ef0c4b4-642b-498f-b9c9-1c3fc2e943ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234254332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2234254332
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.46449868
Short name	T931
Test name
Test status
Simulation time	38101877918 ps
CPU time	16.76 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:08:51 PM PDT 24
Peak memory	199560 kb
Host	smart-b4c15aa9-8601-4dfc-ad88-d2999e62f2aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46449868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.46449868
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/41.uart_intr.4155562601
Short name	T1088
Test name
Test status
Simulation time	20811138343 ps
CPU time	3.83 seconds
Started	Mar 12 01:08:26 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	197064 kb
Host	smart-e3bcd9ef-a168-410c-9250-0f7173513b33
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155562601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4155562601
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_long_xfer_wo_dly.2494117243
Short name	T115
Test name
Test status
Simulation time	70730728544 ps
CPU time	391.75 seconds
Started	Mar 12 01:08:23 PM PDT 24
Finished	Mar 12 01:14:55 PM PDT 24
Peak memory	200100 kb
Host	smart-cc9490d7-8277-48ba-a64c-b3d3a5deaa0f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2494117243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2494117243
Directory	/workspace/41.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/41.uart_loopback.2819755984
Short name	T714
Test name
Test status
Simulation time	1175867203 ps
CPU time	1.09 seconds
Started	Mar 12 01:08:31 PM PDT 24
Finished	Mar 12 01:08:32 PM PDT 24
Peak memory	195708 kb
Host	smart-5c9461ae-c6c4-4e81-9147-c06c9f4994ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819755984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2819755984
Directory	/workspace/41.uart_loopback/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.588947479
Short name	T835
Test name
Test status
Simulation time	134762193017 ps
CPU time	79.67 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:09:45 PM PDT 24
Peak memory	208452 kb
Host	smart-7f32048b-1b3b-4d9a-8109-a312b144470e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588947479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.588947479
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.3694042638
Short name	T637
Test name
Test status
Simulation time	19213984689 ps
CPU time	1077.28 seconds
Started	Mar 12 01:08:31 PM PDT 24
Finished	Mar 12 01:26:28 PM PDT 24
Peak memory	199972 kb
Host	smart-d13d3ebb-b3f1-4173-be24-ea266b53fa7b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3694042638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3694042638
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.811129812
Short name	T843
Test name
Test status
Simulation time	6476622723 ps
CPU time	13.82 seconds
Started	Mar 12 01:08:23 PM PDT 24
Finished	Mar 12 01:08:37 PM PDT 24
Peak memory	198768 kb
Host	smart-0ca5cc94-a8d2-4129-85bf-a4fbf0a6d615
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=811129812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.811129812
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.786089412
Short name	T2
Test name
Test status
Simulation time	37943665985 ps
CPU time	27.69 seconds
Started	Mar 12 01:08:33 PM PDT 24
Finished	Mar 12 01:09:01 PM PDT 24
Peak memory	199380 kb
Host	smart-1a5c636e-0137-429f-9df9-e8b2f67b7a70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786089412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.786089412
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.1436751212
Short name	T621
Test name
Test status
Simulation time	2514705943 ps
CPU time	1.58 seconds
Started	Mar 12 01:08:34 PM PDT 24
Finished	Mar 12 01:08:36 PM PDT 24
Peak memory	195552 kb
Host	smart-33c27aa4-e1ec-4fb5-84aa-6ddf1ecce7ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436751212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1436751212
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.3531362530
Short name	T497
Test name
Test status
Simulation time	684552619 ps
CPU time	2.12 seconds
Started	Mar 12 01:08:24 PM PDT 24
Finished	Mar 12 01:08:26 PM PDT 24
Peak memory	198392 kb
Host	smart-f31f7ad4-a2ab-42a4-a870-169535c2a4df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531362530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3531362530
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.2376182070
Short name	T117
Test name
Test status
Simulation time	219853453535 ps
CPU time	782.31 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:21:38 PM PDT 24
Peak memory	200120 kb
Host	smart-e7c993dc-6d8d-4ba6-9bab-7a5665cb0a51
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376182070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2376182070
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.3423861497
Short name	T20
Test name
Test status
Simulation time	447603638 ps
CPU time	1.49 seconds
Started	Mar 12 01:08:29 PM PDT 24
Finished	Mar 12 01:08:30 PM PDT 24
Peak memory	198048 kb
Host	smart-5dff317b-649c-4fe6-84d5-583a1cffdf47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423861497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3423861497
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.3918250169
Short name	T988
Test name
Test status
Simulation time	42948149558 ps
CPU time	123.85 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:10:39 PM PDT 24
Peak memory	199968 kb
Host	smart-da7565f2-f8e6-4ef6-92f7-3e72c5297031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918250169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3918250169
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.2326307358
Short name	T890
Test name
Test status
Simulation time	13751539 ps
CPU time	0.55 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:08:45 PM PDT 24
Peak memory	195536 kb
Host	smart-dbc8a6e6-397a-4086-b197-050b532f0861
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326307358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2326307358
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.1949736628
Short name	T581
Test name
Test status
Simulation time	181057428021 ps
CPU time	286.2 seconds
Started	Mar 12 01:08:28 PM PDT 24
Finished	Mar 12 01:13:14 PM PDT 24
Peak memory	200140 kb
Host	smart-e1361d11-e8bd-4d08-a9e7-4eb7b45c888c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949736628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1949736628
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.3203510882
Short name	T1071
Test name
Test status
Simulation time	140673224906 ps
CPU time	61.88 seconds
Started	Mar 12 01:08:28 PM PDT 24
Finished	Mar 12 01:09:31 PM PDT 24
Peak memory	200112 kb
Host	smart-50efa189-8304-445e-b7ea-3a0ae14fbeda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3203510882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3203510882
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.1326333733
Short name	T177
Test name
Test status
Simulation time	110083478383 ps
CPU time	111.39 seconds
Started	Mar 12 01:08:32 PM PDT 24
Finished	Mar 12 01:10:23 PM PDT 24
Peak memory	200180 kb
Host	smart-a3e45ec3-86e6-4600-a569-772c142413bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326333733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1326333733
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_intr.1843812709
Short name	T662
Test name
Test status
Simulation time	32237869755 ps
CPU time	13.85 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:08:49 PM PDT 24
Peak memory	198140 kb
Host	smart-308a4d75-6c85-42a9-9c09-8f422215986d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843812709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1843812709
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.1939119885
Short name	T1105
Test name
Test status
Simulation time	104320020172 ps
CPU time	657.24 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:19:33 PM PDT 24
Peak memory	200184 kb
Host	smart-830008d4-51d1-423b-adff-be4118af8d14
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1939119885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1939119885
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.4045937404
Short name	T30
Test name
Test status
Simulation time	8253335886 ps
CPU time	7.97 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:08:44 PM PDT 24
Peak memory	199204 kb
Host	smart-0106a0d9-20fe-4ac6-ab10-98b4624b474b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045937404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4045937404
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.614256082
Short name	T528
Test name
Test status
Simulation time	89256155053 ps
CPU time	42.68 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:09:23 PM PDT 24
Peak memory	199348 kb
Host	smart-334cf584-1d59-41f6-840b-6cdc06240ca6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614256082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.614256082
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.933680932
Short name	T468
Test name
Test status
Simulation time	6470888366 ps
CPU time	61.04 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:09:37 PM PDT 24
Peak memory	198372 kb
Host	smart-3870914c-4611-45ce-97ff-0e7c33255019
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=933680932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.933680932
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.3718892065
Short name	T533
Test name
Test status
Simulation time	77232545439 ps
CPU time	122.63 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:10:42 PM PDT 24
Peak memory	200132 kb
Host	smart-11383b1d-f1cd-421f-9b0e-b7fc8c6445ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718892065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3718892065
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.1252763178
Short name	T708
Test name
Test status
Simulation time	3025822879 ps
CPU time	5.26 seconds
Started	Mar 12 01:08:40 PM PDT 24
Finished	Mar 12 01:08:48 PM PDT 24
Peak memory	195660 kb
Host	smart-2a24f7f1-5602-48cf-8057-4a5b4f53d5e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252763178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1252763178
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.4274206182
Short name	T740
Test name
Test status
Simulation time	509585620 ps
CPU time	2.38 seconds
Started	Mar 12 01:08:33 PM PDT 24
Finished	Mar 12 01:08:35 PM PDT 24
Peak memory	199200 kb
Host	smart-6a89420e-1ac4-4889-89ed-cc4cb57aaa6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274206182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4274206182
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_stress_all.2391994523
Short name	T176
Test name
Test status
Simulation time	48867108189 ps
CPU time	82.76 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:10:02 PM PDT 24
Peak memory	200280 kb
Host	smart-8a951f1f-21f5-468b-970e-4a86f3ce5b1d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391994523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2391994523
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.3855110989
Short name	T938
Test name
Test status
Simulation time	926279586 ps
CPU time	1.95 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:08:45 PM PDT 24
Peak memory	197976 kb
Host	smart-f243135f-7bfa-43c3-89dc-d6d3a229e7ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855110989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3855110989
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.1345038567
Short name	T1050
Test name
Test status
Simulation time	14231049402 ps
CPU time	8.08 seconds
Started	Mar 12 01:08:25 PM PDT 24
Finished	Mar 12 01:08:33 PM PDT 24
Peak memory	199996 kb
Host	smart-f90d8dde-17c5-4853-b0e3-f2d48be7ad43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345038567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1345038567
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.3037374783
Short name	T507
Test name
Test status
Simulation time	12051256 ps
CPU time	0.57 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:08:44 PM PDT 24
Peak memory	195536 kb
Host	smart-7a3c412c-f738-4d90-9333-67d598be5927
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037374783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3037374783
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.3955908549
Short name	T498
Test name
Test status
Simulation time	18449384909 ps
CPU time	30.12 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:09:06 PM PDT 24
Peak memory	199580 kb
Host	smart-8837cad3-84a3-402d-9e14-1086dce67511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955908549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3955908549
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.746510063
Short name	T804
Test name
Test status
Simulation time	23256584029 ps
CPU time	41.76 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	200108 kb
Host	smart-761683e2-0d74-4bef-bb8f-3b789c61951f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746510063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.746510063
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.3513731013
Short name	T107
Test name
Test status
Simulation time	39618643965 ps
CPU time	27.62 seconds
Started	Mar 12 01:08:34 PM PDT 24
Finished	Mar 12 01:09:02 PM PDT 24
Peak memory	200120 kb
Host	smart-123d850f-f33f-460e-922f-389255780573
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513731013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3513731013
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.2517973461
Short name	T492
Test name
Test status
Simulation time	59672890678 ps
CPU time	572.08 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:18:17 PM PDT 24
Peak memory	200140 kb
Host	smart-83748b9b-a814-4c90-a11c-4c7873b88c48
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2517973461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2517973461
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_loopback.3001470654
Short name	T688
Test name
Test status
Simulation time	4183899247 ps
CPU time	8.18 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:08:51 PM PDT 24
Peak memory	198100 kb
Host	smart-ccae4d4f-2d54-445f-816f-39c87b9de173
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001470654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3001470654
Directory	/workspace/43.uart_loopback/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.2482858655
Short name	T738
Test name
Test status
Simulation time	167625164027 ps
CPU time	67.53 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:09:43 PM PDT 24
Peak memory	200344 kb
Host	smart-9ecb98a7-33d7-49ef-b967-8808411e3497
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482858655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2482858655
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.3869168428
Short name	T783
Test name
Test status
Simulation time	5767697269 ps
CPU time	284.45 seconds
Started	Mar 12 01:08:39 PM PDT 24
Finished	Mar 12 01:13:27 PM PDT 24
Peak memory	200044 kb
Host	smart-7c6fb51c-65dc-4ffc-ac74-4c232641fc59
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3869168428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3869168428
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.2371822205
Short name	T817
Test name
Test status
Simulation time	3483233060 ps
CPU time	5.46 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:08:46 PM PDT 24
Peak memory	198516 kb
Host	smart-ec1194dc-fe01-4170-a49b-83989fc93991
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2371822205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2371822205
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.3014772878
Short name	T384
Test name
Test status
Simulation time	52124558957 ps
CPU time	19 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:08:58 PM PDT 24
Peak memory	199092 kb
Host	smart-f95a757b-21ce-42fc-9acf-5306e2c1d709
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014772878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3014772878
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.1523159201
Short name	T5
Test name
Test status
Simulation time	3346706733 ps
CPU time	3.01 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:08:47 PM PDT 24
Peak memory	195576 kb
Host	smart-5148222c-c93a-45eb-b431-9afda0b27626
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523159201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1523159201
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.2138601832
Short name	T667
Test name
Test status
Simulation time	6277473914 ps
CPU time	12.68 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:08:53 PM PDT 24
Peak memory	199024 kb
Host	smart-e6b523c8-ab8a-4755-9b0f-b4543103ceba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138601832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2138601832
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_stress_all.3951371262
Short name	T120
Test name
Test status
Simulation time	171800437414 ps
CPU time	249.06 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:12:48 PM PDT 24
Peak memory	208468 kb
Host	smart-65b19678-ae0a-4bc3-bdbc-de4cfdb8e574
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951371262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3951371262
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_stress_all_with_rand_reset.3778594444
Short name	T233
Test name
Test status
Simulation time	27204188497 ps
CPU time	706.73 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:20:24 PM PDT 24
Peak memory	215880 kb
Host	smart-25f6bcba-f0a7-4a03-a402-b21df8e4af12
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778594444 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3778594444
Directory	/workspace/43.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.1978330126
Short name	T1118
Test name
Test status
Simulation time	1473102377 ps
CPU time	2.36 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:08:38 PM PDT 24
Peak memory	198728 kb
Host	smart-80f2321e-844d-449a-ba13-64a6ba597ffc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978330126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1978330126
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/43.uart_tx_rx.52215689
Short name	T723
Test name
Test status
Simulation time	80284458604 ps
CPU time	146.92 seconds
Started	Mar 12 01:08:39 PM PDT 24
Finished	Mar 12 01:11:10 PM PDT 24
Peak memory	200076 kb
Host	smart-109b401b-62bd-4f37-a54a-18f92d9991cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52215689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.52215689
Directory	/workspace/43.uart_tx_rx/latest

Test location	/workspace/coverage/default/44.uart_alert_test.552975344
Short name	T642
Test name
Test status
Simulation time	42165616 ps
CPU time	0.53 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:08:39 PM PDT 24
Peak memory	195544 kb
Host	smart-35f2c5e9-3fff-4cc8-819e-b0793d296f0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552975344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.552975344
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.4044287838
Short name	T271
Test name
Test status
Simulation time	23975761212 ps
CPU time	9.71 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:08:52 PM PDT 24
Peak memory	199908 kb
Host	smart-f621ae4b-ec8b-4e79-9731-214af142f182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044287838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4044287838
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.508263568
Short name	T619
Test name
Test status
Simulation time	78656517938 ps
CPU time	29.93 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:09:08 PM PDT 24
Peak memory	199980 kb
Host	smart-3f6a83b0-daa5-45af-9ec6-eb88e5b41972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508263568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.508263568
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.706564285
Short name	T716
Test name
Test status
Simulation time	31868364784 ps
CPU time	14.22 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:08:50 PM PDT 24
Peak memory	200100 kb
Host	smart-c44f5b37-f897-437b-91a5-a7b299a48661
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706564285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.706564285
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.4227130700
Short name	T447
Test name
Test status
Simulation time	297146838506 ps
CPU time	128.47 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:10:53 PM PDT 24
Peak memory	199980 kb
Host	smart-ee409157-a910-44cb-bdcc-037899732b31
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227130700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4227130700
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.1432840786
Short name	T454
Test name
Test status
Simulation time	105604313312 ps
CPU time	308.94 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:13:44 PM PDT 24
Peak memory	200156 kb
Host	smart-14db5531-810b-4c63-bf40-055544e4e64d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1432840786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1432840786
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_loopback.4259259820
Short name	T450
Test name
Test status
Simulation time	2738525356 ps
CPU time	6.32 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:08:44 PM PDT 24
Peak memory	198472 kb
Host	smart-71b8cff8-4a5e-4b74-907d-be8c6d0db113
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259259820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.4259259820
Directory	/workspace/44.uart_loopback/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.3196126753
Short name	T996
Test name
Test status
Simulation time	16010106240 ps
CPU time	42.69 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:09:25 PM PDT 24
Peak memory	198404 kb
Host	smart-27357540-c1d9-460c-815b-8748a8d9235c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196126753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3196126753
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.3170323643
Short name	T52
Test name
Test status
Simulation time	9859529901 ps
CPU time	289.32 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:13:30 PM PDT 24
Peak memory	199684 kb
Host	smart-0942f7de-dda3-4445-8dae-0406114846ae
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3170323643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3170323643
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.864210557
Short name	T562
Test name
Test status
Simulation time	4094432606 ps
CPU time	34.87 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	198512 kb
Host	smart-42a10336-e971-45d1-b177-55daa7f81fb6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=864210557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.864210557
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.1996392683
Short name	T1016
Test name
Test status
Simulation time	36465785087 ps
CPU time	63.06 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:09:39 PM PDT 24
Peak memory	200032 kb
Host	smart-22a3114e-a3c9-4658-a514-c7be7bc4ba74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996392683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1996392683
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.3002539979
Short name	T476
Test name
Test status
Simulation time	42735384590 ps
CPU time	18.78 seconds
Started	Mar 12 01:08:39 PM PDT 24
Finished	Mar 12 01:09:01 PM PDT 24
Peak memory	195944 kb
Host	smart-64947023-3c13-4e0c-a756-5c1209124492
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002539979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3002539979
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.2527695306
Short name	T410
Test name
Test status
Simulation time	5536933136 ps
CPU time	8.52 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:08:44 PM PDT 24
Peak memory	199420 kb
Host	smart-b20f0756-359e-4c4b-acd9-7e80769dd6e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527695306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2527695306
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_stress_all_with_rand_reset.2986600501
Short name	T112
Test name
Test status
Simulation time	11218192137 ps
CPU time	94.15 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:10:13 PM PDT 24
Peak memory	215804 kb
Host	smart-ce1bc0ab-e055-4593-b318-55b482f4f474
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986600501 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2986600501
Directory	/workspace/44.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.1834771456
Short name	T797
Test name
Test status
Simulation time	6982909407 ps
CPU time	26.47 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:09:07 PM PDT 24
Peak memory	199820 kb
Host	smart-42b7b9d2-2c86-4bd2-bb3c-0322738b4325
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834771456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1834771456
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.432889884
Short name	T56
Test name
Test status
Simulation time	29815848908 ps
CPU time	51.62 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:09:31 PM PDT 24
Peak memory	200032 kb
Host	smart-b9bae75f-2a65-4abf-9686-5b9387ead9a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432889884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.432889884
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.3198530517
Short name	T871
Test name
Test status
Simulation time	12759608 ps
CPU time	0.56 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:08:51 PM PDT 24
Peak memory	195540 kb
Host	smart-89b6d839-9390-4b17-8761-21d1d30cbd95
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198530517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3198530517
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.2614981790
Short name	T564
Test name
Test status
Simulation time	167360122228 ps
CPU time	259.48 seconds
Started	Mar 12 01:08:35 PM PDT 24
Finished	Mar 12 01:12:55 PM PDT 24
Peak memory	200048 kb
Host	smart-71eca65d-06a0-4fb6-8906-1df876e4f8c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614981790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2614981790
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.2387771620
Short name	T829
Test name
Test status
Simulation time	72692089331 ps
CPU time	47.37 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:09:28 PM PDT 24
Peak memory	199580 kb
Host	smart-18ca45ee-ba81-4552-8761-1aece9dab09e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387771620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2387771620
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.1954611737
Short name	T171
Test name
Test status
Simulation time	29052074139 ps
CPU time	14.2 seconds
Started	Mar 12 01:08:39 PM PDT 24
Finished	Mar 12 01:08:55 PM PDT 24
Peak memory	198096 kb
Host	smart-101d6221-5859-4063-97ad-9580dd572f91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954611737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1954611737
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/45.uart_intr.2789094269
Short name	T672
Test name
Test status
Simulation time	48371245068 ps
CPU time	81.82 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:10:06 PM PDT 24
Peak memory	199300 kb
Host	smart-41eb9b92-87e6-4568-8b89-bd74f454f4a4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789094269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2789094269
Directory	/workspace/45.uart_intr/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.2280181664
Short name	T496
Test name
Test status
Simulation time	181494193045 ps
CPU time	171.4 seconds
Started	Mar 12 01:08:52 PM PDT 24
Finished	Mar 12 01:11:44 PM PDT 24
Peak memory	200156 kb
Host	smart-5d70242d-6ec7-441e-badd-467064bb6d04
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2280181664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2280181664
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.131722895
Short name	T1044
Test name
Test status
Simulation time	12039770332 ps
CPU time	30.97 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:09:09 PM PDT 24
Peak memory	199740 kb
Host	smart-4ecb723c-92a5-4fba-b116-2737d7e3c913
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131722895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.131722895
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.2114755453
Short name	T428
Test name
Test status
Simulation time	44631834555 ps
CPU time	19.41 seconds
Started	Mar 12 01:08:34 PM PDT 24
Finished	Mar 12 01:08:54 PM PDT 24
Peak memory	197452 kb
Host	smart-cefb91c7-8758-4b87-840b-8f39507af7c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114755453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2114755453
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.1897767797
Short name	T578
Test name
Test status
Simulation time	5097019243 ps
CPU time	254.74 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:12:59 PM PDT 24
Peak memory	200000 kb
Host	smart-2720972e-e9b9-48cc-a004-c7f3c2c4215a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1897767797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1897767797
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_oversample.2063142637
Short name	T646
Test name
Test status
Simulation time	5270358965 ps
CPU time	11.47 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:08:55 PM PDT 24
Peak memory	198720 kb
Host	smart-c2bdde69-7987-4408-9adb-d89ca94bebd0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2063142637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2063142637
Directory	/workspace/45.uart_rx_oversample/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.3248824354
Short name	T273
Test name
Test status
Simulation time	43087354185 ps
CPU time	40.51 seconds
Started	Mar 12 01:08:37 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	199936 kb
Host	smart-257a299a-ad87-4fd7-ba84-a13625ea9a95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248824354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3248824354
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.1735852915
Short name	T697
Test name
Test status
Simulation time	3710216740 ps
CPU time	2.08 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:08:43 PM PDT 24
Peak memory	195984 kb
Host	smart-b4335b0e-7b29-4ff9-8958-d6eec86d096b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735852915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1735852915
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.3238120897
Short name	T977
Test name
Test status
Simulation time	679735179 ps
CPU time	1.57 seconds
Started	Mar 12 01:08:41 PM PDT 24
Finished	Mar 12 01:08:46 PM PDT 24
Peak memory	198232 kb
Host	smart-e1ed053e-8af6-4c75-825c-4eae9632589d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238120897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3238120897
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_stress_all.2354377951
Short name	T989
Test name
Test status
Simulation time	196023396943 ps
CPU time	328 seconds
Started	Mar 12 01:09:00 PM PDT 24
Finished	Mar 12 01:14:28 PM PDT 24
Peak memory	200060 kb
Host	smart-1e346367-4174-406c-aa55-8d72d3d2459c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354377951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2354377951
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.3825604703
Short name	T401
Test name
Test status
Simulation time	1578253177 ps
CPU time	2.43 seconds
Started	Mar 12 01:08:36 PM PDT 24
Finished	Mar 12 01:08:38 PM PDT 24
Peak memory	198012 kb
Host	smart-b7322e25-669c-4750-8ff2-0f707ba058fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825604703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3825604703
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.2679728569
Short name	T916
Test name
Test status
Simulation time	112880997451 ps
CPU time	55.61 seconds
Started	Mar 12 01:08:38 PM PDT 24
Finished	Mar 12 01:09:36 PM PDT 24
Peak memory	199920 kb
Host	smart-1ad84293-979b-41e0-8394-5ea26970dc0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679728569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2679728569
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.731027640
Short name	T643
Test name
Test status
Simulation time	11564119 ps
CPU time	0.55 seconds
Started	Mar 12 01:08:47 PM PDT 24
Finished	Mar 12 01:08:50 PM PDT 24
Peak memory	194488 kb
Host	smart-cf271d6e-65f2-436b-8325-cf62b6028302
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731027640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.731027640
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.165141480
Short name	T400
Test name
Test status
Simulation time	161752844926 ps
CPU time	124.47 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:10:56 PM PDT 24
Peak memory	200032 kb
Host	smart-c01c0963-6558-4f63-bed9-bec853b6c8e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165141480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.165141480
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.1640935985
Short name	T553
Test name
Test status
Simulation time	175506961129 ps
CPU time	41.91 seconds
Started	Mar 12 01:08:51 PM PDT 24
Finished	Mar 12 01:09:33 PM PDT 24
Peak memory	199992 kb
Host	smart-fae277e1-5418-455d-9528-66828eb9218c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640935985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1640935985
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_intr.1863817693
Short name	T998
Test name
Test status
Simulation time	80584353313 ps
CPU time	63.93 seconds
Started	Mar 12 01:08:48 PM PDT 24
Finished	Mar 12 01:09:54 PM PDT 24
Peak memory	199140 kb
Host	smart-78823109-d340-4f93-b5ae-dcaebc350c91
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863817693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1863817693
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.3211550278
Short name	T585
Test name
Test status
Simulation time	121671613467 ps
CPU time	138.72 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:11:09 PM PDT 24
Peak memory	200036 kb
Host	smart-be6f552d-aa42-4ed7-8e5b-831ce91433b9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3211550278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3211550278
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.2143359169
Short name	T680
Test name
Test status
Simulation time	9761714320 ps
CPU time	3.88 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:08:54 PM PDT 24
Peak memory	200120 kb
Host	smart-cc94c476-1662-40c0-9fb9-15355da8911f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143359169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2143359169
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.777703329
Short name	T1068
Test name
Test status
Simulation time	138053439245 ps
CPU time	60.22 seconds
Started	Mar 12 01:09:00 PM PDT 24
Finished	Mar 12 01:10:00 PM PDT 24
Peak memory	199352 kb
Host	smart-dfa2b726-314c-44df-ab2c-cbaf6a06b3b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777703329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.777703329
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.2806243240
Short name	T867
Test name
Test status
Simulation time	22275726839 ps
CPU time	1246.75 seconds
Started	Mar 12 01:08:53 PM PDT 24
Finished	Mar 12 01:29:39 PM PDT 24
Peak memory	200020 kb
Host	smart-0edb71a2-9816-4a91-a988-e6eff5ab4c86
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2806243240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2806243240
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.2581868029
Short name	T836
Test name
Test status
Simulation time	7877495360 ps
CPU time	66.56 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:09:58 PM PDT 24
Peak memory	198248 kb
Host	smart-2d842f4b-d0e0-4999-9f21-a210881e2b49
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2581868029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2581868029
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.1152967868
Short name	T588
Test name
Test status
Simulation time	16505258075 ps
CPU time	15.87 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:09:06 PM PDT 24
Peak memory	199768 kb
Host	smart-18d096f1-84df-46ee-a07d-5e33efe46d09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152967868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1152967868
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.3421477356
Short name	T894
Test name
Test status
Simulation time	48166176857 ps
CPU time	19.85 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:09:10 PM PDT 24
Peak memory	195560 kb
Host	smart-aee98ab9-d9be-4bd9-b545-ac499ac6c386
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421477356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3421477356
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.3451843126
Short name	T608
Test name
Test status
Simulation time	430195734 ps
CPU time	3.06 seconds
Started	Mar 12 01:08:48 PM PDT 24
Finished	Mar 12 01:08:53 PM PDT 24
Peak memory	198000 kb
Host	smart-12d29241-2232-4c4b-926c-c7a56dedab71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451843126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3451843126
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.4277362866
Short name	T739
Test name
Test status
Simulation time	176355877715 ps
CPU time	359.39 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:14:50 PM PDT 24
Peak memory	200296 kb
Host	smart-71cd6da6-0c5b-44a2-9fa4-8508bcb5bf80
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277362866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4277362866
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.3797441901
Short name	T501
Test name
Test status
Simulation time	2201491544 ps
CPU time	2.23 seconds
Started	Mar 12 01:08:47 PM PDT 24
Finished	Mar 12 01:08:49 PM PDT 24
Peak memory	198412 kb
Host	smart-931776d8-4e7b-459c-9ceb-73bc04105468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797441901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3797441901
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.2053342789
Short name	T861
Test name
Test status
Simulation time	37473732134 ps
CPU time	55.55 seconds
Started	Mar 12 01:09:00 PM PDT 24
Finished	Mar 12 01:09:56 PM PDT 24
Peak memory	200024 kb
Host	smart-40460904-e887-478a-b619-1d537d326502
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053342789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2053342789
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.3980903897
Short name	T462
Test name
Test status
Simulation time	46544417 ps
CPU time	0.56 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:08:51 PM PDT 24
Peak memory	195560 kb
Host	smart-f02380dc-a81f-480d-9cd4-940f35e7eab9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980903897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3980903897
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.3923819135
Short name	T379
Test name
Test status
Simulation time	75806899088 ps
CPU time	38.93 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:09:29 PM PDT 24
Peak memory	200176 kb
Host	smart-bc5e5028-60d1-43ef-955d-2571e019f111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923819135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3923819135
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.38797166
Short name	T399
Test name
Test status
Simulation time	38805817517 ps
CPU time	56.12 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:58 PM PDT 24
Peak memory	199336 kb
Host	smart-b81183ee-374c-4d6e-9236-69f5a48daf8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38797166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.38797166
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.1167956094
Short name	T305
Test name
Test status
Simulation time	102837742801 ps
CPU time	48.44 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:09:50 PM PDT 24
Peak memory	200064 kb
Host	smart-70233194-21e1-4efc-aaf8-a24de3235ad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167956094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1167956094
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/47.uart_intr.451325944
Short name	T446
Test name
Test status
Simulation time	53456707853 ps
CPU time	33.89 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:09:24 PM PDT 24
Peak memory	200184 kb
Host	smart-124101d8-4b6c-4cb6-963c-c96883583943
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451325944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.451325944
Directory	/workspace/47.uart_intr/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.2139431190
Short name	T409
Test name
Test status
Simulation time	78472197997 ps
CPU time	416.46 seconds
Started	Mar 12 01:08:52 PM PDT 24
Finished	Mar 12 01:15:48 PM PDT 24
Peak memory	200164 kb
Host	smart-2e395cff-bb44-4c22-ae70-cb907db28c78
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2139431190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2139431190
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_loopback.3562402784
Short name	T1035
Test name
Test status
Simulation time	1851273381 ps
CPU time	3.5 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:08:54 PM PDT 24
Peak memory	196932 kb
Host	smart-ea5d5492-44b8-41d3-bede-7663972c8dff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562402784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3562402784
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.3993286651
Short name	T202
Test name
Test status
Simulation time	57255153384 ps
CPU time	46.79 seconds
Started	Mar 12 01:08:47 PM PDT 24
Finished	Mar 12 01:09:37 PM PDT 24
Peak memory	199972 kb
Host	smart-6b9adb89-bc53-4242-a7f8-46bea49c4e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993286651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3993286651
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.510908908
Short name	T51
Test name
Test status
Simulation time	7336105391 ps
CPU time	345.4 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:14:36 PM PDT 24
Peak memory	200088 kb
Host	smart-811a1cfc-c977-452d-bc1a-16069a42ca83
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=510908908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.510908908
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.14676815
Short name	T477
Test name
Test status
Simulation time	1168756378 ps
CPU time	2.63 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:08:53 PM PDT 24
Peak memory	197704 kb
Host	smart-098a59dd-b5fb-4cbc-82d1-18d1e1b753ad
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=14676815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.14676815
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.1052805881
Short name	T195
Test name
Test status
Simulation time	23360201730 ps
CPU time	35.37 seconds
Started	Mar 12 01:08:48 PM PDT 24
Finished	Mar 12 01:09:26 PM PDT 24
Peak memory	199400 kb
Host	smart-3be13b35-a840-41ec-94da-fe2b6b94d365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052805881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1052805881
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.1947605680
Short name	T644
Test name
Test status
Simulation time	615387467 ps
CPU time	1.65 seconds
Started	Mar 12 01:08:51 PM PDT 24
Finished	Mar 12 01:08:53 PM PDT 24
Peak memory	195464 kb
Host	smart-66c91ef6-2dcd-4947-88bb-fd06a11431c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947605680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1947605680
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.382291956
Short name	T778
Test name
Test status
Simulation time	459996804 ps
CPU time	2.22 seconds
Started	Mar 12 01:08:55 PM PDT 24
Finished	Mar 12 01:08:57 PM PDT 24
Peak memory	198576 kb
Host	smart-b41cb436-a0b5-44b9-ad0f-6bc6aa8c5c2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382291956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.382291956
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.757512529
Short name	T756
Test name
Test status
Simulation time	191088345393 ps
CPU time	2009.53 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:42:20 PM PDT 24
Peak memory	200116 kb
Host	smart-5a7478f6-84ca-416f-99b0-a03463855add
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757512529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.757512529
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.2079027968
Short name	T618
Test name
Test status
Simulation time	7900076823 ps
CPU time	9.83 seconds
Started	Mar 12 01:08:47 PM PDT 24
Finished	Mar 12 01:09:00 PM PDT 24
Peak memory	199472 kb
Host	smart-962017aa-fbc1-454c-81d2-a7fb69f82fb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079027968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2079027968
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.3294110765
Short name	T413
Test name
Test status
Simulation time	86523589565 ps
CPU time	86.96 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:10:18 PM PDT 24
Peak memory	200084 kb
Host	smart-fcff6418-5393-4196-8b93-17791867f168
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294110765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3294110765
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.537474829
Short name	T823
Test name
Test status
Simulation time	17922726 ps
CPU time	0.62 seconds
Started	Mar 12 01:08:52 PM PDT 24
Finished	Mar 12 01:08:53 PM PDT 24
Peak memory	194444 kb
Host	smart-c805ae36-1d1d-489a-b1a4-3dea11186884
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537474829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.537474829
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.259855138
Short name	T308
Test name
Test status
Simulation time	80918095300 ps
CPU time	134.75 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:11:05 PM PDT 24
Peak memory	200140 kb
Host	smart-109d9e2b-61f1-442f-beec-946564642e83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259855138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.259855138
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.1284558270
Short name	T999
Test name
Test status
Simulation time	65812107769 ps
CPU time	7.96 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:08:58 PM PDT 24
Peak memory	197612 kb
Host	smart-d476534f-fa2b-45cc-86f9-91d8161190c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284558270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1284558270
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.3300674790
Short name	T570
Test name
Test status
Simulation time	94056476356 ps
CPU time	41.54 seconds
Started	Mar 12 01:08:48 PM PDT 24
Finished	Mar 12 01:09:31 PM PDT 24
Peak memory	200088 kb
Host	smart-318d697d-035e-484e-bd9b-c2a461977f6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300674790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3300674790
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_intr.1113100650
Short name	T942
Test name
Test status
Simulation time	12216528136 ps
CPU time	9.35 seconds
Started	Mar 12 01:08:53 PM PDT 24
Finished	Mar 12 01:09:04 PM PDT 24
Peak memory	196828 kb
Host	smart-a5b7ea68-c6fd-4140-985c-6dbde7d7bac2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113100650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1113100650
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.892597309
Short name	T921
Test name
Test status
Simulation time	77386344957 ps
CPU time	466.77 seconds
Started	Mar 12 01:08:55 PM PDT 24
Finished	Mar 12 01:16:42 PM PDT 24
Peak memory	200184 kb
Host	smart-13e899c4-2d8b-471c-86d0-563716f5b31a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=892597309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.892597309
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.1828488681
Short name	T473
Test name
Test status
Simulation time	7208800238 ps
CPU time	8.5 seconds
Started	Mar 12 01:08:51 PM PDT 24
Finished	Mar 12 01:09:00 PM PDT 24
Peak memory	198264 kb
Host	smart-e3420b5b-315e-49f6-86d1-76205d16395b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828488681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1828488681
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.49207298
Short name	T636
Test name
Test status
Simulation time	132624814778 ps
CPU time	56.3 seconds
Started	Mar 12 01:08:46 PM PDT 24
Finished	Mar 12 01:09:43 PM PDT 24
Peak memory	199684 kb
Host	smart-9f97f3d4-4c0b-420d-804c-e1cd654a9942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49207298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.49207298
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.2374687303
Short name	T1020
Test name
Test status
Simulation time	11310870890 ps
CPU time	271.2 seconds
Started	Mar 12 01:08:50 PM PDT 24
Finished	Mar 12 01:13:22 PM PDT 24
Peak memory	199948 kb
Host	smart-513ca367-3037-4a13-8a98-5f4e5d6787a5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2374687303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2374687303
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_oversample.2697196273
Short name	T603
Test name
Test status
Simulation time	5035692607 ps
CPU time	21.82 seconds
Started	Mar 12 01:08:51 PM PDT 24
Finished	Mar 12 01:09:13 PM PDT 24
Peak memory	198308 kb
Host	smart-0af2082f-d486-488f-8a60-691a94b63624
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2697196273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2697196273
Directory	/workspace/48.uart_rx_oversample/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.3173527265
Short name	T1114
Test name
Test status
Simulation time	18972587950 ps
CPU time	19.15 seconds
Started	Mar 12 01:08:52 PM PDT 24
Finished	Mar 12 01:09:12 PM PDT 24
Peak memory	199588 kb
Host	smart-f8efeedc-c259-47f1-97a9-0c44f5dbfed8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173527265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3173527265
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.606740937
Short name	T416
Test name
Test status
Simulation time	5430206287 ps
CPU time	8.26 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:08:59 PM PDT 24
Peak memory	195896 kb
Host	smart-c00c7d41-9f76-424d-916c-4894cf939f02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606740937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.606740937
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.2894210814
Short name	T551
Test name
Test status
Simulation time	5687953990 ps
CPU time	7.32 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:09:09 PM PDT 24
Peak memory	199392 kb
Host	smart-ae9ab2b4-e2a1-49cd-8d43-4f014b864701
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894210814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2894210814
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_stress_all.423914858
Short name	T1107
Test name
Test status
Simulation time	32765944772 ps
CPU time	902.85 seconds
Started	Mar 12 01:08:52 PM PDT 24
Finished	Mar 12 01:23:55 PM PDT 24
Peak memory	200360 kb
Host	smart-7c7f27ca-8938-46ea-89ca-32f385c095b8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423914858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.423914858
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.2334687211
Short name	T549
Test name
Test status
Simulation time	989682808 ps
CPU time	2.33 seconds
Started	Mar 12 01:08:51 PM PDT 24
Finished	Mar 12 01:08:54 PM PDT 24
Peak memory	198384 kb
Host	smart-992f6342-7190-441b-bf91-36c7a91dd8ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334687211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2334687211
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.1900274560
Short name	T818
Test name
Test status
Simulation time	18784760295 ps
CPU time	32.24 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:09:23 PM PDT 24
Peak memory	200052 kb
Host	smart-4e81afd3-aac0-4b3e-9e73-1b09ba54ae61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900274560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1900274560
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.973140974
Short name	T33
Test name
Test status
Simulation time	126673729 ps
CPU time	0.58 seconds
Started	Mar 12 01:09:07 PM PDT 24
Finished	Mar 12 01:09:08 PM PDT 24
Peak memory	195508 kb
Host	smart-c01abdc4-1aca-45fb-91a1-ae31e243961b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973140974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.973140974
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.3502351661
Short name	T726
Test name
Test status
Simulation time	143618570908 ps
CPU time	206.54 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:12:29 PM PDT 24
Peak memory	200104 kb
Host	smart-5833d962-2c7c-4ac4-82c9-e70a9576170b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502351661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3502351661
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.3398490064
Short name	T886
Test name
Test status
Simulation time	39723842762 ps
CPU time	65.54 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:10:10 PM PDT 24
Peak memory	200080 kb
Host	smart-2ce412a3-e6a8-4722-86e0-d2d7bd9dadfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398490064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3398490064
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.1483816265
Short name	T186
Test name
Test status
Simulation time	12723012150 ps
CPU time	14.18 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:09:18 PM PDT 24
Peak memory	200020 kb
Host	smart-c9cef980-47bc-47f8-bd7d-fb114635b7a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483816265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1483816265
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_intr.2871610854
Short name	T567
Test name
Test status
Simulation time	47831451985 ps
CPU time	111.91 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:10:53 PM PDT 24
Peak memory	200156 kb
Host	smart-a82f6b7a-fae0-4eed-b714-ecfd8ec436ac
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871610854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2871610854
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.878772570
Short name	T866
Test name
Test status
Simulation time	95392488494 ps
CPU time	595.45 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:19:00 PM PDT 24
Peak memory	200096 kb
Host	smart-c1b00b91-5eef-4537-9f35-39b8e600a09b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=878772570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.878772570
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/49.uart_loopback.511840154
Short name	T741
Test name
Test status
Simulation time	8030942663 ps
CPU time	14.33 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:17 PM PDT 24
Peak memory	199460 kb
Host	smart-c1a24425-1198-4db2-835f-4f00b8925494
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511840154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.511840154
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.3467049288
Short name	T949
Test name
Test status
Simulation time	249210830969 ps
CPU time	200.91 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:12:25 PM PDT 24
Peak memory	200316 kb
Host	smart-8e2aeb37-d493-49f2-936a-86dc6fa4463b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467049288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3467049288
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.1309751010
Short name	T773
Test name
Test status
Simulation time	11240601322 ps
CPU time	600.71 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:19:05 PM PDT 24
Peak memory	200132 kb
Host	smart-7703a8c2-3b9b-4997-a5af-d8ab36c71904
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1309751010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1309751010
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.32723034
Short name	T900
Test name
Test status
Simulation time	2440908585 ps
CPU time	3.84 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:09:05 PM PDT 24
Peak memory	198472 kb
Host	smart-2f3ca910-a009-416c-9f8b-ad5e83f73ef6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=32723034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.32723034
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.3996864618
Short name	T110
Test name
Test status
Simulation time	48483639538 ps
CPU time	32.97 seconds
Started	Mar 12 01:09:00 PM PDT 24
Finished	Mar 12 01:09:33 PM PDT 24
Peak memory	199956 kb
Host	smart-31f3b9a0-d441-4a04-98e4-370fcbd221cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996864618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3996864618
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.1263532953
Short name	T430
Test name
Test status
Simulation time	34269923561 ps
CPU time	49.81 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:09:54 PM PDT 24
Peak memory	195560 kb
Host	smart-c594aea9-9205-4afa-ba7d-ca88e746d5b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263532953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1263532953
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.1584675511
Short name	T539
Test name
Test status
Simulation time	626020979 ps
CPU time	2.65 seconds
Started	Mar 12 01:08:49 PM PDT 24
Finished	Mar 12 01:08:53 PM PDT 24
Peak memory	197908 kb
Host	smart-27213932-11be-4c8a-a189-dc4a5fcf9bc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584675511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1584675511
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_stress_all.2564252190
Short name	T119
Test name
Test status
Simulation time	135736389380 ps
CPU time	157.19 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:11:41 PM PDT 24
Peak memory	200124 kb
Host	smart-0ce2b80b-60ba-422d-9481-27f74c6dd740
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564252190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2564252190
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.433855241
Short name	T504
Test name
Test status
Simulation time	6917310894 ps
CPU time	21.3 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:23 PM PDT 24
Peak memory	198808 kb
Host	smart-fb9576be-ffac-46dc-a0ea-978fc8e65f96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433855241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.433855241
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.3176398967
Short name	T178
Test name
Test status
Simulation time	18408157556 ps
CPU time	13.92 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:09:15 PM PDT 24
Peak memory	197520 kb
Host	smart-2e7be3c3-5ea8-49ec-9820-0754e6a5e85d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176398967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3176398967
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.407257629
Short name	T696
Test name
Test status
Simulation time	26357336 ps
CPU time	0.59 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	195552 kb
Host	smart-5bc70121-3eb8-4437-b0a5-0ccdf565d24e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407257629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.407257629
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.1901750183
Short name	T385
Test name
Test status
Simulation time	34971900268 ps
CPU time	28.9 seconds
Started	Mar 12 01:06:52 PM PDT 24
Finished	Mar 12 01:07:22 PM PDT 24
Peak memory	200180 kb
Host	smart-fe7983bb-9263-4206-a30e-da6e2a7a93ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901750183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1901750183
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.1507659221
Short name	T1049
Test name
Test status
Simulation time	116198270265 ps
CPU time	181.57 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:10:02 PM PDT 24
Peak memory	200100 kb
Host	smart-d774a857-5257-441c-af89-f0c5c1773762
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507659221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1507659221
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.806343386
Short name	T250
Test name
Test status
Simulation time	22487863813 ps
CPU time	18.46 seconds
Started	Mar 12 01:06:55 PM PDT 24
Finished	Mar 12 01:07:15 PM PDT 24
Peak memory	199660 kb
Host	smart-b78eebcb-3ac5-4b72-8888-de62e72237a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806343386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.806343386
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.2510365549
Short name	T1074
Test name
Test status
Simulation time	32475974852 ps
CPU time	11.68 seconds
Started	Mar 12 01:07:02 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	198680 kb
Host	smart-147fa82b-4e73-45ad-8e47-4a5254d73107
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510365549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2510365549
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.3419781698
Short name	T1069
Test name
Test status
Simulation time	129693989735 ps
CPU time	1081.76 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:25:14 PM PDT 24
Peak memory	200132 kb
Host	smart-8794de09-b283-48c1-95c3-6206caed93c7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3419781698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3419781698
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.1670991164
Short name	T1004
Test name
Test status
Simulation time	2444904624 ps
CPU time	3.94 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	199296 kb
Host	smart-9cc1d28f-a84b-4927-baf1-ec4fa42f2053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670991164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1670991164
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.2625276275
Short name	T424
Test name
Test status
Simulation time	25729568899 ps
CPU time	27.14 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:30 PM PDT 24
Peak memory	199752 kb
Host	smart-d99de8e1-b115-40e4-b724-959dd87ea88b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625276275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2625276275
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.483860478
Short name	T9
Test name
Test status
Simulation time	20888182433 ps
CPU time	225.58 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:10:51 PM PDT 24
Peak memory	200120 kb
Host	smart-cf1be455-933b-47b7-97d3-976c1cc37f45
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=483860478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.483860478
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.507803362
Short name	T556
Test name
Test status
Simulation time	6038369359 ps
CPU time	8.12 seconds
Started	Mar 12 01:06:57 PM PDT 24
Finished	Mar 12 01:07:05 PM PDT 24
Peak memory	198960 kb
Host	smart-c74db883-47ce-4e67-8ec1-6bd409772fc2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=507803362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.507803362
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.2265713864
Short name	T482
Test name
Test status
Simulation time	47232192809 ps
CPU time	75.27 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:08:21 PM PDT 24
Peak memory	200128 kb
Host	smart-a25fa137-98c7-4ffb-b458-f850a54a789c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265713864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2265713864
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.3839680458
Short name	T815
Test name
Test status
Simulation time	49151225476 ps
CPU time	70.51 seconds
Started	Mar 12 01:06:48 PM PDT 24
Finished	Mar 12 01:08:00 PM PDT 24
Peak memory	195600 kb
Host	smart-b953d604-8597-47a5-9e37-21140e1ee6c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839680458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3839680458
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.1555863154
Short name	T432
Test name
Test status
Simulation time	6270918786 ps
CPU time	11.22 seconds
Started	Mar 12 01:06:47 PM PDT 24
Finished	Mar 12 01:06:59 PM PDT 24
Peak memory	199488 kb
Host	smart-bef17a17-2e3a-40d5-b305-ee93f9b9f2a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555863154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1555863154
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all.2753593358
Short name	T763
Test name
Test status
Simulation time	350017014885 ps
CPU time	919.54 seconds
Started	Mar 12 01:07:02 PM PDT 24
Finished	Mar 12 01:22:22 PM PDT 24
Peak memory	200072 kb
Host	smart-b65e85a7-8223-4d38-8b8b-c4afc30d2b11
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753593358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2753593358
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/5.uart_stress_all_with_rand_reset.1443471843
Short name	T1012
Test name
Test status
Simulation time	70920155012 ps
CPU time	434.54 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:14:26 PM PDT 24
Peak memory	216708 kb
Host	smart-8bec7dc6-116a-4ad4-aba2-733da5c0e149
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443471843 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1443471843
Directory	/workspace/5.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.2721961846
Short name	T1090
Test name
Test status
Simulation time	756591937 ps
CPU time	3.14 seconds
Started	Mar 12 01:06:58 PM PDT 24
Finished	Mar 12 01:07:01 PM PDT 24
Peak memory	198560 kb
Host	smart-559f754f-fc2b-4ff4-ae1f-1b4c2f711579
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721961846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2721961846
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.1480454097
Short name	T974
Test name
Test status
Simulation time	13974610782 ps
CPU time	14.38 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	200120 kb
Host	smart-298676a1-38b5-4ec3-9a41-292a29705e14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480454097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1480454097
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.598864510
Short name	T339
Test name
Test status
Simulation time	244592911575 ps
CPU time	195.8 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:12:20 PM PDT 24
Peak memory	200116 kb
Host	smart-8b391a03-975e-4fbb-9593-cbf2f0a0225a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598864510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.598864510
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.2525550369
Short name	T135
Test name
Test status
Simulation time	27073526684 ps
CPU time	44.9 seconds
Started	Mar 12 01:09:00 PM PDT 24
Finished	Mar 12 01:09:45 PM PDT 24
Peak memory	200108 kb
Host	smart-43c39dd6-9be2-47d2-8192-8bd742eac96b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525550369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2525550369
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_stress_all_with_rand_reset.3550890747
Short name	T388
Test name
Test status
Simulation time	234960787780 ps
CPU time	302.37 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:14:04 PM PDT 24
Peak memory	210228 kb
Host	smart-e928a439-230b-4c75-9c22-87221b815ecc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550890747 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3550890747
Directory	/workspace/51.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.2332909808
Short name	T153
Test name
Test status
Simulation time	88342258794 ps
CPU time	16.78 seconds
Started	Mar 12 01:09:05 PM PDT 24
Finished	Mar 12 01:09:23 PM PDT 24
Peak memory	200048 kb
Host	smart-5b0e2a9c-ee7c-4bf7-a888-816ea76ac75a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332909808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2332909808
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/52.uart_stress_all_with_rand_reset.2855818981
Short name	T114
Test name
Test status
Simulation time	109718739528 ps
CPU time	519.32 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:17:42 PM PDT 24
Peak memory	216644 kb
Host	smart-a9d86d05-c908-437e-9f3c-e779623d656e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855818981 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2855818981
Directory	/workspace/52.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.192837712
Short name	T771
Test name
Test status
Simulation time	39462657804 ps
CPU time	14.68 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:17 PM PDT 24
Peak memory	200044 kb
Host	smart-927d8b66-12e9-44d0-ac2b-b37674c52a37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192837712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.192837712
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.3063748967
Short name	T760
Test name
Test status
Simulation time	80023483705 ps
CPU time	126.52 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:11:09 PM PDT 24
Peak memory	200108 kb
Host	smart-e9927be5-2557-4811-bde3-bad839edd046
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063748967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3063748967
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.1816634218
Short name	T264
Test name
Test status
Simulation time	22513928473 ps
CPU time	19.39 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:22 PM PDT 24
Peak memory	199692 kb
Host	smart-696a283f-0a79-4b70-b8c8-1fa9781f8037
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816634218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1816634218
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/default/55.uart_stress_all_with_rand_reset.726549415
Short name	T987
Test name
Test status
Simulation time	138952291847 ps
CPU time	394.59 seconds
Started	Mar 12 01:09:05 PM PDT 24
Finished	Mar 12 01:15:41 PM PDT 24
Peak memory	216804 kb
Host	smart-8748aed0-176b-4057-b944-61d807c9d6e2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726549415 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.726549415
Directory	/workspace/55.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.2851719211
Short name	T10
Test name
Test status
Simulation time	29128920809 ps
CPU time	14.88 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	199896 kb
Host	smart-f012d7a8-5a2e-4486-b33a-54fc69b96087
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851719211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2851719211
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.2374777051
Short name	T367
Test name
Test status
Simulation time	15670928190 ps
CPU time	8.59 seconds
Started	Mar 12 01:09:00 PM PDT 24
Finished	Mar 12 01:09:09 PM PDT 24
Peak memory	200076 kb
Host	smart-9103fe39-713c-4a69-ae33-3d905e55870d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374777051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2374777051
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.1581445597
Short name	T746
Test name
Test status
Simulation time	15130284120 ps
CPU time	23.08 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:09:24 PM PDT 24
Peak memory	200052 kb
Host	smart-418ae7ae-0a55-42f6-9995-ffb9b35fe532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581445597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1581445597
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.1398798891
Short name	T1101
Test name
Test status
Simulation time	18525642700 ps
CPU time	15.91 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:09:17 PM PDT 24
Peak memory	199772 kb
Host	smart-23f07166-4b21-42f9-9952-92214f4216ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398798891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1398798891
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.3154087752
Short name	T1097
Test name
Test status
Simulation time	43576318 ps
CPU time	0.54 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:11 PM PDT 24
Peak memory	195452 kb
Host	smart-e4584f14-f2cd-40b9-881b-344558f47788
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154087752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3154087752
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.682746577
Short name	T595
Test name
Test status
Simulation time	24776821019 ps
CPU time	8.04 seconds
Started	Mar 12 01:07:04 PM PDT 24
Finished	Mar 12 01:07:13 PM PDT 24
Peak memory	200116 kb
Host	smart-5abb33e4-626f-4e09-aee8-d85352dc9291
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682746577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.682746577
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.4143253231
Short name	T362
Test name
Test status
Simulation time	23538194655 ps
CPU time	38.33 seconds
Started	Mar 12 01:07:04 PM PDT 24
Finished	Mar 12 01:07:42 PM PDT 24
Peak memory	200108 kb
Host	smart-371c5b7c-c29c-420b-893f-8df318cd9032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143253231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4143253231
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_intr.1505348678
Short name	T1026
Test name
Test status
Simulation time	86321988430 ps
CPU time	17.29 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:28 PM PDT 24
Peak memory	200140 kb
Host	smart-0883cae6-9a13-42af-b098-2d837031dab2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505348678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1505348678
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.3635635031
Short name	T765
Test name
Test status
Simulation time	116574570274 ps
CPU time	246.64 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:11:12 PM PDT 24
Peak memory	200096 kb
Host	smart-f5a11b88-7d8d-489a-948c-c7d283a1c652
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3635635031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3635635031
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.1619644152
Short name	T548
Test name
Test status
Simulation time	2973924973 ps
CPU time	1.93 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:07 PM PDT 24
Peak memory	197832 kb
Host	smart-7f96673e-1d94-47ea-b525-28dbdc2389f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619644152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1619644152
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.67060790
Short name	T796
Test name
Test status
Simulation time	85672520729 ps
CPU time	132.75 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:09:24 PM PDT 24
Peak memory	197600 kb
Host	smart-458cb02e-6857-4d6d-8430-3cc04b8c0c0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67060790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.67060790
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.3270234691
Short name	T631
Test name
Test status
Simulation time	10260788306 ps
CPU time	422.49 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:14:14 PM PDT 24
Peak memory	200156 kb
Host	smart-b5ea252e-79b4-49a7-9695-afd6a90a8817
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3270234691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3270234691
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.3933154181
Short name	T443
Test name
Test status
Simulation time	1501348278 ps
CPU time	1.87 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:05 PM PDT 24
Peak memory	197880 kb
Host	smart-9cea9750-4f55-4fd5-ac5a-919275341dd7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3933154181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3933154181
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.645203863
Short name	T466
Test name
Test status
Simulation time	48630098567 ps
CPU time	33.56 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:46 PM PDT 24
Peak memory	199220 kb
Host	smart-8c41c46a-e866-4b7d-8207-3076cb692181
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645203863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.645203863
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.330047182
Short name	T1084
Test name
Test status
Simulation time	1773887861 ps
CPU time	3.48 seconds
Started	Mar 12 01:07:04 PM PDT 24
Finished	Mar 12 01:07:08 PM PDT 24
Peak memory	195564 kb
Host	smart-b5bdf490-59a1-4953-bd13-fa311d84aa16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330047182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.330047182
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.3071250338
Short name	T888
Test name
Test status
Simulation time	5904206133 ps
CPU time	19.09 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:28 PM PDT 24
Peak memory	198892 kb
Host	smart-6dda7d65-b7db-433c-bc0b-d2005e052280
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071250338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3071250338
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.3125154215
Short name	T540
Test name
Test status
Simulation time	71496579892 ps
CPU time	61.84 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:08:07 PM PDT 24
Peak memory	209008 kb
Host	smart-6d958796-45e3-437a-b824-5ca93f2b2d24
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125154215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3125154215
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.547372879
Short name	T772
Test name
Test status
Simulation time	532732290 ps
CPU time	1.21 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:13 PM PDT 24
Peak memory	198068 kb
Host	smart-0bb8d11a-18c4-418d-8144-9f426b768b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547372879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.547372879
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.898716084
Short name	T141
Test name
Test status
Simulation time	120532563855 ps
CPU time	46.29 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:58 PM PDT 24
Peak memory	200120 kb
Host	smart-3f88bcf0-1bcc-4a60-b981-903410fafa11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=898716084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.898716084
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.3682990198
Short name	T1006
Test name
Test status
Simulation time	17573982670 ps
CPU time	16.6 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:19 PM PDT 24
Peak memory	200100 kb
Host	smart-ef7744cb-5efd-4691-beb2-679993e9fc73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682990198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3682990198
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_stress_all_with_rand_reset.307431770
Short name	T39
Test name
Test status
Simulation time	21495675000 ps
CPU time	246.49 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:13:11 PM PDT 24
Peak memory	208660 kb
Host	smart-610497dc-8ad1-4d4d-a8da-799c37c7b056
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307431770 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.307431770
Directory	/workspace/63.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.3769099445
Short name	T1021
Test name
Test status
Simulation time	57956994123 ps
CPU time	94.78 seconds
Started	Mar 12 01:09:06 PM PDT 24
Finished	Mar 12 01:10:41 PM PDT 24
Peak memory	200148 kb
Host	smart-a24ad287-6ede-4dfd-a446-65f977959e6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769099445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3769099445
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.1715265154
Short name	T196
Test name
Test status
Simulation time	137671495756 ps
CPU time	55.25 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:57 PM PDT 24
Peak memory	199704 kb
Host	smart-81ba9f70-73a9-4f98-a050-a22d384eb789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715265154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1715265154
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_stress_all_with_rand_reset.1200230765
Short name	T41
Test name
Test status
Simulation time	200152633788 ps
CPU time	1533.99 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:34:36 PM PDT 24
Peak memory	228688 kb
Host	smart-6de4b45b-1f4a-4414-b50f-bbe6dbc42970
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200230765 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1200230765
Directory	/workspace/65.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.1382662280
Short name	T479
Test name
Test status
Simulation time	13292373437 ps
CPU time	17.76 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:09:21 PM PDT 24
Peak memory	199836 kb
Host	smart-7bb5b820-9b7a-4e68-8cc4-2d925f29f0fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382662280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1382662280
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.756396643
Short name	T343
Test name
Test status
Simulation time	31120957109 ps
CPU time	18.8 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:09:23 PM PDT 24
Peak memory	200092 kb
Host	smart-1908d339-3905-4466-ac2e-782974bb0a84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756396643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.756396643
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.4201560587
Short name	T833
Test name
Test status
Simulation time	105678895674 ps
CPU time	40.45 seconds
Started	Mar 12 01:09:03 PM PDT 24
Finished	Mar 12 01:09:45 PM PDT 24
Peak memory	199804 kb
Host	smart-64f48e26-66eb-4968-b2ee-d37846718f1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201560587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4201560587
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_stress_all_with_rand_reset.247745191
Short name	T356
Test name
Test status
Simulation time	67452359333 ps
CPU time	297.42 seconds
Started	Mar 12 01:09:05 PM PDT 24
Finished	Mar 12 01:14:04 PM PDT 24
Peak memory	216772 kb
Host	smart-b4d6905e-63f6-4a57-842f-8e69e2d73823
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247745191 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.247745191
Directory	/workspace/69.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.1195292632
Short name	T647
Test name
Test status
Simulation time	10884464 ps
CPU time	0.55 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:07:04 PM PDT 24
Peak memory	195548 kb
Host	smart-04d9d6c5-1efd-41be-898e-84703d6dbb52
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195292632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1195292632
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.2758618598
Short name	T764
Test name
Test status
Simulation time	56701927861 ps
CPU time	58.6 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:08:11 PM PDT 24
Peak memory	200116 kb
Host	smart-96711340-abc3-4138-9fd2-f4a421fc929c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758618598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2758618598
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.3953950358
Short name	T625
Test name
Test status
Simulation time	57967008256 ps
CPU time	41.59 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:53 PM PDT 24
Peak memory	200156 kb
Host	smart-756f7826-5325-4343-8ff5-6ba0617dd592
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953950358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3953950358
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.2578786976
Short name	T1003
Test name
Test status
Simulation time	49485521459 ps
CPU time	27.38 seconds
Started	Mar 12 01:07:02 PM PDT 24
Finished	Mar 12 01:07:29 PM PDT 24
Peak memory	200020 kb
Host	smart-223cfce3-5d0b-4521-9565-ea9d2498eace
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578786976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2578786976
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_intr.3757888544
Short name	T532
Test name
Test status
Simulation time	10181052687 ps
CPU time	22.32 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:32 PM PDT 24
Peak memory	198992 kb
Host	smart-8b4a3167-5347-4e6f-9193-a43275378632
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757888544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3757888544
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.358319012
Short name	T661
Test name
Test status
Simulation time	185146096525 ps
CPU time	666.29 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:18:17 PM PDT 24
Peak memory	200048 kb
Host	smart-cf0cc9dc-e53e-41ee-8525-34e719ffcec0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=358319012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.358319012
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_loopback.2076195774
Short name	T530
Test name
Test status
Simulation time	9889257183 ps
CPU time	11.3 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:24 PM PDT 24
Peak memory	197956 kb
Host	smart-c55fec92-d6f0-40b0-9d56-ab82e7d87e7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076195774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2076195774
Directory	/workspace/7.uart_loopback/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.1080060964
Short name	T1061
Test name
Test status
Simulation time	150989764369 ps
CPU time	83.04 seconds
Started	Mar 12 01:07:04 PM PDT 24
Finished	Mar 12 01:08:27 PM PDT 24
Peak memory	208584 kb
Host	smart-4ae8cac0-fdee-4056-84d6-f37e45179e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080060964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1080060964
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.9730790
Short name	T679
Test name
Test status
Simulation time	21316559246 ps
CPU time	234.49 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:11:00 PM PDT 24
Peak memory	200084 kb
Host	smart-b3a8fc56-e953-4e92-b1e4-71aaf4e03580
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=9730790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.9730790
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_oversample.1031984858
Short name	T14
Test name
Test status
Simulation time	3048361816 ps
CPU time	9.75 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:21 PM PDT 24
Peak memory	198624 kb
Host	smart-e693a999-3972-4f71-95e8-51c9f0d1741a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1031984858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1031984858
Directory	/workspace/7.uart_rx_oversample/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.1133737558
Short name	T701
Test name
Test status
Simulation time	11204957735 ps
CPU time	17.31 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:27 PM PDT 24
Peak memory	197884 kb
Host	smart-da6db739-b786-4ef6-bdc8-2554bd681812
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133737558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1133737558
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.621761500
Short name	T415
Test name
Test status
Simulation time	1950106944 ps
CPU time	1.72 seconds
Started	Mar 12 01:07:00 PM PDT 24
Finished	Mar 12 01:07:02 PM PDT 24
Peak memory	195372 kb
Host	smart-516d5936-513f-41cc-b894-13ea85ad4801
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621761500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.621761500
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.2199670364
Short name	T1041
Test name
Test status
Simulation time	651231713 ps
CPU time	2.38 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:07:14 PM PDT 24
Peak memory	198548 kb
Host	smart-9ff21602-9e2b-4be8-9a30-1dd027fef928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199670364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2199670364
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_stress_all.1043924278
Short name	T727
Test name
Test status
Simulation time	361920253291 ps
CPU time	1017.47 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:24:03 PM PDT 24
Peak memory	200124 kb
Host	smart-a5ea84f7-9961-494c-b7ab-72ce935fc876
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043924278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1043924278
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_stress_all_with_rand_reset.3360460552
Short name	T440
Test name
Test status
Simulation time	37935134227 ps
CPU time	445.5 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:14:36 PM PDT 24
Peak memory	216860 kb
Host	smart-4272f2a7-f9f5-492e-aca9-3d3bfbd60049
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360460552 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3360460552
Directory	/workspace/7.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.3544542083
Short name	T22
Test name
Test status
Simulation time	2757924720 ps
CPU time	2.63 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	198316 kb
Host	smart-3ad9d1ac-8bf1-43cc-916f-1e399cde7f3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544542083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3544542083
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.146555361
Short name	T715
Test name
Test status
Simulation time	36677661907 ps
CPU time	14.57 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:24 PM PDT 24
Peak memory	199784 kb
Host	smart-001f36b9-c093-4758-97b0-ea4b4a740f55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146555361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.146555361
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.2566406671
Short name	T303
Test name
Test status
Simulation time	41601099088 ps
CPU time	61.55 seconds
Started	Mar 12 01:09:05 PM PDT 24
Finished	Mar 12 01:10:08 PM PDT 24
Peak memory	200092 kb
Host	smart-8bb1c6a0-ea7e-486e-8996-ede667697712
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566406671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2566406671
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.3986647384
Short name	T191
Test name
Test status
Simulation time	31169954966 ps
CPU time	62.28 seconds
Started	Mar 12 01:09:01 PM PDT 24
Finished	Mar 12 01:10:03 PM PDT 24
Peak memory	200000 kb
Host	smart-2ed4906f-c271-4b17-8894-8aa19aa95d40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986647384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3986647384
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.2772569888
Short name	T550
Test name
Test status
Simulation time	47088178894 ps
CPU time	18.71 seconds
Started	Mar 12 01:09:02 PM PDT 24
Finished	Mar 12 01:09:21 PM PDT 24
Peak memory	199256 kb
Host	smart-1263e8c4-58cb-4187-95d7-1b52140ab73c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772569888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2772569888
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.1397331480
Short name	T315
Test name
Test status
Simulation time	265302504068 ps
CPU time	111.62 seconds
Started	Mar 12 01:09:04 PM PDT 24
Finished	Mar 12 01:10:56 PM PDT 24
Peak memory	199536 kb
Host	smart-fb2dc02b-a8dc-4b7c-950c-61398ce5fd84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397331480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1397331480
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.856851879
Short name	T1082
Test name
Test status
Simulation time	35198701455 ps
CPU time	14.34 seconds
Started	Mar 12 01:09:13 PM PDT 24
Finished	Mar 12 01:09:27 PM PDT 24
Peak memory	200044 kb
Host	smart-706f1646-9661-419f-91ca-1bbd45bc8cc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856851879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.856851879
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.832297539
Short name	T326
Test name
Test status
Simulation time	88154429136 ps
CPU time	34.12 seconds
Started	Mar 12 01:09:12 PM PDT 24
Finished	Mar 12 01:09:47 PM PDT 24
Peak memory	200104 kb
Host	smart-0a304dda-7e1b-4af9-a975-12b484fe2a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832297539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.832297539
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_stress_all_with_rand_reset.2339407665
Short name	T15
Test name
Test status
Simulation time	21968689883 ps
CPU time	220.03 seconds
Started	Mar 12 01:09:17 PM PDT 24
Finished	Mar 12 01:12:58 PM PDT 24
Peak memory	211708 kb
Host	smart-9a001c63-73bf-46c7-bae7-4a43255c9fa0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339407665 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2339407665
Directory	/workspace/78.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.2292332372
Short name	T254
Test name
Test status
Simulation time	118038030926 ps
CPU time	54.69 seconds
Started	Mar 12 01:09:20 PM PDT 24
Finished	Mar 12 01:10:14 PM PDT 24
Peak memory	200048 kb
Host	smart-727367ac-ce9e-46dd-bfea-490ca41b201b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2292332372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2292332372
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.3466407470
Short name	T767
Test name
Test status
Simulation time	34755153 ps
CPU time	0.58 seconds
Started	Mar 12 01:07:02 PM PDT 24
Finished	Mar 12 01:07:03 PM PDT 24
Peak memory	195484 kb
Host	smart-d1948037-cdcb-48de-84bb-19fc1b0d7f39
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466407470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3466407470
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.276719385
Short name	T814
Test name
Test status
Simulation time	26760670237 ps
CPU time	50.1 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:08:01 PM PDT 24
Peak memory	200028 kb
Host	smart-046ef593-5b1c-4b62-929b-95fc879e2c70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276719385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.276719385
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.3395466381
Short name	T128
Test name
Test status
Simulation time	81531896200 ps
CPU time	50.54 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:56 PM PDT 24
Peak memory	199920 kb
Host	smart-edee9b40-1337-43cb-a078-3378574a6793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395466381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3395466381
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.2725674185
Short name	T629
Test name
Test status
Simulation time	40311010825 ps
CPU time	36.85 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:46 PM PDT 24
Peak memory	200076 kb
Host	smart-bcce8cc6-678d-4a31-928d-b48b877f742b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725674185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2725674185
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.2550953704
Short name	T613
Test name
Test status
Simulation time	141993425453 ps
CPU time	355.06 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:13:05 PM PDT 24
Peak memory	200052 kb
Host	smart-b71c1a26-7f27-4a74-afe5-00dbdcbc811f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2550953704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2550953704
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/8.uart_loopback.2190738966
Short name	T576
Test name
Test status
Simulation time	6147323244 ps
CPU time	4.11 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:09 PM PDT 24
Peak memory	197764 kb
Host	smart-bc1dd26d-745e-4912-90e6-3ec48822ef93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190738966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2190738966
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.3420242832
Short name	T1095
Test name
Test status
Simulation time	41510631694 ps
CPU time	60 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:08:06 PM PDT 24
Peak memory	197296 kb
Host	smart-c3733e37-b365-4f8c-b6ad-cd1038a88c0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420242832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3420242832
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.4294115957
Short name	T421
Test name
Test status
Simulation time	23355527545 ps
CPU time	1201.8 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:27:14 PM PDT 24
Peak memory	200068 kb
Host	smart-ae8bdd59-05cb-4647-8f4f-7bc8154ea325
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4294115957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.4294115957
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_oversample.2315074401
Short name	T845
Test name
Test status
Simulation time	6969554973 ps
CPU time	16.93 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:23 PM PDT 24
Peak memory	198480 kb
Host	smart-621703c6-32a8-486a-a88c-b6f69ff1da01
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2315074401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2315074401
Directory	/workspace/8.uart_rx_oversample/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.218353140
Short name	T1051
Test name
Test status
Simulation time	15871022160 ps
CPU time	9.81 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:22 PM PDT 24
Peak memory	197840 kb
Host	smart-0e9c0d49-bd19-421d-9430-cea72ea97a7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218353140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.218353140
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.2911625237
Short name	T1027
Test name
Test status
Simulation time	32841152264 ps
CPU time	24.31 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:36 PM PDT 24
Peak memory	195812 kb
Host	smart-0465e779-79f0-4cac-9e02-925925016876
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911625237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2911625237
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.1706795673
Short name	T645
Test name
Test status
Simulation time	456158263 ps
CPU time	1.52 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:07:11 PM PDT 24
Peak memory	198536 kb
Host	smart-f1960b44-7a9a-4571-ae8a-cfef4860ee3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706795673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1706795673
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all_with_rand_reset.1899232735
Short name	T370
Test name
Test status
Simulation time	115597294604 ps
CPU time	987.35 seconds
Started	Mar 12 01:07:14 PM PDT 24
Finished	Mar 12 01:23:42 PM PDT 24
Peak memory	224980 kb
Host	smart-f5e2796d-4d56-4b15-a3b3-9d82def068bb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899232735 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1899232735
Directory	/workspace/8.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.594214272
Short name	T749
Test name
Test status
Simulation time	6604182477 ps
CPU time	20.15 seconds
Started	Mar 12 01:06:58 PM PDT 24
Finished	Mar 12 01:07:19 PM PDT 24
Peak memory	199640 kb
Host	smart-2a1f6898-376e-4ee0-b0eb-c00c495ce3c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594214272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.594214272
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.1090322156
Short name	T896
Test name
Test status
Simulation time	76127120614 ps
CPU time	57.03 seconds
Started	Mar 12 01:07:03 PM PDT 24
Finished	Mar 12 01:08:00 PM PDT 24
Peak memory	200008 kb
Host	smart-91ee5537-5670-4835-b647-70c1b5cb06fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090322156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1090322156
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.3745739258
Short name	T1052
Test name
Test status
Simulation time	190711106477 ps
CPU time	59.96 seconds
Started	Mar 12 01:09:13 PM PDT 24
Finished	Mar 12 01:10:13 PM PDT 24
Peak memory	200120 kb
Host	smart-263eb634-a7b3-45a0-aae2-b0ab413582cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745739258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3745739258
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.3794043275
Short name	T979
Test name
Test status
Simulation time	105443935947 ps
CPU time	196.46 seconds
Started	Mar 12 01:09:16 PM PDT 24
Finished	Mar 12 01:12:32 PM PDT 24
Peak memory	200044 kb
Host	smart-aba5ccc5-1d3d-47c7-82e5-a731b6426fdb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794043275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3794043275
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.2238009494
Short name	T1083
Test name
Test status
Simulation time	44011877912 ps
CPU time	18.9 seconds
Started	Mar 12 01:09:15 PM PDT 24
Finished	Mar 12 01:09:35 PM PDT 24
Peak memory	200108 kb
Host	smart-0ffb244d-4a57-4315-842d-0e2e11ad2553
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238009494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2238009494
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.2293256488
Short name	T252
Test name
Test status
Simulation time	35951119431 ps
CPU time	35.31 seconds
Started	Mar 12 01:09:14 PM PDT 24
Finished	Mar 12 01:09:50 PM PDT 24
Peak memory	200024 kb
Host	smart-a654f977-8a2f-47f8-9239-71ac70b34a59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293256488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2293256488
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.671594309
Short name	T563
Test name
Test status
Simulation time	47798129583 ps
CPU time	21.87 seconds
Started	Mar 12 01:09:14 PM PDT 24
Finished	Mar 12 01:09:36 PM PDT 24
Peak memory	199264 kb
Host	smart-724c67bf-783b-4e1d-b423-fe09d922100e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671594309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.671594309
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_stress_all_with_rand_reset.1888176206
Short name	T113
Test name
Test status
Simulation time	15993382171 ps
CPU time	152.03 seconds
Started	Mar 12 01:09:16 PM PDT 24
Finished	Mar 12 01:11:48 PM PDT 24
Peak memory	208388 kb
Host	smart-70c19c6b-c00c-451a-9046-2fecf6f9165a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888176206 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1888176206
Directory	/workspace/84.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.3279505601
Short name	T230
Test name
Test status
Simulation time	3677405498 ps
CPU time	6.77 seconds
Started	Mar 12 01:09:19 PM PDT 24
Finished	Mar 12 01:09:26 PM PDT 24
Peak memory	199292 kb
Host	smart-75b9eed0-daec-42fc-ab9c-2ae654d437c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279505601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3279505601
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.3894048485
Short name	T325
Test name
Test status
Simulation time	15635635292 ps
CPU time	14.7 seconds
Started	Mar 12 01:09:20 PM PDT 24
Finished	Mar 12 01:09:35 PM PDT 24
Peak memory	199928 kb
Host	smart-9c71a995-fd65-4787-8709-b814a16e721b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894048485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3894048485
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.695376991
Short name	T267
Test name
Test status
Simulation time	90356656258 ps
CPU time	33.09 seconds
Started	Mar 12 01:09:17 PM PDT 24
Finished	Mar 12 01:09:51 PM PDT 24
Peak memory	200032 kb
Host	smart-8a42e1fb-86dc-41bc-b13f-ac64d42469cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695376991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.695376991
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_stress_all_with_rand_reset.3446970177
Short name	T436
Test name
Test status
Simulation time	270251656887 ps
CPU time	804.69 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:22:50 PM PDT 24
Peak memory	224968 kb
Host	smart-2590b3d4-c182-43a1-9210-085791f1d763
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446970177 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3446970177
Directory	/workspace/87.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/88.uart_stress_all_with_rand_reset.3402492686
Short name	T439
Test name
Test status
Simulation time	28938048884 ps
CPU time	147.96 seconds
Started	Mar 12 01:09:24 PM PDT 24
Finished	Mar 12 01:11:53 PM PDT 24
Peak memory	216100 kb
Host	smart-a5801524-0364-41a3-8b2b-9584db32fea6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402492686 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3402492686
Directory	/workspace/88.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.2246025477
Short name	T982
Test name
Test status
Simulation time	28067169661 ps
CPU time	40.63 seconds
Started	Mar 12 01:09:15 PM PDT 24
Finished	Mar 12 01:09:56 PM PDT 24
Peak memory	199988 kb
Host	smart-a795249c-b09f-47c5-bb44-d5780d086940
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246025477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2246025477
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.1306696756
Short name	T571
Test name
Test status
Simulation time	27735600 ps
CPU time	0.57 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:11 PM PDT 24
Peak memory	194480 kb
Host	smart-7a25dee0-730f-4c58-9a0e-4784c273b45a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306696756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1306696756
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.2314200230
Short name	T352
Test name
Test status
Simulation time	116866718257 ps
CPU time	172.17 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:10:06 PM PDT 24
Peak memory	200156 kb
Host	smart-ac5b5cd6-c5a3-4480-9ef9-e6e3e535a5ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314200230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2314200230
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.1206836053
Short name	T922
Test name
Test status
Simulation time	16583692096 ps
CPU time	8.45 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:20 PM PDT 24
Peak memory	198824 kb
Host	smart-ba215225-5d00-4c1e-a548-a15620d74d5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206836053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1206836053
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.4202016053
Short name	T172
Test name
Test status
Simulation time	154750249924 ps
CPU time	53.81 seconds
Started	Mar 12 01:07:08 PM PDT 24
Finished	Mar 12 01:08:05 PM PDT 24
Peak memory	200112 kb
Host	smart-dea8d61d-e771-4acb-9742-0ab6fd9d9c3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202016053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4202016053
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_intr.2387705057
Short name	T724
Test name
Test status
Simulation time	115952374406 ps
CPU time	177.47 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:10:11 PM PDT 24
Peak memory	200100 kb
Host	smart-c55296d2-b975-431d-88ff-6572cc571efb
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387705057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2387705057
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.400628305
Short name	T461
Test name
Test status
Simulation time	150878393835 ps
CPU time	298.49 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:12:11 PM PDT 24
Peak memory	199900 kb
Host	smart-f7e83b97-f0e1-4f89-aee8-4a2a9df61e08
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=400628305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.400628305
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.612514854
Short name	T800
Test name
Test status
Simulation time	2793199055 ps
CPU time	1.5 seconds
Started	Mar 12 01:07:07 PM PDT 24
Finished	Mar 12 01:07:13 PM PDT 24
Peak memory	196952 kb
Host	smart-94ad41f8-a2b5-4448-80fc-2b90fcea948a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612514854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.612514854
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.1833754088
Short name	T418
Test name
Test status
Simulation time	112364508042 ps
CPU time	121.67 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:09:13 PM PDT 24
Peak memory	200288 kb
Host	smart-ee89e6e5-fbfd-47ce-9bd0-f0e48a89b4ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833754088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1833754088
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.1064012316
Short name	T126
Test name
Test status
Simulation time	14551082249 ps
CPU time	756.1 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:19:48 PM PDT 24
Peak memory	200072 kb
Host	smart-1ce6a1f7-3dcf-47d4-8859-ccd188466ad5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1064012316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1064012316
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_oversample.2982731029
Short name	T1000
Test name
Test status
Simulation time	2949781103 ps
CPU time	21.24 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:33 PM PDT 24
Peak memory	198664 kb
Host	smart-4cb26ade-9d7d-4c7c-8d35-f13933c57183
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2982731029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2982731029
Directory	/workspace/9.uart_rx_oversample/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.480286557
Short name	T287
Test name
Test status
Simulation time	54567016474 ps
CPU time	31.79 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:47 PM PDT 24
Peak memory	200124 kb
Host	smart-6e7385b3-e94b-42ab-9cc9-97e25b440619
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480286557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.480286557
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.1645880143
Short name	T736
Test name
Test status
Simulation time	35456769474 ps
CPU time	14.08 seconds
Started	Mar 12 01:07:09 PM PDT 24
Finished	Mar 12 01:07:26 PM PDT 24
Peak memory	195568 kb
Host	smart-10e361cc-2583-4094-ae3e-ea4bf546116f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645880143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1645880143
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.2710776728
Short name	T920
Test name
Test status
Simulation time	5748321895 ps
CPU time	7.37 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:07:19 PM PDT 24
Peak memory	200136 kb
Host	smart-036fb116-59b6-42a8-a3a5-5fd362596b18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2710776728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2710776728
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all.2928068718
Short name	T231
Test name
Test status
Simulation time	83502062922 ps
CPU time	118.99 seconds
Started	Mar 12 01:07:10 PM PDT 24
Finished	Mar 12 01:09:12 PM PDT 24
Peak memory	200128 kb
Host	smart-91512d7b-ca8c-4f66-970d-9ae267d00a75
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928068718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2928068718
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.1595972342
Short name	T842
Test name
Test status
Simulation time	1606187783 ps
CPU time	1.53 seconds
Started	Mar 12 01:07:06 PM PDT 24
Finished	Mar 12 01:07:12 PM PDT 24
Peak memory	197900 kb
Host	smart-fe3958a1-837f-45e4-a24b-f1ca17fc1d9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595972342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1595972342
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.2446415891
Short name	T806
Test name
Test status
Simulation time	44702943939 ps
CPU time	80.1 seconds
Started	Mar 12 01:07:05 PM PDT 24
Finished	Mar 12 01:08:26 PM PDT 24
Peak memory	200076 kb
Host	smart-651b5935-40e5-4c8c-a034-8a7f27fbffc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446415891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2446415891
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.3681188904
Short name	T1060
Test name
Test status
Simulation time	54970853539 ps
CPU time	26.56 seconds
Started	Mar 12 01:09:14 PM PDT 24
Finished	Mar 12 01:09:40 PM PDT 24
Peak memory	200120 kb
Host	smart-b7450503-4c6a-487f-a8c1-098621a03a12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681188904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3681188904
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.2703024928
Short name	T111
Test name
Test status
Simulation time	370992251268 ps
CPU time	1141.29 seconds
Started	Mar 12 01:09:22 PM PDT 24
Finished	Mar 12 01:28:23 PM PDT 24
Peak memory	224888 kb
Host	smart-b7a877c3-ab29-46df-940c-6607d029a36c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703024928 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2703024928
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.980911537
Short name	T971
Test name
Test status
Simulation time	63351737674 ps
CPU time	102.47 seconds
Started	Mar 12 01:09:19 PM PDT 24
Finished	Mar 12 01:11:02 PM PDT 24
Peak memory	199264 kb
Host	smart-08327d6c-2138-486f-9b45-2af40446657b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980911537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.980911537
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.3438168563
Short name	T204
Test name
Test status
Simulation time	66665613619 ps
CPU time	23.64 seconds
Started	Mar 12 01:09:19 PM PDT 24
Finished	Mar 12 01:09:43 PM PDT 24
Peak memory	199820 kb
Host	smart-f9d49648-aeb2-46e3-9707-f47f14cab7d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438168563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3438168563
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.631508398
Short name	T205
Test name
Test status
Simulation time	47922560647 ps
CPU time	15.7 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:09:41 PM PDT 24
Peak memory	198768 kb
Host	smart-376a1e32-bcae-4bb5-8c9f-3727f4b35ee9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631508398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.631508398
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.2164205773
Short name	T486
Test name
Test status
Simulation time	35859987559 ps
CPU time	49.36 seconds
Started	Mar 12 01:09:25 PM PDT 24
Finished	Mar 12 01:10:14 PM PDT 24
Peak memory	199752 kb
Host	smart-8334df5a-0ed6-4927-938a-37f6cccb90dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164205773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2164205773
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.911124444
Short name	T1094
Test name
Test status
Simulation time	80816756281 ps
CPU time	17.21 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:09:40 PM PDT 24
Peak memory	200092 kb
Host	smart-3d473613-17bb-4b72-af01-99123664d01c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=911124444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.911124444
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.2261301964
Short name	T677
Test name
Test status
Simulation time	13015237870 ps
CPU time	5.71 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:09:28 PM PDT 24
Peak memory	199788 kb
Host	smart-c4462b9e-c3d9-4a31-9658-903fa697038d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261301964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2261301964
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.2165503984
Short name	T1058
Test name
Test status
Simulation time	47639709534 ps
CPU time	21.51 seconds
Started	Mar 12 01:09:19 PM PDT 24
Finished	Mar 12 01:09:41 PM PDT 24
Peak memory	199492 kb
Host	smart-80e08bbe-d648-45e0-855e-4ab6aeff2d7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165503984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2165503984
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.3823383846
Short name	T813
Test name
Test status
Simulation time	35604507839 ps
CPU time	7.48 seconds
Started	Mar 12 01:09:22 PM PDT 24
Finished	Mar 12 01:09:30 PM PDT 24
Peak memory	200128 kb
Host	smart-f90dae10-72b5-44d3-a382-f1694c5734f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823383846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3823383846
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.4063583750
Short name	T345
Test name
Test status
Simulation time	27565070257 ps
CPU time	10.65 seconds
Started	Mar 12 01:09:22 PM PDT 24
Finished	Mar 12 01:09:33 PM PDT 24
Peak memory	199852 kb
Host	smart-e73fb944-ca93-4879-bbdc-fb9a6dc879c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063583750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4063583750
Directory	/workspace/99.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_stress_all_with_rand_reset.3036590639
Short name	T910
Test name
Test status
Simulation time	81751118820 ps
CPU time	473.94 seconds
Started	Mar 12 01:09:23 PM PDT 24
Finished	Mar 12 01:17:17 PM PDT 24
Peak memory	216904 kb
Host	smart-15584014-ac1e-472c-b4dd-b71c82b0f54e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036590639 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3036590639
Directory	/workspace/99.uart_stress_all_with_rand_reset/latest

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