Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60246362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16906725

1

T1

18

T2

23

T3

80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73605718	1			T1	89		T2	14693		T3	1673
values[0x0]	1688565	1			T1	23		T2	31		T3	103
values[0x1]	1858804	1			T1	27		T2	22		T3	115

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41693336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35459751

1

T1

57

T2

4860

T3

684

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	282645	1			T2	30		T4	8		T6	14
valid_sources[0x01]	294743	1			T2	31		T4	7		T6	1
valid_sources[0x02]	268859	1			T1	1		T2	51		T4	1
valid_sources[0x03]	290374	1			T1	1		T2	86		T4	4
valid_sources[0x04]	301373	1			T2	26		T4	4		T6	1
valid_sources[0x05]	282057	1			T1	2		T2	63		T4	1
valid_sources[0x06]	292086	1			T2	52		T4	4		T6	3
valid_sources[0x07]	350055	1			T2	72		T4	6		T6	1
valid_sources[0x08]	279840	1			T2	73		T4	8		T6	2
valid_sources[0x09]	332451	1			T2	35		T4	5		T7	1
valid_sources[0x0a]	309701	1			T2	72		T4	5		T6	8
valid_sources[0x0b]	279972	1			T2	33		T4	5		T8	19
valid_sources[0x0c]	302750	1			T2	72		T4	1		T7	2
valid_sources[0x0d]	293188	1			T2	59		T4	7		T6	7
valid_sources[0x0e]	338174	1			T2	53		T6	19		T7	5
valid_sources[0x0f]	720258	1			T1	4		T2	50		T6	6
valid_sources[0x10]	289379	1			T2	48		T4	3		T6	8
valid_sources[0x11]	297262	1			T2	88		T4	10		T6	4
valid_sources[0x12]	283663	1			T2	78		T7	3		T8	26
valid_sources[0x13]	291158	1			T2	65		T4	1		T7	2
valid_sources[0x14]	316562	1			T2	87		T4	3		T6	2
valid_sources[0x15]	302440	1			T2	86		T4	3		T6	1
valid_sources[0x16]	292608	1			T2	61		T4	3		T8	25
valid_sources[0x17]	309488	1			T2	32		T6	4		T7	2
valid_sources[0x18]	295108	1			T2	75		T4	2		T7	1
valid_sources[0x19]	290994	1			T1	1		T2	38		T4	4
valid_sources[0x1a]	335718	1			T2	84		T4	1		T6	2
valid_sources[0x1b]	278703	1			T2	71		T6	3		T7	3
valid_sources[0x1c]	289674	1			T2	77		T6	2		T8	23
valid_sources[0x1d]	363094	1			T1	1		T2	55		T4	5
valid_sources[0x1e]	287466	1			T1	2		T2	49		T4	2
valid_sources[0x1f]	287374	1			T2	68		T4	3		T7	4
valid_sources[0x20]	296074	1			T1	2		T2	17		T3	83
valid_sources[0x21]	288512	1			T1	1		T2	68		T4	4
valid_sources[0x22]	304769	1			T2	56		T4	3		T7	1
valid_sources[0x23]	286301	1			T2	68		T4	8		T7	1
valid_sources[0x24]	302361	1			T2	54		T4	1		T6	6
valid_sources[0x25]	312261	1			T2	63		T8	31		T9	37
valid_sources[0x26]	285923	1			T2	44		T4	8		T6	12
valid_sources[0x27]	317934	1			T1	1		T2	50		T4	5
valid_sources[0x28]	301263	1			T2	10		T4	1		T8	30
valid_sources[0x29]	271901	1			T2	85		T4	8		T8	20
valid_sources[0x2a]	312186	1			T2	68		T6	12		T7	1
valid_sources[0x2b]	284847	1			T2	55		T5	1019		T6	10
valid_sources[0x2c]	323970	1			T2	27		T4	2		T7	3
valid_sources[0x2d]	272595	1			T2	34		T4	1		T7	11
valid_sources[0x2e]	284599	1			T1	1		T2	65		T4	6
valid_sources[0x2f]	275762	1			T2	29		T4	1		T6	2
valid_sources[0x30]	298428	1			T2	51		T4	7		T7	8
valid_sources[0x31]	275930	1			T2	43		T4	3		T6	1
valid_sources[0x32]	291093	1			T2	56		T4	6		T8	29
valid_sources[0x33]	303669	1			T2	85		T4	3		T6	8
valid_sources[0x34]	297487	1			T2	34		T4	3		T6	6
valid_sources[0x35]	298293	1			T2	42		T4	4		T6	18
valid_sources[0x36]	281765	1			T2	101		T4	1		T8	15
valid_sources[0x37]	270326	1			T2	70		T4	1		T6	2
valid_sources[0x38]	293374	1			T1	4		T2	72		T4	2
valid_sources[0x39]	303596	1			T2	110		T4	2		T8	35
valid_sources[0x3a]	270810	1			T2	44		T4	3		T8	41
valid_sources[0x3b]	290864	1			T2	57		T4	9		T7	1
valid_sources[0x3c]	299577	1			T2	59		T4	2		T6	3
valid_sources[0x3d]	280998	1			T1	1		T2	69		T4	2
valid_sources[0x3e]	278358	1			T1	10		T2	99		T4	2
valid_sources[0x3f]	293644	1			T1	4		T2	36		T4	2
valid_sources[0x40]	294040	1			T1	1		T2	64		T4	3
valid_sources[0x41]	305316	1			T2	51		T4	3		T7	7
valid_sources[0x42]	275571	1			T2	119		T7	3		T8	26
valid_sources[0x43]	299266	1			T1	3		T2	65		T4	4
valid_sources[0x44]	355238	1			T2	86		T4	3		T7	3
valid_sources[0x45]	278301	1			T2	16		T7	4		T8	30
valid_sources[0x46]	285516	1			T2	73		T4	2		T5	317
valid_sources[0x47]	284547	1			T2	54		T4	3		T7	2
valid_sources[0x48]	345707	1			T1	2		T2	58		T4	2
valid_sources[0x49]	274992	1			T2	67		T6	20		T7	2
valid_sources[0x4a]	289207	1			T2	74		T4	7		T7	1
valid_sources[0x4b]	268662	1			T2	69		T6	3		T7	3
valid_sources[0x4c]	288387	1			T2	54		T4	2		T7	3
valid_sources[0x4d]	283319	1			T2	69		T4	2		T6	7
valid_sources[0x4e]	297562	1			T2	91		T4	7		T7	1
valid_sources[0x4f]	308860	1			T2	77		T4	4		T6	2
valid_sources[0x50]	307124	1			T1	4		T2	64		T4	3
valid_sources[0x51]	317135	1			T2	25		T8	30		T9	32
valid_sources[0x52]	415337	1			T2	47		T7	1		T8	34
valid_sources[0x53]	294441	1			T2	76		T4	8		T7	5
valid_sources[0x54]	279728	1			T1	1		T2	82		T4	2
valid_sources[0x55]	383066	1			T2	101		T4	4		T6	6
valid_sources[0x56]	317286	1			T2	45		T7	5		T8	36
valid_sources[0x57]	314316	1			T1	1		T2	43		T4	5
valid_sources[0x58]	274133	1			T2	39		T4	1		T6	2
valid_sources[0x59]	288995	1			T2	98		T4	2		T7	2
valid_sources[0x5a]	373544	1			T2	77		T4	6		T6	3
valid_sources[0x5b]	400086	1			T2	31		T4	2		T8	36
valid_sources[0x5c]	328308	1			T2	100		T4	3		T7	4
valid_sources[0x5d]	314791	1			T2	25		T4	3		T6	6
valid_sources[0x5e]	284056	1			T2	62		T4	2		T6	2
valid_sources[0x5f]	280726	1			T2	52		T3	170		T4	5
valid_sources[0x60]	348811	1			T2	60		T4	3		T7	2
valid_sources[0x61]	282933	1			T2	95		T4	6		T7	7
valid_sources[0x62]	281565	1			T2	80		T8	21		T9	94
valid_sources[0x63]	275921	1			T1	1		T2	84		T4	2
valid_sources[0x64]	290845	1			T2	51		T4	5		T6	9
valid_sources[0x65]	293254	1			T2	59		T4	3		T6	1
valid_sources[0x66]	290152	1			T2	56		T4	1		T6	2
valid_sources[0x67]	287484	1			T2	51		T4	4		T7	1
valid_sources[0x68]	281514	1			T2	94		T6	1		T7	1
valid_sources[0x69]	390311	1			T2	28		T4	1		T6	3
valid_sources[0x6a]	273321	1			T2	48		T4	5		T6	5
valid_sources[0x6b]	286416	1			T2	53		T4	2		T7	1
valid_sources[0x6c]	278267	1			T1	2		T2	71		T4	4
valid_sources[0x6d]	285918	1			T2	90		T4	4		T7	7
valid_sources[0x6e]	295450	1			T1	7		T2	61		T4	4
valid_sources[0x6f]	276409	1			T1	1		T2	69		T4	1
valid_sources[0x70]	400581	1			T1	1		T2	64		T4	4
valid_sources[0x71]	327531	1			T2	59		T7	3		T8	16
valid_sources[0x72]	332923	1			T2	84		T4	3		T7	2
valid_sources[0x73]	310575	1			T1	1		T2	24		T4	6
valid_sources[0x74]	335348	1			T2	61		T4	2		T6	4
valid_sources[0x75]	270748	1			T2	101		T4	4		T6	2
valid_sources[0x76]	300038	1			T2	26		T6	6		T7	9
valid_sources[0x77]	302232	1			T2	18		T4	6		T7	4
valid_sources[0x78]	286035	1			T2	51		T4	1		T7	2
valid_sources[0x79]	281590	1			T2	80		T4	5		T6	10
valid_sources[0x7a]	291389	1			T2	74		T7	2		T8	25
valid_sources[0x7b]	272113	1			T1	1		T2	11		T4	9
valid_sources[0x7c]	285775	1			T2	29		T4	2		T7	1
valid_sources[0x7d]	269937	1			T2	58		T4	5		T7	1
valid_sources[0x7e]	268989	1			T1	1		T2	29		T4	1
valid_sources[0x7f]	306656	1			T2	103		T8	32		T9	52
valid_sources[0x80]	290841	1			T1	1		T2	83		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13994326

1

T1

2

T2

8

T3

12

values[0x0]

all_enables

biggest_size

1480807

1

T1

12

T2

9

T3

38

values[0x1]

all_enables

biggest_size

1431592

1

T1

4

T2

6

T3

30