Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	4602274	0	0
ctrl_rd_A	2147483647	110794	0	0
intr_enable_rd_A	2147483647	97208	0	0
ovrd_rd_A	2147483647	107586	0	0
timeout_ctrl_rd_A	2147483647	109149	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4602274	0	0
T14	365887	0	0	0
T15	0	308334	0	0
T21	213043	85670	0	0
T22	0	114513	0	0
T34	0	176567	0	0
T35	0	105591	0	0
T36	0	271104	0	0
T37	0	210821	0	0
T38	0	101955	0	0
T39	0	65634	0	0
T40	0	136543	0	0
T41	347415	0	0	0
T42	434423	0	0	0
T43	131597	0	0	0
T44	371355	0	0	0
T45	203855	0	0	0
T46	710510	0	0	0
T47	303468	0	0	0
T48	198133	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110794	0	0
T22	477718	12934	0	0
T35	0	5433	0	0
T52	0	4832	0	0
T95	180819	0	0	0
T96	481877	0	0	0
T97	586010	0	0	0
T98	562254	0	0	0
T99	164872	0	0	0
T100	935281	0	0	0
T101	345056	0	0	0
T102	569941	0	0	0
T103	0	4307	0	0
T104	0	6270	0	0
T105	0	24487	0	0
T106	0	4712	0	0
T107	0	3021	0	0
T108	0	4022	0	0
T109	0	23635	0	0
T110	100616	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	97208	0	0
T11	493542	10	0	0
T12	189973	0	0	0
T16	0	12	0	0
T19	237462	0	0	0
T20	213757	0	0	0
T22	0	10749	0	0
T23	203601	0	0	0
T35	0	4671	0	0
T50	717780	0	0	0
T85	502903	0	0	0
T103	0	3456	0	0
T104	0	5245	0	0
T111	0	22	0	0
T112	0	53	0	0
T113	0	5	0	0
T114	0	6	0	0
T115	115384	0	0	0
T116	5502	0	0	0
T117	229925	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107586	0	0
T22	477718	12435	0	0
T35	0	5586	0	0
T52	0	4614	0	0
T95	180819	0	0	0
T96	481877	0	0	0
T97	586010	0	0	0
T98	562254	0	0	0
T99	164872	0	0	0
T100	935281	0	0	0
T101	345056	0	0	0
T102	569941	0	0	0
T103	0	4060	0	0
T104	0	6307	0	0
T105	0	23373	0	0
T106	0	4709	0	0
T107	0	3019	0	0
T108	0	3608	0	0
T109	0	23009	0	0
T110	100616	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109149	0	0
T22	477718	12904	0	0
T35	0	5279	0	0
T52	0	4724	0	0
T95	180819	0	0	0
T96	481877	0	0	0
T97	586010	0	0	0
T98	562254	0	0	0
T99	164872	0	0	0
T100	935281	0	0	0
T101	345056	0	0	0
T102	569941	0	0	0
T103	0	4200	0	0
T104	0	6208	0	0
T105	0	23159	0	0
T106	0	4711	0	0
T107	0	3177	0	0
T108	0	4118	0	0
T109	0	24150	0	0
T110	100616	0	0	0