Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64188517	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17157016

1

T1

26309

T2

56

T3

115

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	77942372	1			T1	94009		T2	62		T3	2593
values[0x0]	1616248	1			T1	340		T2	109		T3	166
values[0x1]	1786913	1			T1	381		T2	99		T3	148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44427002	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36918531

1

T1

45448

T2

86

T3

952

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	355430	1			T1	347		T3	15		T4	4
valid_sources[0x01]	300434	1			T1	375		T3	5		T4	4
valid_sources[0x02]	308947	1			T1	391		T3	10		T4	3
valid_sources[0x03]	327946	1			T1	398		T3	3		T4	1
valid_sources[0x04]	296137	1			T1	360		T3	11		T4	2
valid_sources[0x05]	309313	1			T1	375		T3	11		T4	4
valid_sources[0x06]	309067	1			T1	333		T3	5		T4	2
valid_sources[0x07]	301993	1			T1	375		T3	9		T4	1
valid_sources[0x08]	301604	1			T1	360		T3	9		T4	1
valid_sources[0x09]	360012	1			T1	334		T3	12		T4	4
valid_sources[0x0a]	346528	1			T1	337		T2	195		T3	9
valid_sources[0x0b]	345369	1			T1	365		T3	14		T4	1
valid_sources[0x0c]	325602	1			T1	342		T3	13		T4	2
valid_sources[0x0d]	292613	1			T1	321		T3	10		T4	4
valid_sources[0x0e]	303988	1			T1	334		T3	15		T4	1
valid_sources[0x0f]	294336	1			T1	339		T3	7		T4	3
valid_sources[0x10]	294635	1			T1	380		T3	12		T4	3
valid_sources[0x11]	321377	1			T1	329		T3	11		T4	1
valid_sources[0x12]	348922	1			T1	364		T3	8		T4	3
valid_sources[0x13]	319557	1			T1	350		T3	14		T4	2
valid_sources[0x14]	301116	1			T1	377		T3	16		T4	3
valid_sources[0x15]	316394	1			T1	354		T3	15		T4	3
valid_sources[0x16]	307613	1			T1	306		T3	5		T4	1
valid_sources[0x17]	293025	1			T1	345		T3	15		T4	4
valid_sources[0x18]	316103	1			T1	402		T3	11		T4	2
valid_sources[0x19]	349950	1			T1	363		T3	7		T4	1
valid_sources[0x1a]	299000	1			T1	391		T3	17		T4	1
valid_sources[0x1b]	308355	1			T1	421		T3	15		T4	4
valid_sources[0x1c]	304913	1			T1	367		T3	14		T4	1
valid_sources[0x1d]	377647	1			T1	361		T3	12		T4	1
valid_sources[0x1e]	314255	1			T1	415		T3	11		T4	1
valid_sources[0x1f]	296187	1			T1	395		T3	14		T4	1
valid_sources[0x20]	303089	1			T1	368		T3	13		T4	2
valid_sources[0x21]	285898	1			T1	398		T3	10		T4	5
valid_sources[0x22]	351936	1			T1	383		T3	11		T4	2
valid_sources[0x23]	286407	1			T1	350		T3	5		T4	1
valid_sources[0x24]	343384	1			T1	409		T3	20		T4	3
valid_sources[0x25]	315563	1			T1	333		T3	12		T4	2
valid_sources[0x26]	332459	1			T1	417		T3	15		T6	700
valid_sources[0x27]	296563	1			T1	391		T3	9		T6	759
valid_sources[0x28]	295203	1			T1	349		T3	10		T4	6
valid_sources[0x29]	299154	1			T1	352		T3	10		T4	3
valid_sources[0x2a]	320027	1			T1	402		T3	12		T4	2
valid_sources[0x2b]	306101	1			T1	280		T3	16		T6	728
valid_sources[0x2c]	304924	1			T1	318		T3	13		T4	1
valid_sources[0x2d]	324325	1			T1	350		T3	15		T4	3
valid_sources[0x2e]	311951	1			T1	378		T3	17		T4	1
valid_sources[0x2f]	298410	1			T1	384		T3	14		T4	1
valid_sources[0x30]	314560	1			T1	409		T3	17		T4	2
valid_sources[0x31]	315602	1			T1	373		T3	15		T4	2
valid_sources[0x32]	389033	1			T1	367		T3	13		T4	1
valid_sources[0x33]	416784	1			T1	317		T3	10		T6	769
valid_sources[0x34]	303593	1			T1	387		T3	14		T4	5
valid_sources[0x35]	290153	1			T1	413		T3	8		T4	2
valid_sources[0x36]	299598	1			T1	353		T3	9		T4	4
valid_sources[0x37]	303613	1			T1	324		T3	10		T4	2
valid_sources[0x38]	293998	1			T1	388		T3	18		T4	1
valid_sources[0x39]	296377	1			T1	373		T3	15		T4	3
valid_sources[0x3a]	318833	1			T1	359		T3	17		T4	1
valid_sources[0x3b]	309086	1			T1	366		T3	13		T4	3
valid_sources[0x3c]	358921	1			T1	375		T3	12		T6	777
valid_sources[0x3d]	310190	1			T1	354		T3	10		T4	5
valid_sources[0x3e]	310532	1			T1	327		T3	15		T4	2
valid_sources[0x3f]	312228	1			T1	395		T3	21		T4	1
valid_sources[0x40]	364184	1			T1	401		T3	12		T4	5
valid_sources[0x41]	304366	1			T1	361		T3	13		T4	5
valid_sources[0x42]	286776	1			T1	370		T3	7		T4	1
valid_sources[0x43]	287306	1			T1	318		T3	4		T4	4
valid_sources[0x44]	343475	1			T1	400		T3	9		T4	1
valid_sources[0x45]	305609	1			T1	351		T3	14		T6	745
valid_sources[0x46]	361547	1			T1	367		T3	16		T4	1
valid_sources[0x47]	356192	1			T1	336		T3	16		T4	2
valid_sources[0x48]	320124	1			T1	392		T3	5		T4	3
valid_sources[0x49]	318612	1			T1	383		T3	14		T4	2
valid_sources[0x4a]	377716	1			T1	398		T3	11		T4	1
valid_sources[0x4b]	295115	1			T1	336		T3	13		T6	679
valid_sources[0x4c]	325337	1			T1	346		T3	7		T4	3
valid_sources[0x4d]	309118	1			T1	365		T3	13		T4	3
valid_sources[0x4e]	298489	1			T1	332		T3	10		T6	756
valid_sources[0x4f]	307793	1			T1	397		T3	11		T4	3
valid_sources[0x50]	330184	1			T1	368		T3	11		T4	2
valid_sources[0x51]	329475	1			T1	395		T3	9		T4	4
valid_sources[0x52]	318642	1			T1	345		T3	8		T4	2
valid_sources[0x53]	298224	1			T1	330		T3	7		T4	2
valid_sources[0x54]	320947	1			T1	363		T3	18		T4	4
valid_sources[0x55]	300580	1			T1	363		T3	10		T4	3
valid_sources[0x56]	389314	1			T1	363		T3	11		T4	1
valid_sources[0x57]	301778	1			T1	374		T3	7		T4	2
valid_sources[0x58]	291195	1			T1	409		T3	15		T4	2
valid_sources[0x59]	570484	1			T1	422		T3	14		T6	773
valid_sources[0x5a]	316967	1			T1	384		T3	6		T6	828
valid_sources[0x5b]	295296	1			T1	376		T3	15		T4	7
valid_sources[0x5c]	298577	1			T1	371		T3	9		T4	2
valid_sources[0x5d]	350131	1			T1	365		T3	10		T4	2
valid_sources[0x5e]	313169	1			T1	405		T3	3		T4	2
valid_sources[0x5f]	312368	1			T1	393		T3	10		T4	2
valid_sources[0x60]	321972	1			T1	356		T3	8		T4	1
valid_sources[0x61]	329742	1			T1	366		T3	13		T4	3
valid_sources[0x62]	302657	1			T1	390		T3	9		T4	2
valid_sources[0x63]	320125	1			T1	389		T3	11		T4	3
valid_sources[0x64]	299443	1			T1	391		T3	16		T6	730
valid_sources[0x65]	296833	1			T1	314		T3	11		T4	3
valid_sources[0x66]	326820	1			T1	465		T3	9		T4	7
valid_sources[0x67]	308967	1			T1	376		T3	15		T4	2
valid_sources[0x68]	300292	1			T1	389		T3	10		T4	5
valid_sources[0x69]	294798	1			T1	353		T3	15		T4	1
valid_sources[0x6a]	304377	1			T1	365		T3	12		T6	757
valid_sources[0x6b]	330791	1			T1	358		T3	11		T4	3
valid_sources[0x6c]	299618	1			T1	377		T3	10		T6	703
valid_sources[0x6d]	287964	1			T1	367		T3	14		T4	2
valid_sources[0x6e]	317601	1			T1	396		T3	12		T4	3
valid_sources[0x6f]	307413	1			T1	345		T3	12		T4	2
valid_sources[0x70]	313930	1			T1	369		T3	17		T4	3
valid_sources[0x71]	334678	1			T1	352		T3	8		T4	2
valid_sources[0x72]	326545	1			T1	390		T3	16		T4	4
valid_sources[0x73]	302872	1			T1	385		T3	11		T4	1
valid_sources[0x74]	314749	1			T1	343		T3	7		T4	1
valid_sources[0x75]	292676	1			T1	444		T3	12		T4	2
valid_sources[0x76]	308682	1			T1	402		T3	9		T4	3
valid_sources[0x77]	322891	1			T1	339		T3	13		T4	2
valid_sources[0x78]	305773	1			T1	371		T3	13		T6	747
valid_sources[0x79]	312509	1			T1	362		T3	9		T6	733
valid_sources[0x7a]	305649	1			T1	406		T3	9		T4	5
valid_sources[0x7b]	304828	1			T1	353		T3	10		T4	1
valid_sources[0x7c]	320458	1			T1	326		T3	14		T4	1
valid_sources[0x7d]	296482	1			T1	340		T3	11		T4	4
valid_sources[0x7e]	307866	1			T1	391		T3	13		T4	1
valid_sources[0x7f]	335095	1			T1	378		T3	8		T4	1
valid_sources[0x80]	325520	1			T1	378		T3	13		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14373894

1

T1

26092

T2

4

T3

10

values[0x0]

all_enables

biggest_size

1413847

1

T1

126

T2

31

T3

66

values[0x1]

all_enables

biggest_size

1369275

1

T1

91

T2

21

T3

39