Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	4452793	0	0
ctrl_rd_A	2147483647	74619	0	0
intr_enable_rd_A	2147483647	66829	0	0
ovrd_rd_A	2147483647	75150	0	0
timeout_ctrl_rd_A	2147483647	75384	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4452793	0	0
T11	896824	360278	0	0
T12	579074	0	0	0
T25	0	135706	0	0
T26	0	93532	0	0
T34	0	124902	0	0
T35	0	37934	0	0
T36	0	44094	0	0
T37	0	85814	0	0
T38	0	145640	0	0
T39	0	106739	0	0
T40	0	176081	0	0
T41	480224	0	0	0
T42	762321	0	0	0
T43	101367	0	0	0
T44	537581	0	0	0
T45	852625	0	0	0
T46	203833	0	0	0
T47	541715	0	0	0
T48	499740	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	74619	0	0
T25	844145	15360	0	0
T39	0	11495	0	0
T40	0	19296	0	0
T72	0	22	0	0
T76	0	9	0	0
T98	0	12548	0	0
T99	0	9048	0	0
T100	0	5411	0	0
T101	0	198	0	0
T102	0	17	0	0
T103	411266	0	0	0
T104	933	0	0	0
T105	294192	0	0	0
T106	114680	0	0	0
T107	255176	0	0	0
T108	138419	0	0	0
T109	44216	0	0	0
T110	1131	0	0	0
T111	131252	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	66829	0	0
T25	844145	12904	0	0
T39	0	10572	0	0
T40	0	16777	0	0
T98	0	11831	0	0
T99	0	8445	0	0
T100	0	4760	0	0
T103	411266	0	0	0
T104	933	0	0	0
T105	294192	0	0	0
T106	114680	0	0	0
T107	255176	0	0	0
T108	138419	0	0	0
T109	44216	0	0	0
T110	1131	0	0	0
T111	131252	0	0	0
T112	0	29	0	0
T113	0	22	0	0
T114	0	12	0	0
T115	0	11	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	75150	0	0
T25	844145	15478	0	0
T39	0	12053	0	0
T40	0	19371	0	0
T72	0	2	0	0
T76	0	4	0	0
T98	0	12834	0	0
T99	0	9674	0	0
T100	0	4909	0	0
T101	0	221	0	0
T102	0	22	0	0
T103	411266	0	0	0
T104	933	0	0	0
T105	294192	0	0	0
T106	114680	0	0	0
T107	255176	0	0	0
T108	138419	0	0	0
T109	44216	0	0	0
T110	1131	0	0	0
T111	131252	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	75384	0	0
T25	844145	15299	0	0
T39	0	12189	0	0
T40	0	19532	0	0
T72	0	14	0	0
T76	0	4	0	0
T98	0	12574	0	0
T99	0	9723	0	0
T100	0	5170	0	0
T101	0	222	0	0
T102	0	16	0	0
T103	411266	0	0	0
T104	933	0	0	0
T105	294192	0	0	0
T106	114680	0	0	0
T107	255176	0	0	0
T108	138419	0	0	0
T109	44216	0	0	0
T110	1131	0	0	0
T111	131252	0	0	0