Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67215671	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19225158

1

T1

22

T2

96

T3

125

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82679405	1			T1	1038		T2	963		T3	5540
values[0x0]	1787126	1			T1	33		T2	119		T3	134
values[0x1]	1974298	1			T1	23		T2	104		T3	106

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46622872	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39817957

1

T1

377

T2

417

T3

1966

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	332373	1			T2	6		T5	1		T6	14
valid_sources[0x01]	299647	1			T2	2		T5	2		T6	14
valid_sources[0x02]	304138	1			T1	3		T2	4		T5	1
valid_sources[0x03]	360525	1			T2	1		T5	3		T6	7
valid_sources[0x04]	405991	1			T2	18		T5	2		T6	10
valid_sources[0x05]	323038	1			T1	13		T5	4		T6	8
valid_sources[0x06]	330463	1			T2	7		T5	6		T6	4
valid_sources[0x07]	317752	1			T2	22		T5	2		T6	11
valid_sources[0x08]	316594	1			T2	3		T5	2		T6	12
valid_sources[0x09]	339405	1			T5	2		T6	9		T8	2
valid_sources[0x0a]	354557	1			T1	1		T2	18		T5	4
valid_sources[0x0b]	307741	1			T2	1		T5	3		T6	12
valid_sources[0x0c]	368116	1			T1	1		T5	2		T6	10
valid_sources[0x0d]	332239	1			T1	3		T5	7		T6	14
valid_sources[0x0e]	375915	1			T2	3		T5	3		T6	9
valid_sources[0x0f]	316581	1			T1	1		T2	1		T5	8
valid_sources[0x10]	344189	1			T1	1		T2	1		T5	1
valid_sources[0x11]	310399	1			T1	8		T2	5		T5	1
valid_sources[0x12]	371303	1			T1	4		T2	7		T5	4
valid_sources[0x13]	337274	1			T1	10		T2	5		T5	2
valid_sources[0x14]	387720	1			T1	3		T2	2		T5	3
valid_sources[0x15]	326708	1			T1	3		T2	7		T5	4
valid_sources[0x16]	312509	1			T1	12		T2	4		T5	1
valid_sources[0x17]	309482	1			T2	2		T5	1		T6	14
valid_sources[0x18]	322038	1			T2	2		T5	3		T6	11
valid_sources[0x19]	323275	1			T1	18		T5	7		T6	7
valid_sources[0x1a]	319062	1			T1	4		T6	6		T8	4
valid_sources[0x1b]	323514	1			T1	14		T2	2		T5	4
valid_sources[0x1c]	360228	1			T1	6		T5	6		T6	12
valid_sources[0x1d]	334526	1			T1	12		T2	12		T5	1
valid_sources[0x1e]	356997	1			T2	7		T5	2		T6	11
valid_sources[0x1f]	383839	1			T1	8		T2	2		T5	1
valid_sources[0x20]	309997	1			T1	15		T2	19		T5	4
valid_sources[0x21]	304046	1			T1	40		T2	6		T5	3
valid_sources[0x22]	403602	1			T1	3		T2	10		T5	2
valid_sources[0x23]	332952	1			T1	3		T2	12		T5	3
valid_sources[0x24]	355642	1			T2	5		T5	3		T6	6
valid_sources[0x25]	316522	1			T2	1		T5	1		T6	6
valid_sources[0x26]	356361	1			T1	8		T5	4		T6	12
valid_sources[0x27]	335040	1			T5	2		T6	11		T8	2
valid_sources[0x28]	411647	1			T1	1		T2	8		T5	1
valid_sources[0x29]	721342	1			T1	8		T2	2		T5	3
valid_sources[0x2a]	324924	1			T2	7		T5	2		T6	13
valid_sources[0x2b]	395735	1			T1	18		T2	3		T5	4
valid_sources[0x2c]	306551	1			T1	16		T5	5		T6	9
valid_sources[0x2d]	312655	1			T1	8		T2	24		T5	1
valid_sources[0x2e]	300545	1			T1	2		T5	1		T6	8
valid_sources[0x2f]	344914	1			T2	11		T5	3		T6	9
valid_sources[0x30]	306098	1			T1	2		T2	9		T5	2
valid_sources[0x31]	385239	1			T1	25		T2	5		T5	2
valid_sources[0x32]	344449	1			T1	11		T5	1		T6	9
valid_sources[0x33]	307380	1			T5	2		T6	12		T8	1
valid_sources[0x34]	324350	1			T1	1		T2	10		T5	2
valid_sources[0x35]	324486	1			T1	3		T2	3		T5	3
valid_sources[0x36]	319771	1			T1	8		T2	4		T6	6
valid_sources[0x37]	299189	1			T1	3		T5	7		T6	6
valid_sources[0x38]	297870	1			T1	1		T5	3		T6	9
valid_sources[0x39]	349755	1			T1	8		T5	1		T6	14
valid_sources[0x3a]	306193	1			T1	8		T2	9		T5	4
valid_sources[0x3b]	326215	1			T1	7		T2	20		T5	2
valid_sources[0x3c]	304435	1			T2	7		T5	2		T6	9
valid_sources[0x3d]	308774	1			T1	6		T2	12		T5	2
valid_sources[0x3e]	337118	1			T2	1		T5	2		T6	10
valid_sources[0x3f]	340526	1			T1	4		T2	7		T5	7
valid_sources[0x40]	396624	1			T1	6		T5	5		T6	10
valid_sources[0x41]	305403	1			T1	3		T5	1		T6	13
valid_sources[0x42]	351052	1			T1	11		T2	1		T5	1
valid_sources[0x43]	602321	1			T1	8		T2	2		T4	1445
valid_sources[0x44]	294372	1			T2	2		T5	2		T6	6
valid_sources[0x45]	304962	1			T5	5		T6	9		T21	35
valid_sources[0x46]	312934	1			T2	7		T5	2		T6	15
valid_sources[0x47]	326511	1			T1	5		T2	2		T5	1
valid_sources[0x48]	321239	1			T1	20		T2	5		T5	3
valid_sources[0x49]	305559	1			T1	12		T2	5		T5	3
valid_sources[0x4a]	328832	1			T2	1		T5	8		T6	12
valid_sources[0x4b]	312781	1			T2	6		T6	16		T8	1
valid_sources[0x4c]	322124	1			T2	10		T5	4		T6	12
valid_sources[0x4d]	440930	1			T5	3		T6	10		T8	4
valid_sources[0x4e]	298216	1			T1	8		T2	1		T5	4
valid_sources[0x4f]	302983	1			T1	18		T2	7		T5	3
valid_sources[0x50]	349164	1			T1	42		T2	7		T5	1
valid_sources[0x51]	329755	1			T1	3		T5	1		T6	14
valid_sources[0x52]	321162	1			T1	9		T5	3		T6	12
valid_sources[0x53]	320026	1			T2	6		T5	3		T6	14
valid_sources[0x54]	371593	1			T2	4		T5	2		T6	11
valid_sources[0x55]	337386	1			T1	11		T2	4		T5	2
valid_sources[0x56]	309804	1			T1	8		T2	4		T5	2
valid_sources[0x57]	311870	1			T5	2		T6	9		T14	1
valid_sources[0x58]	312990	1			T2	5		T5	1		T6	11
valid_sources[0x59]	328980	1			T1	9		T2	6		T5	1
valid_sources[0x5a]	326031	1			T1	20		T5	5		T6	8
valid_sources[0x5b]	329392	1			T1	1		T2	14		T5	5
valid_sources[0x5c]	305137	1			T2	3		T5	3		T6	11
valid_sources[0x5d]	309198	1			T1	5		T3	964		T5	3
valid_sources[0x5e]	369730	1			T1	4		T2	34		T5	2
valid_sources[0x5f]	300840	1			T1	1		T2	6		T5	1
valid_sources[0x60]	347086	1			T2	10		T5	6		T6	12
valid_sources[0x61]	330797	1			T2	2		T3	127		T5	1
valid_sources[0x62]	323207	1			T2	2		T5	3		T6	7
valid_sources[0x63]	331151	1			T1	1		T5	4		T6	8
valid_sources[0x64]	382871	1			T1	8		T2	14		T5	1
valid_sources[0x65]	357425	1			T1	10		T2	2		T5	2
valid_sources[0x66]	318045	1			T1	7		T2	6		T5	2
valid_sources[0x67]	342315	1			T1	1		T5	5		T6	6
valid_sources[0x68]	326262	1			T2	4		T5	2		T6	2
valid_sources[0x69]	296350	1			T2	21		T5	3		T6	7
valid_sources[0x6a]	302133	1			T1	8		T5	3		T6	7
valid_sources[0x6b]	428409	1			T1	5		T2	7		T5	4
valid_sources[0x6c]	318689	1			T1	4		T2	4		T5	1
valid_sources[0x6d]	306989	1			T1	2		T2	1		T5	3
valid_sources[0x6e]	372463	1			T1	6		T2	1		T5	5
valid_sources[0x6f]	339327	1			T1	6		T5	4		T6	20
valid_sources[0x70]	330039	1			T1	4		T5	5		T6	8
valid_sources[0x71]	315481	1			T1	16		T2	10		T5	3
valid_sources[0x72]	306743	1			T2	9		T5	4		T6	16
valid_sources[0x73]	305657	1			T2	7		T5	6		T6	13
valid_sources[0x74]	309072	1			T2	11		T5	4		T6	7
valid_sources[0x75]	329523	1			T2	3		T5	1		T6	12
valid_sources[0x76]	296084	1			T1	9		T2	5		T5	9
valid_sources[0x77]	325208	1			T1	12		T5	8		T6	13
valid_sources[0x78]	321557	1			T2	26		T5	6		T6	4
valid_sources[0x79]	293063	1			T1	8		T2	13		T5	3
valid_sources[0x7a]	305307	1			T1	10		T5	2		T6	12
valid_sources[0x7b]	349338	1			T2	9		T5	4		T6	9
valid_sources[0x7c]	363728	1			T5	2		T6	15		T8	2
valid_sources[0x7d]	341171	1			T2	5		T5	2		T6	7
valid_sources[0x7e]	311341	1			T1	2		T5	4		T6	11
valid_sources[0x7f]	378295	1			T1	5		T5	5		T6	4
valid_sources[0x80]	306850	1			T1	2		T2	7		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16124089

1

T1

6

T2

29

T3

49

values[0x0]

all_enables

biggest_size

1574484

1

T1

12

T2

41

T3

56

values[0x1]

all_enables

biggest_size

1526585

1

T1

4

T2

26

T3

20