Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	4979321	0	0
ctrl_rd_A	2147483647	79204	0	0
intr_enable_rd_A	2147483647	70843	0	0
ovrd_rd_A	2147483647	76118	0	0
timeout_ctrl_rd_A	2147483647	77845	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4979321	0	0
T20	607180	0	0	0
T27	345142	102980	0	0
T28	0	117789	0	0
T29	0	236119	0	0
T31	1415	0	0	0
T37	0	137386	0	0
T38	0	84439	0	0
T39	0	50004	0	0
T40	0	85366	0	0
T41	0	51156	0	0
T42	0	190954	0	0
T43	0	212270	0	0
T44	113123	0	0	0
T45	185676	0	0	0
T46	12545	0	0	0
T47	296491	0	0	0
T48	573888	0	0	0
T49	302782	0	0	0
T50	297116	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	79204	0	0
T37	608397	15105	0	0
T38	0	9328	0	0
T39	0	5620	0	0
T41	0	5880	0	0
T43	0	9161	0	0
T55	427380	0	0	0
T56	527759	0	0	0
T57	170315	0	0	0
T58	243028	0	0	0
T59	230271	0	0	0
T60	578900	0	0	0
T61	1037	0	0	0
T62	152342	0	0	0
T63	404172	0	0	0
T87	0	20	0	0
T111	0	14514	0	0
T112	0	11427	0	0
T113	0	4638	0	0
T114	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70843	0	0
T16	401669	18	0	0
T17	495954	0	0	0
T37	0	13452	0	0
T38	0	8477	0	0
T39	0	4835	0	0
T41	0	5107	0	0
T43	0	8268	0	0
T94	237210	0	0	0
T111	0	13075	0	0
T115	0	32	0	0
T116	0	20	0	0
T117	0	14	0	0
T118	375247	0	0	0
T119	458470	0	0	0
T120	793791	0	0	0
T121	60638	0	0	0
T122	380449	0	0	0
T123	216971	0	0	0
T124	156831	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	76118	0	0
T37	608397	14425	0	0
T38	0	9260	0	0
T39	0	5455	0	0
T41	0	5974	0	0
T43	0	9134	0	0
T55	427380	0	0	0
T56	527759	0	0	0
T57	170315	0	0	0
T58	243028	0	0	0
T59	230271	0	0	0
T60	578900	0	0	0
T61	1037	0	0	0
T62	152342	0	0	0
T63	404172	0	0	0
T87	0	19	0	0
T111	0	14302	0	0
T112	0	11308	0	0
T113	0	4720	0	0
T114	0	35	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	77845	0	0
T37	608397	15006	0	0
T38	0	9448	0	0
T39	0	5918	0	0
T41	0	5938	0	0
T43	0	9458	0	0
T55	427380	0	0	0
T56	527759	0	0	0
T57	170315	0	0	0
T58	243028	0	0	0
T59	230271	0	0	0
T60	578900	0	0	0
T61	1037	0	0	0
T62	152342	0	0	0
T63	404172	0	0	0
T87	0	7	0	0
T111	0	14555	0	0
T112	0	11385	0	0
T113	0	4508	0	0
T114	0	20	0	0