Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65387557	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17569872

1

T1

71

T2

9

T3

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	78978696	1			T1	144		T2	314		T3	220
values[0x0]	1893089	1			T1	39		T2	8		T3	54
values[0x1]	2085644	1			T1	32		T2	5		T3	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45120439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37836990

1

T1

104

T2

114

T3

169

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	303763	1			T4	29		T5	100		T6	4
valid_sources[0x01]	334507	1			T1	3		T3	3		T4	37
valid_sources[0x02]	323920	1			T1	1		T3	1		T4	28
valid_sources[0x03]	306044	1			T3	3		T4	36		T5	39
valid_sources[0x04]	285639	1			T1	1		T4	40		T5	69
valid_sources[0x05]	312757	1			T1	2		T2	8		T3	8
valid_sources[0x06]	379983	1			T1	1		T4	43		T5	62
valid_sources[0x07]	292200	1			T4	35		T5	56		T8	5
valid_sources[0x08]	308288	1			T4	30		T5	59		T6	2
valid_sources[0x09]	308086	1			T2	28		T3	1		T4	35
valid_sources[0x0a]	318692	1			T1	1		T3	4		T4	35
valid_sources[0x0b]	311742	1			T1	1		T3	1		T4	46
valid_sources[0x0c]	341347	1			T1	1		T4	41		T5	60
valid_sources[0x0d]	324134	1			T4	31		T5	44		T6	6
valid_sources[0x0e]	496038	1			T4	38		T5	59		T6	6
valid_sources[0x0f]	352610	1			T1	1		T3	3		T4	37
valid_sources[0x10]	317012	1			T4	32		T5	88		T8	4
valid_sources[0x11]	351562	1			T4	36		T5	77		T6	6
valid_sources[0x12]	331325	1			T1	1		T4	33		T5	66
valid_sources[0x13]	299452	1			T3	5		T4	39		T5	93
valid_sources[0x14]	380415	1			T4	32		T5	30		T6	1
valid_sources[0x15]	319138	1			T4	29		T5	57		T6	4
valid_sources[0x16]	312751	1			T1	1		T3	2		T4	23
valid_sources[0x17]	301714	1			T1	1		T2	2		T4	45
valid_sources[0x18]	304739	1			T1	2		T3	4		T4	27
valid_sources[0x19]	341865	1			T3	1		T4	28		T5	51
valid_sources[0x1a]	306634	1			T1	1		T2	2		T3	2
valid_sources[0x1b]	351679	1			T1	1		T4	32		T5	107
valid_sources[0x1c]	353762	1			T3	2		T4	32		T5	88
valid_sources[0x1d]	289482	1			T1	1		T3	2		T4	30
valid_sources[0x1e]	384787	1			T4	23		T5	84		T6	8
valid_sources[0x1f]	322737	1			T1	1		T4	30		T5	67
valid_sources[0x20]	296532	1			T1	4		T4	25		T5	88
valid_sources[0x21]	286413	1			T1	2		T3	6		T4	50
valid_sources[0x22]	285758	1			T4	29		T5	49		T6	7
valid_sources[0x23]	281557	1			T1	1		T2	1		T4	37
valid_sources[0x24]	289318	1			T1	1		T4	33		T5	64
valid_sources[0x25]	314513	1			T1	1		T2	4		T4	41
valid_sources[0x26]	297784	1			T1	1		T4	34		T5	87
valid_sources[0x27]	314940	1			T1	2		T4	38		T5	90
valid_sources[0x28]	330912	1			T1	2		T3	1		T4	27
valid_sources[0x29]	295425	1			T3	3		T4	28		T5	79
valid_sources[0x2a]	344539	1			T1	1		T3	1		T4	40
valid_sources[0x2b]	301429	1			T1	2		T3	3		T4	42
valid_sources[0x2c]	291819	1			T1	3		T2	14		T4	40
valid_sources[0x2d]	349299	1			T3	4		T4	30		T5	59
valid_sources[0x2e]	377918	1			T1	1		T3	1		T4	33
valid_sources[0x2f]	324628	1			T1	1		T4	33		T5	50
valid_sources[0x30]	329710	1			T3	7		T4	26		T5	74
valid_sources[0x31]	329561	1			T4	29		T5	70		T6	16
valid_sources[0x32]	356063	1			T4	26		T5	58		T6	14
valid_sources[0x33]	321361	1			T1	1		T3	3		T4	37
valid_sources[0x34]	403576	1			T1	2		T4	39		T5	50
valid_sources[0x35]	324364	1			T4	33		T5	48		T6	4
valid_sources[0x36]	334420	1			T1	2		T2	1		T3	3
valid_sources[0x37]	305000	1			T3	4		T4	21		T5	50
valid_sources[0x38]	294899	1			T1	1		T3	2		T4	37
valid_sources[0x39]	321853	1			T1	1		T4	35		T5	75
valid_sources[0x3a]	297991	1			T3	8		T4	42		T5	94
valid_sources[0x3b]	315475	1			T4	31		T5	78		T6	6
valid_sources[0x3c]	307033	1			T4	44		T5	54		T6	9
valid_sources[0x3d]	301731	1			T4	28		T5	45		T6	9
valid_sources[0x3e]	297589	1			T4	27		T5	47		T6	2
valid_sources[0x3f]	303077	1			T1	1		T3	2		T4	28
valid_sources[0x40]	378686	1			T3	1		T4	31		T5	67
valid_sources[0x41]	315667	1			T1	1		T3	2		T4	36
valid_sources[0x42]	352626	1			T4	29		T5	61		T6	3
valid_sources[0x43]	302410	1			T4	46		T5	62		T6	4
valid_sources[0x44]	293150	1			T1	2		T2	14		T4	27
valid_sources[0x45]	350736	1			T4	37		T5	70		T8	3
valid_sources[0x46]	299673	1			T1	4		T4	36		T5	57
valid_sources[0x47]	327812	1			T1	1		T4	39		T5	123
valid_sources[0x48]	337899	1			T1	3		T3	1		T4	33
valid_sources[0x49]	316251	1			T1	1		T3	3		T4	39
valid_sources[0x4a]	315664	1			T1	1		T4	36		T5	54
valid_sources[0x4b]	304697	1			T3	4		T4	30		T5	43
valid_sources[0x4c]	293980	1			T1	2		T4	34		T5	69
valid_sources[0x4d]	327547	1			T1	1		T3	1		T4	31
valid_sources[0x4e]	351929	1			T1	1		T3	1		T4	35
valid_sources[0x4f]	298733	1			T1	2		T4	47		T5	64
valid_sources[0x50]	307659	1			T1	1		T4	36		T5	64
valid_sources[0x51]	341549	1			T1	1		T2	15		T4	21
valid_sources[0x52]	332724	1			T1	2		T4	45		T5	85
valid_sources[0x53]	293840	1			T1	1		T3	1		T4	35
valid_sources[0x54]	347528	1			T1	1		T4	21		T5	82
valid_sources[0x55]	312509	1			T4	33		T5	71		T6	8
valid_sources[0x56]	305678	1			T4	33		T5	60		T8	5
valid_sources[0x57]	376172	1			T1	3		T2	6		T4	35
valid_sources[0x58]	290786	1			T3	2		T4	44		T5	50
valid_sources[0x59]	316203	1			T3	3		T4	33		T5	95
valid_sources[0x5a]	303093	1			T3	1		T4	42		T5	51
valid_sources[0x5b]	348807	1			T3	1		T4	30		T5	44
valid_sources[0x5c]	302244	1			T4	31		T5	41		T6	3
valid_sources[0x5d]	296214	1			T4	33		T5	64		T6	5
valid_sources[0x5e]	314457	1			T1	1		T3	1		T4	31
valid_sources[0x5f]	313233	1			T1	1		T3	2		T4	47
valid_sources[0x60]	313979	1			T4	21		T5	48		T6	6
valid_sources[0x61]	295425	1			T3	5		T4	30		T5	51
valid_sources[0x62]	356966	1			T1	3		T4	38		T5	87
valid_sources[0x63]	316969	1			T2	2		T4	38		T5	66
valid_sources[0x64]	356944	1			T1	1		T3	3		T4	37
valid_sources[0x65]	298555	1			T1	1		T4	36		T5	80
valid_sources[0x66]	285223	1			T1	1		T4	25		T5	44
valid_sources[0x67]	296300	1			T1	1		T3	5		T4	26
valid_sources[0x68]	436689	1			T1	1		T4	45		T5	77
valid_sources[0x69]	299176	1			T3	5		T4	34		T5	62
valid_sources[0x6a]	293890	1			T3	3		T4	30		T5	43
valid_sources[0x6b]	335644	1			T3	3		T4	31		T5	80
valid_sources[0x6c]	303842	1			T1	3		T2	3		T4	38
valid_sources[0x6d]	358956	1			T4	31		T5	56		T6	6
valid_sources[0x6e]	316083	1			T1	2		T3	4		T4	34
valid_sources[0x6f]	300761	1			T1	1		T2	1		T3	1
valid_sources[0x70]	311436	1			T1	1		T4	26		T5	69
valid_sources[0x71]	295423	1			T1	1		T4	24		T5	79
valid_sources[0x72]	293837	1			T1	2		T4	33		T5	60
valid_sources[0x73]	312607	1			T1	1		T4	30		T5	71
valid_sources[0x74]	309421	1			T1	1		T2	4		T3	2
valid_sources[0x75]	334506	1			T1	1		T3	1		T4	43
valid_sources[0x76]	323765	1			T1	1		T3	5		T4	29
valid_sources[0x77]	344670	1			T1	1		T4	27		T5	65
valid_sources[0x78]	286957	1			T1	1		T4	34		T5	69
valid_sources[0x79]	306224	1			T4	27		T5	73		T6	4
valid_sources[0x7a]	313527	1			T3	1		T4	35		T5	71
valid_sources[0x7b]	286594	1			T3	1		T4	38		T5	61
valid_sources[0x7c]	312481	1			T4	30		T5	74		T6	9
valid_sources[0x7d]	307799	1			T4	36		T5	89		T6	5
valid_sources[0x7e]	327583	1			T1	2		T3	2		T4	32
valid_sources[0x7f]	299886	1			T1	2		T2	4		T4	39
valid_sources[0x80]	319863	1			T1	2		T3	2		T4	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14234638

1

T1

48

T2

5

T3

89

values[0x0]

all_enables

biggest_size

1693249

1

T1

14

T2

3

T3

24

values[0x1]

all_enables

biggest_size

1641985

1

T1

9

T2

1

T3

15