Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5301720	0	0
ctrl_rd_A	2147483647	126044	0	0
intr_enable_rd_A	2147483647	111803	0	0
ovrd_rd_A	2147483647	126616	0	0
timeout_ctrl_rd_A	2147483647	125366	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5301720	0	0
T13	860098	0	0	0
T15	0	316300	0	0
T17	0	347896	0	0
T22	136529	52565	0	0
T35	0	151210	0	0
T36	0	119591	0	0
T37	0	42708	0	0
T38	0	41677	0	0
T39	0	88967	0	0
T40	0	19668	0	0
T41	0	155084	0	0
T42	647168	0	0	0
T43	231110	0	0	0
T44	590007	0	0	0
T45	106725	0	0	0
T46	223623	0	0	0
T47	536418	0	0	0
T48	294795	0	0	0
T49	108224	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	126044	0	0
T17	153782	38576	0	0
T37	0	4872	0	0
T56	208326	0	0	0
T57	305664	0	0	0
T58	284862	0	0	0
T59	12289	0	0	0
T60	56982	0	0	0
T61	824683	0	0	0
T62	221205	0	0	0
T63	16977	0	0	0
T64	351983	0	0	0
T66	0	10069	0	0
T111	0	6328	0	0
T112	0	4527	0	0
T113	0	16680	0	0
T114	0	9452	0	0
T115	0	19413	0	0
T116	0	10837	0	0
T117	0	2474	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111803	0	0
T17	153782	33242	0	0
T37	0	4283	0	0
T56	208326	0	0	0
T57	305664	0	0	0
T58	284862	0	0	0
T59	12289	0	0	0
T60	56982	0	0	0
T61	824683	0	0	0
T62	221205	0	0	0
T63	16977	0	0	0
T64	351983	0	0	0
T66	0	9201	0	0
T100	0	17	0	0
T111	0	5492	0	0
T112	0	4212	0	0
T113	0	14778	0	0
T118	0	15	0	0
T119	0	15	0	0
T120	0	15	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	126616	0	0
T17	153782	37942	0	0
T37	0	4681	0	0
T56	208326	0	0	0
T57	305664	0	0	0
T58	284862	0	0	0
T59	12289	0	0	0
T60	56982	0	0	0
T61	824683	0	0	0
T62	221205	0	0	0
T63	16977	0	0	0
T64	351983	0	0	0
T66	0	10491	0	0
T111	0	6227	0	0
T112	0	5159	0	0
T113	0	17629	0	0
T114	0	10385	0	0
T115	0	19882	0	0
T116	0	10668	0	0
T117	0	2292	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125366	0	0
T17	153782	38154	0	0
T37	0	4743	0	0
T56	208326	0	0	0
T57	305664	0	0	0
T58	284862	0	0	0
T59	12289	0	0	0
T60	56982	0	0	0
T61	824683	0	0	0
T62	221205	0	0	0
T63	16977	0	0	0
T64	351983	0	0	0
T66	0	10469	0	0
T111	0	6254	0	0
T112	0	5084	0	0
T113	0	16851	0	0
T114	0	10076	0	0
T115	0	19167	0	0
T116	0	10834	0	0
T117	0	2262	0	0