Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.27 97.90 100.00 98.80 100.00 99.59


Total test records in report: 1261
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T1038 /workspace/coverage/default/246.uart_fifo_reset.1740656990 Mar 24 02:47:33 PM PDT 24 Mar 24 02:49:55 PM PDT 24 53521120912 ps
T1039 /workspace/coverage/default/35.uart_alert_test.2555896292 Mar 24 02:45:01 PM PDT 24 Mar 24 02:45:02 PM PDT 24 50795976 ps
T251 /workspace/coverage/default/217.uart_fifo_reset.1800446947 Mar 24 02:47:22 PM PDT 24 Mar 24 02:48:44 PM PDT 24 99586628668 ps
T1040 /workspace/coverage/default/29.uart_rx_start_bit_filter.231736136 Mar 24 02:44:39 PM PDT 24 Mar 24 02:44:57 PM PDT 24 39114412764 ps
T1041 /workspace/coverage/default/271.uart_fifo_reset.81877443 Mar 24 02:47:54 PM PDT 24 Mar 24 02:49:50 PM PDT 24 81030978176 ps
T1042 /workspace/coverage/default/41.uart_rx_oversample.3644722475 Mar 24 02:45:28 PM PDT 24 Mar 24 02:45:32 PM PDT 24 1277869991 ps
T1043 /workspace/coverage/default/30.uart_stress_all.713486382 Mar 24 02:44:41 PM PDT 24 Mar 24 03:02:10 PM PDT 24 309472339783 ps
T1044 /workspace/coverage/default/27.uart_fifo_full.3342353893 Mar 24 02:44:23 PM PDT 24 Mar 24 02:44:50 PM PDT 24 34427438389 ps
T1045 /workspace/coverage/default/32.uart_intr.956148755 Mar 24 02:44:48 PM PDT 24 Mar 24 02:44:56 PM PDT 24 15511858783 ps
T1046 /workspace/coverage/default/19.uart_stress_all.2646927410 Mar 24 02:44:09 PM PDT 24 Mar 24 02:47:01 PM PDT 24 95984598827 ps
T1047 /workspace/coverage/default/8.uart_alert_test.3604978314 Mar 24 02:43:27 PM PDT 24 Mar 24 02:43:28 PM PDT 24 35799088 ps
T1048 /workspace/coverage/default/25.uart_fifo_overflow.2258500357 Mar 24 02:44:15 PM PDT 24 Mar 24 02:45:41 PM PDT 24 146294550997 ps
T1049 /workspace/coverage/default/20.uart_smoke.882232311 Mar 24 02:44:06 PM PDT 24 Mar 24 02:44:07 PM PDT 24 482850000 ps
T183 /workspace/coverage/default/27.uart_rx_parity_err.3124561283 Mar 24 02:44:27 PM PDT 24 Mar 24 02:44:51 PM PDT 24 55492712633 ps
T1050 /workspace/coverage/default/47.uart_fifo_full.633561437 Mar 24 02:45:58 PM PDT 24 Mar 24 02:46:18 PM PDT 24 109255417782 ps
T1051 /workspace/coverage/default/45.uart_loopback.3026307892 Mar 24 02:45:50 PM PDT 24 Mar 24 02:45:51 PM PDT 24 175645071 ps
T1052 /workspace/coverage/default/31.uart_long_xfer_wo_dly.3066298468 Mar 24 02:44:48 PM PDT 24 Mar 24 02:56:05 PM PDT 24 91560845656 ps
T1053 /workspace/coverage/default/40.uart_fifo_full.4084066345 Mar 24 02:45:34 PM PDT 24 Mar 24 02:47:51 PM PDT 24 124242345604 ps
T1054 /workspace/coverage/default/5.uart_long_xfer_wo_dly.752993672 Mar 24 02:43:23 PM PDT 24 Mar 24 02:46:27 PM PDT 24 72639568567 ps
T1055 /workspace/coverage/default/10.uart_rx_start_bit_filter.4072800322 Mar 24 02:43:32 PM PDT 24 Mar 24 02:43:48 PM PDT 24 39404020369 ps
T231 /workspace/coverage/default/202.uart_fifo_reset.26141213 Mar 24 02:47:19 PM PDT 24 Mar 24 02:47:33 PM PDT 24 45831899946 ps
T1056 /workspace/coverage/default/43.uart_noise_filter.1426891024 Mar 24 02:45:39 PM PDT 24 Mar 24 02:46:18 PM PDT 24 24846002462 ps
T1057 /workspace/coverage/default/10.uart_fifo_full.755985845 Mar 24 02:43:32 PM PDT 24 Mar 24 02:44:15 PM PDT 24 83729156526 ps
T1058 /workspace/coverage/default/17.uart_stress_all.2729954206 Mar 24 02:43:55 PM PDT 24 Mar 24 02:48:25 PM PDT 24 364441839410 ps
T1059 /workspace/coverage/default/27.uart_perf.1584455913 Mar 24 02:44:28 PM PDT 24 Mar 24 02:47:05 PM PDT 24 5079136632 ps
T1060 /workspace/coverage/default/34.uart_intr.4043733871 Mar 24 02:45:01 PM PDT 24 Mar 24 02:45:49 PM PDT 24 28363093887 ps
T255 /workspace/coverage/default/121.uart_fifo_reset.3648831806 Mar 24 02:46:44 PM PDT 24 Mar 24 02:48:40 PM PDT 24 76880623413 ps
T1061 /workspace/coverage/default/7.uart_tx_rx.1981821279 Mar 24 02:43:34 PM PDT 24 Mar 24 02:44:20 PM PDT 24 153297757383 ps
T1062 /workspace/coverage/default/18.uart_long_xfer_wo_dly.2091300630 Mar 24 02:44:08 PM PDT 24 Mar 24 02:49:11 PM PDT 24 108647016028 ps
T1063 /workspace/coverage/default/2.uart_long_xfer_wo_dly.363361977 Mar 24 02:43:25 PM PDT 24 Mar 24 02:47:29 PM PDT 24 98955413898 ps
T1064 /workspace/coverage/default/26.uart_intr.2318807958 Mar 24 02:44:20 PM PDT 24 Mar 24 02:44:24 PM PDT 24 3754047883 ps
T1065 /workspace/coverage/default/18.uart_tx_rx.3283802113 Mar 24 02:44:10 PM PDT 24 Mar 24 02:45:52 PM PDT 24 45931405747 ps
T1066 /workspace/coverage/default/19.uart_fifo_full.3480978613 Mar 24 02:44:12 PM PDT 24 Mar 24 02:45:36 PM PDT 24 174050030426 ps
T1067 /workspace/coverage/default/21.uart_rx_oversample.3511049735 Mar 24 02:44:06 PM PDT 24 Mar 24 02:44:09 PM PDT 24 1700886449 ps
T1068 /workspace/coverage/default/78.uart_fifo_reset.435202292 Mar 24 02:46:25 PM PDT 24 Mar 24 02:46:56 PM PDT 24 19538140292 ps
T1069 /workspace/coverage/default/3.uart_fifo_full.360803787 Mar 24 02:43:21 PM PDT 24 Mar 24 02:49:03 PM PDT 24 155988699421 ps
T1070 /workspace/coverage/default/12.uart_fifo_reset.3932743339 Mar 24 02:43:38 PM PDT 24 Mar 24 02:44:41 PM PDT 24 160568074903 ps
T1071 /workspace/coverage/default/24.uart_stress_all.1158969212 Mar 24 02:44:18 PM PDT 24 Mar 24 02:54:20 PM PDT 24 46487740022 ps
T1072 /workspace/coverage/default/251.uart_fifo_reset.1987108565 Mar 24 02:47:34 PM PDT 24 Mar 24 02:48:07 PM PDT 24 73470446126 ps
T1073 /workspace/coverage/default/241.uart_fifo_reset.2783948899 Mar 24 02:47:29 PM PDT 24 Mar 24 02:48:13 PM PDT 24 223923341222 ps
T1074 /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3785266215 Mar 24 02:46:35 PM PDT 24 Mar 24 02:59:16 PM PDT 24 71372052755 ps
T1075 /workspace/coverage/default/42.uart_intr.2265019594 Mar 24 02:45:35 PM PDT 24 Mar 24 02:45:51 PM PDT 24 10373839425 ps
T1076 /workspace/coverage/default/33.uart_stress_all.2393895338 Mar 24 02:44:52 PM PDT 24 Mar 24 02:45:30 PM PDT 24 93325438562 ps
T1077 /workspace/coverage/default/6.uart_alert_test.2219066083 Mar 24 02:43:37 PM PDT 24 Mar 24 02:43:37 PM PDT 24 18716136 ps
T1078 /workspace/coverage/default/225.uart_fifo_reset.3140042585 Mar 24 02:47:32 PM PDT 24 Mar 24 02:48:26 PM PDT 24 46924081587 ps
T1079 /workspace/coverage/default/9.uart_rx_parity_err.1392127218 Mar 24 02:43:24 PM PDT 24 Mar 24 02:45:47 PM PDT 24 72248847322 ps
T1080 /workspace/coverage/default/165.uart_fifo_reset.3299269745 Mar 24 02:47:01 PM PDT 24 Mar 24 02:47:23 PM PDT 24 30522742420 ps
T1081 /workspace/coverage/default/42.uart_noise_filter.3234697488 Mar 24 02:45:35 PM PDT 24 Mar 24 02:45:51 PM PDT 24 19575802813 ps
T1082 /workspace/coverage/default/36.uart_fifo_full.853808177 Mar 24 02:45:07 PM PDT 24 Mar 24 02:45:59 PM PDT 24 33943883516 ps
T1083 /workspace/coverage/default/41.uart_rx_start_bit_filter.2805151022 Mar 24 02:45:28 PM PDT 24 Mar 24 02:45:48 PM PDT 24 45510140384 ps
T1084 /workspace/coverage/default/141.uart_fifo_reset.4264843245 Mar 24 02:46:48 PM PDT 24 Mar 24 02:47:31 PM PDT 24 68731750976 ps
T260 /workspace/coverage/default/125.uart_fifo_reset.1459462085 Mar 24 02:46:43 PM PDT 24 Mar 24 02:47:31 PM PDT 24 109956238635 ps
T1085 /workspace/coverage/default/46.uart_fifo_full.231587649 Mar 24 02:45:55 PM PDT 24 Mar 24 02:48:56 PM PDT 24 219155346846 ps
T1086 /workspace/coverage/default/6.uart_rx_oversample.50885250 Mar 24 02:43:31 PM PDT 24 Mar 24 02:43:53 PM PDT 24 3019350222 ps
T1087 /workspace/coverage/default/183.uart_fifo_reset.3618631791 Mar 24 02:47:11 PM PDT 24 Mar 24 02:47:52 PM PDT 24 23464889066 ps
T1088 /workspace/coverage/default/27.uart_rx_start_bit_filter.1229474833 Mar 24 02:44:25 PM PDT 24 Mar 24 02:44:26 PM PDT 24 3347761567 ps
T1089 /workspace/coverage/default/6.uart_long_xfer_wo_dly.1996832867 Mar 24 02:43:32 PM PDT 24 Mar 24 02:54:22 PM PDT 24 84996821216 ps
T1090 /workspace/coverage/default/276.uart_fifo_reset.2707066571 Mar 24 02:47:56 PM PDT 24 Mar 24 02:48:19 PM PDT 24 12693423330 ps
T1091 /workspace/coverage/default/41.uart_tx_ovrd.2544882548 Mar 24 02:45:27 PM PDT 24 Mar 24 02:45:39 PM PDT 24 7192994957 ps
T1092 /workspace/coverage/default/37.uart_alert_test.4284039727 Mar 24 02:45:13 PM PDT 24 Mar 24 02:45:14 PM PDT 24 16836300 ps
T1093 /workspace/coverage/default/62.uart_fifo_reset.235519995 Mar 24 02:46:14 PM PDT 24 Mar 24 02:46:43 PM PDT 24 80903463508 ps
T234 /workspace/coverage/default/54.uart_fifo_reset.1716233028 Mar 24 02:46:13 PM PDT 24 Mar 24 02:47:13 PM PDT 24 121956298567 ps
T1094 /workspace/coverage/default/208.uart_fifo_reset.2163717204 Mar 24 02:47:18 PM PDT 24 Mar 24 02:47:32 PM PDT 24 35446551556 ps
T1095 /workspace/coverage/default/41.uart_fifo_full.568729861 Mar 24 02:45:27 PM PDT 24 Mar 24 02:46:49 PM PDT 24 136845051018 ps
T1096 /workspace/coverage/default/22.uart_noise_filter.1967826792 Mar 24 02:44:09 PM PDT 24 Mar 24 02:44:42 PM PDT 24 81417140323 ps
T1097 /workspace/coverage/default/283.uart_fifo_reset.1681672715 Mar 24 02:47:52 PM PDT 24 Mar 24 02:48:58 PM PDT 24 79284130764 ps
T1098 /workspace/coverage/default/8.uart_loopback.3296488297 Mar 24 02:43:33 PM PDT 24 Mar 24 02:43:45 PM PDT 24 5689317699 ps
T1099 /workspace/coverage/default/32.uart_fifo_full.3138407023 Mar 24 02:44:53 PM PDT 24 Mar 24 02:45:39 PM PDT 24 148041197025 ps
T1100 /workspace/coverage/default/49.uart_rx_oversample.1933288940 Mar 24 02:46:07 PM PDT 24 Mar 24 02:46:58 PM PDT 24 6508808975 ps
T1101 /workspace/coverage/default/148.uart_fifo_reset.269909888 Mar 24 02:46:53 PM PDT 24 Mar 24 02:47:06 PM PDT 24 7974044444 ps
T1102 /workspace/coverage/default/13.uart_stress_all.361151801 Mar 24 02:44:05 PM PDT 24 Mar 24 02:49:09 PM PDT 24 291436236428 ps
T1103 /workspace/coverage/default/37.uart_intr.2681683488 Mar 24 02:45:10 PM PDT 24 Mar 24 02:45:35 PM PDT 24 15959872221 ps
T1104 /workspace/coverage/default/23.uart_tx_rx.1550688344 Mar 24 02:44:19 PM PDT 24 Mar 24 02:45:33 PM PDT 24 17962502011 ps
T1105 /workspace/coverage/default/24.uart_rx_start_bit_filter.689835327 Mar 24 02:44:16 PM PDT 24 Mar 24 02:44:31 PM PDT 24 41118033137 ps
T1106 /workspace/coverage/default/259.uart_fifo_reset.1224799008 Mar 24 02:47:40 PM PDT 24 Mar 24 02:47:59 PM PDT 24 10848883614 ps
T1107 /workspace/coverage/default/294.uart_fifo_reset.4046237523 Mar 24 02:47:59 PM PDT 24 Mar 24 02:48:17 PM PDT 24 42087517580 ps
T1108 /workspace/coverage/default/24.uart_rx_oversample.2648054175 Mar 24 02:44:15 PM PDT 24 Mar 24 02:44:21 PM PDT 24 3034390986 ps
T1109 /workspace/coverage/default/41.uart_fifo_reset.1997209614 Mar 24 02:45:26 PM PDT 24 Mar 24 02:47:19 PM PDT 24 170536766934 ps
T1110 /workspace/coverage/default/7.uart_fifo_full.2496353311 Mar 24 02:43:29 PM PDT 24 Mar 24 02:43:46 PM PDT 24 39903295678 ps
T1111 /workspace/coverage/default/27.uart_loopback.1299599834 Mar 24 02:44:28 PM PDT 24 Mar 24 02:44:48 PM PDT 24 13178978973 ps
T1112 /workspace/coverage/default/21.uart_rx_parity_err.780677735 Mar 24 02:44:13 PM PDT 24 Mar 24 02:45:44 PM PDT 24 55510164427 ps
T1113 /workspace/coverage/default/26.uart_alert_test.2383833942 Mar 24 02:44:25 PM PDT 24 Mar 24 02:44:26 PM PDT 24 59577491 ps
T1114 /workspace/coverage/default/21.uart_intr.3233504565 Mar 24 02:44:08 PM PDT 24 Mar 24 02:45:38 PM PDT 24 78396484204 ps
T1115 /workspace/coverage/default/12.uart_long_xfer_wo_dly.63246127 Mar 24 02:43:52 PM PDT 24 Mar 24 02:55:59 PM PDT 24 77219953942 ps
T1116 /workspace/coverage/default/1.uart_stress_all.1713042478 Mar 24 02:43:21 PM PDT 24 Mar 24 03:09:20 PM PDT 24 160272424466 ps
T1117 /workspace/coverage/default/42.uart_smoke.375691585 Mar 24 02:45:36 PM PDT 24 Mar 24 02:45:38 PM PDT 24 721957657 ps
T1118 /workspace/coverage/default/7.uart_long_xfer_wo_dly.994971835 Mar 24 02:43:29 PM PDT 24 Mar 24 02:47:32 PM PDT 24 76032374314 ps
T1119 /workspace/coverage/default/257.uart_fifo_reset.714391795 Mar 24 02:47:39 PM PDT 24 Mar 24 02:50:11 PM PDT 24 101966938903 ps
T1120 /workspace/coverage/default/14.uart_stress_all.1349031629 Mar 24 02:43:45 PM PDT 24 Mar 24 02:44:18 PM PDT 24 40036701133 ps
T1121 /workspace/coverage/default/13.uart_noise_filter.3532806338 Mar 24 02:43:56 PM PDT 24 Mar 24 02:43:59 PM PDT 24 1557431030 ps
T117 /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3658810450 Mar 24 02:46:14 PM PDT 24 Mar 24 02:48:47 PM PDT 24 31019475948 ps
T1122 /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2062133782 Mar 24 02:45:10 PM PDT 24 Mar 24 02:48:11 PM PDT 24 58210681588 ps
T1123 /workspace/coverage/default/51.uart_fifo_reset.2044471839 Mar 24 02:46:08 PM PDT 24 Mar 24 02:46:29 PM PDT 24 37344894659 ps
T1124 /workspace/coverage/default/18.uart_intr.4143688056 Mar 24 02:44:10 PM PDT 24 Mar 24 02:46:18 PM PDT 24 65312637324 ps
T1125 /workspace/coverage/default/6.uart_stress_all.770118206 Mar 24 02:43:27 PM PDT 24 Mar 24 02:45:33 PM PDT 24 10986789423 ps
T1126 /workspace/coverage/default/34.uart_rx_parity_err.1598362233 Mar 24 02:44:57 PM PDT 24 Mar 24 02:45:18 PM PDT 24 40227807069 ps
T1127 /workspace/coverage/cover_reg_top/43.uart_intr_test.3174821777 Mar 24 12:40:26 PM PDT 24 Mar 24 12:40:27 PM PDT 24 19753442 ps
T91 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1505741698 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:51 PM PDT 24 48328908 ps
T1128 /workspace/coverage/cover_reg_top/33.uart_intr_test.3633169077 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 13812273 ps
T1129 /workspace/coverage/cover_reg_top/49.uart_intr_test.1292723591 Mar 24 12:40:25 PM PDT 24 Mar 24 12:40:26 PM PDT 24 12666251 ps
T1130 /workspace/coverage/cover_reg_top/34.uart_intr_test.4063726325 Mar 24 12:40:14 PM PDT 24 Mar 24 12:40:15 PM PDT 24 14845986 ps
T1131 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2683617720 Mar 24 12:39:54 PM PDT 24 Mar 24 12:39:56 PM PDT 24 35321863 ps
T1132 /workspace/coverage/cover_reg_top/44.uart_intr_test.3782367676 Mar 24 12:40:05 PM PDT 24 Mar 24 12:40:06 PM PDT 24 65806922 ps
T1133 /workspace/coverage/cover_reg_top/10.uart_tl_errors.921921293 Mar 24 12:39:56 PM PDT 24 Mar 24 12:39:57 PM PDT 24 74906738 ps
T1134 /workspace/coverage/cover_reg_top/10.uart_intr_test.1784907449 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 30654863 ps
T1135 /workspace/coverage/cover_reg_top/0.uart_intr_test.2384247513 Mar 24 12:39:45 PM PDT 24 Mar 24 12:39:46 PM PDT 24 13773750 ps
T101 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.152652019 Mar 24 12:40:04 PM PDT 24 Mar 24 12:40:05 PM PDT 24 336746391 ps
T1136 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3624589100 Mar 24 12:40:25 PM PDT 24 Mar 24 12:40:26 PM PDT 24 34380979 ps
T70 /workspace/coverage/cover_reg_top/18.uart_csr_rw.2252498597 Mar 24 12:40:17 PM PDT 24 Mar 24 12:40:18 PM PDT 24 41905113 ps
T1137 /workspace/coverage/cover_reg_top/5.uart_tl_errors.271495357 Mar 24 12:39:46 PM PDT 24 Mar 24 12:39:48 PM PDT 24 28006450 ps
T1138 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1724840951 Mar 24 12:39:48 PM PDT 24 Mar 24 12:39:49 PM PDT 24 60332884 ps
T1139 /workspace/coverage/cover_reg_top/12.uart_tl_errors.657997529 Mar 24 12:40:11 PM PDT 24 Mar 24 12:40:12 PM PDT 24 839295372 ps
T102 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.731362228 Mar 24 12:40:00 PM PDT 24 Mar 24 12:40:02 PM PDT 24 161289704 ps
T92 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1054686011 Mar 24 12:40:16 PM PDT 24 Mar 24 12:40:16 PM PDT 24 48355245 ps
T1140 /workspace/coverage/cover_reg_top/36.uart_intr_test.3436732404 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:51 PM PDT 24 26193168 ps
T103 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.744947028 Mar 24 12:39:54 PM PDT 24 Mar 24 12:40:00 PM PDT 24 194442202 ps
T93 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3870966281 Mar 24 12:40:07 PM PDT 24 Mar 24 12:40:07 PM PDT 24 248594920 ps
T1141 /workspace/coverage/cover_reg_top/41.uart_intr_test.1882316842 Mar 24 12:40:09 PM PDT 24 Mar 24 12:40:10 PM PDT 24 141003676 ps
T1142 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3754561091 Mar 24 12:39:59 PM PDT 24 Mar 24 12:40:01 PM PDT 24 116469071 ps
T1143 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2877131099 Mar 24 12:40:15 PM PDT 24 Mar 24 12:40:15 PM PDT 24 44062063 ps
T1144 /workspace/coverage/cover_reg_top/2.uart_intr_test.3164097830 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:58 PM PDT 24 30755714 ps
T1145 /workspace/coverage/cover_reg_top/28.uart_intr_test.4055294830 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:54 PM PDT 24 20966875 ps
T1146 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1293769379 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:03 PM PDT 24 20680242 ps
T1147 /workspace/coverage/cover_reg_top/18.uart_intr_test.3674063356 Mar 24 12:40:06 PM PDT 24 Mar 24 12:40:07 PM PDT 24 13016495 ps
T1148 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3618225977 Mar 24 12:39:56 PM PDT 24 Mar 24 12:39:58 PM PDT 24 129319839 ps
T1149 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4212047493 Mar 24 12:40:06 PM PDT 24 Mar 24 12:40:07 PM PDT 24 108763171 ps
T1150 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3428720339 Mar 24 12:39:52 PM PDT 24 Mar 24 12:39:53 PM PDT 24 46856621 ps
T125 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.820622492 Mar 24 12:40:00 PM PDT 24 Mar 24 12:40:01 PM PDT 24 401094922 ps
T1151 /workspace/coverage/cover_reg_top/21.uart_intr_test.665417383 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:55 PM PDT 24 21992590 ps
T94 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2370087174 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:03 PM PDT 24 24982177 ps
T95 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1838802485 Mar 24 12:40:00 PM PDT 24 Mar 24 12:40:01 PM PDT 24 23387961 ps
T1152 /workspace/coverage/cover_reg_top/35.uart_intr_test.2335436 Mar 24 12:40:26 PM PDT 24 Mar 24 12:40:27 PM PDT 24 38851109 ps
T107 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1672069292 Mar 24 12:40:00 PM PDT 24 Mar 24 12:40:01 PM PDT 24 948544367 ps
T96 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3666100312 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:53 PM PDT 24 32515677 ps
T1153 /workspace/coverage/cover_reg_top/47.uart_intr_test.2735340332 Mar 24 12:40:23 PM PDT 24 Mar 24 12:40:23 PM PDT 24 50076690 ps
T1154 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.577997112 Mar 24 12:39:45 PM PDT 24 Mar 24 12:39:46 PM PDT 24 20379527 ps
T1155 /workspace/coverage/cover_reg_top/6.uart_intr_test.1977741719 Mar 24 12:39:56 PM PDT 24 Mar 24 12:39:57 PM PDT 24 45364706 ps
T97 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3959834601 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:56 PM PDT 24 15109128 ps
T71 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2291909382 Mar 24 12:39:45 PM PDT 24 Mar 24 12:39:46 PM PDT 24 17187282 ps
T98 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2748611928 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:58 PM PDT 24 24816710 ps
T1156 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3110134395 Mar 24 12:39:44 PM PDT 24 Mar 24 12:39:45 PM PDT 24 49075656 ps
T1157 /workspace/coverage/cover_reg_top/11.uart_tl_errors.49189380 Mar 24 12:40:10 PM PDT 24 Mar 24 12:40:11 PM PDT 24 64022006 ps
T88 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2761558978 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 108940932 ps
T99 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2698631574 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:03 PM PDT 24 14425289 ps
T1158 /workspace/coverage/cover_reg_top/19.uart_intr_test.637524183 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:58 PM PDT 24 28400634 ps
T1159 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1857788151 Mar 24 12:39:52 PM PDT 24 Mar 24 12:39:53 PM PDT 24 36795470 ps
T1160 /workspace/coverage/cover_reg_top/25.uart_intr_test.2872206338 Mar 24 12:40:00 PM PDT 24 Mar 24 12:40:01 PM PDT 24 29650406 ps
T1161 /workspace/coverage/cover_reg_top/14.uart_csr_rw.622771104 Mar 24 12:40:12 PM PDT 24 Mar 24 12:40:12 PM PDT 24 30268610 ps
T1162 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3014487655 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:55 PM PDT 24 29612865 ps
T1163 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.708577372 Mar 24 12:39:47 PM PDT 24 Mar 24 12:39:48 PM PDT 24 50950746 ps
T1164 /workspace/coverage/cover_reg_top/31.uart_intr_test.405391605 Mar 24 12:40:05 PM PDT 24 Mar 24 12:40:06 PM PDT 24 13918657 ps
T1165 /workspace/coverage/cover_reg_top/46.uart_intr_test.2654159713 Mar 24 12:40:10 PM PDT 24 Mar 24 12:40:11 PM PDT 24 12853416 ps
T1166 /workspace/coverage/cover_reg_top/3.uart_csr_rw.150382490 Mar 24 12:40:05 PM PDT 24 Mar 24 12:40:06 PM PDT 24 48951113 ps
T1167 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2614647837 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:57 PM PDT 24 47771818 ps
T1168 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1272890434 Mar 24 12:39:52 PM PDT 24 Mar 24 12:39:53 PM PDT 24 16349650 ps
T1169 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1543016641 Mar 24 12:40:12 PM PDT 24 Mar 24 12:40:19 PM PDT 24 37660762 ps
T1170 /workspace/coverage/cover_reg_top/7.uart_csr_rw.258594634 Mar 24 12:40:18 PM PDT 24 Mar 24 12:40:19 PM PDT 24 23053276 ps
T1171 /workspace/coverage/cover_reg_top/12.uart_csr_rw.118613166 Mar 24 12:39:54 PM PDT 24 Mar 24 12:39:55 PM PDT 24 17553171 ps
T72 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3668946169 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:58 PM PDT 24 58275699 ps
T1172 /workspace/coverage/cover_reg_top/20.uart_intr_test.414939646 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:58 PM PDT 24 38965001 ps
T1173 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1558590801 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:56 PM PDT 24 34231933 ps
T1174 /workspace/coverage/cover_reg_top/32.uart_intr_test.3966121511 Mar 24 12:40:17 PM PDT 24 Mar 24 12:40:17 PM PDT 24 14933292 ps
T1175 /workspace/coverage/cover_reg_top/3.uart_intr_test.268374180 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:02 PM PDT 24 16156107 ps
T104 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2891390985 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:55 PM PDT 24 67782235 ps
T1176 /workspace/coverage/cover_reg_top/12.uart_intr_test.849342773 Mar 24 12:39:54 PM PDT 24 Mar 24 12:39:54 PM PDT 24 41938204 ps
T1177 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3874249995 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:03 PM PDT 24 13240862 ps
T1178 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1795188712 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:52 PM PDT 24 214072070 ps
T1179 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1049503367 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:56 PM PDT 24 13956119 ps
T1180 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1453391599 Mar 24 12:39:56 PM PDT 24 Mar 24 12:39:56 PM PDT 24 23842916 ps
T86 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1626881686 Mar 24 12:40:32 PM PDT 24 Mar 24 12:40:32 PM PDT 24 16129504 ps
T1181 /workspace/coverage/cover_reg_top/19.uart_tl_errors.275472045 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:56 PM PDT 24 400684718 ps
T1182 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1481314103 Mar 24 12:40:18 PM PDT 24 Mar 24 12:40:20 PM PDT 24 193552756 ps
T1183 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2449771485 Mar 24 12:39:43 PM PDT 24 Mar 24 12:39:44 PM PDT 24 30254966 ps
T1184 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2419710249 Mar 24 12:39:59 PM PDT 24 Mar 24 12:40:00 PM PDT 24 86964239 ps
T1185 /workspace/coverage/cover_reg_top/42.uart_intr_test.920046809 Mar 24 12:40:16 PM PDT 24 Mar 24 12:40:16 PM PDT 24 14167220 ps
T1186 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.206406855 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 47390269 ps
T1187 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1637617818 Mar 24 12:39:46 PM PDT 24 Mar 24 12:39:47 PM PDT 24 92933162 ps
T1188 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2649066927 Mar 24 12:40:07 PM PDT 24 Mar 24 12:40:08 PM PDT 24 40280353 ps
T1189 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2680197977 Mar 24 12:40:12 PM PDT 24 Mar 24 12:40:12 PM PDT 24 46381803 ps
T1190 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1623789130 Mar 24 12:40:17 PM PDT 24 Mar 24 12:40:18 PM PDT 24 72849528 ps
T1191 /workspace/coverage/cover_reg_top/29.uart_intr_test.3300434750 Mar 24 12:39:52 PM PDT 24 Mar 24 12:39:53 PM PDT 24 13181805 ps
T1192 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2491820791 Mar 24 12:40:01 PM PDT 24 Mar 24 12:40:02 PM PDT 24 59428180 ps
T1193 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3448910225 Mar 24 12:39:47 PM PDT 24 Mar 24 12:39:48 PM PDT 24 240667903 ps
T1194 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3509619970 Mar 24 12:40:04 PM PDT 24 Mar 24 12:40:05 PM PDT 24 16241079 ps
T1195 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2263103098 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:51 PM PDT 24 47253489 ps
T73 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3518042809 Mar 24 12:40:15 PM PDT 24 Mar 24 12:40:16 PM PDT 24 12313806 ps
T1196 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2721042336 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:51 PM PDT 24 442409837 ps
T1197 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2600469020 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:52 PM PDT 24 93768893 ps
T1198 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1410476006 Mar 24 12:40:21 PM PDT 24 Mar 24 12:40:22 PM PDT 24 92579550 ps
T1199 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2037819930 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:54 PM PDT 24 26640248 ps
T74 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1469689737 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:53 PM PDT 24 56817022 ps
T1200 /workspace/coverage/cover_reg_top/26.uart_intr_test.1724151453 Mar 24 12:40:05 PM PDT 24 Mar 24 12:40:06 PM PDT 24 87239166 ps
T1201 /workspace/coverage/cover_reg_top/9.uart_intr_test.891113553 Mar 24 12:40:44 PM PDT 24 Mar 24 12:40:46 PM PDT 24 62318305 ps
T1202 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2041606814 Mar 24 12:40:05 PM PDT 24 Mar 24 12:40:06 PM PDT 24 18907929 ps
T1203 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3460495934 Mar 24 12:39:52 PM PDT 24 Mar 24 12:39:53 PM PDT 24 79177998 ps
T1204 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.65981662 Mar 24 12:40:04 PM PDT 24 Mar 24 12:40:05 PM PDT 24 122911658 ps
T87 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3338860800 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 41490656 ps
T1205 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3231704455 Mar 24 12:39:42 PM PDT 24 Mar 24 12:39:43 PM PDT 24 52318346 ps
T1206 /workspace/coverage/cover_reg_top/2.uart_tl_errors.642166284 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:59 PM PDT 24 63018915 ps
T1207 /workspace/coverage/cover_reg_top/15.uart_intr_test.1959368259 Mar 24 12:40:10 PM PDT 24 Mar 24 12:40:11 PM PDT 24 30042392 ps
T1208 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2467181472 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:53 PM PDT 24 325032611 ps
T1209 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3574519965 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:56 PM PDT 24 14034892 ps
T1210 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2023234296 Mar 24 12:40:00 PM PDT 24 Mar 24 12:40:00 PM PDT 24 50650301 ps
T1211 /workspace/coverage/cover_reg_top/2.uart_csr_rw.12026630 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:07 PM PDT 24 16932982 ps
T1212 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3190366156 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:59 PM PDT 24 67522347 ps
T1213 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2543359067 Mar 24 12:39:47 PM PDT 24 Mar 24 12:39:48 PM PDT 24 104453103 ps
T1214 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3449985037 Mar 24 12:40:01 PM PDT 24 Mar 24 12:40:02 PM PDT 24 576099518 ps
T1215 /workspace/coverage/cover_reg_top/14.uart_intr_test.1609283268 Mar 24 12:39:52 PM PDT 24 Mar 24 12:39:53 PM PDT 24 18170967 ps
T1216 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1356110749 Mar 24 12:40:29 PM PDT 24 Mar 24 12:40:31 PM PDT 24 243646236 ps
T1217 /workspace/coverage/cover_reg_top/38.uart_intr_test.3095918428 Mar 24 12:40:08 PM PDT 24 Mar 24 12:40:08 PM PDT 24 19816982 ps
T89 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1955747498 Mar 24 12:40:16 PM PDT 24 Mar 24 12:40:16 PM PDT 24 11928048 ps
T90 /workspace/coverage/cover_reg_top/13.uart_csr_rw.286541318 Mar 24 12:40:24 PM PDT 24 Mar 24 12:40:25 PM PDT 24 63706891 ps
T105 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2499966205 Mar 24 12:39:49 PM PDT 24 Mar 24 12:39:50 PM PDT 24 76026963 ps
T1218 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4239672791 Mar 24 12:39:48 PM PDT 24 Mar 24 12:39:49 PM PDT 24 14178581 ps
T1219 /workspace/coverage/cover_reg_top/40.uart_intr_test.3668567464 Mar 24 12:40:25 PM PDT 24 Mar 24 12:40:26 PM PDT 24 24035326 ps
T1220 /workspace/coverage/cover_reg_top/8.uart_intr_test.368529902 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 31084282 ps
T1221 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1282190762 Mar 24 12:39:41 PM PDT 24 Mar 24 12:39:42 PM PDT 24 15657915 ps
T1222 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2604390260 Mar 24 12:39:47 PM PDT 24 Mar 24 12:39:49 PM PDT 24 155655115 ps
T1223 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.825677161 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:08 PM PDT 24 45083534 ps
T1224 /workspace/coverage/cover_reg_top/5.uart_intr_test.3675695411 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:50 PM PDT 24 82462568 ps
T1225 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2221169105 Mar 24 12:39:49 PM PDT 24 Mar 24 12:39:50 PM PDT 24 176692573 ps
T1226 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1887208085 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 128243978 ps
T1227 /workspace/coverage/cover_reg_top/39.uart_intr_test.1271908168 Mar 24 12:40:20 PM PDT 24 Mar 24 12:40:21 PM PDT 24 48738266 ps
T1228 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.443090414 Mar 24 12:40:18 PM PDT 24 Mar 24 12:40:19 PM PDT 24 91073181 ps
T1229 /workspace/coverage/cover_reg_top/11.uart_intr_test.1089840819 Mar 24 12:40:02 PM PDT 24 Mar 24 12:40:03 PM PDT 24 14062359 ps
T1230 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2299337597 Mar 24 12:40:06 PM PDT 24 Mar 24 12:40:07 PM PDT 24 259853659 ps
T75 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2437262604 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 15235190 ps
T1231 /workspace/coverage/cover_reg_top/7.uart_intr_test.2345690636 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:53 PM PDT 24 27964624 ps
T1232 /workspace/coverage/cover_reg_top/13.uart_intr_test.3372331961 Mar 24 12:40:15 PM PDT 24 Mar 24 12:40:16 PM PDT 24 13723605 ps
T1233 /workspace/coverage/cover_reg_top/1.uart_intr_test.3717062541 Mar 24 12:39:41 PM PDT 24 Mar 24 12:39:41 PM PDT 24 12692250 ps
T1234 /workspace/coverage/cover_reg_top/45.uart_intr_test.3121146298 Mar 24 12:40:14 PM PDT 24 Mar 24 12:40:15 PM PDT 24 14701193 ps
T1235 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4117711654 Mar 24 12:40:00 PM PDT 24 Mar 24 12:40:01 PM PDT 24 163327186 ps
T126 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1285856709 Mar 24 12:39:43 PM PDT 24 Mar 24 12:39:45 PM PDT 24 164542818 ps
T1236 /workspace/coverage/cover_reg_top/22.uart_intr_test.511519862 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:56 PM PDT 24 53748840 ps
T1237 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1620172253 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 103342478 ps
T1238 /workspace/coverage/cover_reg_top/30.uart_intr_test.1351378492 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:54 PM PDT 24 24290996 ps
T1239 /workspace/coverage/cover_reg_top/16.uart_intr_test.3896140677 Mar 24 12:39:46 PM PDT 24 Mar 24 12:39:46 PM PDT 24 12662257 ps
T1240 /workspace/coverage/cover_reg_top/4.uart_intr_test.2105184958 Mar 24 12:39:55 PM PDT 24 Mar 24 12:39:56 PM PDT 24 12573507 ps
T1241 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2617679337 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:54 PM PDT 24 27949738 ps
T1242 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1715121821 Mar 24 12:40:12 PM PDT 24 Mar 24 12:40:13 PM PDT 24 19252761 ps
T1243 /workspace/coverage/cover_reg_top/37.uart_intr_test.2263878373 Mar 24 12:40:18 PM PDT 24 Mar 24 12:40:19 PM PDT 24 172348407 ps
T1244 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.321268956 Mar 24 12:39:46 PM PDT 24 Mar 24 12:39:47 PM PDT 24 20379298 ps
T1245 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2488876390 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:54 PM PDT 24 258822929 ps
T1246 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3179423272 Mar 24 12:39:50 PM PDT 24 Mar 24 12:39:52 PM PDT 24 16528680 ps
T1247 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1155584667 Mar 24 12:39:40 PM PDT 24 Mar 24 12:39:41 PM PDT 24 24679017 ps
T1248 /workspace/coverage/cover_reg_top/13.uart_tl_errors.4024457069 Mar 24 12:39:52 PM PDT 24 Mar 24 12:39:53 PM PDT 24 171393760 ps
T1249 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3775769838 Mar 24 12:39:51 PM PDT 24 Mar 24 12:39:52 PM PDT 24 19160419 ps
T1250 /workspace/coverage/cover_reg_top/48.uart_intr_test.2850462395 Mar 24 12:39:53 PM PDT 24 Mar 24 12:39:53 PM PDT 24 15656965 ps
T1251 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2096449440 Mar 24 12:39:57 PM PDT 24 Mar 24 12:39:59 PM PDT 24 41594771 ps
T1252 /workspace/coverage/cover_reg_top/27.uart_intr_test.3538707066 Mar 24 12:40:01 PM PDT 24 Mar 24 12:40:02 PM PDT 24 16019263 ps
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