Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.27	97.90	100.00		98.80	100.00	99.59

Total test records in report: 1261

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1253	/workspace/coverage/cover_reg_top/17.uart_intr_test.2736124777			Mar 24 12:40:06 PM PDT 24	Mar 24 12:40:07 PM PDT 24	11906465 ps
T106	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2645881718			Mar 24 12:39:41 PM PDT 24	Mar 24 12:39:42 PM PDT 24	236377909 ps
T1254	/workspace/coverage/cover_reg_top/23.uart_intr_test.154348966			Mar 24 12:39:59 PM PDT 24	Mar 24 12:40:00 PM PDT 24	15401473 ps
T1255	/workspace/coverage/cover_reg_top/7.uart_tl_errors.3631775989			Mar 24 12:40:05 PM PDT 24	Mar 24 12:40:08 PM PDT 24	119868772 ps
T76	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1521304432			Mar 24 12:40:04 PM PDT 24	Mar 24 12:40:06 PM PDT 24	217479389 ps
T1256	/workspace/coverage/cover_reg_top/16.uart_csr_rw.3324970693			Mar 24 12:40:08 PM PDT 24	Mar 24 12:40:09 PM PDT 24	15745713 ps
T1257	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.278055384			Mar 24 12:39:35 PM PDT 24	Mar 24 12:39:36 PM PDT 24	58243547 ps
T1258	/workspace/coverage/cover_reg_top/18.uart_tl_errors.3510785179			Mar 24 12:40:06 PM PDT 24	Mar 24 12:40:08 PM PDT 24	45482286 ps
T1259	/workspace/coverage/cover_reg_top/3.uart_tl_errors.4060708741			Mar 24 12:39:52 PM PDT 24	Mar 24 12:39:54 PM PDT 24	308320322 ps
T1260	/workspace/coverage/cover_reg_top/8.uart_tl_errors.2592981419			Mar 24 12:40:00 PM PDT 24	Mar 24 12:40:01 PM PDT 24	111525885 ps
T1261	/workspace/coverage/cover_reg_top/24.uart_intr_test.3867411253			Mar 24 12:40:03 PM PDT 24	Mar 24 12:40:13 PM PDT 24	17352490 ps

Test location	/workspace/coverage/default/274.uart_fifo_reset.1332890817
Short name	T4
Test name
Test status
Simulation time	79346255273 ps
CPU time	35.97 seconds
Started	Mar 24 02:47:50 PM PDT 24
Finished	Mar 24 02:48:27 PM PDT 24
Peak memory	200204 kb
Host	smart-0a21b1c9-9fc1-4860-bd00-24c751cc8fe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332890817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1332890817
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_stress_all_with_rand_reset.3925867864
Short name	T15
Test name
Test status
Simulation time	988265967445 ps
CPU time	1104.97 seconds
Started	Mar 24 02:44:14 PM PDT 24
Finished	Mar 24 03:02:40 PM PDT 24
Peak memory	226584 kb
Host	smart-01d2ad84-112e-40ea-8c2e-f894ecd529c5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925867864 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3925867864
Directory	/workspace/24.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.1490400781
Short name	T267
Test name
Test status
Simulation time	107668710516 ps
CPU time	921.78 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:59:37 PM PDT 24
Peak memory	200152 kb
Host	smart-b6a7b9c1-cdf1-4f77-81ed-44e20ee2d80b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1490400781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1490400781
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_stress_all.692827400
Short name	T277
Test name
Test status
Simulation time	437255885852 ps
CPU time	596.24 seconds
Started	Mar 24 02:43:43 PM PDT 24
Finished	Mar 24 02:53:40 PM PDT 24
Peak memory	208480 kb
Host	smart-46dc0c40-6d83-4fd4-bbc8-9b00c6a9f9ea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692827400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.692827400
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/default/52.uart_stress_all_with_rand_reset.75514999
Short name	T17
Test name
Test status
Simulation time	156919770282 ps
CPU time	1422.67 seconds
Started	Mar 24 02:46:13 PM PDT 24
Finished	Mar 24 03:09:56 PM PDT 24
Peak memory	231492 kb
Host	smart-ea26b1d0-c32a-4807-bb7d-040fee14189b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75514999 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.75514999
Directory	/workspace/52.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.3143913735
Short name	T26
Test name
Test status
Simulation time	90407315299 ps
CPU time	86.4 seconds
Started	Mar 24 02:44:45 PM PDT 24
Finished	Mar 24 02:46:14 PM PDT 24
Peak memory	200076 kb
Host	smart-59012016-dfcc-42da-b388-75781ed4a2ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143913735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3143913735
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.1319792184
Short name	T146
Test name
Test status
Simulation time	174325277911 ps
CPU time	244.31 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:48:22 PM PDT 24
Peak memory	200200 kb
Host	smart-07455c25-78b6-4136-a84b-fcd135f1bcbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319792184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1319792184
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.1318204714
Short name	T33
Test name
Test status
Simulation time	167085706 ps
CPU time	0.77 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:43:25 PM PDT 24
Peak memory	218636 kb
Host	smart-39570cf9-bbfb-4ef6-b95f-7cc274e96294
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318204714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1318204714
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/default/45.uart_stress_all.4278088685
Short name	T274
Test name
Test status
Simulation time	521367423760 ps
CPU time	359.12 seconds
Started	Mar 24 02:45:53 PM PDT 24
Finished	Mar 24 02:51:57 PM PDT 24
Peak memory	200124 kb
Host	smart-971e8f87-9b4d-452e-8613-af1807b4dfab
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278088685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4278088685
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/23.uart_stress_all.780690837
Short name	T100
Test name
Test status
Simulation time	183503219534 ps
CPU time	645.86 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:55:06 PM PDT 24
Peak memory	200120 kb
Host	smart-e445671c-6674-4200-947b-803f2ea53f01
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780690837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.780690837
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.1381184342
Short name	T49
Test name
Test status
Simulation time	135281115454 ps
CPU time	88.2 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200056 kb
Host	smart-bf3e5a0c-a149-4e08-a919-52d2ff22bbd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381184342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1381184342
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_stress_all.4143280338
Short name	T316
Test name
Test status
Simulation time	331444507788 ps
CPU time	296.56 seconds
Started	Mar 24 02:44:31 PM PDT 24
Finished	Mar 24 02:49:28 PM PDT 24
Peak memory	208476 kb
Host	smart-052a50aa-7596-4b12-ac60-02112ae20186
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143280338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4143280338
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.2343556254
Short name	T121
Test name
Test status
Simulation time	38312316926 ps
CPU time	66.53 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:47:21 PM PDT 24
Peak memory	200008 kb
Host	smart-e86691a8-d9a2-4d75-b458-37f2497ffe01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343556254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2343556254
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.1965297635
Short name	T197
Test name
Test status
Simulation time	66291633669 ps
CPU time	62.64 seconds
Started	Mar 24 02:47:00 PM PDT 24
Finished	Mar 24 02:48:03 PM PDT 24
Peak memory	200184 kb
Host	smart-319fce89-e89a-4d92-977e-e895ad611c57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965297635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1965297635
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_stress_all_with_rand_reset.2287384503
Short name	T41
Test name
Test status
Simulation time	151831721448 ps
CPU time	610.95 seconds
Started	Mar 24 02:44:39 PM PDT 24
Finished	Mar 24 02:54:50 PM PDT 24
Peak memory	225016 kb
Host	smart-470df04c-0bf4-45ea-8dbb-1dbb352fa214
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287384503 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2287384503
Directory	/workspace/29.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.841455766
Short name	T14
Test name
Test status
Simulation time	344617119701 ps
CPU time	196.71 seconds
Started	Mar 24 02:43:40 PM PDT 24
Finished	Mar 24 02:46:56 PM PDT 24
Peak memory	200132 kb
Host	smart-9b6fe2e2-173b-4d61-9374-1714836724b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841455766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.841455766
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2891390985
Short name	T104
Test name
Test status
Simulation time	67782235 ps
CPU time	1.3 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:55 PM PDT 24
Peak memory	199720 kb
Host	smart-0bc00731-fcbb-49c7-a49f-d8583bb7e6c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891390985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2891390985
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/15.uart_stress_all.1417210826
Short name	T273
Test name
Test status
Simulation time	144683004356 ps
CPU time	696.1 seconds
Started	Mar 24 02:43:48 PM PDT 24
Finished	Mar 24 02:55:24 PM PDT 24
Peak memory	208472 kb
Host	smart-edf2a77b-3512-4204-baa9-0e91961a1ffe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417210826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1417210826
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_alert_test.2875952954
Short name	T373
Test name
Test status
Simulation time	18847880 ps
CPU time	0.56 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:43:35 PM PDT 24
Peak memory	194980 kb
Host	smart-2f978130-b849-4867-a370-80922b1f25e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875952954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2875952954
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.2252498597
Short name	T70
Test name
Test status
Simulation time	41905113 ps
CPU time	0.62 seconds
Started	Mar 24 12:40:17 PM PDT 24
Finished	Mar 24 12:40:18 PM PDT 24
Peak memory	195804 kb
Host	smart-0b547054-74e4-43a6-8ff8-c5ed160a6b9f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252498597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2252498597
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.2636771730
Short name	T494
Test name
Test status
Simulation time	34469193154 ps
CPU time	130.24 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:46:29 PM PDT 24
Peak memory	200140 kb
Host	smart-0be1306b-ff63-4ac3-9a71-50bc969ca0a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2636771730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2636771730
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.2897774420
Short name	T45
Test name
Test status
Simulation time	44469184566 ps
CPU time	20.01 seconds
Started	Mar 24 02:46:54 PM PDT 24
Finished	Mar 24 02:47:16 PM PDT 24
Peak memory	200188 kb
Host	smart-217c7303-958b-4d81-89fe-2cb5a88f42b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897774420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2897774420
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.2348036660
Short name	T153
Test name
Test status
Simulation time	99186708885 ps
CPU time	336.34 seconds
Started	Mar 24 02:47:45 PM PDT 24
Finished	Mar 24 02:53:21 PM PDT 24
Peak memory	200188 kb
Host	smart-cc8af21d-f7be-4d72-aad1-00a39c307cd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348036660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2348036660
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.762108261
Short name	T12
Test name
Test status
Simulation time	21827368610 ps
CPU time	35.77 seconds
Started	Mar 24 02:47:31 PM PDT 24
Finished	Mar 24 02:48:07 PM PDT 24
Peak memory	200140 kb
Host	smart-24fa0332-8e9b-4d6b-b96e-c9c84e3beb1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762108261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.762108261
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.2910987631
Short name	T305
Test name
Test status
Simulation time	60495225732 ps
CPU time	34.99 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:43:57 PM PDT 24
Peak memory	200108 kb
Host	smart-ac459044-0de5-41c2-9f03-ddf80e571b8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910987631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2910987631
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_stress_all_with_rand_reset.1302028908
Short name	T35
Test name
Test status
Simulation time	73299196984 ps
CPU time	566.83 seconds
Started	Mar 24 02:45:33 PM PDT 24
Finished	Mar 24 02:55:01 PM PDT 24
Peak memory	216688 kb
Host	smart-d10575f8-a476-4a46-b935-b6725fd9ea37
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302028908 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1302028908
Directory	/workspace/42.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1469689737
Short name	T74
Test name
Test status
Simulation time	56817022 ps
CPU time	2.13 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	197604 kb
Host	smart-11ad872f-2398-4300-897d-18a7cb735572
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469689737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1469689737
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.2421511167
Short name	T157
Test name
Test status
Simulation time	209906963487 ps
CPU time	123.46 seconds
Started	Mar 24 02:47:27 PM PDT 24
Finished	Mar 24 02:49:30 PM PDT 24
Peak memory	200080 kb
Host	smart-6a96dad7-d76c-42b1-93b6-e857c06dd61a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421511167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2421511167
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_stress_all.3220023487
Short name	T200
Test name
Test status
Simulation time	115348870476 ps
CPU time	67.9 seconds
Started	Mar 24 02:45:11 PM PDT 24
Finished	Mar 24 02:46:19 PM PDT 24
Peak memory	200136 kb
Host	smart-3c5701c5-0c5e-4a6a-8a0a-7773c8774066
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220023487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3220023487
Directory	/workspace/37.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.2146330827
Short name	T151
Test name
Test status
Simulation time	88116193023 ps
CPU time	153.4 seconds
Started	Mar 24 02:45:38 PM PDT 24
Finished	Mar 24 02:48:12 PM PDT 24
Peak memory	200108 kb
Host	smart-f0739aaf-2ef0-4695-954e-926217ce5d13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146330827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2146330827
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_stress_all.486959088
Short name	T128
Test name
Test status
Simulation time	150582390254 ps
CPU time	450.37 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:50:54 PM PDT 24
Peak memory	200168 kb
Host	smart-7d438098-59c5-4532-a31c-5bcd0e624d4d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486959088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.486959088
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.11015170
Short name	T263
Test name
Test status
Simulation time	85535692322 ps
CPU time	168.43 seconds
Started	Mar 24 02:46:27 PM PDT 24
Finished	Mar 24 02:49:16 PM PDT 24
Peak memory	200388 kb
Host	smart-7ab63c43-216d-4d34-bdda-ba7b1812fbe4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11015170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.11015170
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.1560043070
Short name	T167
Test name
Test status
Simulation time	64569898981 ps
CPU time	31.43 seconds
Started	Mar 24 02:47:39 PM PDT 24
Finished	Mar 24 02:48:10 PM PDT 24
Peak memory	200164 kb
Host	smart-84f8dda9-09ef-4dcf-80b4-961811a77825
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560043070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1560043070
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_stress_all.1264715842
Short name	T330
Test name
Test status
Simulation time	200700662482 ps
CPU time	323.65 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:48:58 PM PDT 24
Peak memory	200140 kb
Host	smart-c28ccf43-c195-44e7-9617-0b4451d6c5a4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264715842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1264715842
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.2358660337
Short name	T159
Test name
Test status
Simulation time	54819343634 ps
CPU time	24.99 seconds
Started	Mar 24 02:46:59 PM PDT 24
Finished	Mar 24 02:47:25 PM PDT 24
Peak memory	200112 kb
Host	smart-cb925f52-fd76-4385-be2c-ee2e8d286f72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2358660337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2358660337
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.2783948899
Short name	T1073
Test name
Test status
Simulation time	223923341222 ps
CPU time	43.76 seconds
Started	Mar 24 02:47:29 PM PDT 24
Finished	Mar 24 02:48:13 PM PDT 24
Peak memory	200140 kb
Host	smart-07b4b92e-b261-4de4-8231-3679348fc155
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783948899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2783948899
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_stress_all_with_rand_reset.146303716
Short name	T178
Test name
Test status
Simulation time	110494760015 ps
CPU time	378.82 seconds
Started	Mar 24 02:44:58 PM PDT 24
Finished	Mar 24 02:51:17 PM PDT 24
Peak memory	216688 kb
Host	smart-22cc2d46-c35d-4d93-bff1-1854befa5d99
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146303716 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.146303716
Directory	/workspace/34.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.uart_stress_all.3242672400
Short name	T222
Test name
Test status
Simulation time	272934287782 ps
CPU time	722.42 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:58:12 PM PDT 24
Peak memory	208332 kb
Host	smart-74d2ef35-743a-4dc9-94bb-24c1552aa0f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242672400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3242672400
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.3134298115
Short name	T1
Test name
Test status
Simulation time	128834540219 ps
CPU time	48.07 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	199800 kb
Host	smart-511c6025-655b-48da-8e99-6c20269e28d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134298115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3134298115
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.2499979562
Short name	T152
Test name
Test status
Simulation time	34657136005 ps
CPU time	14.72 seconds
Started	Mar 24 02:44:08 PM PDT 24
Finished	Mar 24 02:44:23 PM PDT 24
Peak memory	200076 kb
Host	smart-07370d29-2bed-4548-b220-fc60b49fb41e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499979562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2499979562
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.115743401
Short name	T81
Test name
Test status
Simulation time	41691957135 ps
CPU time	14.22 seconds
Started	Mar 24 02:47:27 PM PDT 24
Finished	Mar 24 02:47:41 PM PDT 24
Peak memory	200088 kb
Host	smart-7a1b9df9-a4d2-47e8-95af-1aaf52dc245e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115743401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.115743401
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_stress_all.3997512724
Short name	T485
Test name
Test status
Simulation time	406706482933 ps
CPU time	714.57 seconds
Started	Mar 24 02:44:23 PM PDT 24
Finished	Mar 24 02:56:18 PM PDT 24
Peak memory	200136 kb
Host	smart-f01b7e2f-ee2c-42e3-a38e-12d52b126717
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997512724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3997512724
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.2330204380
Short name	T82
Test name
Test status
Simulation time	31802458525 ps
CPU time	31.7 seconds
Started	Mar 24 02:46:38 PM PDT 24
Finished	Mar 24 02:47:10 PM PDT 24
Peak memory	200192 kb
Host	smart-c9034940-05ce-41dc-aa5c-fcce3e26a268
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330204380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2330204380
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.555818095
Short name	T233
Test name
Test status
Simulation time	210053735563 ps
CPU time	93.3 seconds
Started	Mar 24 02:46:52 PM PDT 24
Finished	Mar 24 02:48:26 PM PDT 24
Peak memory	200120 kb
Host	smart-55caabdd-2fed-4469-8feb-85c5b76b759c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555818095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.555818095
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.1699237394
Short name	T398
Test name
Test status
Simulation time	32309394615 ps
CPU time	57.9 seconds
Started	Mar 24 02:47:00 PM PDT 24
Finished	Mar 24 02:47:58 PM PDT 24
Peak memory	200120 kb
Host	smart-3b38577e-87b6-49f0-8333-25de7a58a277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699237394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1699237394
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.3900566956
Short name	T203
Test name
Test status
Simulation time	34759825115 ps
CPU time	13.83 seconds
Started	Mar 24 02:47:54 PM PDT 24
Finished	Mar 24 02:48:08 PM PDT 24
Peak memory	198832 kb
Host	smart-535c4efe-4abb-4374-8d4e-3d7ebb3f1c4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900566956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3900566956
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_stress_all.2425543132
Short name	T118
Test name
Test status
Simulation time	239122494233 ps
CPU time	814.38 seconds
Started	Mar 24 02:45:18 PM PDT 24
Finished	Mar 24 02:58:53 PM PDT 24
Peak memory	216088 kb
Host	smart-62a69142-6f30-44ee-8039-782ed207a1e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425543132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2425543132
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.3105261406
Short name	T225
Test name
Test status
Simulation time	99817512293 ps
CPU time	176.32 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:49:35 PM PDT 24
Peak memory	200168 kb
Host	smart-2241a091-d63f-4a4f-aca8-da58b4d0c09c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105261406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3105261406
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.2888425246
Short name	T220
Test name
Test status
Simulation time	43066370892 ps
CPU time	71.09 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:47:55 PM PDT 24
Peak memory	200156 kb
Host	smart-164c00e4-e258-4835-9b94-d659fcb3a779
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2888425246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2888425246
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.3858763604
Short name	T53
Test name
Test status
Simulation time	105531870403 ps
CPU time	161.03 seconds
Started	Mar 24 02:46:43 PM PDT 24
Finished	Mar 24 02:49:24 PM PDT 24
Peak memory	200180 kb
Host	smart-aed2dcf0-391f-47ce-805b-3960938c2fa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3858763604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3858763604
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.3465682450
Short name	T229
Test name
Test status
Simulation time	437357239377 ps
CPU time	41.9 seconds
Started	Mar 24 02:47:04 PM PDT 24
Finished	Mar 24 02:47:46 PM PDT 24
Peak memory	200204 kb
Host	smart-42c3bdab-b68d-4bb4-85de-9862b866a802
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465682450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3465682450
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.3022002517
Short name	T186
Test name
Test status
Simulation time	135583931882 ps
CPU time	20.65 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:33 PM PDT 24
Peak memory	200112 kb
Host	smart-5e68be80-6cc8-48a8-b798-2c6d7502b589
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022002517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3022002517
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.687345786
Short name	T355
Test name
Test status
Simulation time	35037708327 ps
CPU time	25.94 seconds
Started	Mar 24 02:47:38 PM PDT 24
Finished	Mar 24 02:48:04 PM PDT 24
Peak memory	200184 kb
Host	smart-d7e22236-5bcf-4433-a50e-a7cb49bb9049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687345786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.687345786
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.3124561283
Short name	T183
Test name
Test status
Simulation time	55492712633 ps
CPU time	23.35 seconds
Started	Mar 24 02:44:27 PM PDT 24
Finished	Mar 24 02:44:51 PM PDT 24
Peak memory	200204 kb
Host	smart-af9b5770-0a33-4057-a0d5-f4e83df175e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124561283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3124561283
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.1483304487
Short name	T797
Test name
Test status
Simulation time	88292803825 ps
CPU time	42.13 seconds
Started	Mar 24 02:44:42 PM PDT 24
Finished	Mar 24 02:45:26 PM PDT 24
Peak memory	200132 kb
Host	smart-471b0a9b-01cd-4b1c-86c8-3fcb66c1209b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483304487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1483304487
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.2566865130
Short name	T240
Test name
Test status
Simulation time	17383903135 ps
CPU time	22.49 seconds
Started	Mar 24 02:46:17 PM PDT 24
Finished	Mar 24 02:46:40 PM PDT 24
Peak memory	200192 kb
Host	smart-ae3acb94-3eb2-4071-8737-772078a7ad9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566865130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2566865130
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.2223408615
Short name	T169
Test name
Test status
Simulation time	285258214374 ps
CPU time	53.99 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:47:09 PM PDT 24
Peak memory	199992 kb
Host	smart-efb6156e-4196-4348-b7a7-fc15be5efd5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223408615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2223408615
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.2414032181
Short name	T249
Test name
Test status
Simulation time	143184538671 ps
CPU time	144.39 seconds
Started	Mar 24 02:46:19 PM PDT 24
Finished	Mar 24 02:48:44 PM PDT 24
Peak memory	200148 kb
Host	smart-841aecfa-39f9-4758-bdbb-73b9321b039f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2414032181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2414032181
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.820622492
Short name	T125
Test name
Test status
Simulation time	401094922 ps
CPU time	1.33 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:01 PM PDT 24
Peak memory	199892 kb
Host	smart-3d8a04ae-a6a6-43be-a658-2a802ff6c0e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820622492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.820622492
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.744947028
Short name	T103
Test name
Test status
Simulation time	194442202 ps
CPU time	0.94 seconds
Started	Mar 24 12:39:54 PM PDT 24
Finished	Mar 24 12:40:00 PM PDT 24
Peak memory	199304 kb
Host	smart-2d60d7fa-31ea-406f-8381-c79482cae317
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744947028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.744947028
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.1035813460
Short name	T223
Test name
Test status
Simulation time	124149578786 ps
CPU time	14.5 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:43:46 PM PDT 24
Peak memory	200144 kb
Host	smart-06818266-b183-40d6-ac2b-68c8fbe9faf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035813460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1035813460
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.1407856551
Short name	T210
Test name
Test status
Simulation time	19409908651 ps
CPU time	17.77 seconds
Started	Mar 24 02:46:38 PM PDT 24
Finished	Mar 24 02:46:56 PM PDT 24
Peak memory	200040 kb
Host	smart-9698e604-a8c1-42d2-9388-e4a2d57c370c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407856551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1407856551
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.3648831806
Short name	T255
Test name
Test status
Simulation time	76880623413 ps
CPU time	114.87 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:48:40 PM PDT 24
Peak memory	200140 kb
Host	smart-22444f2c-8195-457a-a1c4-75b65b5fd52d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648831806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3648831806
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.21742138
Short name	T245
Test name
Test status
Simulation time	112423247981 ps
CPU time	88.92 seconds
Started	Mar 24 02:46:45 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200076 kb
Host	smart-d3741de5-66d9-4490-93cf-db5b3f3ad1a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21742138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.21742138
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.1459462085
Short name	T260
Test name
Test status
Simulation time	109956238635 ps
CPU time	47.62 seconds
Started	Mar 24 02:46:43 PM PDT 24
Finished	Mar 24 02:47:31 PM PDT 24
Peak memory	200336 kb
Host	smart-afe625a9-927c-49e9-a9fa-6439a9899244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459462085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1459462085
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.1750622611
Short name	T161
Test name
Test status
Simulation time	144836682106 ps
CPU time	210.27 seconds
Started	Mar 24 02:46:47 PM PDT 24
Finished	Mar 24 02:50:17 PM PDT 24
Peak memory	200204 kb
Host	smart-077225d2-478e-4ec8-b31a-25fceb2c62e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750622611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1750622611
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.4057154823
Short name	T246
Test name
Test status
Simulation time	17256907633 ps
CPU time	27.47 seconds
Started	Mar 24 02:46:45 PM PDT 24
Finished	Mar 24 02:47:13 PM PDT 24
Peak memory	200176 kb
Host	smart-bb086a8f-e160-44e4-8e97-468f014e7eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057154823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4057154823
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.1242156951
Short name	T142
Test name
Test status
Simulation time	118517887681 ps
CPU time	97.49 seconds
Started	Mar 24 02:46:55 PM PDT 24
Finished	Mar 24 02:48:34 PM PDT 24
Peak memory	200172 kb
Host	smart-e7054398-4eb4-4bc2-b4cf-059cb2de4adc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242156951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1242156951
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.2523322700
Short name	T196
Test name
Test status
Simulation time	54456244318 ps
CPU time	85.2 seconds
Started	Mar 24 02:46:49 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200048 kb
Host	smart-d1c166aa-edb2-4aa1-ac42-1b6fa7095637
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523322700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2523322700
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.1022482952
Short name	T261
Test name
Test status
Simulation time	183210975899 ps
CPU time	211.45 seconds
Started	Mar 24 02:46:55 PM PDT 24
Finished	Mar 24 02:50:28 PM PDT 24
Peak memory	200168 kb
Host	smart-34e5fac2-1dd9-45d2-936f-34254757e0a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022482952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1022482952
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.520633299
Short name	T47
Test name
Test status
Simulation time	107283750586 ps
CPU time	86.3 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:45:33 PM PDT 24
Peak memory	200144 kb
Host	smart-6c526312-11de-4fde-86cb-0b0be918f942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520633299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.520633299
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_reset.2138489482
Short name	T242
Test name
Test status
Simulation time	51913475902 ps
CPU time	122.04 seconds
Started	Mar 24 02:43:56 PM PDT 24
Finished	Mar 24 02:45:58 PM PDT 24
Peak memory	200192 kb
Host	smart-11be473e-35e5-4eaa-9d65-d1a89d2c5a4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138489482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2138489482
Directory	/workspace/17.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_stress_all_with_rand_reset.2743258480
Short name	T67
Test name
Test status
Simulation time	135353385296 ps
CPU time	909.15 seconds
Started	Mar 24 02:44:13 PM PDT 24
Finished	Mar 24 02:59:22 PM PDT 24
Peak memory	225036 kb
Host	smart-be57bf36-8e72-4851-ab05-b036c3fc74dd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743258480 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2743258480
Directory	/workspace/18.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.2330305069
Short name	T56
Test name
Test status
Simulation time	21043029291 ps
CPU time	40.3 seconds
Started	Mar 24 02:44:02 PM PDT 24
Finished	Mar 24 02:44:43 PM PDT 24
Peak memory	200092 kb
Host	smart-3d36906d-5f01-4056-bbf9-2c5c0fd4f0b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330305069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2330305069
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.1294881155
Short name	T259
Test name
Test status
Simulation time	67382379669 ps
CPU time	17.37 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:44:28 PM PDT 24
Peak memory	200104 kb
Host	smart-1adb2d9e-3fa8-45df-ad51-4e6557a2e81b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294881155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1294881155
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_stress_all_with_rand_reset.1670965102
Short name	T114
Test name
Test status
Simulation time	91779577638 ps
CPU time	445.41 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:51:36 PM PDT 24
Peak memory	216740 kb
Host	smart-a89e8475-d1d1-4280-bec8-fbbde128bf28
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670965102 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1670965102
Directory	/workspace/19.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.1000384884
Short name	T256
Test name
Test status
Simulation time	119809285131 ps
CPU time	58.28 seconds
Started	Mar 24 02:47:21 PM PDT 24
Finished	Mar 24 02:48:20 PM PDT 24
Peak memory	200084 kb
Host	smart-09ab3e5f-7eba-4cae-9b71-bb817b8d0169
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000384884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1000384884
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.1800446947
Short name	T251
Test name
Test status
Simulation time	99586628668 ps
CPU time	81.65 seconds
Started	Mar 24 02:47:22 PM PDT 24
Finished	Mar 24 02:48:44 PM PDT 24
Peak memory	200060 kb
Host	smart-cdacd20b-b255-42a5-bc48-0d2497dfa9bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800446947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1800446947
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.2985074662
Short name	T253
Test name
Test status
Simulation time	142148003373 ps
CPU time	198.13 seconds
Started	Mar 24 02:47:26 PM PDT 24
Finished	Mar 24 02:50:45 PM PDT 24
Peak memory	200044 kb
Host	smart-2481dd58-7b46-4076-a297-271665d5cae4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985074662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2985074662
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.1609461161
Short name	T237
Test name
Test status
Simulation time	97419252861 ps
CPU time	188.33 seconds
Started	Mar 24 02:47:27 PM PDT 24
Finished	Mar 24 02:50:35 PM PDT 24
Peak memory	200144 kb
Host	smart-d00335ad-ce21-4b29-9f18-f7417f307cff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609461161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1609461161
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.4112039352
Short name	T218
Test name
Test status
Simulation time	23418253631 ps
CPU time	10.71 seconds
Started	Mar 24 02:47:53 PM PDT 24
Finished	Mar 24 02:48:04 PM PDT 24
Peak memory	200064 kb
Host	smart-0d43a9d7-9695-4cce-b27c-8427b220c4b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112039352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4112039352
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.1818703308
Short name	T248
Test name
Test status
Simulation time	122170785486 ps
CPU time	17 seconds
Started	Mar 24 02:47:57 PM PDT 24
Finished	Mar 24 02:48:15 PM PDT 24
Peak memory	200048 kb
Host	smart-64c0a136-ae53-4cc7-b869-2f19f62248f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818703308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1818703308
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.3984123831
Short name	T16
Test name
Test status
Simulation time	99364375290 ps
CPU time	159.77 seconds
Started	Mar 24 02:45:32 PM PDT 24
Finished	Mar 24 02:48:12 PM PDT 24
Peak memory	200076 kb
Host	smart-ad097e8c-8621-420b-abe9-e0dcdfb8fc46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984123831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3984123831
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.2197703750
Short name	T254
Test name
Test status
Simulation time	111636286512 ps
CPU time	90.19 seconds
Started	Mar 24 02:46:12 PM PDT 24
Finished	Mar 24 02:47:42 PM PDT 24
Peak memory	200100 kb
Host	smart-f1f65158-e720-4563-8e39-7983cd651c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197703750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2197703750
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_stress_all_with_rand_reset.3658810450
Short name	T117
Test name
Test status
Simulation time	31019475948 ps
CPU time	151.88 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:48:47 PM PDT 24
Peak memory	216808 kb
Host	smart-d38739a2-bf70-4296-9d51-c3ccf28a2a4c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658810450 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3658810450
Directory	/workspace/62.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1155584667
Short name	T1247
Test name
Test status
Simulation time	24679017 ps
CPU time	0.68 seconds
Started	Mar 24 12:39:40 PM PDT 24
Finished	Mar 24 12:39:41 PM PDT 24
Peak memory	195924 kb
Host	smart-4389d1ad-008f-41b0-ba4f-45a8c7104ea1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155584667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1155584667
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2761558978
Short name	T88
Test name
Test status
Simulation time	108940932 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	195680 kb
Host	smart-8cc0fac7-480f-4f7c-9635-e457dae83f86
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761558978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2761558978
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3110134395
Short name	T1156
Test name
Test status
Simulation time	49075656 ps
CPU time	0.78 seconds
Started	Mar 24 12:39:44 PM PDT 24
Finished	Mar 24 12:39:45 PM PDT 24
Peak memory	198640 kb
Host	smart-911a4d69-cc0a-48d2-9398-471972758c4a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110134395 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3110134395
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.2437262604
Short name	T75
Test name
Test status
Simulation time	15235190 ps
CPU time	0.59 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	195712 kb
Host	smart-d24ab521-0612-480f-bade-39fa9fa42ae6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437262604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2437262604
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.2384247513
Short name	T1135
Test name
Test status
Simulation time	13773750 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:45 PM PDT 24
Finished	Mar 24 12:39:46 PM PDT 24
Peak memory	194696 kb
Host	smart-d247387d-08f3-467c-b38e-9397f413159e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384247513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2384247513
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1505741698
Short name	T91
Test name
Test status
Simulation time	48328908 ps
CPU time	0.72 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:51 PM PDT 24
Peak memory	197456 kb
Host	smart-7ee384f3-0f64-488e-bfdf-7a256b71917c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505741698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.1505741698
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.2604390260
Short name	T1222
Test name
Test status
Simulation time	155655115 ps
CPU time	1.76 seconds
Started	Mar 24 12:39:47 PM PDT 24
Finished	Mar 24 12:39:49 PM PDT 24
Peak memory	200320 kb
Host	smart-f1d9a4c8-fab6-440e-8bbf-f1d8809e9e70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604390260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2604390260
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.278055384
Short name	T1257
Test name
Test status
Simulation time	58243547 ps
CPU time	0.99 seconds
Started	Mar 24 12:39:35 PM PDT 24
Finished	Mar 24 12:39:36 PM PDT 24
Peak memory	199072 kb
Host	smart-9188c2d8-8fa4-435a-8b6f-22abd258b08d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278055384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.278055384
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3338860800
Short name	T87
Test name
Test status
Simulation time	41490656 ps
CPU time	0.74 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	196592 kb
Host	smart-c15bad0a-27bd-4f36-86c6-2902f0694dd8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338860800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3338860800
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1857788151
Short name	T1159
Test name
Test status
Simulation time	36795470 ps
CPU time	1.43 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	198104 kb
Host	smart-86c72b81-f187-47b0-b4c8-e6155087dd20
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857788151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1857788151
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.577997112
Short name	T1154
Test name
Test status
Simulation time	20379527 ps
CPU time	0.6 seconds
Started	Mar 24 12:39:45 PM PDT 24
Finished	Mar 24 12:39:46 PM PDT 24
Peak memory	195684 kb
Host	smart-7fce8ce9-a06a-473f-88fd-d8de6c049b9e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577997112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.577997112
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1637617818
Short name	T1187
Test name
Test status
Simulation time	92933162 ps
CPU time	0.79 seconds
Started	Mar 24 12:39:46 PM PDT 24
Finished	Mar 24 12:39:47 PM PDT 24
Peak memory	199348 kb
Host	smart-84ca9c71-5ff3-48bc-b1fd-ba07e34dd5e0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637617818 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1637617818
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.2023234296
Short name	T1210
Test name
Test status
Simulation time	50650301 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:00 PM PDT 24
Peak memory	196008 kb
Host	smart-84cb5dc1-f7cc-44b9-be3e-af7dbddbf2f6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023234296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2023234296
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.3717062541
Short name	T1233
Test name
Test status
Simulation time	12692250 ps
CPU time	0.56 seconds
Started	Mar 24 12:39:41 PM PDT 24
Finished	Mar 24 12:39:41 PM PDT 24
Peak memory	194580 kb
Host	smart-70c465f0-03b2-40a9-92b4-d0ed41c0569e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717062541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3717062541
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1838802485
Short name	T95
Test name
Test status
Simulation time	23387961 ps
CPU time	0.64 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:01 PM PDT 24
Peak memory	196112 kb
Host	smart-25c1457b-42ad-47d4-b036-1a08aec0654c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838802485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.1838802485
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.3754561091
Short name	T1142
Test name
Test status
Simulation time	116469071 ps
CPU time	1.32 seconds
Started	Mar 24 12:39:59 PM PDT 24
Finished	Mar 24 12:40:01 PM PDT 24
Peak memory	200336 kb
Host	smart-57a07b40-899f-4eb3-912c-ce20053e79e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754561091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3754561091
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2263103098
Short name	T1195
Test name
Test status
Simulation time	47253489 ps
CPU time	0.93 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:51 PM PDT 24
Peak memory	199256 kb
Host	smart-3bd1f0bc-b8e8-46cd-9a69-ff46b9f6e32b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263103098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2263103098
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1558590801
Short name	T1173
Test name
Test status
Simulation time	34231933 ps
CPU time	0.94 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	200140 kb
Host	smart-a6d4c984-af68-43dd-89bf-fd60d07b9f61
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558590801 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1558590801
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.3959834601
Short name	T97
Test name
Test status
Simulation time	15109128 ps
CPU time	0.65 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	195744 kb
Host	smart-a42b61f3-7906-4c58-964b-a168df870841
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959834601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3959834601
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.1784907449
Short name	T1134
Test name
Test status
Simulation time	30654863 ps
CPU time	0.59 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	194572 kb
Host	smart-a9716489-d713-4bd2-b13f-5338a22b9756
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784907449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1784907449
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2419710249
Short name	T1184
Test name
Test status
Simulation time	86964239 ps
CPU time	0.75 seconds
Started	Mar 24 12:39:59 PM PDT 24
Finished	Mar 24 12:40:00 PM PDT 24
Peak memory	196920 kb
Host	smart-5090b7e6-061a-4a4d-9148-cce2ce7ed5de
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419710249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.2419710249
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.921921293
Short name	T1133
Test name
Test status
Simulation time	74906738 ps
CPU time	1.5 seconds
Started	Mar 24 12:39:56 PM PDT 24
Finished	Mar 24 12:39:57 PM PDT 24
Peak memory	200228 kb
Host	smart-2591b8ac-f6d1-4a66-ad09-74a66ad5594d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921921293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.921921293
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3449985037
Short name	T1214
Test name
Test status
Simulation time	576099518 ps
CPU time	0.96 seconds
Started	Mar 24 12:40:01 PM PDT 24
Finished	Mar 24 12:40:02 PM PDT 24
Peak memory	199408 kb
Host	smart-1bf7be05-aec9-44a6-9fe2-c8af9b48b92f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449985037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3449985037
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2488876390
Short name	T1245
Test name
Test status
Simulation time	258822929 ps
CPU time	0.74 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:54 PM PDT 24
Peak memory	198624 kb
Host	smart-ad2c2149-ae91-4b8d-b5c1-35d5301ac48c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488876390 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2488876390
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.2698631574
Short name	T99
Test name
Test status
Simulation time	14425289 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:03 PM PDT 24
Peak memory	195716 kb
Host	smart-441adcc7-1c3e-4763-ae2f-6367f5f2e0ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698631574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2698631574
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.1089840819
Short name	T1229
Test name
Test status
Simulation time	14062359 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:03 PM PDT 24
Peak memory	194688 kb
Host	smart-19bc2a32-d54a-4eaf-9f8d-f8be450ad432
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089840819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1089840819
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.65981662
Short name	T1204
Test name
Test status
Simulation time	122911658 ps
CPU time	0.81 seconds
Started	Mar 24 12:40:04 PM PDT 24
Finished	Mar 24 12:40:05 PM PDT 24
Peak memory	197508 kb
Host	smart-deb373f0-324a-449b-b4c1-ed3c6957c07b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65981662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_ outstanding.65981662
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.49189380
Short name	T1157
Test name
Test status
Simulation time	64022006 ps
CPU time	1.47 seconds
Started	Mar 24 12:40:10 PM PDT 24
Finished	Mar 24 12:40:11 PM PDT 24
Peak memory	200304 kb
Host	smart-a6ea6985-38e4-4d82-b363-74e7791f8a47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49189380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.49189380
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3448910225
Short name	T1193
Test name
Test status
Simulation time	240667903 ps
CPU time	0.83 seconds
Started	Mar 24 12:39:47 PM PDT 24
Finished	Mar 24 12:39:48 PM PDT 24
Peak memory	200200 kb
Host	smart-c1dedb43-5925-42f8-9e32-2097988cb10e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448910225 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3448910225
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.118613166
Short name	T1171
Test name
Test status
Simulation time	17553171 ps
CPU time	0.61 seconds
Started	Mar 24 12:39:54 PM PDT 24
Finished	Mar 24 12:39:55 PM PDT 24
Peak memory	195816 kb
Host	smart-3269c9a7-84cc-4e61-93f7-24b8dfffa2ea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118613166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.118613166
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.849342773
Short name	T1176
Test name
Test status
Simulation time	41938204 ps
CPU time	0.59 seconds
Started	Mar 24 12:39:54 PM PDT 24
Finished	Mar 24 12:39:54 PM PDT 24
Peak memory	194568 kb
Host	smart-513d2893-b972-422e-a743-14b2104ce0a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849342773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.849342773
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3666100312
Short name	T96
Test name
Test status
Simulation time	32515677 ps
CPU time	0.73 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	196920 kb
Host	smart-aa0a7185-743d-4245-a23d-f502e2e58a5a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666100312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.3666100312
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.657997529
Short name	T1139
Test name
Test status
Simulation time	839295372 ps
CPU time	1.44 seconds
Started	Mar 24 12:40:11 PM PDT 24
Finished	Mar 24 12:40:12 PM PDT 24
Peak memory	200280 kb
Host	smart-cba5b2f1-d2a5-49bd-a042-2c1920e55699
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657997529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.657997529
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1795188712
Short name	T1178
Test name
Test status
Simulation time	214072070 ps
CPU time	0.95 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	199244 kb
Host	smart-a34e54b5-cb9d-4540-9e74-9d94dabd4d86
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795188712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1795188712
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2491820791
Short name	T1192
Test name
Test status
Simulation time	59428180 ps
CPU time	0.87 seconds
Started	Mar 24 12:40:01 PM PDT 24
Finished	Mar 24 12:40:02 PM PDT 24
Peak memory	200104 kb
Host	smart-772aa8f4-02b2-46a9-87a6-c7aa91a8f0bf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491820791 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2491820791
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.286541318
Short name	T90
Test name
Test status
Simulation time	63706891 ps
CPU time	0.61 seconds
Started	Mar 24 12:40:24 PM PDT 24
Finished	Mar 24 12:40:25 PM PDT 24
Peak memory	195644 kb
Host	smart-a2579601-9833-4fe4-bea7-0f0c8984b8ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286541318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.286541318
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.3372331961
Short name	T1232
Test name
Test status
Simulation time	13723605 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:15 PM PDT 24
Finished	Mar 24 12:40:16 PM PDT 24
Peak memory	194660 kb
Host	smart-ebad37df-f3da-4ebf-aa2c-bda8fda806bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372331961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3372331961
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3190366156
Short name	T1212
Test name
Test status
Simulation time	67522347 ps
CPU time	0.72 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:59 PM PDT 24
Peak memory	197436 kb
Host	smart-426ce555-b2b8-4bab-ab03-a43f037dacbc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190366156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.3190366156
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.4024457069
Short name	T1248
Test name
Test status
Simulation time	171393760 ps
CPU time	1.24 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	200244 kb
Host	smart-992f49d7-0ac1-4a3c-913c-c03262b7e438
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024457069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4024457069
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.731362228
Short name	T102
Test name
Test status
Simulation time	161289704 ps
CPU time	1.31 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:02 PM PDT 24
Peak memory	200004 kb
Host	smart-ee33d8ab-2760-4a20-be13-b1013b0f0da3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731362228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.731362228
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1293769379
Short name	T1146
Test name
Test status
Simulation time	20680242 ps
CPU time	0.85 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:03 PM PDT 24
Peak memory	199076 kb
Host	smart-56a52277-eae7-458b-96b8-bf3750c3c01e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293769379 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1293769379
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.622771104
Short name	T1161
Test name
Test status
Simulation time	30268610 ps
CPU time	0.57 seconds
Started	Mar 24 12:40:12 PM PDT 24
Finished	Mar 24 12:40:12 PM PDT 24
Peak memory	195652 kb
Host	smart-5f900284-bdd1-4252-84d2-837499bd1ef6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622771104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.622771104
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.1609283268
Short name	T1215
Test name
Test status
Simulation time	18170967 ps
CPU time	0.54 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	194640 kb
Host	smart-0456deb6-8906-46d6-b9ef-1edaf8bd486f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609283268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1609283268
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3870966281
Short name	T93
Test name
Test status
Simulation time	248594920 ps
CPU time	0.66 seconds
Started	Mar 24 12:40:07 PM PDT 24
Finished	Mar 24 12:40:07 PM PDT 24
Peak memory	196992 kb
Host	smart-f3003016-626f-4583-afeb-5421b9c2fa71
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870966281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.3870966281
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.1481314103
Short name	T1182
Test name
Test status
Simulation time	193552756 ps
CPU time	1.8 seconds
Started	Mar 24 12:40:18 PM PDT 24
Finished	Mar 24 12:40:20 PM PDT 24
Peak memory	200296 kb
Host	smart-958222f6-3d40-444a-8ae4-0e297056f0ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481314103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1481314103
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1887208085
Short name	T1226
Test name
Test status
Simulation time	128243978 ps
CPU time	0.95 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	200148 kb
Host	smart-b1296ff6-6978-49f6-911e-19476ba48d40
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887208085 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1887208085
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.2877131099
Short name	T1143
Test name
Test status
Simulation time	44062063 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:15 PM PDT 24
Finished	Mar 24 12:40:15 PM PDT 24
Peak memory	195624 kb
Host	smart-7f7671b7-e29b-4a0a-bd4d-a5bd17c0588c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877131099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2877131099
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.1959368259
Short name	T1207
Test name
Test status
Simulation time	30042392 ps
CPU time	0.57 seconds
Started	Mar 24 12:40:10 PM PDT 24
Finished	Mar 24 12:40:11 PM PDT 24
Peak memory	194592 kb
Host	smart-759741d2-d40d-43e1-9dc8-70c3b0f00dbb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959368259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1959368259
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1054686011
Short name	T92
Test name
Test status
Simulation time	48355245 ps
CPU time	0.6 seconds
Started	Mar 24 12:40:16 PM PDT 24
Finished	Mar 24 12:40:16 PM PDT 24
Peak memory	195768 kb
Host	smart-ccbade2f-8cd5-4428-888d-07a7e239f48e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054686011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.1054686011
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.3618225977
Short name	T1148
Test name
Test status
Simulation time	129319839 ps
CPU time	2.11 seconds
Started	Mar 24 12:39:56 PM PDT 24
Finished	Mar 24 12:39:58 PM PDT 24
Peak memory	200328 kb
Host	smart-8b5f2d98-45b1-4388-b447-f4979ff1e082
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618225977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3618225977
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3231704455
Short name	T1205
Test name
Test status
Simulation time	52318346 ps
CPU time	0.97 seconds
Started	Mar 24 12:39:42 PM PDT 24
Finished	Mar 24 12:39:43 PM PDT 24
Peak memory	199168 kb
Host	smart-0493b425-1299-4d2d-a527-91cf9dca3028
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231704455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3231704455
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4212047493
Short name	T1149
Test name
Test status
Simulation time	108763171 ps
CPU time	0.67 seconds
Started	Mar 24 12:40:06 PM PDT 24
Finished	Mar 24 12:40:07 PM PDT 24
Peak memory	197972 kb
Host	smart-2a691eaf-04f3-4dc2-8617-b643906a5dd2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212047493 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4212047493
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.3324970693
Short name	T1256
Test name
Test status
Simulation time	15745713 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:08 PM PDT 24
Finished	Mar 24 12:40:09 PM PDT 24
Peak memory	195808 kb
Host	smart-7e847cb6-3cd2-4f0f-9276-5d2bc2a6dfa9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324970693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3324970693
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.3896140677
Short name	T1239
Test name
Test status
Simulation time	12662257 ps
CPU time	0.57 seconds
Started	Mar 24 12:39:46 PM PDT 24
Finished	Mar 24 12:39:46 PM PDT 24
Peak memory	194604 kb
Host	smart-c7390006-b8fa-490b-ae9b-a7c7fe62b42e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896140677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3896140677
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2680197977
Short name	T1189
Test name
Test status
Simulation time	46381803 ps
CPU time	0.6 seconds
Started	Mar 24 12:40:12 PM PDT 24
Finished	Mar 24 12:40:12 PM PDT 24
Peak memory	195928 kb
Host	smart-41c6a520-cb31-403c-acf5-752f3068db93
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680197977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.2680197977
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.1410476006
Short name	T1198
Test name
Test status
Simulation time	92579550 ps
CPU time	1.15 seconds
Started	Mar 24 12:40:21 PM PDT 24
Finished	Mar 24 12:40:22 PM PDT 24
Peak memory	200272 kb
Host	smart-54ac33d2-4213-4e36-a546-31af0b8ebf50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410476006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1410476006
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.443090414
Short name	T1228
Test name
Test status
Simulation time	91073181 ps
CPU time	1.34 seconds
Started	Mar 24 12:40:18 PM PDT 24
Finished	Mar 24 12:40:19 PM PDT 24
Peak memory	199752 kb
Host	smart-e98a16e0-41e2-40aa-b352-249d858d8cd9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443090414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.443090414
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.825677161
Short name	T1223
Test name
Test status
Simulation time	45083534 ps
CPU time	1.22 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:08 PM PDT 24
Peak memory	200404 kb
Host	smart-2907bd50-d606-47b9-97fc-a4fc3776f427
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825677161 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.825677161
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.3460495934
Short name	T1203
Test name
Test status
Simulation time	79177998 ps
CPU time	0.57 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	195704 kb
Host	smart-b36ea99d-12d9-4d85-ba33-e619ddd317e9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460495934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3460495934
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.2736124777
Short name	T1253
Test name
Test status
Simulation time	11906465 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:06 PM PDT 24
Finished	Mar 24 12:40:07 PM PDT 24
Peak memory	194648 kb
Host	smart-b6e4a409-25a9-4afa-9d24-29ce80942d5f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736124777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2736124777
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2370087174
Short name	T94
Test name
Test status
Simulation time	24982177 ps
CPU time	0.63 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:03 PM PDT 24
Peak memory	194952 kb
Host	smart-614e5ade-abe9-4a25-ace9-d258e4245e55
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370087174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.2370087174
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.1543016641
Short name	T1169
Test name
Test status
Simulation time	37660762 ps
CPU time	1.78 seconds
Started	Mar 24 12:40:12 PM PDT 24
Finished	Mar 24 12:40:19 PM PDT 24
Peak memory	200328 kb
Host	smart-85c2bfe6-c8e9-40fc-9e47-9fde3d0572a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543016641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1543016641
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4117711654
Short name	T1235
Test name
Test status
Simulation time	163327186 ps
CPU time	0.91 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:01 PM PDT 24
Peak memory	199380 kb
Host	smart-856a7c3e-2f16-4805-92d9-2f1979de7405
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117711654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4117711654
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3509619970
Short name	T1194
Test name
Test status
Simulation time	16241079 ps
CPU time	0.66 seconds
Started	Mar 24 12:40:04 PM PDT 24
Finished	Mar 24 12:40:05 PM PDT 24
Peak memory	197920 kb
Host	smart-459e41f8-c781-4952-83f7-50785c75bd16
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509619970 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3509619970
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.3674063356
Short name	T1147
Test name
Test status
Simulation time	13016495 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:06 PM PDT 24
Finished	Mar 24 12:40:07 PM PDT 24
Peak memory	194640 kb
Host	smart-c21472e7-a6b6-4a8c-b233-de4156e48ba9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674063356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3674063356
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1453391599
Short name	T1180
Test name
Test status
Simulation time	23842916 ps
CPU time	0.64 seconds
Started	Mar 24 12:39:56 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	196056 kb
Host	smart-832987d2-3164-4818-873e-09629731870f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453391599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.1453391599
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.3510785179
Short name	T1258
Test name
Test status
Simulation time	45482286 ps
CPU time	1.1 seconds
Started	Mar 24 12:40:06 PM PDT 24
Finished	Mar 24 12:40:08 PM PDT 24
Peak memory	200268 kb
Host	smart-6b19074c-d16b-441a-bc91-e31fa31a19c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510785179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3510785179
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1356110749
Short name	T1216
Test name
Test status
Simulation time	243646236 ps
CPU time	0.99 seconds
Started	Mar 24 12:40:29 PM PDT 24
Finished	Mar 24 12:40:31 PM PDT 24
Peak memory	199448 kb
Host	smart-79620b92-4d75-46a3-91a3-5514d6351f0e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356110749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1356110749
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1715121821
Short name	T1242
Test name
Test status
Simulation time	19252761 ps
CPU time	0.66 seconds
Started	Mar 24 12:40:12 PM PDT 24
Finished	Mar 24 12:40:13 PM PDT 24
Peak memory	198144 kb
Host	smart-c3db8c10-c70e-41f7-b1c3-58d8f02bfda1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715121821 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1715121821
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.1955747498
Short name	T89
Test name
Test status
Simulation time	11928048 ps
CPU time	0.61 seconds
Started	Mar 24 12:40:16 PM PDT 24
Finished	Mar 24 12:40:16 PM PDT 24
Peak memory	195984 kb
Host	smart-951070c5-a8c6-4e0e-9779-85d3b1cf0369
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955747498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1955747498
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.637524183
Short name	T1158
Test name
Test status
Simulation time	28400634 ps
CPU time	0.56 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:58 PM PDT 24
Peak memory	194688 kb
Host	smart-6b8448b0-94f0-4611-a017-fc1ce8c10f9e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637524183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.637524183
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3874249995
Short name	T1177
Test name
Test status
Simulation time	13240862 ps
CPU time	0.63 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:03 PM PDT 24
Peak memory	195844 kb
Host	smart-ecb5c9f8-6f07-4e12-ae39-2a59829187e4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874249995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.3874249995
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.275472045
Short name	T1181
Test name
Test status
Simulation time	400684718 ps
CPU time	1.92 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	200248 kb
Host	smart-3e85837b-61e1-4803-8b58-f4e6a97f5f55
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275472045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.275472045
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.152652019
Short name	T101
Test name
Test status
Simulation time	336746391 ps
CPU time	1.37 seconds
Started	Mar 24 12:40:04 PM PDT 24
Finished	Mar 24 12:40:05 PM PDT 24
Peak memory	199488 kb
Host	smart-1e8906d8-8421-476a-9961-38643df2cec9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152652019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.152652019
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3014487655
Short name	T1162
Test name
Test status
Simulation time	29612865 ps
CPU time	0.77 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:55 PM PDT 24
Peak memory	196724 kb
Host	smart-9f68855c-4565-4bda-bfa0-a04812b5d486
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014487655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3014487655
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2600469020
Short name	T1197
Test name
Test status
Simulation time	93768893 ps
CPU time	1.47 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	197536 kb
Host	smart-1ce788c0-b50d-42c8-b28f-7a4b82a19483
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600469020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2600469020
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4239672791
Short name	T1218
Test name
Test status
Simulation time	14178581 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:48 PM PDT 24
Finished	Mar 24 12:39:49 PM PDT 24
Peak memory	195680 kb
Host	smart-934ba9ce-ca85-498e-82b0-d9d7a961d6b0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239672791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4239672791
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2096449440
Short name	T1251
Test name
Test status
Simulation time	41594771 ps
CPU time	0.98 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:59 PM PDT 24
Peak memory	200224 kb
Host	smart-b5b1e802-65be-4335-9dc3-c5a2a0692a50
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096449440 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2096449440
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.12026630
Short name	T1211
Test name
Test status
Simulation time	16932982 ps
CPU time	0.64 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:07 PM PDT 24
Peak memory	196080 kb
Host	smart-72884df7-69b7-47a9-930e-06bafbe0ac25
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12026630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.12026630
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.3164097830
Short name	T1144
Test name
Test status
Simulation time	30755714 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:58 PM PDT 24
Peak memory	194652 kb
Host	smart-4fb6185f-ac1f-4309-b003-c733bc306896
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164097830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3164097830
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2617679337
Short name	T1241
Test name
Test status
Simulation time	27949738 ps
CPU time	0.81 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:54 PM PDT 24
Peak memory	197864 kb
Host	smart-8a7f9144-3804-4494-a572-e6d5ac7cd4d0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617679337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.2617679337
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.642166284
Short name	T1206
Test name
Test status
Simulation time	63018915 ps
CPU time	1.26 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:59 PM PDT 24
Peak memory	200396 kb
Host	smart-b64cb2d7-ba30-4d3a-8dc4-b7efedff51f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642166284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.642166284
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2543359067
Short name	T1213
Test name
Test status
Simulation time	104453103 ps
CPU time	0.94 seconds
Started	Mar 24 12:39:47 PM PDT 24
Finished	Mar 24 12:39:48 PM PDT 24
Peak memory	199064 kb
Host	smart-f4a6b0ae-f815-4cd2-94c5-f3c9514a61cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543359067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2543359067
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.414939646
Short name	T1172
Test name
Test status
Simulation time	38965001 ps
CPU time	0.57 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:58 PM PDT 24
Peak memory	194708 kb
Host	smart-c2f11164-f392-4e32-9485-97415f3ed4dc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414939646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.414939646
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.665417383
Short name	T1151
Test name
Test status
Simulation time	21992590 ps
CPU time	0.59 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:55 PM PDT 24
Peak memory	194684 kb
Host	smart-a23eb0b3-6295-4c8d-8cc6-552c8d271bbc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665417383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.665417383
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.511519862
Short name	T1236
Test name
Test status
Simulation time	53748840 ps
CPU time	0.55 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	194616 kb
Host	smart-d1189bc0-ba82-4a37-b687-8e359b07056a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511519862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.511519862
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.154348966
Short name	T1254
Test name
Test status
Simulation time	15401473 ps
CPU time	0.57 seconds
Started	Mar 24 12:39:59 PM PDT 24
Finished	Mar 24 12:40:00 PM PDT 24
Peak memory	194712 kb
Host	smart-360f433a-e97d-40d4-b7d9-aa53f71e5166
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154348966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.154348966
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.3867411253
Short name	T1261
Test name
Test status
Simulation time	17352490 ps
CPU time	0.57 seconds
Started	Mar 24 12:40:03 PM PDT 24
Finished	Mar 24 12:40:13 PM PDT 24
Peak memory	194676 kb
Host	smart-4a69df62-23ae-47d5-b3f6-d13597c71e86
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867411253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3867411253
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.2872206338
Short name	T1160
Test name
Test status
Simulation time	29650406 ps
CPU time	0.55 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:01 PM PDT 24
Peak memory	194752 kb
Host	smart-20e5b6a7-eb43-4a1c-ae9d-49b888c4ab8c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872206338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2872206338
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.1724151453
Short name	T1200
Test name
Test status
Simulation time	87239166 ps
CPU time	0.54 seconds
Started	Mar 24 12:40:05 PM PDT 24
Finished	Mar 24 12:40:06 PM PDT 24
Peak memory	194640 kb
Host	smart-7d04e1e0-0a7f-445c-beba-b5eb2b0570df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724151453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1724151453
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.3538707066
Short name	T1252
Test name
Test status
Simulation time	16019263 ps
CPU time	0.56 seconds
Started	Mar 24 12:40:01 PM PDT 24
Finished	Mar 24 12:40:02 PM PDT 24
Peak memory	194580 kb
Host	smart-951f6c4e-b6b2-4067-aaf0-060f1b27d5db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538707066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3538707066
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.4055294830
Short name	T1145
Test name
Test status
Simulation time	20966875 ps
CPU time	0.54 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:54 PM PDT 24
Peak memory	194644 kb
Host	smart-30bd939a-3b69-4b1e-b66f-9b1b89323251
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055294830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4055294830
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.3300434750
Short name	T1191
Test name
Test status
Simulation time	13181805 ps
CPU time	0.54 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	194684 kb
Host	smart-808b8795-e8a6-45b5-885f-b447bea07406
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300434750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3300434750
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2683617720
Short name	T1131
Test name
Test status
Simulation time	35321863 ps
CPU time	0.77 seconds
Started	Mar 24 12:39:54 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	196672 kb
Host	smart-d51d2322-227c-4db1-b19c-ccf1fef01e77
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683617720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2683617720
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2221169105
Short name	T1225
Test name
Test status
Simulation time	176692573 ps
CPU time	1.4 seconds
Started	Mar 24 12:39:49 PM PDT 24
Finished	Mar 24 12:39:50 PM PDT 24
Peak memory	197972 kb
Host	smart-c599a4ae-5448-4ba0-a4af-6a57fe377679
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221169105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2221169105
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1282190762
Short name	T1221
Test name
Test status
Simulation time	15657915 ps
CPU time	0.6 seconds
Started	Mar 24 12:39:41 PM PDT 24
Finished	Mar 24 12:39:42 PM PDT 24
Peak memory	195748 kb
Host	smart-2d43679b-9031-4fd2-a00a-95323e80bb97
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282190762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1282190762
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2721042336
Short name	T1196
Test name
Test status
Simulation time	442409837 ps
CPU time	0.76 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:51 PM PDT 24
Peak memory	198952 kb
Host	smart-138121d8-087f-4f27-a782-cd7156b3ee07
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721042336 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2721042336
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.150382490
Short name	T1166
Test name
Test status
Simulation time	48951113 ps
CPU time	0.61 seconds
Started	Mar 24 12:40:05 PM PDT 24
Finished	Mar 24 12:40:06 PM PDT 24
Peak memory	195864 kb
Host	smart-0ed8315c-117a-4074-a0cc-ae298113ca74
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150382490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.150382490
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.268374180
Short name	T1175
Test name
Test status
Simulation time	16156107 ps
CPU time	0.57 seconds
Started	Mar 24 12:40:02 PM PDT 24
Finished	Mar 24 12:40:02 PM PDT 24
Peak memory	194776 kb
Host	smart-5cb363e1-d4e1-40b0-8537-c13a80b25da6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268374180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.268374180
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2037819930
Short name	T1199
Test name
Test status
Simulation time	26640248 ps
CPU time	0.67 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:54 PM PDT 24
Peak memory	196828 kb
Host	smart-c7067563-7c9c-430c-a8af-9179e87d3609
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037819930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.2037819930
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.4060708741
Short name	T1259
Test name
Test status
Simulation time	308320322 ps
CPU time	1.73 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:54 PM PDT 24
Peak memory	200584 kb
Host	smart-bbc501d2-f4a8-4425-8dbb-372f8fea62d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060708741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4060708741
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2649066927
Short name	T1188
Test name
Test status
Simulation time	40280353 ps
CPU time	0.93 seconds
Started	Mar 24 12:40:07 PM PDT 24
Finished	Mar 24 12:40:08 PM PDT 24
Peak memory	198920 kb
Host	smart-7960ad9a-9f0d-446a-b2bc-2ee3f2e9c91d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649066927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2649066927
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.1351378492
Short name	T1238
Test name
Test status
Simulation time	24290996 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:54 PM PDT 24
Peak memory	194688 kb
Host	smart-4a55bb16-9b31-4db5-a1f9-f184ec8ae406
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351378492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1351378492
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.405391605
Short name	T1164
Test name
Test status
Simulation time	13918657 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:05 PM PDT 24
Finished	Mar 24 12:40:06 PM PDT 24
Peak memory	194644 kb
Host	smart-692ecaf5-1bc4-4201-89d0-cdb17db5e708
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405391605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.405391605
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.3966121511
Short name	T1174
Test name
Test status
Simulation time	14933292 ps
CPU time	0.54 seconds
Started	Mar 24 12:40:17 PM PDT 24
Finished	Mar 24 12:40:17 PM PDT 24
Peak memory	194636 kb
Host	smart-81de9aa0-a9ae-4f25-8d63-c61916ffe768
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966121511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3966121511
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.3633169077
Short name	T1128
Test name
Test status
Simulation time	13812273 ps
CPU time	0.55 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	194608 kb
Host	smart-231d572e-7b85-40cb-8e8a-273e47ab691b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633169077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3633169077
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.4063726325
Short name	T1130
Test name
Test status
Simulation time	14845986 ps
CPU time	0.56 seconds
Started	Mar 24 12:40:14 PM PDT 24
Finished	Mar 24 12:40:15 PM PDT 24
Peak memory	194668 kb
Host	smart-1a55105a-49fa-49c7-a71a-7f3bba2f06fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063726325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4063726325
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.2335436
Short name	T1152
Test name
Test status
Simulation time	38851109 ps
CPU time	0.56 seconds
Started	Mar 24 12:40:26 PM PDT 24
Finished	Mar 24 12:40:27 PM PDT 24
Peak memory	194640 kb
Host	smart-01128e5f-b026-4882-a9ce-2ebb0b9c99f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2335436
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.3436732404
Short name	T1140
Test name
Test status
Simulation time	26193168 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:51 PM PDT 24
Peak memory	194648 kb
Host	smart-80b88fb2-c02e-493f-a30c-1d9461f1c16d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436732404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3436732404
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.2263878373
Short name	T1243
Test name
Test status
Simulation time	172348407 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:18 PM PDT 24
Finished	Mar 24 12:40:19 PM PDT 24
Peak memory	194644 kb
Host	smart-73fb8240-ed2e-4c89-a9ca-22c95fe2481e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263878373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2263878373
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.3095918428
Short name	T1217
Test name
Test status
Simulation time	19816982 ps
CPU time	0.55 seconds
Started	Mar 24 12:40:08 PM PDT 24
Finished	Mar 24 12:40:08 PM PDT 24
Peak memory	194596 kb
Host	smart-2f5190e4-5abd-4aaf-9ea2-6e5f3716fefc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095918428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3095918428
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.1271908168
Short name	T1227
Test name
Test status
Simulation time	48738266 ps
CPU time	0.56 seconds
Started	Mar 24 12:40:20 PM PDT 24
Finished	Mar 24 12:40:21 PM PDT 24
Peak memory	194604 kb
Host	smart-04b2b7cb-6996-40f7-998f-a063e1c710e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271908168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1271908168
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.321268956
Short name	T1244
Test name
Test status
Simulation time	20379298 ps
CPU time	0.67 seconds
Started	Mar 24 12:39:46 PM PDT 24
Finished	Mar 24 12:39:47 PM PDT 24
Peak memory	196008 kb
Host	smart-aed376f5-2a26-4f4d-9974-b417dcd68578
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321268956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.321268956
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1521304432
Short name	T76
Test name
Test status
Simulation time	217479389 ps
CPU time	2.26 seconds
Started	Mar 24 12:40:04 PM PDT 24
Finished	Mar 24 12:40:06 PM PDT 24
Peak memory	198180 kb
Host	smart-41357810-7c7a-4e3a-88c5-37aa9bef7485
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521304432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1521304432
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2291909382
Short name	T71
Test name
Test status
Simulation time	17187282 ps
CPU time	0.59 seconds
Started	Mar 24 12:39:45 PM PDT 24
Finished	Mar 24 12:39:46 PM PDT 24
Peak memory	195620 kb
Host	smart-ef4fec9b-66f2-4a77-a1d3-a5cd5ff8283d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291909382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2291909382
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1623789130
Short name	T1190
Test name
Test status
Simulation time	72849528 ps
CPU time	0.75 seconds
Started	Mar 24 12:40:17 PM PDT 24
Finished	Mar 24 12:40:18 PM PDT 24
Peak memory	199708 kb
Host	smart-d9373b2c-ce03-4fd7-8bc6-e609743cb02e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623789130 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1623789130
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.3574519965
Short name	T1209
Test name
Test status
Simulation time	14034892 ps
CPU time	0.59 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	195760 kb
Host	smart-a070532f-0d22-43df-bfc8-cf5f93555d1a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574519965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3574519965
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.2105184958
Short name	T1240
Test name
Test status
Simulation time	12573507 ps
CPU time	0.59 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	194616 kb
Host	smart-e8fd4d4b-385c-461d-b964-23712fdf9e5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105184958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2105184958
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1049503367
Short name	T1179
Test name
Test status
Simulation time	13956119 ps
CPU time	0.66 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:56 PM PDT 24
Peak memory	194952 kb
Host	smart-22e38936-34e2-4203-aac5-82a81c030aea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049503367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.1049503367
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.2467181472
Short name	T1208
Test name
Test status
Simulation time	325032611 ps
CPU time	1.39 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	200260 kb
Host	smart-8ee13c1b-1a9f-4037-901b-0a374dcede91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467181472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2467181472
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1285856709
Short name	T126
Test name
Test status
Simulation time	164542818 ps
CPU time	1.42 seconds
Started	Mar 24 12:39:43 PM PDT 24
Finished	Mar 24 12:39:45 PM PDT 24
Peak memory	199888 kb
Host	smart-c70193b3-8bdc-49fa-83f6-b9250bd3ab43
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285856709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1285856709
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.3668567464
Short name	T1219
Test name
Test status
Simulation time	24035326 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:25 PM PDT 24
Finished	Mar 24 12:40:26 PM PDT 24
Peak memory	194636 kb
Host	smart-6ebd3dae-6cb1-4cb3-9cb8-fb727e1b73ec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668567464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3668567464
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.1882316842
Short name	T1141
Test name
Test status
Simulation time	141003676 ps
CPU time	0.58 seconds
Started	Mar 24 12:40:09 PM PDT 24
Finished	Mar 24 12:40:10 PM PDT 24
Peak memory	194596 kb
Host	smart-d7d2ae2f-808d-4f7c-aba1-48030f46f7a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882316842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1882316842
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.920046809
Short name	T1185
Test name
Test status
Simulation time	14167220 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:16 PM PDT 24
Finished	Mar 24 12:40:16 PM PDT 24
Peak memory	194780 kb
Host	smart-4dfcfd8b-ef94-4ee3-b9f0-671c9f8dfe9e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920046809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.920046809
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.3174821777
Short name	T1127
Test name
Test status
Simulation time	19753442 ps
CPU time	0.55 seconds
Started	Mar 24 12:40:26 PM PDT 24
Finished	Mar 24 12:40:27 PM PDT 24
Peak memory	194760 kb
Host	smart-75891f8f-fce1-494e-9584-76241e1cef3f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174821777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3174821777
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.3782367676
Short name	T1132
Test name
Test status
Simulation time	65806922 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:05 PM PDT 24
Finished	Mar 24 12:40:06 PM PDT 24
Peak memory	194576 kb
Host	smart-76d4cf4c-881e-4239-8230-cb05801ad746
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782367676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3782367676
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.3121146298
Short name	T1234
Test name
Test status
Simulation time	14701193 ps
CPU time	0.54 seconds
Started	Mar 24 12:40:14 PM PDT 24
Finished	Mar 24 12:40:15 PM PDT 24
Peak memory	194640 kb
Host	smart-b2dfd688-9bd6-44f8-a35f-6a7e3549f351
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121146298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3121146298
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.2654159713
Short name	T1165
Test name
Test status
Simulation time	12853416 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:10 PM PDT 24
Finished	Mar 24 12:40:11 PM PDT 24
Peak memory	194680 kb
Host	smart-a39b5a95-d951-4df8-9754-0d7ebeda9f6a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654159713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2654159713
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.2735340332
Short name	T1153
Test name
Test status
Simulation time	50076690 ps
CPU time	0.55 seconds
Started	Mar 24 12:40:23 PM PDT 24
Finished	Mar 24 12:40:23 PM PDT 24
Peak memory	194624 kb
Host	smart-3c25a43c-87c5-4a30-9d84-e2b3de77660e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735340332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2735340332
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.2850462395
Short name	T1250
Test name
Test status
Simulation time	15656965 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	194708 kb
Host	smart-cd09a637-73c0-49cf-b3f2-f6851d85f545
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850462395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2850462395
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.1292723591
Short name	T1129
Test name
Test status
Simulation time	12666251 ps
CPU time	0.57 seconds
Started	Mar 24 12:40:25 PM PDT 24
Finished	Mar 24 12:40:26 PM PDT 24
Peak memory	194704 kb
Host	smart-7a124d54-d0a5-419b-8fcf-bd69c69a0dcf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292723591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1292723591
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3624589100
Short name	T1136
Test name
Test status
Simulation time	34380979 ps
CPU time	0.67 seconds
Started	Mar 24 12:40:25 PM PDT 24
Finished	Mar 24 12:40:26 PM PDT 24
Peak memory	197836 kb
Host	smart-7a5c6dfb-f597-48d7-a1e8-7f963201a312
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624589100 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3624589100
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.1272890434
Short name	T1168
Test name
Test status
Simulation time	16349650 ps
CPU time	0.61 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	195924 kb
Host	smart-20c14590-1e3a-4add-987b-85aa29602fca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272890434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1272890434
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.3675695411
Short name	T1224
Test name
Test status
Simulation time	82462568 ps
CPU time	0.58 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:50 PM PDT 24
Peak memory	194648 kb
Host	smart-e7b48b04-fce0-4aff-943e-29f42d8b9b83
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675695411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3675695411
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2299337597
Short name	T1230
Test name
Test status
Simulation time	259853659 ps
CPU time	0.76 seconds
Started	Mar 24 12:40:06 PM PDT 24
Finished	Mar 24 12:40:07 PM PDT 24
Peak memory	197532 kb
Host	smart-04f5fcd5-040f-45cb-aa7c-dfeb506862cd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299337597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.2299337597
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.271495357
Short name	T1137
Test name
Test status
Simulation time	28006450 ps
CPU time	1.38 seconds
Started	Mar 24 12:39:46 PM PDT 24
Finished	Mar 24 12:39:48 PM PDT 24
Peak memory	200332 kb
Host	smart-54cf769a-40f0-4e55-ab32-df720cd7e2a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271495357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.271495357
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2645881718
Short name	T106
Test name
Test status
Simulation time	236377909 ps
CPU time	1.35 seconds
Started	Mar 24 12:39:41 PM PDT 24
Finished	Mar 24 12:39:42 PM PDT 24
Peak memory	199628 kb
Host	smart-a2897c26-8cf0-4e0f-ba35-0424fb971756
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645881718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2645881718
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3428720339
Short name	T1150
Test name
Test status
Simulation time	46856621 ps
CPU time	0.75 seconds
Started	Mar 24 12:39:52 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	198812 kb
Host	smart-103dd655-8c60-40bd-b27b-a70509fcf59b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428720339 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3428720339
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.1626881686
Short name	T86
Test name
Test status
Simulation time	16129504 ps
CPU time	0.59 seconds
Started	Mar 24 12:40:32 PM PDT 24
Finished	Mar 24 12:40:32 PM PDT 24
Peak memory	195656 kb
Host	smart-24a690ce-3b41-49da-b4e5-2f7f319bf373
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626881686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1626881686
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.1977741719
Short name	T1155
Test name
Test status
Simulation time	45364706 ps
CPU time	0.56 seconds
Started	Mar 24 12:39:56 PM PDT 24
Finished	Mar 24 12:39:57 PM PDT 24
Peak memory	194576 kb
Host	smart-f296aecb-67b2-426c-929f-33df04e866a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977741719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1977741719
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2748611928
Short name	T98
Test name
Test status
Simulation time	24816710 ps
CPU time	0.64 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:58 PM PDT 24
Peak memory	195988 kb
Host	smart-11852686-466f-491d-bc7e-94e73edaaa9b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748611928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.2748611928
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.1724840951
Short name	T1138
Test name
Test status
Simulation time	60332884 ps
CPU time	1.43 seconds
Started	Mar 24 12:39:48 PM PDT 24
Finished	Mar 24 12:39:49 PM PDT 24
Peak memory	200648 kb
Host	smart-c08fe7c5-1646-4182-a6aa-023af59b925e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724840951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1724840951
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1672069292
Short name	T107
Test name
Test status
Simulation time	948544367 ps
CPU time	1.31 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:01 PM PDT 24
Peak memory	199748 kb
Host	smart-5719df44-34e4-448b-b331-0689435ad950
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672069292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1672069292
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.708577372
Short name	T1163
Test name
Test status
Simulation time	50950746 ps
CPU time	0.79 seconds
Started	Mar 24 12:39:47 PM PDT 24
Finished	Mar 24 12:39:48 PM PDT 24
Peak memory	200280 kb
Host	smart-19a10e13-ff0d-4087-89e2-be7bd4d77c4f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708577372 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.708577372
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.258594634
Short name	T1170
Test name
Test status
Simulation time	23053276 ps
CPU time	0.6 seconds
Started	Mar 24 12:40:18 PM PDT 24
Finished	Mar 24 12:40:19 PM PDT 24
Peak memory	195728 kb
Host	smart-c4f1aa42-db88-4ebb-8aa1-8f9a53acf479
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258594634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.258594634
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.2345690636
Short name	T1231
Test name
Test status
Simulation time	27964624 ps
CPU time	0.56 seconds
Started	Mar 24 12:39:53 PM PDT 24
Finished	Mar 24 12:39:53 PM PDT 24
Peak memory	194664 kb
Host	smart-ed77bd15-5ca8-4c02-ac42-e9c67e2eb4db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345690636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2345690636
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.206406855
Short name	T1186
Test name
Test status
Simulation time	47390269 ps
CPU time	0.7 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	198168 kb
Host	smart-7f0111cd-e32a-4c9b-82a5-1b8e81ca5634
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206406855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_ outstanding.206406855
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.3631775989
Short name	T1255
Test name
Test status
Simulation time	119868772 ps
CPU time	2.18 seconds
Started	Mar 24 12:40:05 PM PDT 24
Finished	Mar 24 12:40:08 PM PDT 24
Peak memory	200272 kb
Host	smart-221f78ce-5cba-4630-9833-2f586d876fb8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631775989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3631775989
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3775769838
Short name	T1249
Test name
Test status
Simulation time	19160419 ps
CPU time	0.66 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	197604 kb
Host	smart-7dc0636d-7df0-436c-a121-2441abd4cb8a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775769838 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3775769838
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.3668946169
Short name	T72
Test name
Test status
Simulation time	58275699 ps
CPU time	0.6 seconds
Started	Mar 24 12:39:57 PM PDT 24
Finished	Mar 24 12:39:58 PM PDT 24
Peak memory	195612 kb
Host	smart-21d6231f-c080-4bab-ab9e-3d214dc94aa2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668946169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3668946169
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.368529902
Short name	T1220
Test name
Test status
Simulation time	31084282 ps
CPU time	0.57 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	194664 kb
Host	smart-ee6c0bef-e366-4feb-81f5-f7ab86357d52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368529902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.368529902
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3179423272
Short name	T1246
Test name
Test status
Simulation time	16528680 ps
CPU time	0.74 seconds
Started	Mar 24 12:39:50 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	197808 kb
Host	smart-a9022680-673d-4a1d-8887-e5487a132696
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179423272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.3179423272
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.2592981419
Short name	T1260
Test name
Test status
Simulation time	111525885 ps
CPU time	1.26 seconds
Started	Mar 24 12:40:00 PM PDT 24
Finished	Mar 24 12:40:01 PM PDT 24
Peak memory	200292 kb
Host	smart-e7906a9b-1178-4dd6-acf4-e67db5ea66bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592981419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2592981419
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1620172253
Short name	T1237
Test name
Test status
Simulation time	103342478 ps
CPU time	0.94 seconds
Started	Mar 24 12:39:51 PM PDT 24
Finished	Mar 24 12:39:52 PM PDT 24
Peak memory	199048 kb
Host	smart-f8d56000-8af5-4aab-a4d9-c4fda34578c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620172253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1620172253
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2449771485
Short name	T1183
Test name
Test status
Simulation time	30254966 ps
CPU time	0.88 seconds
Started	Mar 24 12:39:43 PM PDT 24
Finished	Mar 24 12:39:44 PM PDT 24
Peak memory	200132 kb
Host	smart-1bef20c3-805a-4aad-8f93-f052733f2c45
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449771485 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2449771485
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.3518042809
Short name	T73
Test name
Test status
Simulation time	12313806 ps
CPU time	0.62 seconds
Started	Mar 24 12:40:15 PM PDT 24
Finished	Mar 24 12:40:16 PM PDT 24
Peak memory	195700 kb
Host	smart-d7b4cb2f-b74f-41a1-9bc8-9feb063f4c60
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518042809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3518042809
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.891113553
Short name	T1201
Test name
Test status
Simulation time	62318305 ps
CPU time	0.55 seconds
Started	Mar 24 12:40:44 PM PDT 24
Finished	Mar 24 12:40:46 PM PDT 24
Peak memory	194760 kb
Host	smart-27bedbfe-3a2a-4a4a-a182-67db4398cf16
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891113553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.891113553
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2041606814
Short name	T1202
Test name
Test status
Simulation time	18907929 ps
CPU time	0.72 seconds
Started	Mar 24 12:40:05 PM PDT 24
Finished	Mar 24 12:40:06 PM PDT 24
Peak memory	195948 kb
Host	smart-40ebd85c-07a9-4a8a-b607-1cb336b6d173
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041606814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.2041606814
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.2614647837
Short name	T1167
Test name
Test status
Simulation time	47771818 ps
CPU time	1.14 seconds
Started	Mar 24 12:39:55 PM PDT 24
Finished	Mar 24 12:39:57 PM PDT 24
Peak memory	200252 kb
Host	smart-4dbc6e17-769b-412d-84e4-a32cd6e803a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614647837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2614647837
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2499966205
Short name	T105
Test name
Test status
Simulation time	76026963 ps
CPU time	0.94 seconds
Started	Mar 24 12:39:49 PM PDT 24
Finished	Mar 24 12:39:50 PM PDT 24
Peak memory	199476 kb
Host	smart-c668e01b-ceb2-40bf-9b05-69e80fc35853
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499966205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2499966205
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_alert_test.863688333
Short name	T409
Test name
Test status
Simulation time	19021783 ps
CPU time	0.55 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:43:26 PM PDT 24
Peak memory	195612 kb
Host	smart-7c6e6c18-6993-4f30-9893-49d024ffdf79
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863688333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.863688333
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.1102238877
Short name	T673
Test name
Test status
Simulation time	85225431442 ps
CPU time	152.14 seconds
Started	Mar 24 02:43:06 PM PDT 24
Finished	Mar 24 02:45:40 PM PDT 24
Peak memory	200064 kb
Host	smart-d04ab5c3-09de-4b63-aa66-7d72efdd3ba6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102238877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1102238877
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.3922529032
Short name	T132
Test name
Test status
Simulation time	36442208066 ps
CPU time	61.64 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:44:34 PM PDT 24
Peak memory	199776 kb
Host	smart-7e7082ad-89a2-489f-8a20-c71e26639736
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922529032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3922529032
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_intr.920009895
Short name	T438
Test name
Test status
Simulation time	34476388097 ps
CPU time	26.08 seconds
Started	Mar 24 02:43:07 PM PDT 24
Finished	Mar 24 02:43:34 PM PDT 24
Peak memory	199188 kb
Host	smart-1a009898-723a-4e06-8b8f-18ecdde17ec6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920009895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.920009895
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.273612547
Short name	T560
Test name
Test status
Simulation time	109193644262 ps
CPU time	1000.89 seconds
Started	Mar 24 02:43:16 PM PDT 24
Finished	Mar 24 02:59:59 PM PDT 24
Peak memory	200188 kb
Host	smart-9af905d6-3c6e-4fe5-9a7e-407290cfe327
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=273612547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.273612547
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/0.uart_loopback.784460413
Short name	T379
Test name
Test status
Simulation time	5157535855 ps
CPU time	4.29 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:43:30 PM PDT 24
Peak memory	198368 kb
Host	smart-bfda8844-f4ba-4bd5-b6ed-92272114d5c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784460413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.784460413
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.3699265484
Short name	T270
Test name
Test status
Simulation time	53498128401 ps
CPU time	102.36 seconds
Started	Mar 24 02:43:16 PM PDT 24
Finished	Mar 24 02:45:00 PM PDT 24
Peak memory	200112 kb
Host	smart-c8982fa8-0b74-4a23-93b3-1397a9b359b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699265484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3699265484
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.221112286
Short name	T85
Test name
Test status
Simulation time	16772433792 ps
CPU time	318.3 seconds
Started	Mar 24 02:43:12 PM PDT 24
Finished	Mar 24 02:48:33 PM PDT 24
Peak memory	200212 kb
Host	smart-365f05b8-5517-47bb-bb23-94609f8b506f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=221112286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.221112286
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.3893368458
Short name	T789
Test name
Test status
Simulation time	4826308080 ps
CPU time	21.77 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:43:49 PM PDT 24
Peak memory	198260 kb
Host	smart-7357da01-18ea-4220-8acb-fe96c8c345c8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3893368458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3893368458
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.1372640390
Short name	T564
Test name
Test status
Simulation time	32166503112 ps
CPU time	17.41 seconds
Started	Mar 24 02:43:11 PM PDT 24
Finished	Mar 24 02:43:33 PM PDT 24
Peak memory	200080 kb
Host	smart-c80fca39-1c1f-4ab0-bcf8-458528db0187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372640390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1372640390
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.4070562673
Short name	T684
Test name
Test status
Simulation time	3379148727 ps
CPU time	6.48 seconds
Started	Mar 24 02:43:07 PM PDT 24
Finished	Mar 24 02:43:15 PM PDT 24
Peak memory	196244 kb
Host	smart-45c2991e-eb30-46c4-8961-09c49e732635
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070562673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4070562673
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_smoke.784272756
Short name	T965
Test name
Test status
Simulation time	6273018998 ps
CPU time	6.85 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:29 PM PDT 24
Peak memory	199912 kb
Host	smart-7c4698f1-a10e-40ef-9571-8478c9aece44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784272756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.784272756
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_stress_all.1442344530
Short name	T792
Test name
Test status
Simulation time	431257930096 ps
CPU time	132.35 seconds
Started	Mar 24 02:43:12 PM PDT 24
Finished	Mar 24 02:45:27 PM PDT 24
Peak memory	200140 kb
Host	smart-5e5ee379-a9b0-4a4c-af68-ee0ecf1ac48c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442344530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1442344530
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.3292185598
Short name	T788
Test name
Test status
Simulation time	426326537 ps
CPU time	1.15 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:43:28 PM PDT 24
Peak memory	198192 kb
Host	smart-260cc29f-9174-43ed-a49a-b30504c8ea5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292185598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3292185598
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.2076881302
Short name	T989
Test name
Test status
Simulation time	44277705506 ps
CPU time	103.64 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:45:08 PM PDT 24
Peak memory	200120 kb
Host	smart-d3e4f583-616b-4bb9-ac35-b09cf82ac068
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076881302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2076881302
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/1.uart_alert_test.2887508344
Short name	T751
Test name
Test status
Simulation time	47574690 ps
CPU time	0.54 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:28 PM PDT 24
Peak memory	194996 kb
Host	smart-6707872b-b085-48dc-a873-0838d9c5ff0e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887508344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2887508344
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.782147377
Short name	T449
Test name
Test status
Simulation time	35539808540 ps
CPU time	61.66 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:44:27 PM PDT 24
Peak memory	200080 kb
Host	smart-247418a3-526a-421a-8240-933afdbc8a39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782147377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.782147377
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.2470016523
Short name	T652
Test name
Test status
Simulation time	41998186222 ps
CPU time	13.79 seconds
Started	Mar 24 02:43:16 PM PDT 24
Finished	Mar 24 02:43:32 PM PDT 24
Peak memory	199612 kb
Host	smart-c420bc54-3b96-4c62-9652-03f53ed347dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470016523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2470016523
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.2029272058
Short name	T723
Test name
Test status
Simulation time	37181109480 ps
CPU time	45.72 seconds
Started	Mar 24 02:43:13 PM PDT 24
Finished	Mar 24 02:44:02 PM PDT 24
Peak memory	200164 kb
Host	smart-47381410-cdce-49a9-8b6a-54d03ed0b06c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029272058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2029272058
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_intr.2919265810
Short name	T637
Test name
Test status
Simulation time	6629926480 ps
CPU time	54.85 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:44:16 PM PDT 24
Peak memory	200000 kb
Host	smart-b61ff929-af96-4717-8933-4f06fac42b82
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919265810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2919265810
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.665054761
Short name	T466
Test name
Test status
Simulation time	161419445687 ps
CPU time	692.6 seconds
Started	Mar 24 02:43:12 PM PDT 24
Finished	Mar 24 02:54:47 PM PDT 24
Peak memory	200088 kb
Host	smart-7669d932-9ef3-4a40-aeac-324a3b2b8717
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=665054761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.665054761
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.1160464649
Short name	T579
Test name
Test status
Simulation time	8514384298 ps
CPU time	14.79 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:42 PM PDT 24
Peak memory	199260 kb
Host	smart-f08bf018-6086-4dc2-91bd-837d59d40927
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160464649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1160464649
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.2545468580
Short name	T543
Test name
Test status
Simulation time	112467616271 ps
CPU time	333.73 seconds
Started	Mar 24 02:43:12 PM PDT 24
Finished	Mar 24 02:48:48 PM PDT 24
Peak memory	199864 kb
Host	smart-3f366ff2-72d2-4502-ab94-b4c102c04104
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545468580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2545468580
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/1.uart_perf.2139666167
Short name	T362
Test name
Test status
Simulation time	638727431 ps
CPU time	19.44 seconds
Started	Mar 24 02:43:10 PM PDT 24
Finished	Mar 24 02:43:32 PM PDT 24
Peak memory	200008 kb
Host	smart-164180d3-10f4-4a24-8a19-5e8ba684ebe0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2139666167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2139666167
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.2337103962
Short name	T1025
Test name
Test status
Simulation time	5469057141 ps
CPU time	12.09 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:34 PM PDT 24
Peak memory	199240 kb
Host	smart-c753e291-b9c9-4fc0-befe-de0de8343fd1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2337103962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2337103962
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.716037559
Short name	T746
Test name
Test status
Simulation time	103684326863 ps
CPU time	80.69 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:44:49 PM PDT 24
Peak memory	200200 kb
Host	smart-e49665a5-1093-4130-83a2-1cd2d10427cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716037559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.716037559
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.1612857328
Short name	T464
Test name
Test status
Simulation time	4009843895 ps
CPU time	2.28 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:43:29 PM PDT 24
Peak memory	196156 kb
Host	smart-94e2f253-50f7-4b4c-812c-940243565859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612857328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1612857328
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.1110211388
Short name	T108
Test name
Test status
Simulation time	40766245 ps
CPU time	0.76 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:43:27 PM PDT 24
Peak memory	218636 kb
Host	smart-23a34190-8dee-4232-ad9b-bd4f7340b62c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110211388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1110211388
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/1.uart_smoke.2152862548
Short name	T848
Test name
Test status
Simulation time	845787514 ps
CPU time	2.96 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:43:27 PM PDT 24
Peak memory	198352 kb
Host	smart-2f18863c-f80a-4b3a-85cf-1ef54311a830
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152862548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2152862548
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_stress_all.1713042478
Short name	T1116
Test name
Test status
Simulation time	160272424466 ps
CPU time	1558.83 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 03:09:20 PM PDT 24
Peak memory	200168 kb
Host	smart-d596c90f-e111-4a40-a766-e677811ea4c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713042478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1713042478
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.940117299
Short name	T518
Test name
Test status
Simulation time	923661794 ps
CPU time	2.07 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:43:26 PM PDT 24
Peak memory	198852 kb
Host	smart-3e3a8dc6-4033-4425-9f41-f814c7584d80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940117299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.940117299
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.4058953544
Short name	T535
Test name
Test status
Simulation time	33907408649 ps
CPU time	48.49 seconds
Started	Mar 24 02:43:12 PM PDT 24
Finished	Mar 24 02:44:03 PM PDT 24
Peak memory	200148 kb
Host	smart-ac437103-0c5d-4152-99ec-3bfd22cc946c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058953544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4058953544
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.755985845
Short name	T1057
Test name
Test status
Simulation time	83729156526 ps
CPU time	43.1 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	200148 kb
Host	smart-58363c78-6682-46a8-b4b7-96e66d5b0b4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755985845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.755985845
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.149477328
Short name	T397
Test name
Test status
Simulation time	17299514377 ps
CPU time	16.59 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:43:49 PM PDT 24
Peak memory	198472 kb
Host	smart-b637fec1-1887-4fde-bac6-aa789d8fa1e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149477328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.149477328
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_intr.3777549325
Short name	T644
Test name
Test status
Simulation time	24459062133 ps
CPU time	11.87 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:43:46 PM PDT 24
Peak memory	199568 kb
Host	smart-09988614-601b-42e6-be3d-508cd744a2f7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777549325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3777549325
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.3360605195
Short name	T866
Test name
Test status
Simulation time	76513901511 ps
CPU time	583.44 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:53:19 PM PDT 24
Peak memory	200152 kb
Host	smart-ab368d1a-6c06-4bcb-9dc1-b30f84c6b0de
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3360605195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3360605195
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.3223168928
Short name	T432
Test name
Test status
Simulation time	4375860744 ps
CPU time	14.27 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:43:48 PM PDT 24
Peak memory	199792 kb
Host	smart-f40de8ae-5609-463f-be27-be478bba7103
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223168928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3223168928
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_noise_filter.1102480914
Short name	T283
Test name
Test status
Simulation time	152875764270 ps
CPU time	212.73 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:47:08 PM PDT 24
Peak memory	200264 kb
Host	smart-95118ce0-8aac-47a7-b135-cad64ecc9144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102480914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1102480914
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/10.uart_perf.2545976975
Short name	T812
Test name
Test status
Simulation time	26518309377 ps
CPU time	322.38 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:48:54 PM PDT 24
Peak memory	200080 kb
Host	smart-bbbb6055-866a-44f9-9394-d0d7216ff506
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2545976975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2545976975
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.3654107023
Short name	T545
Test name
Test status
Simulation time	5922103078 ps
CPU time	4.97 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:43:40 PM PDT 24
Peak memory	198200 kb
Host	smart-ab51ee89-e286-4814-80e6-6249258084a5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3654107023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3654107023
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.2276167960
Short name	T1002
Test name
Test status
Simulation time	75099155974 ps
CPU time	29.02 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:44:03 PM PDT 24
Peak memory	200156 kb
Host	smart-24d55456-806f-4c04-ae37-da05347cfed1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276167960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2276167960
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.4072800322
Short name	T1055
Test name
Test status
Simulation time	39404020369 ps
CPU time	16.45 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:43:48 PM PDT 24
Peak memory	196460 kb
Host	smart-18a27a6e-e1e2-4a53-9ea0-dca2284f2740
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072800322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.4072800322
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.1202670553
Short name	T669
Test name
Test status
Simulation time	681195510 ps
CPU time	1.95 seconds
Started	Mar 24 02:43:37 PM PDT 24
Finished	Mar 24 02:43:44 PM PDT 24
Peak memory	198872 kb
Host	smart-e79ad97e-838f-4d24-ac2b-27e56b659845
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202670553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1202670553
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.985144429
Short name	T20
Test name
Test status
Simulation time	832507896 ps
CPU time	3.03 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:43:37 PM PDT 24
Peak memory	199500 kb
Host	smart-8d76e146-75a7-4b72-ab10-e8e47c28f6eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985144429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.985144429
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.917822436
Short name	T521
Test name
Test status
Simulation time	33905893208 ps
CPU time	15.77 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	200108 kb
Host	smart-1caff1f4-af7f-4884-9103-09aaf8bda5e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917822436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.917822436
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.3826782787
Short name	T1034
Test name
Test status
Simulation time	50558019362 ps
CPU time	38.75 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:47:18 PM PDT 24
Peak memory	200132 kb
Host	smart-9aab76ca-6714-4e3d-97a8-8309b126f35e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826782787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3826782787
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.1747772484
Short name	T961
Test name
Test status
Simulation time	15246712955 ps
CPU time	17.75 seconds
Started	Mar 24 02:46:41 PM PDT 24
Finished	Mar 24 02:46:59 PM PDT 24
Peak memory	200340 kb
Host	smart-7b9ed7b5-011a-4be9-bdfd-bcbb8bb26442
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747772484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1747772484
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.4140635837
Short name	T180
Test name
Test status
Simulation time	148579090010 ps
CPU time	126.48 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:48:45 PM PDT 24
Peak memory	200152 kb
Host	smart-b09d84fb-392b-4b38-84ef-c944e9ffd8bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140635837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4140635837
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.2313793907
Short name	T420
Test name
Test status
Simulation time	10115946286 ps
CPU time	15.95 seconds
Started	Mar 24 02:46:40 PM PDT 24
Finished	Mar 24 02:46:56 PM PDT 24
Peak memory	199852 kb
Host	smart-fecb244a-51d3-427c-b6b6-adf945ebcdbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313793907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2313793907
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.2420200469
Short name	T27
Test name
Test status
Simulation time	72210718396 ps
CPU time	118.58 seconds
Started	Mar 24 02:46:40 PM PDT 24
Finished	Mar 24 02:48:39 PM PDT 24
Peak memory	200396 kb
Host	smart-1e7feef2-f9f1-4104-a779-4989e56101f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420200469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2420200469
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.2463374910
Short name	T726
Test name
Test status
Simulation time	42741415037 ps
CPU time	19.85 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:46:59 PM PDT 24
Peak memory	200116 kb
Host	smart-df048994-d5da-488b-8576-c71173d10e5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463374910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2463374910
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.4107252949
Short name	T342
Test name
Test status
Simulation time	231576268303 ps
CPU time	383.48 seconds
Started	Mar 24 02:46:38 PM PDT 24
Finished	Mar 24 02:53:02 PM PDT 24
Peak memory	200124 kb
Host	smart-54dcb0c8-1ada-4626-af00-df4da92c7bea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107252949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4107252949
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.2359832746
Short name	T1005
Test name
Test status
Simulation time	47516438 ps
CPU time	0.52 seconds
Started	Mar 24 02:43:42 PM PDT 24
Finished	Mar 24 02:43:43 PM PDT 24
Peak memory	194532 kb
Host	smart-05b43ba4-ddcf-478d-916c-97bceee02478
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359832746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2359832746
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.223967613
Short name	T754
Test name
Test status
Simulation time	29840405089 ps
CPU time	15.83 seconds
Started	Mar 24 02:43:57 PM PDT 24
Finished	Mar 24 02:44:13 PM PDT 24
Peak memory	200040 kb
Host	smart-fe07e0d0-1b60-4cf2-a62b-8ba363efaac1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223967613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.223967613
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.134476371
Short name	T836
Test name
Test status
Simulation time	169048625945 ps
CPU time	131.95 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:45:45 PM PDT 24
Peak memory	200120 kb
Host	smart-4b792e03-45ca-4107-a3cf-1fed861746ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134476371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.134476371
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.1262750606
Short name	T241
Test name
Test status
Simulation time	26600078212 ps
CPU time	37.64 seconds
Started	Mar 24 02:43:31 PM PDT 24
Finished	Mar 24 02:44:08 PM PDT 24
Peak memory	200192 kb
Host	smart-628e3e6d-0642-4d42-9be6-854b2fb54ca8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262750606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1262750606
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_intr.1010057795
Short name	T668
Test name
Test status
Simulation time	45625672204 ps
CPU time	13.46 seconds
Started	Mar 24 02:43:37 PM PDT 24
Finished	Mar 24 02:43:51 PM PDT 24
Peak memory	200152 kb
Host	smart-4c2dcc6f-6bbc-42c2-8744-51fc1a7050ea
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010057795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1010057795
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.2154899088
Short name	T943
Test name
Test status
Simulation time	135787068704 ps
CPU time	945.14 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:59:19 PM PDT 24
Peak memory	200076 kb
Host	smart-95a38bd9-8f98-4255-ba42-60d045495ee3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2154899088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2154899088
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.1472019881
Short name	T360
Test name
Test status
Simulation time	2577983832 ps
CPU time	2.05 seconds
Started	Mar 24 02:43:37 PM PDT 24
Finished	Mar 24 02:43:39 PM PDT 24
Peak memory	198816 kb
Host	smart-188a38ff-bb79-4352-bb61-e382155d583a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472019881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1472019881
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.1644713764
Short name	T843
Test name
Test status
Simulation time	79549347139 ps
CPU time	160.18 seconds
Started	Mar 24 02:43:38 PM PDT 24
Finished	Mar 24 02:46:18 PM PDT 24
Peak memory	200116 kb
Host	smart-ee588de7-e705-4e17-88c9-c1aaf3592798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644713764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1644713764
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.459271444
Short name	T25
Test name
Test status
Simulation time	28037541996 ps
CPU time	807.71 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:57:04 PM PDT 24
Peak memory	200100 kb
Host	smart-9783e1e2-a416-4142-be61-d3540a222ded
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=459271444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.459271444
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.2007043992
Short name	T386
Test name
Test status
Simulation time	2326754196 ps
CPU time	12.9 seconds
Started	Mar 24 02:43:31 PM PDT 24
Finished	Mar 24 02:43:44 PM PDT 24
Peak memory	198236 kb
Host	smart-f3c498ad-4f4b-4fa4-959c-623abe895ff7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2007043992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2007043992
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.4292817786
Short name	T984
Test name
Test status
Simulation time	131999643419 ps
CPU time	27.82 seconds
Started	Mar 24 02:43:38 PM PDT 24
Finished	Mar 24 02:44:06 PM PDT 24
Peak memory	200256 kb
Host	smart-b2833158-0c66-4be1-90cc-acfca9970585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292817786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4292817786
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.2202455077
Short name	T334
Test name
Test status
Simulation time	5030574812 ps
CPU time	1.66 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:43:33 PM PDT 24
Peak memory	196224 kb
Host	smart-d2ee844c-aad5-4bda-a937-9c31ee48bdfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202455077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2202455077
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.2495316560
Short name	T290
Test name
Test status
Simulation time	5788770967 ps
CPU time	14.76 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:43:46 PM PDT 24
Peak memory	200076 kb
Host	smart-5b786b9a-274c-4766-ae3b-56b19be71561
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495316560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2495316560
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all.2038213856
Short name	T120
Test name
Test status
Simulation time	33053000423 ps
CPU time	57.43 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:44:33 PM PDT 24
Peak memory	200172 kb
Host	smart-2516be07-4639-42d6-987b-a74b44be2e59
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038213856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2038213856
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.3299539603
Short name	T508
Test name
Test status
Simulation time	6293027054 ps
CPU time	19.8 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:43:54 PM PDT 24
Peak memory	200188 kb
Host	smart-a0863f6d-2392-4db8-9007-02889bb0e869
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299539603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3299539603
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.3765360354
Short name	T372
Test name
Test status
Simulation time	36173518448 ps
CPU time	15.22 seconds
Started	Mar 24 02:43:47 PM PDT 24
Finished	Mar 24 02:44:02 PM PDT 24
Peak memory	200048 kb
Host	smart-3e420b26-08b8-4084-9fc6-11cb4a68abf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765360354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3765360354
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.1884985948
Short name	T978
Test name
Test status
Simulation time	22597397022 ps
CPU time	15.35 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:46:54 PM PDT 24
Peak memory	200120 kb
Host	smart-bd02542e-5992-4a1c-a8fe-d86682993e43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884985948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1884985948
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.4170248513
Short name	T818
Test name
Test status
Simulation time	18479052576 ps
CPU time	8.46 seconds
Started	Mar 24 02:46:40 PM PDT 24
Finished	Mar 24 02:46:48 PM PDT 24
Peak memory	200112 kb
Host	smart-71668d26-3765-49c0-ab36-0cea36053ee3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170248513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4170248513
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.3880846658
Short name	T313
Test name
Test status
Simulation time	75366157298 ps
CPU time	56.93 seconds
Started	Mar 24 02:46:38 PM PDT 24
Finished	Mar 24 02:47:35 PM PDT 24
Peak memory	200140 kb
Host	smart-17064028-ca76-48df-82a2-b2a30c506079
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880846658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3880846658
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.2591399900
Short name	T177
Test name
Test status
Simulation time	22309178961 ps
CPU time	17.57 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:46:56 PM PDT 24
Peak memory	200100 kb
Host	smart-c7ce88ee-d80f-4a08-a15c-6a728c7ccf47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591399900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2591399900
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.340149623
Short name	T226
Test name
Test status
Simulation time	153384998454 ps
CPU time	151.89 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:49:12 PM PDT 24
Peak memory	200228 kb
Host	smart-206b338c-5ba6-4296-a7cf-30c5471cb8e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340149623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.340149623
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.965075175
Short name	T309
Test name
Test status
Simulation time	39948041713 ps
CPU time	39.96 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:47:25 PM PDT 24
Peak memory	200176 kb
Host	smart-bb0499a0-2565-4bfc-a9b6-eb4f63d0dbfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965075175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.965075175
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.3207026001
Short name	T615
Test name
Test status
Simulation time	85318720624 ps
CPU time	63.92 seconds
Started	Mar 24 02:46:43 PM PDT 24
Finished	Mar 24 02:47:47 PM PDT 24
Peak memory	200220 kb
Host	smart-374f391a-678c-45f2-833b-237ef95b5751
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207026001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3207026001
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.3024474183
Short name	T148
Test name
Test status
Simulation time	25917567808 ps
CPU time	53.57 seconds
Started	Mar 24 02:46:45 PM PDT 24
Finished	Mar 24 02:47:39 PM PDT 24
Peak memory	200160 kb
Host	smart-3d27c1b8-50b4-467a-b3f5-6a6c0162a4b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024474183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3024474183
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.2184204882
Short name	T699
Test name
Test status
Simulation time	9768522180 ps
CPU time	8.66 seconds
Started	Mar 24 02:46:46 PM PDT 24
Finished	Mar 24 02:46:54 PM PDT 24
Peak memory	200044 kb
Host	smart-e8805058-83a4-4c47-8b66-7e1c7e4df1ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184204882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2184204882
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.3751959759
Short name	T31
Test name
Test status
Simulation time	32281594 ps
CPU time	0.55 seconds
Started	Mar 24 02:43:41 PM PDT 24
Finished	Mar 24 02:43:42 PM PDT 24
Peak memory	194948 kb
Host	smart-89b9fbe1-46e2-4e2b-a216-af7400a70730
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751959759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3751959759
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.744331843
Short name	T135
Test name
Test status
Simulation time	85004429993 ps
CPU time	161.14 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:46:16 PM PDT 24
Peak memory	200172 kb
Host	smart-c69ed174-afb7-4659-836c-8fbdeb1ef1e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744331843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.744331843
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.738244800
Short name	T577
Test name
Test status
Simulation time	51507038247 ps
CPU time	94.89 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:45:15 PM PDT 24
Peak memory	200140 kb
Host	smart-f7eddc3a-41ab-4595-864f-fe5759614a58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738244800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.738244800
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.3932743339
Short name	T1070
Test name
Test status
Simulation time	160568074903 ps
CPU time	63.09 seconds
Started	Mar 24 02:43:38 PM PDT 24
Finished	Mar 24 02:44:41 PM PDT 24
Peak memory	200144 kb
Host	smart-286ed441-554a-4afa-b638-8771ffe3a49e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932743339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3932743339
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_intr.3544708802
Short name	T557
Test name
Test status
Simulation time	11984142184 ps
CPU time	6.68 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:43:43 PM PDT 24
Peak memory	200148 kb
Host	smart-10517ec6-db5e-4511-a270-f4330869cc32
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544708802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3544708802
Directory	/workspace/12.uart_intr/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.63246127
Short name	T1115
Test name
Test status
Simulation time	77219953942 ps
CPU time	727.28 seconds
Started	Mar 24 02:43:52 PM PDT 24
Finished	Mar 24 02:55:59 PM PDT 24
Peak memory	200100 kb
Host	smart-39dd17c3-cbac-45eb-9145-0493fa647f16
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=63246127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.63246127
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_loopback.2230921900
Short name	T487
Test name
Test status
Simulation time	8869402502 ps
CPU time	7.63 seconds
Started	Mar 24 02:43:41 PM PDT 24
Finished	Mar 24 02:43:49 PM PDT 24
Peak memory	197940 kb
Host	smart-0475dab3-a716-4b6b-a882-913db885fc6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230921900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2230921900
Directory	/workspace/12.uart_loopback/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.3044144800
Short name	T760
Test name
Test status
Simulation time	78585651026 ps
CPU time	142.21 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:45:58 PM PDT 24
Peak memory	200212 kb
Host	smart-129ce49b-dfc4-4e39-a7fb-f60f30fc42dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044144800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3044144800
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.3035653898
Short name	T500
Test name
Test status
Simulation time	8884582628 ps
CPU time	202.34 seconds
Started	Mar 24 02:43:38 PM PDT 24
Finished	Mar 24 02:47:01 PM PDT 24
Peak memory	200132 kb
Host	smart-307bef55-d0d1-458f-a208-480c46978e99
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3035653898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3035653898
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.2066198699
Short name	T938
Test name
Test status
Simulation time	3831540422 ps
CPU time	28.75 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:44:04 PM PDT 24
Peak memory	199024 kb
Host	smart-c6c4cb84-c871-44ba-9f33-db3bd703d2e5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2066198699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2066198699
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.2638290677
Short name	T481
Test name
Test status
Simulation time	71099523977 ps
CPU time	103.56 seconds
Started	Mar 24 02:43:37 PM PDT 24
Finished	Mar 24 02:45:20 PM PDT 24
Peak memory	199728 kb
Host	smart-a3adfe63-000f-49a9-8ea9-aceea3843ad0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638290677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2638290677
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.2282175008
Short name	T617
Test name
Test status
Simulation time	3115572029 ps
CPU time	5.73 seconds
Started	Mar 24 02:43:38 PM PDT 24
Finished	Mar 24 02:43:44 PM PDT 24
Peak memory	196516 kb
Host	smart-b81a87fa-dc8d-4385-b5b9-0a09f7adb25f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282175008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2282175008
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.1539394330
Short name	T401
Test name
Test status
Simulation time	6002787210 ps
CPU time	8.42 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:43:45 PM PDT 24
Peak memory	200024 kb
Host	smart-f04a614b-dc83-4e93-be2d-0a7d4d17a8fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539394330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1539394330
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.3982123098
Short name	T315
Test name
Test status
Simulation time	6958148994 ps
CPU time	32.25 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:44:08 PM PDT 24
Peak memory	200084 kb
Host	smart-d9045b12-8faf-4c91-ad1c-cf09b86a128c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982123098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3982123098
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.3165253470
Short name	T839
Test name
Test status
Simulation time	12495024108 ps
CPU time	8.09 seconds
Started	Mar 24 02:43:38 PM PDT 24
Finished	Mar 24 02:43:46 PM PDT 24
Peak memory	200032 kb
Host	smart-8fc6f3a7-b970-4310-867d-d71d262879b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165253470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3165253470
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.3480129919
Short name	T589
Test name
Test status
Simulation time	51223837947 ps
CPU time	45.52 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:47:29 PM PDT 24
Peak memory	200140 kb
Host	smart-77170a0b-1a37-4743-a236-5b7e87339a3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480129919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3480129919
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.2959936895
Short name	T905
Test name
Test status
Simulation time	83447774870 ps
CPU time	20.98 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:47:05 PM PDT 24
Peak memory	200052 kb
Host	smart-13257e40-7651-4870-86b8-dee67e17c859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959936895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2959936895
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.2440139308
Short name	T791
Test name
Test status
Simulation time	219632952640 ps
CPU time	59.06 seconds
Started	Mar 24 02:46:45 PM PDT 24
Finished	Mar 24 02:47:45 PM PDT 24
Peak memory	200204 kb
Host	smart-fbc47b8f-e97f-4445-abae-386eba11c85d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440139308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2440139308
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.668321498
Short name	T215
Test name
Test status
Simulation time	68345828867 ps
CPU time	30.56 seconds
Started	Mar 24 02:46:48 PM PDT 24
Finished	Mar 24 02:47:19 PM PDT 24
Peak memory	200124 kb
Host	smart-05aea357-993f-4856-aa0b-521b108010e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668321498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.668321498
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.583923574
Short name	T165
Test name
Test status
Simulation time	36787760388 ps
CPU time	29.12 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:47:13 PM PDT 24
Peak memory	200040 kb
Host	smart-6e36e52a-200b-415e-a483-0f34b12c136a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583923574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.583923574
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.2875242657
Short name	T211
Test name
Test status
Simulation time	19264791261 ps
CPU time	31.36 seconds
Started	Mar 24 02:46:46 PM PDT 24
Finished	Mar 24 02:47:17 PM PDT 24
Peak memory	200092 kb
Host	smart-d99a792d-70af-46fb-8de4-69aafc4799c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875242657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2875242657
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.4078787399
Short name	T612
Test name
Test status
Simulation time	45479789791 ps
CPU time	52.38 seconds
Started	Mar 24 02:46:44 PM PDT 24
Finished	Mar 24 02:47:36 PM PDT 24
Peak memory	200108 kb
Host	smart-2f946687-6c1a-4834-94cc-5f0bde1be960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078787399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.4078787399
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_alert_test.4240363253
Short name	T387
Test name
Test status
Simulation time	44012706 ps
CPU time	0.54 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:44:06 PM PDT 24
Peak memory	195628 kb
Host	smart-ce6056f5-0dda-410c-9ba2-3d621d94bfd0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240363253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4240363253
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.889840596
Short name	T955
Test name
Test status
Simulation time	242033123334 ps
CPU time	78.01 seconds
Started	Mar 24 02:44:01 PM PDT 24
Finished	Mar 24 02:45:19 PM PDT 24
Peak memory	200052 kb
Host	smart-8bae8e31-4754-4546-9498-8a880e862369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889840596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.889840596
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.2756696855
Short name	T992
Test name
Test status
Simulation time	63046430107 ps
CPU time	118.68 seconds
Started	Mar 24 02:43:40 PM PDT 24
Finished	Mar 24 02:45:39 PM PDT 24
Peak memory	200172 kb
Host	smart-77fe896b-4db0-4cef-a874-7694bbe42f7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756696855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2756696855
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.3673361333
Short name	T819
Test name
Test status
Simulation time	13263626971 ps
CPU time	6.14 seconds
Started	Mar 24 02:43:58 PM PDT 24
Finished	Mar 24 02:44:04 PM PDT 24
Peak memory	197992 kb
Host	smart-90695af1-61a5-4e0b-a43b-326f9ed75692
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673361333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3673361333
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.2726984189
Short name	T496
Test name
Test status
Simulation time	90436069012 ps
CPU time	125.39 seconds
Started	Mar 24 02:43:58 PM PDT 24
Finished	Mar 24 02:46:04 PM PDT 24
Peak memory	200160 kb
Host	smart-efca3783-4201-466c-8b4c-6ab44d234045
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2726984189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2726984189
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/13.uart_loopback.1121045971
Short name	T512
Test name
Test status
Simulation time	5569227967 ps
CPU time	10.84 seconds
Started	Mar 24 02:44:02 PM PDT 24
Finished	Mar 24 02:44:13 PM PDT 24
Peak memory	199304 kb
Host	smart-8bdaa688-8aaa-4ce1-aa96-c4d51e95a781
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121045971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1121045971
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.3532806338
Short name	T1121
Test name
Test status
Simulation time	1557431030 ps
CPU time	3.27 seconds
Started	Mar 24 02:43:56 PM PDT 24
Finished	Mar 24 02:43:59 PM PDT 24
Peak memory	195196 kb
Host	smart-0fd93402-14e2-493f-a5ab-9d7d2ef15e11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532806338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3532806338
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.1515753750
Short name	T502
Test name
Test status
Simulation time	12346765050 ps
CPU time	278.76 seconds
Started	Mar 24 02:43:44 PM PDT 24
Finished	Mar 24 02:48:23 PM PDT 24
Peak memory	200088 kb
Host	smart-33ce59a9-1405-4004-876c-ff7cdd12ce23
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1515753750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1515753750
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.1699515465
Short name	T380
Test name
Test status
Simulation time	4638800820 ps
CPU time	16.85 seconds
Started	Mar 24 02:43:50 PM PDT 24
Finished	Mar 24 02:44:07 PM PDT 24
Peak memory	199308 kb
Host	smart-4f285bc2-3d9a-4af7-9e13-f9baad1fb5e8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1699515465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1699515465
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.63151408
Short name	T539
Test name
Test status
Simulation time	273936434637 ps
CPU time	113.43 seconds
Started	Mar 24 02:43:39 PM PDT 24
Finished	Mar 24 02:45:32 PM PDT 24
Peak memory	200100 kb
Host	smart-f722b040-0625-4a39-8a99-6850ef7d1d71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63151408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.63151408
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.2018233534
Short name	T829
Test name
Test status
Simulation time	5167164706 ps
CPU time	2.93 seconds
Started	Mar 24 02:43:39 PM PDT 24
Finished	Mar 24 02:43:42 PM PDT 24
Peak memory	196244 kb
Host	smart-36055582-6191-4d7a-b1b6-d9ff48d336c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018233534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2018233534
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.1102434513
Short name	T899
Test name
Test status
Simulation time	136011610 ps
CPU time	0.81 seconds
Started	Mar 24 02:43:41 PM PDT 24
Finished	Mar 24 02:43:42 PM PDT 24
Peak memory	197836 kb
Host	smart-687d4474-fde1-4e8a-989e-f073f1294278
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102434513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1102434513
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_stress_all.361151801
Short name	T1102
Test name
Test status
Simulation time	291436236428 ps
CPU time	303.79 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:49:09 PM PDT 24
Peak memory	200104 kb
Host	smart-e73fa0fe-c4cf-4bc9-bf1d-88519b454e45
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361151801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.361151801
Directory	/workspace/13.uart_stress_all/latest

Test location	/workspace/coverage/default/13.uart_stress_all_with_rand_reset.1819859165
Short name	T814
Test name
Test status
Simulation time	20176059950 ps
CPU time	245.57 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:48:12 PM PDT 24
Peak memory	215696 kb
Host	smart-90a567ac-a2a1-47b9-ba0f-a023c125d2ec
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819859165 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1819859165
Directory	/workspace/13.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.4084562904
Short name	T19
Test name
Test status
Simulation time	1161147712 ps
CPU time	1.48 seconds
Started	Mar 24 02:44:04 PM PDT 24
Finished	Mar 24 02:44:06 PM PDT 24
Peak memory	199964 kb
Host	smart-f70c614f-e62c-437f-9b5d-9463f0f51144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084562904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4084562904
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.1051109166
Short name	T766
Test name
Test status
Simulation time	96316509406 ps
CPU time	37.77 seconds
Started	Mar 24 02:43:42 PM PDT 24
Finished	Mar 24 02:44:19 PM PDT 24
Peak memory	200048 kb
Host	smart-e3d30127-f3b3-4b36-92de-c6bb03629eba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051109166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1051109166
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.63787853
Short name	T64
Test name
Test status
Simulation time	73328683661 ps
CPU time	51.88 seconds
Started	Mar 24 02:46:46 PM PDT 24
Finished	Mar 24 02:47:38 PM PDT 24
Peak memory	200152 kb
Host	smart-d6ffdaa9-ce00-468a-a815-eaa26f4fcc02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63787853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.63787853
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.3694021939
Short name	T933
Test name
Test status
Simulation time	126823323968 ps
CPU time	200.18 seconds
Started	Mar 24 02:46:45 PM PDT 24
Finished	Mar 24 02:50:06 PM PDT 24
Peak memory	199860 kb
Host	smart-c44d470e-9a03-4bb1-a2ec-3d912bf222aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694021939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3694021939
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.509194402
Short name	T872
Test name
Test status
Simulation time	112076347095 ps
CPU time	179.8 seconds
Started	Mar 24 02:46:49 PM PDT 24
Finished	Mar 24 02:49:49 PM PDT 24
Peak memory	200112 kb
Host	smart-783bbbf5-1778-4755-b083-6997b53fcba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509194402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.509194402
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.1570604138
Short name	T411
Test name
Test status
Simulation time	58427142896 ps
CPU time	43.38 seconds
Started	Mar 24 02:46:48 PM PDT 24
Finished	Mar 24 02:47:32 PM PDT 24
Peak memory	200096 kb
Host	smart-41dcece8-8218-458f-b926-242136dfd82e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570604138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1570604138
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.2950242303
Short name	T470
Test name
Test status
Simulation time	130853064467 ps
CPU time	75.38 seconds
Started	Mar 24 02:46:50 PM PDT 24
Finished	Mar 24 02:48:06 PM PDT 24
Peak memory	200164 kb
Host	smart-f7010108-5ef2-4420-a3dc-1bba41271252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950242303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2950242303
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.2599795925
Short name	T711
Test name
Test status
Simulation time	12518760 ps
CPU time	0.57 seconds
Started	Mar 24 02:43:45 PM PDT 24
Finished	Mar 24 02:43:46 PM PDT 24
Peak memory	195616 kb
Host	smart-429e983d-c518-4f28-b808-a707bf8232cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599795925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2599795925
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.1548455543
Short name	T272
Test name
Test status
Simulation time	18032122992 ps
CPU time	7.14 seconds
Started	Mar 24 02:43:47 PM PDT 24
Finished	Mar 24 02:43:54 PM PDT 24
Peak memory	200024 kb
Host	smart-4520750e-fd3c-4859-86ad-a8a42f5d9d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548455543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1548455543
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.770008137
Short name	T453
Test name
Test status
Simulation time	99977789339 ps
CPU time	75.84 seconds
Started	Mar 24 02:43:44 PM PDT 24
Finished	Mar 24 02:45:00 PM PDT 24
Peak memory	200192 kb
Host	smart-dace4d06-8e6b-44a6-8603-19465a0ba0b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770008137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.770008137
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.1964669670
Short name	T202
Test name
Test status
Simulation time	231225221116 ps
CPU time	99.69 seconds
Started	Mar 24 02:43:58 PM PDT 24
Finished	Mar 24 02:45:39 PM PDT 24
Peak memory	200208 kb
Host	smart-541572e9-1885-4c97-a8ad-3a78018fff15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964669670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1964669670
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.1526736719
Short name	T1019
Test name
Test status
Simulation time	57674707768 ps
CPU time	47.76 seconds
Started	Mar 24 02:44:02 PM PDT 24
Finished	Mar 24 02:44:51 PM PDT 24
Peak memory	199988 kb
Host	smart-ab358a2a-0ceb-4b45-96ae-f45e32e87e63
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526736719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1526736719
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.827858994
Short name	T914
Test name
Test status
Simulation time	149934838801 ps
CPU time	1111.4 seconds
Started	Mar 24 02:43:59 PM PDT 24
Finished	Mar 24 03:02:30 PM PDT 24
Peak memory	200136 kb
Host	smart-1453e44c-1a73-4f4f-a79f-5a8956b2d93f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=827858994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.827858994
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.797809669
Short name	T21
Test name
Test status
Simulation time	4858357746 ps
CPU time	8.21 seconds
Started	Mar 24 02:44:02 PM PDT 24
Finished	Mar 24 02:44:11 PM PDT 24
Peak memory	199936 kb
Host	smart-7e3f858e-5042-40dc-bffb-5f6b20e183f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797809669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.797809669
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.2123875702
Short name	T675
Test name
Test status
Simulation time	27598844376 ps
CPU time	42.54 seconds
Started	Mar 24 02:43:47 PM PDT 24
Finished	Mar 24 02:44:30 PM PDT 24
Peak memory	200192 kb
Host	smart-272703bb-fbf1-423d-a33a-a70c79ee726b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123875702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2123875702
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_perf.4268821682
Short name	T654
Test name
Test status
Simulation time	6558355417 ps
CPU time	198.91 seconds
Started	Mar 24 02:44:01 PM PDT 24
Finished	Mar 24 02:47:20 PM PDT 24
Peak memory	200096 kb
Host	smart-cbfb580d-a6ec-4b58-a0c5-1b75d1d0ad82
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4268821682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.4268821682
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.3492086486
Short name	T553
Test name
Test status
Simulation time	4407255716 ps
CPU time	9.08 seconds
Started	Mar 24 02:43:47 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	198268 kb
Host	smart-d973bfb6-2520-4eb2-b5df-b003bbcc34b6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3492086486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3492086486
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.2026333501
Short name	T530
Test name
Test status
Simulation time	97551554337 ps
CPU time	59.57 seconds
Started	Mar 24 02:44:00 PM PDT 24
Finished	Mar 24 02:45:00 PM PDT 24
Peak memory	200176 kb
Host	smart-2521b720-616c-4d74-b008-29589b42e4cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2026333501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2026333501
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.1020369163
Short name	T787
Test name
Test status
Simulation time	700714294 ps
CPU time	1.78 seconds
Started	Mar 24 02:44:00 PM PDT 24
Finished	Mar 24 02:44:02 PM PDT 24
Peak memory	195836 kb
Host	smart-edf9fa74-f544-49ab-bf49-4391c59112c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020369163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1020369163
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.4077422760
Short name	T328
Test name
Test status
Simulation time	5766267437 ps
CPU time	23.02 seconds
Started	Mar 24 02:43:46 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	199892 kb
Host	smart-fe4f7330-97da-4a5a-9e32-f50e89ab58bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077422760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4077422760
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_stress_all.1349031629
Short name	T1120
Test name
Test status
Simulation time	40036701133 ps
CPU time	33.24 seconds
Started	Mar 24 02:43:45 PM PDT 24
Finished	Mar 24 02:44:18 PM PDT 24
Peak memory	200164 kb
Host	smart-466535f8-ecc3-4378-ad40-b48bc7b5236e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349031629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1349031629
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.274889500
Short name	T375
Test name
Test status
Simulation time	1079805235 ps
CPU time	1.14 seconds
Started	Mar 24 02:44:00 PM PDT 24
Finished	Mar 24 02:44:01 PM PDT 24
Peak memory	199080 kb
Host	smart-997c89c5-a3dc-4f08-9a99-2fc1f0634afc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274889500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.274889500
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.536034443
Short name	T963
Test name
Test status
Simulation time	16022695746 ps
CPU time	26.62 seconds
Started	Mar 24 02:43:46 PM PDT 24
Finished	Mar 24 02:44:13 PM PDT 24
Peak memory	200104 kb
Host	smart-7dcf2214-8d4c-48e9-8f59-fc07136e639d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536034443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.536034443
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.132422895
Short name	T385
Test name
Test status
Simulation time	28448784745 ps
CPU time	39.57 seconds
Started	Mar 24 02:46:55 PM PDT 24
Finished	Mar 24 02:47:36 PM PDT 24
Peak memory	200016 kb
Host	smart-892d4fb1-b22e-4ae4-97af-11290e81dcbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132422895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.132422895
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.4264843245
Short name	T1084
Test name
Test status
Simulation time	68731750976 ps
CPU time	41.86 seconds
Started	Mar 24 02:46:48 PM PDT 24
Finished	Mar 24 02:47:31 PM PDT 24
Peak memory	200176 kb
Host	smart-ab823c99-44ed-423a-ac76-a8babcd1071a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264843245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4264843245
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.3563618633
Short name	T140
Test name
Test status
Simulation time	118105660658 ps
CPU time	85.87 seconds
Started	Mar 24 02:46:55 PM PDT 24
Finished	Mar 24 02:48:22 PM PDT 24
Peak memory	200116 kb
Host	smart-673f3a0f-0d07-4954-8974-172c7c2b8b00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3563618633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3563618633
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.2870092770
Short name	T550
Test name
Test status
Simulation time	17637815416 ps
CPU time	21.36 seconds
Started	Mar 24 02:46:49 PM PDT 24
Finished	Mar 24 02:47:11 PM PDT 24
Peak memory	200188 kb
Host	smart-844fbfcc-9b2e-4953-9310-d5be30866d43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870092770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2870092770
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.3535541740
Short name	T764
Test name
Test status
Simulation time	110031217926 ps
CPU time	58.41 seconds
Started	Mar 24 02:46:49 PM PDT 24
Finished	Mar 24 02:47:49 PM PDT 24
Peak memory	200156 kb
Host	smart-69d08e8a-1ced-4c37-b5b1-976221cf00da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535541740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3535541740
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.1402308393
Short name	T212
Test name
Test status
Simulation time	179615764299 ps
CPU time	121.77 seconds
Started	Mar 24 02:46:47 PM PDT 24
Finished	Mar 24 02:48:49 PM PDT 24
Peak memory	200096 kb
Host	smart-3ace4bd6-e8ea-4dac-8cf9-fd91923e868e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402308393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1402308393
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.627911654
Short name	T590
Test name
Test status
Simulation time	131609808663 ps
CPU time	113.86 seconds
Started	Mar 24 02:46:47 PM PDT 24
Finished	Mar 24 02:48:41 PM PDT 24
Peak memory	200124 kb
Host	smart-a06b70f3-06f2-4f0d-8660-3ff60b104dd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627911654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.627911654
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.269909888
Short name	T1101
Test name
Test status
Simulation time	7974044444 ps
CPU time	12.43 seconds
Started	Mar 24 02:46:53 PM PDT 24
Finished	Mar 24 02:47:06 PM PDT 24
Peak memory	200052 kb
Host	smart-7793a436-efde-46ff-bf2a-73c0c9d91596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269909888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.269909888
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.3235377587
Short name	T715
Test name
Test status
Simulation time	33639416 ps
CPU time	0.57 seconds
Started	Mar 24 02:43:51 PM PDT 24
Finished	Mar 24 02:43:52 PM PDT 24
Peak memory	195624 kb
Host	smart-d0cec05b-6c20-4415-af67-85fc86b86292
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235377587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3235377587
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.2857320458
Short name	T827
Test name
Test status
Simulation time	188638950974 ps
CPU time	60.58 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:45:08 PM PDT 24
Peak memory	200140 kb
Host	smart-d60dc774-808c-4213-bfec-c7da760bbee6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857320458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2857320458
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.3573104906
Short name	T887
Test name
Test status
Simulation time	124974156100 ps
CPU time	111.63 seconds
Started	Mar 24 02:44:04 PM PDT 24
Finished	Mar 24 02:45:56 PM PDT 24
Peak memory	200088 kb
Host	smart-f3b11c6e-f9b2-4d1b-8bd6-1dc3cf9a0fff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3573104906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3573104906
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.3314052343
Short name	T799
Test name
Test status
Simulation time	58969305801 ps
CPU time	96.63 seconds
Started	Mar 24 02:43:51 PM PDT 24
Finished	Mar 24 02:45:27 PM PDT 24
Peak memory	199840 kb
Host	smart-c8e36a2a-3656-4632-9b17-ea9e36d7c3e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314052343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3314052343
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_intr.289644274
Short name	T717
Test name
Test status
Simulation time	17626602951 ps
CPU time	7.09 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	200080 kb
Host	smart-3a3896bf-1163-482c-b7a5-08bd7684d650
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289644274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.289644274
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.1495182131
Short name	T845
Test name
Test status
Simulation time	224587321533 ps
CPU time	742.24 seconds
Started	Mar 24 02:43:50 PM PDT 24
Finished	Mar 24 02:56:13 PM PDT 24
Peak memory	200152 kb
Host	smart-81039cb1-03f8-468b-8ccb-28f6b08dfb7c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1495182131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1495182131
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_loopback.3581339071
Short name	T852
Test name
Test status
Simulation time	8556378442 ps
CPU time	17.55 seconds
Started	Mar 24 02:43:51 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	199200 kb
Host	smart-3683b613-3e2b-4463-b8e4-41b1c2718453
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3581339071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3581339071
Directory	/workspace/15.uart_loopback/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.3288373116
Short name	T841
Test name
Test status
Simulation time	209960017580 ps
CPU time	78.78 seconds
Started	Mar 24 02:43:49 PM PDT 24
Finished	Mar 24 02:45:07 PM PDT 24
Peak memory	216572 kb
Host	smart-3ba952a7-ff57-4fec-ad75-d60d37fe53a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288373116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3288373116
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_perf.4116550173
Short name	T1003
Test name
Test status
Simulation time	11744438394 ps
CPU time	600.69 seconds
Started	Mar 24 02:43:53 PM PDT 24
Finished	Mar 24 02:53:54 PM PDT 24
Peak memory	200156 kb
Host	smart-1a8b30c5-3c03-49fd-b9ac-52fdca2a6f2c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4116550173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4116550173
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.2111707403
Short name	T506
Test name
Test status
Simulation time	5470579735 ps
CPU time	46.02 seconds
Started	Mar 24 02:44:03 PM PDT 24
Finished	Mar 24 02:44:49 PM PDT 24
Peak memory	199760 kb
Host	smart-0e131f4e-dde4-4359-8bdc-ce688eb27d28
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2111707403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2111707403
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.2530865668
Short name	T948
Test name
Test status
Simulation time	65356259732 ps
CPU time	119.08 seconds
Started	Mar 24 02:43:51 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	200184 kb
Host	smart-52b62790-1729-459d-8d06-751883dd9f55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530865668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2530865668
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.2421730331
Short name	T346
Test name
Test status
Simulation time	2024784822 ps
CPU time	4.08 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	195724 kb
Host	smart-9f4eb44a-1b5d-4dd3-a47e-bff75d3dfff8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421730331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2421730331
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.636474697
Short name	T436
Test name
Test status
Simulation time	110045233 ps
CPU time	0.79 seconds
Started	Mar 24 02:44:03 PM PDT 24
Finished	Mar 24 02:44:05 PM PDT 24
Peak memory	197216 kb
Host	smart-15577044-485d-4b74-9974-f17b06dda771
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636474697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.636474697
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.2783678348
Short name	T415
Test name
Test status
Simulation time	1468515397 ps
CPU time	2.29 seconds
Started	Mar 24 02:43:52 PM PDT 24
Finished	Mar 24 02:43:54 PM PDT 24
Peak memory	198328 kb
Host	smart-8eeaaf9f-589a-41ca-8330-22be5ef836ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783678348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2783678348
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.3109979437
Short name	T718
Test name
Test status
Simulation time	29014805807 ps
CPU time	59.22 seconds
Started	Mar 24 02:44:04 PM PDT 24
Finished	Mar 24 02:45:04 PM PDT 24
Peak memory	200100 kb
Host	smart-e858ea62-643d-4e39-96e5-bd4d9b7d7279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109979437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3109979437
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.1846379358
Short name	T633
Test name
Test status
Simulation time	132152959377 ps
CPU time	50.12 seconds
Started	Mar 24 02:46:53 PM PDT 24
Finished	Mar 24 02:47:43 PM PDT 24
Peak memory	200176 kb
Host	smart-5a31036b-d1e5-4d5b-91ba-2f458efc1655
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846379358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1846379358
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.3688010100
Short name	T771
Test name
Test status
Simulation time	19934834078 ps
CPU time	36.76 seconds
Started	Mar 24 02:46:56 PM PDT 24
Finished	Mar 24 02:47:33 PM PDT 24
Peak memory	200172 kb
Host	smart-daa8d509-d017-4488-a14b-9d1a4d8d209b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688010100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3688010100
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.1579911057
Short name	T646
Test name
Test status
Simulation time	76659726552 ps
CPU time	21.64 seconds
Started	Mar 24 02:46:53 PM PDT 24
Finished	Mar 24 02:47:16 PM PDT 24
Peak memory	200124 kb
Host	smart-0387f36d-f956-4e33-a6f7-036cc824df16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579911057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1579911057
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.2084927807
Short name	T526
Test name
Test status
Simulation time	30358325750 ps
CPU time	55.2 seconds
Started	Mar 24 02:46:56 PM PDT 24
Finished	Mar 24 02:47:51 PM PDT 24
Peak memory	200152 kb
Host	smart-166da743-aea0-41e4-8df1-9745ba8f36e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084927807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2084927807
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.3611670962
Short name	T807
Test name
Test status
Simulation time	52790575923 ps
CPU time	93.3 seconds
Started	Mar 24 02:46:54 PM PDT 24
Finished	Mar 24 02:48:27 PM PDT 24
Peak memory	200132 kb
Host	smart-38637518-8f23-485a-bb7b-91c96b8d3001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611670962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3611670962
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.1879359335
Short name	T214
Test name
Test status
Simulation time	18615077265 ps
CPU time	29.64 seconds
Started	Mar 24 02:46:54 PM PDT 24
Finished	Mar 24 02:47:24 PM PDT 24
Peak memory	200192 kb
Host	smart-6bd93d16-d82c-4467-ad24-b5bed81c1a4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879359335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1879359335
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.2126211488
Short name	T209
Test name
Test status
Simulation time	22778862286 ps
CPU time	20.33 seconds
Started	Mar 24 02:46:54 PM PDT 24
Finished	Mar 24 02:47:14 PM PDT 24
Peak memory	200144 kb
Host	smart-e3a5e4cc-c7d6-49bc-baac-757e7ff13195
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126211488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2126211488
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.1049578292
Short name	T217
Test name
Test status
Simulation time	30070340851 ps
CPU time	24.83 seconds
Started	Mar 24 02:46:59 PM PDT 24
Finished	Mar 24 02:47:25 PM PDT 24
Peak memory	200160 kb
Host	smart-cecdf0a9-6b58-4cea-9f7b-c2690af999b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049578292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1049578292
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.1125917717
Short name	T390
Test name
Test status
Simulation time	29457747 ps
CPU time	0.55 seconds
Started	Mar 24 02:43:50 PM PDT 24
Finished	Mar 24 02:43:50 PM PDT 24
Peak memory	195568 kb
Host	smart-a4ecf0a4-4d9f-4f52-923b-b0b98359c541
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125917717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1125917717
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.3691829644
Short name	T597
Test name
Test status
Simulation time	23300157013 ps
CPU time	35.89 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:44 PM PDT 24
Peak memory	200044 kb
Host	smart-31f00918-4b54-4f30-9ea3-58b2965cf912
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691829644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3691829644
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.1393817920
Short name	T614
Test name
Test status
Simulation time	94599400286 ps
CPU time	69.2 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:45:15 PM PDT 24
Peak memory	200112 kb
Host	smart-243a58d1-89a8-41d7-8041-6ced8f6a6299
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393817920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1393817920
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.1138479507
Short name	T52
Test name
Test status
Simulation time	25479836784 ps
CPU time	20.38 seconds
Started	Mar 24 02:44:06 PM PDT 24
Finished	Mar 24 02:44:27 PM PDT 24
Peak memory	199908 kb
Host	smart-e3890602-691f-4e24-8010-ad7748f4a036
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138479507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1138479507
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_intr.3343525528
Short name	T1031
Test name
Test status
Simulation time	1208734033 ps
CPU time	1.15 seconds
Started	Mar 24 02:43:59 PM PDT 24
Finished	Mar 24 02:44:00 PM PDT 24
Peak memory	195768 kb
Host	smart-a390e7e5-854c-4af8-a1cc-bd6966092d9b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343525528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3343525528
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.1326476990
Short name	T451
Test name
Test status
Simulation time	41865010420 ps
CPU time	88.52 seconds
Started	Mar 24 02:43:51 PM PDT 24
Finished	Mar 24 02:45:20 PM PDT 24
Peak memory	200072 kb
Host	smart-02e2f5bd-43d3-487f-9e81-904981478dd7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1326476990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1326476990
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.2136375876
Short name	T783
Test name
Test status
Simulation time	4095521426 ps
CPU time	4.11 seconds
Started	Mar 24 02:43:52 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	199972 kb
Host	smart-7ab81236-ebc0-4f24-aee3-72588f5bca83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136375876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2136375876
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.1837771397
Short name	T288
Test name
Test status
Simulation time	48042890666 ps
CPU time	19.43 seconds
Started	Mar 24 02:43:50 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	200060 kb
Host	smart-ad723420-5310-4421-a8b9-a356b1205ea9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837771397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1837771397
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.180341705
Short name	T901
Test name
Test status
Simulation time	11512945437 ps
CPU time	471.67 seconds
Started	Mar 24 02:43:51 PM PDT 24
Finished	Mar 24 02:51:43 PM PDT 24
Peak memory	200196 kb
Host	smart-de7bb59a-a602-4033-9ede-133fb7cf7fb8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=180341705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.180341705
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.2939681713
Short name	T410
Test name
Test status
Simulation time	6206435906 ps
CPU time	52.21 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:59 PM PDT 24
Peak memory	198240 kb
Host	smart-1bb52730-926c-43ee-8de9-77d68bb897f1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2939681713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2939681713
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.3376248071
Short name	T623
Test name
Test status
Simulation time	258812057034 ps
CPU time	31.43 seconds
Started	Mar 24 02:43:48 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	199860 kb
Host	smart-59c4edea-11ff-4e25-9b7f-58ff1298f784
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376248071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3376248071
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.1869081084
Short name	T689
Test name
Test status
Simulation time	4127135010 ps
CPU time	6.38 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:13 PM PDT 24
Peak memory	196124 kb
Host	smart-a9e570b5-1538-4a5a-afb4-e9748c6a0093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869081084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1869081084
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.1521509955
Short name	T425
Test name
Test status
Simulation time	715768652 ps
CPU time	3.13 seconds
Started	Mar 24 02:43:53 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	198848 kb
Host	smart-e4cad755-8395-4edb-ba49-6f9cb29a98ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1521509955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1521509955
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_stress_all.2075185701
Short name	T610
Test name
Test status
Simulation time	57342852587 ps
CPU time	15.57 seconds
Started	Mar 24 02:43:49 PM PDT 24
Finished	Mar 24 02:44:05 PM PDT 24
Peak memory	200188 kb
Host	smart-dccc0011-2e04-47e2-ae4e-1cbdcfb156ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075185701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2075185701
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.268525088
Short name	T572
Test name
Test status
Simulation time	669184539 ps
CPU time	2.54 seconds
Started	Mar 24 02:43:48 PM PDT 24
Finished	Mar 24 02:43:51 PM PDT 24
Peak memory	200056 kb
Host	smart-20e334c2-cb91-4830-94de-566e315a4eb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268525088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.268525088
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.2886614521
Short name	T628
Test name
Test status
Simulation time	52937027218 ps
CPU time	43.44 seconds
Started	Mar 24 02:43:51 PM PDT 24
Finished	Mar 24 02:44:35 PM PDT 24
Peak memory	200160 kb
Host	smart-fec55b1b-d75e-4deb-b46b-ef68b7206252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886614521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2886614521
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.803399398
Short name	T138
Test name
Test status
Simulation time	102172750741 ps
CPU time	97.11 seconds
Started	Mar 24 02:46:58 PM PDT 24
Finished	Mar 24 02:48:37 PM PDT 24
Peak memory	200148 kb
Host	smart-8ca5bc49-a7e1-4e20-adc3-d9b09560f934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803399398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.803399398
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.1176777703
Short name	T653
Test name
Test status
Simulation time	268211864708 ps
CPU time	138.3 seconds
Started	Mar 24 02:46:59 PM PDT 24
Finished	Mar 24 02:49:18 PM PDT 24
Peak memory	200156 kb
Host	smart-a468fe67-1fae-4b3c-b6ff-19b85f580dbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176777703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1176777703
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.3412147538
Short name	T227
Test name
Test status
Simulation time	174502195683 ps
CPU time	75.78 seconds
Started	Mar 24 02:47:01 PM PDT 24
Finished	Mar 24 02:48:17 PM PDT 24
Peak memory	200104 kb
Host	smart-dd5b14a8-ec7a-44b8-8cab-b2abd141f7f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412147538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3412147538
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.2508023156
Short name	T235
Test name
Test status
Simulation time	219946481750 ps
CPU time	90.61 seconds
Started	Mar 24 02:47:02 PM PDT 24
Finished	Mar 24 02:48:33 PM PDT 24
Peak memory	200048 kb
Host	smart-b7e9f654-25bb-4253-aa3f-af79a418527b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508023156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2508023156
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.1248203560
Short name	T348
Test name
Test status
Simulation time	50948339081 ps
CPU time	17.87 seconds
Started	Mar 24 02:47:01 PM PDT 24
Finished	Mar 24 02:47:19 PM PDT 24
Peak memory	199964 kb
Host	smart-77aa1f4c-0a63-4d38-9633-ac82aaa39427
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248203560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1248203560
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.3299269745
Short name	T1080
Test name
Test status
Simulation time	30522742420 ps
CPU time	21.19 seconds
Started	Mar 24 02:47:01 PM PDT 24
Finished	Mar 24 02:47:23 PM PDT 24
Peak memory	198532 kb
Host	smart-fdc29674-ba4b-4082-9e97-6bfad680d02b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299269745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3299269745
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.3091868357
Short name	T207
Test name
Test status
Simulation time	38642096775 ps
CPU time	100.09 seconds
Started	Mar 24 02:46:59 PM PDT 24
Finished	Mar 24 02:48:40 PM PDT 24
Peak memory	200152 kb
Host	smart-a2105c1c-b7a5-4696-a85d-ae7ff869b04a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091868357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3091868357
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.140623978
Short name	T50
Test name
Test status
Simulation time	13325252 ps
CPU time	0.57 seconds
Started	Mar 24 02:44:03 PM PDT 24
Finished	Mar 24 02:44:04 PM PDT 24
Peak memory	194544 kb
Host	smart-f0ae104d-47d5-4dd9-916e-782bab8f44b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140623978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.140623978
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.2716525859
Short name	T339
Test name
Test status
Simulation time	26446551440 ps
CPU time	22.05 seconds
Started	Mar 24 02:43:55 PM PDT 24
Finished	Mar 24 02:44:18 PM PDT 24
Peak memory	199416 kb
Host	smart-00c84043-5e1c-4752-a9e0-7875899d92f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716525859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2716525859
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_intr.1339646941
Short name	T782
Test name
Test status
Simulation time	100020512452 ps
CPU time	82.78 seconds
Started	Mar 24 02:43:56 PM PDT 24
Finished	Mar 24 02:45:18 PM PDT 24
Peak memory	196852 kb
Host	smart-a65c606e-6263-4368-afe2-da62115f0718
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339646941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1339646941
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.3336265514
Short name	T616
Test name
Test status
Simulation time	134406605863 ps
CPU time	348.29 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:49:59 PM PDT 24
Peak memory	200100 kb
Host	smart-1a02032a-db02-44e2-b3d1-9c06a88af941
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3336265514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3336265514
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.1039680309
Short name	T472
Test name
Test status
Simulation time	2078488674 ps
CPU time	1.61 seconds
Started	Mar 24 02:43:55 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	197912 kb
Host	smart-b15703db-ea4c-423b-8812-125d3cda6169
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039680309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1039680309
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.3110528102
Short name	T974
Test name
Test status
Simulation time	50298383093 ps
CPU time	20.91 seconds
Started	Mar 24 02:43:59 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	208444 kb
Host	smart-9abb75dd-d4bf-47e1-97dc-0015ce2b0d71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110528102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3110528102
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.4220450157
Short name	T538
Test name
Test status
Simulation time	13022431278 ps
CPU time	319.23 seconds
Started	Mar 24 02:43:53 PM PDT 24
Finished	Mar 24 02:49:12 PM PDT 24
Peak memory	200136 kb
Host	smart-5492f144-2ad6-4b15-8a8a-0f3e46012ea5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4220450157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4220450157
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.2792027353
Short name	T988
Test name
Test status
Simulation time	2104355023 ps
CPU time	12.06 seconds
Started	Mar 24 02:43:57 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	198136 kb
Host	smart-23e37ea1-abbf-4060-ae0b-05281c66a697
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2792027353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2792027353
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.4230865695
Short name	T622
Test name
Test status
Simulation time	31557446272 ps
CPU time	55.08 seconds
Started	Mar 24 02:44:03 PM PDT 24
Finished	Mar 24 02:44:59 PM PDT 24
Peak memory	200092 kb
Host	smart-1c81c572-c7c4-4141-aa85-3e67f63f0266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230865695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4230865695
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.2854585085
Short name	T983
Test name
Test status
Simulation time	5234493282 ps
CPU time	3.49 seconds
Started	Mar 24 02:44:03 PM PDT 24
Finished	Mar 24 02:44:06 PM PDT 24
Peak memory	196196 kb
Host	smart-30a7947a-c619-4832-9d8d-5552de9ad9f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854585085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2854585085
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.2907145170
Short name	T934
Test name
Test status
Simulation time	143167915 ps
CPU time	0.82 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:44:06 PM PDT 24
Peak memory	198200 kb
Host	smart-ed34d5ca-dea5-4428-a07f-bb81530a7b95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907145170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2907145170
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_stress_all.2729954206
Short name	T1058
Test name
Test status
Simulation time	364441839410 ps
CPU time	269.54 seconds
Started	Mar 24 02:43:55 PM PDT 24
Finished	Mar 24 02:48:25 PM PDT 24
Peak memory	215736 kb
Host	smart-e283eebf-0d09-40f0-a8d6-efbb0a274ff1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729954206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2729954206
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/17.uart_stress_all_with_rand_reset.243473158
Short name	T22
Test name
Test status
Simulation time	15692758711 ps
CPU time	146.34 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:46:36 PM PDT 24
Peak memory	215860 kb
Host	smart-d90ffb5c-4956-492b-8359-2ee2f4890a51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243473158 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.243473158
Directory	/workspace/17.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.4131884572
Short name	T522
Test name
Test status
Simulation time	2461790721 ps
CPU time	1.88 seconds
Started	Mar 24 02:43:56 PM PDT 24
Finished	Mar 24 02:43:58 PM PDT 24
Peak memory	200032 kb
Host	smart-3c6cfc4e-df6a-411a-b546-a5597924c6b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131884572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4131884572
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.3853663696
Short name	T642
Test name
Test status
Simulation time	1848922134 ps
CPU time	2.89 seconds
Started	Mar 24 02:43:53 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	197360 kb
Host	smart-fb2caaf5-aedb-4f56-91d5-1dd91286e6f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3853663696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3853663696
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.211800843
Short name	T681
Test name
Test status
Simulation time	78336894174 ps
CPU time	64.18 seconds
Started	Mar 24 02:46:59 PM PDT 24
Finished	Mar 24 02:48:04 PM PDT 24
Peak memory	199936 kb
Host	smart-78001aea-b997-457c-a666-d38d4441d278
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211800843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.211800843
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.1365689445
Short name	T737
Test name
Test status
Simulation time	52317631176 ps
CPU time	45.76 seconds
Started	Mar 24 02:47:03 PM PDT 24
Finished	Mar 24 02:47:50 PM PDT 24
Peak memory	200076 kb
Host	smart-1aa3cabb-49e7-40e8-b420-52643b59e3c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365689445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1365689445
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/172.uart_fifo_reset.2510367024
Short name	T345
Test name
Test status
Simulation time	6371979112 ps
CPU time	10.63 seconds
Started	Mar 24 02:47:03 PM PDT 24
Finished	Mar 24 02:47:13 PM PDT 24
Peak memory	197580 kb
Host	smart-12a9ff5a-fbdd-480a-b0b4-60ff0a6d1bbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510367024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2510367024
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.1622425563
Short name	T547
Test name
Test status
Simulation time	100671268918 ps
CPU time	51.54 seconds
Started	Mar 24 02:47:04 PM PDT 24
Finished	Mar 24 02:47:56 PM PDT 24
Peak memory	200160 kb
Host	smart-341a7523-1a4a-4e21-a3e0-8cd3a479b853
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622425563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1622425563
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.2794116590
Short name	T371
Test name
Test status
Simulation time	57574616329 ps
CPU time	151.87 seconds
Started	Mar 24 02:47:04 PM PDT 24
Finished	Mar 24 02:49:36 PM PDT 24
Peak memory	200192 kb
Host	smart-b380e35f-e74c-459c-bac9-8da251a279b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794116590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2794116590
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.3334277663
Short name	T763
Test name
Test status
Simulation time	45446793928 ps
CPU time	39.11 seconds
Started	Mar 24 02:47:03 PM PDT 24
Finished	Mar 24 02:47:43 PM PDT 24
Peak memory	200156 kb
Host	smart-00c9b4b6-40f3-4cc4-97b1-dd97a9602412
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334277663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3334277663
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.2461629919
Short name	T947
Test name
Test status
Simulation time	105478254376 ps
CPU time	62.76 seconds
Started	Mar 24 02:47:05 PM PDT 24
Finished	Mar 24 02:48:08 PM PDT 24
Peak memory	200096 kb
Host	smart-20ba501b-9397-4c62-bdea-3fca9ff2521b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461629919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2461629919
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.1810162806
Short name	T806
Test name
Test status
Simulation time	52733096879 ps
CPU time	67.96 seconds
Started	Mar 24 02:47:04 PM PDT 24
Finished	Mar 24 02:48:12 PM PDT 24
Peak memory	200108 kb
Host	smart-37064366-e1be-496c-949b-3622928c520a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810162806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1810162806
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.759644345
Short name	T929
Test name
Test status
Simulation time	45417482033 ps
CPU time	103.74 seconds
Started	Mar 24 02:47:03 PM PDT 24
Finished	Mar 24 02:48:47 PM PDT 24
Peak memory	200120 kb
Host	smart-3d0a8995-447e-49a4-9337-b522d15130d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759644345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.759644345
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.229881153
Short name	T491
Test name
Test status
Simulation time	138717302185 ps
CPU time	227.64 seconds
Started	Mar 24 02:47:04 PM PDT 24
Finished	Mar 24 02:50:52 PM PDT 24
Peak memory	200048 kb
Host	smart-21e654f2-1cdf-4f18-a937-73c23c9a7eac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229881153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.229881153
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_alert_test.2034849169
Short name	T603
Test name
Test status
Simulation time	15823713 ps
CPU time	0.56 seconds
Started	Mar 24 02:43:59 PM PDT 24
Finished	Mar 24 02:43:59 PM PDT 24
Peak memory	195664 kb
Host	smart-d48043a5-38b7-41bf-a2d8-a3fecd3dbed1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034849169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2034849169
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.3097324709
Short name	T162
Test name
Test status
Simulation time	204559043182 ps
CPU time	199.82 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:47:30 PM PDT 24
Peak memory	200148 kb
Host	smart-87734cc9-fd5b-4fe3-9143-f9dddc342b3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097324709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3097324709
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.1346449140
Short name	T702
Test name
Test status
Simulation time	111900474888 ps
CPU time	173.62 seconds
Started	Mar 24 02:43:56 PM PDT 24
Finished	Mar 24 02:46:50 PM PDT 24
Peak memory	200316 kb
Host	smart-d38ed3f0-e811-455e-8f17-982c7be771cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346449140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1346449140
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.204241958
Short name	T831
Test name
Test status
Simulation time	23124564108 ps
CPU time	10.66 seconds
Started	Mar 24 02:44:11 PM PDT 24
Finished	Mar 24 02:44:22 PM PDT 24
Peak memory	200096 kb
Host	smart-21d37183-e44b-41d4-a549-101dd7c8d37e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204241958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.204241958
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_intr.4143688056
Short name	T1124
Test name
Test status
Simulation time	65312637324 ps
CPU time	127.61 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:46:18 PM PDT 24
Peak memory	200100 kb
Host	smart-f90d5de7-db16-462d-aa3f-02832afed685
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143688056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4143688056
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_long_xfer_wo_dly.2091300630
Short name	T1062
Test name
Test status
Simulation time	108647016028 ps
CPU time	301.99 seconds
Started	Mar 24 02:44:08 PM PDT 24
Finished	Mar 24 02:49:11 PM PDT 24
Peak memory	200044 kb
Host	smart-809d4201-37c2-4a32-9714-7566a9f7a979
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2091300630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2091300630
Directory	/workspace/18.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/18.uart_loopback.2563661957
Short name	T376
Test name
Test status
Simulation time	2626390088 ps
CPU time	3.66 seconds
Started	Mar 24 02:44:08 PM PDT 24
Finished	Mar 24 02:44:13 PM PDT 24
Peak memory	198940 kb
Host	smart-bd3fbecc-a311-4e98-94f4-d189a70a4aa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2563661957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2563661957
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.3097229946
Short name	T913
Test name
Test status
Simulation time	104516398842 ps
CPU time	56.58 seconds
Started	Mar 24 02:44:03 PM PDT 24
Finished	Mar 24 02:45:00 PM PDT 24
Peak memory	199800 kb
Host	smart-9d9cfcb4-391e-40c5-9416-f1f18ed840da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097229946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3097229946
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.1627861845
Short name	T569
Test name
Test status
Simulation time	9586993614 ps
CPU time	172.37 seconds
Started	Mar 24 02:44:00 PM PDT 24
Finished	Mar 24 02:46:53 PM PDT 24
Peak memory	200304 kb
Host	smart-cde91902-4629-4b51-969d-e4d83b98ea55
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1627861845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1627861845
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.3480129823
Short name	T60
Test name
Test status
Simulation time	1499572359 ps
CPU time	3.77 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	198040 kb
Host	smart-0c1ac22b-e0db-42c5-bfdc-edfc7bcac595
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3480129823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3480129823
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.881083321
Short name	T1028
Test name
Test status
Simulation time	82603108924 ps
CPU time	209.63 seconds
Started	Mar 24 02:44:01 PM PDT 24
Finished	Mar 24 02:47:31 PM PDT 24
Peak memory	200060 kb
Host	smart-9efde851-1dd4-4b55-9bff-dfe063958d0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881083321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.881083321
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.1453042229
Short name	T581
Test name
Test status
Simulation time	3860726057 ps
CPU time	1.84 seconds
Started	Mar 24 02:43:59 PM PDT 24
Finished	Mar 24 02:44:01 PM PDT 24
Peak memory	196184 kb
Host	smart-1db48251-ea45-4842-90ad-c13ecf3e5c16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453042229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1453042229
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.2636417779
Short name	T778
Test name
Test status
Simulation time	290129362 ps
CPU time	1.2 seconds
Started	Mar 24 02:43:58 PM PDT 24
Finished	Mar 24 02:44:00 PM PDT 24
Peak memory	198456 kb
Host	smart-b44a1fa7-f672-45c3-8471-fc3dffd065a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636417779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2636417779
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_stress_all.1075733381
Short name	T745
Test name
Test status
Simulation time	340926016073 ps
CPU time	224.93 seconds
Started	Mar 24 02:44:04 PM PDT 24
Finished	Mar 24 02:47:50 PM PDT 24
Peak memory	200160 kb
Host	smart-d7de57a5-9199-492d-91ba-06d2e71b2936
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075733381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1075733381
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.2982731290
Short name	T790
Test name
Test status
Simulation time	6384994917 ps
CPU time	21.32 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:44:31 PM PDT 24
Peak memory	199516 kb
Host	smart-97bcd6d0-9780-484d-9af4-e2f3990f963b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982731290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2982731290
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.3283802113
Short name	T1065
Test name
Test status
Simulation time	45931405747 ps
CPU time	101.81 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:45:52 PM PDT 24
Peak memory	200176 kb
Host	smart-7d4f88d1-1853-4fd8-9fba-35a21c6be0b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283802113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3283802113
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.2257394507
Short name	T307
Test name
Test status
Simulation time	130047527378 ps
CPU time	32.52 seconds
Started	Mar 24 02:47:04 PM PDT 24
Finished	Mar 24 02:47:37 PM PDT 24
Peak memory	200128 kb
Host	smart-d7fd4ee9-860d-4293-8c74-6865ddc65c1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257394507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2257394507
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.854209791
Short name	T364
Test name
Test status
Simulation time	65577245139 ps
CPU time	125.19 seconds
Started	Mar 24 02:47:02 PM PDT 24
Finished	Mar 24 02:49:08 PM PDT 24
Peak memory	200056 kb
Host	smart-87b7517d-8db8-4000-a032-aab2bf25199b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854209791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.854209791
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.3618631791
Short name	T1087
Test name
Test status
Simulation time	23464889066 ps
CPU time	39.69 seconds
Started	Mar 24 02:47:11 PM PDT 24
Finished	Mar 24 02:47:52 PM PDT 24
Peak memory	200128 kb
Host	smart-0795deea-3415-449b-91f0-c904f3b0e6f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618631791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3618631791
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.1980581324
Short name	T434
Test name
Test status
Simulation time	147499900167 ps
CPU time	272.99 seconds
Started	Mar 24 02:47:10 PM PDT 24
Finished	Mar 24 02:51:43 PM PDT 24
Peak memory	200064 kb
Host	smart-1670b338-3b13-4799-ad79-cf808ebd747f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980581324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1980581324
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.3143676915
Short name	T201
Test name
Test status
Simulation time	42257761712 ps
CPU time	82.97 seconds
Started	Mar 24 02:47:08 PM PDT 24
Finished	Mar 24 02:48:31 PM PDT 24
Peak memory	200208 kb
Host	smart-fa6b0253-324a-419b-98ff-3a609c84f667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143676915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3143676915
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.2083184348
Short name	T331
Test name
Test status
Simulation time	104632675417 ps
CPU time	53.66 seconds
Started	Mar 24 02:47:10 PM PDT 24
Finished	Mar 24 02:48:04 PM PDT 24
Peak memory	200052 kb
Host	smart-6bbd29bc-f35f-4721-a78d-a7c077863d69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083184348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2083184348
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.4246578389
Short name	T221
Test name
Test status
Simulation time	102536175323 ps
CPU time	138.35 seconds
Started	Mar 24 02:47:10 PM PDT 24
Finished	Mar 24 02:49:29 PM PDT 24
Peak memory	200396 kb
Host	smart-a1e98ef5-037c-4fb7-a389-c342887b08b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246578389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4246578389
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.3565713961
Short name	T903
Test name
Test status
Simulation time	353112584130 ps
CPU time	31.32 seconds
Started	Mar 24 02:47:10 PM PDT 24
Finished	Mar 24 02:47:42 PM PDT 24
Peak memory	200148 kb
Host	smart-8b84d71a-f475-49cc-97f0-8d93805c0d2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565713961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3565713961
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.1978953134
Short name	T686
Test name
Test status
Simulation time	35933035102 ps
CPU time	58.91 seconds
Started	Mar 24 02:47:10 PM PDT 24
Finished	Mar 24 02:48:09 PM PDT 24
Peak memory	200192 kb
Host	smart-89c78717-0c04-4c63-8e5f-ae07fc301484
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978953134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1978953134
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.210769503
Short name	T478
Test name
Test status
Simulation time	49558871 ps
CPU time	0.58 seconds
Started	Mar 24 02:44:08 PM PDT 24
Finished	Mar 24 02:44:10 PM PDT 24
Peak memory	195616 kb
Host	smart-bf70ba8d-1f5a-4a63-a57a-454d15f42cbd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210769503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.210769503
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.3480978613
Short name	T1066
Test name
Test status
Simulation time	174050030426 ps
CPU time	83.31 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:45:36 PM PDT 24
Peak memory	200096 kb
Host	smart-261c6b7b-25bc-4fc5-8ae0-37888bb44e91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480978613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3480978613
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/19.uart_intr.3324738324
Short name	T828
Test name
Test status
Simulation time	21689628917 ps
CPU time	10.48 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:44:28 PM PDT 24
Peak memory	198732 kb
Host	smart-1494573a-f1f1-4644-9cdb-915541425cc9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324738324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3324738324
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.1296927031
Short name	T534
Test name
Test status
Simulation time	108425610584 ps
CPU time	342.75 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:49:52 PM PDT 24
Peak memory	200168 kb
Host	smart-446c12a2-ef01-49e5-a67c-2c899ae748f6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1296927031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1296927031
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/19.uart_loopback.1150823982
Short name	T897
Test name
Test status
Simulation time	12153880889 ps
CPU time	24.12 seconds
Started	Mar 24 02:44:08 PM PDT 24
Finished	Mar 24 02:44:34 PM PDT 24
Peak memory	198916 kb
Host	smart-fe37acf2-549b-4ab9-8f75-c05e0e191638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150823982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1150823982
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.1692714331
Short name	T632
Test name
Test status
Simulation time	136114110460 ps
CPU time	273.98 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:48:43 PM PDT 24
Peak memory	200208 kb
Host	smart-c6bb6fda-7a15-4115-bd29-124df7dcdbcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692714331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1692714331
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/19.uart_perf.418513579
Short name	T643
Test name
Test status
Simulation time	26845292566 ps
CPU time	668.34 seconds
Started	Mar 24 02:44:16 PM PDT 24
Finished	Mar 24 02:55:25 PM PDT 24
Peak memory	200136 kb
Host	smart-23da5ac2-1020-4321-b146-bb7c4b005a5d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=418513579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.418513579
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.1692931508
Short name	T1024
Test name
Test status
Simulation time	7647624410 ps
CPU time	5.1 seconds
Started	Mar 24 02:44:11 PM PDT 24
Finished	Mar 24 02:44:17 PM PDT 24
Peak memory	199432 kb
Host	smart-de327521-e09e-46a3-b2f5-8fcb89e2de88
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1692931508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1692931508
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.2527944523
Short name	T463
Test name
Test status
Simulation time	33368085949 ps
CPU time	42.37 seconds
Started	Mar 24 02:44:04 PM PDT 24
Finished	Mar 24 02:44:47 PM PDT 24
Peak memory	200044 kb
Host	smart-708ac3bc-e09c-4367-8b62-f30f8b4b319e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527944523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2527944523
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.3533976853
Short name	T710
Test name
Test status
Simulation time	52749060529 ps
CPU time	62.3 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:45:13 PM PDT 24
Peak memory	195964 kb
Host	smart-70360b3c-b1be-499b-8545-776d898390ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533976853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3533976853
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.3444627205
Short name	T456
Test name
Test status
Simulation time	690658704 ps
CPU time	2.4 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:44:08 PM PDT 24
Peak memory	199536 kb
Host	smart-6e8fde85-09a9-4788-9d18-dd9bbb50fc4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3444627205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3444627205
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_stress_all.2646927410
Short name	T1046
Test name
Test status
Simulation time	95984598827 ps
CPU time	171.15 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:47:01 PM PDT 24
Peak memory	200124 kb
Host	smart-bf36eb9c-3eba-482a-bd89-90faebf57152
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646927410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2646927410
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.2194589725
Short name	T462
Test name
Test status
Simulation time	7628642910 ps
CPU time	9.77 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:44:26 PM PDT 24
Peak memory	199424 kb
Host	smart-baa754ad-bc06-4722-ae2f-57ed8b118fb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194589725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2194589725
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.1829305387
Short name	T467
Test name
Test status
Simulation time	27771828276 ps
CPU time	14.8 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:22 PM PDT 24
Peak memory	200112 kb
Host	smart-46bd6be1-1d8a-4bad-95a9-20a196110868
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829305387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1829305387
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.1256896670
Short name	T1001
Test name
Test status
Simulation time	144940664907 ps
CPU time	23.81 seconds
Started	Mar 24 02:47:14 PM PDT 24
Finished	Mar 24 02:47:39 PM PDT 24
Peak memory	200316 kb
Host	smart-46d538db-6abe-47d9-af3e-c59fa5c1cd4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256896670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1256896670
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.579953943
Short name	T517
Test name
Test status
Simulation time	3055524043 ps
CPU time	5.44 seconds
Started	Mar 24 02:47:17 PM PDT 24
Finished	Mar 24 02:47:23 PM PDT 24
Peak memory	200108 kb
Host	smart-eb2b48e2-0555-420a-8e88-1618d340d532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579953943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.579953943
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.1023400108
Short name	T883
Test name
Test status
Simulation time	30152739886 ps
CPU time	21.02 seconds
Started	Mar 24 02:47:12 PM PDT 24
Finished	Mar 24 02:47:33 PM PDT 24
Peak memory	200024 kb
Host	smart-139f92f2-6e6a-468d-b5ce-a6c7b11d0875
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023400108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1023400108
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.158484196
Short name	T160
Test name
Test status
Simulation time	82461012054 ps
CPU time	483.99 seconds
Started	Mar 24 02:47:14 PM PDT 24
Finished	Mar 24 02:55:19 PM PDT 24
Peak memory	200116 kb
Host	smart-dc261ca7-8e04-4db7-bae6-ab4ac2b8a77e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158484196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.158484196
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.1005874441
Short name	T916
Test name
Test status
Simulation time	69912989667 ps
CPU time	28.97 seconds
Started	Mar 24 02:47:16 PM PDT 24
Finished	Mar 24 02:47:45 PM PDT 24
Peak memory	199940 kb
Host	smart-798b1800-67bb-4e51-8901-9e50071416b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005874441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1005874441
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.30766629
Short name	T968
Test name
Test status
Simulation time	66143759350 ps
CPU time	94.38 seconds
Started	Mar 24 02:47:13 PM PDT 24
Finished	Mar 24 02:48:48 PM PDT 24
Peak memory	200172 kb
Host	smart-c4e0a33b-f0cc-4f66-b35f-835247a9528b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30766629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.30766629
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.4094821418
Short name	T909
Test name
Test status
Simulation time	35600890108 ps
CPU time	32.67 seconds
Started	Mar 24 02:47:15 PM PDT 24
Finished	Mar 24 02:47:48 PM PDT 24
Peak memory	200120 kb
Host	smart-22628e67-2920-462f-a7ed-34fa659bfd1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094821418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4094821418
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.1932959722
Short name	T247
Test name
Test status
Simulation time	30664437763 ps
CPU time	17.83 seconds
Started	Mar 24 02:47:12 PM PDT 24
Finished	Mar 24 02:47:30 PM PDT 24
Peak memory	200140 kb
Host	smart-51ba56e0-ce62-46d7-a223-891fd8c05139
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932959722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1932959722
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.2479624321
Short name	T748
Test name
Test status
Simulation time	152804217719 ps
CPU time	53.77 seconds
Started	Mar 24 02:47:16 PM PDT 24
Finished	Mar 24 02:48:10 PM PDT 24
Peak memory	200112 kb
Host	smart-f3c8af86-f6e0-43fe-9dcc-bc7f7ac3a4da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479624321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2479624321
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.2184533361
Short name	T403
Test name
Test status
Simulation time	39584923 ps
CPU time	0.59 seconds
Started	Mar 24 02:43:20 PM PDT 24
Finished	Mar 24 02:43:21 PM PDT 24
Peak memory	195668 kb
Host	smart-c3dca120-84fb-439a-a851-38dfc9fe3524
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184533361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2184533361
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.2136534969
Short name	T8
Test name
Test status
Simulation time	83396774414 ps
CPU time	137.77 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:45:48 PM PDT 24
Peak memory	200152 kb
Host	smart-497e6efa-6fe1-4e7d-bffe-06021c57abed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136534969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2136534969
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.2594815398
Short name	T176
Test name
Test status
Simulation time	40636615276 ps
CPU time	21.25 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:43:47 PM PDT 24
Peak memory	200112 kb
Host	smart-5b29f7ce-98f9-4f43-81a8-274048921256
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594815398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2594815398
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.3719651550
Short name	T936
Test name
Test status
Simulation time	17954410053 ps
CPU time	33.38 seconds
Started	Mar 24 02:43:15 PM PDT 24
Finished	Mar 24 02:43:51 PM PDT 24
Peak memory	200292 kb
Host	smart-7f2c04bf-85a2-4ea5-8a37-09a8b0f11ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719651550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3719651550
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_intr.3990599066
Short name	T541
Test name
Test status
Simulation time	9632766671 ps
CPU time	3.79 seconds
Started	Mar 24 02:43:29 PM PDT 24
Finished	Mar 24 02:43:33 PM PDT 24
Peak memory	197920 kb
Host	smart-ec4663cb-14ae-44b7-95f3-b763c9770dad
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990599066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3990599066
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.363361977
Short name	T1063
Test name
Test status
Simulation time	98955413898 ps
CPU time	243.21 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:47:29 PM PDT 24
Peak memory	200120 kb
Host	smart-d3d5dcd5-4644-42bf-8978-9a6c21258a16
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=363361977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.363361977
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.3862900573
Short name	T701
Test name
Test status
Simulation time	2724391192 ps
CPU time	4.04 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:43:26 PM PDT 24
Peak memory	198560 kb
Host	smart-94070bdc-8cdf-4570-844b-1451aba07f97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862900573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3862900573
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.1130866053
Short name	T265
Test name
Test status
Simulation time	15438956363 ps
CPU time	14.76 seconds
Started	Mar 24 02:43:18 PM PDT 24
Finished	Mar 24 02:43:34 PM PDT 24
Peak memory	199080 kb
Host	smart-e6154a54-4747-45fb-bf8c-218f4ae69cca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130866053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1130866053
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.587291675
Short name	T336
Test name
Test status
Simulation time	32357464515 ps
CPU time	101.45 seconds
Started	Mar 24 02:43:20 PM PDT 24
Finished	Mar 24 02:45:02 PM PDT 24
Peak memory	200084 kb
Host	smart-7ee87c23-e90b-4aa6-9b1b-f7bd17fd78de
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=587291675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.587291675
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.3237909784
Short name	T389
Test name
Test status
Simulation time	4138495978 ps
CPU time	4.37 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:43:28 PM PDT 24
Peak memory	198084 kb
Host	smart-132d75d6-c7da-4b4f-abfa-ed65bf231409
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3237909784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3237909784
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.4255873990
Short name	T729
Test name
Test status
Simulation time	120580142587 ps
CPU time	12.61 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:43:38 PM PDT 24
Peak memory	199892 kb
Host	smart-39211a85-016d-44ba-8a43-59ca3bd169e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255873990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4255873990
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.473966286
Short name	T423
Test name
Test status
Simulation time	725780393 ps
CPU time	1.32 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:43:25 PM PDT 24
Peak memory	195532 kb
Host	smart-e8d35eb6-7087-49c5-80bc-5f4d9b42002a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473966286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.473966286
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.1312505536
Short name	T109
Test name
Test status
Simulation time	128795546 ps
CPU time	0.78 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:28 PM PDT 24
Peak memory	218752 kb
Host	smart-b5057ad5-2086-4d31-a314-b03acbd8c68d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312505536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1312505536
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/2.uart_smoke.2564024975
Short name	T311
Test name
Test status
Simulation time	5481617214 ps
CPU time	8.4 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:43:33 PM PDT 24
Peak memory	199884 kb
Host	smart-c4b02af1-00f8-4e17-bd99-2a7f0b6b2570
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564024975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2564024975
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_stress_all.3083023525
Short name	T422
Test name
Test status
Simulation time	37289418365 ps
CPU time	173.16 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:46:15 PM PDT 24
Peak memory	200064 kb
Host	smart-7e601753-ef00-4858-8c4e-fa7f3b202691
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083023525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3083023525
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.2561088260
Short name	T1037
Test name
Test status
Simulation time	1021204668 ps
CPU time	1.45 seconds
Started	Mar 24 02:43:14 PM PDT 24
Finished	Mar 24 02:43:18 PM PDT 24
Peak memory	197816 kb
Host	smart-dd3908d0-cb29-4997-b309-e7e645a23d60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561088260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2561088260
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.3085330391
Short name	T908
Test name
Test status
Simulation time	101618180890 ps
CPU time	94.01 seconds
Started	Mar 24 02:43:13 PM PDT 24
Finished	Mar 24 02:44:50 PM PDT 24
Peak memory	200104 kb
Host	smart-54508e40-f5a0-4c06-b00d-8ffaba6ac4d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085330391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3085330391
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_alert_test.2228184104
Short name	T752
Test name
Test status
Simulation time	14235982 ps
CPU time	0.57 seconds
Started	Mar 24 02:44:13 PM PDT 24
Finished	Mar 24 02:44:14 PM PDT 24
Peak memory	195644 kb
Host	smart-52282534-61cb-4b0a-b846-9fd8afa17fe6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228184104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2228184104
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.1338073076
Short name	T629
Test name
Test status
Simulation time	15532563685 ps
CPU time	24.52 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:44:34 PM PDT 24
Peak memory	199608 kb
Host	smart-a214b4ea-bede-431d-8738-c4650aa17cd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338073076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1338073076
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.2263972437
Short name	T156
Test name
Test status
Simulation time	19134581588 ps
CPU time	9.3 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	199856 kb
Host	smart-83d51b00-8478-4ec6-a18b-2bbeb54eedb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263972437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2263972437
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_intr.2204256510
Short name	T966
Test name
Test status
Simulation time	7424287543 ps
CPU time	5.4 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	200008 kb
Host	smart-4eb09f05-bc31-41f0-ae75-b3a6db503ced
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204256510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2204256510
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.760967961
Short name	T1026
Test name
Test status
Simulation time	102011694151 ps
CPU time	880.35 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:58:57 PM PDT 24
Peak memory	200088 kb
Host	smart-29b208d3-b999-404b-a3e9-781dd1a6853e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=760967961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.760967961
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.4142365964
Short name	T709
Test name
Test status
Simulation time	319464995 ps
CPU time	1.06 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:44:17 PM PDT 24
Peak memory	198588 kb
Host	smart-c6a4fd8c-d3d4-4004-a91b-3e0e660794f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142365964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.4142365964
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.1709716924
Short name	T793
Test name
Test status
Simulation time	71471718845 ps
CPU time	63.51 seconds
Started	Mar 24 02:44:11 PM PDT 24
Finished	Mar 24 02:45:15 PM PDT 24
Peak memory	215604 kb
Host	smart-24b2d7d4-1dba-47bb-a9f7-ebf77a1b4348
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709716924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1709716924
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.1742069704
Short name	T1007
Test name
Test status
Simulation time	8317770627 ps
CPU time	122.26 seconds
Started	Mar 24 02:44:13 PM PDT 24
Finished	Mar 24 02:46:15 PM PDT 24
Peak memory	200144 kb
Host	smart-9abdadbf-45f6-4029-bfb8-914820f9fa1f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1742069704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1742069704
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.719787900
Short name	T513
Test name
Test status
Simulation time	6474717140 ps
CPU time	6.87 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:44:24 PM PDT 24
Peak memory	198212 kb
Host	smart-3ec39299-5590-45a1-91cd-7d457da33598
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=719787900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.719787900
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.875845922
Short name	T185
Test name
Test status
Simulation time	23202814299 ps
CPU time	21.46 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:29 PM PDT 24
Peak memory	200096 kb
Host	smart-c4da2bf6-45a0-4533-9063-536f7bf3460b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875845922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.875845922
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.1944130821
Short name	T29
Test name
Test status
Simulation time	3156808959 ps
CPU time	1.47 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	196212 kb
Host	smart-313ef311-62a1-46c6-a970-ea23ba1c7d1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944130821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1944130821
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.882232311
Short name	T1049
Test name
Test status
Simulation time	482850000 ps
CPU time	1.22 seconds
Started	Mar 24 02:44:06 PM PDT 24
Finished	Mar 24 02:44:07 PM PDT 24
Peak memory	198640 kb
Host	smart-58c8fdd7-5781-4581-a81a-4bab92b58f64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882232311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.882232311
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.78447977
Short name	T976
Test name
Test status
Simulation time	241028771823 ps
CPU time	792.85 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:57:29 PM PDT 24
Peak memory	200144 kb
Host	smart-7b2fe079-8a6c-46f7-9f57-75853a9afa3e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78447977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.78447977
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_stress_all_with_rand_reset.1171997244
Short name	T860
Test name
Test status
Simulation time	316366710825 ps
CPU time	818.24 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:57:56 PM PDT 24
Peak memory	224128 kb
Host	smart-23e1742b-9fc3-4abf-9619-8295a910a07d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171997244 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1171997244
Directory	/workspace/20.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.278113918
Short name	T770
Test name
Test status
Simulation time	699981305 ps
CPU time	3.2 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:11 PM PDT 24
Peak memory	198908 kb
Host	smart-5fe82dea-e8d3-4e4b-b756-b8bb04b928c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=278113918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.278113918
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.1123103216
Short name	T525
Test name
Test status
Simulation time	3273541981 ps
CPU time	5.31 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:18 PM PDT 24
Peak memory	197132 kb
Host	smart-f4e4795a-598c-46ca-9de3-2c815971d797
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123103216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1123103216
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.3606731464
Short name	T145
Test name
Test status
Simulation time	86682116837 ps
CPU time	106.81 seconds
Started	Mar 24 02:47:18 PM PDT 24
Finished	Mar 24 02:49:05 PM PDT 24
Peak memory	200172 kb
Host	smart-afe7b7fa-4193-445a-b20d-ea91b4924d65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606731464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3606731464
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.3958401131
Short name	T332
Test name
Test status
Simulation time	22624276201 ps
CPU time	18.96 seconds
Started	Mar 24 02:47:17 PM PDT 24
Finished	Mar 24 02:47:37 PM PDT 24
Peak memory	200168 kb
Host	smart-86987af5-e335-419d-a9ac-c0169221c2c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3958401131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3958401131
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.26141213
Short name	T231
Test name
Test status
Simulation time	45831899946 ps
CPU time	14.04 seconds
Started	Mar 24 02:47:19 PM PDT 24
Finished	Mar 24 02:47:33 PM PDT 24
Peak memory	199380 kb
Host	smart-507df662-622f-421d-b791-d044a814ffc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26141213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.26141213
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.17565404
Short name	T869
Test name
Test status
Simulation time	69737929534 ps
CPU time	111.21 seconds
Started	Mar 24 02:47:18 PM PDT 24
Finished	Mar 24 02:49:10 PM PDT 24
Peak memory	200096 kb
Host	smart-2a71d2a4-969e-483e-a809-00d0a43f7040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17565404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.17565404
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.1725239926
Short name	T504
Test name
Test status
Simulation time	27274936833 ps
CPU time	24.3 seconds
Started	Mar 24 02:47:17 PM PDT 24
Finished	Mar 24 02:47:41 PM PDT 24
Peak memory	200120 kb
Host	smart-7743c8bb-0995-48cd-96e3-255f08802c3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725239926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1725239926
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.3945137073
Short name	T817
Test name
Test status
Simulation time	62385402656 ps
CPU time	130.58 seconds
Started	Mar 24 02:47:21 PM PDT 24
Finished	Mar 24 02:49:32 PM PDT 24
Peak memory	200148 kb
Host	smart-d446559e-37e7-4f9e-a39e-8ba840432e10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945137073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3945137073
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.4217424819
Short name	T602
Test name
Test status
Simulation time	59329458303 ps
CPU time	100.08 seconds
Started	Mar 24 02:47:18 PM PDT 24
Finished	Mar 24 02:48:58 PM PDT 24
Peak memory	200124 kb
Host	smart-49c18fea-b33b-449d-9fe6-8c78594d3b70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217424819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4217424819
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.2272515551
Short name	T232
Test name
Test status
Simulation time	55933630678 ps
CPU time	46.71 seconds
Started	Mar 24 02:47:17 PM PDT 24
Finished	Mar 24 02:48:04 PM PDT 24
Peak memory	200184 kb
Host	smart-05149b91-cd02-4c00-952b-f6e586c8127d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272515551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2272515551
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.2163717204
Short name	T1094
Test name
Test status
Simulation time	35446551556 ps
CPU time	13.25 seconds
Started	Mar 24 02:47:18 PM PDT 24
Finished	Mar 24 02:47:32 PM PDT 24
Peak memory	200084 kb
Host	smart-cbae730e-8fc5-4df3-a298-66e283d87f9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163717204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2163717204
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.3993130238
Short name	T665
Test name
Test status
Simulation time	143078911781 ps
CPU time	48.19 seconds
Started	Mar 24 02:47:23 PM PDT 24
Finished	Mar 24 02:48:11 PM PDT 24
Peak memory	199844 kb
Host	smart-55fc310a-f35a-4178-9c44-b3fcc6422967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993130238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3993130238
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.2204687326
Short name	T649
Test name
Test status
Simulation time	32949482 ps
CPU time	0.55 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:13 PM PDT 24
Peak memory	195644 kb
Host	smart-efb5bcdb-b500-45e1-85af-5cd7485e8a5e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204687326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2204687326
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.3391366387
Short name	T511
Test name
Test status
Simulation time	162510882974 ps
CPU time	68.33 seconds
Started	Mar 24 02:44:11 PM PDT 24
Finished	Mar 24 02:45:20 PM PDT 24
Peak memory	200168 kb
Host	smart-69c5c78f-5f91-4397-821c-4b7edeead8be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391366387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3391366387
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.991319332
Short name	T876
Test name
Test status
Simulation time	173969846629 ps
CPU time	113.7 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:46:01 PM PDT 24
Peak memory	200184 kb
Host	smart-fc18d0d0-074d-4461-91e8-07d0e87de149
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=991319332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.991319332
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.2947333339
Short name	T413
Test name
Test status
Simulation time	116522859088 ps
CPU time	46.17 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:45:05 PM PDT 24
Peak memory	200088 kb
Host	smart-19582018-cfab-42e2-b821-760ed0278ba3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947333339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2947333339
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_intr.3233504565
Short name	T1114
Test name
Test status
Simulation time	78396484204 ps
CPU time	89.11 seconds
Started	Mar 24 02:44:08 PM PDT 24
Finished	Mar 24 02:45:38 PM PDT 24
Peak memory	200004 kb
Host	smart-363d92c9-8292-4c1c-bd50-02e4ebabfe39
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233504565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3233504565
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.1760232821
Short name	T898
Test name
Test status
Simulation time	144629134201 ps
CPU time	660.86 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:55:08 PM PDT 24
Peak memory	200076 kb
Host	smart-099a2b17-c514-496f-99c2-9ceaa99576c1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1760232821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1760232821
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.2450972535
Short name	T595
Test name
Test status
Simulation time	708103329 ps
CPU time	0.72 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:19 PM PDT 24
Peak memory	195968 kb
Host	smart-c5c81059-ec1d-44ce-907c-1a369534c17d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450972535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2450972535
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.2000650463
Short name	T856
Test name
Test status
Simulation time	65948979453 ps
CPU time	151.82 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:46:51 PM PDT 24
Peak memory	199164 kb
Host	smart-a15e921a-53f6-472f-818a-d0d4e770834f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000650463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2000650463
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_perf.384058497
Short name	T798
Test name
Test status
Simulation time	31656149203 ps
CPU time	1480.42 seconds
Started	Mar 24 02:44:13 PM PDT 24
Finished	Mar 24 03:08:54 PM PDT 24
Peak memory	200092 kb
Host	smart-48567271-9d63-4ac6-8426-2315d92a8e07
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=384058497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.384058497
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.3511049735
Short name	T1067
Test name
Test status
Simulation time	1700886449 ps
CPU time	2.63 seconds
Started	Mar 24 02:44:06 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	198104 kb
Host	smart-1641d6e8-853a-41c5-bf07-a0405fc8a343
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3511049735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3511049735
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.780677735
Short name	T1112
Test name
Test status
Simulation time	55510164427 ps
CPU time	90.47 seconds
Started	Mar 24 02:44:13 PM PDT 24
Finished	Mar 24 02:45:44 PM PDT 24
Peak memory	200100 kb
Host	smart-fd3b5141-148a-45ea-a239-0b50d0d20723
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780677735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.780677735
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.244592341
Short name	T639
Test name
Test status
Simulation time	86957749645 ps
CPU time	35.31 seconds
Started	Mar 24 02:44:14 PM PDT 24
Finished	Mar 24 02:44:49 PM PDT 24
Peak memory	195964 kb
Host	smart-08a053b3-ab2e-4c28-aee6-efb6117f60b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244592341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.244592341
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.3651934653
Short name	T340
Test name
Test status
Simulation time	5557753058 ps
CPU time	19.62 seconds
Started	Mar 24 02:44:05 PM PDT 24
Finished	Mar 24 02:44:25 PM PDT 24
Peak memory	199912 kb
Host	smart-b80f98e4-d74c-46d7-b3d6-8b472cc34c9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651934653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3651934653
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_stress_all.4144012053
Short name	T363
Test name
Test status
Simulation time	29451384446 ps
CPU time	19.96 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:44:29 PM PDT 24
Peak memory	200184 kb
Host	smart-6da4c4e9-70bf-4d15-b157-20ce25d98d54
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144012053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4144012053
Directory	/workspace/21.uart_stress_all/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.1840057470
Short name	T474
Test name
Test status
Simulation time	8335540808 ps
CPU time	18.27 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:31 PM PDT 24
Peak memory	199952 kb
Host	smart-e0395153-c081-4ee1-b499-7951793c6e5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840057470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1840057470
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.789269667
Short name	T77
Test name
Test status
Simulation time	76142180803 ps
CPU time	175.36 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:47:15 PM PDT 24
Peak memory	200080 kb
Host	smart-758c0233-c657-4d14-a4f2-38e9be7da34e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789269667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.789269667
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.1813714011
Short name	T264
Test name
Test status
Simulation time	46204895991 ps
CPU time	26.23 seconds
Started	Mar 24 02:47:22 PM PDT 24
Finished	Mar 24 02:47:48 PM PDT 24
Peak memory	200140 kb
Host	smart-c3a5bde5-df3c-4597-824b-b35e5f87082b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813714011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1813714011
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.1442773851
Short name	T175
Test name
Test status
Simulation time	20511753938 ps
CPU time	38.39 seconds
Started	Mar 24 02:47:22 PM PDT 24
Finished	Mar 24 02:48:00 PM PDT 24
Peak memory	200188 kb
Host	smart-b1ca6c22-933b-46d1-9521-aa7083cd6c3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442773851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1442773851
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.1052586123
Short name	T131
Test name
Test status
Simulation time	8584141949 ps
CPU time	14.14 seconds
Started	Mar 24 02:47:22 PM PDT 24
Finished	Mar 24 02:47:37 PM PDT 24
Peak memory	200092 kb
Host	smart-1420add7-7048-4f60-955b-3ea44082aeb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052586123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1052586123
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.1493280017
Short name	T862
Test name
Test status
Simulation time	38220039339 ps
CPU time	19.28 seconds
Started	Mar 24 02:47:23 PM PDT 24
Finished	Mar 24 02:47:43 PM PDT 24
Peak memory	200124 kb
Host	smart-2c80b7fa-1da1-4584-a760-ba8d0dc65cb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493280017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1493280017
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.443491271
Short name	T861
Test name
Test status
Simulation time	44644609789 ps
CPU time	52.76 seconds
Started	Mar 24 02:47:23 PM PDT 24
Finished	Mar 24 02:48:15 PM PDT 24
Peak memory	200112 kb
Host	smart-4f612bcd-f8b6-4214-9ead-dfc908962ce4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443491271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.443491271
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.3483464876
Short name	T734
Test name
Test status
Simulation time	77940018564 ps
CPU time	86.99 seconds
Started	Mar 24 02:47:22 PM PDT 24
Finished	Mar 24 02:48:49 PM PDT 24
Peak memory	200080 kb
Host	smart-1357f90a-ec75-4bd9-a582-416bd1c2cd69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483464876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3483464876
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.2960101554
Short name	T172
Test name
Test status
Simulation time	122629028653 ps
CPU time	51.95 seconds
Started	Mar 24 02:47:22 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200108 kb
Host	smart-41f6f74a-1a2d-483f-bfbb-89b7c24519be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960101554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2960101554
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.1292474379
Short name	T584
Test name
Test status
Simulation time	59755617318 ps
CPU time	30.98 seconds
Started	Mar 24 02:47:24 PM PDT 24
Finished	Mar 24 02:47:55 PM PDT 24
Peak memory	200172 kb
Host	smart-b70630d1-dd8e-45fb-93c6-8928572f7ee5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292474379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1292474379
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.3828230672
Short name	T134
Test name
Test status
Simulation time	118902079956 ps
CPU time	205.08 seconds
Started	Mar 24 02:47:24 PM PDT 24
Finished	Mar 24 02:50:49 PM PDT 24
Peak memory	200168 kb
Host	smart-68100d9c-8e34-445c-8b97-703fbe18be19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828230672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3828230672
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.4104379179
Short name	T834
Test name
Test status
Simulation time	20022426 ps
CPU time	0.53 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	194556 kb
Host	smart-a6cf11bd-36f0-4534-b9cf-5bf67beb9887
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104379179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4104379179
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.856744933
Short name	T465
Test name
Test status
Simulation time	245421733504 ps
CPU time	374.92 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:50:34 PM PDT 24
Peak memory	200108 kb
Host	smart-832014f3-8c66-49a1-9026-f0f831c3b730
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856744933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.856744933
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.3620433457
Short name	T849
Test name
Test status
Simulation time	21455570605 ps
CPU time	10.9 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:23 PM PDT 24
Peak memory	200048 kb
Host	smart-0cd44213-e32e-4be8-b7e8-3ce2a1f6fd2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620433457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3620433457
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.1136235900
Short name	T193
Test name
Test status
Simulation time	15928184471 ps
CPU time	14.67 seconds
Started	Mar 24 02:44:13 PM PDT 24
Finished	Mar 24 02:44:28 PM PDT 24
Peak memory	199376 kb
Host	smart-28793624-2c30-4946-a6bd-30c5d51e39fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136235900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1136235900
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.3677378370
Short name	T996
Test name
Test status
Simulation time	15143933733 ps
CPU time	27.63 seconds
Started	Mar 24 02:44:14 PM PDT 24
Finished	Mar 24 02:44:41 PM PDT 24
Peak memory	200096 kb
Host	smart-e710b7fa-cf75-493d-b83a-c2b9ad930d01
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677378370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3677378370
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.3706776437
Short name	T281
Test name
Test status
Simulation time	115303485059 ps
CPU time	237.37 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:48:05 PM PDT 24
Peak memory	200040 kb
Host	smart-889cbb57-9902-4591-9141-43009933fe1d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3706776437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3706776437
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.1391743702
Short name	T435
Test name
Test status
Simulation time	3968565542 ps
CPU time	2.5 seconds
Started	Mar 24 02:44:10 PM PDT 24
Finished	Mar 24 02:44:13 PM PDT 24
Peak memory	198360 kb
Host	smart-6afda43b-307d-4e05-bc61-2fec62d1efa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391743702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1391743702
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.1967826792
Short name	T1096
Test name
Test status
Simulation time	81417140323 ps
CPU time	32.83 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:44:42 PM PDT 24
Peak memory	199692 kb
Host	smart-06c16942-3ee7-427f-85e8-bd80ca6417ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967826792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1967826792
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.2074521826
Short name	T404
Test name
Test status
Simulation time	6990932882 ps
CPU time	104.37 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:45:57 PM PDT 24
Peak memory	200216 kb
Host	smart-20555094-7b0b-4956-a742-397707c9996d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2074521826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2074521826
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.1961716819
Short name	T683
Test name
Test status
Simulation time	6089126611 ps
CPU time	36.8 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	199508 kb
Host	smart-90ba8650-4bce-413a-a5c0-bdc3337b5098
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1961716819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1961716819
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.2315976240
Short name	T421
Test name
Test status
Simulation time	27910546827 ps
CPU time	40.51 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	200176 kb
Host	smart-c073a531-2052-40bd-b57f-1726db424642
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315976240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2315976240
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.1797197944
Short name	T638
Test name
Test status
Simulation time	42948579323 ps
CPU time	34 seconds
Started	Mar 24 02:44:14 PM PDT 24
Finished	Mar 24 02:44:48 PM PDT 24
Peak memory	196248 kb
Host	smart-a8a6d7f3-b24a-405d-8cc2-24e3f00640cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797197944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1797197944
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.202513394
Short name	T291
Test name
Test status
Simulation time	504965000 ps
CPU time	2.05 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	199196 kb
Host	smart-356d3055-2a8f-4f04-acdf-ea5d8d5d46ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202513394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.202513394
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_stress_all.1329306425
Short name	T127
Test name
Test status
Simulation time	568797638686 ps
CPU time	277.5 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:48:47 PM PDT 24
Peak memory	216452 kb
Host	smart-1a87d115-3e0f-4c0b-b3a5-56b96ab4bc1e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329306425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1329306425
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.573756458
Short name	T427
Test name
Test status
Simulation time	13291329893 ps
CPU time	8.77 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:44:18 PM PDT 24
Peak memory	200052 kb
Host	smart-e329c943-bd7f-4354-b037-c18cba5e9dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573756458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.573756458
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.2630685078
Short name	T864
Test name
Test status
Simulation time	44262245143 ps
CPU time	34.39 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:47 PM PDT 24
Peak memory	200112 kb
Host	smart-3dd6653f-f3bb-4032-b58a-561b1746652a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630685078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2630685078
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.1746749167
Short name	T228
Test name
Test status
Simulation time	69943821571 ps
CPU time	35.34 seconds
Started	Mar 24 02:47:23 PM PDT 24
Finished	Mar 24 02:47:58 PM PDT 24
Peak memory	200188 kb
Host	smart-1abf4887-4caa-4a81-ab2c-cc0b8cce0a23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746749167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1746749167
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.3050943847
Short name	T1011
Test name
Test status
Simulation time	133917913868 ps
CPU time	12.23 seconds
Started	Mar 24 02:47:21 PM PDT 24
Finished	Mar 24 02:47:34 PM PDT 24
Peak memory	200028 kb
Host	smart-db59d729-e3cd-4892-a052-9beba87f5ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050943847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3050943847
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.4051456332
Short name	T692
Test name
Test status
Simulation time	177980385244 ps
CPU time	71.34 seconds
Started	Mar 24 02:47:28 PM PDT 24
Finished	Mar 24 02:48:39 PM PDT 24
Peak memory	200164 kb
Host	smart-a2c587ae-08bd-434e-a78c-33e157602f8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051456332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4051456332
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.783603028
Short name	T928
Test name
Test status
Simulation time	111382557939 ps
CPU time	182.04 seconds
Started	Mar 24 02:47:28 PM PDT 24
Finished	Mar 24 02:50:30 PM PDT 24
Peak memory	200016 kb
Host	smart-16f22293-d9da-480d-b9ac-2bd611748cef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783603028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.783603028
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.1382721304
Short name	T194
Test name
Test status
Simulation time	37570516040 ps
CPU time	29.85 seconds
Started	Mar 24 02:47:27 PM PDT 24
Finished	Mar 24 02:47:57 PM PDT 24
Peak memory	200144 kb
Host	smart-4de86504-616b-4c34-8b2c-47117509350d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382721304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1382721304
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.3140042585
Short name	T1078
Test name
Test status
Simulation time	46924081587 ps
CPU time	53.31 seconds
Started	Mar 24 02:47:32 PM PDT 24
Finished	Mar 24 02:48:26 PM PDT 24
Peak memory	200152 kb
Host	smart-16edac40-224f-4f2c-bc52-1c36d57266a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140042585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3140042585
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.3493649962
Short name	T1018
Test name
Test status
Simulation time	152512210065 ps
CPU time	315.95 seconds
Started	Mar 24 02:47:29 PM PDT 24
Finished	Mar 24 02:52:45 PM PDT 24
Peak memory	200184 kb
Host	smart-f3dc70af-c9f1-4b9d-b06b-7cecad61aecf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493649962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3493649962
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_alert_test.3195541082
Short name	T1030
Test name
Test status
Simulation time	14165171 ps
CPU time	0.55 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	195628 kb
Host	smart-287c7486-189f-4615-b954-59d0b85abec0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195541082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3195541082
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.1022230607
Short name	T971
Test name
Test status
Simulation time	30807573537 ps
CPU time	26.91 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:39 PM PDT 24
Peak memory	200092 kb
Host	smart-81d6ba3c-9972-4959-81a4-13b5ec6af06f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022230607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1022230607
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.3044952927
Short name	T482
Test name
Test status
Simulation time	65789986835 ps
CPU time	46.27 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:45:06 PM PDT 24
Peak memory	200008 kb
Host	smart-175e60da-19b8-41cb-9419-665812d5f85f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044952927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3044952927
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.331272013
Short name	T1009
Test name
Test status
Simulation time	12728291984 ps
CPU time	10.04 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:30 PM PDT 24
Peak memory	200040 kb
Host	smart-f791f504-d067-4d5d-87a4-ed199c67a14b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331272013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.331272013
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_intr.337783716
Short name	T890
Test name
Test status
Simulation time	51746637309 ps
CPU time	89.84 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:45:48 PM PDT 24
Peak memory	199936 kb
Host	smart-2225a23e-1046-4228-8f8e-2774a0cdfe11
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337783716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.337783716
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.1037362205
Short name	T514
Test name
Test status
Simulation time	25910318880 ps
CPU time	210.39 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:47:46 PM PDT 24
Peak memory	200164 kb
Host	smart-a0e4b33e-d35e-4b67-b0f7-0b4824e3b443
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1037362205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1037362205
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.700246963
Short name	T720
Test name
Test status
Simulation time	12117915604 ps
CPU time	14.02 seconds
Started	Mar 24 02:44:09 PM PDT 24
Finished	Mar 24 02:44:24 PM PDT 24
Peak memory	199940 kb
Host	smart-6fa25ce2-642b-444a-9c62-f15ac33071c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700246963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.700246963
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.674600765
Short name	T979
Test name
Test status
Simulation time	15678658310 ps
CPU time	27.27 seconds
Started	Mar 24 02:44:07 PM PDT 24
Finished	Mar 24 02:44:35 PM PDT 24
Peak memory	200228 kb
Host	smart-3bcb6aa2-ec85-4b57-af07-20f2f72d3e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674600765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.674600765
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_perf.3878575875
Short name	T554
Test name
Test status
Simulation time	22235446604 ps
CPU time	266.93 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:48:45 PM PDT 24
Peak memory	200088 kb
Host	smart-c1f54545-bc34-4713-bccf-90f8ef50a2c2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3878575875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3878575875
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.50254136
Short name	T374
Test name
Test status
Simulation time	2028044948 ps
CPU time	3.81 seconds
Started	Mar 24 02:44:08 PM PDT 24
Finished	Mar 24 02:44:12 PM PDT 24
Peak memory	198096 kb
Host	smart-de4a4e6c-f505-4841-a848-8463ad82d292
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=50254136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.50254136
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.3461323264
Short name	T457
Test name
Test status
Simulation time	36884799714 ps
CPU time	62.97 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:45:15 PM PDT 24
Peak memory	196232 kb
Host	smart-885d5e1c-909e-4321-8d4a-153a6f1b1f5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461323264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3461323264
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.3404813286
Short name	T758
Test name
Test status
Simulation time	576933133 ps
CPU time	1.73 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:44:18 PM PDT 24
Peak memory	199948 kb
Host	smart-f8ce3472-afd5-4aa0-a1a0-5da9afd23f48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404813286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3404813286
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_stress_all_with_rand_reset.1793703851
Short name	T39
Test name
Test status
Simulation time	98179567775 ps
CPU time	273.18 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:48:49 PM PDT 24
Peak memory	216668 kb
Host	smart-7c02ac2b-d50b-4f54-862f-c3a42c3c2bef
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793703851 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1793703851
Directory	/workspace/23.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.1528107431
Short name	T515
Test name
Test status
Simulation time	884995575 ps
CPU time	3.14 seconds
Started	Mar 24 02:44:11 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	198888 kb
Host	smart-f7b969f4-c952-468c-b7f6-295f277f3b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528107431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1528107431
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.1550688344
Short name	T1104
Test name
Test status
Simulation time	17962502011 ps
CPU time	72.96 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:45:33 PM PDT 24
Peak memory	200068 kb
Host	smart-4c33ec6d-868e-462a-b972-c03c3ac4a6ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550688344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1550688344
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.3888730279
Short name	T892
Test name
Test status
Simulation time	156496493320 ps
CPU time	58.86 seconds
Started	Mar 24 02:47:28 PM PDT 24
Finished	Mar 24 02:48:28 PM PDT 24
Peak memory	200088 kb
Host	smart-d4fabd22-6c4b-4450-a3fd-c0cf80b25de3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888730279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3888730279
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.28345760
Short name	T224
Test name
Test status
Simulation time	265151813258 ps
CPU time	23.55 seconds
Started	Mar 24 02:47:27 PM PDT 24
Finished	Mar 24 02:47:51 PM PDT 24
Peak memory	200136 kb
Host	smart-a4ff0c3c-59dc-45df-af40-898a7767996e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28345760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.28345760
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.1787870926
Short name	T944
Test name
Test status
Simulation time	8157058508 ps
CPU time	16.44 seconds
Started	Mar 24 02:47:28 PM PDT 24
Finished	Mar 24 02:47:44 PM PDT 24
Peak memory	200200 kb
Host	smart-97e61138-9d21-4c66-b355-a0b302b364f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787870926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1787870926
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.360173181
Short name	T213
Test name
Test status
Simulation time	62697019571 ps
CPU time	42.5 seconds
Started	Mar 24 02:47:31 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200188 kb
Host	smart-1504b949-08b2-426a-9d63-df8d1139c63e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360173181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.360173181
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.1568274322
Short name	T471
Test name
Test status
Simulation time	94767436830 ps
CPU time	163.69 seconds
Started	Mar 24 02:47:32 PM PDT 24
Finished	Mar 24 02:50:16 PM PDT 24
Peak memory	200084 kb
Host	smart-859cae34-e12d-4e70-843d-d0b10ed3b224
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568274322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1568274322
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.3046461723
Short name	T808
Test name
Test status
Simulation time	153185964553 ps
CPU time	67.9 seconds
Started	Mar 24 02:47:28 PM PDT 24
Finished	Mar 24 02:48:36 PM PDT 24
Peak memory	200116 kb
Host	smart-2c75a307-5fb8-4093-8a38-f049a19847c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046461723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3046461723
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.826029416
Short name	T190
Test name
Test status
Simulation time	128873251269 ps
CPU time	44.33 seconds
Started	Mar 24 02:47:29 PM PDT 24
Finished	Mar 24 02:48:13 PM PDT 24
Peak memory	200184 kb
Host	smart-82067b40-3c48-4359-bd67-984601e72b48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826029416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.826029416
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.2168675928
Short name	T921
Test name
Test status
Simulation time	11027834528 ps
CPU time	16.25 seconds
Started	Mar 24 02:47:29 PM PDT 24
Finished	Mar 24 02:47:45 PM PDT 24
Peak memory	200388 kb
Host	smart-e253e69f-a1d7-4686-a257-61695d755cb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168675928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2168675928
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.3580405921
Short name	T606
Test name
Test status
Simulation time	14102533 ps
CPU time	0.58 seconds
Started	Mar 24 02:44:22 PM PDT 24
Finished	Mar 24 02:44:23 PM PDT 24
Peak memory	195584 kb
Host	smart-b5fb164c-8fe4-4dfc-96ae-0c88a0a6cbfb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580405921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3580405921
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.2595439558
Short name	T149
Test name
Test status
Simulation time	68326159551 ps
CPU time	32.55 seconds
Started	Mar 24 02:44:14 PM PDT 24
Finished	Mar 24 02:44:47 PM PDT 24
Peak memory	200184 kb
Host	smart-08bdbb0f-1516-4cd9-a060-d1d7bbbfd681
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595439558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2595439558
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.2796166034
Short name	T958
Test name
Test status
Simulation time	17854444046 ps
CPU time	34.47 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:44:51 PM PDT 24
Peak memory	199980 kb
Host	smart-902f8afd-1639-432b-b984-f79ac79b5001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796166034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2796166034
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.494342953
Short name	T537
Test name
Test status
Simulation time	17533838487 ps
CPU time	14.96 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:35 PM PDT 24
Peak memory	200128 kb
Host	smart-fd3e7cbc-497b-4136-b930-d9c8ccbb5f58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494342953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.494342953
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_intr.3947371198
Short name	T772
Test name
Test status
Simulation time	41561483348 ps
CPU time	74.39 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:45:32 PM PDT 24
Peak memory	200116 kb
Host	smart-b2f13197-b31e-424e-83c3-6c4a5eabc55a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947371198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3947371198
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_loopback.1338209575
Short name	T442
Test name
Test status
Simulation time	9111871804 ps
CPU time	3.8 seconds
Started	Mar 24 02:44:12 PM PDT 24
Finished	Mar 24 02:44:17 PM PDT 24
Peak memory	199840 kb
Host	smart-68cbdaff-8338-4fc5-9491-9ddb06a19e44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338209575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1338209575
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.888459888
Short name	T492
Test name
Test status
Simulation time	46927203899 ps
CPU time	25.47 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:44:42 PM PDT 24
Peak memory	200296 kb
Host	smart-f14b3203-e4d5-4bc4-a6c5-3ade6902aa49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888459888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.888459888
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.3937926285
Short name	T563
Test name
Test status
Simulation time	6703862980 ps
CPU time	77.79 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:45:36 PM PDT 24
Peak memory	200140 kb
Host	smart-ff0722bc-ac29-458a-8ab3-b8a58a75d9b5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3937926285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3937926285
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.2648054175
Short name	T1108
Test name
Test status
Simulation time	3034390986 ps
CPU time	6.32 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:44:21 PM PDT 24
Peak memory	198024 kb
Host	smart-5ee4a189-612e-4a87-9505-b0e643a1bc59
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2648054175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2648054175
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.2302022329
Short name	T704
Test name
Test status
Simulation time	33774353608 ps
CPU time	28.56 seconds
Started	Mar 24 02:44:14 PM PDT 24
Finished	Mar 24 02:44:43 PM PDT 24
Peak memory	200076 kb
Host	smart-8be736e2-f6aa-4c52-ab0f-a016027f0f7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302022329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2302022329
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.689835327
Short name	T1105
Test name
Test status
Simulation time	41118033137 ps
CPU time	14.22 seconds
Started	Mar 24 02:44:16 PM PDT 24
Finished	Mar 24 02:44:31 PM PDT 24
Peak memory	195932 kb
Host	smart-37f14827-5e9c-40cc-9fbf-d041d5dc706a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689835327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.689835327
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.2779311929
Short name	T567
Test name
Test status
Simulation time	783084795 ps
CPU time	1.56 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:21 PM PDT 24
Peak memory	198320 kb
Host	smart-4f219d3a-a3d0-4c79-83b4-707b363f69e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779311929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2779311929
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all.1158969212
Short name	T1071
Test name
Test status
Simulation time	46487740022 ps
CPU time	601.89 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:54:20 PM PDT 24
Peak memory	200136 kb
Host	smart-8335a22a-c014-4f51-a5ff-a0e9a4325174
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158969212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1158969212
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.2468960037
Short name	T327
Test name
Test status
Simulation time	1381699612 ps
CPU time	2.13 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:44:18 PM PDT 24
Peak memory	198772 kb
Host	smart-cd371c26-e9f1-4634-b08a-149e225028d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468960037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2468960037
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.457418129
Short name	T962
Test name
Test status
Simulation time	113799095412 ps
CPU time	66.23 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:45:26 PM PDT 24
Peak memory	200028 kb
Host	smart-7a752fa0-3f8b-4483-901a-6a9693760244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457418129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.457418129
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.1164515156
Short name	T439
Test name
Test status
Simulation time	45517167576 ps
CPU time	17.48 seconds
Started	Mar 24 02:47:33 PM PDT 24
Finished	Mar 24 02:47:50 PM PDT 24
Peak memory	200000 kb
Host	smart-b7da454e-9e17-42d0-8dee-4fa9780781ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164515156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1164515156
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.2308962539
Short name	T967
Test name
Test status
Simulation time	82538743225 ps
CPU time	101.86 seconds
Started	Mar 24 02:47:28 PM PDT 24
Finished	Mar 24 02:49:10 PM PDT 24
Peak memory	200148 kb
Host	smart-35e1929a-d102-457a-882c-1fd59a624770
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2308962539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2308962539
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.4282629256
Short name	T164
Test name
Test status
Simulation time	20839695061 ps
CPU time	38.92 seconds
Started	Mar 24 02:47:28 PM PDT 24
Finished	Mar 24 02:48:07 PM PDT 24
Peak memory	200104 kb
Host	smart-37866d0b-6297-4c11-a2a0-120e55c7e259
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282629256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4282629256
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.1919243529
Short name	T191
Test name
Test status
Simulation time	118649629100 ps
CPU time	91.19 seconds
Started	Mar 24 02:47:33 PM PDT 24
Finished	Mar 24 02:49:04 PM PDT 24
Peak memory	200120 kb
Host	smart-70c418bb-b5d5-45b7-801d-961c289bc7fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919243529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1919243529
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.3881764617
Short name	T728
Test name
Test status
Simulation time	16004747097 ps
CPU time	27 seconds
Started	Mar 24 02:47:33 PM PDT 24
Finished	Mar 24 02:48:00 PM PDT 24
Peak memory	200060 kb
Host	smart-2e47b91c-b4f6-4e05-9c95-c889d607167e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881764617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3881764617
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.1740656990
Short name	T1038
Test name
Test status
Simulation time	53521120912 ps
CPU time	141.87 seconds
Started	Mar 24 02:47:33 PM PDT 24
Finished	Mar 24 02:49:55 PM PDT 24
Peak memory	200128 kb
Host	smart-5717d177-c254-4f6c-82c4-c5fb6f234394
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740656990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1740656990
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.2756925917
Short name	T870
Test name
Test status
Simulation time	122704203939 ps
CPU time	101.79 seconds
Started	Mar 24 02:47:33 PM PDT 24
Finished	Mar 24 02:49:15 PM PDT 24
Peak memory	200188 kb
Host	smart-67aa7014-62ec-44b3-9fe4-7c563d8043c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756925917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2756925917
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.3899463468
Short name	T825
Test name
Test status
Simulation time	264158308622 ps
CPU time	73.84 seconds
Started	Mar 24 02:47:35 PM PDT 24
Finished	Mar 24 02:48:49 PM PDT 24
Peak memory	200252 kb
Host	smart-8815826a-3285-4155-a4e8-a00b8c09cd3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899463468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3899463468
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.599845459
Short name	T447
Test name
Test status
Simulation time	31166296949 ps
CPU time	46.29 seconds
Started	Mar 24 02:47:32 PM PDT 24
Finished	Mar 24 02:48:19 PM PDT 24
Peak memory	200140 kb
Host	smart-00914338-17fd-4483-8b20-9e9d24678637
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599845459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.599845459
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.3957957401
Short name	T536
Test name
Test status
Simulation time	36876715 ps
CPU time	0.56 seconds
Started	Mar 24 02:44:20 PM PDT 24
Finished	Mar 24 02:44:21 PM PDT 24
Peak memory	194540 kb
Host	smart-ede9c0cc-70c9-4510-84e7-3b07da187153
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957957401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3957957401
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.68194565
Short name	T873
Test name
Test status
Simulation time	54172427603 ps
CPU time	36.74 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:44:54 PM PDT 24
Peak memory	200108 kb
Host	smart-107a6122-9ca0-42bd-af90-472cbf503171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68194565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.68194565
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.2258500357
Short name	T1048
Test name
Test status
Simulation time	146294550997 ps
CPU time	85.15 seconds
Started	Mar 24 02:44:15 PM PDT 24
Finished	Mar 24 02:45:41 PM PDT 24
Peak memory	199992 kb
Host	smart-ed9e6452-00c2-4fe3-b724-3c0287db9455
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258500357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2258500357
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.2194715918
Short name	T912
Test name
Test status
Simulation time	286775498038 ps
CPU time	47.17 seconds
Started	Mar 24 02:44:20 PM PDT 24
Finished	Mar 24 02:45:08 PM PDT 24
Peak memory	200036 kb
Host	smart-c4dbc987-1ce1-4d48-a6f5-57b2e3121fa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194715918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2194715918
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_intr.2268293797
Short name	T877
Test name
Test status
Simulation time	68123716471 ps
CPU time	123.67 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:46:22 PM PDT 24
Peak memory	200132 kb
Host	smart-0189bcc5-2a13-4ce7-924f-44a3f76c9dcc
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268293797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2268293797
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_loopback.3556443907
Short name	T383
Test name
Test status
Simulation time	188286060 ps
CPU time	1.09 seconds
Started	Mar 24 02:44:21 PM PDT 24
Finished	Mar 24 02:44:23 PM PDT 24
Peak memory	197328 kb
Host	smart-d0711635-6dfa-4379-ab5c-f413dff3cee9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556443907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3556443907
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.852525773
Short name	T448
Test name
Test status
Simulation time	101650795301 ps
CPU time	83.41 seconds
Started	Mar 24 02:44:16 PM PDT 24
Finished	Mar 24 02:45:40 PM PDT 24
Peak memory	200304 kb
Host	smart-67e6d664-a296-42bf-8701-f47f799516f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852525773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.852525773
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.266999336
Short name	T730
Test name
Test status
Simulation time	4846059432 ps
CPU time	227.16 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:48:07 PM PDT 24
Peak memory	200128 kb
Host	smart-8f2b3444-4ff1-4875-8633-3b0b8b81cd44
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=266999336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.266999336
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.2461517611
Short name	T441
Test name
Test status
Simulation time	1805117101 ps
CPU time	2.85 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:44:22 PM PDT 24
Peak memory	199320 kb
Host	smart-04447cf1-212a-49d1-8d72-45d00b9dba64
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2461517611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2461517611
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.4169910553
Short name	T973
Test name
Test status
Simulation time	83016261302 ps
CPU time	125.62 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:46:24 PM PDT 24
Peak memory	200104 kb
Host	smart-c36e1fbb-4565-4e05-bd5b-bf6599191de1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169910553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4169910553
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.3119456414
Short name	T733
Test name
Test status
Simulation time	3369790177 ps
CPU time	1.71 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	196252 kb
Host	smart-2190bdee-875e-4c96-bf60-259817bc4886
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119456414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3119456414
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/25.uart_smoke.2243338206
Short name	T59
Test name
Test status
Simulation time	307278688 ps
CPU time	1.13 seconds
Started	Mar 24 02:44:17 PM PDT 24
Finished	Mar 24 02:44:18 PM PDT 24
Peak memory	198664 kb
Host	smart-e3d2330f-2181-49b6-a3c8-3e0f4d34128a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243338206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2243338206
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.3395000210
Short name	T994
Test name
Test status
Simulation time	1390031005 ps
CPU time	2.37 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:22 PM PDT 24
Peak memory	199636 kb
Host	smart-3695f010-7609-43fa-8bc4-f66176b32529
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395000210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3395000210
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.995369194
Short name	T3
Test name
Test status
Simulation time	15920690195 ps
CPU time	27.75 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:47 PM PDT 24
Peak memory	200200 kb
Host	smart-9e668a27-1f52-4e40-ad21-2c1460f10a77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995369194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.995369194
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.2633885570
Short name	T282
Test name
Test status
Simulation time	185487001959 ps
CPU time	383.04 seconds
Started	Mar 24 02:47:33 PM PDT 24
Finished	Mar 24 02:53:56 PM PDT 24
Peak memory	200144 kb
Host	smart-286ecc2f-9c85-4d55-ada8-6b96cc97d37f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633885570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2633885570
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.1987108565
Short name	T1072
Test name
Test status
Simulation time	73470446126 ps
CPU time	33.59 seconds
Started	Mar 24 02:47:34 PM PDT 24
Finished	Mar 24 02:48:07 PM PDT 24
Peak memory	200096 kb
Host	smart-0758289a-1a36-483f-a9a3-3759891c3471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987108565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1987108565
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.3550084956
Short name	T262
Test name
Test status
Simulation time	12286120309 ps
CPU time	14.05 seconds
Started	Mar 24 02:47:41 PM PDT 24
Finished	Mar 24 02:47:55 PM PDT 24
Peak memory	200128 kb
Host	smart-72ada621-c48d-4e2b-b7b8-b50ef93de962
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550084956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3550084956
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.758556457
Short name	T208
Test name
Test status
Simulation time	153867297343 ps
CPU time	73.73 seconds
Started	Mar 24 02:47:40 PM PDT 24
Finished	Mar 24 02:48:54 PM PDT 24
Peak memory	200132 kb
Host	smart-256ebb51-a4e3-4d85-a953-f16e65c1b16f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758556457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.758556457
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.187231480
Short name	T199
Test name
Test status
Simulation time	140593411257 ps
CPU time	56.81 seconds
Started	Mar 24 02:47:40 PM PDT 24
Finished	Mar 24 02:48:37 PM PDT 24
Peak memory	200128 kb
Host	smart-a26b734f-a81d-4c3d-a858-bf0cb0863f86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187231480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.187231480
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.714391795
Short name	T1119
Test name
Test status
Simulation time	101966938903 ps
CPU time	151.8 seconds
Started	Mar 24 02:47:39 PM PDT 24
Finished	Mar 24 02:50:11 PM PDT 24
Peak memory	200048 kb
Host	smart-1990cc4c-7bca-40c2-92af-0644ca8e6ea5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714391795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.714391795
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.3690892326
Short name	T747
Test name
Test status
Simulation time	71226170217 ps
CPU time	26.18 seconds
Started	Mar 24 02:47:38 PM PDT 24
Finished	Mar 24 02:48:05 PM PDT 24
Peak memory	200128 kb
Host	smart-8035de42-36d2-40a9-a277-59580ac7fcb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3690892326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3690892326
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.1224799008
Short name	T1106
Test name
Test status
Simulation time	10848883614 ps
CPU time	18.12 seconds
Started	Mar 24 02:47:40 PM PDT 24
Finished	Mar 24 02:47:59 PM PDT 24
Peak memory	200108 kb
Host	smart-0d62e06b-7b39-45bd-a165-6f4d705b7471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224799008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1224799008
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.2383833942
Short name	T1113
Test name
Test status
Simulation time	59577491 ps
CPU time	0.55 seconds
Started	Mar 24 02:44:25 PM PDT 24
Finished	Mar 24 02:44:26 PM PDT 24
Peak memory	195636 kb
Host	smart-73f75218-4649-4fa9-9484-a641625986d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383833942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2383833942
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.1565460471
Short name	T498
Test name
Test status
Simulation time	22175217276 ps
CPU time	16.08 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:44:35 PM PDT 24
Peak memory	200052 kb
Host	smart-550fb851-eb4c-4902-aad0-129247c7348a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565460471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1565460471
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.198690670
Short name	T801
Test name
Test status
Simulation time	274288325148 ps
CPU time	26 seconds
Started	Mar 24 02:44:19 PM PDT 24
Finished	Mar 24 02:44:46 PM PDT 24
Peak memory	198672 kb
Host	smart-9d8c3d6c-0916-4cbb-ab30-ca274be27aa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198690670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.198690670
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_intr.2318807958
Short name	T1064
Test name
Test status
Simulation time	3754047883 ps
CPU time	3.33 seconds
Started	Mar 24 02:44:20 PM PDT 24
Finished	Mar 24 02:44:24 PM PDT 24
Peak memory	196000 kb
Host	smart-a3e01ede-e84e-408a-bb19-74d60371721f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318807958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2318807958
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.1550412070
Short name	T583
Test name
Test status
Simulation time	108421479414 ps
CPU time	642.72 seconds
Started	Mar 24 02:44:24 PM PDT 24
Finished	Mar 24 02:55:07 PM PDT 24
Peak memory	200120 kb
Host	smart-bd2184e3-800d-45db-b66a-7b0e45ff0456
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1550412070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1550412070
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.3430824893
Short name	T378
Test name
Test status
Simulation time	4493162670 ps
CPU time	2.24 seconds
Started	Mar 24 02:44:23 PM PDT 24
Finished	Mar 24 02:44:26 PM PDT 24
Peak memory	197672 kb
Host	smart-ff84621f-0c7a-437b-843c-5b9dc93b0067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430824893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3430824893
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.4155229478
Short name	T368
Test name
Test status
Simulation time	6351402652 ps
CPU time	10.41 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:44:28 PM PDT 24
Peak memory	196680 kb
Host	smart-8a90154e-d86c-4e78-8de9-ddb2eae47a4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155229478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4155229478
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/26.uart_perf.585455975
Short name	T279
Test name
Test status
Simulation time	17263760068 ps
CPU time	105.48 seconds
Started	Mar 24 02:44:26 PM PDT 24
Finished	Mar 24 02:46:12 PM PDT 24
Peak memory	200208 kb
Host	smart-46902aa1-ecae-43cc-9aed-e5371c541fd7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=585455975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.585455975
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.907889883
Short name	T677
Test name
Test status
Simulation time	6730521685 ps
CPU time	29.56 seconds
Started	Mar 24 02:44:23 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	198824 kb
Host	smart-1506394d-f019-47d0-87fb-4ccb25bf1510
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=907889883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.907889883
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.20327981
Short name	T1008
Test name
Test status
Simulation time	126134113581 ps
CPU time	107.6 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:46:06 PM PDT 24
Peak memory	199964 kb
Host	smart-d4d5fe80-91ea-4f55-9dd2-01439123d9fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20327981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.20327981
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.3670161122
Short name	T484
Test name
Test status
Simulation time	653235631 ps
CPU time	0.83 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:44:19 PM PDT 24
Peak memory	195536 kb
Host	smart-73754efa-58fe-483f-846f-cdecc839a30a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670161122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3670161122
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.1160295282
Short name	T587
Test name
Test status
Simulation time	652270847 ps
CPU time	2.16 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:44:21 PM PDT 24
Peak memory	198784 kb
Host	smart-ac0884fa-70b6-4908-85f2-4f88d5c4c2ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160295282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1160295282
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all.1921112691
Short name	T1015
Test name
Test status
Simulation time	93500392727 ps
CPU time	1021.11 seconds
Started	Mar 24 02:44:21 PM PDT 24
Finished	Mar 24 03:01:23 PM PDT 24
Peak memory	200192 kb
Host	smart-947b4ab4-9b1f-4469-be7e-034d2885258b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921112691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1921112691
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.865266604
Short name	T580
Test name
Test status
Simulation time	1348807653 ps
CPU time	1.57 seconds
Started	Mar 24 02:44:24 PM PDT 24
Finished	Mar 24 02:44:26 PM PDT 24
Peak memory	198848 kb
Host	smart-7b5fd7be-df18-48d4-a544-537be09a51e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865266604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.865266604
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.1371589806
Short name	T552
Test name
Test status
Simulation time	50960550452 ps
CPU time	48.41 seconds
Started	Mar 24 02:44:18 PM PDT 24
Finished	Mar 24 02:45:07 PM PDT 24
Peak memory	200352 kb
Host	smart-de78a93d-b69a-4b0e-b08b-c5b95c902d4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371589806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1371589806
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.1749112316
Short name	T982
Test name
Test status
Simulation time	31810960649 ps
CPU time	55.88 seconds
Started	Mar 24 02:47:47 PM PDT 24
Finished	Mar 24 02:48:43 PM PDT 24
Peak memory	200144 kb
Host	smart-2655da7d-8f92-4d98-ae34-80d41ed39725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749112316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1749112316
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.329034771
Short name	T269
Test name
Test status
Simulation time	86318706010 ps
CPU time	257.84 seconds
Started	Mar 24 02:47:45 PM PDT 24
Finished	Mar 24 02:52:03 PM PDT 24
Peak memory	200364 kb
Host	smart-ce0c4657-53d1-4c63-92bb-5764c7e65d9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329034771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.329034771
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.977060569
Short name	T894
Test name
Test status
Simulation time	11872153083 ps
CPU time	18.97 seconds
Started	Mar 24 02:47:44 PM PDT 24
Finished	Mar 24 02:48:03 PM PDT 24
Peak memory	200064 kb
Host	smart-690e02a3-591a-4e2d-b3e0-21f09a3c3868
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977060569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.977060569
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/263.uart_fifo_reset.1529395074
Short name	T805
Test name
Test status
Simulation time	104965886466 ps
CPU time	42.11 seconds
Started	Mar 24 02:47:45 PM PDT 24
Finished	Mar 24 02:48:27 PM PDT 24
Peak memory	200164 kb
Host	smart-6f0ca33e-3e74-4b68-8a0a-76811227be96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529395074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1529395074
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.3933730002
Short name	T608
Test name
Test status
Simulation time	31071579755 ps
CPU time	17.61 seconds
Started	Mar 24 02:47:44 PM PDT 24
Finished	Mar 24 02:48:02 PM PDT 24
Peak memory	200072 kb
Host	smart-3828c43c-4e2c-4076-9f08-4ef8544456f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933730002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3933730002
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.612946842
Short name	T679
Test name
Test status
Simulation time	11672115836 ps
CPU time	17.35 seconds
Started	Mar 24 02:47:46 PM PDT 24
Finished	Mar 24 02:48:03 PM PDT 24
Peak memory	200136 kb
Host	smart-72bec4df-dc3e-4c56-829f-3642c2073526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612946842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.612946842
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.2472903877
Short name	T406
Test name
Test status
Simulation time	9826671152 ps
CPU time	5.16 seconds
Started	Mar 24 02:47:45 PM PDT 24
Finished	Mar 24 02:47:50 PM PDT 24
Peak memory	200040 kb
Host	smart-a45087d4-cd2d-407f-afeb-f3a4ecb66693
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2472903877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2472903877
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.2594230212
Short name	T257
Test name
Test status
Simulation time	41483563445 ps
CPU time	26.81 seconds
Started	Mar 24 02:47:45 PM PDT 24
Finished	Mar 24 02:48:12 PM PDT 24
Peak memory	200096 kb
Host	smart-48a7f987-d4ea-4e72-b8cf-a5bfc29a276d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594230212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2594230212
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.566411020
Short name	T940
Test name
Test status
Simulation time	176865572407 ps
CPU time	393.45 seconds
Started	Mar 24 02:47:50 PM PDT 24
Finished	Mar 24 02:54:24 PM PDT 24
Peak memory	199908 kb
Host	smart-07348b31-4719-433b-ab07-b44608cc91a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566411020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.566411020
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.2715905123
Short name	T391
Test name
Test status
Simulation time	36635876 ps
CPU time	0.54 seconds
Started	Mar 24 02:44:32 PM PDT 24
Finished	Mar 24 02:44:33 PM PDT 24
Peak memory	195080 kb
Host	smart-8830b89f-284b-4092-865a-abb2aa3b1be7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715905123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2715905123
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.3342353893
Short name	T1044
Test name
Test status
Simulation time	34427438389 ps
CPU time	25.94 seconds
Started	Mar 24 02:44:23 PM PDT 24
Finished	Mar 24 02:44:50 PM PDT 24
Peak memory	199372 kb
Host	smart-c2b86446-8ff4-495b-a132-029d01e0387e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342353893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3342353893
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.2803981002
Short name	T480
Test name
Test status
Simulation time	32846893724 ps
CPU time	15.89 seconds
Started	Mar 24 02:44:25 PM PDT 24
Finished	Mar 24 02:44:41 PM PDT 24
Peak memory	200064 kb
Host	smart-223ee9a3-4cac-4eae-aaae-52bc9e88168b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803981002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2803981002
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.3981897667
Short name	T930
Test name
Test status
Simulation time	7332971768 ps
CPU time	12.11 seconds
Started	Mar 24 02:44:22 PM PDT 24
Finished	Mar 24 02:44:34 PM PDT 24
Peak memory	200100 kb
Host	smart-d1fe9983-b5a2-4547-84a6-51edff460daf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981897667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3981897667
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_intr.4243395149
Short name	T23
Test name
Test status
Simulation time	38208240171 ps
CPU time	61.67 seconds
Started	Mar 24 02:44:23 PM PDT 24
Finished	Mar 24 02:45:25 PM PDT 24
Peak memory	200164 kb
Host	smart-08e36dc0-b0cb-49ca-8424-66dafc454cb7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243395149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4243395149
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.2493881809
Short name	T813
Test name
Test status
Simulation time	84459689680 ps
CPU time	202.46 seconds
Started	Mar 24 02:44:27 PM PDT 24
Finished	Mar 24 02:47:49 PM PDT 24
Peak memory	200148 kb
Host	smart-26ca3ef3-8677-4707-bb3a-2fd44a5ab9cd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2493881809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2493881809
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.1299599834
Short name	T1111
Test name
Test status
Simulation time	13178978973 ps
CPU time	19.88 seconds
Started	Mar 24 02:44:28 PM PDT 24
Finished	Mar 24 02:44:48 PM PDT 24
Peak memory	200100 kb
Host	smart-c8ea57fc-990a-46bc-b33d-c27613819431
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299599834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1299599834
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.402084578
Short name	T972
Test name
Test status
Simulation time	42348190268 ps
CPU time	12.95 seconds
Started	Mar 24 02:44:24 PM PDT 24
Finished	Mar 24 02:44:38 PM PDT 24
Peak memory	198372 kb
Host	smart-43c9d2ab-a94a-4735-bc04-af24e2066823
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402084578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.402084578
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.1584455913
Short name	T1059
Test name
Test status
Simulation time	5079136632 ps
CPU time	156.03 seconds
Started	Mar 24 02:44:28 PM PDT 24
Finished	Mar 24 02:47:05 PM PDT 24
Peak memory	200112 kb
Host	smart-e8d89c4b-d515-4f09-90af-3ca75f770fa9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1584455913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1584455913
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.3854159506
Short name	T28
Test name
Test status
Simulation time	1166365213 ps
CPU time	2.57 seconds
Started	Mar 24 02:44:24 PM PDT 24
Finished	Mar 24 02:44:27 PM PDT 24
Peak memory	198164 kb
Host	smart-932cb68b-566c-4827-a23c-6b4edaf192b5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3854159506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3854159506
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.1229474833
Short name	T1088
Test name
Test status
Simulation time	3347761567 ps
CPU time	1.39 seconds
Started	Mar 24 02:44:25 PM PDT 24
Finished	Mar 24 02:44:26 PM PDT 24
Peak memory	196232 kb
Host	smart-73e2adb9-16b3-4262-8114-113d1d5194c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229474833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1229474833
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.1934259024
Short name	T696
Test name
Test status
Simulation time	5977154840 ps
CPU time	10.41 seconds
Started	Mar 24 02:44:25 PM PDT 24
Finished	Mar 24 02:44:36 PM PDT 24
Peak memory	199828 kb
Host	smart-baa331f8-1491-462b-9d85-21c933d22a9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934259024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1934259024
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all.1473854689
Short name	T137
Test name
Test status
Simulation time	145951119539 ps
CPU time	145.02 seconds
Started	Mar 24 02:44:29 PM PDT 24
Finished	Mar 24 02:46:54 PM PDT 24
Peak memory	215840 kb
Host	smart-00e025cf-d7f4-494f-a416-000081e9a280
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473854689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1473854689
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/27.uart_stress_all_with_rand_reset.2840189644
Short name	T949
Test name
Test status
Simulation time	21857614929 ps
CPU time	200.82 seconds
Started	Mar 24 02:44:29 PM PDT 24
Finished	Mar 24 02:47:50 PM PDT 24
Peak memory	215844 kb
Host	smart-ca66a774-8185-4a75-8a4d-20c1cfd48dee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840189644 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2840189644
Directory	/workspace/27.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.4112953084
Short name	T893
Test name
Test status
Simulation time	2383552945 ps
CPU time	2.34 seconds
Started	Mar 24 02:44:28 PM PDT 24
Finished	Mar 24 02:44:31 PM PDT 24
Peak memory	199116 kb
Host	smart-6ce37725-72f2-434a-ba52-29b37337fc13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112953084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4112953084
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.225953173
Short name	T437
Test name
Test status
Simulation time	36805023628 ps
CPU time	17.66 seconds
Started	Mar 24 02:44:25 PM PDT 24
Finished	Mar 24 02:44:43 PM PDT 24
Peak memory	200004 kb
Host	smart-07f7db38-d693-43cf-aaaa-c47b134888a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225953173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.225953173
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.884508642
Short name	T483
Test name
Test status
Simulation time	66024329407 ps
CPU time	26.79 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:48:20 PM PDT 24
Peak memory	199864 kb
Host	smart-98513cdd-5cce-462f-b613-e8c64c7d58bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884508642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.884508642
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.81877443
Short name	T1041
Test name
Test status
Simulation time	81030978176 ps
CPU time	115.7 seconds
Started	Mar 24 02:47:54 PM PDT 24
Finished	Mar 24 02:49:50 PM PDT 24
Peak memory	200112 kb
Host	smart-5d070365-a2ac-4e9f-b4dc-5540e2f8e0e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81877443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.81877443
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.2920078426
Short name	T761
Test name
Test status
Simulation time	66477356287 ps
CPU time	103.91 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:49:36 PM PDT 24
Peak memory	200152 kb
Host	smart-f8295de0-ea09-4f97-8df0-bb27e9b0b6ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920078426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2920078426
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.1235403362
Short name	T78
Test name
Test status
Simulation time	187565319128 ps
CPU time	26.23 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:48:18 PM PDT 24
Peak memory	200160 kb
Host	smart-fdc8edaa-4f4c-4c72-87c2-6f60f0b37297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235403362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1235403362
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.2707066571
Short name	T1090
Test name
Test status
Simulation time	12693423330 ps
CPU time	22.22 seconds
Started	Mar 24 02:47:56 PM PDT 24
Finished	Mar 24 02:48:19 PM PDT 24
Peak memory	200152 kb
Host	smart-8468d87f-49d3-44a7-b92d-90b9caf550da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707066571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2707066571
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.2032651243
Short name	T174
Test name
Test status
Simulation time	118096123473 ps
CPU time	55.25 seconds
Started	Mar 24 02:47:56 PM PDT 24
Finished	Mar 24 02:48:52 PM PDT 24
Peak memory	200092 kb
Host	smart-1dda0848-3b60-4aaf-a19d-a6d6865f2354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032651243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2032651243
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.2618201656
Short name	T216
Test name
Test status
Simulation time	8288507651 ps
CPU time	16.38 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:48:09 PM PDT 24
Peak memory	200188 kb
Host	smart-d7cdbd85-d792-49b1-8f30-851d9235ef44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618201656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2618201656
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.3231654104
Short name	T1020
Test name
Test status
Simulation time	10723419876 ps
CPU time	33.39 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:48:25 PM PDT 24
Peak memory	200116 kb
Host	smart-c8edbb5c-6151-4b48-a057-70336bd2ea4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231654104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3231654104
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.252697141
Short name	T658
Test name
Test status
Simulation time	20678679 ps
CPU time	0.56 seconds
Started	Mar 24 02:44:33 PM PDT 24
Finished	Mar 24 02:44:34 PM PDT 24
Peak memory	195588 kb
Host	smart-2ad3acb9-8b5d-4b98-a331-b5fe4749ab2f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252697141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.252697141
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.1300646859
Short name	T1010
Test name
Test status
Simulation time	40033031374 ps
CPU time	30.23 seconds
Started	Mar 24 02:44:28 PM PDT 24
Finished	Mar 24 02:44:59 PM PDT 24
Peak memory	200352 kb
Host	smart-1eb245fd-a30c-41b1-989a-a44c46b2d308
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300646859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1300646859
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.3763984988
Short name	T957
Test name
Test status
Simulation time	28463700857 ps
CPU time	55.5 seconds
Started	Mar 24 02:44:26 PM PDT 24
Finished	Mar 24 02:45:22 PM PDT 24
Peak memory	200028 kb
Host	smart-2234daed-2204-415a-bd72-c7e153119d45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763984988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3763984988
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.3422706375
Short name	T885
Test name
Test status
Simulation time	13032041703 ps
CPU time	17.04 seconds
Started	Mar 24 02:44:27 PM PDT 24
Finished	Mar 24 02:44:44 PM PDT 24
Peak memory	200020 kb
Host	smart-e225eae1-0368-4b9a-b338-80b3744a941b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422706375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3422706375
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.3986045181
Short name	T703
Test name
Test status
Simulation time	35772961711 ps
CPU time	49.54 seconds
Started	Mar 24 02:44:34 PM PDT 24
Finished	Mar 24 02:45:25 PM PDT 24
Peak memory	200124 kb
Host	smart-da5ea69c-7900-4f4c-b980-c803e94a865a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986045181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3986045181
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.2889151354
Short name	T278
Test name
Test status
Simulation time	156651942716 ps
CPU time	229.04 seconds
Started	Mar 24 02:44:35 PM PDT 24
Finished	Mar 24 02:48:24 PM PDT 24
Peak memory	200168 kb
Host	smart-ae1f9d83-8ff5-46ed-84b7-c277aeaa5947
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2889151354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2889151354
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.2990890652
Short name	T951
Test name
Test status
Simulation time	5667271470 ps
CPU time	2.05 seconds
Started	Mar 24 02:44:35 PM PDT 24
Finished	Mar 24 02:44:37 PM PDT 24
Peak memory	199348 kb
Host	smart-c94ad39f-b79c-41d1-9a6e-e105bad7ecd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990890652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2990890652
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.1342342100
Short name	T445
Test name
Test status
Simulation time	143274082410 ps
CPU time	56.83 seconds
Started	Mar 24 02:44:34 PM PDT 24
Finished	Mar 24 02:45:31 PM PDT 24
Peak memory	200264 kb
Host	smart-5389b84f-7903-45a2-a5f8-6e2e7c1df12b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342342100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1342342100
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.1499612808
Short name	T750
Test name
Test status
Simulation time	3359992500 ps
CPU time	196.6 seconds
Started	Mar 24 02:44:32 PM PDT 24
Finished	Mar 24 02:47:49 PM PDT 24
Peak memory	200016 kb
Host	smart-92eea285-9905-46ea-9025-a746d6531b15
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1499612808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1499612808
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.322254787
Short name	T820
Test name
Test status
Simulation time	3347373831 ps
CPU time	11.09 seconds
Started	Mar 24 02:44:27 PM PDT 24
Finished	Mar 24 02:44:39 PM PDT 24
Peak memory	198392 kb
Host	smart-e85dba4b-82b4-4beb-9413-617792b8bdbf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=322254787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.322254787
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.608897848
Short name	T179
Test name
Test status
Simulation time	52066475727 ps
CPU time	47.3 seconds
Started	Mar 24 02:44:33 PM PDT 24
Finished	Mar 24 02:45:20 PM PDT 24
Peak memory	200088 kb
Host	smart-997be137-81ab-4012-93cd-59493ec8f934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608897848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.608897848
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.4031097671
Short name	T308
Test name
Test status
Simulation time	32692876474 ps
CPU time	33.91 seconds
Started	Mar 24 02:44:34 PM PDT 24
Finished	Mar 24 02:45:09 PM PDT 24
Peak memory	195952 kb
Host	smart-fe456e57-bc65-4b32-8232-18572a42aec3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031097671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4031097671
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.2858348202
Short name	T662
Test name
Test status
Simulation time	278120177 ps
CPU time	1.11 seconds
Started	Mar 24 02:44:28 PM PDT 24
Finished	Mar 24 02:44:30 PM PDT 24
Peak memory	198552 kb
Host	smart-917b4a22-3d1d-457d-a704-e6cd63fd1c90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858348202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2858348202
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_stress_all_with_rand_reset.200222373
Short name	T116
Test name
Test status
Simulation time	39669279760 ps
CPU time	377.3 seconds
Started	Mar 24 02:44:34 PM PDT 24
Finished	Mar 24 02:50:53 PM PDT 24
Peak memory	216856 kb
Host	smart-4f7a7ac4-c9df-427e-882e-8a50d0473a32
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200222373 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.200222373
Directory	/workspace/28.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.1988406378
Short name	T323
Test name
Test status
Simulation time	620664007 ps
CPU time	2.2 seconds
Started	Mar 24 02:44:31 PM PDT 24
Finished	Mar 24 02:44:34 PM PDT 24
Peak memory	198748 kb
Host	smart-50bc4c49-b857-430b-a968-b68f49bf9629
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988406378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1988406378
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.4194781960
Short name	T405
Test name
Test status
Simulation time	20483424021 ps
CPU time	33.26 seconds
Started	Mar 24 02:44:28 PM PDT 24
Finished	Mar 24 02:45:01 PM PDT 24
Peak memory	200068 kb
Host	smart-8e3a022e-6d51-4217-a1a2-6ab6a7520490
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194781960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4194781960
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.4271914607
Short name	T317
Test name
Test status
Simulation time	18307675165 ps
CPU time	17.24 seconds
Started	Mar 24 02:47:56 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200120 kb
Host	smart-fa86d8f6-589e-433b-a0b3-040cdd64ca35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271914607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4271914607
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.1797476885
Short name	T1006
Test name
Test status
Simulation time	28963628637 ps
CPU time	49.74 seconds
Started	Mar 24 02:47:50 PM PDT 24
Finished	Mar 24 02:48:40 PM PDT 24
Peak memory	200112 kb
Host	smart-31b30b6f-7975-4d32-8027-656592f4f6e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797476885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1797476885
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.3049614618
Short name	T320
Test name
Test status
Simulation time	24546997390 ps
CPU time	17.5 seconds
Started	Mar 24 02:47:51 PM PDT 24
Finished	Mar 24 02:48:09 PM PDT 24
Peak memory	199928 kb
Host	smart-f4e056b5-f2f9-47d3-bb5c-633da53fab9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049614618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3049614618
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.1681672715
Short name	T1097
Test name
Test status
Simulation time	79284130764 ps
CPU time	66.12 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:48:58 PM PDT 24
Peak memory	200048 kb
Host	smart-04dc2685-28a2-4843-b51e-f1b3a43e9b02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681672715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1681672715
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.2981649450
Short name	T708
Test name
Test status
Simulation time	133949688677 ps
CPU time	45.88 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:48:38 PM PDT 24
Peak memory	199956 kb
Host	smart-16bd7510-9834-4d09-bf0f-f2951e49444e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981649450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2981649450
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.3762259414
Short name	T835
Test name
Test status
Simulation time	141031428244 ps
CPU time	85.8 seconds
Started	Mar 24 02:47:52 PM PDT 24
Finished	Mar 24 02:49:18 PM PDT 24
Peak memory	199972 kb
Host	smart-c5769386-c9cd-47a2-a2a0-3f159a35d803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3762259414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3762259414
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.2705419710
Short name	T528
Test name
Test status
Simulation time	38099922956 ps
CPU time	18.11 seconds
Started	Mar 24 02:47:58 PM PDT 24
Finished	Mar 24 02:48:17 PM PDT 24
Peak memory	200164 kb
Host	smart-7dae988e-7066-4f17-9450-9b6cc8502670
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705419710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2705419710
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.1074970388
Short name	T250
Test name
Test status
Simulation time	17830140306 ps
CPU time	24.52 seconds
Started	Mar 24 02:47:59 PM PDT 24
Finished	Mar 24 02:48:24 PM PDT 24
Peak memory	200120 kb
Host	smart-0ea20a1d-18e1-4484-a715-f849308f83fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074970388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1074970388
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.3236727753
Short name	T333
Test name
Test status
Simulation time	34181397726 ps
CPU time	25.16 seconds
Started	Mar 24 02:48:00 PM PDT 24
Finished	Mar 24 02:48:25 PM PDT 24
Peak memory	200188 kb
Host	smart-02ff71f8-ad06-404e-ba68-6276a3f8683d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236727753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3236727753
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.1093651371
Short name	T980
Test name
Test status
Simulation time	22490829 ps
CPU time	0.57 seconds
Started	Mar 24 02:44:40 PM PDT 24
Finished	Mar 24 02:44:40 PM PDT 24
Peak memory	195628 kb
Host	smart-990d3ada-c555-4eed-ae60-6de4b9360f3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093651371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1093651371
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.2848487395
Short name	T58
Test name
Test status
Simulation time	29984693510 ps
CPU time	105.81 seconds
Started	Mar 24 02:44:32 PM PDT 24
Finished	Mar 24 02:46:19 PM PDT 24
Peak memory	200148 kb
Host	smart-fbe9b919-4861-4969-919e-9e74082276c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848487395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2848487395
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.3270902269
Short name	T695
Test name
Test status
Simulation time	16967199503 ps
CPU time	25.96 seconds
Started	Mar 24 02:44:38 PM PDT 24
Finished	Mar 24 02:45:04 PM PDT 24
Peak memory	200084 kb
Host	smart-b254069d-42bf-4e3f-af9e-946a473cd973
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270902269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3270902269
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.648536664
Short name	T685
Test name
Test status
Simulation time	25296940902 ps
CPU time	19 seconds
Started	Mar 24 02:44:38 PM PDT 24
Finished	Mar 24 02:44:57 PM PDT 24
Peak memory	199988 kb
Host	smart-aa57a5c9-2ea4-410b-89eb-157a4e2d7391
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648536664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.648536664
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_intr.3568404512
Short name	T953
Test name
Test status
Simulation time	46378872818 ps
CPU time	9.67 seconds
Started	Mar 24 02:44:40 PM PDT 24
Finished	Mar 24 02:44:50 PM PDT 24
Peak memory	200132 kb
Host	smart-89be93e3-757d-42ac-a730-4c36d9e363b8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568404512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3568404512
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.3369685149
Short name	T353
Test name
Test status
Simulation time	165019590195 ps
CPU time	531.93 seconds
Started	Mar 24 02:44:37 PM PDT 24
Finished	Mar 24 02:53:29 PM PDT 24
Peak memory	200164 kb
Host	smart-cd1322e4-feb8-4474-884e-ae274473f2c7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3369685149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3369685149
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/29.uart_loopback.4056939911
Short name	T458
Test name
Test status
Simulation time	5665544649 ps
CPU time	3.5 seconds
Started	Mar 24 02:44:37 PM PDT 24
Finished	Mar 24 02:44:41 PM PDT 24
Peak memory	199552 kb
Host	smart-451632f0-aec6-4105-a807-912bf9bcead8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056939911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4056939911
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.3863382378
Short name	T923
Test name
Test status
Simulation time	209952213000 ps
CPU time	125.13 seconds
Started	Mar 24 02:44:39 PM PDT 24
Finished	Mar 24 02:46:44 PM PDT 24
Peak memory	200192 kb
Host	smart-4c46909b-a8db-4cfc-85ad-6fe63df34b86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863382378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3863382378
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.1953265251
Short name	T667
Test name
Test status
Simulation time	13619069181 ps
CPU time	695.15 seconds
Started	Mar 24 02:44:37 PM PDT 24
Finished	Mar 24 02:56:13 PM PDT 24
Peak memory	200116 kb
Host	smart-c3598c52-03c0-4256-bfbf-6ead255d0b46
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1953265251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1953265251
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.2183393464
Short name	T693
Test name
Test status
Simulation time	6220579048 ps
CPU time	34.95 seconds
Started	Mar 24 02:44:37 PM PDT 24
Finished	Mar 24 02:45:12 PM PDT 24
Peak memory	199300 kb
Host	smart-4a4b4b5e-d4d4-46c6-b1ee-77c66747c873
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2183393464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2183393464
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.650044585
Short name	T510
Test name
Test status
Simulation time	64912880830 ps
CPU time	90.84 seconds
Started	Mar 24 02:44:40 PM PDT 24
Finished	Mar 24 02:46:12 PM PDT 24
Peak memory	199752 kb
Host	smart-7ec814ea-bceb-43a6-ac74-5065be104b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650044585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.650044585
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.231736136
Short name	T1040
Test name
Test status
Simulation time	39114412764 ps
CPU time	16.85 seconds
Started	Mar 24 02:44:39 PM PDT 24
Finished	Mar 24 02:44:57 PM PDT 24
Peak memory	196512 kb
Host	smart-29dd3f24-5c6e-4dfc-93cd-6af7b15021fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231736136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.231736136
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.3755149972
Short name	T821
Test name
Test status
Simulation time	5916882581 ps
CPU time	18 seconds
Started	Mar 24 02:44:35 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	199208 kb
Host	smart-ae198900-50c1-4632-ab64-c6a6207090e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755149972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3755149972
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.2066970069
Short name	T168
Test name
Test status
Simulation time	202688019044 ps
CPU time	308.05 seconds
Started	Mar 24 02:44:38 PM PDT 24
Finished	Mar 24 02:49:46 PM PDT 24
Peak memory	216712 kb
Host	smart-7fd4ab5f-aa88-4576-bf51-30b4c36e1106
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066970069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2066970069
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.1797101633
Short name	T396
Test name
Test status
Simulation time	404222142 ps
CPU time	1.54 seconds
Started	Mar 24 02:44:39 PM PDT 24
Finished	Mar 24 02:44:41 PM PDT 24
Peak memory	198500 kb
Host	smart-7963304a-5802-4912-9498-1e61d573709b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797101633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1797101633
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.4244442841
Short name	T429
Test name
Test status
Simulation time	5897062665 ps
CPU time	11.05 seconds
Started	Mar 24 02:44:35 PM PDT 24
Finished	Mar 24 02:44:46 PM PDT 24
Peak memory	197728 kb
Host	smart-eaf6e4c4-e58e-48b9-b1ca-f49ebd8e4c31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244442841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4244442841
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.283109333
Short name	T826
Test name
Test status
Simulation time	130870360409 ps
CPU time	182.21 seconds
Started	Mar 24 02:47:59 PM PDT 24
Finished	Mar 24 02:51:02 PM PDT 24
Peak memory	200148 kb
Host	smart-b6862c49-0b17-40b7-a2b7-6f705714f0cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283109333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.283109333
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.3155592419
Short name	T815
Test name
Test status
Simulation time	223556567683 ps
CPU time	337.16 seconds
Started	Mar 24 02:47:59 PM PDT 24
Finished	Mar 24 02:53:36 PM PDT 24
Peak memory	200140 kb
Host	smart-88d202b5-74f3-44cb-952b-085f81097659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155592419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3155592419
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.1827628355
Short name	T650
Test name
Test status
Simulation time	30051162923 ps
CPU time	12.55 seconds
Started	Mar 24 02:48:02 PM PDT 24
Finished	Mar 24 02:48:15 PM PDT 24
Peak memory	200032 kb
Host	smart-a7123564-7936-4407-b15e-bfb66ddf91db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827628355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1827628355
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.4046237523
Short name	T1107
Test name
Test status
Simulation time	42087517580 ps
CPU time	17.07 seconds
Started	Mar 24 02:47:59 PM PDT 24
Finished	Mar 24 02:48:17 PM PDT 24
Peak memory	199808 kb
Host	smart-cf2b6f6d-873e-4cd5-b6d4-022488c34ef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046237523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4046237523
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.997628585
Short name	T239
Test name
Test status
Simulation time	34801788205 ps
CPU time	66.94 seconds
Started	Mar 24 02:47:58 PM PDT 24
Finished	Mar 24 02:49:05 PM PDT 24
Peak memory	200096 kb
Host	smart-88d84ade-d3a8-4bfc-ad02-d3174f5d65f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997628585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.997628585
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.4147794536
Short name	T796
Test name
Test status
Simulation time	10663059263 ps
CPU time	17.07 seconds
Started	Mar 24 02:47:59 PM PDT 24
Finished	Mar 24 02:48:16 PM PDT 24
Peak memory	200188 kb
Host	smart-0c7a5de2-8a03-4a69-82f5-514a0132ce43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147794536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4147794536
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.3533920900
Short name	T1029
Test name
Test status
Simulation time	214794091523 ps
CPU time	95.38 seconds
Started	Mar 24 02:48:00 PM PDT 24
Finished	Mar 24 02:49:36 PM PDT 24
Peak memory	200112 kb
Host	smart-a96799ee-9b72-42a1-9a16-3c2d0d19e710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533920900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3533920900
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.4055587221
Short name	T184
Test name
Test status
Simulation time	32075502584 ps
CPU time	10.89 seconds
Started	Mar 24 02:48:01 PM PDT 24
Finished	Mar 24 02:48:13 PM PDT 24
Peak memory	200052 kb
Host	smart-892a5778-2ad1-40e9-a393-d4a98671e14d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055587221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.4055587221
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.101680541
Short name	T144
Test name
Test status
Simulation time	28184877141 ps
CPU time	16.74 seconds
Started	Mar 24 02:48:00 PM PDT 24
Finished	Mar 24 02:48:17 PM PDT 24
Peak memory	200108 kb
Host	smart-3fbdf730-1269-4b56-8c10-e1034ac4289c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101680541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.101680541
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.3438564076
Short name	T837
Test name
Test status
Simulation time	28702424 ps
CPU time	0.57 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:43:24 PM PDT 24
Peak memory	194992 kb
Host	smart-8d440ecf-d908-487c-a208-8905e3bdc9e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438564076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3438564076
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.360803787
Short name	T1069
Test name
Test status
Simulation time	155988699421 ps
CPU time	340.99 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:49:03 PM PDT 24
Peak memory	200104 kb
Host	smart-14463db8-3653-458e-8cd0-3b87bc143138
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360803787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.360803787
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.4170937975
Short name	T369
Test name
Test status
Simulation time	61929376091 ps
CPU time	88.97 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:44:57 PM PDT 24
Peak memory	199856 kb
Host	smart-a38ca0ad-edf8-4136-bbae-f7a4e133acc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170937975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4170937975
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.3431347257
Short name	T206
Test name
Test status
Simulation time	217714100614 ps
CPU time	266.46 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:47:52 PM PDT 24
Peak memory	200140 kb
Host	smart-8f6cf594-30c5-4053-9210-ad25f4c684fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431347257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3431347257
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_intr.513736457
Short name	T735
Test name
Test status
Simulation time	98035154561 ps
CPU time	161.4 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:46:06 PM PDT 24
Peak memory	196324 kb
Host	smart-d71f925e-9aa4-4fd0-ba1b-4308d4cd89c1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513736457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.513736457
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.3059367248
Short name	T354
Test name
Test status
Simulation time	157045437925 ps
CPU time	965.55 seconds
Started	Mar 24 02:43:18 PM PDT 24
Finished	Mar 24 02:59:24 PM PDT 24
Peak memory	200136 kb
Host	smart-a3061c0e-ff55-4e0b-9485-f1e508f234fd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3059367248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3059367248
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.3287022254
Short name	T1016
Test name
Test status
Simulation time	12022887484 ps
CPU time	25.09 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:52 PM PDT 24
Peak memory	198780 kb
Host	smart-0dab4b2d-8ca3-467c-9e8a-614732d3bcbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287022254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3287022254
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.2115293770
Short name	T347
Test name
Test status
Simulation time	54003532371 ps
CPU time	129.62 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:45:34 PM PDT 24
Peak memory	198088 kb
Host	smart-9fb854c2-14fb-415d-8b01-082390e27964
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115293770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2115293770
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.4008259209
Short name	T645
Test name
Test status
Simulation time	12220999363 ps
CPU time	589.35 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:53:16 PM PDT 24
Peak memory	200020 kb
Host	smart-a91000c8-90be-423e-80b8-b09b95267dce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4008259209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4008259209
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.2485866529
Short name	T1012
Test name
Test status
Simulation time	5825772919 ps
CPU time	49.3 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:44:23 PM PDT 24
Peak memory	199196 kb
Host	smart-227f9e77-4c03-4d30-bd27-e18269693c53
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2485866529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2485866529
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.4103180386
Short name	T744
Test name
Test status
Simulation time	27882103406 ps
CPU time	52.29 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:44:15 PM PDT 24
Peak memory	200172 kb
Host	smart-01481f19-223e-4dce-87a2-8913b4762b75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4103180386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4103180386
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.2814788710
Short name	T725
Test name
Test status
Simulation time	28579641035 ps
CPU time	43.45 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:44:04 PM PDT 24
Peak memory	196224 kb
Host	smart-092f7649-332c-47e2-b6c1-8d28ad2ede06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814788710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2814788710
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.1882836194
Short name	T7
Test name
Test status
Simulation time	65340179 ps
CPU time	0.83 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:23 PM PDT 24
Peak memory	218836 kb
Host	smart-2f3ef11f-770e-4ec6-ad45-283eb5131961
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882836194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1882836194
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/3.uart_smoke.3275277322
Short name	T655
Test name
Test status
Simulation time	290974893 ps
CPU time	1.39 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:43:22 PM PDT 24
Peak memory	198340 kb
Host	smart-3952d415-003c-410c-bd6c-753978628767
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275277322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3275277322
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_stress_all.3334108180
Short name	T499
Test name
Test status
Simulation time	179355760668 ps
CPU time	209.71 seconds
Started	Mar 24 02:43:18 PM PDT 24
Finished	Mar 24 02:46:49 PM PDT 24
Peak memory	200120 kb
Host	smart-271d20b1-b634-4759-81a5-69bf7cfdee88
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334108180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3334108180
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.3498887349
Short name	T688
Test name
Test status
Simulation time	1989254282 ps
CPU time	2.62 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:25 PM PDT 24
Peak memory	198836 kb
Host	smart-71dba04c-f75e-4611-ab43-4bf013658a9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498887349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3498887349
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.625776836
Short name	T293
Test name
Test status
Simulation time	48178291639 ps
CPU time	65.22 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:44:29 PM PDT 24
Peak memory	200032 kb
Host	smart-53458eb9-c664-4425-8b3a-87c4a6e19ee2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625776836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.625776836
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.4269782631
Short name	T995
Test name
Test status
Simulation time	15986688 ps
CPU time	0.58 seconds
Started	Mar 24 02:44:45 PM PDT 24
Finished	Mar 24 02:44:47 PM PDT 24
Peak memory	195628 kb
Host	smart-32a6965d-ccb0-48b8-96dc-86b6091302f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269782631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4269782631
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.4051793213
Short name	T325
Test name
Test status
Simulation time	164569329661 ps
CPU time	450.57 seconds
Started	Mar 24 02:44:46 PM PDT 24
Finished	Mar 24 02:52:17 PM PDT 24
Peak memory	200148 kb
Host	smart-67e68fc6-ffd7-4171-8061-ec201d040bb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051793213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4051793213
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.597995686
Short name	T155
Test name
Test status
Simulation time	16120877188 ps
CPU time	35.54 seconds
Started	Mar 24 02:44:43 PM PDT 24
Finished	Mar 24 02:45:20 PM PDT 24
Peak memory	200092 kb
Host	smart-14436a57-ef83-45a2-8e86-12db69f2c91d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597995686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.597995686
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/30.uart_intr.3829025544
Short name	T469
Test name
Test status
Simulation time	264143758663 ps
CPU time	198.38 seconds
Started	Mar 24 02:44:43 PM PDT 24
Finished	Mar 24 02:48:02 PM PDT 24
Peak memory	200092 kb
Host	smart-4f8c6223-da8a-44a0-935b-386d168b1096
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829025544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3829025544
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.1385096217
Short name	T993
Test name
Test status
Simulation time	87249588588 ps
CPU time	216.83 seconds
Started	Mar 24 02:44:48 PM PDT 24
Finished	Mar 24 02:48:26 PM PDT 24
Peak memory	200012 kb
Host	smart-980785f4-c114-4919-bbad-26daeb83ae59
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1385096217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1385096217
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_loopback.2704783453
Short name	T455
Test name
Test status
Simulation time	3733624702 ps
CPU time	4.18 seconds
Started	Mar 24 02:44:46 PM PDT 24
Finished	Mar 24 02:44:52 PM PDT 24
Peak memory	199052 kb
Host	smart-3eb333ed-3e18-437c-b2a1-5d01d2b7b295
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704783453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2704783453
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.834608946
Short name	T889
Test name
Test status
Simulation time	123491215842 ps
CPU time	33.27 seconds
Started	Mar 24 02:44:46 PM PDT 24
Finished	Mar 24 02:45:21 PM PDT 24
Peak memory	200292 kb
Host	smart-847998d1-86e3-4ebf-8c56-7f8e8b60c338
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834608946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.834608946
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_perf.259588153
Short name	T299
Test name
Test status
Simulation time	20234174398 ps
CPU time	1074.57 seconds
Started	Mar 24 02:44:46 PM PDT 24
Finished	Mar 24 03:02:41 PM PDT 24
Peak memory	200104 kb
Host	smart-261e1858-7a0b-41b1-b304-a6d8439a4a1d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=259588153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.259588153
Directory	/workspace/30.uart_perf/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.137750266
Short name	T588
Test name
Test status
Simulation time	1376674321 ps
CPU time	3.02 seconds
Started	Mar 24 02:44:44 PM PDT 24
Finished	Mar 24 02:44:48 PM PDT 24
Peak memory	197288 kb
Host	smart-59de836b-ee52-4cf0-b9c2-ecdb40055634
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=137750266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.137750266
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.3905559913
Short name	T742
Test name
Test status
Simulation time	191762040830 ps
CPU time	335.1 seconds
Started	Mar 24 02:44:44 PM PDT 24
Finished	Mar 24 02:50:20 PM PDT 24
Peak memory	200180 kb
Host	smart-303db364-a90f-442f-9116-4a7ee99be294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905559913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3905559913
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.4022538851
Short name	T306
Test name
Test status
Simulation time	1764044278 ps
CPU time	2.36 seconds
Started	Mar 24 02:44:42 PM PDT 24
Finished	Mar 24 02:44:46 PM PDT 24
Peak memory	195520 kb
Host	smart-9a402eb0-5b9b-4e24-a09d-3c46d98a11ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022538851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4022538851
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.2349823926
Short name	T310
Test name
Test status
Simulation time	436268674 ps
CPU time	1.97 seconds
Started	Mar 24 02:44:40 PM PDT 24
Finished	Mar 24 02:44:42 PM PDT 24
Peak memory	199728 kb
Host	smart-03d1e529-d1e7-48a8-a9d1-a6bd2404d5ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349823926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2349823926
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all.713486382
Short name	T1043
Test name
Test status
Simulation time	309472339783 ps
CPU time	1048.24 seconds
Started	Mar 24 02:44:41 PM PDT 24
Finished	Mar 24 03:02:10 PM PDT 24
Peak memory	216608 kb
Host	smart-5d1d9427-d2ac-495f-b5a9-e8b899ce2663
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713486382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.713486382
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/30.uart_stress_all_with_rand_reset.2102624200
Short name	T922
Test name
Test status
Simulation time	48674603075 ps
CPU time	590.96 seconds
Started	Mar 24 02:44:41 PM PDT 24
Finished	Mar 24 02:54:33 PM PDT 24
Peak memory	209600 kb
Host	smart-403678b2-8d9b-4b83-bcb7-38f2e77dec9a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102624200 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2102624200
Directory	/workspace/30.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.282521435
Short name	T762
Test name
Test status
Simulation time	1920927911 ps
CPU time	1.6 seconds
Started	Mar 24 02:44:47 PM PDT 24
Finished	Mar 24 02:44:50 PM PDT 24
Peak memory	198648 kb
Host	smart-1de6c6b8-94d6-4d29-ac06-2ac28f287384
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282521435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.282521435
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.2012943137
Short name	T314
Test name
Test status
Simulation time	34386717433 ps
CPU time	20.07 seconds
Started	Mar 24 02:44:39 PM PDT 24
Finished	Mar 24 02:44:59 PM PDT 24
Peak memory	200108 kb
Host	smart-5b1e8d15-447b-46a8-b500-4f05a0d26268
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012943137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2012943137
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.1256411732
Short name	T705
Test name
Test status
Simulation time	33996406 ps
CPU time	0.56 seconds
Started	Mar 24 02:44:47 PM PDT 24
Finished	Mar 24 02:44:49 PM PDT 24
Peak memory	195092 kb
Host	smart-f11b1757-39e1-4381-8015-f40948e800d3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256411732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1256411732
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.1696904578
Short name	T882
Test name
Test status
Simulation time	55194981988 ps
CPU time	50.17 seconds
Started	Mar 24 02:44:45 PM PDT 24
Finished	Mar 24 02:45:37 PM PDT 24
Peak memory	200088 kb
Host	smart-f90ecf76-0cd1-40bc-9e95-0ea88ad0a0fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696904578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1696904578
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.481132589
Short name	T886
Test name
Test status
Simulation time	75235128194 ps
CPU time	130.25 seconds
Started	Mar 24 02:44:43 PM PDT 24
Finished	Mar 24 02:46:54 PM PDT 24
Peak memory	200128 kb
Host	smart-84191631-a406-4b85-a441-02f39d64bafe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481132589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.481132589
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.3810105090
Short name	T388
Test name
Test status
Simulation time	20509468858 ps
CPU time	8.55 seconds
Started	Mar 24 02:44:44 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	197896 kb
Host	smart-8882ae48-1573-4dd4-ad78-1dcfe6fd6f06
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810105090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3810105090
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.3066298468
Short name	T1052
Test name
Test status
Simulation time	91560845656 ps
CPU time	675.96 seconds
Started	Mar 24 02:44:48 PM PDT 24
Finished	Mar 24 02:56:05 PM PDT 24
Peak memory	200152 kb
Host	smart-87048063-f3e3-45b7-8226-a2a7400fbe82
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3066298468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3066298468
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_loopback.466333222
Short name	T384
Test name
Test status
Simulation time	6885607068 ps
CPU time	8.57 seconds
Started	Mar 24 02:44:53 PM PDT 24
Finished	Mar 24 02:45:02 PM PDT 24
Peak memory	199752 kb
Host	smart-f137dc49-ae25-4b16-97bc-9da796e2a901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466333222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.466333222
Directory	/workspace/31.uart_loopback/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.2732932879
Short name	T335
Test name
Test status
Simulation time	74313403052 ps
CPU time	48.42 seconds
Started	Mar 24 02:44:48 PM PDT 24
Finished	Mar 24 02:45:37 PM PDT 24
Peak memory	199824 kb
Host	smart-86dfd39b-5fb5-442a-81cd-4ccf1bd104cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732932879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2732932879
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.4261018928
Short name	T542
Test name
Test status
Simulation time	18084209266 ps
CPU time	175.55 seconds
Started	Mar 24 02:44:54 PM PDT 24
Finished	Mar 24 02:47:50 PM PDT 24
Peak memory	200152 kb
Host	smart-96dd8780-4936-421c-9732-489042f5e1c6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4261018928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4261018928
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_oversample.2126137618
Short name	T946
Test name
Test status
Simulation time	7084200695 ps
CPU time	15.07 seconds
Started	Mar 24 02:44:43 PM PDT 24
Finished	Mar 24 02:45:00 PM PDT 24
Peak memory	198832 kb
Host	smart-cc772efd-b5d3-4534-a59c-323d8614be27
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2126137618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2126137618
Directory	/workspace/31.uart_rx_oversample/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.4098125272
Short name	T170
Test name
Test status
Simulation time	88909365652 ps
CPU time	75.85 seconds
Started	Mar 24 02:44:46 PM PDT 24
Finished	Mar 24 02:46:03 PM PDT 24
Peak memory	199972 kb
Host	smart-68af04c2-d24b-4034-8cac-b2f09bcec05e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098125272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.4098125272
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.2906385501
Short name	T540
Test name
Test status
Simulation time	4789875098 ps
CPU time	1.17 seconds
Started	Mar 24 02:44:56 PM PDT 24
Finished	Mar 24 02:44:57 PM PDT 24
Peak memory	196228 kb
Host	smart-715267a6-48e3-454a-8916-e83b0c70b9dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906385501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2906385501
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.3016018577
Short name	T625
Test name
Test status
Simulation time	479816863 ps
CPU time	1.92 seconds
Started	Mar 24 02:44:47 PM PDT 24
Finished	Mar 24 02:44:50 PM PDT 24
Peak memory	198652 kb
Host	smart-d5a5da10-90e4-44d3-90e8-510a04e3133e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016018577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3016018577
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_stress_all.1743846740
Short name	T154
Test name
Test status
Simulation time	706199479064 ps
CPU time	113.81 seconds
Started	Mar 24 02:44:47 PM PDT 24
Finished	Mar 24 02:46:41 PM PDT 24
Peak memory	215860 kb
Host	smart-e1ecf262-4ea6-4846-8523-68bf86701139
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743846740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1743846740
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.2412109745
Short name	T724
Test name
Test status
Simulation time	916441766 ps
CPU time	3.45 seconds
Started	Mar 24 02:44:51 PM PDT 24
Finished	Mar 24 02:44:55 PM PDT 24
Peak memory	199352 kb
Host	smart-131c20b9-61a7-458c-b798-893c437a4b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412109745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2412109745
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.1915949639
Short name	T575
Test name
Test status
Simulation time	50513501016 ps
CPU time	98.72 seconds
Started	Mar 24 02:44:45 PM PDT 24
Finished	Mar 24 02:46:25 PM PDT 24
Peak memory	200180 kb
Host	smart-58fcdda1-c74b-47d4-b466-e01de19c7345
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915949639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1915949639
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.264516432
Short name	T738
Test name
Test status
Simulation time	23042198 ps
CPU time	0.55 seconds
Started	Mar 24 02:44:51 PM PDT 24
Finished	Mar 24 02:44:52 PM PDT 24
Peak memory	195664 kb
Host	smart-67673f6b-12e4-4d08-9083-7410d4f90ec5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264516432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.264516432
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.3138407023
Short name	T1099
Test name
Test status
Simulation time	148041197025 ps
CPU time	45.95 seconds
Started	Mar 24 02:44:53 PM PDT 24
Finished	Mar 24 02:45:39 PM PDT 24
Peak memory	200172 kb
Host	smart-b023c4f0-163f-462f-a83a-6b9a3dccccfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138407023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3138407023
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.185327489
Short name	T412
Test name
Test status
Simulation time	176301648000 ps
CPU time	74.57 seconds
Started	Mar 24 02:44:46 PM PDT 24
Finished	Mar 24 02:46:02 PM PDT 24
Peak memory	200088 kb
Host	smart-7d195945-228b-4e23-a94b-730bf01f8b3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185327489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.185327489
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.1038776611
Short name	T252
Test name
Test status
Simulation time	121092828200 ps
CPU time	189.09 seconds
Started	Mar 24 02:44:49 PM PDT 24
Finished	Mar 24 02:47:59 PM PDT 24
Peak memory	200124 kb
Host	smart-a275361c-44c0-4728-b2e1-41bcd3685c51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038776611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1038776611
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_intr.956148755
Short name	T1045
Test name
Test status
Simulation time	15511858783 ps
CPU time	6.71 seconds
Started	Mar 24 02:44:48 PM PDT 24
Finished	Mar 24 02:44:56 PM PDT 24
Peak memory	200032 kb
Host	smart-8fccfa12-3535-4b2d-ab46-cbe3ac52f016
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956148755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.956148755
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.3779606647
Short name	T811
Test name
Test status
Simulation time	144917633267 ps
CPU time	797.69 seconds
Started	Mar 24 02:44:51 PM PDT 24
Finished	Mar 24 02:58:09 PM PDT 24
Peak memory	200076 kb
Host	smart-0971f2fd-d2dc-4029-ab01-7e5e888b5175
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3779606647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3779606647
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.803076891
Short name	T853
Test name
Test status
Simulation time	4288685826 ps
CPU time	3.26 seconds
Started	Mar 24 02:44:48 PM PDT 24
Finished	Mar 24 02:44:52 PM PDT 24
Peak memory	199280 kb
Host	smart-085a75d3-d495-4fec-a475-5b4d2d752a60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803076891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.803076891
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_noise_filter.559959408
Short name	T647
Test name
Test status
Simulation time	45878603050 ps
CPU time	17.25 seconds
Started	Mar 24 02:44:48 PM PDT 24
Finished	Mar 24 02:45:06 PM PDT 24
Peak memory	196228 kb
Host	smart-e8d2bd23-4cd0-419a-8032-f0639ccf7103
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559959408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.559959408
Directory	/workspace/32.uart_noise_filter/latest

Test location	/workspace/coverage/default/32.uart_perf.4128807076
Short name	T295
Test name
Test status
Simulation time	14712455926 ps
CPU time	251.32 seconds
Started	Mar 24 02:44:50 PM PDT 24
Finished	Mar 24 02:49:01 PM PDT 24
Peak memory	200064 kb
Host	smart-b9f7e2f5-5a44-40a2-a03b-e3fa823d256c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4128807076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4128807076
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.480051000
Short name	T519
Test name
Test status
Simulation time	3746394105 ps
CPU time	13.55 seconds
Started	Mar 24 02:44:47 PM PDT 24
Finished	Mar 24 02:45:01 PM PDT 24
Peak memory	198116 kb
Host	smart-bc6a22e8-1bd1-4da6-a85a-11a2857c83a1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=480051000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.480051000
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.2363228295
Short name	T1032
Test name
Test status
Simulation time	34152918330 ps
CPU time	14.62 seconds
Started	Mar 24 02:44:51 PM PDT 24
Finished	Mar 24 02:45:06 PM PDT 24
Peak memory	197396 kb
Host	smart-52776061-3a6b-40f2-836f-c6c9d9eb0a75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363228295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2363228295
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.1709338340
Short name	T631
Test name
Test status
Simulation time	2605749841 ps
CPU time	1.66 seconds
Started	Mar 24 02:44:49 PM PDT 24
Finished	Mar 24 02:44:52 PM PDT 24
Peak memory	195912 kb
Host	smart-e4384a1d-cab3-47bd-b043-822e2142bf91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709338340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1709338340
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.233758939
Short name	T907
Test name
Test status
Simulation time	5989187103 ps
CPU time	9.92 seconds
Started	Mar 24 02:44:50 PM PDT 24
Finished	Mar 24 02:45:01 PM PDT 24
Peak memory	199952 kb
Host	smart-6fe07ae0-56e0-4103-9ac3-d203091f6f6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233758939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.233758939
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_stress_all.1272260494
Short name	T975
Test name
Test status
Simulation time	252877679130 ps
CPU time	168.31 seconds
Started	Mar 24 02:44:51 PM PDT 24
Finished	Mar 24 02:47:40 PM PDT 24
Peak memory	216220 kb
Host	smart-bc3dd15f-2ffd-4cbf-9b71-406c397ee2fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272260494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1272260494
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.285684094
Short name	T833
Test name
Test status
Simulation time	1367467038 ps
CPU time	2.77 seconds
Started	Mar 24 02:44:50 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	198836 kb
Host	smart-3c34c7e8-0db5-4961-a732-95f92c1a7cbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285684094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.285684094
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.470184739
Short name	T48
Test name
Test status
Simulation time	140378772503 ps
CPU time	42.59 seconds
Started	Mar 24 02:44:47 PM PDT 24
Finished	Mar 24 02:45:31 PM PDT 24
Peak memory	200180 kb
Host	smart-fb2111b1-5a76-4c15-aada-c8eb922add95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470184739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.470184739
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.463288557
Short name	T479
Test name
Test status
Simulation time	49216212 ps
CPU time	0.55 seconds
Started	Mar 24 02:44:52 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	195572 kb
Host	smart-68bdc800-7421-47eb-9196-376c9824fd76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463288557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.463288557
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.2518500268
Short name	T303
Test name
Test status
Simulation time	62724165693 ps
CPU time	33.55 seconds
Started	Mar 24 02:44:54 PM PDT 24
Finished	Mar 24 02:45:27 PM PDT 24
Peak memory	200136 kb
Host	smart-1b5fbd01-af1a-463a-8b47-3fe6a0bfa488
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518500268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2518500268
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.3134220527
Short name	T268
Test name
Test status
Simulation time	71422142430 ps
CPU time	53.77 seconds
Started	Mar 24 02:44:51 PM PDT 24
Finished	Mar 24 02:45:45 PM PDT 24
Peak memory	200144 kb
Host	smart-41426ed3-5524-41e6-bb86-8e6bc37734a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134220527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3134220527
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.3794971058
Short name	T598
Test name
Test status
Simulation time	76384389684 ps
CPU time	182.28 seconds
Started	Mar 24 02:44:52 PM PDT 24
Finished	Mar 24 02:47:55 PM PDT 24
Peak memory	200156 kb
Host	smart-b1d641ba-e653-4436-8e27-d8e1454f329c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794971058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3794971058
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.123132750
Short name	T739
Test name
Test status
Simulation time	240019891191 ps
CPU time	373.41 seconds
Started	Mar 24 02:44:54 PM PDT 24
Finished	Mar 24 02:51:07 PM PDT 24
Peak memory	198652 kb
Host	smart-d75398a2-680a-4ec5-8eec-41f7f0120110
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123132750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.123132750
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.3267919559
Short name	T809
Test name
Test status
Simulation time	204018341799 ps
CPU time	808.1 seconds
Started	Mar 24 02:44:55 PM PDT 24
Finished	Mar 24 02:58:23 PM PDT 24
Peak memory	200108 kb
Host	smart-45bb84a6-7adf-455c-a287-b555802845a3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3267919559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3267919559
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.2959540059
Short name	T626
Test name
Test status
Simulation time	5684301559 ps
CPU time	14.13 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:45:11 PM PDT 24
Peak memory	199552 kb
Host	smart-d37bbaa3-89da-404b-aa6f-b7a9dfeb1b1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959540059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2959540059
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.4249740562
Short name	T635
Test name
Test status
Simulation time	65864119596 ps
CPU time	105.39 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:46:42 PM PDT 24
Peak memory	199416 kb
Host	smart-830c3c70-21d7-4c5d-a69a-427406610a11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249740562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4249740562
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.3687197069
Short name	T505
Test name
Test status
Simulation time	14024931594 ps
CPU time	389.58 seconds
Started	Mar 24 02:44:50 PM PDT 24
Finished	Mar 24 02:51:21 PM PDT 24
Peak memory	200084 kb
Host	smart-ab4c2b21-137d-49c6-bdc4-7ac0ab5f06ff
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3687197069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3687197069
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.3543574104
Short name	T392
Test name
Test status
Simulation time	7110314440 ps
CPU time	59.99 seconds
Started	Mar 24 02:44:52 PM PDT 24
Finished	Mar 24 02:45:52 PM PDT 24
Peak memory	197936 kb
Host	smart-1c15e298-3250-490b-a823-e634339e6c37
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3543574104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3543574104
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.3658713838
Short name	T634
Test name
Test status
Simulation time	15490814127 ps
CPU time	33.31 seconds
Started	Mar 24 02:44:51 PM PDT 24
Finished	Mar 24 02:45:25 PM PDT 24
Peak memory	200052 kb
Host	smart-73fc9c30-84ed-474c-94ff-09cfc4e6ee95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658713838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3658713838
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.4049922130
Short name	T351
Test name
Test status
Simulation time	1927057969 ps
CPU time	1.44 seconds
Started	Mar 24 02:44:52 PM PDT 24
Finished	Mar 24 02:44:54 PM PDT 24
Peak memory	195548 kb
Host	smart-320828e7-c103-4277-8ee9-b56ebcc660ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049922130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4049922130
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.3905631670
Short name	T803
Test name
Test status
Simulation time	5364888845 ps
CPU time	15.93 seconds
Started	Mar 24 02:44:56 PM PDT 24
Finished	Mar 24 02:45:12 PM PDT 24
Peak memory	200024 kb
Host	smart-513b17c3-48a7-4a58-92fd-3b8bb13ca8dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905631670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3905631670
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all.2393895338
Short name	T1076
Test name
Test status
Simulation time	93325438562 ps
CPU time	37.8 seconds
Started	Mar 24 02:44:52 PM PDT 24
Finished	Mar 24 02:45:30 PM PDT 24
Peak memory	200164 kb
Host	smart-54792fd8-7b4b-40e8-b6ec-26073d4535f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393895338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2393895338
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.3285773466
Short name	T523
Test name
Test status
Simulation time	6627145236 ps
CPU time	6.15 seconds
Started	Mar 24 02:44:53 PM PDT 24
Finished	Mar 24 02:44:59 PM PDT 24
Peak memory	199884 kb
Host	smart-67d01f49-aadf-4a84-bd3b-77efc27e4df3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285773466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3285773466
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.3378086403
Short name	T881
Test name
Test status
Simulation time	55505641309 ps
CPU time	77.28 seconds
Started	Mar 24 02:44:52 PM PDT 24
Finished	Mar 24 02:46:09 PM PDT 24
Peak memory	200108 kb
Host	smart-4181c914-29a0-470e-969a-d8c181fb038e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378086403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3378086403
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.3743838742
Short name	T444
Test name
Test status
Simulation time	35225502 ps
CPU time	0.53 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:44:58 PM PDT 24
Peak memory	194928 kb
Host	smart-a5f90ce6-7b7d-43ef-b73a-d22bf594790a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743838742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3743838742
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.3231823997
Short name	T1033
Test name
Test status
Simulation time	105809861764 ps
CPU time	87.65 seconds
Started	Mar 24 02:44:56 PM PDT 24
Finished	Mar 24 02:46:24 PM PDT 24
Peak memory	200036 kb
Host	smart-1ed1543c-c667-448d-8c35-90be0eb0098e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231823997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3231823997
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.2424430007
Short name	T459
Test name
Test status
Simulation time	13600673903 ps
CPU time	13.81 seconds
Started	Mar 24 02:44:55 PM PDT 24
Finished	Mar 24 02:45:09 PM PDT 24
Peak memory	197964 kb
Host	smart-f4d30e67-6aae-4e3d-8e24-a9131827ad88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424430007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2424430007
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.3114012024
Short name	T663
Test name
Test status
Simulation time	118755522219 ps
CPU time	129.2 seconds
Started	Mar 24 02:44:58 PM PDT 24
Finished	Mar 24 02:47:07 PM PDT 24
Peak memory	200088 kb
Host	smart-02a2f107-dac7-46fd-9b60-1b11f117f0e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114012024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3114012024
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_intr.4043733871
Short name	T1060
Test name
Test status
Simulation time	28363093887 ps
CPU time	47.56 seconds
Started	Mar 24 02:45:01 PM PDT 24
Finished	Mar 24 02:45:49 PM PDT 24
Peak memory	200152 kb
Host	smart-c6c0b83a-ec0e-4410-b33e-cc185965651d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043733871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4043733871
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.157155316
Short name	T276
Test name
Test status
Simulation time	169559106733 ps
CPU time	228.93 seconds
Started	Mar 24 02:44:56 PM PDT 24
Finished	Mar 24 02:48:45 PM PDT 24
Peak memory	200056 kb
Host	smart-12970dc5-8adc-4779-9a87-e3e20cb2f5ee
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=157155316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.157155316
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.2746231493
Short name	T568
Test name
Test status
Simulation time	8359705855 ps
CPU time	5.38 seconds
Started	Mar 24 02:44:59 PM PDT 24
Finished	Mar 24 02:45:05 PM PDT 24
Peak memory	199820 kb
Host	smart-f93050a3-8515-40cd-b904-1d44f9ce81e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746231493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2746231493
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.1850628490
Short name	T287
Test name
Test status
Simulation time	66973417912 ps
CPU time	40.87 seconds
Started	Mar 24 02:45:00 PM PDT 24
Finished	Mar 24 02:45:41 PM PDT 24
Peak memory	200204 kb
Host	smart-d9f8a392-b162-4f65-b924-56c4cce1f350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850628490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1850628490
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_perf.3553611414
Short name	T318
Test name
Test status
Simulation time	16148180478 ps
CPU time	780.23 seconds
Started	Mar 24 02:44:59 PM PDT 24
Finished	Mar 24 02:58:00 PM PDT 24
Peak memory	200080 kb
Host	smart-36f50748-e7f7-451a-9c89-2bcb15f1d76a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3553611414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3553611414
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.2145719581
Short name	T867
Test name
Test status
Simulation time	2425848922 ps
CPU time	7.96 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:45:05 PM PDT 24
Peak memory	198408 kb
Host	smart-2cd1fbe4-cb12-44ee-9be8-d5307b045587
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2145719581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2145719581
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.1598362233
Short name	T1126
Test name
Test status
Simulation time	40227807069 ps
CPU time	20.33 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:45:18 PM PDT 24
Peak memory	200164 kb
Host	smart-84d60a29-9b07-428f-b671-ee3fedbbd145
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598362233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1598362233
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.3424456072
Short name	T443
Test name
Test status
Simulation time	4581818166 ps
CPU time	1.09 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:44:58 PM PDT 24
Peak memory	196520 kb
Host	smart-c519ae81-ba28-43d6-af08-8e7178b591b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424456072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3424456072
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.3972129343
Short name	T960
Test name
Test status
Simulation time	676682586 ps
CPU time	1.42 seconds
Started	Mar 24 02:44:55 PM PDT 24
Finished	Mar 24 02:44:56 PM PDT 24
Peak memory	199888 kb
Host	smart-68cabc31-fcc5-47d0-9bf6-236b62aad588
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972129343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3972129343
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_stress_all.528647583
Short name	T516
Test name
Test status
Simulation time	313096107905 ps
CPU time	172.31 seconds
Started	Mar 24 02:44:56 PM PDT 24
Finished	Mar 24 02:47:49 PM PDT 24
Peak memory	200196 kb
Host	smart-7e952305-68f5-43ca-b5a1-6e68c20e54ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528647583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.528647583
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.1968356645
Short name	T300
Test name
Test status
Simulation time	6557904538 ps
CPU time	39.12 seconds
Started	Mar 24 02:45:00 PM PDT 24
Finished	Mar 24 02:45:39 PM PDT 24
Peak memory	199612 kb
Host	smart-f17305d0-4c8d-4136-8d5a-0790976c0373
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968356645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1968356645
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.407525537
Short name	T924
Test name
Test status
Simulation time	18118495255 ps
CPU time	14.61 seconds
Started	Mar 24 02:44:52 PM PDT 24
Finished	Mar 24 02:45:08 PM PDT 24
Peak memory	200168 kb
Host	smart-573309e6-58a0-4503-8547-d2f154791fff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407525537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.407525537
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.2555896292
Short name	T1039
Test name
Test status
Simulation time	50795976 ps
CPU time	0.55 seconds
Started	Mar 24 02:45:01 PM PDT 24
Finished	Mar 24 02:45:02 PM PDT 24
Peak memory	195652 kb
Host	smart-3a5eee6c-8cb1-4de3-9ece-0f2eb8a89a37
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555896292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2555896292
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.1886760698
Short name	T659
Test name
Test status
Simulation time	30649493559 ps
CPU time	14.23 seconds
Started	Mar 24 02:45:01 PM PDT 24
Finished	Mar 24 02:45:16 PM PDT 24
Peak memory	200060 kb
Host	smart-2c28d386-3cc4-43fe-805f-87f8f059ca8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886760698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1886760698
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.3406768504
Short name	T599
Test name
Test status
Simulation time	34682962208 ps
CPU time	65.43 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:46:03 PM PDT 24
Peak memory	200088 kb
Host	smart-2cc73678-98c6-4310-9f07-34dfdba0db68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3406768504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3406768504
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.206816251
Short name	T244
Test name
Test status
Simulation time	120660559416 ps
CPU time	177.75 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:47:55 PM PDT 24
Peak memory	200188 kb
Host	smart-27970a83-9886-4964-ae70-b41f50c3e141
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206816251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.206816251
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/35.uart_intr.882839050
Short name	T780
Test name
Test status
Simulation time	55166580387 ps
CPU time	30.01 seconds
Started	Mar 24 02:45:04 PM PDT 24
Finished	Mar 24 02:45:34 PM PDT 24
Peak memory	200372 kb
Host	smart-f3880b74-7196-4ccd-a540-1185ad900d51
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882839050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.882839050
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.1005322243
Short name	T55
Test name
Test status
Simulation time	83831281222 ps
CPU time	328.92 seconds
Started	Mar 24 02:45:05 PM PDT 24
Finished	Mar 24 02:50:34 PM PDT 24
Peak memory	200108 kb
Host	smart-bbd2b68d-58ed-4706-8141-f1a8bba0d9a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1005322243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1005322243
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.3821439742
Short name	T756
Test name
Test status
Simulation time	2857754130 ps
CPU time	5.48 seconds
Started	Mar 24 02:45:02 PM PDT 24
Finished	Mar 24 02:45:07 PM PDT 24
Peak memory	197696 kb
Host	smart-5e2839c7-9669-4888-890e-45955128b474
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821439742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3821439742
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_noise_filter.218922719
Short name	T627
Test name
Test status
Simulation time	30109574686 ps
CPU time	68.81 seconds
Started	Mar 24 02:45:02 PM PDT 24
Finished	Mar 24 02:46:11 PM PDT 24
Peak memory	200252 kb
Host	smart-3554f5ad-208f-43b3-81bd-1f1d737b56f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218922719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.218922719
Directory	/workspace/35.uart_noise_filter/latest

Test location	/workspace/coverage/default/35.uart_perf.2246367800
Short name	T533
Test name
Test status
Simulation time	24993840300 ps
CPU time	278.84 seconds
Started	Mar 24 02:45:07 PM PDT 24
Finished	Mar 24 02:49:46 PM PDT 24
Peak memory	200084 kb
Host	smart-65f6ea04-77d3-4f5b-8cb5-a29092f84ff4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2246367800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2246367800
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.1282800591
Short name	T1027
Test name
Test status
Simulation time	6908873270 ps
CPU time	39.62 seconds
Started	Mar 24 02:44:59 PM PDT 24
Finished	Mar 24 02:45:38 PM PDT 24
Peak memory	198388 kb
Host	smart-8d872ae7-fd3e-4596-bc26-b0682d412af6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1282800591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1282800591
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.66248051
Short name	T775
Test name
Test status
Simulation time	15238406484 ps
CPU time	27.83 seconds
Started	Mar 24 02:45:01 PM PDT 24
Finished	Mar 24 02:45:29 PM PDT 24
Peak memory	199996 kb
Host	smart-98900c70-d2d4-48e0-a1c6-917a00353f42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66248051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.66248051
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.115737319
Short name	T450
Test name
Test status
Simulation time	2179186159 ps
CPU time	1.72 seconds
Started	Mar 24 02:45:04 PM PDT 24
Finished	Mar 24 02:45:06 PM PDT 24
Peak memory	195876 kb
Host	smart-553fc88b-f2c6-476b-9f07-10ed0e9d32d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115737319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.115737319
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.2254661407
Short name	T407
Test name
Test status
Simulation time	708898951 ps
CPU time	1.87 seconds
Started	Mar 24 02:44:57 PM PDT 24
Finished	Mar 24 02:44:59 PM PDT 24
Peak memory	199944 kb
Host	smart-8b9bce6d-5055-4a6c-ac4c-e6b095da02db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254661407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2254661407
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all.946137318
Short name	T753
Test name
Test status
Simulation time	351515710238 ps
CPU time	188.91 seconds
Started	Mar 24 02:45:06 PM PDT 24
Finished	Mar 24 02:48:15 PM PDT 24
Peak memory	200176 kb
Host	smart-cee72a2a-438a-49e2-98f6-e1cbb9d96d27
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946137318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.946137318
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.3095448608
Short name	T619
Test name
Test status
Simulation time	1495612738 ps
CPU time	1.78 seconds
Started	Mar 24 02:45:05 PM PDT 24
Finished	Mar 24 02:45:07 PM PDT 24
Peak memory	198460 kb
Host	smart-7cde8377-b4ea-458b-a1c4-0ec434a1f093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095448608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3095448608
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.3527604146
Short name	T501
Test name
Test status
Simulation time	94437533390 ps
CPU time	63.92 seconds
Started	Mar 24 02:44:58 PM PDT 24
Finished	Mar 24 02:46:02 PM PDT 24
Peak memory	200164 kb
Host	smart-77b980e5-be3a-4907-98a6-53c48a8b0e04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527604146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3527604146
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.1981627771
Short name	T900
Test name
Test status
Simulation time	20639731 ps
CPU time	0.58 seconds
Started	Mar 24 02:45:05 PM PDT 24
Finished	Mar 24 02:45:06 PM PDT 24
Peak memory	195612 kb
Host	smart-75cf505c-e302-4037-b424-be4155331c51
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981627771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1981627771
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.853808177
Short name	T1082
Test name
Test status
Simulation time	33943883516 ps
CPU time	51.31 seconds
Started	Mar 24 02:45:07 PM PDT 24
Finished	Mar 24 02:45:59 PM PDT 24
Peak memory	200180 kb
Host	smart-005fa3b6-9a89-476f-9ee1-94dc03b18ad5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853808177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.853808177
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.3539126018
Short name	T319
Test name
Test status
Simulation time	119223927917 ps
CPU time	153.98 seconds
Started	Mar 24 02:45:02 PM PDT 24
Finished	Mar 24 02:47:36 PM PDT 24
Peak memory	200048 kb
Host	smart-a06b885e-080e-43a4-9a63-21bda905b539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539126018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3539126018
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.1827865575
Short name	T236
Test name
Test status
Simulation time	42778345460 ps
CPU time	19.73 seconds
Started	Mar 24 02:45:03 PM PDT 24
Finished	Mar 24 02:45:23 PM PDT 24
Peak memory	199948 kb
Host	smart-1868fdc1-da79-41f5-9fb6-3a71a27e6d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827865575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1827865575
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_intr.2408985686
Short name	T13
Test name
Test status
Simulation time	86878546600 ps
CPU time	141.68 seconds
Started	Mar 24 02:45:02 PM PDT 24
Finished	Mar 24 02:47:23 PM PDT 24
Peak memory	199352 kb
Host	smart-8f48596a-fdb1-4590-9a61-43e864b3e2b4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408985686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2408985686
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.2610606147
Short name	T418
Test name
Test status
Simulation time	121997474318 ps
CPU time	272.17 seconds
Started	Mar 24 02:45:08 PM PDT 24
Finished	Mar 24 02:49:40 PM PDT 24
Peak memory	200124 kb
Host	smart-662d3e4c-d884-4004-ab86-6690436c63f5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2610606147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2610606147
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.3462851998
Short name	T1022
Test name
Test status
Simulation time	7106997671 ps
CPU time	14.04 seconds
Started	Mar 24 02:45:06 PM PDT 24
Finished	Mar 24 02:45:20 PM PDT 24
Peak memory	199748 kb
Host	smart-543709dd-627d-4bd4-a53d-281d846ff27f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462851998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3462851998
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.1990904488
Short name	T561
Test name
Test status
Simulation time	29605222911 ps
CPU time	26.63 seconds
Started	Mar 24 02:45:03 PM PDT 24
Finished	Mar 24 02:45:29 PM PDT 24
Peak memory	199556 kb
Host	smart-694defe7-884e-47cd-8527-bb5283a45816
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990904488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1990904488
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.2793863857
Short name	T51
Test name
Test status
Simulation time	9644084822 ps
CPU time	580.07 seconds
Started	Mar 24 02:45:11 PM PDT 24
Finished	Mar 24 02:54:51 PM PDT 24
Peak memory	200160 kb
Host	smart-6c1d7836-00ef-4e97-853b-471905e62747
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2793863857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2793863857
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.4276564570
Short name	T719
Test name
Test status
Simulation time	4312878628 ps
CPU time	8.69 seconds
Started	Mar 24 02:45:04 PM PDT 24
Finished	Mar 24 02:45:13 PM PDT 24
Peak memory	198736 kb
Host	smart-ac2c8fe4-7c53-4368-8b19-3d9bd1cba2ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4276564570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4276564570
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.389927900
Short name	T173
Test name
Test status
Simulation time	33614734986 ps
CPU time	19.62 seconds
Started	Mar 24 02:45:01 PM PDT 24
Finished	Mar 24 02:45:21 PM PDT 24
Peak memory	200164 kb
Host	smart-5330c495-055e-40d7-8f93-086a38ff7f76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389927900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.389927900
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.3017320461
Short name	T1035
Test name
Test status
Simulation time	1388523189 ps
CPU time	3 seconds
Started	Mar 24 02:45:03 PM PDT 24
Finished	Mar 24 02:45:06 PM PDT 24
Peak memory	195800 kb
Host	smart-284dcfe6-2313-4da9-aa2a-bd5de953e364
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017320461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3017320461
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.3528374696
Short name	T110
Test name
Test status
Simulation time	933304449 ps
CPU time	1.89 seconds
Started	Mar 24 02:45:00 PM PDT 24
Finished	Mar 24 02:45:02 PM PDT 24
Peak memory	198712 kb
Host	smart-0f711fb7-e795-4fd5-a6da-7ce489546320
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528374696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3528374696
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all.2052254244
Short name	T727
Test name
Test status
Simulation time	183773864740 ps
CPU time	429.33 seconds
Started	Mar 24 02:45:04 PM PDT 24
Finished	Mar 24 02:52:14 PM PDT 24
Peak memory	208468 kb
Host	smart-92c972ec-165f-4905-9f36-8356b35fb42d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052254244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2052254244
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.3826982589
Short name	T672
Test name
Test status
Simulation time	878050463 ps
CPU time	2.9 seconds
Started	Mar 24 02:45:02 PM PDT 24
Finished	Mar 24 02:45:04 PM PDT 24
Peak memory	199152 kb
Host	smart-1257b221-8475-452f-83fb-9811606f2219
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826982589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3826982589
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.2966255411
Short name	T544
Test name
Test status
Simulation time	38733983733 ps
CPU time	70.77 seconds
Started	Mar 24 02:45:06 PM PDT 24
Finished	Mar 24 02:46:17 PM PDT 24
Peak memory	200116 kb
Host	smart-9d6b54b8-c4c9-4227-8000-d210d56c9dd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966255411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2966255411
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.4284039727
Short name	T1092
Test name
Test status
Simulation time	16836300 ps
CPU time	0.56 seconds
Started	Mar 24 02:45:13 PM PDT 24
Finished	Mar 24 02:45:14 PM PDT 24
Peak memory	195628 kb
Host	smart-392f4c39-7b81-4fd8-86f2-a53131ec3609
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284039727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4284039727
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.4049191489
Short name	T275
Test name
Test status
Simulation time	209798494695 ps
CPU time	107.38 seconds
Started	Mar 24 02:45:07 PM PDT 24
Finished	Mar 24 02:46:54 PM PDT 24
Peak memory	200156 kb
Host	smart-b2f251b6-820f-4209-b4ae-f27580d90822
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049191489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4049191489
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.3694878725
Short name	T698
Test name
Test status
Simulation time	179955291377 ps
CPU time	34.12 seconds
Started	Mar 24 02:45:13 PM PDT 24
Finished	Mar 24 02:45:48 PM PDT 24
Peak memory	200056 kb
Host	smart-3cd18f21-a0af-401b-ae21-64d0358cc0b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694878725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3694878725
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.3007511493
Short name	T562
Test name
Test status
Simulation time	32901757817 ps
CPU time	26.96 seconds
Started	Mar 24 02:45:06 PM PDT 24
Finished	Mar 24 02:45:33 PM PDT 24
Peak memory	199960 kb
Host	smart-97bc6165-0075-4801-810f-97b93e5b3468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007511493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3007511493
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_intr.2681683488
Short name	T1103
Test name
Test status
Simulation time	15959872221 ps
CPU time	25.52 seconds
Started	Mar 24 02:45:10 PM PDT 24
Finished	Mar 24 02:45:35 PM PDT 24
Peak memory	196868 kb
Host	smart-2f607612-5f1c-4fa1-b57d-7d2ee494a6c3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681683488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2681683488
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.2150195238
Short name	T402
Test name
Test status
Simulation time	155628464347 ps
CPU time	297.65 seconds
Started	Mar 24 02:45:15 PM PDT 24
Finished	Mar 24 02:50:13 PM PDT 24
Peak memory	200356 kb
Host	smart-909eabed-91cc-42d3-9fe4-10517f0fb1e7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2150195238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2150195238
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.4067562995
Short name	T755
Test name
Test status
Simulation time	6192480712 ps
CPU time	9.76 seconds
Started	Mar 24 02:45:06 PM PDT 24
Finished	Mar 24 02:45:16 PM PDT 24
Peak memory	197960 kb
Host	smart-482b43f5-c320-4f45-8e75-8c89f9c15c77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067562995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4067562995
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.4194867162
Short name	T716
Test name
Test status
Simulation time	64538685133 ps
CPU time	49.19 seconds
Started	Mar 24 02:45:06 PM PDT 24
Finished	Mar 24 02:45:55 PM PDT 24
Peak memory	200260 kb
Host	smart-f48ac8c0-5b64-4111-b9eb-dc09b12228ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194867162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4194867162
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.3761832080
Short name	T416
Test name
Test status
Simulation time	5855886835 ps
CPU time	75.42 seconds
Started	Mar 24 02:45:14 PM PDT 24
Finished	Mar 24 02:46:29 PM PDT 24
Peak memory	200024 kb
Host	smart-ac03d3cf-144b-443e-8c09-ae4d4121553b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3761832080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3761832080
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.2655531331
Short name	T426
Test name
Test status
Simulation time	5535930098 ps
CPU time	40.28 seconds
Started	Mar 24 02:45:09 PM PDT 24
Finished	Mar 24 02:45:50 PM PDT 24
Peak memory	198172 kb
Host	smart-3e0aa93e-c6a4-4765-8a7d-cd32e071346d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2655531331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2655531331
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.2373812978
Short name	T759
Test name
Test status
Simulation time	47391284421 ps
CPU time	17.77 seconds
Started	Mar 24 02:45:14 PM PDT 24
Finished	Mar 24 02:45:32 PM PDT 24
Peak memory	200064 kb
Host	smart-46f70a43-eca6-40cf-b5da-e8c42aedb247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373812978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2373812978
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.1201336638
Short name	T694
Test name
Test status
Simulation time	658603463 ps
CPU time	1.11 seconds
Started	Mar 24 02:45:13 PM PDT 24
Finished	Mar 24 02:45:14 PM PDT 24
Peak memory	195476 kb
Host	smart-7d90f290-3939-4928-b42b-0b71789baff7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201336638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1201336638
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.245224355
Short name	T660
Test name
Test status
Simulation time	294857767 ps
CPU time	1.97 seconds
Started	Mar 24 02:45:05 PM PDT 24
Finished	Mar 24 02:45:07 PM PDT 24
Peak memory	198204 kb
Host	smart-159dcd5b-8310-4511-a7ea-dc866a589fce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245224355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.245224355
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_stress_all_with_rand_reset.2062133782
Short name	T1122
Test name
Test status
Simulation time	58210681588 ps
CPU time	181.18 seconds
Started	Mar 24 02:45:10 PM PDT 24
Finished	Mar 24 02:48:11 PM PDT 24
Peak memory	216856 kb
Host	smart-2ed4c8e7-d76c-4148-b23c-a1081e18534a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062133782 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2062133782
Directory	/workspace/37.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.4089501516
Short name	T80
Test name
Test status
Simulation time	4187955596 ps
CPU time	1.46 seconds
Started	Mar 24 02:45:07 PM PDT 24
Finished	Mar 24 02:45:08 PM PDT 24
Peak memory	198876 kb
Host	smart-8ecd0083-8ca8-4988-8478-fde42ab1106c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089501516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4089501516
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.1392709846
Short name	T985
Test name
Test status
Simulation time	43297602875 ps
CPU time	39.43 seconds
Started	Mar 24 02:45:07 PM PDT 24
Finished	Mar 24 02:45:47 PM PDT 24
Peak memory	200072 kb
Host	smart-e99fd64d-c394-4bcf-89f5-bb20fcbdca1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392709846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1392709846
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.3981285187
Short name	T640
Test name
Test status
Simulation time	41419880 ps
CPU time	0.56 seconds
Started	Mar 24 02:45:16 PM PDT 24
Finished	Mar 24 02:45:17 PM PDT 24
Peak memory	195652 kb
Host	smart-4c273b5f-ebd1-4f95-b34c-d3158c335c05
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981285187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3981285187
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.3624810720
Short name	T158
Test name
Test status
Simulation time	71295882629 ps
CPU time	32.48 seconds
Started	Mar 24 02:45:15 PM PDT 24
Finished	Mar 24 02:45:47 PM PDT 24
Peak memory	200376 kb
Host	smart-9fe9472a-24a3-45e2-9105-2da3b4f5e80f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624810720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3624810720
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.200561069
Short name	T163
Test name
Test status
Simulation time	20976278446 ps
CPU time	33.8 seconds
Started	Mar 24 02:45:11 PM PDT 24
Finished	Mar 24 02:45:45 PM PDT 24
Peak memory	200080 kb
Host	smart-e7942b08-c129-44e5-8f0f-7957b5a722ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200561069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.200561069
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.85407814
Short name	T243
Test name
Test status
Simulation time	65884690699 ps
CPU time	34.65 seconds
Started	Mar 24 02:45:12 PM PDT 24
Finished	Mar 24 02:45:46 PM PDT 24
Peak memory	200176 kb
Host	smart-cb7b8a5e-edc2-497c-a41e-965de95db481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85407814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.85407814
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_intr.1859111623
Short name	T786
Test name
Test status
Simulation time	6831111506 ps
CPU time	11.67 seconds
Started	Mar 24 02:45:19 PM PDT 24
Finished	Mar 24 02:45:31 PM PDT 24
Peak memory	200064 kb
Host	smart-d757b928-3956-493d-9782-7df61e1bf66e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859111623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1859111623
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.2617761560
Short name	T408
Test name
Test status
Simulation time	106669703502 ps
CPU time	368.4 seconds
Started	Mar 24 02:45:18 PM PDT 24
Finished	Mar 24 02:51:27 PM PDT 24
Peak memory	200100 kb
Host	smart-e2f867c1-9508-44b2-b601-c50bb59efb68
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2617761560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2617761560
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_loopback.3718558559
Short name	T868
Test name
Test status
Simulation time	1872705748 ps
CPU time	10.85 seconds
Started	Mar 24 02:45:16 PM PDT 24
Finished	Mar 24 02:45:27 PM PDT 24
Peak memory	198728 kb
Host	smart-ddaad13d-62aa-4f99-a91d-cdf41e105789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718558559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3718558559
Directory	/workspace/38.uart_loopback/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.908664210
Short name	T304
Test name
Test status
Simulation time	19288783251 ps
CPU time	33.93 seconds
Started	Mar 24 02:45:18 PM PDT 24
Finished	Mar 24 02:45:52 PM PDT 24
Peak memory	198568 kb
Host	smart-a2e7ea5b-98a6-46d9-85c4-9ce0fc556129
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908664210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.908664210
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.324322045
Short name	T531
Test name
Test status
Simulation time	8647446384 ps
CPU time	124.39 seconds
Started	Mar 24 02:45:18 PM PDT 24
Finished	Mar 24 02:47:23 PM PDT 24
Peak memory	200140 kb
Host	smart-fa9fb542-58eb-4785-863d-d4f83dd191c8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=324322045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.324322045
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_oversample.158509516
Short name	T714
Test name
Test status
Simulation time	4491565988 ps
CPU time	8.75 seconds
Started	Mar 24 02:45:19 PM PDT 24
Finished	Mar 24 02:45:28 PM PDT 24
Peak memory	197556 kb
Host	smart-0378ad29-a057-4666-b10e-ba5226af16bd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=158509516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.158509516
Directory	/workspace/38.uart_rx_oversample/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.851995673
Short name	T143
Test name
Test status
Simulation time	112829069375 ps
CPU time	49.15 seconds
Started	Mar 24 02:45:19 PM PDT 24
Finished	Mar 24 02:46:08 PM PDT 24
Peak memory	200160 kb
Host	smart-b623b6cd-85d4-47a7-aa24-e271687eec7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851995673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.851995673
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.15913378
Short name	T863
Test name
Test status
Simulation time	30274933959 ps
CPU time	7.47 seconds
Started	Mar 24 02:45:20 PM PDT 24
Finished	Mar 24 02:45:28 PM PDT 24
Peak memory	196440 kb
Host	smart-8c56e6e1-191c-4603-b111-9d4cf0266145
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15913378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.15913378
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.2196735405
Short name	T289
Test name
Test status
Simulation time	271763513 ps
CPU time	1.52 seconds
Started	Mar 24 02:45:10 PM PDT 24
Finished	Mar 24 02:45:12 PM PDT 24
Peak memory	198872 kb
Host	smart-0202464d-87c3-4bcb-aa4f-a4d8392e3733
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196735405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2196735405
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.3586535881
Short name	T888
Test name
Test status
Simulation time	6392629360 ps
CPU time	1.77 seconds
Started	Mar 24 02:45:17 PM PDT 24
Finished	Mar 24 02:45:19 PM PDT 24
Peak memory	200016 kb
Host	smart-43e1e6e5-146b-403b-ba07-0e0707c7927a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586535881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3586535881
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.3808481675
Short name	T591
Test name
Test status
Simulation time	49167813998 ps
CPU time	21.13 seconds
Started	Mar 24 02:45:14 PM PDT 24
Finished	Mar 24 02:45:35 PM PDT 24
Peak memory	200116 kb
Host	smart-891b7486-eeb9-438c-a58b-3b1a048c15b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808481675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3808481675
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/default/39.uart_alert_test.4155227592
Short name	T414
Test name
Test status
Simulation time	11497380 ps
CPU time	0.58 seconds
Started	Mar 24 02:45:21 PM PDT 24
Finished	Mar 24 02:45:21 PM PDT 24
Peak memory	195628 kb
Host	smart-092361dc-a394-42da-9968-cc95a9e98f2c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155227592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4155227592
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.230877266
Short name	T769
Test name
Test status
Simulation time	105886364012 ps
CPU time	137.9 seconds
Started	Mar 24 02:45:21 PM PDT 24
Finished	Mar 24 02:47:39 PM PDT 24
Peak memory	200160 kb
Host	smart-e953056d-14e9-4348-8e1c-21d1fa04a744
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230877266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.230877266
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.3492269163
Short name	T9
Test name
Test status
Simulation time	52669015559 ps
CPU time	56.34 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:46:19 PM PDT 24
Peak memory	200176 kb
Host	smart-cde822cd-2c3d-4777-9edf-b404e3b9c384
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492269163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3492269163
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.3667742428
Short name	T1036
Test name
Test status
Simulation time	107346232686 ps
CPU time	38.57 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:46:02 PM PDT 24
Peak memory	200124 kb
Host	smart-9263ac15-43ab-4060-ab8f-ef73da5236b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667742428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3667742428
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.4128402883
Short name	T707
Test name
Test status
Simulation time	42260934343 ps
CPU time	38.5 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:46:01 PM PDT 24
Peak memory	199852 kb
Host	smart-93cb1b26-cf12-4570-8b0f-9f0f1520b8cb
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128402883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4128402883
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.3784252692
Short name	T926
Test name
Test status
Simulation time	87419640350 ps
CPU time	452.21 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:53:07 PM PDT 24
Peak memory	200148 kb
Host	smart-36b8c877-70d8-4abf-b42c-c8a064172a3f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3784252692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3784252692
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/39.uart_loopback.2655061034
Short name	T585
Test name
Test status
Simulation time	156487520 ps
CPU time	0.83 seconds
Started	Mar 24 02:45:24 PM PDT 24
Finished	Mar 24 02:45:24 PM PDT 24
Peak memory	196316 kb
Host	smart-958e120b-5c3a-4726-8474-22d5abe54eb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655061034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2655061034
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.14395630
Short name	T891
Test name
Test status
Simulation time	63309644720 ps
CPU time	33.79 seconds
Started	Mar 24 02:45:22 PM PDT 24
Finished	Mar 24 02:45:55 PM PDT 24
Peak memory	200016 kb
Host	smart-d1256aff-299a-4811-ad33-868816c190c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14395630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.14395630
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.2356064432
Short name	T840
Test name
Test status
Simulation time	19833349745 ps
CPU time	929.46 seconds
Started	Mar 24 02:45:21 PM PDT 24
Finished	Mar 24 03:00:51 PM PDT 24
Peak memory	200116 kb
Host	smart-5ce26c11-eee5-4f40-91a1-8c5a394f2a10
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2356064432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2356064432
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_oversample.1760335603
Short name	T952
Test name
Test status
Simulation time	7191473301 ps
CPU time	63.13 seconds
Started	Mar 24 02:45:25 PM PDT 24
Finished	Mar 24 02:46:28 PM PDT 24
Peak memory	198808 kb
Host	smart-425c8e46-7662-4a5e-a420-27ee6548e1db
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1760335603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1760335603
Directory	/workspace/39.uart_rx_oversample/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.952647846
Short name	T932
Test name
Test status
Simulation time	61950100966 ps
CPU time	138.32 seconds
Started	Mar 24 02:45:22 PM PDT 24
Finished	Mar 24 02:47:40 PM PDT 24
Peak memory	200120 kb
Host	smart-b92ebc1c-083f-45c6-a38e-dc798b1a8426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952647846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.952647846
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.296643242
Short name	T713
Test name
Test status
Simulation time	28843360068 ps
CPU time	7.73 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:45:43 PM PDT 24
Peak memory	196232 kb
Host	smart-cf4fca7b-a07f-495d-bdb7-e21590daabdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296643242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.296643242
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.3937822063
Short name	T454
Test name
Test status
Simulation time	295225013 ps
CPU time	1.09 seconds
Started	Mar 24 02:45:18 PM PDT 24
Finished	Mar 24 02:45:19 PM PDT 24
Peak memory	198468 kb
Host	smart-0ed7e4a7-8345-48ff-9023-0fe5a4c402c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937822063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3937822063
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all.773214382
Short name	T198
Test name
Test status
Simulation time	87549042755 ps
CPU time	139.49 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:47:43 PM PDT 24
Peak memory	200128 kb
Host	smart-4f468030-4ad4-4e6b-abde-cbdc91637d55
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773214382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.773214382
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.1344215373
Short name	T609
Test name
Test status
Simulation time	1353746066 ps
CPU time	1.62 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:45:25 PM PDT 24
Peak memory	199100 kb
Host	smart-0f8cbca8-fc2b-4aab-b614-14ca5e8d814e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344215373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1344215373
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.4122919864
Short name	T286
Test name
Test status
Simulation time	16972126852 ps
CPU time	25.75 seconds
Started	Mar 24 02:45:18 PM PDT 24
Finished	Mar 24 02:45:43 PM PDT 24
Peak memory	200160 kb
Host	smart-cf243dff-b563-42e6-bbe4-76e4fbf06fb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122919864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4122919864
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.2187267602
Short name	T524
Test name
Test status
Simulation time	11679770 ps
CPU time	0.59 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:43:31 PM PDT 24
Peak memory	195632 kb
Host	smart-8e7dc5fb-4c0d-458a-9b9e-ee69e5d3b03b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187267602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2187267602
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.1076344505
Short name	T939
Test name
Test status
Simulation time	116650874881 ps
CPU time	191.84 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:46:39 PM PDT 24
Peak memory	200104 kb
Host	smart-e1e50b0e-9967-41f6-8188-b7815465ea66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076344505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1076344505
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.1620084591
Short name	T475
Test name
Test status
Simulation time	124656839638 ps
CPU time	172.49 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:46:19 PM PDT 24
Peak memory	200168 kb
Host	smart-3ddb0ddd-9b5c-46b7-a0d3-93a2b8ba9d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1620084591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1620084591
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.3833910659
Short name	T329
Test name
Test status
Simulation time	62584159655 ps
CPU time	30.9 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	200040 kb
Host	smart-2f0827f5-d684-42eb-8fb3-f140ca02aa35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833910659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3833910659
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_intr.2844911846
Short name	T847
Test name
Test status
Simulation time	40884301051 ps
CPU time	16.77 seconds
Started	Mar 24 02:43:31 PM PDT 24
Finished	Mar 24 02:43:47 PM PDT 24
Peak memory	199384 kb
Host	smart-600742a1-00ef-4a7b-b7e6-bf01c2c1ddd0
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844911846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2844911846
Directory	/workspace/4.uart_intr/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.2609055118
Short name	T855
Test name
Test status
Simulation time	54760015152 ps
CPU time	87.88 seconds
Started	Mar 24 02:43:19 PM PDT 24
Finished	Mar 24 02:44:47 PM PDT 24
Peak memory	200056 kb
Host	smart-7114ab39-5933-4aaf-b27f-7e4c4b3d2aca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2609055118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2609055118
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.518642697
Short name	T527
Test name
Test status
Simulation time	4291455975 ps
CPU time	6.08 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:43:41 PM PDT 24
Peak memory	200124 kb
Host	smart-b418bd7b-288b-4e72-864b-744e9e6b9c8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518642697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.518642697
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.3760826061
Short name	T687
Test name
Test status
Simulation time	106236135672 ps
CPU time	241.14 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:47:27 PM PDT 24
Peak memory	208460 kb
Host	smart-943bdd01-6565-46f5-8b6c-dc36c567e8b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760826061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3760826061
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.890146881
Short name	T24
Test name
Test status
Simulation time	5753947676 ps
CPU time	289.12 seconds
Started	Mar 24 02:43:19 PM PDT 24
Finished	Mar 24 02:48:08 PM PDT 24
Peak memory	200072 kb
Host	smart-b65ac905-808f-44a4-80a9-f6e60f1865a0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=890146881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.890146881
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_oversample.4164586105
Short name	T749
Test name
Test status
Simulation time	2545288392 ps
CPU time	16.77 seconds
Started	Mar 24 02:43:17 PM PDT 24
Finished	Mar 24 02:43:35 PM PDT 24
Peak memory	199188 kb
Host	smart-caa1f9ac-be7e-4860-9bfd-909cc3448c2a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4164586105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4164586105
Directory	/workspace/4.uart_rx_oversample/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.863209586
Short name	T586
Test name
Test status
Simulation time	1897334433 ps
CPU time	2.2 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:25 PM PDT 24
Peak memory	195548 kb
Host	smart-dd73b6dc-d619-4af6-8f11-9b3c059cfee5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863209586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.863209586
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.2603106681
Short name	T34
Test name
Test status
Simulation time	188758020 ps
CPU time	0.93 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:43:25 PM PDT 24
Peak memory	218652 kb
Host	smart-321a0bd2-c422-4d24-bacb-3ebd1ff541a7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603106681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2603106681
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/4.uart_smoke.676480319
Short name	T2
Test name
Test status
Simulation time	122316171 ps
CPU time	1 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:43:25 PM PDT 24
Peak memory	197940 kb
Host	smart-8b2c1ce4-b0a6-4d67-ad91-947b49643a7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676480319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.676480319
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.853662102
Short name	T630
Test name
Test status
Simulation time	180068956719 ps
CPU time	378.18 seconds
Started	Mar 24 02:43:21 PM PDT 24
Finished	Mar 24 02:49:39 PM PDT 24
Peak memory	200556 kb
Host	smart-1dbed21c-dd02-45b5-8797-ded6b4420b6e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853662102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.853662102
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_stress_all_with_rand_reset.904471614
Short name	T358
Test name
Test status
Simulation time	348799291199 ps
CPU time	763.46 seconds
Started	Mar 24 02:43:15 PM PDT 24
Finished	Mar 24 02:56:01 PM PDT 24
Peak memory	216728 kb
Host	smart-442fc668-8bff-446d-93be-b396e219a261
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904471614 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.904471614
Directory	/workspace/4.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.2395034799
Short name	T822
Test name
Test status
Simulation time	4098426223 ps
CPU time	1.45 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:24 PM PDT 24
Peak memory	199776 kb
Host	smart-01447243-f941-4806-abc0-2a6607307a14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395034799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2395034799
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.2266253777
Short name	T904
Test name
Test status
Simulation time	14360290229 ps
CPU time	23.04 seconds
Started	Mar 24 02:43:17 PM PDT 24
Finished	Mar 24 02:43:41 PM PDT 24
Peak memory	200184 kb
Host	smart-fd9833a0-4940-423a-b112-a53b25a78e6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266253777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2266253777
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.583368432
Short name	T394
Test name
Test status
Simulation time	21144260 ps
CPU time	0.55 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:45:36 PM PDT 24
Peak memory	195636 kb
Host	smart-6991a902-5db9-4cdf-8fa7-91dbebb64982
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583368432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.583368432
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.4084066345
Short name	T1053
Test name
Test status
Simulation time	124242345604 ps
CPU time	136.1 seconds
Started	Mar 24 02:45:34 PM PDT 24
Finished	Mar 24 02:47:51 PM PDT 24
Peak memory	200156 kb
Host	smart-501ab55c-8491-4864-800d-c341b2f45a1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084066345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.4084066345
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.951878987
Short name	T987
Test name
Test status
Simulation time	106833861097 ps
CPU time	16.63 seconds
Started	Mar 24 02:45:34 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	200148 kb
Host	smart-709edc0f-08fc-4fae-8310-0f53fe1105af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951878987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.951878987
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.3654727287
Short name	T678
Test name
Test status
Simulation time	144658006730 ps
CPU time	38.61 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:46:01 PM PDT 24
Peak memory	200052 kb
Host	smart-65e9a2cd-c6c0-4152-b1a4-acbfabc06375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654727287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3654727287
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.1479324445
Short name	T990
Test name
Test status
Simulation time	34100145575 ps
CPU time	17.29 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:45:40 PM PDT 24
Peak memory	200036 kb
Host	smart-a19520ec-62f9-49d6-a252-de2da6700d5e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479324445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1479324445
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.269296326
Short name	T460
Test name
Test status
Simulation time	134408920864 ps
CPU time	166.7 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200020 kb
Host	smart-10890b59-cdc7-470f-9425-fbe2ccea6f6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=269296326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.269296326
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.2371208469
Short name	T970
Test name
Test status
Simulation time	1818262102 ps
CPU time	3.73 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:45:31 PM PDT 24
Peak memory	198640 kb
Host	smart-8e455e56-b18d-4374-9196-13881aab1790
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371208469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2371208469
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.1877864895
Short name	T294
Test name
Test status
Simulation time	44006718194 ps
CPU time	16.51 seconds
Started	Mar 24 02:45:34 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	199208 kb
Host	smart-5cdb6713-65e9-46ca-bb07-5a7c64d9147c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877864895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1877864895
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.3984448549
Short name	T84
Test name
Test status
Simulation time	14436862929 ps
CPU time	269 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:49:57 PM PDT 24
Peak memory	200160 kb
Host	smart-5e94a45a-b063-4173-a0e8-3231c2f28116
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3984448549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3984448549
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.1776528522
Short name	T592
Test name
Test status
Simulation time	6463475829 ps
CPU time	64.4 seconds
Started	Mar 24 02:45:22 PM PDT 24
Finished	Mar 24 02:46:27 PM PDT 24
Peak memory	199436 kb
Host	smart-8a303305-bf81-45fe-8785-6418e5c8cf5e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1776528522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1776528522
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.4087788513
Short name	T147
Test name
Test status
Simulation time	28168846507 ps
CPU time	47.74 seconds
Started	Mar 24 02:45:29 PM PDT 24
Finished	Mar 24 02:46:17 PM PDT 24
Peak memory	200120 kb
Host	smart-c437dc3e-18be-48db-ad0a-1ff14b6c1bf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087788513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4087788513
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.2333089913
Short name	T824
Test name
Test status
Simulation time	729262110 ps
CPU time	1.79 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:45:37 PM PDT 24
Peak memory	195820 kb
Host	smart-457b9faf-ce50-4c8b-8bfd-013332987970
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333089913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2333089913
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.3012714784
Short name	T324
Test name
Test status
Simulation time	267665796 ps
CPU time	1.63 seconds
Started	Mar 24 02:45:23 PM PDT 24
Finished	Mar 24 02:45:25 PM PDT 24
Peak memory	198360 kb
Host	smart-671ba8c4-7c54-464d-a447-db509534e565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012714784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3012714784
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.3678831370
Short name	T195
Test name
Test status
Simulation time	208595812732 ps
CPU time	91.35 seconds
Started	Mar 24 02:45:26 PM PDT 24
Finished	Mar 24 02:46:58 PM PDT 24
Peak memory	200072 kb
Host	smart-4f2b59e7-f6dd-4220-bdfb-aa9c69af6f4e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678831370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3678831370
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.385678811
Short name	T430
Test name
Test status
Simulation time	6591203299 ps
CPU time	12.58 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:45:40 PM PDT 24
Peak memory	199520 kb
Host	smart-deb339fb-e409-4ac2-ab74-373ec87c61d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385678811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.385678811
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.359783475
Short name	T326
Test name
Test status
Simulation time	25102964423 ps
CPU time	10.26 seconds
Started	Mar 24 02:45:22 PM PDT 24
Finished	Mar 24 02:45:33 PM PDT 24
Peak memory	199920 kb
Host	smart-0b904c79-1bb6-4b39-b4a6-571eb665a064
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359783475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.359783475
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.2880047424
Short name	T950
Test name
Test status
Simulation time	16943052 ps
CPU time	0.54 seconds
Started	Mar 24 02:45:34 PM PDT 24
Finished	Mar 24 02:45:35 PM PDT 24
Peak memory	195596 kb
Host	smart-b4cd07d0-e42a-40a3-b5a9-2fe03f4b5934
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880047424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2880047424
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.568729861
Short name	T1095
Test name
Test status
Simulation time	136845051018 ps
CPU time	81.41 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:46:49 PM PDT 24
Peak memory	200140 kb
Host	smart-86277255-4802-4029-8e4d-25077cacecd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568729861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.568729861
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.1009096092
Short name	T181
Test name
Test status
Simulation time	18483635030 ps
CPU time	16.49 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:45:44 PM PDT 24
Peak memory	200104 kb
Host	smart-4ccf6f19-3e3d-4719-83ae-28abbda166c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009096092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1009096092
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.1997209614
Short name	T1109
Test name
Test status
Simulation time	170536766934 ps
CPU time	112.97 seconds
Started	Mar 24 02:45:26 PM PDT 24
Finished	Mar 24 02:47:19 PM PDT 24
Peak memory	200164 kb
Host	smart-caff6fe7-57e0-4390-821d-dce05b32e5c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997209614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1997209614
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/41.uart_intr.1787844692
Short name	T555
Test name
Test status
Simulation time	44188228011 ps
CPU time	78.61 seconds
Started	Mar 24 02:45:29 PM PDT 24
Finished	Mar 24 02:46:48 PM PDT 24
Peak memory	200148 kb
Host	smart-4561e8ea-8faa-4856-8534-fca7d3f12a0e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787844692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1787844692
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_long_xfer_wo_dly.2217390880
Short name	T607
Test name
Test status
Simulation time	37675983118 ps
CPU time	175.58 seconds
Started	Mar 24 02:45:28 PM PDT 24
Finished	Mar 24 02:48:25 PM PDT 24
Peak memory	200184 kb
Host	smart-cace6f94-46c3-41f4-9bee-ddb21f2122cf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2217390880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2217390880
Directory	/workspace/41.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/41.uart_loopback.2571443263
Short name	T393
Test name
Test status
Simulation time	5199546665 ps
CPU time	6.79 seconds
Started	Mar 24 02:45:29 PM PDT 24
Finished	Mar 24 02:45:36 PM PDT 24
Peak memory	199620 kb
Host	smart-041e8d67-a789-43bd-8692-3da93860a8a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571443263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2571443263
Directory	/workspace/41.uart_loopback/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.1510861925
Short name	T1014
Test name
Test status
Simulation time	77398905467 ps
CPU time	188.62 seconds
Started	Mar 24 02:45:29 PM PDT 24
Finished	Mar 24 02:48:38 PM PDT 24
Peak memory	200228 kb
Host	smart-364d5722-f93e-4dea-a072-81c1f7b40d5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510861925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1510861925
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.2089732893
Short name	T851
Test name
Test status
Simulation time	17798196889 ps
CPU time	965.01 seconds
Started	Mar 24 02:45:29 PM PDT 24
Finished	Mar 24 03:01:35 PM PDT 24
Peak memory	200092 kb
Host	smart-d3ba2fd6-635f-443b-a73e-0aafbddd4ca3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2089732893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2089732893
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.3644722475
Short name	T1042
Test name
Test status
Simulation time	1277869991 ps
CPU time	3.39 seconds
Started	Mar 24 02:45:28 PM PDT 24
Finished	Mar 24 02:45:32 PM PDT 24
Peak memory	198328 kb
Host	smart-b2a0692a-19d7-4805-98d7-abe57dea5234
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3644722475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3644722475
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.2758411557
Short name	T601
Test name
Test status
Simulation time	5011258581 ps
CPU time	9.19 seconds
Started	Mar 24 02:45:28 PM PDT 24
Finished	Mar 24 02:45:38 PM PDT 24
Peak memory	200068 kb
Host	smart-4a67a422-8e4f-43c8-919d-b786b7c75bb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758411557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2758411557
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.2805151022
Short name	T1083
Test name
Test status
Simulation time	45510140384 ps
CPU time	19.32 seconds
Started	Mar 24 02:45:28 PM PDT 24
Finished	Mar 24 02:45:48 PM PDT 24
Peak memory	195964 kb
Host	smart-5ac980cd-22a5-4845-bc96-1d1782b969e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805151022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2805151022
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.1682683922
Short name	T785
Test name
Test status
Simulation time	881964649 ps
CPU time	3.29 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:45:30 PM PDT 24
Peak memory	199948 kb
Host	smart-c195cd31-1274-4339-99b9-41468e8f88b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682683922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1682683922
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.4289537570
Short name	T1013
Test name
Test status
Simulation time	120518708702 ps
CPU time	103.16 seconds
Started	Mar 24 02:45:33 PM PDT 24
Finished	Mar 24 02:47:16 PM PDT 24
Peak memory	200208 kb
Host	smart-4414e81a-15b7-4520-bffa-585f727e0c30
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289537570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4289537570
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_stress_all_with_rand_reset.2497726364
Short name	T113
Test name
Test status
Simulation time	73494330122 ps
CPU time	717.69 seconds
Started	Mar 24 02:45:33 PM PDT 24
Finished	Mar 24 02:57:31 PM PDT 24
Peak memory	225000 kb
Host	smart-c1ddaf10-7341-4aff-8fdc-1291110f64e4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497726364 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2497726364
Directory	/workspace/41.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.2544882548
Short name	T1091
Test name
Test status
Simulation time	7192994957 ps
CPU time	11.42 seconds
Started	Mar 24 02:45:27 PM PDT 24
Finished	Mar 24 02:45:39 PM PDT 24
Peak memory	200020 kb
Host	smart-8a994d56-ffb6-41eb-a1d8-f7cc0c956544
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544882548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2544882548
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.3834304607
Short name	T666
Test name
Test status
Simulation time	53084350967 ps
CPU time	16.02 seconds
Started	Mar 24 02:45:30 PM PDT 24
Finished	Mar 24 02:45:46 PM PDT 24
Peak memory	200136 kb
Host	smart-38a6beb4-10f4-4775-a7f1-6d42d02b931d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834304607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3834304607
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.2432481340
Short name	T700
Test name
Test status
Simulation time	53813161 ps
CPU time	0.56 seconds
Started	Mar 24 02:45:32 PM PDT 24
Finished	Mar 24 02:45:32 PM PDT 24
Peak memory	195588 kb
Host	smart-571a1c03-27b7-4694-8ba7-404e0be638be
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432481340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2432481340
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.4226073006
Short name	T322
Test name
Test status
Simulation time	120484691945 ps
CPU time	249.21 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:49:45 PM PDT 24
Peak memory	200124 kb
Host	smart-b56544cf-9ff8-445b-b33e-ac7c94635cda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226073006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4226073006
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.1410775422
Short name	T136
Test name
Test status
Simulation time	94016722404 ps
CPU time	157.22 seconds
Started	Mar 24 02:45:36 PM PDT 24
Finished	Mar 24 02:48:14 PM PDT 24
Peak memory	200120 kb
Host	smart-2a88174d-340c-416e-9bac-30418680799e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410775422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1410775422
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/42.uart_intr.2265019594
Short name	T1075
Test name
Test status
Simulation time	10373839425 ps
CPU time	16.33 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	196936 kb
Host	smart-2ff297b9-01fb-4dd0-a470-1739a42433ab
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265019594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2265019594
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.3030105540
Short name	T781
Test name
Test status
Simulation time	151708413664 ps
CPU time	353.91 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:51:29 PM PDT 24
Peak memory	200144 kb
Host	smart-eb95d1a7-f58a-417a-a3f6-192b9d966d83
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3030105540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3030105540
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.2446575234
Short name	T10
Test name
Test status
Simulation time	10819624718 ps
CPU time	17.66 seconds
Started	Mar 24 02:45:33 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	198720 kb
Host	smart-f3511c9f-2e7f-410a-a5c4-f954dcf36199
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446575234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2446575234
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.3234697488
Short name	T1081
Test name
Test status
Simulation time	19575802813 ps
CPU time	15.25 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	200144 kb
Host	smart-3a091534-0ea4-46cb-8f98-e41a2bce9c09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234697488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3234697488
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_perf.2731626540
Short name	T298
Test name
Test status
Simulation time	23285223410 ps
CPU time	170.33 seconds
Started	Mar 24 02:45:35 PM PDT 24
Finished	Mar 24 02:48:26 PM PDT 24
Peak memory	200364 kb
Host	smart-7d6cf738-7b2c-4239-be99-0cc3ce168776
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2731626540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2731626540
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.2191437003
Short name	T1004
Test name
Test status
Simulation time	3531978766 ps
CPU time	6.91 seconds
Started	Mar 24 02:45:34 PM PDT 24
Finished	Mar 24 02:45:41 PM PDT 24
Peak memory	198432 kb
Host	smart-9e726e0a-ab70-4303-b768-f0f4cbcdd4ba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2191437003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2191437003
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.727285652
Short name	T917
Test name
Test status
Simulation time	36680170645 ps
CPU time	35.04 seconds
Started	Mar 24 02:45:33 PM PDT 24
Finished	Mar 24 02:46:09 PM PDT 24
Peak memory	200176 kb
Host	smart-570dcebc-2baf-44d0-9c38-c6b9e543ec64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727285652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.727285652
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.4142987400
Short name	T452
Test name
Test status
Simulation time	6241323604 ps
CPU time	5.21 seconds
Started	Mar 24 02:45:32 PM PDT 24
Finished	Mar 24 02:45:37 PM PDT 24
Peak memory	196176 kb
Host	smart-eed6f1f0-2b07-451e-8f55-401ed49099d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142987400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4142987400
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.375691585
Short name	T1117
Test name
Test status
Simulation time	721957657 ps
CPU time	1.44 seconds
Started	Mar 24 02:45:36 PM PDT 24
Finished	Mar 24 02:45:38 PM PDT 24
Peak memory	198764 kb
Host	smart-f89f918f-0d5f-4800-ab85-562f9e7947a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375691585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.375691585
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_stress_all.4124854321
Short name	T119
Test name
Test status
Simulation time	319040722704 ps
CPU time	323.29 seconds
Started	Mar 24 02:45:36 PM PDT 24
Finished	Mar 24 02:50:59 PM PDT 24
Peak memory	216024 kb
Host	smart-cbabd2a3-8427-4276-ba8f-4cee18a08bd6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124854321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.4124854321
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.2703939975
Short name	T594
Test name
Test status
Simulation time	1148049189 ps
CPU time	1.88 seconds
Started	Mar 24 02:45:32 PM PDT 24
Finished	Mar 24 02:45:34 PM PDT 24
Peak memory	198104 kb
Host	smart-0ffa1617-38a1-4cd6-8af4-458aa8d2af69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703939975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2703939975
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.2695242459
Short name	T61
Test name
Test status
Simulation time	34362179714 ps
CPU time	12.77 seconds
Started	Mar 24 02:45:33 PM PDT 24
Finished	Mar 24 02:45:46 PM PDT 24
Peak memory	198396 kb
Host	smart-908b88d5-e9ea-4241-bbc5-8b6ce8c70ea1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695242459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2695242459
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.584362452
Short name	T651
Test name
Test status
Simulation time	11640935 ps
CPU time	0.56 seconds
Started	Mar 24 02:45:41 PM PDT 24
Finished	Mar 24 02:45:42 PM PDT 24
Peak memory	194976 kb
Host	smart-0651af6c-8c4f-424d-bbd8-c2fe225843e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584362452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.584362452
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.1323138842
Short name	T133
Test name
Test status
Simulation time	86100861125 ps
CPU time	72.2 seconds
Started	Mar 24 02:45:36 PM PDT 24
Finished	Mar 24 02:46:49 PM PDT 24
Peak memory	200152 kb
Host	smart-031acb64-a7e7-418a-9047-f3e45eda52ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323138842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1323138842
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.3507254663
Short name	T497
Test name
Test status
Simulation time	40745531331 ps
CPU time	22.49 seconds
Started	Mar 24 02:45:37 PM PDT 24
Finished	Mar 24 02:45:59 PM PDT 24
Peak memory	200136 kb
Host	smart-06fbf62d-1a4f-40d7-b2e8-f634b183f640
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507254663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3507254663
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.3152857383
Short name	T123
Test name
Test status
Simulation time	51842742678 ps
CPU time	40.4 seconds
Started	Mar 24 02:45:37 PM PDT 24
Finished	Mar 24 02:46:18 PM PDT 24
Peak memory	200132 kb
Host	smart-1ec56d03-e0ef-4e49-b919-1bd6b5be1fcd
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152857383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3152857383
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.4056296649
Short name	T280
Test name
Test status
Simulation time	112650179754 ps
CPU time	341.85 seconds
Started	Mar 24 02:45:42 PM PDT 24
Finished	Mar 24 02:51:24 PM PDT 24
Peak memory	200160 kb
Host	smart-f481417b-287b-4012-b3b3-5a7aac62f8a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4056296649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4056296649
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_loopback.3177173139
Short name	T682
Test name
Test status
Simulation time	5553094523 ps
CPU time	3.14 seconds
Started	Mar 24 02:45:39 PM PDT 24
Finished	Mar 24 02:45:43 PM PDT 24
Peak memory	197896 kb
Host	smart-92eaad50-371d-41de-9c50-162ae6ad22c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177173139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3177173139
Directory	/workspace/43.uart_loopback/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.1426891024
Short name	T1056
Test name
Test status
Simulation time	24846002462 ps
CPU time	38.01 seconds
Started	Mar 24 02:45:39 PM PDT 24
Finished	Mar 24 02:46:18 PM PDT 24
Peak memory	200292 kb
Host	smart-7174867c-e04e-46bc-9441-ede5a7221cb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426891024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1426891024
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.506605265
Short name	T489
Test name
Test status
Simulation time	16076860988 ps
CPU time	219.48 seconds
Started	Mar 24 02:45:38 PM PDT 24
Finished	Mar 24 02:49:19 PM PDT 24
Peak memory	200104 kb
Host	smart-9abbd578-5843-45da-aac0-93f1a17ace3b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=506605265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.506605265
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.1609775277
Short name	T381
Test name
Test status
Simulation time	7829763380 ps
CPU time	63.36 seconds
Started	Mar 24 02:45:38 PM PDT 24
Finished	Mar 24 02:46:41 PM PDT 24
Peak memory	198436 kb
Host	smart-8615b7e3-0b7f-4e60-9894-a38523872a98
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1609775277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1609775277
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.272071176
Short name	T621
Test name
Test status
Simulation time	38989287043 ps
CPU time	27.65 seconds
Started	Mar 24 02:45:37 PM PDT 24
Finished	Mar 24 02:46:05 PM PDT 24
Peak memory	200188 kb
Host	smart-ce74d14a-d1ce-4fde-a175-303d898736cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272071176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.272071176
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.3315571242
Short name	T297
Test name
Test status
Simulation time	75896359586 ps
CPU time	17.92 seconds
Started	Mar 24 02:45:37 PM PDT 24
Finished	Mar 24 02:45:55 PM PDT 24
Peak memory	196172 kb
Host	smart-c64863aa-2033-48ee-8e83-7a14ea512cec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315571242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3315571242
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.2423392401
Short name	T573
Test name
Test status
Simulation time	518013145 ps
CPU time	1.34 seconds
Started	Mar 24 02:45:38 PM PDT 24
Finished	Mar 24 02:45:40 PM PDT 24
Peak memory	198316 kb
Host	smart-e2f0357f-1087-4c67-ba8d-8b1598a56579
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423392401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2423392401
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_stress_all.3352511479
Short name	T857
Test name
Test status
Simulation time	144530263797 ps
CPU time	293.8 seconds
Started	Mar 24 02:45:42 PM PDT 24
Finished	Mar 24 02:50:36 PM PDT 24
Peak memory	200092 kb
Host	smart-794d362f-5049-4a59-8b53-7929d92719f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352511479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3352511479
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_stress_all_with_rand_reset.1685833939
Short name	T65
Test name
Test status
Simulation time	248513212102 ps
CPU time	691.39 seconds
Started	Mar 24 02:45:40 PM PDT 24
Finished	Mar 24 02:57:11 PM PDT 24
Peak memory	226804 kb
Host	smart-4af5222c-f3cd-4920-ab03-bbd963750b79
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685833939 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1685833939
Directory	/workspace/43.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.3272283796
Short name	T991
Test name
Test status
Simulation time	1291076046 ps
CPU time	2.59 seconds
Started	Mar 24 02:45:40 PM PDT 24
Finished	Mar 24 02:45:43 PM PDT 24
Peak memory	198896 kb
Host	smart-982d2b17-c1f0-4520-bcd5-251878b9d627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272283796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3272283796
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/43.uart_tx_rx.2662081482
Short name	T810
Test name
Test status
Simulation time	205160504518 ps
CPU time	282.04 seconds
Started	Mar 24 02:45:44 PM PDT 24
Finished	Mar 24 02:50:26 PM PDT 24
Peak memory	200088 kb
Host	smart-6b02af7e-d3c2-4fb2-97a4-37dc895eff3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662081482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2662081482
Directory	/workspace/43.uart_tx_rx/latest

Test location	/workspace/coverage/default/44.uart_alert_test.3950518858
Short name	T486
Test name
Test status
Simulation time	28989696 ps
CPU time	0.58 seconds
Started	Mar 24 02:45:41 PM PDT 24
Finished	Mar 24 02:45:42 PM PDT 24
Peak memory	195632 kb
Host	smart-289c576d-54b3-4979-9f76-3794a7ebd0e5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950518858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3950518858
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.1067324536
Short name	T757
Test name
Test status
Simulation time	103708673839 ps
CPU time	61.08 seconds
Started	Mar 24 02:45:38 PM PDT 24
Finished	Mar 24 02:46:39 PM PDT 24
Peak memory	200152 kb
Host	smart-a4c0955b-8f55-4650-bd6b-c10f74b8c92f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067324536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1067324536
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.2896727419
Short name	T871
Test name
Test status
Simulation time	39286293476 ps
CPU time	16.39 seconds
Started	Mar 24 02:45:39 PM PDT 24
Finished	Mar 24 02:45:56 PM PDT 24
Peak memory	198684 kb
Host	smart-d35ec03c-531d-49c6-af01-c9fbb342b365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896727419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2896727419
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.807325024
Short name	T565
Test name
Test status
Simulation time	122670343872 ps
CPU time	51.97 seconds
Started	Mar 24 02:45:37 PM PDT 24
Finished	Mar 24 02:46:30 PM PDT 24
Peak memory	200188 kb
Host	smart-ae8554a1-1c75-41e1-b66e-d4356388a01c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807325024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.807325024
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.411392877
Short name	T493
Test name
Test status
Simulation time	29444432119 ps
CPU time	32.15 seconds
Started	Mar 24 02:45:43 PM PDT 24
Finished	Mar 24 02:46:16 PM PDT 24
Peak memory	200124 kb
Host	smart-521b0937-c05e-4625-925b-a80f8db27967
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411392877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.411392877
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.890972838
Short name	T937
Test name
Test status
Simulation time	120100709366 ps
CPU time	309.14 seconds
Started	Mar 24 02:45:44 PM PDT 24
Finished	Mar 24 02:50:54 PM PDT 24
Peak memory	200092 kb
Host	smart-d379d5ec-7f4b-41f2-b20c-700841cbc268
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=890972838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.890972838
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_loopback.3930488722
Short name	T773
Test name
Test status
Simulation time	5590830388 ps
CPU time	11.82 seconds
Started	Mar 24 02:45:43 PM PDT 24
Finished	Mar 24 02:45:55 PM PDT 24
Peak memory	200032 kb
Host	smart-0f0dd286-c036-4162-8d27-0891ac11a486
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930488722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3930488722
Directory	/workspace/44.uart_loopback/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.950176729
Short name	T419
Test name
Test status
Simulation time	55065768749 ps
CPU time	93.53 seconds
Started	Mar 24 02:45:43 PM PDT 24
Finished	Mar 24 02:47:18 PM PDT 24
Peak memory	199960 kb
Host	smart-d57f2980-d8e8-438e-a273-e4db6565842b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950176729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.950176729
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.631576308
Short name	T779
Test name
Test status
Simulation time	18161970727 ps
CPU time	120.58 seconds
Started	Mar 24 02:45:43 PM PDT 24
Finished	Mar 24 02:47:45 PM PDT 24
Peak memory	200160 kb
Host	smart-1a6edb9b-0bf3-4ceb-9a59-6c278e477cf8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=631576308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.631576308
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.1301076542
Short name	T382
Test name
Test status
Simulation time	5038796719 ps
CPU time	46.69 seconds
Started	Mar 24 02:45:44 PM PDT 24
Finished	Mar 24 02:46:31 PM PDT 24
Peak memory	198304 kb
Host	smart-7f05b236-95ba-4f32-b6c6-8d76be968ac0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1301076542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1301076542
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.2397408658
Short name	T661
Test name
Test status
Simulation time	125992360329 ps
CPU time	259.37 seconds
Started	Mar 24 02:45:42 PM PDT 24
Finished	Mar 24 02:50:02 PM PDT 24
Peak memory	200164 kb
Host	smart-cc4a7131-adbb-4dbe-b261-caf8c1df0f4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397408658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2397408658
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.1779279579
Short name	T712
Test name
Test status
Simulation time	40325745554 ps
CPU time	67.87 seconds
Started	Mar 24 02:45:43 PM PDT 24
Finished	Mar 24 02:46:52 PM PDT 24
Peak memory	196528 kb
Host	smart-80a26368-9042-4a73-b3c9-9e5e9adb1698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1779279579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1779279579
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.2679143180
Short name	T395
Test name
Test status
Simulation time	6293381031 ps
CPU time	7.86 seconds
Started	Mar 24 02:45:39 PM PDT 24
Finished	Mar 24 02:45:48 PM PDT 24
Peak memory	199536 kb
Host	smart-34b945a6-665a-4da4-a362-6643f9f0a001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679143180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2679143180
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_stress_all.611029857
Short name	T999
Test name
Test status
Simulation time	242936090491 ps
CPU time	99.29 seconds
Started	Mar 24 02:45:43 PM PDT 24
Finished	Mar 24 02:47:22 PM PDT 24
Peak memory	200128 kb
Host	smart-576af2a1-1b1b-4300-9f36-6ba12e6bd160
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611029857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.611029857
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.2511078994
Short name	T823
Test name
Test status
Simulation time	915267375 ps
CPU time	2.54 seconds
Started	Mar 24 02:45:42 PM PDT 24
Finished	Mar 24 02:45:45 PM PDT 24
Peak memory	198956 kb
Host	smart-cadadc4d-be95-47ef-bf7e-b8d3ccb41e22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511078994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2511078994
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.4257785052
Short name	T927
Test name
Test status
Simulation time	381889351 ps
CPU time	1.12 seconds
Started	Mar 24 02:45:41 PM PDT 24
Finished	Mar 24 02:45:42 PM PDT 24
Peak memory	197472 kb
Host	smart-1430b7dd-1af1-4c72-835e-d3c4119e3fe7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257785052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4257785052
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.211195358
Short name	T32
Test name
Test status
Simulation time	32207608 ps
CPU time	0.56 seconds
Started	Mar 24 02:45:50 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	195608 kb
Host	smart-5d3ac286-db5d-4946-ba89-086e7f7f7d13
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211195358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.211195358
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.3180612522
Short name	T349
Test name
Test status
Simulation time	69577934433 ps
CPU time	129.2 seconds
Started	Mar 24 02:45:44 PM PDT 24
Finished	Mar 24 02:47:53 PM PDT 24
Peak memory	200140 kb
Host	smart-cd7c670c-840e-413b-bb08-3158478fb2cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180612522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3180612522
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.3799862225
Short name	T919
Test name
Test status
Simulation time	89932990831 ps
CPU time	43.07 seconds
Started	Mar 24 02:45:44 PM PDT 24
Finished	Mar 24 02:46:27 PM PDT 24
Peak memory	200184 kb
Host	smart-d1a03cca-e39a-4fa4-855a-60b8d7f35b24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799862225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3799862225
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.2968921053
Short name	T765
Test name
Test status
Simulation time	79024439183 ps
CPU time	15.5 seconds
Started	Mar 24 02:45:43 PM PDT 24
Finished	Mar 24 02:45:58 PM PDT 24
Peak memory	200156 kb
Host	smart-8ef8ac05-0391-40dd-8b25-fa8d7f53a290
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968921053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2968921053
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/45.uart_intr.1304240028
Short name	T124
Test name
Test status
Simulation time	62046086739 ps
CPU time	104.26 seconds
Started	Mar 24 02:45:50 PM PDT 24
Finished	Mar 24 02:47:34 PM PDT 24
Peak memory	200060 kb
Host	smart-63010f0d-db7a-461a-8075-7df479695816
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304240028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1304240028
Directory	/workspace/45.uart_intr/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.3756092097
Short name	T46
Test name
Test status
Simulation time	248470605701 ps
CPU time	214.46 seconds
Started	Mar 24 02:45:51 PM PDT 24
Finished	Mar 24 02:49:26 PM PDT 24
Peak memory	200016 kb
Host	smart-843619f0-5d96-497a-8735-b704d61344c8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3756092097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3756092097
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.3026307892
Short name	T1051
Test name
Test status
Simulation time	175645071 ps
CPU time	0.76 seconds
Started	Mar 24 02:45:50 PM PDT 24
Finished	Mar 24 02:45:51 PM PDT 24
Peak memory	196136 kb
Host	smart-0a7dad5d-444f-4ea4-9a49-c9a8bbd785ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026307892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3026307892
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.1733173036
Short name	T365
Test name
Test status
Simulation time	128231663571 ps
CPU time	55.09 seconds
Started	Mar 24 02:45:52 PM PDT 24
Finished	Mar 24 02:46:48 PM PDT 24
Peak memory	200312 kb
Host	smart-c01744f1-7735-47f0-b80f-def51cc86508
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733173036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1733173036
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.1974354807
Short name	T576
Test name
Test status
Simulation time	15058569257 ps
CPU time	101.06 seconds
Started	Mar 24 02:45:49 PM PDT 24
Finished	Mar 24 02:47:31 PM PDT 24
Peak memory	200192 kb
Host	smart-b1cd2496-cde5-4881-813b-eccaf141e2ad
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1974354807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1974354807
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_oversample.2521220239
Short name	T428
Test name
Test status
Simulation time	1839493597 ps
CPU time	2.06 seconds
Started	Mar 24 02:45:51 PM PDT 24
Finished	Mar 24 02:45:53 PM PDT 24
Peak memory	197712 kb
Host	smart-0d6ca7f9-a04b-40e4-9fd7-ffdd38f0998f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2521220239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2521220239
Directory	/workspace/45.uart_rx_oversample/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.2298171953
Short name	T942
Test name
Test status
Simulation time	18018640348 ps
CPU time	34.67 seconds
Started	Mar 24 02:45:50 PM PDT 24
Finished	Mar 24 02:46:25 PM PDT 24
Peak memory	200092 kb
Host	smart-5bc770a7-3b76-4711-9c69-509bb251e0a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298171953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2298171953
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.2407234042
Short name	T731
Test name
Test status
Simulation time	2643000940 ps
CPU time	2.77 seconds
Started	Mar 24 02:45:51 PM PDT 24
Finished	Mar 24 02:45:54 PM PDT 24
Peak memory	195932 kb
Host	smart-a26a852b-774b-44ca-91a8-77e48088bbda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407234042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2407234042
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.1865939683
Short name	T63
Test name
Test status
Simulation time	707492920 ps
CPU time	1.51 seconds
Started	Mar 24 02:45:42 PM PDT 24
Finished	Mar 24 02:45:43 PM PDT 24
Peak memory	198368 kb
Host	smart-1fda9eea-4133-4a76-bbf7-67e8e0667baf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865939683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1865939683
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.2497849271
Short name	T721
Test name
Test status
Simulation time	7287537766 ps
CPU time	11.68 seconds
Started	Mar 24 02:45:50 PM PDT 24
Finished	Mar 24 02:46:01 PM PDT 24
Peak memory	199392 kb
Host	smart-74427a90-6668-433b-b296-df988fac4009
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497849271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2497849271
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.897740165
Short name	T266
Test name
Test status
Simulation time	48638794489 ps
CPU time	83.48 seconds
Started	Mar 24 02:45:42 PM PDT 24
Finished	Mar 24 02:47:06 PM PDT 24
Peak memory	200120 kb
Host	smart-4708a768-0537-4ebf-962b-8c67d6a751aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897740165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.897740165
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.3701968743
Short name	T858
Test name
Test status
Simulation time	19781851 ps
CPU time	0.56 seconds
Started	Mar 24 02:45:55 PM PDT 24
Finished	Mar 24 02:45:57 PM PDT 24
Peak memory	195628 kb
Host	smart-020c1a35-91df-4c8f-b698-29d977cd18fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701968743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3701968743
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.231587649
Short name	T1085
Test name
Test status
Simulation time	219155346846 ps
CPU time	179.56 seconds
Started	Mar 24 02:45:55 PM PDT 24
Finished	Mar 24 02:48:56 PM PDT 24
Peak memory	200108 kb
Host	smart-d7ed6e18-9eb0-4dd7-82c1-a21e15bdb2ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231587649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.231587649
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.3072701790
Short name	T574
Test name
Test status
Simulation time	129616098643 ps
CPU time	51.07 seconds
Started	Mar 24 02:45:57 PM PDT 24
Finished	Mar 24 02:46:49 PM PDT 24
Peak memory	199988 kb
Host	smart-7dc5494a-7208-446e-9e8e-e12e57be4e66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072701790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3072701790
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.679309378
Short name	T192
Test name
Test status
Simulation time	56156565188 ps
CPU time	87.55 seconds
Started	Mar 24 02:45:56 PM PDT 24
Finished	Mar 24 02:47:24 PM PDT 24
Peak memory	200112 kb
Host	smart-092c5f8a-05e6-4542-9837-c3c2727e286a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679309378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.679309378
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/default/46.uart_intr.3309238390
Short name	T344
Test name
Test status
Simulation time	22142613894 ps
CPU time	36.76 seconds
Started	Mar 24 02:45:55 PM PDT 24
Finished	Mar 24 02:46:33 PM PDT 24
Peak memory	199920 kb
Host	smart-a5a629cf-c761-4c5b-8f20-8b952fc50b15
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309238390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3309238390
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.2449575900
Short name	T605
Test name
Test status
Simulation time	288781640403 ps
CPU time	239.75 seconds
Started	Mar 24 02:45:58 PM PDT 24
Finished	Mar 24 02:49:58 PM PDT 24
Peak memory	200096 kb
Host	smart-abae93e2-0f28-4bb2-a52e-dd9fd59c95c6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2449575900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2449575900
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.1824449228
Short name	T895
Test name
Test status
Simulation time	11193571493 ps
CPU time	8.89 seconds
Started	Mar 24 02:45:55 PM PDT 24
Finished	Mar 24 02:46:07 PM PDT 24
Peak memory	200080 kb
Host	smart-76cc614f-8915-4777-b3be-d889e723a0f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824449228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1824449228
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.2249431101
Short name	T918
Test name
Test status
Simulation time	24486079087 ps
CPU time	10.59 seconds
Started	Mar 24 02:45:58 PM PDT 24
Finished	Mar 24 02:46:08 PM PDT 24
Peak memory	198076 kb
Host	smart-762ce672-47a1-4cab-9211-17d13a9bab52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249431101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2249431101
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.3728805069
Short name	T959
Test name
Test status
Simulation time	28410462750 ps
CPU time	1161.17 seconds
Started	Mar 24 02:45:55 PM PDT 24
Finished	Mar 24 03:05:18 PM PDT 24
Peak memory	200132 kb
Host	smart-50efdabc-cfd4-416b-bbea-9d7f71dbd07e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3728805069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3728805069
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.2976793711
Short name	T79
Test name
Test status
Simulation time	3288236982 ps
CPU time	5.54 seconds
Started	Mar 24 02:45:58 PM PDT 24
Finished	Mar 24 02:46:05 PM PDT 24
Peak memory	198108 kb
Host	smart-5e0f76c4-97d6-4578-85ec-d3cd8dc2c888
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2976793711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2976793711
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.1258699352
Short name	T44
Test name
Test status
Simulation time	53637026874 ps
CPU time	13.58 seconds
Started	Mar 24 02:45:54 PM PDT 24
Finished	Mar 24 02:46:10 PM PDT 24
Peak memory	200160 kb
Host	smart-ce98d661-e318-41ee-9a7a-12e90191b8e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258699352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1258699352
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.3404570406
Short name	T875
Test name
Test status
Simulation time	72674061030 ps
CPU time	60.23 seconds
Started	Mar 24 02:45:57 PM PDT 24
Finished	Mar 24 02:46:58 PM PDT 24
Peak memory	196216 kb
Host	smart-61e65d05-1d3d-41f9-b719-1363004009de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404570406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3404570406
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.4135875575
Short name	T520
Test name
Test status
Simulation time	260334114 ps
CPU time	1.16 seconds
Started	Mar 24 02:45:51 PM PDT 24
Finished	Mar 24 02:45:53 PM PDT 24
Peak memory	199108 kb
Host	smart-4eb7a88f-c45e-425f-9cbc-53ffe76f1f12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135875575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4135875575
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.109856652
Short name	T690
Test name
Test status
Simulation time	335192296495 ps
CPU time	235.01 seconds
Started	Mar 24 02:45:57 PM PDT 24
Finished	Mar 24 02:49:53 PM PDT 24
Peak memory	200180 kb
Host	smart-42a055fc-e2ff-4f3d-af66-d5e14d019b55
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109856652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.109856652
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.1932734571
Short name	T910
Test name
Test status
Simulation time	1704436743 ps
CPU time	1.92 seconds
Started	Mar 24 02:45:55 PM PDT 24
Finished	Mar 24 02:45:59 PM PDT 24
Peak memory	198724 kb
Host	smart-4a0c422e-25b6-4b04-8032-4442f5f7fcca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932734571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1932734571
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.1511006883
Short name	T42
Test name
Test status
Simulation time	6471707082 ps
CPU time	9.67 seconds
Started	Mar 24 02:45:51 PM PDT 24
Finished	Mar 24 02:46:01 PM PDT 24
Peak memory	198300 kb
Host	smart-d4ff304d-f3d5-4774-bbc5-d33da722f387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511006883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1511006883
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.3003854981
Short name	T680
Test name
Test status
Simulation time	61524987 ps
CPU time	0.55 seconds
Started	Mar 24 02:45:59 PM PDT 24
Finished	Mar 24 02:46:00 PM PDT 24
Peak memory	195600 kb
Host	smart-d60cbe54-173a-41fb-9fe6-0b1404e766c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003854981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3003854981
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.633561437
Short name	T1050
Test name
Test status
Simulation time	109255417782 ps
CPU time	19.78 seconds
Started	Mar 24 02:45:58 PM PDT 24
Finished	Mar 24 02:46:18 PM PDT 24
Peak memory	200068 kb
Host	smart-6c426415-163a-410d-a983-872e9f48cc75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633561437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.633561437
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.2561669408
Short name	T902
Test name
Test status
Simulation time	36777086110 ps
CPU time	13.6 seconds
Started	Mar 24 02:45:56 PM PDT 24
Finished	Mar 24 02:46:10 PM PDT 24
Peak memory	199996 kb
Host	smart-a803b9fa-0f2c-448c-b5eb-b6bb322af294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561669408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2561669408
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.3949019790
Short name	T674
Test name
Test status
Simulation time	22208405453 ps
CPU time	9.98 seconds
Started	Mar 24 02:45:57 PM PDT 24
Finished	Mar 24 02:46:08 PM PDT 24
Peak memory	199784 kb
Host	smart-97c48ba8-df80-43a8-9106-f9d58477bbf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949019790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3949019790
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/47.uart_intr.2945025829
Short name	T424
Test name
Test status
Simulation time	27816681992 ps
CPU time	16.37 seconds
Started	Mar 24 02:45:59 PM PDT 24
Finished	Mar 24 02:46:16 PM PDT 24
Peak memory	200080 kb
Host	smart-5da2743e-08c4-42c5-9486-f9900e28a14b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945025829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2945025829
Directory	/workspace/47.uart_intr/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.3420846452
Short name	T906
Test name
Test status
Simulation time	110119060201 ps
CPU time	473.17 seconds
Started	Mar 24 02:45:59 PM PDT 24
Finished	Mar 24 02:53:52 PM PDT 24
Peak memory	200120 kb
Host	smart-ceaf3200-c338-40ce-a913-19f3abbd542c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3420846452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3420846452
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_loopback.2915327206
Short name	T476
Test name
Test status
Simulation time	10547236298 ps
CPU time	6.49 seconds
Started	Mar 24 02:46:05 PM PDT 24
Finished	Mar 24 02:46:12 PM PDT 24
Peak memory	199184 kb
Host	smart-e227fabd-c9a7-4059-b336-f01ecf9f4dbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915327206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2915327206
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.794018006
Short name	T846
Test name
Test status
Simulation time	38554121777 ps
CPU time	67.9 seconds
Started	Mar 24 02:46:00 PM PDT 24
Finished	Mar 24 02:47:09 PM PDT 24
Peak memory	208408 kb
Host	smart-15240c73-5b44-4611-9057-163d7843c21a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=794018006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.794018006
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.2071539493
Short name	T366
Test name
Test status
Simulation time	10891622655 ps
CPU time	294.84 seconds
Started	Mar 24 02:46:05 PM PDT 24
Finished	Mar 24 02:51:00 PM PDT 24
Peak memory	200084 kb
Host	smart-2b0d8d66-aa25-4810-8e9d-348277afc81e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2071539493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2071539493
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.1053075580
Short name	T832
Test name
Test status
Simulation time	5175980491 ps
CPU time	10.54 seconds
Started	Mar 24 02:45:57 PM PDT 24
Finished	Mar 24 02:46:08 PM PDT 24
Peak memory	198112 kb
Host	smart-7026b1cd-32ac-43af-ae42-a4c5b2fd580e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1053075580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1053075580
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.2597112289
Short name	T935
Test name
Test status
Simulation time	114410078413 ps
CPU time	170.43 seconds
Started	Mar 24 02:46:00 PM PDT 24
Finished	Mar 24 02:48:50 PM PDT 24
Peak memory	200120 kb
Host	smart-6d7daf49-0070-47c8-b363-7a319dcbbdfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597112289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2597112289
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.2322829233
Short name	T566
Test name
Test status
Simulation time	34346390246 ps
CPU time	47.92 seconds
Started	Mar 24 02:46:00 PM PDT 24
Finished	Mar 24 02:46:49 PM PDT 24
Peak memory	196180 kb
Host	smart-7f7a969d-b1db-45d5-8307-87ad76f776e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322829233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2322829233
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.2135409538
Short name	T54
Test name
Test status
Simulation time	275489532 ps
CPU time	1.32 seconds
Started	Mar 24 02:45:56 PM PDT 24
Finished	Mar 24 02:45:59 PM PDT 24
Peak memory	198284 kb
Host	smart-ab2c5196-4d77-4dbf-b3f3-317fee7127d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135409538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2135409538
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.2227312408
Short name	T182
Test name
Test status
Simulation time	54055586284 ps
CPU time	91.86 seconds
Started	Mar 24 02:46:04 PM PDT 24
Finished	Mar 24 02:47:37 PM PDT 24
Peak memory	200092 kb
Host	smart-b370a5c3-760e-4600-95cc-373813e61ca7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227312408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2227312408
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_stress_all_with_rand_reset.3197934810
Short name	T1023
Test name
Test status
Simulation time	31744259318 ps
CPU time	249.96 seconds
Started	Mar 24 02:46:01 PM PDT 24
Finished	Mar 24 02:50:11 PM PDT 24
Peak memory	215868 kb
Host	smart-5d6bd9bf-3058-490d-b6f0-b34fe59527cf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197934810 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3197934810
Directory	/workspace/47.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.1742670254
Short name	T400
Test name
Test status
Simulation time	968149169 ps
CPU time	2.4 seconds
Started	Mar 24 02:46:01 PM PDT 24
Finished	Mar 24 02:46:04 PM PDT 24
Peak memory	198884 kb
Host	smart-8ad83034-4880-4864-9452-c0fdbb24d4d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742670254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1742670254
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.4123267712
Short name	T722
Test name
Test status
Simulation time	10441297383 ps
CPU time	16.54 seconds
Started	Mar 24 02:45:55 PM PDT 24
Finished	Mar 24 02:46:13 PM PDT 24
Peak memory	200136 kb
Host	smart-35e03e56-18c4-4fc7-bb17-9823f4fe4042
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123267712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4123267712
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.3991592595
Short name	T593
Test name
Test status
Simulation time	38334940 ps
CPU time	0.6 seconds
Started	Mar 24 02:46:04 PM PDT 24
Finished	Mar 24 02:46:06 PM PDT 24
Peak memory	194948 kb
Host	smart-e84195e6-de3b-4293-b267-d4a02a53ba8d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991592595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3991592595
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.810438290
Short name	T941
Test name
Test status
Simulation time	129476194087 ps
CPU time	106.08 seconds
Started	Mar 24 02:46:02 PM PDT 24
Finished	Mar 24 02:47:49 PM PDT 24
Peak memory	200160 kb
Host	smart-c0e8d8d2-7b01-406e-8106-01e48cb0e4b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810438290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.810438290
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.2742042604
Short name	T488
Test name
Test status
Simulation time	20114015765 ps
CPU time	41.32 seconds
Started	Mar 24 02:46:00 PM PDT 24
Finished	Mar 24 02:46:41 PM PDT 24
Peak memory	200112 kb
Host	smart-e35bc757-23ef-4fd3-8180-d9e8ac78a25c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742042604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2742042604
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.3537573127
Short name	T188
Test name
Test status
Simulation time	14611027187 ps
CPU time	28.15 seconds
Started	Mar 24 02:46:03 PM PDT 24
Finished	Mar 24 02:46:31 PM PDT 24
Peak memory	200060 kb
Host	smart-4f253f6a-ece8-4ef3-ad61-255928305897
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537573127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3537573127
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_intr.2234152779
Short name	T624
Test name
Test status
Simulation time	47426043109 ps
CPU time	31.64 seconds
Started	Mar 24 02:46:06 PM PDT 24
Finished	Mar 24 02:46:37 PM PDT 24
Peak memory	200356 kb
Host	smart-f1f5cff3-6fd1-4e0c-9323-f0085f15e72f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234152779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2234152779
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.2300873458
Short name	T611
Test name
Test status
Simulation time	53986577112 ps
CPU time	89.26 seconds
Started	Mar 24 02:46:03 PM PDT 24
Finished	Mar 24 02:47:32 PM PDT 24
Peak memory	200072 kb
Host	smart-29e8a747-1c16-4842-8733-3f51c06f59e5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2300873458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2300873458
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.1085066049
Short name	T62
Test name
Test status
Simulation time	9217024727 ps
CPU time	7.19 seconds
Started	Mar 24 02:46:03 PM PDT 24
Finished	Mar 24 02:46:11 PM PDT 24
Peak memory	200064 kb
Host	smart-10125ec9-50d2-410d-a164-97e66d5c0b4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085066049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1085066049
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.226797933
Short name	T507
Test name
Test status
Simulation time	119141325174 ps
CPU time	107.46 seconds
Started	Mar 24 02:46:03 PM PDT 24
Finished	Mar 24 02:47:51 PM PDT 24
Peak memory	200228 kb
Host	smart-7684d2e0-04f8-4201-a9d6-09ba4c844b7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226797933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.226797933
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.3801174500
Short name	T417
Test name
Test status
Simulation time	16840660773 ps
CPU time	201.75 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:49:31 PM PDT 24
Peak memory	200104 kb
Host	smart-42523419-ede2-4b7b-8e25-b5a5f3e8ae0e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3801174500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3801174500
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_oversample.2136201700
Short name	T794
Test name
Test status
Simulation time	4701717285 ps
CPU time	25.13 seconds
Started	Mar 24 02:46:08 PM PDT 24
Finished	Mar 24 02:46:33 PM PDT 24
Peak memory	198416 kb
Host	smart-387b1300-eacb-44cf-b14a-071fbbbd2339
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2136201700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2136201700
Directory	/workspace/48.uart_rx_oversample/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.2286412701
Short name	T706
Test name
Test status
Simulation time	127390197616 ps
CPU time	16.59 seconds
Started	Mar 24 02:46:05 PM PDT 24
Finished	Mar 24 02:46:22 PM PDT 24
Peak memory	199452 kb
Host	smart-117f8920-7d03-45af-8a0b-40582bf12dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286412701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2286412701
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.984206978
Short name	T956
Test name
Test status
Simulation time	2933811367 ps
CPU time	1.84 seconds
Started	Mar 24 02:46:06 PM PDT 24
Finished	Mar 24 02:46:08 PM PDT 24
Peak memory	196224 kb
Host	smart-2442531c-294b-4d9d-ac3c-fd67f421c363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984206978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.984206978
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.3995550464
Short name	T774
Test name
Test status
Simulation time	604994119 ps
CPU time	3.57 seconds
Started	Mar 24 02:46:04 PM PDT 24
Finished	Mar 24 02:46:09 PM PDT 24
Peak memory	198424 kb
Host	smart-63a38699-607e-484b-ba73-96d5c1f21c34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995550464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3995550464
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.502389722
Short name	T777
Test name
Test status
Simulation time	6226347437 ps
CPU time	9.7 seconds
Started	Mar 24 02:46:05 PM PDT 24
Finished	Mar 24 02:46:15 PM PDT 24
Peak memory	199564 kb
Host	smart-89851f16-d062-4595-9089-557742f17cd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502389722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.502389722
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.564611323
Short name	T838
Test name
Test status
Simulation time	107799316054 ps
CPU time	41.96 seconds
Started	Mar 24 02:46:04 PM PDT 24
Finished	Mar 24 02:46:47 PM PDT 24
Peak memory	200136 kb
Host	smart-bb8d732a-f729-403b-a780-747f0424b00c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564611323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.564611323
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.926464597
Short name	T30
Test name
Test status
Simulation time	53032030 ps
CPU time	0.54 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:46:09 PM PDT 24
Peak memory	195004 kb
Host	smart-9318e156-e4ed-4bdc-b467-d3e38c29ea86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926464597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.926464597
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.214774505
Short name	T842
Test name
Test status
Simulation time	79652368363 ps
CPU time	40.37 seconds
Started	Mar 24 02:46:06 PM PDT 24
Finished	Mar 24 02:46:46 PM PDT 24
Peak memory	200128 kb
Host	smart-441db87c-0979-4b7d-9176-8756b46e818b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214774505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.214774505
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.3002176558
Short name	T977
Test name
Test status
Simulation time	30951723649 ps
CPU time	70.34 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:47:20 PM PDT 24
Peak memory	199944 kb
Host	smart-a4d8d6c6-fe0e-405e-b6f9-e1cbee39d202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002176558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3002176558
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.1312718152
Short name	T879
Test name
Test status
Simulation time	8746380797 ps
CPU time	14.12 seconds
Started	Mar 24 02:46:05 PM PDT 24
Finished	Mar 24 02:46:19 PM PDT 24
Peak memory	199992 kb
Host	smart-ebce1573-7fbb-4f02-a628-79696b0463d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312718152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1312718152
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_intr.1747972369
Short name	T431
Test name
Test status
Simulation time	34433891895 ps
CPU time	29.53 seconds
Started	Mar 24 02:46:10 PM PDT 24
Finished	Mar 24 02:46:40 PM PDT 24
Peak memory	198696 kb
Host	smart-7828a850-2add-464f-bfd5-1475f99af9bd
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747972369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1747972369
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.452565003
Short name	T620
Test name
Test status
Simulation time	40136162589 ps
CPU time	71.46 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:47:21 PM PDT 24
Peak memory	200116 kb
Host	smart-3b564de0-621c-41c9-9a29-2e223c3fb36d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=452565003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.452565003
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/49.uart_loopback.2858690460
Short name	T83
Test name
Test status
Simulation time	11118248785 ps
CPU time	6.62 seconds
Started	Mar 24 02:46:10 PM PDT 24
Finished	Mar 24 02:46:17 PM PDT 24
Peak memory	200176 kb
Host	smart-af2d5b35-c2f6-4eb9-8df0-617ed5f2d902
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858690460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2858690460
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.809188901
Short name	T664
Test name
Test status
Simulation time	70660769576 ps
CPU time	53.62 seconds
Started	Mar 24 02:46:08 PM PDT 24
Finished	Mar 24 02:47:02 PM PDT 24
Peak memory	200240 kb
Host	smart-59696dff-02fa-4937-8455-90f4ed1ba9f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809188901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.809188901
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.2824435590
Short name	T292
Test name
Test status
Simulation time	5244228768 ps
CPU time	271.4 seconds
Started	Mar 24 02:46:08 PM PDT 24
Finished	Mar 24 02:50:39 PM PDT 24
Peak memory	200076 kb
Host	smart-9f59a877-d0a4-46c2-be7a-7162d7376d70
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2824435590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2824435590
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.1933288940
Short name	T1100
Test name
Test status
Simulation time	6508808975 ps
CPU time	51.26 seconds
Started	Mar 24 02:46:07 PM PDT 24
Finished	Mar 24 02:46:58 PM PDT 24
Peak memory	200100 kb
Host	smart-af51c4b8-3685-4897-a456-e074fa03dc76
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1933288940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1933288940
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.359989458
Short name	T477
Test name
Test status
Simulation time	116981035788 ps
CPU time	37.78 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:46:46 PM PDT 24
Peak memory	199916 kb
Host	smart-bcfbcf03-52f6-4060-803e-7e909bf01e0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359989458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.359989458
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.944918008
Short name	T670
Test name
Test status
Simulation time	36825633755 ps
CPU time	16.93 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:46:26 PM PDT 24
Peak memory	196212 kb
Host	smart-3576d963-f6fa-4ca5-8639-8e862b82fb7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944918008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.944918008
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.2854267944
Short name	T529
Test name
Test status
Simulation time	464834114 ps
CPU time	1.68 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:46:11 PM PDT 24
Peak memory	198940 kb
Host	smart-9a863c88-9e88-4db5-aefd-4e214b059af7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854267944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2854267944
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_stress_all.144608593
Short name	T884
Test name
Test status
Simulation time	323625149132 ps
CPU time	586.1 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:55:55 PM PDT 24
Peak memory	200140 kb
Host	smart-0b2803d3-e3cb-41c1-b1d1-7b78de2f244a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144608593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.144608593
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.612127375
Short name	T600
Test name
Test status
Simulation time	885875055 ps
CPU time	2.69 seconds
Started	Mar 24 02:46:09 PM PDT 24
Finished	Mar 24 02:46:12 PM PDT 24
Peak memory	198668 kb
Host	smart-36472702-822b-4706-84d5-9cd96791f4e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612127375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.612127375
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.3311321173
Short name	T865
Test name
Test status
Simulation time	88405534565 ps
CPU time	35.05 seconds
Started	Mar 24 02:46:04 PM PDT 24
Finished	Mar 24 02:46:40 PM PDT 24
Peak memory	200080 kb
Host	smart-8da01185-9099-4c51-a8ee-37eac64851aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311321173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3311321173
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.3418269538
Short name	T859
Test name
Test status
Simulation time	111675702 ps
CPU time	0.57 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:27 PM PDT 24
Peak memory	194604 kb
Host	smart-e959e3e9-ac2d-4661-8e3a-df60a82057ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418269538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3418269538
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.3833648647
Short name	T931
Test name
Test status
Simulation time	26027730746 ps
CPU time	12.19 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:43:35 PM PDT 24
Peak memory	200172 kb
Host	smart-cf80bc7c-c607-472e-a7cb-eb783541374b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833648647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3833648647
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.4084324965
Short name	T558
Test name
Test status
Simulation time	37072882822 ps
CPU time	27.34 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:43:55 PM PDT 24
Peak memory	200164 kb
Host	smart-dcea5c80-0c75-4024-abf5-12d5341639ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084324965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4084324965
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.1250875977
Short name	T238
Test name
Test status
Simulation time	93319256398 ps
CPU time	40.3 seconds
Started	Mar 24 02:43:29 PM PDT 24
Finished	Mar 24 02:44:10 PM PDT 24
Peak memory	200168 kb
Host	smart-859d5c50-5dda-4fa8-b2e3-92f2f12e78c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250875977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1250875977
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.1633339637
Short name	T641
Test name
Test status
Simulation time	9789672271 ps
CPU time	15.74 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:43:41 PM PDT 24
Peak memory	197444 kb
Host	smart-fde5c65b-35d0-407f-a909-145be9acba52
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633339637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1633339637
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.752993672
Short name	T1054
Test name
Test status
Simulation time	72639568567 ps
CPU time	183.45 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:46:27 PM PDT 24
Peak memory	200116 kb
Host	smart-fb1cfbf5-077f-4f11-b6b3-8b0e05643536
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=752993672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.752993672
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.1104996909
Short name	T802
Test name
Test status
Simulation time	4528699199 ps
CPU time	5.62 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:43:36 PM PDT 24
Peak memory	199208 kb
Host	smart-c70c68cd-db09-4e27-96b2-2c5bfd5e537d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104996909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1104996909
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.1122715403
Short name	T129
Test name
Test status
Simulation time	108892935977 ps
CPU time	97.78 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:45:11 PM PDT 24
Peak memory	199044 kb
Host	smart-c37da854-7ef9-4e92-b250-5397c4d73c24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122715403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1122715403
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.2476762382
Short name	T271
Test name
Test status
Simulation time	19392137790 ps
CPU time	201.65 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:46:55 PM PDT 24
Peak memory	200180 kb
Host	smart-025e8a6e-f7fb-4271-8857-da3e432647e7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2476762382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2476762382
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.4234843759
Short name	T878
Test name
Test status
Simulation time	2012089402 ps
CPU time	9.45 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:43:33 PM PDT 24
Peak memory	198548 kb
Host	smart-d38e075c-c6d1-4857-b688-94952fc808b3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4234843759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.4234843759
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.3351680094
Short name	T141
Test name
Test status
Simulation time	24875446004 ps
CPU time	10.12 seconds
Started	Mar 24 02:43:18 PM PDT 24
Finished	Mar 24 02:43:29 PM PDT 24
Peak memory	200144 kb
Host	smart-f0ce888a-3b61-442e-b420-c75390eca845
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351680094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3351680094
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.4179528707
Short name	T981
Test name
Test status
Simulation time	6174146027 ps
CPU time	2.94 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:43:36 PM PDT 24
Peak memory	196204 kb
Host	smart-9af8d407-ea69-42b3-a5b8-5efc3cf52bee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179528707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4179528707
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.3180756525
Short name	T986
Test name
Test status
Simulation time	5888453395 ps
CPU time	15.39 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:43:50 PM PDT 24
Peak memory	200060 kb
Host	smart-18ce45c9-30bb-4c01-9529-3d9fe9cde925
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180756525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3180756525
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all_with_rand_reset.2202036548
Short name	T656
Test name
Test status
Simulation time	151387107295 ps
CPU time	621.59 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:53:50 PM PDT 24
Peak memory	225036 kb
Host	smart-200645c1-fed5-4c9a-a95a-979d53a78814
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202036548 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2202036548
Directory	/workspace/5.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.2969582122
Short name	T784
Test name
Test status
Simulation time	1332190818 ps
CPU time	1.97 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:24 PM PDT 24
Peak memory	199840 kb
Host	smart-170c6c43-aaf4-4f64-ad76-d3c3dc2fed32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969582122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2969582122
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.1818939487
Short name	T741
Test name
Test status
Simulation time	96433781631 ps
CPU time	161.89 seconds
Started	Mar 24 02:43:19 PM PDT 24
Finished	Mar 24 02:46:02 PM PDT 24
Peak memory	200088 kb
Host	smart-e4f87cfc-b34c-484b-8e48-cafcd9804aa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818939487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1818939487
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.2740360756
Short name	T559
Test name
Test status
Simulation time	160633502931 ps
CPU time	40.37 seconds
Started	Mar 24 02:46:11 PM PDT 24
Finished	Mar 24 02:46:51 PM PDT 24
Peak memory	200124 kb
Host	smart-bb6b3a3b-4466-4534-b386-0ce694082134
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740360756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2740360756
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.2044471839
Short name	T1123
Test name
Test status
Simulation time	37344894659 ps
CPU time	20.44 seconds
Started	Mar 24 02:46:08 PM PDT 24
Finished	Mar 24 02:46:29 PM PDT 24
Peak memory	200116 kb
Host	smart-49a4c937-9ae4-43af-8e89-249b54445332
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044471839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2044471839
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.1522741757
Short name	T925
Test name
Test status
Simulation time	109947613023 ps
CPU time	168.85 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:49:04 PM PDT 24
Peak memory	200060 kb
Host	smart-073a3d1a-7c56-4d25-9de9-862cb0f3b566
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522741757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1522741757
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.1152869251
Short name	T130
Test name
Test status
Simulation time	48533777230 ps
CPU time	96.32 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:47:51 PM PDT 24
Peak memory	200136 kb
Host	smart-9eeda6f8-b7b2-4945-966d-6da7cbac2a1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152869251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1152869251
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.1716233028
Short name	T234
Test name
Test status
Simulation time	121956298567 ps
CPU time	60.33 seconds
Started	Mar 24 02:46:13 PM PDT 24
Finished	Mar 24 02:47:13 PM PDT 24
Peak memory	199912 kb
Host	smart-ce844203-53d9-4f3a-9f5d-751311e07b08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716233028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1716233028
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_stress_all_with_rand_reset.3025695541
Short name	T68
Test name
Test status
Simulation time	51153432645 ps
CPU time	487.88 seconds
Started	Mar 24 02:46:16 PM PDT 24
Finished	Mar 24 02:54:24 PM PDT 24
Peak memory	216720 kb
Host	smart-14bceb79-d8f5-47ac-9e4b-2539631cf037
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025695541 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3025695541
Directory	/workspace/54.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.2677271909
Short name	T596
Test name
Test status
Simulation time	108072500837 ps
CPU time	161.18 seconds
Started	Mar 24 02:46:16 PM PDT 24
Finished	Mar 24 02:48:58 PM PDT 24
Peak memory	200072 kb
Host	smart-d0404635-22a9-43b4-9574-ea7880cfa8ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677271909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2677271909
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.2677797491
Short name	T367
Test name
Test status
Simulation time	107647645534 ps
CPU time	111.98 seconds
Started	Mar 24 02:46:13 PM PDT 24
Finished	Mar 24 02:48:07 PM PDT 24
Peak memory	200144 kb
Host	smart-024ad661-c068-4179-bcbc-673bbeebbd7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677797491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2677797491
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_stress_all_with_rand_reset.3294581962
Short name	T112
Test name
Test status
Simulation time	29940798713 ps
CPU time	192.06 seconds
Started	Mar 24 02:46:16 PM PDT 24
Finished	Mar 24 02:49:28 PM PDT 24
Peak memory	216220 kb
Host	smart-0ed33461-8677-4210-b676-c0d84389f79d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294581962 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3294581962
Directory	/workspace/57.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/58.uart_stress_all_with_rand_reset.3991361113
Short name	T732
Test name
Test status
Simulation time	43301856258 ps
CPU time	301.17 seconds
Started	Mar 24 02:46:12 PM PDT 24
Finished	Mar 24 02:51:14 PM PDT 24
Peak memory	215768 kb
Host	smart-b7429489-5001-48ae-8f03-fc8864430e3f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991361113 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3991361113
Directory	/workspace/58.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.2219066083
Short name	T1077
Test name
Test status
Simulation time	18716136 ps
CPU time	0.56 seconds
Started	Mar 24 02:43:37 PM PDT 24
Finished	Mar 24 02:43:37 PM PDT 24
Peak memory	195612 kb
Host	smart-cc803b80-7a52-4ee4-8a10-386f8c8e0701
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219066083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2219066083
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.811745893
Short name	T343
Test name
Test status
Simulation time	124351585229 ps
CPU time	194.66 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:46:45 PM PDT 24
Peak memory	200172 kb
Host	smart-e9c5592c-7f67-4ec0-9c60-852e25d527f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811745893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.811745893
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.4225553151
Short name	T776
Test name
Test status
Simulation time	16989143956 ps
CPU time	8.55 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:43:32 PM PDT 24
Peak memory	199756 kb
Host	smart-229d13b6-cda4-4559-b6f5-4e87b435bd20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225553151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4225553151
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_fifo_reset.1865692844
Short name	T361
Test name
Test status
Simulation time	53112038415 ps
CPU time	15.23 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:38 PM PDT 24
Peak memory	200176 kb
Host	smart-b325764b-9331-44eb-866e-87a621024127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865692844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1865692844
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_intr.2961704080
Short name	T312
Test name
Test status
Simulation time	20550230067 ps
CPU time	6.65 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:43:29 PM PDT 24
Peak memory	199780 kb
Host	smart-44f7437c-4968-4051-8126-2f14f80f462b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961704080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2961704080
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.1996832867
Short name	T1089
Test name
Test status
Simulation time	84996821216 ps
CPU time	649.56 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:54:22 PM PDT 24
Peak memory	200080 kb
Host	smart-0aa61048-c644-4324-a38c-fc96c99528ff
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1996832867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1996832867
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.3379000747
Short name	T582
Test name
Test status
Simulation time	9119893002 ps
CPU time	3.58 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:31 PM PDT 24
Peak memory	200116 kb
Host	smart-b57d35fa-bb9c-4e1f-8922-fa37807bd8eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379000747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3379000747
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.3692339847
Short name	T998
Test name
Test status
Simulation time	24414445150 ps
CPU time	10.47 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:43:43 PM PDT 24
Peak memory	194976 kb
Host	smart-5c8c1384-8aa2-4664-ad23-65bcb4ad1986
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692339847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3692339847
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.1804843185
Short name	T964
Test name
Test status
Simulation time	8062068688 ps
CPU time	492.37 seconds
Started	Mar 24 02:43:22 PM PDT 24
Finished	Mar 24 02:51:35 PM PDT 24
Peak memory	200084 kb
Host	smart-39b788e6-ad5d-42c7-91a8-f94f9f274b93
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1804843185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1804843185
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.50885250
Short name	T1086
Test name
Test status
Simulation time	3019350222 ps
CPU time	22.05 seconds
Started	Mar 24 02:43:31 PM PDT 24
Finished	Mar 24 02:43:53 PM PDT 24
Peak memory	198140 kb
Host	smart-c8f8b09c-c4c1-42d1-9c4e-0fc37caae33b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=50885250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.50885250
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.971267381
Short name	T1017
Test name
Test status
Simulation time	36070881170 ps
CPU time	14.96 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:43:43 PM PDT 24
Peak memory	198848 kb
Host	smart-212e5c3f-576f-4a96-8b79-82b004e41a33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971267381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.971267381
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.310808344
Short name	T636
Test name
Test status
Simulation time	59241866196 ps
CPU time	17.92 seconds
Started	Mar 24 02:43:20 PM PDT 24
Finished	Mar 24 02:43:39 PM PDT 24
Peak memory	196228 kb
Host	smart-279e3f10-fbf2-43a3-af65-6ac9e664ac28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310808344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.310808344
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.2008503757
Short name	T604
Test name
Test status
Simulation time	529017209 ps
CPU time	2.25 seconds
Started	Mar 24 02:43:23 PM PDT 24
Finished	Mar 24 02:43:25 PM PDT 24
Peak memory	198304 kb
Host	smart-6bdb846a-4468-4c47-bcf8-d10225d2672e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008503757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2008503757
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.770118206
Short name	T1125
Test name
Test status
Simulation time	10986789423 ps
CPU time	125.79 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:45:33 PM PDT 24
Peak memory	200160 kb
Host	smart-d81b812b-72a7-493a-9c23-4792a60ce2e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770118206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.770118206
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.1797357599
Short name	T767
Test name
Test status
Simulation time	487123515 ps
CPU time	2.07 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:43:26 PM PDT 24
Peak memory	198020 kb
Host	smart-a00ce7ca-c4eb-45bb-a8bc-951249e66237
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797357599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1797357599
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.2007228244
Short name	T285
Test name
Test status
Simulation time	51977768510 ps
CPU time	112.49 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:45:17 PM PDT 24
Peak memory	200052 kb
Host	smart-27f9c495-0ede-43bb-b089-a14a7a8b9e9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007228244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2007228244
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.2720182068
Short name	T166
Test name
Test status
Simulation time	15068116951 ps
CPU time	13.12 seconds
Started	Mar 24 02:46:15 PM PDT 24
Finished	Mar 24 02:46:28 PM PDT 24
Peak memory	200008 kb
Host	smart-a5ba54d4-9872-4b8a-b16b-e537ea68b13b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720182068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2720182068
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/60.uart_stress_all_with_rand_reset.1294999774
Short name	T36
Test name
Test status
Simulation time	76953731115 ps
CPU time	340.06 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:51:55 PM PDT 24
Peak memory	216732 kb
Host	smart-705ede1c-bae2-47a5-b086-04b87b873929
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294999774 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1294999774
Directory	/workspace/60.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.235519995
Short name	T1093
Test name
Test status
Simulation time	80903463508 ps
CPU time	28.13 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:46:43 PM PDT 24
Peak memory	200044 kb
Host	smart-186c89ec-fe6c-4d7c-9176-e024086d4284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235519995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.235519995
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_fifo_reset.787236015
Short name	T219
Test name
Test status
Simulation time	86852118308 ps
CPU time	82.03 seconds
Started	Mar 24 02:46:18 PM PDT 24
Finished	Mar 24 02:47:40 PM PDT 24
Peak memory	200140 kb
Host	smart-c65499a4-8933-4611-959f-155c2b094b04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787236015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.787236015
Directory	/workspace/63.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_stress_all_with_rand_reset.493708939
Short name	T356
Test name
Test status
Simulation time	109730345006 ps
CPU time	1078.39 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 03:04:13 PM PDT 24
Peak memory	225240 kb
Host	smart-fa1c25ad-d0b4-4a9b-b4fa-5f6c20d837c3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493708939 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.493708939
Directory	/workspace/63.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.1042393294
Short name	T204
Test name
Test status
Simulation time	53841086865 ps
CPU time	71.69 seconds
Started	Mar 24 02:46:14 PM PDT 24
Finished	Mar 24 02:47:27 PM PDT 24
Peak memory	200120 kb
Host	smart-c1d35fb1-f4a5-4be8-b31f-9ba74d73b8f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042393294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1042393294
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_stress_all_with_rand_reset.3163214957
Short name	T880
Test name
Test status
Simulation time	12816690418 ps
CPU time	312.96 seconds
Started	Mar 24 02:46:19 PM PDT 24
Finished	Mar 24 02:51:32 PM PDT 24
Peak memory	200336 kb
Host	smart-03cdaf32-2cf8-43c2-90a9-e5eb4fb17f51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163214957 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3163214957
Directory	/workspace/64.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.2604432021
Short name	T230
Test name
Test status
Simulation time	48465535272 ps
CPU time	17.37 seconds
Started	Mar 24 02:46:18 PM PDT 24
Finished	Mar 24 02:46:35 PM PDT 24
Peak memory	200136 kb
Host	smart-b7f583d3-beca-4b6c-9a4f-5e7f716d566d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604432021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2604432021
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_stress_all_with_rand_reset.2067388707
Short name	T37
Test name
Test status
Simulation time	20123472610 ps
CPU time	162.11 seconds
Started	Mar 24 02:46:23 PM PDT 24
Finished	Mar 24 02:49:05 PM PDT 24
Peak memory	208536 kb
Host	smart-1b0156d5-10fa-44d6-ab74-ab389759da64
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067388707 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2067388707
Directory	/workspace/65.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.3367547587
Short name	T671
Test name
Test status
Simulation time	207868559185 ps
CPU time	170.4 seconds
Started	Mar 24 02:46:20 PM PDT 24
Finished	Mar 24 02:49:11 PM PDT 24
Peak memory	200128 kb
Host	smart-626c8909-9287-4775-a611-d1e8d412cb7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367547587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3367547587
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.3948430521
Short name	T468
Test name
Test status
Simulation time	66698686489 ps
CPU time	52.35 seconds
Started	Mar 24 02:46:18 PM PDT 24
Finished	Mar 24 02:47:10 PM PDT 24
Peak memory	200104 kb
Host	smart-be897a1a-bd2f-4a1a-ad1e-06a2d8f12c98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948430521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3948430521
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.1677870866
Short name	T370
Test name
Test status
Simulation time	21969566268 ps
CPU time	37.18 seconds
Started	Mar 24 02:46:18 PM PDT 24
Finished	Mar 24 02:46:55 PM PDT 24
Peak memory	200252 kb
Host	smart-0f88d69e-0e0e-42e9-a8ad-0507dedb31fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677870866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1677870866
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.3916651658
Short name	T296
Test name
Test status
Simulation time	16147884780 ps
CPU time	8.78 seconds
Started	Mar 24 02:46:19 PM PDT 24
Finished	Mar 24 02:46:28 PM PDT 24
Peak memory	200164 kb
Host	smart-9f305ca4-633e-4856-af86-867373348577
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916651658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3916651658
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.2025609052
Short name	T503
Test name
Test status
Simulation time	49339924 ps
CPU time	0.57 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:43:31 PM PDT 24
Peak memory	195628 kb
Host	smart-15ea25bd-8a27-4574-a257-de527f6d860a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025609052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2025609052
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.2496353311
Short name	T1110
Test name
Test status
Simulation time	39903295678 ps
CPU time	17.06 seconds
Started	Mar 24 02:43:29 PM PDT 24
Finished	Mar 24 02:43:46 PM PDT 24
Peak memory	200188 kb
Host	smart-927f4ba1-96a4-45c5-a1b3-b0ee5c2c14f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496353311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2496353311
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.1206349826
Short name	T697
Test name
Test status
Simulation time	44492310444 ps
CPU time	87.45 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:44:59 PM PDT 24
Peak memory	200156 kb
Host	smart-5c3e9587-0561-443d-a8e2-a28e76026482
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206349826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1206349826
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.3644616487
Short name	T171
Test name
Test status
Simulation time	139364969561 ps
CPU time	54.8 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	200104 kb
Host	smart-5ca7ed92-740a-4963-a598-5cc6ed0627e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644616487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3644616487
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_intr.3594961805
Short name	T816
Test name
Test status
Simulation time	200534213722 ps
CPU time	304.16 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:48:37 PM PDT 24
Peak memory	197248 kb
Host	smart-777808b7-bbf5-4040-9cbd-a70fb48d8d97
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594961805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3594961805
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.994971835
Short name	T1118
Test name
Test status
Simulation time	76032374314 ps
CPU time	242.63 seconds
Started	Mar 24 02:43:29 PM PDT 24
Finished	Mar 24 02:47:32 PM PDT 24
Peak memory	200124 kb
Host	smart-504918a7-50f7-4860-9401-b23c0f84b48d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=994971835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.994971835
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_loopback.1626682202
Short name	T433
Test name
Test status
Simulation time	827211451 ps
CPU time	0.9 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:43:31 PM PDT 24
Peak memory	195804 kb
Host	smart-08db5de3-e5ee-43fc-a175-4039e5fac99c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626682202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1626682202
Directory	/workspace/7.uart_loopback/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.2855728042
Short name	T284
Test name
Test status
Simulation time	157370430239 ps
CPU time	86.14 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:44:53 PM PDT 24
Peak memory	199716 kb
Host	smart-5281f52f-b50c-4ea8-8499-5aa181e78eec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855728042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2855728042
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.2620949513
Short name	T691
Test name
Test status
Simulation time	8553643166 ps
CPU time	493.93 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:51:39 PM PDT 24
Peak memory	200160 kb
Host	smart-4c223a72-c5b1-4a0c-934f-0efb3b83b745
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2620949513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2620949513
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_oversample.848061647
Short name	T18
Test name
Test status
Simulation time	3974590692 ps
CPU time	14.77 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:43:43 PM PDT 24
Peak memory	199052 kb
Host	smart-6dd2630c-cb4e-4ba6-b892-55f5dd0afa7b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=848061647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.848061647
Directory	/workspace/7.uart_rx_oversample/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.3443845672
Short name	T613
Test name
Test status
Simulation time	110603980836 ps
CPU time	169.78 seconds
Started	Mar 24 02:43:43 PM PDT 24
Finished	Mar 24 02:46:33 PM PDT 24
Peak memory	200092 kb
Host	smart-af7ddc13-7484-4cec-ae73-15aefef26b50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443845672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3443845672
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.3226146831
Short name	T399
Test name
Test status
Simulation time	3088208760 ps
CPU time	1.75 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:29 PM PDT 24
Peak memory	196252 kb
Host	smart-4026cdba-ff60-4083-944f-081b6a152293
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226146831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3226146831
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.4013893644
Short name	T896
Test name
Test status
Simulation time	5764416200 ps
CPU time	17.2 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:43:53 PM PDT 24
Peak memory	199512 kb
Host	smart-f3ab253d-5e89-429c-80c3-75602e3ca11d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013893644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4013893644
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_stress_all.3897428896
Short name	T800
Test name
Test status
Simulation time	263001021253 ps
CPU time	220.94 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:47:14 PM PDT 24
Peak memory	200144 kb
Host	smart-bd66b6c4-0589-4332-876f-8812f95aecbb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897428896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3897428896
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.3250524586
Short name	T337
Test name
Test status
Simulation time	1782165288 ps
CPU time	1.68 seconds
Started	Mar 24 02:43:29 PM PDT 24
Finished	Mar 24 02:43:31 PM PDT 24
Peak memory	199944 kb
Host	smart-4d7850f7-51ca-4434-9901-1c8aee981901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250524586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3250524586
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.1981821279
Short name	T1061
Test name
Test status
Simulation time	153297757383 ps
CPU time	45.67 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:44:20 PM PDT 24
Peak memory	200124 kb
Host	smart-c38fae25-4255-49d5-a4bc-5ef6f9c4b893
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981821279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1981821279
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.75147189
Short name	T122
Test name
Test status
Simulation time	8685876958 ps
CPU time	4.84 seconds
Started	Mar 24 02:46:19 PM PDT 24
Finished	Mar 24 02:46:24 PM PDT 24
Peak memory	200348 kb
Host	smart-736171d6-2eee-4aed-b3e4-8803a3f43d72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75147189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.75147189
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.2748806295
Short name	T850
Test name
Test status
Simulation time	44831400148 ps
CPU time	24.11 seconds
Started	Mar 24 02:46:18 PM PDT 24
Finished	Mar 24 02:46:43 PM PDT 24
Peak memory	200148 kb
Host	smart-c6569f0b-5d42-4b60-9bea-dad9b85ed102
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748806295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2748806295
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.1130473170
Short name	T341
Test name
Test status
Simulation time	61152485507 ps
CPU time	233.04 seconds
Started	Mar 24 02:46:20 PM PDT 24
Finished	Mar 24 02:50:14 PM PDT 24
Peak memory	200184 kb
Host	smart-64a215aa-dc93-49f0-8ec0-7c91042f3460
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130473170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1130473170
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_stress_all_with_rand_reset.334169180
Short name	T40
Test name
Test status
Simulation time	552952012663 ps
CPU time	283.92 seconds
Started	Mar 24 02:46:26 PM PDT 24
Finished	Mar 24 02:51:11 PM PDT 24
Peak memory	217028 kb
Host	smart-9559e578-9d09-4b6f-a357-6d1cbd48d7d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334169180 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.334169180
Directory	/workspace/73.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.1635503557
Short name	T844
Test name
Test status
Simulation time	146653448726 ps
CPU time	149.48 seconds
Started	Mar 24 02:46:22 PM PDT 24
Finished	Mar 24 02:48:52 PM PDT 24
Peak memory	200172 kb
Host	smart-fc18abeb-d50b-4ec0-87c4-18757dc57329
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635503557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1635503557
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.676733176
Short name	T945
Test name
Test status
Simulation time	69962409460 ps
CPU time	30.35 seconds
Started	Mar 24 02:46:25 PM PDT 24
Finished	Mar 24 02:46:56 PM PDT 24
Peak memory	200124 kb
Host	smart-5a2f6218-7160-4c35-b37a-b7ff5b7d32fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676733176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.676733176
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/75.uart_stress_all_with_rand_reset.1843957239
Short name	T549
Test name
Test status
Simulation time	214056575423 ps
CPU time	853.94 seconds
Started	Mar 24 02:46:26 PM PDT 24
Finished	Mar 24 03:00:41 PM PDT 24
Peak memory	216840 kb
Host	smart-285c7d16-8a58-41eb-8bca-9214dcf53f87
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843957239 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1843957239
Directory	/workspace/75.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/76.uart_stress_all_with_rand_reset.1471482064
Short name	T66
Test name
Test status
Simulation time	236571357245 ps
CPU time	601.27 seconds
Started	Mar 24 02:46:24 PM PDT 24
Finished	Mar 24 02:56:26 PM PDT 24
Peak memory	216836 kb
Host	smart-e7551c93-9a9e-4ece-a764-bdc187a04d00
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471482064 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1471482064
Directory	/workspace/76.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.1798647842
Short name	T43
Test name
Test status
Simulation time	105051441774 ps
CPU time	41.06 seconds
Started	Mar 24 02:46:26 PM PDT 24
Finished	Mar 24 02:47:08 PM PDT 24
Peak memory	199812 kb
Host	smart-c375a2e8-34f5-4b0f-aa37-93bde981d338
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798647842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1798647842
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/77.uart_stress_all_with_rand_reset.7926155
Short name	T571
Test name
Test status
Simulation time	84362150686 ps
CPU time	283.99 seconds
Started	Mar 24 02:46:27 PM PDT 24
Finished	Mar 24 02:51:11 PM PDT 24
Peak memory	216740 kb
Host	smart-9ee7a250-8f92-42e5-b677-ccc6c932bc10
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7926155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.7926155
Directory	/workspace/77.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.435202292
Short name	T1068
Test name
Test status
Simulation time	19538140292 ps
CPU time	30.34 seconds
Started	Mar 24 02:46:25 PM PDT 24
Finished	Mar 24 02:46:56 PM PDT 24
Peak memory	200084 kb
Host	smart-f5201f83-789f-449f-aed0-f359786a18f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435202292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.435202292
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_stress_all_with_rand_reset.449927283
Short name	T111
Test name
Test status
Simulation time	22656373515 ps
CPU time	203.28 seconds
Started	Mar 24 02:46:23 PM PDT 24
Finished	Mar 24 02:49:47 PM PDT 24
Peak memory	211440 kb
Host	smart-d03f398c-0ba4-4304-9900-22a4800fad5b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449927283 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.449927283
Directory	/workspace/78.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.449652587
Short name	T854
Test name
Test status
Simulation time	104309204109 ps
CPU time	74.53 seconds
Started	Mar 24 02:46:26 PM PDT 24
Finished	Mar 24 02:47:42 PM PDT 24
Peak memory	200192 kb
Host	smart-6551adc9-f6a0-4f3e-932a-52558f9d8b68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449652587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.449652587
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_stress_all_with_rand_reset.2375084994
Short name	T359
Test name
Test status
Simulation time	8907930995 ps
CPU time	374.27 seconds
Started	Mar 24 02:46:23 PM PDT 24
Finished	Mar 24 02:52:38 PM PDT 24
Peak memory	208664 kb
Host	smart-129781b1-3772-4366-b701-eaaae5d70551
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375084994 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2375084994
Directory	/workspace/79.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.3604978314
Short name	T1047
Test name
Test status
Simulation time	35799088 ps
CPU time	0.55 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:28 PM PDT 24
Peak memory	195624 kb
Host	smart-9f8ba9c4-f3bc-4afa-9249-0ae06a13ac17
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604978314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3604978314
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.2123376536
Short name	T1021
Test name
Test status
Simulation time	50073025542 ps
CPU time	28.09 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:44:04 PM PDT 24
Peak memory	200448 kb
Host	smart-0c015651-59d8-4293-8c4e-926f41ea5071
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123376536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2123376536
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.348835506
Short name	T969
Test name
Test status
Simulation time	16353737759 ps
CPU time	30.44 seconds
Started	Mar 24 02:43:25 PM PDT 24
Finished	Mar 24 02:43:56 PM PDT 24
Peak memory	199900 kb
Host	smart-157e27d6-062e-4b23-bbb6-73aaa3fa7cfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348835506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.348835506
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.3090845905
Short name	T578
Test name
Test status
Simulation time	45073492272 ps
CPU time	110.45 seconds
Started	Mar 24 02:43:31 PM PDT 24
Finished	Mar 24 02:45:21 PM PDT 24
Peak memory	200144 kb
Host	smart-9347286f-21f7-4966-bdd6-d4fcad91590f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090845905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3090845905
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.840010777
Short name	T352
Test name
Test status
Simulation time	16164403820 ps
CPU time	10.8 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 02:43:38 PM PDT 24
Peak memory	197288 kb
Host	smart-e6cf4571-2d3a-4b28-8b79-f62e57d2e798
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840010777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.840010777
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.527042965
Short name	T532
Test name
Test status
Simulation time	190301545875 ps
CPU time	419.8 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:50:38 PM PDT 24
Peak memory	200152 kb
Host	smart-bbc5cb86-7340-4e95-8cd9-af6a3e872e5d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=527042965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.527042965
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/8.uart_loopback.3296488297
Short name	T1098
Test name
Test status
Simulation time	5689317699 ps
CPU time	11.35 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:43:45 PM PDT 24
Peak memory	199924 kb
Host	smart-52d64f5e-f203-4a9b-afb3-a90bd8a92217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296488297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3296488297
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.3699257127
Short name	T57
Test name
Test status
Simulation time	254719440501 ps
CPU time	54.31 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:44:31 PM PDT 24
Peak memory	208252 kb
Host	smart-ca79a92e-d87c-4227-9b51-ff90d8aeaf51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699257127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3699257127
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.2054770727
Short name	T736
Test name
Test status
Simulation time	9093049647 ps
CPU time	361.25 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:49:37 PM PDT 24
Peak memory	200136 kb
Host	smart-4087fa07-3215-4667-bb96-4e15597e2a3c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2054770727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2054770727
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_oversample.4113355932
Short name	T440
Test name
Test status
Simulation time	4603324472 ps
CPU time	9.1 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:43:39 PM PDT 24
Peak memory	198232 kb
Host	smart-cd093a0b-2c92-476d-8e24-87cfbbd39957
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4113355932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.4113355932
Directory	/workspace/8.uart_rx_oversample/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.834807820
Short name	T1000
Test name
Test status
Simulation time	128675575398 ps
CPU time	133.14 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:45:44 PM PDT 24
Peak memory	200200 kb
Host	smart-697a878d-1691-42ee-9ae9-27441bcc76d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834807820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.834807820
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.1834069997
Short name	T556
Test name
Test status
Simulation time	2612822823 ps
CPU time	1.69 seconds
Started	Mar 24 02:43:37 PM PDT 24
Finished	Mar 24 02:43:39 PM PDT 24
Peak memory	195872 kb
Host	smart-ac34fa58-5e36-4b5c-9f0b-edced24b20ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834069997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1834069997
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.3888132579
Short name	T302
Test name
Test status
Simulation time	5566540877 ps
CPU time	3.6 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:43:39 PM PDT 24
Peak memory	199732 kb
Host	smart-3a236ed1-0145-4695-a601-b5383bce4660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888132579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3888132579
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all.2867396473
Short name	T768
Test name
Test status
Simulation time	38068279493 ps
CPU time	1521.87 seconds
Started	Mar 24 02:43:27 PM PDT 24
Finished	Mar 24 03:08:49 PM PDT 24
Peak memory	200136 kb
Host	smart-c72d0194-25ea-455f-965f-34f255b66ed1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867396473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2867396473
Directory	/workspace/8.uart_stress_all/latest

Test location	/workspace/coverage/default/8.uart_stress_all_with_rand_reset.893369639
Short name	T38
Test name
Test status
Simulation time	35019852797 ps
CPU time	130.52 seconds
Started	Mar 24 02:43:29 PM PDT 24
Finished	Mar 24 02:45:39 PM PDT 24
Peak memory	215660 kb
Host	smart-8ff822c8-3a4f-417d-839a-63c058eb8928
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893369639 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.893369639
Directory	/workspace/8.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.1490937696
Short name	T546
Test name
Test status
Simulation time	1880188324 ps
CPU time	3.18 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:43:35 PM PDT 24
Peak memory	199896 kb
Host	smart-af87ade2-9d6d-4d77-a1a5-5fa6cbaaaf0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490937696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1490937696
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.2266316514
Short name	T338
Test name
Test status
Simulation time	34220563831 ps
CPU time	54.18 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:44:22 PM PDT 24
Peak memory	200392 kb
Host	smart-38eac87e-e4ac-4159-9210-bd9631f1c0ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266316514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2266316514
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.2205570012
Short name	T321
Test name
Test status
Simulation time	60329308598 ps
CPU time	27.25 seconds
Started	Mar 24 02:46:26 PM PDT 24
Finished	Mar 24 02:46:54 PM PDT 24
Peak memory	200168 kb
Host	smart-65cae7fb-deda-4aaa-92d7-7d78ecd3f4f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205570012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2205570012
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.2738963375
Short name	T258
Test name
Test status
Simulation time	139668268668 ps
CPU time	107.47 seconds
Started	Mar 24 02:46:23 PM PDT 24
Finished	Mar 24 02:48:11 PM PDT 24
Peak memory	200168 kb
Host	smart-c9caa5fa-56a6-417f-ba13-21f55729129c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738963375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2738963375
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.2102401306
Short name	T187
Test name
Test status
Simulation time	71630360282 ps
CPU time	40.71 seconds
Started	Mar 24 02:46:24 PM PDT 24
Finished	Mar 24 02:47:05 PM PDT 24
Peak memory	200084 kb
Host	smart-ff1a0fd6-2aea-4e52-a81c-822d9ed31cfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2102401306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2102401306
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.3131167444
Short name	T189
Test name
Test status
Simulation time	22737816091 ps
CPU time	9.56 seconds
Started	Mar 24 02:46:26 PM PDT 24
Finished	Mar 24 02:46:37 PM PDT 24
Peak memory	200244 kb
Host	smart-facdd58c-e851-4ece-8f82-41ff1c1f4c1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131167444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3131167444
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.2233069820
Short name	T915
Test name
Test status
Simulation time	55859351583 ps
CPU time	149.6 seconds
Started	Mar 24 02:46:31 PM PDT 24
Finished	Mar 24 02:49:01 PM PDT 24
Peak memory	200168 kb
Host	smart-36eb90b0-d5e1-4805-9e66-6921522799b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233069820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2233069820
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_stress_all_with_rand_reset.558484966
Short name	T69
Test name
Test status
Simulation time	165981249477 ps
CPU time	519.6 seconds
Started	Mar 24 02:46:34 PM PDT 24
Finished	Mar 24 02:55:15 PM PDT 24
Peak memory	216848 kb
Host	smart-462cd7c3-224d-4259-a2ce-42e82e445c58
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558484966 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.558484966
Directory	/workspace/84.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.760537479
Short name	T495
Test name
Test status
Simulation time	48614077874 ps
CPU time	39.33 seconds
Started	Mar 24 02:46:32 PM PDT 24
Finished	Mar 24 02:47:15 PM PDT 24
Peak memory	200164 kb
Host	smart-0ed0f7f0-e15a-4fae-b2a0-ae66cfd673bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760537479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.760537479
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.2505004494
Short name	T997
Test name
Test status
Simulation time	187757637075 ps
CPU time	121.79 seconds
Started	Mar 24 02:46:33 PM PDT 24
Finished	Mar 24 02:48:38 PM PDT 24
Peak memory	200160 kb
Host	smart-580dad65-62f7-4367-98a7-e31b2d9a9ee9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505004494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2505004494
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_stress_all_with_rand_reset.1842753612
Short name	T509
Test name
Test status
Simulation time	47120624550 ps
CPU time	222.9 seconds
Started	Mar 24 02:46:29 PM PDT 24
Finished	Mar 24 02:50:13 PM PDT 24
Peak memory	216992 kb
Host	smart-08ea8395-197b-4a8e-ad37-ca93e3f04e35
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842753612 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1842753612
Directory	/workspace/86.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.3569971289
Short name	T795
Test name
Test status
Simulation time	181822192512 ps
CPU time	145.51 seconds
Started	Mar 24 02:46:32 PM PDT 24
Finished	Mar 24 02:49:01 PM PDT 24
Peak memory	200160 kb
Host	smart-d4f7b66d-cc44-491e-b502-eb5c96c11d48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569971289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3569971289
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.78380994
Short name	T911
Test name
Test status
Simulation time	142273743646 ps
CPU time	27.55 seconds
Started	Mar 24 02:46:33 PM PDT 24
Finished	Mar 24 02:47:03 PM PDT 24
Peak memory	200152 kb
Host	smart-d44e24ff-2cfb-411d-a867-c745b2f1b5a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78380994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.78380994
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/88.uart_stress_all_with_rand_reset.3530916665
Short name	T357
Test name
Test status
Simulation time	78512917829 ps
CPU time	502.53 seconds
Started	Mar 24 02:46:31 PM PDT 24
Finished	Mar 24 02:54:58 PM PDT 24
Peak memory	225008 kb
Host	smart-8d33479b-8fab-4bd7-a23a-03f8cc8a7aac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530916665 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3530916665
Directory	/workspace/88.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.3549838296
Short name	T874
Test name
Test status
Simulation time	189790883412 ps
CPU time	373.6 seconds
Started	Mar 24 02:46:30 PM PDT 24
Finished	Mar 24 02:52:45 PM PDT 24
Peak memory	200188 kb
Host	smart-60d2e387-be38-4e1a-9fdc-0b92eafa07b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549838296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3549838296
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.1925947993
Short name	T804
Test name
Test status
Simulation time	47320558 ps
CPU time	0.59 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:43:36 PM PDT 24
Peak memory	195628 kb
Host	smart-6b438821-5101-4970-a96d-3435d5cd2175
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925947993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1925947993
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.2514608536
Short name	T657
Test name
Test status
Simulation time	35675787570 ps
CPU time	33.94 seconds
Started	Mar 24 02:43:34 PM PDT 24
Finished	Mar 24 02:44:09 PM PDT 24
Peak memory	200124 kb
Host	smart-0e4a92d1-2111-4817-9024-ef3350917d89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514608536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2514608536
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.3965840749
Short name	T740
Test name
Test status
Simulation time	6836546376 ps
CPU time	11 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:43:39 PM PDT 24
Peak memory	200196 kb
Host	smart-40efbc15-a1be-4582-b89d-30aabe6a9d46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965840749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3965840749
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.3990578722
Short name	T150
Test name
Test status
Simulation time	21738526922 ps
CPU time	9.57 seconds
Started	Mar 24 02:43:33 PM PDT 24
Finished	Mar 24 02:43:42 PM PDT 24
Peak memory	200096 kb
Host	smart-f77367d9-6704-4b07-b988-bf2efc4f13a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990578722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3990578722
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_intr.2381897219
Short name	T301
Test name
Test status
Simulation time	13104443485 ps
CPU time	3.19 seconds
Started	Mar 24 02:43:32 PM PDT 24
Finished	Mar 24 02:43:35 PM PDT 24
Peak memory	199636 kb
Host	smart-5422fa92-9024-46a6-8c20-5a6cf0163c1e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381897219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2381897219
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.834947776
Short name	T570
Test name
Test status
Simulation time	204720960709 ps
CPU time	1554.92 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 03:09:31 PM PDT 24
Peak memory	200348 kb
Host	smart-a453e4f9-2926-41e9-a7eb-94f622079cca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=834947776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.834947776
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.862819743
Short name	T830
Test name
Test status
Simulation time	2985387931 ps
CPU time	1.84 seconds
Started	Mar 24 02:43:37 PM PDT 24
Finished	Mar 24 02:43:39 PM PDT 24
Peak memory	198160 kb
Host	smart-57328c46-4c9f-4e9d-9800-b895995c03ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862819743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.862819743
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.3545631601
Short name	T350
Test name
Test status
Simulation time	171135846932 ps
CPU time	101.86 seconds
Started	Mar 24 02:43:26 PM PDT 24
Finished	Mar 24 02:45:08 PM PDT 24
Peak memory	208328 kb
Host	smart-a293621d-f2f3-415a-a86a-a11bf15f3bec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545631601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3545631601
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.1401121031
Short name	T490
Test name
Test status
Simulation time	11970552841 ps
CPU time	509.72 seconds
Started	Mar 24 02:43:35 PM PDT 24
Finished	Mar 24 02:52:05 PM PDT 24
Peak memory	200088 kb
Host	smart-254c405f-f8b5-4e86-b998-d4ac74d25dba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1401121031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1401121031
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_oversample.4267374883
Short name	T377
Test name
Test status
Simulation time	2771993792 ps
CPU time	1.59 seconds
Started	Mar 24 02:43:31 PM PDT 24
Finished	Mar 24 02:43:33 PM PDT 24
Peak memory	199356 kb
Host	smart-8f69d94a-5989-4c0d-bb27-be30db14fc54
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4267374883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4267374883
Directory	/workspace/9.uart_rx_oversample/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.1392127218
Short name	T1079
Test name
Test status
Simulation time	72248847322 ps
CPU time	142.9 seconds
Started	Mar 24 02:43:24 PM PDT 24
Finished	Mar 24 02:45:47 PM PDT 24
Peak memory	200120 kb
Host	smart-4360d39c-743a-48af-9a8e-5f4ead9db750
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392127218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1392127218
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.72487877
Short name	T743
Test name
Test status
Simulation time	3112262719 ps
CPU time	1.1 seconds
Started	Mar 24 02:43:29 PM PDT 24
Finished	Mar 24 02:43:30 PM PDT 24
Peak memory	196008 kb
Host	smart-323e15d9-4c74-4e67-84fe-92440dd081fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72487877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.72487877
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.482251309
Short name	T11
Test name
Test status
Simulation time	6210944340 ps
CPU time	21.36 seconds
Started	Mar 24 02:43:30 PM PDT 24
Finished	Mar 24 02:43:51 PM PDT 24
Peak memory	199292 kb
Host	smart-cc0a1e9d-0f3e-4806-a195-a71557db2eb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482251309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.482251309
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all.2820736553
Short name	T920
Test name
Test status
Simulation time	667847948916 ps
CPU time	3291.76 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 03:38:28 PM PDT 24
Peak memory	200188 kb
Host	smart-c45ef62d-fec8-48e1-a494-68a1d0992d9c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820736553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2820736553
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.536974868
Short name	T648
Test name
Test status
Simulation time	1492207313 ps
CPU time	1.79 seconds
Started	Mar 24 02:43:36 PM PDT 24
Finished	Mar 24 02:43:38 PM PDT 24
Peak memory	198768 kb
Host	smart-37d6e9e8-d3e3-4398-ad2a-4a884137af1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536974868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.536974868
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.3654879951
Short name	T461
Test name
Test status
Simulation time	40132051320 ps
CPU time	6.1 seconds
Started	Mar 24 02:43:28 PM PDT 24
Finished	Mar 24 02:43:34 PM PDT 24
Peak memory	199912 kb
Host	smart-db8d0d8b-d870-43f4-9e36-80244f1ac870
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654879951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3654879951
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.3972197082
Short name	T551
Test name
Test status
Simulation time	53494592747 ps
CPU time	38.97 seconds
Started	Mar 24 02:46:29 PM PDT 24
Finished	Mar 24 02:47:09 PM PDT 24
Peak memory	200160 kb
Host	smart-4870ab99-e4ac-4fce-a73d-be11d2780d96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972197082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3972197082
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.1346673951
Short name	T548
Test name
Test status
Simulation time	10991090991 ps
CPU time	190.67 seconds
Started	Mar 24 02:46:33 PM PDT 24
Finished	Mar 24 02:49:46 PM PDT 24
Peak memory	216668 kb
Host	smart-0094d528-5682-47e9-82f8-378ea05b61e2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346673951 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1346673951
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.1804340496
Short name	T954
Test name
Test status
Simulation time	108478302013 ps
CPU time	157.32 seconds
Started	Mar 24 02:46:31 PM PDT 24
Finished	Mar 24 02:49:09 PM PDT 24
Peak memory	200120 kb
Host	smart-b78b7348-3c78-4c77-8699-1918cbdeb277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804340496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1804340496
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.2490812073
Short name	T473
Test name
Test status
Simulation time	80250824754 ps
CPU time	18.36 seconds
Started	Mar 24 02:46:34 PM PDT 24
Finished	Mar 24 02:46:54 PM PDT 24
Peak memory	200100 kb
Host	smart-cc051fae-56fc-4508-941d-ded1c65f8558
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490812073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2490812073
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.881499249
Short name	T139
Test name
Test status
Simulation time	195776582380 ps
CPU time	37.61 seconds
Started	Mar 24 02:46:35 PM PDT 24
Finished	Mar 24 02:47:13 PM PDT 24
Peak memory	200128 kb
Host	smart-6b9cb4be-56eb-413b-aa7c-09f6027d1c01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881499249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.881499249
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.1512559075
Short name	T205
Test name
Test status
Simulation time	101096693616 ps
CPU time	161.67 seconds
Started	Mar 24 02:46:35 PM PDT 24
Finished	Mar 24 02:49:17 PM PDT 24
Peak memory	200164 kb
Host	smart-4b7ce9ab-e624-4e7c-945d-d4f74650703d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1512559075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1512559075
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.1619414393
Short name	T676
Test name
Test status
Simulation time	92675362474 ps
CPU time	128.74 seconds
Started	Mar 24 02:46:32 PM PDT 24
Finished	Mar 24 02:48:44 PM PDT 24
Peak memory	200184 kb
Host	smart-399e5f09-31b2-43d8-bb07-bc7f5debdb08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619414393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1619414393
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.3192784582
Short name	T618
Test name
Test status
Simulation time	187658190007 ps
CPU time	83.28 seconds
Started	Mar 24 02:46:34 PM PDT 24
Finished	Mar 24 02:47:59 PM PDT 24
Peak memory	200204 kb
Host	smart-603153aa-63de-4a9d-a9df-0ef7daa65ba3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192784582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3192784582
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.3694786843
Short name	T5
Test name
Test status
Simulation time	57376871633 ps
CPU time	37.65 seconds
Started	Mar 24 02:46:34 PM PDT 24
Finished	Mar 24 02:47:13 PM PDT 24
Peak memory	200028 kb
Host	smart-3cdd644c-a983-4363-9bbd-e9d887520f4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694786843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3694786843
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.1119295624
Short name	T446
Test name
Test status
Simulation time	24082223929 ps
CPU time	39 seconds
Started	Mar 24 02:46:38 PM PDT 24
Finished	Mar 24 02:47:18 PM PDT 24
Peak memory	200116 kb
Host	smart-b92dcd6b-eafd-45e3-9a7c-13a69b567006
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119295624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1119295624
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_stress_all_with_rand_reset.3785266215
Short name	T1074
Test name
Test status
Simulation time	71372052755 ps
CPU time	760.74 seconds
Started	Mar 24 02:46:35 PM PDT 24
Finished	Mar 24 02:59:16 PM PDT 24
Peak memory	226216 kb
Host	smart-dd2e568b-3de6-45f3-a745-9ce8c3a84c48
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785266215 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3785266215
Directory	/workspace/98.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.2680540993
Short name	T6
Test name
Test status
Simulation time	9550906599 ps
CPU time	16.9 seconds
Started	Mar 24 02:46:32 PM PDT 24
Finished	Mar 24 02:46:53 PM PDT 24
Peak memory	200148 kb
Host	smart-696b3ae5-677d-49f7-8ea2-8ffe21d39bcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680540993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2680540993
Directory	/workspace/99.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_stress_all_with_rand_reset.3302845769
Short name	T115
Test name
Test status
Simulation time	445948829809 ps
CPU time	660.37 seconds
Started	Mar 24 02:46:39 PM PDT 24
Finished	Mar 24 02:57:39 PM PDT 24
Peak memory	225048 kb
Host	smart-8bd66492-1bf4-4f19-9efb-38c9926d3665
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302845769 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3302845769
Directory	/workspace/99.uart_stress_all_with_rand_reset/latest

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