Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70407039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19628816

1

T1

27

T2

187

T3

74

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86924545	1			T1	1045		T2	2293		T3	1733
values[0x0]	1480983	1			T1	24		T2	103		T3	104
values[0x1]	1630327	1			T1	30		T2	116		T3	87

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48882297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41153558

1

T1

367

T2

916

T3

644

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	334704	1			T1	5		T3	5		T4	34
valid_sources[0x01]	450631	1			T1	5		T3	14		T4	17
valid_sources[0x02]	363589	1			T1	7		T3	8		T4	29
valid_sources[0x03]	348248	1			T1	4		T2	1		T3	4
valid_sources[0x04]	461726	1			T1	2		T3	11		T4	17
valid_sources[0x05]	314396	1			T1	5		T3	9		T4	17
valid_sources[0x06]	362850	1			T1	7		T3	8		T4	21
valid_sources[0x07]	318835	1			T1	9		T3	4		T4	42
valid_sources[0x08]	393365	1			T1	7		T3	13		T4	28
valid_sources[0x09]	474806	1			T1	3		T3	8		T4	22
valid_sources[0x0a]	319558	1			T1	4		T3	7		T4	27
valid_sources[0x0b]	333873	1			T1	6		T3	10		T4	27
valid_sources[0x0c]	321832	1			T1	6		T3	12		T4	29
valid_sources[0x0d]	341217	1			T1	6		T3	8		T4	17
valid_sources[0x0e]	308829	1			T1	2		T3	6		T4	29
valid_sources[0x0f]	312839	1			T1	1		T3	10		T4	18
valid_sources[0x10]	321626	1			T1	9		T3	7		T4	21
valid_sources[0x11]	331692	1			T1	5		T3	14		T4	42
valid_sources[0x12]	333763	1			T1	2		T3	5		T4	38
valid_sources[0x13]	330273	1			T1	5		T3	4		T4	19
valid_sources[0x14]	385868	1			T1	3		T3	6		T4	27
valid_sources[0x15]	355423	1			T1	2		T3	9		T4	24
valid_sources[0x16]	323227	1			T1	10		T3	5		T4	23
valid_sources[0x17]	336186	1			T1	4		T3	9		T4	26
valid_sources[0x18]	331338	1			T1	1		T3	4		T4	21
valid_sources[0x19]	324338	1			T1	6		T3	6		T4	29
valid_sources[0x1a]	379732	1			T1	9		T3	8		T4	23
valid_sources[0x1b]	322847	1			T1	3		T3	9		T4	23
valid_sources[0x1c]	341609	1			T1	1		T3	3		T4	34
valid_sources[0x1d]	335949	1			T1	6		T3	9		T4	30
valid_sources[0x1e]	368244	1			T1	4		T3	9		T4	26
valid_sources[0x1f]	334496	1			T1	8		T3	8		T4	20
valid_sources[0x20]	347940	1			T1	10		T3	5		T4	18
valid_sources[0x21]	453538	1			T1	7		T3	2		T4	35
valid_sources[0x22]	335906	1			T1	6		T3	9		T4	32
valid_sources[0x23]	433713	1			T1	5		T3	9		T4	20
valid_sources[0x24]	319144	1			T1	2		T3	11		T4	18
valid_sources[0x25]	342379	1			T1	3		T3	8		T4	35
valid_sources[0x26]	323315	1			T1	4		T3	9		T4	34
valid_sources[0x27]	366228	1			T1	3		T3	11		T4	37
valid_sources[0x28]	393770	1			T1	6		T3	3		T4	18
valid_sources[0x29]	347714	1			T1	2		T3	8		T4	28
valid_sources[0x2a]	379728	1			T1	3		T3	7		T4	19
valid_sources[0x2b]	368818	1			T1	2		T3	6		T4	24
valid_sources[0x2c]	380000	1			T1	3		T3	3		T4	26
valid_sources[0x2d]	418827	1			T1	3		T3	5		T4	25
valid_sources[0x2e]	483581	1			T1	5		T3	11		T4	28
valid_sources[0x2f]	322249	1			T1	8		T3	10		T4	28
valid_sources[0x30]	461391	1			T1	1		T3	9		T4	29
valid_sources[0x31]	316004	1			T1	5		T3	7		T4	35
valid_sources[0x32]	348744	1			T1	4		T3	2		T4	36
valid_sources[0x33]	371440	1			T1	3		T2	1		T3	7
valid_sources[0x34]	346734	1			T1	5		T3	5		T4	21
valid_sources[0x35]	331029	1			T1	6		T3	7		T4	24
valid_sources[0x36]	364089	1			T1	5		T3	15		T4	25
valid_sources[0x37]	315360	1			T1	5		T3	10		T4	28
valid_sources[0x38]	332944	1			T1	4		T3	8		T4	29
valid_sources[0x39]	337942	1			T1	7		T3	9		T4	33
valid_sources[0x3a]	327073	1			T1	3		T3	11		T4	22
valid_sources[0x3b]	328586	1			T1	4		T3	6		T4	28
valid_sources[0x3c]	311917	1			T1	4		T3	6		T4	25
valid_sources[0x3d]	376969	1			T1	2		T3	8		T4	25
valid_sources[0x3e]	388578	1			T1	2		T3	8		T4	25
valid_sources[0x3f]	308034	1			T1	3		T3	8		T4	28
valid_sources[0x40]	317461	1			T1	6		T3	8		T4	33
valid_sources[0x41]	362595	1			T1	4		T3	14		T4	35
valid_sources[0x42]	350761	1			T1	4		T3	8		T4	30
valid_sources[0x43]	340497	1			T1	6		T3	7		T4	25
valid_sources[0x44]	458876	1			T1	10		T3	8		T4	30
valid_sources[0x45]	355041	1			T1	6		T3	10		T4	25
valid_sources[0x46]	310202	1			T1	3		T3	6		T4	20
valid_sources[0x47]	372526	1			T1	6		T3	11		T4	29
valid_sources[0x48]	303620	1			T1	8		T3	10		T4	23
valid_sources[0x49]	311560	1			T1	6		T3	6		T4	26
valid_sources[0x4a]	336071	1			T1	5		T3	5		T4	22
valid_sources[0x4b]	368119	1			T1	6		T3	4		T4	32
valid_sources[0x4c]	341210	1			T1	3		T3	4		T4	29
valid_sources[0x4d]	376495	1			T1	4		T3	5		T4	19
valid_sources[0x4e]	354787	1			T1	3		T3	7		T4	17
valid_sources[0x4f]	321794	1			T1	4		T3	8		T4	23
valid_sources[0x50]	320804	1			T1	1		T3	8		T4	23
valid_sources[0x51]	380721	1			T1	7		T3	4		T4	24
valid_sources[0x52]	512355	1			T1	1		T2	2		T3	9
valid_sources[0x53]	328499	1			T1	3		T2	1139		T3	4
valid_sources[0x54]	375036	1			T1	5		T3	7		T4	25
valid_sources[0x55]	413766	1			T1	6		T3	8		T4	27
valid_sources[0x56]	369636	1			T1	2		T3	10		T4	20
valid_sources[0x57]	329981	1			T1	5		T3	8		T4	23
valid_sources[0x58]	316113	1			T1	6		T3	5		T4	30
valid_sources[0x59]	382458	1			T1	3		T3	8		T4	26
valid_sources[0x5a]	361298	1			T1	5		T3	8		T4	39
valid_sources[0x5b]	395360	1			T1	3		T3	1		T4	37
valid_sources[0x5c]	324118	1			T1	5		T3	6		T4	32
valid_sources[0x5d]	321434	1			T1	2		T3	8		T4	23
valid_sources[0x5e]	321590	1			T1	7		T3	4		T4	30
valid_sources[0x5f]	332872	1			T1	2		T3	4		T4	29
valid_sources[0x60]	379037	1			T1	7		T3	6		T4	42
valid_sources[0x61]	317714	1			T1	3		T3	6		T4	31
valid_sources[0x62]	352800	1			T1	5		T3	5		T4	14
valid_sources[0x63]	423143	1			T1	9		T3	1		T4	29
valid_sources[0x64]	342517	1			T1	5		T3	5		T4	30
valid_sources[0x65]	490171	1			T1	3		T3	3		T4	26
valid_sources[0x66]	363337	1			T3	11		T4	25		T5	3235
valid_sources[0x67]	313332	1			T1	2		T3	6		T4	25
valid_sources[0x68]	337290	1			T1	7		T3	3		T4	15
valid_sources[0x69]	344936	1			T1	2		T3	2		T4	39
valid_sources[0x6a]	340889	1			T1	2		T3	7		T4	20
valid_sources[0x6b]	333565	1			T1	2		T2	1		T3	10
valid_sources[0x6c]	350113	1			T1	6		T3	11		T4	26
valid_sources[0x6d]	354253	1			T1	5		T3	14		T4	24
valid_sources[0x6e]	337840	1			T1	3		T3	12		T4	16
valid_sources[0x6f]	369407	1			T1	9		T3	11		T4	37
valid_sources[0x70]	334665	1			T1	4		T3	6		T4	24
valid_sources[0x71]	316851	1			T1	2		T3	4		T4	18
valid_sources[0x72]	316407	1			T1	3		T3	8		T4	18
valid_sources[0x73]	351617	1			T1	5		T3	6		T4	33
valid_sources[0x74]	371286	1			T1	5		T3	6		T4	31
valid_sources[0x75]	352725	1			T1	8		T3	5		T4	38
valid_sources[0x76]	316075	1			T1	6		T3	9		T4	25
valid_sources[0x77]	347746	1			T1	4		T3	8		T4	30
valid_sources[0x78]	339419	1			T1	3		T3	6		T4	35
valid_sources[0x79]	363664	1			T1	5		T3	7		T4	21
valid_sources[0x7a]	370693	1			T1	4		T3	6		T4	21
valid_sources[0x7b]	320256	1			T1	4		T3	7		T4	19
valid_sources[0x7c]	322133	1			T1	3		T3	7		T4	24
valid_sources[0x7d]	332360	1			T1	5		T3	4		T4	27
valid_sources[0x7e]	354595	1			T1	4		T3	8		T4	22
valid_sources[0x7f]	348545	1			T1	2		T3	9		T4	25
valid_sources[0x80]	347542	1			T1	6		T3	3		T4	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17124589

1

T1

10

T2

133

T3

22

values[0x0]

all_enables

biggest_size

1275475

1

T1

12

T2

31

T3

32

values[0x1]

all_enables

biggest_size

1228752

1

T1

5

T2

23

T3

20