Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3934392	0	0
ctrl_rd_A	2147483647	90547	0	0
intr_enable_rd_A	2147483647	80215	0	0
ovrd_rd_A	2147483647	88392	0	0
timeout_ctrl_rd_A	2147483647	88931	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3934392	0	0
T21	249707	99926	0	0
T25	165230	0	0	0
T30	0	77049	0	0
T31	0	261070	0	0
T39	0	49870	0	0
T40	0	202644	0	0
T41	0	237874	0	0
T42	0	120398	0	0
T43	0	71210	0	0
T44	0	64181	0	0
T45	0	210247	0	0
T46	326940	0	0	0
T47	1120	0	0	0
T48	278683	0	0	0
T49	116477	0	0	0
T50	235960	0	0	0
T51	324466	0	0	0
T52	119010	0	0	0
T53	83675	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90547	0	0
T39	185995	5444	0	0
T62	0	16186	0	0
T101	275542	0	0	0
T122	0	9486	0	0
T123	0	2155	0	0
T124	0	7731	0	0
T125	0	5487	0	0
T126	0	3643	0	0
T127	0	3393	0	0
T128	0	2833	0	0
T129	0	11590	0	0
T130	177776	0	0	0
T131	730998	0	0	0
T132	116773	0	0	0
T133	328016	0	0	0
T134	935727	0	0	0
T135	183041	0	0	0
T136	931413	0	0	0
T137	178575	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80215	0	0
T17	158886	30	0	0
T18	328716	0	0	0
T39	0	4775	0	0
T62	0	13650	0	0
T122	0	8704	0	0
T123	0	2087	0	0
T124	0	6618	0	0
T125	0	4648	0	0
T138	0	9	0	0
T139	0	21	0	0
T140	0	22	0	0
T141	84139	0	0	0
T142	118125	0	0	0
T143	466295	0	0	0
T144	106865	0	0	0
T145	767108	0	0	0
T146	553195	0	0	0
T147	18401	0	0	0
T148	153782	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	88392	0	0
T39	185995	5326	0	0
T62	0	15585	0	0
T101	275542	0	0	0
T122	0	9235	0	0
T123	0	2632	0	0
T124	0	7829	0	0
T125	0	5705	0	0
T126	0	3373	0	0
T127	0	3526	0	0
T128	0	2978	0	0
T129	0	12169	0	0
T130	177776	0	0	0
T131	730998	0	0	0
T132	116773	0	0	0
T133	328016	0	0	0
T134	935727	0	0	0
T135	183041	0	0	0
T136	931413	0	0	0
T137	178575	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	88931	0	0
T39	185995	5309	0	0
T62	0	15937	0	0
T101	275542	0	0	0
T122	0	9767	0	0
T123	0	2467	0	0
T124	0	7609	0	0
T125	0	5467	0	0
T126	0	3515	0	0
T127	0	3425	0	0
T128	0	2860	0	0
T129	0	12069	0	0
T130	177776	0	0	0
T131	730998	0	0	0
T132	116773	0	0	0
T133	328016	0	0	0
T134	935727	0	0	0
T135	183041	0	0	0
T136	931413	0	0	0
T137	178575	0	0	0