Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.27 97.95 100.00 98.80 100.00 99.52


Total test records in report: 1256
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T1051 /workspace/coverage/default/2.uart_tx_ovrd.541947756 Mar 26 02:19:28 PM PDT 24 Mar 26 02:19:30 PM PDT 24 787051511 ps
T1052 /workspace/coverage/default/0.uart_loopback.1394759961 Mar 26 02:19:17 PM PDT 24 Mar 26 02:19:18 PM PDT 24 58723579 ps
T1053 /workspace/coverage/default/115.uart_fifo_reset.1218638734 Mar 26 02:28:29 PM PDT 24 Mar 26 02:28:38 PM PDT 24 91059990525 ps
T1054 /workspace/coverage/default/48.uart_tx_ovrd.2617205300 Mar 26 02:26:40 PM PDT 24 Mar 26 02:26:46 PM PDT 24 1222428958 ps
T272 /workspace/coverage/default/177.uart_fifo_reset.1098332765 Mar 26 02:29:18 PM PDT 24 Mar 26 02:29:40 PM PDT 24 17264226028 ps
T1055 /workspace/coverage/default/21.uart_perf.1984060774 Mar 26 02:21:55 PM PDT 24 Mar 26 02:25:13 PM PDT 24 4069135429 ps
T1056 /workspace/coverage/default/44.uart_rx_parity_err.2479448529 Mar 26 02:26:05 PM PDT 24 Mar 26 02:28:11 PM PDT 24 180120560319 ps
T1057 /workspace/coverage/default/43.uart_noise_filter.1783526434 Mar 26 02:26:02 PM PDT 24 Mar 26 02:27:50 PM PDT 24 60494725986 ps
T1058 /workspace/coverage/default/24.uart_loopback.1493986964 Mar 26 02:22:28 PM PDT 24 Mar 26 02:22:31 PM PDT 24 4258503030 ps
T1059 /workspace/coverage/default/29.uart_stress_all.1764685095 Mar 26 02:23:17 PM PDT 24 Mar 26 02:24:58 PM PDT 24 308420219068 ps
T1060 /workspace/coverage/default/23.uart_rx_start_bit_filter.3196317309 Mar 26 02:22:16 PM PDT 24 Mar 26 02:22:18 PM PDT 24 1884714857 ps
T1061 /workspace/coverage/default/7.uart_long_xfer_wo_dly.500528616 Mar 26 02:20:24 PM PDT 24 Mar 26 02:35:03 PM PDT 24 88898682308 ps
T1062 /workspace/coverage/default/39.uart_long_xfer_wo_dly.1161745113 Mar 26 02:25:09 PM PDT 24 Mar 26 02:28:13 PM PDT 24 127262966138 ps
T1063 /workspace/coverage/default/47.uart_rx_parity_err.3689839339 Mar 26 02:26:30 PM PDT 24 Mar 26 02:27:42 PM PDT 24 36218762089 ps
T1064 /workspace/coverage/default/203.uart_fifo_reset.2036828926 Mar 26 02:29:34 PM PDT 24 Mar 26 02:31:42 PM PDT 24 74368586090 ps
T70 /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3539399831 Mar 26 02:27:32 PM PDT 24 Mar 26 02:40:23 PM PDT 24 233657027619 ps
T82 /workspace/coverage/default/12.uart_long_xfer_wo_dly.2147854645 Mar 26 02:20:59 PM PDT 24 Mar 26 02:27:20 PM PDT 24 86091062780 ps
T83 /workspace/coverage/default/29.uart_noise_filter.3906558233 Mar 26 02:23:14 PM PDT 24 Mar 26 02:24:27 PM PDT 24 342944137217 ps
T84 /workspace/coverage/default/265.uart_fifo_reset.1232756454 Mar 26 02:30:19 PM PDT 24 Mar 26 02:30:48 PM PDT 24 52920631804 ps
T85 /workspace/coverage/default/38.uart_alert_test.64445556 Mar 26 02:25:01 PM PDT 24 Mar 26 02:25:03 PM PDT 24 33746366 ps
T86 /workspace/coverage/default/32.uart_tx_ovrd.2630890339 Mar 26 02:23:43 PM PDT 24 Mar 26 02:23:46 PM PDT 24 533482967 ps
T87 /workspace/coverage/default/36.uart_smoke.378153083 Mar 26 02:24:28 PM PDT 24 Mar 26 02:24:30 PM PDT 24 296320990 ps
T88 /workspace/coverage/default/14.uart_intr.3637392688 Mar 26 02:20:59 PM PDT 24 Mar 26 02:21:26 PM PDT 24 40713109144 ps
T89 /workspace/coverage/default/9.uart_fifo_reset.1066027723 Mar 26 02:20:24 PM PDT 24 Mar 26 02:20:41 PM PDT 24 8840803404 ps
T90 /workspace/coverage/default/4.uart_noise_filter.2179129030 Mar 26 02:19:44 PM PDT 24 Mar 26 02:20:21 PM PDT 24 82106916774 ps
T1065 /workspace/coverage/default/46.uart_noise_filter.1893235653 Mar 26 02:26:22 PM PDT 24 Mar 26 02:26:39 PM PDT 24 10391950367 ps
T1066 /workspace/coverage/default/114.uart_fifo_reset.1967365473 Mar 26 02:28:27 PM PDT 24 Mar 26 02:29:08 PM PDT 24 69294770105 ps
T1067 /workspace/coverage/default/19.uart_loopback.1065197609 Mar 26 02:21:43 PM PDT 24 Mar 26 02:21:50 PM PDT 24 3045036267 ps
T1068 /workspace/coverage/default/207.uart_fifo_reset.1463349758 Mar 26 02:29:33 PM PDT 24 Mar 26 02:29:55 PM PDT 24 44999428021 ps
T353 /workspace/coverage/default/39.uart_stress_all_with_rand_reset.641418494 Mar 26 02:25:19 PM PDT 24 Mar 26 02:33:17 PM PDT 24 109694174253 ps
T1069 /workspace/coverage/default/31.uart_loopback.2455142725 Mar 26 02:23:31 PM PDT 24 Mar 26 02:23:51 PM PDT 24 10084344203 ps
T1070 /workspace/coverage/default/20.uart_stress_all.4201391198 Mar 26 02:21:45 PM PDT 24 Mar 26 02:33:27 PM PDT 24 288811064522 ps
T1071 /workspace/coverage/default/21.uart_smoke.2271683826 Mar 26 02:21:46 PM PDT 24 Mar 26 02:21:47 PM PDT 24 455306285 ps
T1072 /workspace/coverage/default/35.uart_tx_rx.4043689874 Mar 26 02:24:11 PM PDT 24 Mar 26 02:24:48 PM PDT 24 89682019041 ps
T1073 /workspace/coverage/default/16.uart_tx_rx.2505707674 Mar 26 02:21:09 PM PDT 24 Mar 26 02:21:57 PM PDT 24 32487373863 ps
T1074 /workspace/coverage/default/71.uart_fifo_reset.3413424048 Mar 26 02:27:21 PM PDT 24 Mar 26 02:27:48 PM PDT 24 59420371960 ps
T241 /workspace/coverage/default/69.uart_fifo_reset.1602792420 Mar 26 02:27:22 PM PDT 24 Mar 26 02:27:42 PM PDT 24 41632114925 ps
T1075 /workspace/coverage/default/43.uart_smoke.1451679249 Mar 26 02:25:47 PM PDT 24 Mar 26 02:25:49 PM PDT 24 462538210 ps
T1076 /workspace/coverage/default/34.uart_loopback.3329405326 Mar 26 02:24:12 PM PDT 24 Mar 26 02:24:13 PM PDT 24 80691453 ps
T1077 /workspace/coverage/default/34.uart_stress_all.3327715664 Mar 26 02:24:11 PM PDT 24 Mar 26 02:28:23 PM PDT 24 273283734716 ps
T1078 /workspace/coverage/default/47.uart_alert_test.2034926720 Mar 26 02:26:30 PM PDT 24 Mar 26 02:26:31 PM PDT 24 41156216 ps
T1079 /workspace/coverage/default/11.uart_fifo_full.3816403438 Mar 26 02:20:42 PM PDT 24 Mar 26 02:21:19 PM PDT 24 30182225817 ps
T1080 /workspace/coverage/default/91.uart_fifo_reset.9299006 Mar 26 02:27:51 PM PDT 24 Mar 26 02:28:46 PM PDT 24 33363753968 ps
T1081 /workspace/coverage/default/31.uart_perf.65244189 Mar 26 02:23:30 PM PDT 24 Mar 26 02:31:17 PM PDT 24 22936881614 ps
T1082 /workspace/coverage/default/12.uart_perf.1231434109 Mar 26 02:20:55 PM PDT 24 Mar 26 02:29:03 PM PDT 24 12914485062 ps
T1083 /workspace/coverage/default/136.uart_fifo_reset.3116400989 Mar 26 02:28:35 PM PDT 24 Mar 26 02:29:59 PM PDT 24 219378901290 ps
T1084 /workspace/coverage/default/22.uart_intr.1256626220 Mar 26 02:21:54 PM PDT 24 Mar 26 02:26:52 PM PDT 24 186153174196 ps
T260 /workspace/coverage/default/48.uart_fifo_reset.3009234117 Mar 26 02:26:40 PM PDT 24 Mar 26 02:27:23 PM PDT 24 100331311183 ps
T1085 /workspace/coverage/default/28.uart_rx_start_bit_filter.2859657703 Mar 26 02:23:02 PM PDT 24 Mar 26 02:23:04 PM PDT 24 1502935727 ps
T1086 /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1197328847 Mar 26 02:27:22 PM PDT 24 Mar 26 02:32:56 PM PDT 24 158290885987 ps
T1087 /workspace/coverage/default/22.uart_long_xfer_wo_dly.2255506516 Mar 26 02:22:11 PM PDT 24 Mar 26 02:24:44 PM PDT 24 235433412884 ps
T1088 /workspace/coverage/default/32.uart_rx_parity_err.3871087278 Mar 26 02:23:43 PM PDT 24 Mar 26 02:23:58 PM PDT 24 25096392636 ps
T1089 /workspace/coverage/default/116.uart_fifo_reset.3493021663 Mar 26 02:28:28 PM PDT 24 Mar 26 02:30:37 PM PDT 24 101797026907 ps
T1090 /workspace/coverage/default/213.uart_fifo_reset.468175858 Mar 26 02:29:44 PM PDT 24 Mar 26 02:29:58 PM PDT 24 16657515497 ps
T1091 /workspace/coverage/default/21.uart_fifo_overflow.4081353573 Mar 26 02:21:49 PM PDT 24 Mar 26 02:24:29 PM PDT 24 83053203267 ps
T1092 /workspace/coverage/default/41.uart_perf.3431552800 Mar 26 02:25:37 PM PDT 24 Mar 26 02:29:57 PM PDT 24 22011747111 ps
T1093 /workspace/coverage/default/29.uart_rx_oversample.59606887 Mar 26 02:23:13 PM PDT 24 Mar 26 02:23:38 PM PDT 24 3669464860 ps
T1094 /workspace/coverage/default/296.uart_fifo_reset.2771403512 Mar 26 02:30:44 PM PDT 24 Mar 26 02:31:23 PM PDT 24 43795592840 ps
T1095 /workspace/coverage/default/38.uart_perf.1299199736 Mar 26 02:25:02 PM PDT 24 Mar 26 02:40:34 PM PDT 24 21631453684 ps
T1096 /workspace/coverage/default/1.uart_loopback.1957468860 Mar 26 02:19:26 PM PDT 24 Mar 26 02:19:32 PM PDT 24 2997847695 ps
T1097 /workspace/coverage/default/18.uart_alert_test.1717723542 Mar 26 02:21:34 PM PDT 24 Mar 26 02:21:35 PM PDT 24 44808765 ps
T1098 /workspace/coverage/default/187.uart_fifo_reset.1913943539 Mar 26 02:29:27 PM PDT 24 Mar 26 02:34:08 PM PDT 24 115793653355 ps
T1099 /workspace/coverage/default/21.uart_stress_all.276903688 Mar 26 02:21:57 PM PDT 24 Mar 26 02:24:01 PM PDT 24 70812671504 ps
T1100 /workspace/coverage/default/38.uart_rx_oversample.2034183645 Mar 26 02:25:07 PM PDT 24 Mar 26 02:25:18 PM PDT 24 2951882269 ps
T1101 /workspace/coverage/default/31.uart_fifo_reset.45652087 Mar 26 02:23:34 PM PDT 24 Mar 26 02:23:59 PM PDT 24 43683990301 ps
T1102 /workspace/coverage/default/40.uart_rx_oversample.2334718867 Mar 26 02:25:27 PM PDT 24 Mar 26 02:26:21 PM PDT 24 6154482968 ps
T1103 /workspace/coverage/default/17.uart_long_xfer_wo_dly.3784882687 Mar 26 02:21:22 PM PDT 24 Mar 26 02:25:34 PM PDT 24 82135646256 ps
T1104 /workspace/coverage/default/11.uart_perf.185640280 Mar 26 02:20:43 PM PDT 24 Mar 26 02:22:23 PM PDT 24 18062791366 ps
T1105 /workspace/coverage/default/1.uart_perf.2218009824 Mar 26 02:19:30 PM PDT 24 Mar 26 02:21:21 PM PDT 24 14658727483 ps
T1106 /workspace/coverage/default/33.uart_alert_test.1341651935 Mar 26 02:24:06 PM PDT 24 Mar 26 02:24:06 PM PDT 24 20500051 ps
T1107 /workspace/coverage/default/68.uart_fifo_reset.2051187123 Mar 26 02:27:21 PM PDT 24 Mar 26 02:28:06 PM PDT 24 63082249167 ps
T1108 /workspace/coverage/default/6.uart_long_xfer_wo_dly.972193528 Mar 26 02:20:11 PM PDT 24 Mar 26 02:24:47 PM PDT 24 247919542603 ps
T1109 /workspace/coverage/default/19.uart_rx_oversample.470550250 Mar 26 02:21:46 PM PDT 24 Mar 26 02:21:51 PM PDT 24 2877810678 ps
T1110 /workspace/coverage/default/31.uart_tx_rx.1638022862 Mar 26 02:23:34 PM PDT 24 Mar 26 02:23:48 PM PDT 24 29555733671 ps
T1111 /workspace/coverage/default/22.uart_tx_rx.1123051229 Mar 26 02:21:55 PM PDT 24 Mar 26 02:24:13 PM PDT 24 197960837916 ps
T1112 /workspace/coverage/default/26.uart_rx_start_bit_filter.134989202 Mar 26 02:22:39 PM PDT 24 Mar 26 02:22:41 PM PDT 24 3275592555 ps
T1113 /workspace/coverage/default/224.uart_fifo_reset.3986935443 Mar 26 02:29:53 PM PDT 24 Mar 26 02:30:22 PM PDT 24 16384566583 ps
T1114 /workspace/coverage/default/10.uart_noise_filter.1625210039 Mar 26 02:20:41 PM PDT 24 Mar 26 02:21:49 PM PDT 24 48423734998 ps
T1115 /workspace/coverage/default/158.uart_fifo_reset.2270462715 Mar 26 02:28:56 PM PDT 24 Mar 26 02:29:19 PM PDT 24 52541633361 ps
T1116 /workspace/coverage/default/4.uart_rx_oversample.3106742479 Mar 26 02:19:43 PM PDT 24 Mar 26 02:19:57 PM PDT 24 6644641830 ps
T1117 /workspace/coverage/default/257.uart_fifo_reset.3870320129 Mar 26 02:30:18 PM PDT 24 Mar 26 02:31:37 PM PDT 24 46143876309 ps
T1118 /workspace/coverage/default/13.uart_rx_oversample.240353125 Mar 26 02:20:55 PM PDT 24 Mar 26 02:21:08 PM PDT 24 5794326986 ps
T1119 /workspace/coverage/default/11.uart_rx_oversample.1408515537 Mar 26 02:20:42 PM PDT 24 Mar 26 02:21:45 PM PDT 24 7245428409 ps
T1120 /workspace/coverage/default/22.uart_fifo_overflow.4166370443 Mar 26 02:21:57 PM PDT 24 Mar 26 02:22:45 PM PDT 24 115883836681 ps
T1121 /workspace/coverage/default/194.uart_fifo_reset.2892310290 Mar 26 02:29:25 PM PDT 24 Mar 26 02:29:56 PM PDT 24 14906343251 ps
T115 /workspace/coverage/default/1.uart_sec_cm.139263223 Mar 26 02:19:29 PM PDT 24 Mar 26 02:19:30 PM PDT 24 165774836 ps
T1122 /workspace/coverage/default/8.uart_noise_filter.2325267607 Mar 26 02:20:26 PM PDT 24 Mar 26 02:20:43 PM PDT 24 38688726433 ps
T1123 /workspace/coverage/default/95.uart_fifo_reset.1899461371 Mar 26 02:28:00 PM PDT 24 Mar 26 02:28:22 PM PDT 24 42989719745 ps
T1124 /workspace/coverage/default/37.uart_fifo_full.352555936 Mar 26 02:24:52 PM PDT 24 Mar 26 02:25:41 PM PDT 24 41751868749 ps
T250 /workspace/coverage/default/92.uart_fifo_reset.3356561959 Mar 26 02:27:53 PM PDT 24 Mar 26 02:29:11 PM PDT 24 41236992547 ps
T1125 /workspace/coverage/default/45.uart_fifo_overflow.2323612418 Mar 26 02:26:04 PM PDT 24 Mar 26 02:28:32 PM PDT 24 91798879392 ps
T92 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1869101192 Mar 26 12:40:05 PM PDT 24 Mar 26 12:40:05 PM PDT 24 38137253 ps
T1126 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3734194913 Mar 26 12:39:59 PM PDT 24 Mar 26 12:40:02 PM PDT 24 126836116 ps
T93 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.974988245 Mar 26 12:39:56 PM PDT 24 Mar 26 12:39:57 PM PDT 24 13678234 ps
T1127 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2829605668 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:59 PM PDT 24 86529641 ps
T71 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1453850105 Mar 26 12:39:45 PM PDT 24 Mar 26 12:39:46 PM PDT 24 18687325 ps
T94 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3923114436 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 11291645 ps
T1128 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2265623644 Mar 26 12:40:09 PM PDT 24 Mar 26 12:40:10 PM PDT 24 279108639 ps
T102 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.947702787 Mar 26 12:40:00 PM PDT 24 Mar 26 12:40:01 PM PDT 24 417910835 ps
T1129 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1022289745 Mar 26 12:39:55 PM PDT 24 Mar 26 12:39:56 PM PDT 24 25292774 ps
T95 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4192155060 Mar 26 12:40:01 PM PDT 24 Mar 26 12:40:02 PM PDT 24 31420022 ps
T1130 /workspace/coverage/cover_reg_top/17.uart_intr_test.2965149760 Mar 26 12:40:30 PM PDT 24 Mar 26 12:40:31 PM PDT 24 47511382 ps
T1131 /workspace/coverage/cover_reg_top/27.uart_intr_test.3252412394 Mar 26 12:40:46 PM PDT 24 Mar 26 12:40:47 PM PDT 24 39273377 ps
T103 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1812538366 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:59 PM PDT 24 81704575 ps
T1132 /workspace/coverage/cover_reg_top/36.uart_intr_test.1516996791 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 42492103 ps
T1133 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2939990601 Mar 26 12:40:12 PM PDT 24 Mar 26 12:40:14 PM PDT 24 89642499 ps
T1134 /workspace/coverage/cover_reg_top/11.uart_intr_test.3277259623 Mar 26 12:39:55 PM PDT 24 Mar 26 12:39:56 PM PDT 24 65091057 ps
T96 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.858430248 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 17350406 ps
T104 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3966270126 Mar 26 12:39:53 PM PDT 24 Mar 26 12:39:55 PM PDT 24 232696580 ps
T97 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1034360011 Mar 26 12:39:50 PM PDT 24 Mar 26 12:39:51 PM PDT 24 16234380 ps
T1135 /workspace/coverage/cover_reg_top/8.uart_intr_test.568767211 Mar 26 12:40:00 PM PDT 24 Mar 26 12:40:01 PM PDT 24 26228210 ps
T1136 /workspace/coverage/cover_reg_top/42.uart_intr_test.2545407238 Mar 26 12:40:17 PM PDT 24 Mar 26 12:40:17 PM PDT 24 23438667 ps
T1137 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4000394911 Mar 26 12:39:46 PM PDT 24 Mar 26 12:39:47 PM PDT 24 105967270 ps
T1138 /workspace/coverage/cover_reg_top/16.uart_intr_test.986713274 Mar 26 12:40:13 PM PDT 24 Mar 26 12:40:14 PM PDT 24 11899249 ps
T78 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1349748513 Mar 26 12:39:46 PM PDT 24 Mar 26 12:39:48 PM PDT 24 38018874 ps
T1139 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1225048088 Mar 26 12:39:59 PM PDT 24 Mar 26 12:40:01 PM PDT 24 136145303 ps
T1140 /workspace/coverage/cover_reg_top/7.uart_tl_errors.818373528 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:59 PM PDT 24 186413942 ps
T110 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1646435150 Mar 26 12:39:52 PM PDT 24 Mar 26 12:39:54 PM PDT 24 314620890 ps
T105 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.481320574 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 155906224 ps
T1141 /workspace/coverage/cover_reg_top/7.uart_intr_test.2551189906 Mar 26 12:39:51 PM PDT 24 Mar 26 12:39:52 PM PDT 24 12759745 ps
T72 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3768079494 Mar 26 12:40:09 PM PDT 24 Mar 26 12:40:09 PM PDT 24 12489262 ps
T1142 /workspace/coverage/cover_reg_top/15.uart_intr_test.2922502078 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 87721116 ps
T1143 /workspace/coverage/cover_reg_top/48.uart_intr_test.4069130983 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 63640632 ps
T106 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3073478393 Mar 26 12:39:50 PM PDT 24 Mar 26 12:39:51 PM PDT 24 235168612 ps
T111 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.393670481 Mar 26 12:40:17 PM PDT 24 Mar 26 12:40:18 PM PDT 24 66031087 ps
T1144 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4134413261 Mar 26 12:39:53 PM PDT 24 Mar 26 12:39:55 PM PDT 24 404108597 ps
T1145 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1734603560 Mar 26 12:40:11 PM PDT 24 Mar 26 12:40:13 PM PDT 24 74200965 ps
T1146 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3911603951 Mar 26 12:39:56 PM PDT 24 Mar 26 12:39:58 PM PDT 24 84939830 ps
T98 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3381147505 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 14713348 ps
T1147 /workspace/coverage/cover_reg_top/24.uart_intr_test.1153856154 Mar 26 12:40:04 PM PDT 24 Mar 26 12:40:05 PM PDT 24 58976556 ps
T73 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.629473915 Mar 26 12:40:16 PM PDT 24 Mar 26 12:40:16 PM PDT 24 67334941 ps
T99 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2040014569 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:58 PM PDT 24 21120399 ps
T1148 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.770527982 Mar 26 12:39:47 PM PDT 24 Mar 26 12:39:47 PM PDT 24 50684473 ps
T1149 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.169864947 Mar 26 12:40:03 PM PDT 24 Mar 26 12:40:04 PM PDT 24 40396018 ps
T1150 /workspace/coverage/cover_reg_top/8.uart_tl_errors.401446505 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 24804986 ps
T1151 /workspace/coverage/cover_reg_top/29.uart_intr_test.332584818 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:08 PM PDT 24 14821188 ps
T74 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.922559515 Mar 26 12:40:01 PM PDT 24 Mar 26 12:40:01 PM PDT 24 30122678 ps
T107 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1110295091 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 336792095 ps
T1152 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2039347477 Mar 26 12:39:47 PM PDT 24 Mar 26 12:39:48 PM PDT 24 23526796 ps
T1153 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1165017513 Mar 26 12:39:45 PM PDT 24 Mar 26 12:39:47 PM PDT 24 351223510 ps
T1154 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3262340257 Mar 26 12:39:48 PM PDT 24 Mar 26 12:39:50 PM PDT 24 109520167 ps
T1155 /workspace/coverage/cover_reg_top/19.uart_intr_test.2749262834 Mar 26 12:40:04 PM PDT 24 Mar 26 12:40:04 PM PDT 24 12615337 ps
T1156 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3454289232 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:59 PM PDT 24 16835614 ps
T1157 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2636105457 Mar 26 12:40:01 PM PDT 24 Mar 26 12:40:01 PM PDT 24 13192974 ps
T1158 /workspace/coverage/cover_reg_top/6.uart_intr_test.3339539763 Mar 26 12:39:59 PM PDT 24 Mar 26 12:40:00 PM PDT 24 59519526 ps
T1159 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.21786467 Mar 26 12:40:13 PM PDT 24 Mar 26 12:40:14 PM PDT 24 51475173 ps
T1160 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3369580469 Mar 26 12:39:56 PM PDT 24 Mar 26 12:39:57 PM PDT 24 31154930 ps
T1161 /workspace/coverage/cover_reg_top/19.uart_tl_errors.681571155 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:10 PM PDT 24 123185507 ps
T1162 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3336033750 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 17002874 ps
T1163 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2372881542 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:59 PM PDT 24 24270824 ps
T1164 /workspace/coverage/cover_reg_top/28.uart_intr_test.1817845284 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:06 PM PDT 24 45327748 ps
T1165 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3867268066 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:58 PM PDT 24 15320563 ps
T1166 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2703939791 Mar 26 12:40:11 PM PDT 24 Mar 26 12:40:16 PM PDT 24 20514604 ps
T1167 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2638905720 Mar 26 12:39:46 PM PDT 24 Mar 26 12:39:47 PM PDT 24 29870650 ps
T1168 /workspace/coverage/cover_reg_top/6.uart_csr_rw.4138532975 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 26537555 ps
T1169 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2297207367 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 15718726 ps
T1170 /workspace/coverage/cover_reg_top/5.uart_intr_test.1469425218 Mar 26 12:40:05 PM PDT 24 Mar 26 12:40:06 PM PDT 24 13261482 ps
T160 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2109779085 Mar 26 12:40:00 PM PDT 24 Mar 26 12:40:01 PM PDT 24 780445232 ps
T1171 /workspace/coverage/cover_reg_top/46.uart_intr_test.3425116939 Mar 26 12:40:04 PM PDT 24 Mar 26 12:40:05 PM PDT 24 87165047 ps
T75 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1927093123 Mar 26 12:39:49 PM PDT 24 Mar 26 12:39:49 PM PDT 24 16249892 ps
T1172 /workspace/coverage/cover_reg_top/33.uart_intr_test.1712800588 Mar 26 12:40:18 PM PDT 24 Mar 26 12:40:18 PM PDT 24 42743452 ps
T1173 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3285082856 Mar 26 12:40:01 PM PDT 24 Mar 26 12:40:02 PM PDT 24 15312358 ps
T1174 /workspace/coverage/cover_reg_top/44.uart_intr_test.3061399934 Mar 26 12:40:07 PM PDT 24 Mar 26 12:40:07 PM PDT 24 42053599 ps
T1175 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1904326600 Mar 26 12:39:50 PM PDT 24 Mar 26 12:39:51 PM PDT 24 22485347 ps
T1176 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.479880838 Mar 26 12:39:57 PM PDT 24 Mar 26 12:39:58 PM PDT 24 104065916 ps
T1177 /workspace/coverage/cover_reg_top/26.uart_intr_test.1663703629 Mar 26 12:40:05 PM PDT 24 Mar 26 12:40:05 PM PDT 24 32149897 ps
T1178 /workspace/coverage/cover_reg_top/47.uart_intr_test.32922155 Mar 26 12:40:29 PM PDT 24 Mar 26 12:40:29 PM PDT 24 13977223 ps
T1179 /workspace/coverage/cover_reg_top/30.uart_intr_test.1483365641 Mar 26 12:40:09 PM PDT 24 Mar 26 12:40:09 PM PDT 24 32163220 ps
T1180 /workspace/coverage/cover_reg_top/4.uart_intr_test.4003214325 Mar 26 12:40:00 PM PDT 24 Mar 26 12:40:01 PM PDT 24 39169016 ps
T1181 /workspace/coverage/cover_reg_top/0.uart_intr_test.4030887392 Mar 26 12:39:43 PM PDT 24 Mar 26 12:39:44 PM PDT 24 28243938 ps
T1182 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.379001321 Mar 26 12:39:53 PM PDT 24 Mar 26 12:39:54 PM PDT 24 20725521 ps
T1183 /workspace/coverage/cover_reg_top/23.uart_intr_test.1554713143 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 45858763 ps
T1184 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.773436241 Mar 26 12:40:04 PM PDT 24 Mar 26 12:40:04 PM PDT 24 13412442 ps
T1185 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2978853780 Mar 26 12:39:59 PM PDT 24 Mar 26 12:40:00 PM PDT 24 68480151 ps
T76 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3790309120 Mar 26 12:39:58 PM PDT 24 Mar 26 12:39:58 PM PDT 24 14926160 ps
T1186 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.34056556 Mar 26 12:40:17 PM PDT 24 Mar 26 12:40:18 PM PDT 24 28001560 ps
T159 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2217793315 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 51559784 ps
T77 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2923047079 Mar 26 12:39:48 PM PDT 24 Mar 26 12:39:48 PM PDT 24 39126450 ps
T112 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2764863382 Mar 26 12:40:12 PM PDT 24 Mar 26 12:40:14 PM PDT 24 52822388 ps
T79 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3943387776 Mar 26 12:39:47 PM PDT 24 Mar 26 12:39:48 PM PDT 24 167495491 ps
T1187 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.967462933 Mar 26 12:39:52 PM PDT 24 Mar 26 12:39:53 PM PDT 24 22553587 ps
T1188 /workspace/coverage/cover_reg_top/45.uart_intr_test.1932780108 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 46895938 ps
T1189 /workspace/coverage/cover_reg_top/35.uart_intr_test.1575356053 Mar 26 12:40:12 PM PDT 24 Mar 26 12:40:13 PM PDT 24 33597901 ps
T1190 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1928192448 Mar 26 12:40:09 PM PDT 24 Mar 26 12:40:10 PM PDT 24 115904731 ps
T1191 /workspace/coverage/cover_reg_top/49.uart_intr_test.1482924293 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 10841243 ps
T1192 /workspace/coverage/cover_reg_top/10.uart_intr_test.614424313 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 49515222 ps
T1193 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2463058605 Mar 26 12:39:57 PM PDT 24 Mar 26 12:39:57 PM PDT 24 34810078 ps
T1194 /workspace/coverage/cover_reg_top/22.uart_intr_test.3721724655 Mar 26 12:40:11 PM PDT 24 Mar 26 12:40:11 PM PDT 24 25043272 ps
T1195 /workspace/coverage/cover_reg_top/38.uart_intr_test.3337357271 Mar 26 12:40:17 PM PDT 24 Mar 26 12:40:18 PM PDT 24 11675767 ps
T1196 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.31613562 Mar 26 12:39:59 PM PDT 24 Mar 26 12:40:00 PM PDT 24 78505329 ps
T1197 /workspace/coverage/cover_reg_top/34.uart_intr_test.3286531023 Mar 26 12:40:07 PM PDT 24 Mar 26 12:40:07 PM PDT 24 39454683 ps
T1198 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2648503140 Mar 26 12:40:27 PM PDT 24 Mar 26 12:40:29 PM PDT 24 54921958 ps
T1199 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2058604220 Mar 26 12:40:03 PM PDT 24 Mar 26 12:40:04 PM PDT 24 43191267 ps
T1200 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2928259257 Mar 26 12:39:59 PM PDT 24 Mar 26 12:40:01 PM PDT 24 155906715 ps
T1201 /workspace/coverage/cover_reg_top/1.uart_intr_test.3502902574 Mar 26 12:39:47 PM PDT 24 Mar 26 12:39:47 PM PDT 24 20240350 ps
T1202 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2272458498 Mar 26 12:39:45 PM PDT 24 Mar 26 12:39:46 PM PDT 24 24823717 ps
T1203 /workspace/coverage/cover_reg_top/37.uart_intr_test.209075038 Mar 26 12:40:09 PM PDT 24 Mar 26 12:40:10 PM PDT 24 15228840 ps
T1204 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1829480394 Mar 26 12:40:10 PM PDT 24 Mar 26 12:40:11 PM PDT 24 111212284 ps
T1205 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1490120078 Mar 26 12:40:17 PM PDT 24 Mar 26 12:40:19 PM PDT 24 51572077 ps
T1206 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2025365162 Mar 26 12:40:18 PM PDT 24 Mar 26 12:40:19 PM PDT 24 44368626 ps
T1207 /workspace/coverage/cover_reg_top/18.uart_intr_test.650171746 Mar 26 12:40:09 PM PDT 24 Mar 26 12:40:09 PM PDT 24 13981097 ps
T1208 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.141409692 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 51973622 ps
T1209 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2324236826 Mar 26 12:40:17 PM PDT 24 Mar 26 12:40:18 PM PDT 24 99532804 ps
T1210 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3094330201 Mar 26 12:40:05 PM PDT 24 Mar 26 12:40:06 PM PDT 24 24476719 ps
T1211 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2817400564 Mar 26 12:39:49 PM PDT 24 Mar 26 12:39:50 PM PDT 24 111045763 ps
T1212 /workspace/coverage/cover_reg_top/20.uart_intr_test.2002801456 Mar 26 12:40:07 PM PDT 24 Mar 26 12:40:08 PM PDT 24 14174206 ps
T1213 /workspace/coverage/cover_reg_top/12.uart_intr_test.1217484905 Mar 26 12:40:03 PM PDT 24 Mar 26 12:40:04 PM PDT 24 15505709 ps
T108 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3222460081 Mar 26 12:39:56 PM PDT 24 Mar 26 12:39:58 PM PDT 24 105108963 ps
T1214 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1772149333 Mar 26 12:40:11 PM PDT 24 Mar 26 12:40:12 PM PDT 24 65512527 ps
T1215 /workspace/coverage/cover_reg_top/40.uart_intr_test.2898450073 Mar 26 12:40:04 PM PDT 24 Mar 26 12:40:05 PM PDT 24 41730912 ps
T80 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2465979601 Mar 26 12:39:56 PM PDT 24 Mar 26 12:39:57 PM PDT 24 79796551 ps
T1216 /workspace/coverage/cover_reg_top/14.uart_tl_errors.982863877 Mar 26 12:39:58 PM PDT 24 Mar 26 12:40:00 PM PDT 24 229263677 ps
T1217 /workspace/coverage/cover_reg_top/39.uart_intr_test.1104002827 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 23133466 ps
T1218 /workspace/coverage/cover_reg_top/2.uart_intr_test.1429810638 Mar 26 12:39:52 PM PDT 24 Mar 26 12:39:52 PM PDT 24 42073109 ps
T1219 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.558707628 Mar 26 12:39:59 PM PDT 24 Mar 26 12:40:01 PM PDT 24 323262367 ps
T91 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3895169098 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 89949144 ps
T1220 /workspace/coverage/cover_reg_top/32.uart_intr_test.3140524709 Mar 26 12:40:11 PM PDT 24 Mar 26 12:40:11 PM PDT 24 23002725 ps
T1221 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2567840063 Mar 26 12:39:48 PM PDT 24 Mar 26 12:39:50 PM PDT 24 109521735 ps
T1222 /workspace/coverage/cover_reg_top/25.uart_intr_test.1749384489 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:06 PM PDT 24 14402123 ps
T81 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3047181850 Mar 26 12:39:51 PM PDT 24 Mar 26 12:39:52 PM PDT 24 51250666 ps
T1223 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4132940042 Mar 26 12:39:58 PM PDT 24 Mar 26 12:40:01 PM PDT 24 346980142 ps
T1224 /workspace/coverage/cover_reg_top/16.uart_tl_errors.782744800 Mar 26 12:40:14 PM PDT 24 Mar 26 12:40:15 PM PDT 24 106279695 ps
T1225 /workspace/coverage/cover_reg_top/13.uart_intr_test.3207965004 Mar 26 12:39:57 PM PDT 24 Mar 26 12:39:58 PM PDT 24 15070869 ps
T109 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1573673865 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:08 PM PDT 24 339408049 ps
T1226 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2927425744 Mar 26 12:39:52 PM PDT 24 Mar 26 12:39:53 PM PDT 24 36669794 ps
T1227 /workspace/coverage/cover_reg_top/41.uart_intr_test.2248762821 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 80211992 ps
T1228 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1754923641 Mar 26 12:39:50 PM PDT 24 Mar 26 12:39:52 PM PDT 24 72994024 ps
T1229 /workspace/coverage/cover_reg_top/14.uart_intr_test.2609558878 Mar 26 12:40:03 PM PDT 24 Mar 26 12:40:04 PM PDT 24 33939451 ps
T1230 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3973087344 Mar 26 12:40:05 PM PDT 24 Mar 26 12:40:05 PM PDT 24 28151206 ps
T1231 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1586824026 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 20023721 ps
T1232 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1116077101 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 29660364 ps
T1233 /workspace/coverage/cover_reg_top/21.uart_intr_test.41729848 Mar 26 12:40:15 PM PDT 24 Mar 26 12:40:16 PM PDT 24 36870098 ps
T161 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.507453270 Mar 26 12:39:56 PM PDT 24 Mar 26 12:39:57 PM PDT 24 72508070 ps
T1234 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1495754810 Mar 26 12:40:05 PM PDT 24 Mar 26 12:40:06 PM PDT 24 12695695 ps
T1235 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3442490347 Mar 26 12:40:11 PM PDT 24 Mar 26 12:40:12 PM PDT 24 12362776 ps
T1236 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1515592538 Mar 26 12:40:10 PM PDT 24 Mar 26 12:40:11 PM PDT 24 49665430 ps
T1237 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2843890279 Mar 26 12:40:06 PM PDT 24 Mar 26 12:40:07 PM PDT 24 72366544 ps
T1238 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3528437877 Mar 26 12:39:53 PM PDT 24 Mar 26 12:39:54 PM PDT 24 79422484 ps
T1239 /workspace/coverage/cover_reg_top/43.uart_intr_test.2579600290 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 20784038 ps
T1240 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3160558931 Mar 26 12:39:47 PM PDT 24 Mar 26 12:39:48 PM PDT 24 12636930 ps
T1241 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2037729901 Mar 26 12:40:12 PM PDT 24 Mar 26 12:40:14 PM PDT 24 310830093 ps
T1242 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1141945184 Mar 26 12:39:50 PM PDT 24 Mar 26 12:39:51 PM PDT 24 26562885 ps
T1243 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.647350836 Mar 26 12:40:05 PM PDT 24 Mar 26 12:40:06 PM PDT 24 94607678 ps
T1244 /workspace/coverage/cover_reg_top/9.uart_intr_test.4132092858 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 44538178 ps
T1245 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3615792006 Mar 26 12:39:53 PM PDT 24 Mar 26 12:39:54 PM PDT 24 58200627 ps
T1246 /workspace/coverage/cover_reg_top/31.uart_intr_test.124977505 Mar 26 12:40:17 PM PDT 24 Mar 26 12:40:18 PM PDT 24 22168390 ps
T1247 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1085474327 Mar 26 12:39:47 PM PDT 24 Mar 26 12:39:49 PM PDT 24 735910084 ps
T1248 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3557986743 Mar 26 12:40:02 PM PDT 24 Mar 26 12:40:03 PM PDT 24 16043137 ps
T1249 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1998202902 Mar 26 12:39:51 PM PDT 24 Mar 26 12:39:52 PM PDT 24 86770984 ps
T1250 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3252991189 Mar 26 12:40:08 PM PDT 24 Mar 26 12:40:09 PM PDT 24 20167742 ps
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