Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.27	97.95	100.00		98.80	100.00	99.52

Total test records in report: 1256

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/9.uart_csr_rw.639509359			Mar 26 12:40:16 PM PDT 24	Mar 26 12:40:17 PM PDT 24	41701618 ps
T1252	/workspace/coverage/cover_reg_top/4.uart_tl_errors.894805484			Mar 26 12:39:49 PM PDT 24	Mar 26 12:39:50 PM PDT 24	35091448 ps
T1253	/workspace/coverage/cover_reg_top/3.uart_tl_errors.3494876097			Mar 26 12:39:55 PM PDT 24	Mar 26 12:39:57 PM PDT 24	26410985 ps
T1254	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3855369177			Mar 26 12:39:54 PM PDT 24	Mar 26 12:39:56 PM PDT 24	39783585 ps
T1255	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1151102899			Mar 26 12:40:18 PM PDT 24	Mar 26 12:40:18 PM PDT 24	25510644 ps
T1256	/workspace/coverage/cover_reg_top/3.uart_intr_test.3251438088			Mar 26 12:39:59 PM PDT 24	Mar 26 12:40:00 PM PDT 24	18338176 ps

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.1964916484
Short name	T5
Test name
Test status
Simulation time	87670487861 ps
CPU time	699.01 seconds
Started	Mar 26 02:23:14 PM PDT 24
Finished	Mar 26 02:34:53 PM PDT 24
Peak memory	200084 kb
Host	smart-e7872de7-2c26-45d8-9e00-8beb2ae33164
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1964916484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1964916484
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_stress_all.2350928788
Short name	T16
Test name
Test status
Simulation time	994553713207 ps
CPU time	670.2 seconds
Started	Mar 26 02:22:19 PM PDT 24
Finished	Mar 26 02:33:29 PM PDT 24
Peak memory	199960 kb
Host	smart-746052b1-31e1-4e68-b455-e0fd2562ee13
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350928788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2350928788
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/15.uart_stress_all_with_rand_reset.2564565706
Short name	T21
Test name
Test status
Simulation time	24970796362 ps
CPU time	315.28 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:26:24 PM PDT 24
Peak memory	216544 kb
Host	smart-f16f481c-251b-4c29-b7cf-d2092a2569bd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564565706 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2564565706
Directory	/workspace/15.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.uart_stress_all.692743232
Short name	T155
Test name
Test status
Simulation time	228963322002 ps
CPU time	106.95 seconds
Started	Mar 26 02:23:01 PM PDT 24
Finished	Mar 26 02:24:48 PM PDT 24
Peak memory	200124 kb
Host	smart-8d45fd3a-39ac-4d35-8d4a-5c352069d128
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692743232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.692743232
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.2027033108
Short name	T7
Test name
Test status
Simulation time	188240314573 ps
CPU time	58.6 seconds
Started	Mar 26 02:27:29 PM PDT 24
Finished	Mar 26 02:28:27 PM PDT 24
Peak memory	200064 kb
Host	smart-d917b953-31bb-4169-b439-7ebb47fec5e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027033108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2027033108
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_stress_all.3863228560
Short name	T17
Test name
Test status
Simulation time	170850738363 ps
CPU time	600.27 seconds
Started	Mar 26 02:21:21 PM PDT 24
Finished	Mar 26 02:31:21 PM PDT 24
Peak memory	200160 kb
Host	smart-f68959cb-0405-4b5f-b78d-2926fe2bf1da
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863228560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3863228560
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_long_xfer_wo_dly.532640689
Short name	T279
Test name
Test status
Simulation time	86691609440 ps
CPU time	204.95 seconds
Started	Mar 26 02:21:34 PM PDT 24
Finished	Mar 26 02:24:59 PM PDT 24
Peak memory	200024 kb
Host	smart-76c5f33a-e9e2-4f41-8c12-a1a21050a241
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=532640689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.532640689
Directory	/workspace/18.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.2781777042
Short name	T150
Test name
Test status
Simulation time	132831096523 ps
CPU time	72.84 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:24:04 PM PDT 24
Peak memory	200040 kb
Host	smart-0dbeb2f3-9c35-45c5-ae19-8eee4850fbfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781777042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2781777042
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.3743127852
Short name	T33
Test name
Test status
Simulation time	272100133 ps
CPU time	0.89 seconds
Started	Mar 26 02:19:43 PM PDT 24
Finished	Mar 26 02:19:44 PM PDT 24
Peak memory	218768 kb
Host	smart-7fd04d64-2043-47e1-984a-66d0e453c722
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743127852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3743127852
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.3970016848
Short name	T169
Test name
Test status
Simulation time	118792198407 ps
CPU time	320.33 seconds
Started	Mar 26 02:29:26 PM PDT 24
Finished	Mar 26 02:34:46 PM PDT 24
Peak memory	200124 kb
Host	smart-5e5d9e41-9186-427e-85a4-3a83da4c228b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970016848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3970016848
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_stress_all_with_rand_reset.2770416633
Short name	T42
Test name
Test status
Simulation time	125470303724 ps
CPU time	466.96 seconds
Started	Mar 26 02:28:08 PM PDT 24
Finished	Mar 26 02:35:56 PM PDT 24
Peak memory	211756 kb
Host	smart-d82c043a-4b1d-4c86-a6fc-7fbe93675869
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770416633 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2770416633
Directory	/workspace/99.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.1747764864
Short name	T164
Test name
Test status
Simulation time	93526487858 ps
CPU time	45.1 seconds
Started	Mar 26 02:27:30 PM PDT 24
Finished	Mar 26 02:28:16 PM PDT 24
Peak memory	200080 kb
Host	smart-28996b97-a33f-4c4b-a0ca-26ba63eeca78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747764864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1747764864
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/55.uart_stress_all_with_rand_reset.4089570366
Short name	T40
Test name
Test status
Simulation time	290240938476 ps
CPU time	636.08 seconds
Started	Mar 26 02:27:13 PM PDT 24
Finished	Mar 26 02:37:51 PM PDT 24
Peak memory	228360 kb
Host	smart-233064b3-4460-4da6-84c4-0a66a5896bc0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089570366 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.4089570366
Directory	/workspace/55.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.uart_stress_all_with_rand_reset.1235200371
Short name	T39
Test name
Test status
Simulation time	77499025446 ps
CPU time	168.76 seconds
Started	Mar 26 02:23:43 PM PDT 24
Finished	Mar 26 02:26:32 PM PDT 24
Peak memory	210256 kb
Host	smart-3fafa296-693a-4158-b39b-5842b40de014
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235200371 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1235200371
Directory	/workspace/31.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3790309120
Short name	T76
Test name
Test status
Simulation time	14926160 ps
CPU time	0.58 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:58 PM PDT 24
Peak memory	195788 kb
Host	smart-bef3915b-6aef-4904-961c-cd952064d27d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790309120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3790309120
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.854322861
Short name	T166
Test name
Test status
Simulation time	297537242910 ps
CPU time	110.73 seconds
Started	Mar 26 02:25:56 PM PDT 24
Finished	Mar 26 02:27:47 PM PDT 24
Peak memory	200044 kb
Host	smart-352e96c2-bd88-4fdd-b771-02af61201179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854322861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.854322861
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.1706594243
Short name	T100
Test name
Test status
Simulation time	40700912449 ps
CPU time	71.77 seconds
Started	Mar 26 02:29:09 PM PDT 24
Finished	Mar 26 02:30:20 PM PDT 24
Peak memory	200184 kb
Host	smart-56a782f7-8739-4730-82d1-c0dc76dddbcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706594243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1706594243
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.2501265767
Short name	T13
Test name
Test status
Simulation time	181034028828 ps
CPU time	107.67 seconds
Started	Mar 26 02:20:22 PM PDT 24
Finished	Mar 26 02:22:10 PM PDT 24
Peak memory	200144 kb
Host	smart-e1cf6208-3b11-457c-8a69-0a7982da8038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501265767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2501265767
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.3835419624
Short name	T212
Test name
Test status
Simulation time	374919283762 ps
CPU time	200.53 seconds
Started	Mar 26 02:28:41 PM PDT 24
Finished	Mar 26 02:32:02 PM PDT 24
Peak memory	200044 kb
Host	smart-38a59bab-2534-403b-8bc3-c76b1a7b4620
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835419624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3835419624
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.294296730
Short name	T57
Test name
Test status
Simulation time	78979441493 ps
CPU time	42.27 seconds
Started	Mar 26 02:26:40 PM PDT 24
Finished	Mar 26 02:27:22 PM PDT 24
Peak memory	199900 kb
Host	smart-24be5c1c-3a23-46ff-a5d1-3e42fcf63404
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294296730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.294296730
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3073478393
Short name	T106
Test name
Test status
Simulation time	235168612 ps
CPU time	1.29 seconds
Started	Mar 26 12:39:50 PM PDT 24
Finished	Mar 26 12:39:51 PM PDT 24
Peak memory	199476 kb
Host	smart-9976e4db-4442-49e3-bae1-48dbdcf691ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073478393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3073478393
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.2577340542
Short name	T41
Test name
Test status
Simulation time	690521724604 ps
CPU time	710.42 seconds
Started	Mar 26 02:27:50 PM PDT 24
Finished	Mar 26 02:39:41 PM PDT 24
Peak memory	216704 kb
Host	smart-a6528b72-3de5-4234-b2a0-15d4809b4ad1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577340542 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2577340542
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.1413249777
Short name	T6
Test name
Test status
Simulation time	3452938728 ps
CPU time	3.49 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:22:32 PM PDT 24
Peak memory	196448 kb
Host	smart-39db8ff8-b8ab-4bfa-b136-edf97bc6d7b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413249777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1413249777
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_alert_test.2670675370
Short name	T380
Test name
Test status
Simulation time	28745977 ps
CPU time	0.6 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:22:19 PM PDT 24
Peak memory	195456 kb
Host	smart-b5d2352b-44df-49a6-ae72-c763d3e0f09d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670675370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2670675370
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.1881303471
Short name	T131
Test name
Test status
Simulation time	75358698959 ps
CPU time	125.95 seconds
Started	Mar 26 02:19:37 PM PDT 24
Finished	Mar 26 02:21:43 PM PDT 24
Peak memory	200088 kb
Host	smart-befea421-6e74-4e01-866e-919024503d55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881303471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1881303471
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/83.uart_stress_all_with_rand_reset.212979021
Short name	T31
Test name
Test status
Simulation time	75367445460 ps
CPU time	717.11 seconds
Started	Mar 26 02:27:39 PM PDT 24
Finished	Mar 26 02:39:36 PM PDT 24
Peak memory	216544 kb
Host	smart-6b55495d-3c47-4467-8f94-a75cf9bb8033
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212979021 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.212979021
Directory	/workspace/83.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.14667912
Short name	T210
Test name
Test status
Simulation time	115526465936 ps
CPU time	180.11 seconds
Started	Mar 26 02:30:16 PM PDT 24
Finished	Mar 26 02:33:16 PM PDT 24
Peak memory	200080 kb
Host	smart-bbed7bd8-e3ab-4015-8117-6efb7faffefd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14667912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.14667912
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.1659118641
Short name	T46
Test name
Test status
Simulation time	68111557963 ps
CPU time	59.06 seconds
Started	Mar 26 02:19:57 PM PDT 24
Finished	Mar 26 02:20:56 PM PDT 24
Peak memory	200104 kb
Host	smart-42c3a013-1620-403e-9b6e-d28ec51a7654
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659118641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1659118641
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.162667769
Short name	T153
Test name
Test status
Simulation time	176296706248 ps
CPU time	70.4 seconds
Started	Mar 26 02:19:42 PM PDT 24
Finished	Mar 26 02:20:52 PM PDT 24
Peak memory	200140 kb
Host	smart-28b6833a-c5fc-4261-bf89-d096fade7a8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162667769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.162667769
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.1453850105
Short name	T71
Test name
Test status
Simulation time	18687325 ps
CPU time	0.59 seconds
Started	Mar 26 12:39:45 PM PDT 24
Finished	Mar 26 12:39:46 PM PDT 24
Peak memory	195644 kb
Host	smart-94443ee3-f03c-4f2d-b715-8a667272e75f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453850105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1453850105
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/default/32.uart_stress_all.691079462
Short name	T181
Test name
Test status
Simulation time	360805671721 ps
CPU time	936.86 seconds
Started	Mar 26 02:23:55 PM PDT 24
Finished	Mar 26 02:39:32 PM PDT 24
Peak memory	200092 kb
Host	smart-377bae59-3486-4674-988a-59f1eb03d73d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691079462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.691079462
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/12.uart_stress_all.219909716
Short name	T134
Test name
Test status
Simulation time	425334834120 ps
CPU time	737.99 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:33:14 PM PDT 24
Peak memory	200088 kb
Host	smart-7b434d2d-d011-496b-9066-74758e37b2f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219909716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.219909716
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1646435150
Short name	T110
Test name
Test status
Simulation time	314620890 ps
CPU time	1.4 seconds
Started	Mar 26 12:39:52 PM PDT 24
Finished	Mar 26 12:39:54 PM PDT 24
Peak memory	199752 kb
Host	smart-85b4b54b-6414-4b74-89ce-4388f471d6d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646435150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1646435150
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/3.uart_stress_all.3562288279
Short name	T158
Test name
Test status
Simulation time	310323752402 ps
CPU time	570.55 seconds
Started	Mar 26 02:19:43 PM PDT 24
Finished	Mar 26 02:29:14 PM PDT 24
Peak memory	215648 kb
Host	smart-8c22dfd7-2db1-4993-ab31-0e4f182f5a20
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562288279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3562288279
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.466495051
Short name	T171
Test name
Test status
Simulation time	126848361930 ps
CPU time	55.13 seconds
Started	Mar 26 02:25:27 PM PDT 24
Finished	Mar 26 02:26:24 PM PDT 24
Peak memory	200048 kb
Host	smart-d66bb2bb-2338-4f84-b091-42302d86e81e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466495051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.466495051
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.2230349877
Short name	T771
Test name
Test status
Simulation time	106051541745 ps
CPU time	29.9 seconds
Started	Mar 26 02:23:42 PM PDT 24
Finished	Mar 26 02:24:12 PM PDT 24
Peak memory	200032 kb
Host	smart-0d49b3c7-6416-4fc5-9c16-ae1ee8189889
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230349877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2230349877
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.114741459
Short name	T50
Test name
Test status
Simulation time	47192131535 ps
CPU time	41.27 seconds
Started	Mar 26 02:27:23 PM PDT 24
Finished	Mar 26 02:28:04 PM PDT 24
Peak memory	200076 kb
Host	smart-b74f3ba1-495b-436a-aa3e-525d251d426b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114741459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.114741459
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_stress_all.1122752019
Short name	T203
Test name
Test status
Simulation time	159090874985 ps
CPU time	237.97 seconds
Started	Mar 26 02:22:09 PM PDT 24
Finished	Mar 26 02:26:07 PM PDT 24
Peak memory	200080 kb
Host	smart-1f26c1f4-3b98-4cc8-ac37-fc66f6c091b1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122752019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1122752019
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_stress_all_with_rand_reset.1034692027
Short name	T30
Test name
Test status
Simulation time	81746933431 ps
CPU time	276.09 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:25:30 PM PDT 24
Peak memory	216624 kb
Host	smart-2e3c0051-485d-4484-ba2c-fe8c4252b307
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034692027 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1034692027
Directory	/workspace/14.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.4116747270
Short name	T208
Test name
Test status
Simulation time	76648018576 ps
CPU time	203.64 seconds
Started	Mar 26 02:30:10 PM PDT 24
Finished	Mar 26 02:33:34 PM PDT 24
Peak memory	200064 kb
Host	smart-6783df63-4473-416f-ba71-8bb80d9f90c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116747270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4116747270
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.3481727049
Short name	T297
Test name
Test status
Simulation time	97647993733 ps
CPU time	96.07 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:24:15 PM PDT 24
Peak memory	208276 kb
Host	smart-7fbe5844-7787-4e04-be2e-ee425c7da79d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481727049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3481727049
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.3136503207
Short name	T265
Test name
Test status
Simulation time	104281101082 ps
CPU time	47.42 seconds
Started	Mar 26 02:29:33 PM PDT 24
Finished	Mar 26 02:30:21 PM PDT 24
Peak memory	200068 kb
Host	smart-d0449da0-bb68-48ee-9b1e-d283df628c9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136503207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3136503207
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.3791153511
Short name	T332
Test name
Test status
Simulation time	41096592736 ps
CPU time	142.66 seconds
Started	Mar 26 02:29:34 PM PDT 24
Finished	Mar 26 02:31:57 PM PDT 24
Peak memory	200044 kb
Host	smart-7ed3d820-b4c2-4f07-b596-794f053eeb86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791153511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3791153511
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.58378526
Short name	T52
Test name
Test status
Simulation time	79340748599 ps
CPU time	21.48 seconds
Started	Mar 26 02:30:02 PM PDT 24
Finished	Mar 26 02:30:24 PM PDT 24
Peak memory	200128 kb
Host	smart-2f39208c-9945-4e72-b671-2ec28e3ba6a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58378526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.58378526
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.1476163459
Short name	T188
Test name
Test status
Simulation time	88926312435 ps
CPU time	11.29 seconds
Started	Mar 26 02:23:25 PM PDT 24
Finished	Mar 26 02:23:36 PM PDT 24
Peak memory	199948 kb
Host	smart-c0315981-9765-44a6-859c-f8750aaa58dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476163459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1476163459
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.210344702
Short name	T229
Test name
Test status
Simulation time	14229177179 ps
CPU time	12.58 seconds
Started	Mar 26 02:28:27 PM PDT 24
Finished	Mar 26 02:28:40 PM PDT 24
Peak memory	200108 kb
Host	smart-a6064f4f-4989-413b-8259-f3a1ba2e93d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210344702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.210344702
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.3040564405
Short name	T299
Test name
Test status
Simulation time	135980104246 ps
CPU time	85.85 seconds
Started	Mar 26 02:21:32 PM PDT 24
Finished	Mar 26 02:22:58 PM PDT 24
Peak memory	199948 kb
Host	smart-60c50132-be6f-449f-992c-8f2d7612e412
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040564405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3040564405
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.3992074791
Short name	T218
Test name
Test status
Simulation time	20607639302 ps
CPU time	33.7 seconds
Started	Mar 26 02:30:10 PM PDT 24
Finished	Mar 26 02:30:44 PM PDT 24
Peak memory	200136 kb
Host	smart-28456f2b-3820-4126-9ca5-d3e62d8d1f2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992074791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3992074791
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_stress_all_with_rand_reset.3703858979
Short name	T351
Test name
Test status
Simulation time	34333323882 ps
CPU time	244.23 seconds
Started	Mar 26 02:23:01 PM PDT 24
Finished	Mar 26 02:27:06 PM PDT 24
Peak memory	208464 kb
Host	smart-60bae59c-6bbf-4262-9f5c-02637de05360
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703858979 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3703858979
Directory	/workspace/28.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.507453270
Short name	T161
Test name
Test status
Simulation time	72508070 ps
CPU time	1.23 seconds
Started	Mar 26 12:39:56 PM PDT 24
Finished	Mar 26 12:39:57 PM PDT 24
Peak memory	199644 kb
Host	smart-298b1fc9-59dd-488b-a87d-990d8aa5790e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507453270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.507453270
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.71620169
Short name	T8
Test name
Test status
Simulation time	35439573697 ps
CPU time	20.32 seconds
Started	Mar 26 02:28:28 PM PDT 24
Finished	Mar 26 02:28:49 PM PDT 24
Peak memory	200044 kb
Host	smart-d377f607-b8ea-4ca1-9543-7483a88d4107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71620169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.71620169
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.348942118
Short name	T242
Test name
Test status
Simulation time	61071270023 ps
CPU time	25.85 seconds
Started	Mar 26 02:28:41 PM PDT 24
Finished	Mar 26 02:29:07 PM PDT 24
Peak memory	199212 kb
Host	smart-fc8d29c9-d8d7-40f8-a656-b63ecb23428d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348942118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.348942118
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.3577965647
Short name	T730
Test name
Test status
Simulation time	101518344290 ps
CPU time	27.29 seconds
Started	Mar 26 02:21:33 PM PDT 24
Finished	Mar 26 02:22:01 PM PDT 24
Peak memory	200144 kb
Host	smart-e77352bd-c6d1-41c6-b711-c9caeac4e05b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577965647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3577965647
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.3552492722
Short name	T253
Test name
Test status
Simulation time	66208020740 ps
CPU time	73.87 seconds
Started	Mar 26 02:29:16 PM PDT 24
Finished	Mar 26 02:30:30 PM PDT 24
Peak memory	199976 kb
Host	smart-154cbff7-948b-4fb2-a6ff-e522d667361d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552492722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3552492722
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.1187485667
Short name	T205
Test name
Test status
Simulation time	30116661385 ps
CPU time	24.06 seconds
Started	Mar 26 02:29:41 PM PDT 24
Finished	Mar 26 02:30:06 PM PDT 24
Peak memory	200040 kb
Host	smart-70c4f319-716a-4870-8715-8310090f2484
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187485667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1187485667
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.2561584006
Short name	T261
Test name
Test status
Simulation time	124939978893 ps
CPU time	191.44 seconds
Started	Mar 26 02:29:51 PM PDT 24
Finished	Mar 26 02:33:02 PM PDT 24
Peak memory	199924 kb
Host	smart-6acbfa97-16ff-4075-bfdf-1873feddabaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561584006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2561584006
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.3087881654
Short name	T259
Test name
Test status
Simulation time	107492242372 ps
CPU time	134.06 seconds
Started	Mar 26 02:27:12 PM PDT 24
Finished	Mar 26 02:29:27 PM PDT 24
Peak memory	200032 kb
Host	smart-7cc83801-7f76-44fc-ae21-96e6c8b81a93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087881654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3087881654
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.300974799
Short name	T60
Test name
Test status
Simulation time	85072746351 ps
CPU time	343.27 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:25:11 PM PDT 24
Peak memory	200064 kb
Host	smart-1480872e-cf48-41eb-bce3-c26db910eb93
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=300974799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.300974799
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.3152040393
Short name	T271
Test name
Test status
Simulation time	28304160402 ps
CPU time	46.47 seconds
Started	Mar 26 02:28:17 PM PDT 24
Finished	Mar 26 02:29:03 PM PDT 24
Peak memory	200092 kb
Host	smart-cf3fcdde-efad-4381-892d-6f0d752bb4df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152040393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3152040393
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.4163828252
Short name	T216
Test name
Test status
Simulation time	15169498244 ps
CPU time	25.49 seconds
Started	Mar 26 02:28:28 PM PDT 24
Finished	Mar 26 02:28:53 PM PDT 24
Peak memory	200008 kb
Host	smart-5156910c-b741-4b5e-a364-54471dd08e0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163828252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.4163828252
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.1341223044
Short name	T187
Test name
Test status
Simulation time	32415675116 ps
CPU time	11.08 seconds
Started	Mar 26 02:28:27 PM PDT 24
Finished	Mar 26 02:28:38 PM PDT 24
Peak memory	200132 kb
Host	smart-716be6b5-6f51-4e43-8802-2fbf13f03615
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341223044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1341223044
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.1087237486
Short name	T308
Test name
Test status
Simulation time	116739254220 ps
CPU time	45.41 seconds
Started	Mar 26 02:20:47 PM PDT 24
Finished	Mar 26 02:21:33 PM PDT 24
Peak memory	199860 kb
Host	smart-4cdb4bbd-42a9-4ec0-b761-23eaed1e8bae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087237486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1087237486
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.3367654012
Short name	T224
Test name
Test status
Simulation time	32670540305 ps
CPU time	53.73 seconds
Started	Mar 26 02:28:27 PM PDT 24
Finished	Mar 26 02:29:21 PM PDT 24
Peak memory	200108 kb
Host	smart-57d1e7c6-5515-435e-b313-cc50fb2c4d2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367654012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3367654012
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.2519667822
Short name	T202
Test name
Test status
Simulation time	14773354677 ps
CPU time	17.98 seconds
Started	Mar 26 02:28:47 PM PDT 24
Finished	Mar 26 02:29:05 PM PDT 24
Peak memory	200136 kb
Host	smart-d4d9881b-ea2e-4034-9a3e-076eb1176e59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519667822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2519667822
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.3841133878
Short name	T239
Test name
Test status
Simulation time	57495269553 ps
CPU time	90.33 seconds
Started	Mar 26 02:28:45 PM PDT 24
Finished	Mar 26 02:30:15 PM PDT 24
Peak memory	200104 kb
Host	smart-1824b1e6-503e-4cee-ab27-f4c75dfa786b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841133878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3841133878
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.2014107621
Short name	T256
Test name
Test status
Simulation time	32723082270 ps
CPU time	20.48 seconds
Started	Mar 26 02:28:54 PM PDT 24
Finished	Mar 26 02:29:15 PM PDT 24
Peak memory	200024 kb
Host	smart-80429c9f-2077-403d-97fe-f9095c35df2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014107621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2014107621
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.3524892135
Short name	T579
Test name
Test status
Simulation time	58425187493 ps
CPU time	54.21 seconds
Started	Mar 26 02:21:12 PM PDT 24
Finished	Mar 26 02:22:07 PM PDT 24
Peak memory	200144 kb
Host	smart-b334d782-b3be-46e7-adc4-0e6bb4f4ca1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524892135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3524892135
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.3438914860
Short name	T246
Test name
Test status
Simulation time	9042290779 ps
CPU time	10.61 seconds
Started	Mar 26 02:29:08 PM PDT 24
Finished	Mar 26 02:29:19 PM PDT 24
Peak memory	200060 kb
Host	smart-d43b7bf2-f1dc-4c81-aa8d-2a0174441cd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438914860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3438914860
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.3158815627
Short name	T270
Test name
Test status
Simulation time	86839814827 ps
CPU time	66.21 seconds
Started	Mar 26 02:29:15 PM PDT 24
Finished	Mar 26 02:30:21 PM PDT 24
Peak memory	200140 kb
Host	smart-bc3a81aa-c6f6-414a-bc10-bccf3514b6ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158815627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3158815627
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.344746074
Short name	T252
Test name
Test status
Simulation time	38421472156 ps
CPU time	59.6 seconds
Started	Mar 26 02:29:16 PM PDT 24
Finished	Mar 26 02:30:16 PM PDT 24
Peak memory	199984 kb
Host	smart-2abde12c-8590-47d1-9152-8465b74af1bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344746074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.344746074
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.547590823
Short name	T247
Test name
Test status
Simulation time	36528303516 ps
CPU time	19.31 seconds
Started	Mar 26 02:21:44 PM PDT 24
Finished	Mar 26 02:22:04 PM PDT 24
Peak memory	200068 kb
Host	smart-a47a9fc2-4eb8-408e-983a-0f77d7ab81a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547590823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.547590823
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.4489942
Short name	T264
Test name
Test status
Simulation time	182633526834 ps
CPU time	298.49 seconds
Started	Mar 26 02:29:33 PM PDT 24
Finished	Mar 26 02:34:31 PM PDT 24
Peak memory	200072 kb
Host	smart-0d5b0dda-fef1-4571-a679-4534ca11d321
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4489942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4489942
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.1662043203
Short name	T182
Test name
Test status
Simulation time	62818947165 ps
CPU time	37.2 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:31:13 PM PDT 24
Peak memory	200096 kb
Host	smart-25f79b21-93fb-4116-a2d0-df96a6bfc7c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1662043203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1662043203
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.1532374553
Short name	T262
Test name
Test status
Simulation time	78702811288 ps
CPU time	32.68 seconds
Started	Mar 26 02:30:45 PM PDT 24
Finished	Mar 26 02:31:18 PM PDT 24
Peak memory	200332 kb
Host	smart-08c26f1a-09d7-4015-9498-4e6eb3b3b247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532374553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1532374553
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_stress_all_with_rand_reset.791607669
Short name	T43
Test name
Test status
Simulation time	22307378872 ps
CPU time	292.15 seconds
Started	Mar 26 02:24:03 PM PDT 24
Finished	Mar 26 02:28:56 PM PDT 24
Peak memory	216728 kb
Host	smart-6f483d81-3481-46f0-91e0-9d27b1f701a0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791607669 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.791607669
Directory	/workspace/33.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.3009234117
Short name	T260
Test name
Test status
Simulation time	100331311183 ps
CPU time	42.88 seconds
Started	Mar 26 02:26:40 PM PDT 24
Finished	Mar 26 02:27:23 PM PDT 24
Peak memory	200124 kb
Host	smart-e98b0924-3b61-4704-81db-238f6d0ebf29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009234117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3009234117
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.2417528671
Short name	T269
Test name
Test status
Simulation time	83605291534 ps
CPU time	52.92 seconds
Started	Mar 26 02:27:28 PM PDT 24
Finished	Mar 26 02:28:21 PM PDT 24
Peak memory	200016 kb
Host	smart-6d95f0e5-1d54-4184-a802-aa06c2671be7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417528671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2417528671
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.3659550570
Short name	T268
Test name
Test status
Simulation time	100622202732 ps
CPU time	146.39 seconds
Started	Mar 26 02:27:36 PM PDT 24
Finished	Mar 26 02:30:03 PM PDT 24
Peak memory	199700 kb
Host	smart-e58baeff-803e-43b7-b761-7470ecc72b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659550570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3659550570
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.2303286479
Short name	T204
Test name
Test status
Simulation time	36407790820 ps
CPU time	18.88 seconds
Started	Mar 26 02:27:39 PM PDT 24
Finished	Mar 26 02:27:58 PM PDT 24
Peak memory	199972 kb
Host	smart-49eb47fe-1617-4493-86d4-c689606ed198
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303286479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2303286479
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1904326600
Short name	T1175
Test name
Test status
Simulation time	22485347 ps
CPU time	0.67 seconds
Started	Mar 26 12:39:50 PM PDT 24
Finished	Mar 26 12:39:51 PM PDT 24
Peak memory	195676 kb
Host	smart-2d6c1727-2117-4c82-9049-03cda75964e2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904326600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1904326600
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1165017513
Short name	T1153
Test name
Test status
Simulation time	351223510 ps
CPU time	1.45 seconds
Started	Mar 26 12:39:45 PM PDT 24
Finished	Mar 26 12:39:47 PM PDT 24
Peak memory	197924 kb
Host	smart-00e86d53-85e9-4fc0-adf2-549eca0e9f48
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165017513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1165017513
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3943387776
Short name	T79
Test name
Test status
Simulation time	167495491 ps
CPU time	0.6 seconds
Started	Mar 26 12:39:47 PM PDT 24
Finished	Mar 26 12:39:48 PM PDT 24
Peak memory	195708 kb
Host	smart-fde7612f-06e7-4c77-b5b7-e1b0cab405b1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943387776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3943387776
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2272458498
Short name	T1202
Test name
Test status
Simulation time	24823717 ps
CPU time	0.71 seconds
Started	Mar 26 12:39:45 PM PDT 24
Finished	Mar 26 12:39:46 PM PDT 24
Peak memory	198412 kb
Host	smart-1fc66f80-d9ed-4e87-8ff8-72bee160e96f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272458498 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2272458498
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.2923047079
Short name	T77
Test name
Test status
Simulation time	39126450 ps
CPU time	0.61 seconds
Started	Mar 26 12:39:48 PM PDT 24
Finished	Mar 26 12:39:48 PM PDT 24
Peak memory	195936 kb
Host	smart-fd9c2fc0-03ee-4f25-ade1-69b4f6050bc0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923047079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2923047079
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.4030887392
Short name	T1181
Test name
Test status
Simulation time	28243938 ps
CPU time	0.57 seconds
Started	Mar 26 12:39:43 PM PDT 24
Finished	Mar 26 12:39:44 PM PDT 24
Peak memory	194800 kb
Host	smart-d721b1d0-0e48-4482-b4b3-b1b9127d3125
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030887392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4030887392
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2638905720
Short name	T1167
Test name
Test status
Simulation time	29870650 ps
CPU time	0.79 seconds
Started	Mar 26 12:39:46 PM PDT 24
Finished	Mar 26 12:39:47 PM PDT 24
Peak memory	196320 kb
Host	smart-f852c53c-cd22-4be1-8f5a-d8f31b06a093
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638905720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.2638905720
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.3262340257
Short name	T1154
Test name
Test status
Simulation time	109520167 ps
CPU time	1.21 seconds
Started	Mar 26 12:39:48 PM PDT 24
Finished	Mar 26 12:39:50 PM PDT 24
Peak memory	200252 kb
Host	smart-b2a6967e-495a-4dbc-8c7c-a73a254bde43
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262340257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3262340257
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2817400564
Short name	T1211
Test name
Test status
Simulation time	111045763 ps
CPU time	1.32 seconds
Started	Mar 26 12:39:49 PM PDT 24
Finished	Mar 26 12:39:50 PM PDT 24
Peak memory	199648 kb
Host	smart-f1349864-1603-44ec-86b6-dc289a654494
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817400564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2817400564
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3160558931
Short name	T1240
Test name
Test status
Simulation time	12636930 ps
CPU time	0.65 seconds
Started	Mar 26 12:39:47 PM PDT 24
Finished	Mar 26 12:39:48 PM PDT 24
Peak memory	195664 kb
Host	smart-6ac6885f-3326-4450-ada9-8022b18186e8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160558931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3160558931
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1085474327
Short name	T1247
Test name
Test status
Simulation time	735910084 ps
CPU time	2.25 seconds
Started	Mar 26 12:39:47 PM PDT 24
Finished	Mar 26 12:39:49 PM PDT 24
Peak memory	198148 kb
Host	smart-2d0bb505-ff6a-4d3b-8343-4210625c751c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085474327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1085474327
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.770527982
Short name	T1148
Test name
Test status
Simulation time	50684473 ps
CPU time	0.6 seconds
Started	Mar 26 12:39:47 PM PDT 24
Finished	Mar 26 12:39:47 PM PDT 24
Peak memory	195740 kb
Host	smart-6648fd20-5661-4727-a3a9-20b4ae9259ad
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770527982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.770527982
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4000394911
Short name	T1137
Test name
Test status
Simulation time	105967270 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:46 PM PDT 24
Finished	Mar 26 12:39:47 PM PDT 24
Peak memory	200148 kb
Host	smart-c81cc38e-4df4-46af-8c45-9936e4661915
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000394911 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.4000394911
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.3502902574
Short name	T1201
Test name
Test status
Simulation time	20240350 ps
CPU time	0.56 seconds
Started	Mar 26 12:39:47 PM PDT 24
Finished	Mar 26 12:39:47 PM PDT 24
Peak memory	194696 kb
Host	smart-13fd7cbe-a5ad-4502-a6a4-7680496e8002
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502902574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3502902574
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.974988245
Short name	T93
Test name
Test status
Simulation time	13678234 ps
CPU time	0.64 seconds
Started	Mar 26 12:39:56 PM PDT 24
Finished	Mar 26 12:39:57 PM PDT 24
Peak memory	195840 kb
Host	smart-ac6f5723-7bfb-40c6-b726-fa73d6b4849f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974988245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_ outstanding.974988245
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.2039347477
Short name	T1152
Test name
Test status
Simulation time	23526796 ps
CPU time	1.15 seconds
Started	Mar 26 12:39:47 PM PDT 24
Finished	Mar 26 12:39:48 PM PDT 24
Peak memory	200308 kb
Host	smart-65a85dde-a4e3-4567-ae09-7dc3c619025d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039347477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2039347477
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3615792006
Short name	T1245
Test name
Test status
Simulation time	58200627 ps
CPU time	0.92 seconds
Started	Mar 26 12:39:53 PM PDT 24
Finished	Mar 26 12:39:54 PM PDT 24
Peak memory	199108 kb
Host	smart-5b422802-d998-4d82-a40c-b89bde6d8eb3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615792006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3615792006
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3094330201
Short name	T1210
Test name
Test status
Simulation time	24476719 ps
CPU time	1.22 seconds
Started	Mar 26 12:40:05 PM PDT 24
Finished	Mar 26 12:40:06 PM PDT 24
Peak memory	200244 kb
Host	smart-ec11b5f4-a26c-4497-841b-614e4770f28d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094330201 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3094330201
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.2703939791
Short name	T1166
Test name
Test status
Simulation time	20514604 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:11 PM PDT 24
Finished	Mar 26 12:40:16 PM PDT 24
Peak memory	195660 kb
Host	smart-591954ce-d212-45f6-8319-af2e643b8530
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703939791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2703939791
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.614424313
Short name	T1192
Test name
Test status
Simulation time	49515222 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	195088 kb
Host	smart-84128a7c-abff-4a47-8bf7-f567799e2a66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614424313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.614424313
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1998202902
Short name	T1249
Test name
Test status
Simulation time	86770984 ps
CPU time	0.7 seconds
Started	Mar 26 12:39:51 PM PDT 24
Finished	Mar 26 12:39:52 PM PDT 24
Peak memory	195252 kb
Host	smart-7de007db-f08c-4aa4-97e6-e0342d97dfa8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998202902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.1998202902
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.3911603951
Short name	T1146
Test name
Test status
Simulation time	84939830 ps
CPU time	1.4 seconds
Started	Mar 26 12:39:56 PM PDT 24
Finished	Mar 26 12:39:58 PM PDT 24
Peak memory	200304 kb
Host	smart-4e958b6e-c120-4ed1-a6f9-ade96f2951f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911603951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3911603951
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3369580469
Short name	T1160
Test name
Test status
Simulation time	31154930 ps
CPU time	0.7 seconds
Started	Mar 26 12:39:56 PM PDT 24
Finished	Mar 26 12:39:57 PM PDT 24
Peak memory	197592 kb
Host	smart-e8e911b4-9e4d-4ba7-80bf-e8d9adf72d95
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369580469 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3369580469
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.3285082856
Short name	T1173
Test name
Test status
Simulation time	15312358 ps
CPU time	0.6 seconds
Started	Mar 26 12:40:01 PM PDT 24
Finished	Mar 26 12:40:02 PM PDT 24
Peak memory	195844 kb
Host	smart-82bd010d-beea-4b08-866f-1454dc3c074e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285082856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3285082856
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.3277259623
Short name	T1134
Test name
Test status
Simulation time	65091057 ps
CPU time	0.54 seconds
Started	Mar 26 12:39:55 PM PDT 24
Finished	Mar 26 12:39:56 PM PDT 24
Peak memory	194720 kb
Host	smart-ea48c98b-5d37-4ca2-8c62-d2aebcbe3849
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277259623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3277259623
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3454289232
Short name	T1156
Test name
Test status
Simulation time	16835614 ps
CPU time	0.71 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:59 PM PDT 24
Peak memory	196004 kb
Host	smart-0ac1ba95-2b18-43fd-a266-543f9ad627b5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454289232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3454289232
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.2928259257
Short name	T1200
Test name
Test status
Simulation time	155906715 ps
CPU time	2.02 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	200320 kb
Host	smart-ea7cfd21-ab67-45e4-8d88-4abf5f9a8c4a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928259257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2928259257
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.169864947
Short name	T1149
Test name
Test status
Simulation time	40396018 ps
CPU time	0.99 seconds
Started	Mar 26 12:40:03 PM PDT 24
Finished	Mar 26 12:40:04 PM PDT 24
Peak memory	199172 kb
Host	smart-3ab96b79-386c-4ec9-a04d-931bb029f39b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169864947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.169864947
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.379001321
Short name	T1182
Test name
Test status
Simulation time	20725521 ps
CPU time	1.13 seconds
Started	Mar 26 12:39:53 PM PDT 24
Finished	Mar 26 12:39:54 PM PDT 24
Peak memory	200532 kb
Host	smart-0d3dfc0e-2b0c-4383-8dee-efd848dd463c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379001321 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.379001321
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.2636105457
Short name	T1157
Test name
Test status
Simulation time	13192974 ps
CPU time	0.6 seconds
Started	Mar 26 12:40:01 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	195696 kb
Host	smart-1dd2f814-d73d-4a35-95c3-fcb913809dd7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636105457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2636105457
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.1217484905
Short name	T1213
Test name
Test status
Simulation time	15505709 ps
CPU time	0.63 seconds
Started	Mar 26 12:40:03 PM PDT 24
Finished	Mar 26 12:40:04 PM PDT 24
Peak memory	194736 kb
Host	smart-7d01146e-fea1-4100-925f-608fd8af0207
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217484905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1217484905
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1495754810
Short name	T1234
Test name
Test status
Simulation time	12695695 ps
CPU time	0.64 seconds
Started	Mar 26 12:40:05 PM PDT 24
Finished	Mar 26 12:40:06 PM PDT 24
Peak memory	195996 kb
Host	smart-4a2d3551-856e-4100-bb86-c52fc8015a07
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495754810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.1495754810
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.1754923641
Short name	T1228
Test name
Test status
Simulation time	72994024 ps
CPU time	1.74 seconds
Started	Mar 26 12:39:50 PM PDT 24
Finished	Mar 26 12:39:52 PM PDT 24
Peak memory	200340 kb
Host	smart-c8ca6aee-e478-470b-bd03-32a5641f6f25
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754923641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1754923641
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.947702787
Short name	T102
Test name
Test status
Simulation time	417910835 ps
CPU time	1.4 seconds
Started	Mar 26 12:40:00 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	199792 kb
Host	smart-e3e23198-b015-48e7-9ea5-58707c127654
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947702787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.947702787
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2265623644
Short name	T1128
Test name
Test status
Simulation time	279108639 ps
CPU time	0.94 seconds
Started	Mar 26 12:40:09 PM PDT 24
Finished	Mar 26 12:40:10 PM PDT 24
Peak memory	200136 kb
Host	smart-c23d7069-6794-4ba4-8e48-1aaabaf5fa04
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265623644 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2265623644
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.2465979601
Short name	T80
Test name
Test status
Simulation time	79796551 ps
CPU time	0.68 seconds
Started	Mar 26 12:39:56 PM PDT 24
Finished	Mar 26 12:39:57 PM PDT 24
Peak memory	195564 kb
Host	smart-278d553f-e769-48f1-a688-ca7015c2d385
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465979601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2465979601
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.3207965004
Short name	T1225
Test name
Test status
Simulation time	15070869 ps
CPU time	0.56 seconds
Started	Mar 26 12:39:57 PM PDT 24
Finished	Mar 26 12:39:58 PM PDT 24
Peak memory	194652 kb
Host	smart-5de02281-fa4d-4823-8e4f-6876636f00c2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207965004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3207965004
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3855369177
Short name	T1254
Test name
Test status
Simulation time	39783585 ps
CPU time	0.62 seconds
Started	Mar 26 12:39:54 PM PDT 24
Finished	Mar 26 12:39:56 PM PDT 24
Peak memory	196024 kb
Host	smart-f44993d8-a5e8-4d3d-9ad8-1bcf8c1c3c0f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855369177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.3855369177
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.1928192448
Short name	T1190
Test name
Test status
Simulation time	115904731 ps
CPU time	1.09 seconds
Started	Mar 26 12:40:09 PM PDT 24
Finished	Mar 26 12:40:10 PM PDT 24
Peak memory	200344 kb
Host	smart-faab90d6-8421-4203-a965-b580966c61e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928192448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1928192448
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3222460081
Short name	T108
Test name
Test status
Simulation time	105108963 ps
CPU time	1.04 seconds
Started	Mar 26 12:39:56 PM PDT 24
Finished	Mar 26 12:39:58 PM PDT 24
Peak memory	199136 kb
Host	smart-4fae6714-947d-4946-b099-9908ef127f56
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222460081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3222460081
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2324236826
Short name	T1209
Test name
Test status
Simulation time	99532804 ps
CPU time	0.79 seconds
Started	Mar 26 12:40:17 PM PDT 24
Finished	Mar 26 12:40:18 PM PDT 24
Peak memory	200260 kb
Host	smart-08b440de-44a9-4567-ad92-7b750d1e5a59
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324236826 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2324236826
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.3442490347
Short name	T1235
Test name
Test status
Simulation time	12362776 ps
CPU time	0.61 seconds
Started	Mar 26 12:40:11 PM PDT 24
Finished	Mar 26 12:40:12 PM PDT 24
Peak memory	195724 kb
Host	smart-8daa86f3-82ef-45d4-ad75-72729b435643
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442490347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3442490347
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.2609558878
Short name	T1229
Test name
Test status
Simulation time	33939451 ps
CPU time	0.6 seconds
Started	Mar 26 12:40:03 PM PDT 24
Finished	Mar 26 12:40:04 PM PDT 24
Peak memory	194688 kb
Host	smart-a80c7366-50f9-422b-8566-3438aa845ee3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609558878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2609558878
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.858430248
Short name	T96
Test name
Test status
Simulation time	17350406 ps
CPU time	0.69 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	196176 kb
Host	smart-dbf420c6-d323-431c-9e0d-efb79346c1ee
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858430248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr _outstanding.858430248
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.982863877
Short name	T1216
Test name
Test status
Simulation time	229263677 ps
CPU time	2.29 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:40:00 PM PDT 24
Peak memory	200336 kb
Host	smart-a1298a1b-ccfe-4b68-bf7c-933e8fcc926a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982863877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.982863877
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4134413261
Short name	T1144
Test name
Test status
Simulation time	404108597 ps
CPU time	1.34 seconds
Started	Mar 26 12:39:53 PM PDT 24
Finished	Mar 26 12:39:55 PM PDT 24
Peak memory	199600 kb
Host	smart-e43bdea1-223d-4791-8fa5-8ab4c0c61ccb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134413261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4134413261
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3973087344
Short name	T1230
Test name
Test status
Simulation time	28151206 ps
CPU time	0.73 seconds
Started	Mar 26 12:40:05 PM PDT 24
Finished	Mar 26 12:40:05 PM PDT 24
Peak memory	199168 kb
Host	smart-2cdc4974-1226-4c12-807c-87e081db9b54
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973087344 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3973087344
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.1772149333
Short name	T1214
Test name
Test status
Simulation time	65512527 ps
CPU time	0.59 seconds
Started	Mar 26 12:40:11 PM PDT 24
Finished	Mar 26 12:40:12 PM PDT 24
Peak memory	195772 kb
Host	smart-6adfca26-fb88-4e9e-990a-980b121c9d81
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772149333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1772149333
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.2922502078
Short name	T1142
Test name
Test status
Simulation time	87721116 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	194624 kb
Host	smart-90069f68-6364-4602-ae81-9df6cf5beef6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922502078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2922502078
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1515592538
Short name	T1236
Test name
Test status
Simulation time	49665430 ps
CPU time	0.77 seconds
Started	Mar 26 12:40:10 PM PDT 24
Finished	Mar 26 12:40:11 PM PDT 24
Peak memory	197832 kb
Host	smart-c42fea2a-2f06-464b-9083-2f8202663e39
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515592538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.1515592538
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.2648503140
Short name	T1198
Test name
Test status
Simulation time	54921958 ps
CPU time	1.39 seconds
Started	Mar 26 12:40:27 PM PDT 24
Finished	Mar 26 12:40:29 PM PDT 24
Peak memory	200304 kb
Host	smart-c3243e23-72dd-4b9d-9f2e-4c82b4410559
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648503140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2648503140
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.481320574
Short name	T105
Test name
Test status
Simulation time	155906224 ps
CPU time	0.86 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	199268 kb
Host	smart-693fa68e-9338-4d74-b789-c4e8bc28a464
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481320574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.481320574
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1151102899
Short name	T1255
Test name
Test status
Simulation time	25510644 ps
CPU time	0.77 seconds
Started	Mar 26 12:40:18 PM PDT 24
Finished	Mar 26 12:40:18 PM PDT 24
Peak memory	199380 kb
Host	smart-a27b9c1c-3d3d-4ed3-9d84-cb874700bf54
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151102899 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1151102899
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.3557986743
Short name	T1248
Test name
Test status
Simulation time	16043137 ps
CPU time	0.61 seconds
Started	Mar 26 12:40:02 PM PDT 24
Finished	Mar 26 12:40:03 PM PDT 24
Peak memory	195924 kb
Host	smart-1da76ac5-7539-4903-8ad2-fa5a318d33fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557986743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3557986743
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.986713274
Short name	T1138
Test name
Test status
Simulation time	11899249 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:13 PM PDT 24
Finished	Mar 26 12:40:14 PM PDT 24
Peak memory	194652 kb
Host	smart-ad003b0a-a7d1-4132-9512-16afcc54316f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986713274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.986713274
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2037729901
Short name	T1241
Test name
Test status
Simulation time	310830093 ps
CPU time	0.99 seconds
Started	Mar 26 12:40:12 PM PDT 24
Finished	Mar 26 12:40:14 PM PDT 24
Peak memory	197296 kb
Host	smart-20417f5a-41d6-429a-8ee8-5573fee89cc2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037729901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.2037729901
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.782744800
Short name	T1224
Test name
Test status
Simulation time	106279695 ps
CPU time	0.87 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	200188 kb
Host	smart-f26293d8-e049-47d2-81d3-9a78e2fc3425
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782744800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.782744800
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.393670481
Short name	T111
Test name
Test status
Simulation time	66031087 ps
CPU time	0.93 seconds
Started	Mar 26 12:40:17 PM PDT 24
Finished	Mar 26 12:40:18 PM PDT 24
Peak memory	199380 kb
Host	smart-19970b64-36ad-42ea-a219-e21fb245114d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393670481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.393670481
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1829480394
Short name	T1204
Test name
Test status
Simulation time	111212284 ps
CPU time	0.84 seconds
Started	Mar 26 12:40:10 PM PDT 24
Finished	Mar 26 12:40:11 PM PDT 24
Peak memory	200136 kb
Host	smart-d1d0c354-be7e-43dd-afde-3f4b90eeda82
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829480394 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1829480394
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.3895169098
Short name	T91
Test name
Test status
Simulation time	89949144 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	195572 kb
Host	smart-09a2b27b-1232-4de6-a4db-7706f8e868d1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895169098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3895169098
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.2965149760
Short name	T1130
Test name
Test status
Simulation time	47511382 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:30 PM PDT 24
Finished	Mar 26 12:40:31 PM PDT 24
Peak memory	194660 kb
Host	smart-0d3ed5b4-b845-407e-92a6-9565822f5f6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965149760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2965149760
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.21786467
Short name	T1159
Test name
Test status
Simulation time	51475173 ps
CPU time	0.8 seconds
Started	Mar 26 12:40:13 PM PDT 24
Finished	Mar 26 12:40:14 PM PDT 24
Peak memory	197400 kb
Host	smart-3997f72b-d42c-4e59-80cf-6b821539dc8d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21786467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_ outstanding.21786467
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.1490120078
Short name	T1205
Test name
Test status
Simulation time	51572077 ps
CPU time	1.4 seconds
Started	Mar 26 12:40:17 PM PDT 24
Finished	Mar 26 12:40:19 PM PDT 24
Peak memory	200428 kb
Host	smart-bf5ef178-965e-4581-a6f1-4b1037086127
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490120078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1490120078
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2764863382
Short name	T112
Test name
Test status
Simulation time	52822388 ps
CPU time	1.06 seconds
Started	Mar 26 12:40:12 PM PDT 24
Finished	Mar 26 12:40:14 PM PDT 24
Peak memory	199340 kb
Host	smart-9f5c5289-c018-47b7-93c7-7204d53a4444
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764863382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2764863382
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.141409692
Short name	T1208
Test name
Test status
Simulation time	51973622 ps
CPU time	0.83 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	200236 kb
Host	smart-06195dcb-c383-46b7-8271-b1ccf6f80a37
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141409692 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.141409692
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.1869101192
Short name	T92
Test name
Test status
Simulation time	38137253 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:05 PM PDT 24
Finished	Mar 26 12:40:05 PM PDT 24
Peak memory	195708 kb
Host	smart-ec260a48-d41a-4700-941f-b86c99e310b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869101192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1869101192
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.650171746
Short name	T1207
Test name
Test status
Simulation time	13981097 ps
CPU time	0.63 seconds
Started	Mar 26 12:40:09 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	194768 kb
Host	smart-3d5b41ef-b750-4f89-a935-986b6efad67b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650171746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.650171746
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3381147505
Short name	T98
Test name
Test status
Simulation time	14713348 ps
CPU time	0.65 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	196148 kb
Host	smart-36444fc8-d683-45fc-97c2-236f3c04af79
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381147505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.3381147505
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.2843890279
Short name	T1237
Test name
Test status
Simulation time	72366544 ps
CPU time	1.42 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	200344 kb
Host	smart-a75b80c6-1327-4aea-aa47-1a2335400d7b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843890279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2843890279
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2217793315
Short name	T159
Test name
Test status
Simulation time	51559784 ps
CPU time	0.9 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	199176 kb
Host	smart-47f21ea3-4e57-4707-9fd7-bab92d7dbf2a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217793315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2217793315
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3336033750
Short name	T1162
Test name
Test status
Simulation time	17002874 ps
CPU time	0.71 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	198884 kb
Host	smart-da812df3-02c1-4a4c-826d-2b57c534ec8a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336033750 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3336033750
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.3768079494
Short name	T72
Test name
Test status
Simulation time	12489262 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:09 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	195760 kb
Host	smart-ade21acf-0355-4a83-902e-e0ec4f529ab5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768079494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3768079494
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.2749262834
Short name	T1155
Test name
Test status
Simulation time	12615337 ps
CPU time	0.54 seconds
Started	Mar 26 12:40:04 PM PDT 24
Finished	Mar 26 12:40:04 PM PDT 24
Peak memory	194696 kb
Host	smart-4fab1818-5998-4412-b0aa-edf6f93fd816
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749262834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2749262834
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.34056556
Short name	T1186
Test name
Test status
Simulation time	28001560 ps
CPU time	0.72 seconds
Started	Mar 26 12:40:17 PM PDT 24
Finished	Mar 26 12:40:18 PM PDT 24
Peak memory	197444 kb
Host	smart-09ba6a73-c067-4c72-96d9-79ef0c5742f3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34056556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_ outstanding.34056556
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.681571155
Short name	T1161
Test name
Test status
Simulation time	123185507 ps
CPU time	1.72 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:10 PM PDT 24
Peak memory	200296 kb
Host	smart-53b16b5e-7fab-4e6b-b715-115fc76ba4c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681571155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.681571155
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2025365162
Short name	T1206
Test name
Test status
Simulation time	44368626 ps
CPU time	0.86 seconds
Started	Mar 26 12:40:18 PM PDT 24
Finished	Mar 26 12:40:19 PM PDT 24
Peak memory	199296 kb
Host	smart-11fe7a32-f9e1-4676-a4c1-86a4b407db51
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025365162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2025365162
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.967462933
Short name	T1187
Test name
Test status
Simulation time	22553587 ps
CPU time	0.65 seconds
Started	Mar 26 12:39:52 PM PDT 24
Finished	Mar 26 12:39:53 PM PDT 24
Peak memory	195708 kb
Host	smart-d58fc214-b938-490b-987d-1a8f3c9b65bd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967462933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.967462933
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1349748513
Short name	T78
Test name
Test status
Simulation time	38018874 ps
CPU time	1.41 seconds
Started	Mar 26 12:39:46 PM PDT 24
Finished	Mar 26 12:39:48 PM PDT 24
Peak memory	198300 kb
Host	smart-df19c627-cb67-49a6-9f7e-8477bccbb8ee
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349748513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1349748513
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3047181850
Short name	T81
Test name
Test status
Simulation time	51250666 ps
CPU time	0.54 seconds
Started	Mar 26 12:39:51 PM PDT 24
Finished	Mar 26 12:39:52 PM PDT 24
Peak memory	195704 kb
Host	smart-89c92d0d-bc0a-4bad-bdd1-933e3ae8fdaf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047181850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3047181850
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1141945184
Short name	T1242
Test name
Test status
Simulation time	26562885 ps
CPU time	0.74 seconds
Started	Mar 26 12:39:50 PM PDT 24
Finished	Mar 26 12:39:51 PM PDT 24
Peak memory	198604 kb
Host	smart-834f6fac-0576-4c8a-8abe-afe2cf7cfc5d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141945184 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1141945184
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.2927425744
Short name	T1226
Test name
Test status
Simulation time	36669794 ps
CPU time	0.57 seconds
Started	Mar 26 12:39:52 PM PDT 24
Finished	Mar 26 12:39:53 PM PDT 24
Peak memory	195668 kb
Host	smart-af62c9ce-835b-4142-a0c6-b5ff93db17fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927425744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2927425744
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.1429810638
Short name	T1218
Test name
Test status
Simulation time	42073109 ps
CPU time	0.6 seconds
Started	Mar 26 12:39:52 PM PDT 24
Finished	Mar 26 12:39:52 PM PDT 24
Peak memory	194720 kb
Host	smart-959ee970-0354-455e-b6e5-c32b7ec7d76f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429810638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1429810638
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.479880838
Short name	T1176
Test name
Test status
Simulation time	104065916 ps
CPU time	0.66 seconds
Started	Mar 26 12:39:57 PM PDT 24
Finished	Mar 26 12:39:58 PM PDT 24
Peak memory	195912 kb
Host	smart-9aae9b59-1c8e-4d3e-abee-2209a3451808
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479880838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_ outstanding.479880838
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2567840063
Short name	T1221
Test name
Test status
Simulation time	109521735 ps
CPU time	1.95 seconds
Started	Mar 26 12:39:48 PM PDT 24
Finished	Mar 26 12:39:50 PM PDT 24
Peak memory	200272 kb
Host	smart-9c2a34c1-4db5-405b-8f2a-89bb8c0a161c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567840063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2567840063
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.558707628
Short name	T1219
Test name
Test status
Simulation time	323262367 ps
CPU time	1.28 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	199744 kb
Host	smart-08ac06fa-d2ce-4fd6-b589-ce98ac9f37b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558707628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.558707628
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.2002801456
Short name	T1212
Test name
Test status
Simulation time	14174206 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:07 PM PDT 24
Finished	Mar 26 12:40:08 PM PDT 24
Peak memory	194712 kb
Host	smart-715e0ebb-71d2-432c-9199-1952ad72ec96
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002801456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2002801456
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.41729848
Short name	T1233
Test name
Test status
Simulation time	36870098 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:15 PM PDT 24
Finished	Mar 26 12:40:16 PM PDT 24
Peak memory	195068 kb
Host	smart-c7185bed-dc5f-4d00-9c3e-bb245d14b0b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41729848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.41729848
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.3721724655
Short name	T1194
Test name
Test status
Simulation time	25043272 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:11 PM PDT 24
Finished	Mar 26 12:40:11 PM PDT 24
Peak memory	194596 kb
Host	smart-9e43c7de-7e65-4e2d-8b0a-b571c95aeb91
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721724655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3721724655
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.1554713143
Short name	T1183
Test name
Test status
Simulation time	45858763 ps
CPU time	0.59 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	194768 kb
Host	smart-cbc41606-a6a4-4caf-9c0a-0c4398ed2e11
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554713143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1554713143
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.1153856154
Short name	T1147
Test name
Test status
Simulation time	58976556 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:04 PM PDT 24
Finished	Mar 26 12:40:05 PM PDT 24
Peak memory	194804 kb
Host	smart-df5bd38d-ecee-478d-b684-33ecf206e77a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153856154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1153856154
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1749384489
Short name	T1222
Test name
Test status
Simulation time	14402123 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:06 PM PDT 24
Peak memory	194676 kb
Host	smart-8dbd8eae-5a4c-420e-b75c-952f4e48fcf0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749384489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1749384489
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.1663703629
Short name	T1177
Test name
Test status
Simulation time	32149897 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:05 PM PDT 24
Finished	Mar 26 12:40:05 PM PDT 24
Peak memory	194620 kb
Host	smart-23666516-4b7a-4247-b13e-c75283c3ceca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663703629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1663703629
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.3252412394
Short name	T1131
Test name
Test status
Simulation time	39273377 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:46 PM PDT 24
Finished	Mar 26 12:40:47 PM PDT 24
Peak memory	194728 kb
Host	smart-70f9409a-047e-4293-b454-96517b2e5a29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252412394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3252412394
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.1817845284
Short name	T1164
Test name
Test status
Simulation time	45327748 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:06 PM PDT 24
Peak memory	194644 kb
Host	smart-58dd9ea7-36f1-4b1f-9580-60ee3dc6858d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817845284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1817845284
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.332584818
Short name	T1151
Test name
Test status
Simulation time	14821188 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:08 PM PDT 24
Peak memory	194696 kb
Host	smart-906320d9-a56c-47cc-9eef-a20e2723ba2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332584818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.332584818
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1927093123
Short name	T75
Test name
Test status
Simulation time	16249892 ps
CPU time	0.77 seconds
Started	Mar 26 12:39:49 PM PDT 24
Finished	Mar 26 12:39:49 PM PDT 24
Peak memory	196428 kb
Host	smart-90ed25da-c020-4b83-b0cb-c9337ad902d6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927093123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1927093123
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4132940042
Short name	T1223
Test name
Test status
Simulation time	346980142 ps
CPU time	2.49 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	198128 kb
Host	smart-ae07379b-9851-4259-a3e1-66080057a838
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132940042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4132940042
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.922559515
Short name	T74
Test name
Test status
Simulation time	30122678 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:01 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	195680 kb
Host	smart-1769151f-9667-4153-9550-ecd50eb09d5b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922559515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.922559515
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2978853780
Short name	T1185
Test name
Test status
Simulation time	68480151 ps
CPU time	0.73 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:00 PM PDT 24
Peak memory	198956 kb
Host	smart-6d2e0c6a-b76d-4f27-af6a-e452ab631f91
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978853780 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2978853780
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.1034360011
Short name	T97
Test name
Test status
Simulation time	16234380 ps
CPU time	0.63 seconds
Started	Mar 26 12:39:50 PM PDT 24
Finished	Mar 26 12:39:51 PM PDT 24
Peak memory	195672 kb
Host	smart-9cd978e2-1e28-4332-9928-94aabc70666b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034360011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1034360011
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.3251438088
Short name	T1256
Test name
Test status
Simulation time	18338176 ps
CPU time	0.59 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:00 PM PDT 24
Peak memory	194640 kb
Host	smart-f32b5e32-82fe-4292-b293-f4efb956d998
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251438088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3251438088
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3528437877
Short name	T1238
Test name
Test status
Simulation time	79422484 ps
CPU time	0.7 seconds
Started	Mar 26 12:39:53 PM PDT 24
Finished	Mar 26 12:39:54 PM PDT 24
Peak memory	195344 kb
Host	smart-d13ba4f9-c336-48c1-a8d0-c92a9b748d7e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528437877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.3528437877
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.3494876097
Short name	T1253
Test name
Test status
Simulation time	26410985 ps
CPU time	1.13 seconds
Started	Mar 26 12:39:55 PM PDT 24
Finished	Mar 26 12:39:57 PM PDT 24
Peak memory	200280 kb
Host	smart-53f6b9de-3155-4fc8-ad98-532213422eb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494876097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3494876097
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1573673865
Short name	T109
Test name
Test status
Simulation time	339408049 ps
CPU time	1.23 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:08 PM PDT 24
Peak memory	199696 kb
Host	smart-95b5da77-92e3-4335-8dae-20cab58f5567
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573673865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1573673865
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.1483365641
Short name	T1179
Test name
Test status
Simulation time	32163220 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:09 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	194632 kb
Host	smart-a95287f0-b35c-4992-967d-0cb50285cc00
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483365641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1483365641
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.124977505
Short name	T1246
Test name
Test status
Simulation time	22168390 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:17 PM PDT 24
Finished	Mar 26 12:40:18 PM PDT 24
Peak memory	194688 kb
Host	smart-4aa4989a-f989-4a98-9791-2c638feb94fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124977505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.124977505
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.3140524709
Short name	T1220
Test name
Test status
Simulation time	23002725 ps
CPU time	0.59 seconds
Started	Mar 26 12:40:11 PM PDT 24
Finished	Mar 26 12:40:11 PM PDT 24
Peak memory	194668 kb
Host	smart-004b7c4d-c7ed-4b33-936e-60ed2e9de38f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140524709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3140524709
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.1712800588
Short name	T1172
Test name
Test status
Simulation time	42743452 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:18 PM PDT 24
Finished	Mar 26 12:40:18 PM PDT 24
Peak memory	194688 kb
Host	smart-86de1859-bbf9-486b-bff1-3c69fc7dfc1a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712800588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1712800588
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.3286531023
Short name	T1197
Test name
Test status
Simulation time	39454683 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:07 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	194740 kb
Host	smart-b4864bdd-6a95-4913-9158-c95d698a1da8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286531023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3286531023
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.1575356053
Short name	T1189
Test name
Test status
Simulation time	33597901 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:12 PM PDT 24
Finished	Mar 26 12:40:13 PM PDT 24
Peak memory	194612 kb
Host	smart-cf7af026-8205-4281-83ad-4ba3e6192809
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575356053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1575356053
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.1516996791
Short name	T1132
Test name
Test status
Simulation time	42492103 ps
CPU time	0.64 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	194676 kb
Host	smart-4c196ed7-9d26-4603-8427-d9aebee41f5a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516996791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1516996791
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.209075038
Short name	T1203
Test name
Test status
Simulation time	15228840 ps
CPU time	0.59 seconds
Started	Mar 26 12:40:09 PM PDT 24
Finished	Mar 26 12:40:10 PM PDT 24
Peak memory	194768 kb
Host	smart-d58e3521-d620-4d4d-88b2-ecc0aeeb6ada
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209075038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.209075038
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.3337357271
Short name	T1195
Test name
Test status
Simulation time	11675767 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:17 PM PDT 24
Finished	Mar 26 12:40:18 PM PDT 24
Peak memory	194748 kb
Host	smart-89956bb9-5aa3-47da-a864-023f22b0f5eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337357271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3337357271
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.1104002827
Short name	T1217
Test name
Test status
Simulation time	23133466 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	194716 kb
Host	smart-55c016b2-ee5f-48fc-942f-265591c7f4d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104002827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1104002827
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.629473915
Short name	T73
Test name
Test status
Simulation time	67334941 ps
CPU time	0.61 seconds
Started	Mar 26 12:40:16 PM PDT 24
Finished	Mar 26 12:40:16 PM PDT 24
Peak memory	195216 kb
Host	smart-c01d3657-8648-4c05-9db3-e366c8c77595
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629473915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.629473915
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2939990601
Short name	T1133
Test name
Test status
Simulation time	89642499 ps
CPU time	1.46 seconds
Started	Mar 26 12:40:12 PM PDT 24
Finished	Mar 26 12:40:14 PM PDT 24
Peak memory	198252 kb
Host	smart-4f1bc4e3-bfa0-434e-8b2d-3c8c7e9144bc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939990601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2939990601
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.31613562
Short name	T1196
Test name
Test status
Simulation time	78505329 ps
CPU time	0.69 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:00 PM PDT 24
Peak memory	198308 kb
Host	smart-ac2ed62f-1398-43ca-9dbf-c8b5514660f2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31613562 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.31613562
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.3867268066
Short name	T1165
Test name
Test status
Simulation time	15320563 ps
CPU time	0.59 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:58 PM PDT 24
Peak memory	195784 kb
Host	smart-9afdd7c6-74f5-4f00-9783-b550bab6bceb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867268066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3867268066
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.4003214325
Short name	T1180
Test name
Test status
Simulation time	39169016 ps
CPU time	0.54 seconds
Started	Mar 26 12:40:00 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	194632 kb
Host	smart-7e6aac75-c9b7-47f9-80fa-c290cf4ccf5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003214325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4003214325
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.773436241
Short name	T1184
Test name
Test status
Simulation time	13412442 ps
CPU time	0.6 seconds
Started	Mar 26 12:40:04 PM PDT 24
Finished	Mar 26 12:40:04 PM PDT 24
Peak memory	196004 kb
Host	smart-e011cf64-62ec-41aa-a5c4-74d118ab97d8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773436241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_ outstanding.773436241
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.894805484
Short name	T1252
Test name
Test status
Simulation time	35091448 ps
CPU time	1.77 seconds
Started	Mar 26 12:39:49 PM PDT 24
Finished	Mar 26 12:39:50 PM PDT 24
Peak memory	200300 kb
Host	smart-ece4e7e3-9abf-4472-9d9f-737c93239d41
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894805484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.894805484
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.2898450073
Short name	T1215
Test name
Test status
Simulation time	41730912 ps
CPU time	0.54 seconds
Started	Mar 26 12:40:04 PM PDT 24
Finished	Mar 26 12:40:05 PM PDT 24
Peak memory	194632 kb
Host	smart-6cc3fb9a-a156-4b1d-aa90-151e115d17fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898450073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2898450073
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.2248762821
Short name	T1227
Test name
Test status
Simulation time	80211992 ps
CPU time	0.6 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	194844 kb
Host	smart-f0d94fb7-bbb5-4412-86c2-37f452185319
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248762821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2248762821
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.2545407238
Short name	T1136
Test name
Test status
Simulation time	23438667 ps
CPU time	0.55 seconds
Started	Mar 26 12:40:17 PM PDT 24
Finished	Mar 26 12:40:17 PM PDT 24
Peak memory	194668 kb
Host	smart-5eea513d-0264-43a8-85bc-c366c70e6be2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545407238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2545407238
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.2579600290
Short name	T1239
Test name
Test status
Simulation time	20784038 ps
CPU time	0.59 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	194636 kb
Host	smart-98cdd695-c1d6-4c61-9112-e94a0c1870de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579600290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2579600290
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.3061399934
Short name	T1174
Test name
Test status
Simulation time	42053599 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:07 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	194652 kb
Host	smart-d5daec6d-bf32-4f60-8d40-f0d360c6dd17
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061399934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3061399934
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.1932780108
Short name	T1188
Test name
Test status
Simulation time	46895938 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	194640 kb
Host	smart-8b91b80d-4679-4eff-8039-615ae395dc2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932780108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1932780108
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.3425116939
Short name	T1171
Test name
Test status
Simulation time	87165047 ps
CPU time	0.54 seconds
Started	Mar 26 12:40:04 PM PDT 24
Finished	Mar 26 12:40:05 PM PDT 24
Peak memory	194664 kb
Host	smart-3648e643-5560-4ccf-bf37-3be7afde07ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425116939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3425116939
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.32922155
Short name	T1178
Test name
Test status
Simulation time	13977223 ps
CPU time	0.57 seconds
Started	Mar 26 12:40:29 PM PDT 24
Finished	Mar 26 12:40:29 PM PDT 24
Peak memory	194744 kb
Host	smart-9390db2e-a0b2-4f12-af27-3bb839463bfb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.32922155
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.4069130983
Short name	T1143
Test name
Test status
Simulation time	63640632 ps
CPU time	0.59 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	194740 kb
Host	smart-267b00a2-2e9e-429f-b12a-a2e64b213c55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069130983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4069130983
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.1482924293
Short name	T1191
Test name
Test status
Simulation time	10841243 ps
CPU time	0.59 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	194704 kb
Host	smart-831f7a29-6849-4bf9-a891-4846e390ccf8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482924293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1482924293
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2463058605
Short name	T1193
Test name
Test status
Simulation time	34810078 ps
CPU time	0.62 seconds
Started	Mar 26 12:39:57 PM PDT 24
Finished	Mar 26 12:39:57 PM PDT 24
Peak memory	197920 kb
Host	smart-2b8bd199-db47-460f-b5fa-f78a4c62d1ba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463058605 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2463058605
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.2297207367
Short name	T1169
Test name
Test status
Simulation time	15718726 ps
CPU time	0.61 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	195784 kb
Host	smart-c0ea8b6e-c898-40ee-bf25-1d0331dd8f63
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297207367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2297207367
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.1469425218
Short name	T1170
Test name
Test status
Simulation time	13261482 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:05 PM PDT 24
Finished	Mar 26 12:40:06 PM PDT 24
Peak memory	194740 kb
Host	smart-131c6077-27d9-4c9c-82c6-4177174a9136
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469425218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1469425218
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2058604220
Short name	T1199
Test name
Test status
Simulation time	43191267 ps
CPU time	0.74 seconds
Started	Mar 26 12:40:03 PM PDT 24
Finished	Mar 26 12:40:04 PM PDT 24
Peak memory	197316 kb
Host	smart-bd9fcf20-0fac-4da0-8bc1-5623ac55e646
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058604220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.2058604220
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.1225048088
Short name	T1139
Test name
Test status
Simulation time	136145303 ps
CPU time	1.6 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	200420 kb
Host	smart-dbe6bf31-8523-4747-b8c2-1811c384b07c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225048088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1225048088
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1812538366
Short name	T103
Test name
Test status
Simulation time	81704575 ps
CPU time	0.93 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:59 PM PDT 24
Peak memory	199236 kb
Host	smart-1d71e157-60e2-4d95-969d-cb14ae6411ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812538366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1812538366
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.647350836
Short name	T1243
Test name
Test status
Simulation time	94607678 ps
CPU time	0.83 seconds
Started	Mar 26 12:40:05 PM PDT 24
Finished	Mar 26 12:40:06 PM PDT 24
Peak memory	200132 kb
Host	smart-0f4f1602-d3be-4beb-8773-af66f85981f8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647350836 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.647350836
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.4138532975
Short name	T1168
Test name
Test status
Simulation time	26537555 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	195664 kb
Host	smart-877e243a-c526-4455-818f-79d144118d64
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138532975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4138532975
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.3339539763
Short name	T1158
Test name
Test status
Simulation time	59519526 ps
CPU time	0.61 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:00 PM PDT 24
Peak memory	194640 kb
Host	smart-f96613c7-8ee6-4dc0-94bf-63edbcfed2f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339539763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3339539763
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1586824026
Short name	T1231
Test name
Test status
Simulation time	20023721 ps
CPU time	0.64 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	196088 kb
Host	smart-bef0c8ec-29cc-4845-8c00-ac2cd78f9661
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586824026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.1586824026
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.3734194913
Short name	T1126
Test name
Test status
Simulation time	126836116 ps
CPU time	2.6 seconds
Started	Mar 26 12:39:59 PM PDT 24
Finished	Mar 26 12:40:02 PM PDT 24
Peak memory	200420 kb
Host	smart-c5a2eb8f-72eb-45b8-aa3f-84b08e6b3921
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734194913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3734194913
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1110295091
Short name	T107
Test name
Test status
Simulation time	336792095 ps
CPU time	1.25 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	199628 kb
Host	smart-2cba9574-131e-4528-88e0-8fa260514c8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110295091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1110295091
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2829605668
Short name	T1127
Test name
Test status
Simulation time	86529641 ps
CPU time	0.76 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:59 PM PDT 24
Peak memory	198988 kb
Host	smart-eba141e1-0f27-453e-8ffe-33b25f6ccadc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829605668 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2829605668
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.3923114436
Short name	T94
Test name
Test status
Simulation time	11291645 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	195692 kb
Host	smart-79ba6877-1434-4c85-af41-6c8116f34aa9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923114436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3923114436
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.2551189906
Short name	T1141
Test name
Test status
Simulation time	12759745 ps
CPU time	0.59 seconds
Started	Mar 26 12:39:51 PM PDT 24
Finished	Mar 26 12:39:52 PM PDT 24
Peak memory	194620 kb
Host	smart-34870b42-a8cc-4b61-8c72-03555fa0804c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551189906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2551189906
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4192155060
Short name	T95
Test name
Test status
Simulation time	31420022 ps
CPU time	0.62 seconds
Started	Mar 26 12:40:01 PM PDT 24
Finished	Mar 26 12:40:02 PM PDT 24
Peak memory	196208 kb
Host	smart-b3e1b06d-d988-4ad3-880d-45bd85195f68
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192155060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.4192155060
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.818373528
Short name	T1140
Test name
Test status
Simulation time	186413942 ps
CPU time	1.17 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:59 PM PDT 24
Peak memory	200424 kb
Host	smart-c69eb5ef-9cf2-40f1-831d-1cddf621c0fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818373528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.818373528
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3966270126
Short name	T104
Test name
Test status
Simulation time	232696580 ps
CPU time	1.04 seconds
Started	Mar 26 12:39:53 PM PDT 24
Finished	Mar 26 12:39:55 PM PDT 24
Peak memory	199452 kb
Host	smart-5b126379-1c26-448b-b8b4-37b1926b7cf7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966270126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3966270126
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1022289745
Short name	T1129
Test name
Test status
Simulation time	25292774 ps
CPU time	0.73 seconds
Started	Mar 26 12:39:55 PM PDT 24
Finished	Mar 26 12:39:56 PM PDT 24
Peak memory	199392 kb
Host	smart-0efcfdc1-cccc-4805-b1d3-cfbe759fc807
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022289745 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1022289745
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.1116077101
Short name	T1232
Test name
Test status
Simulation time	29660364 ps
CPU time	0.6 seconds
Started	Mar 26 12:40:06 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	195668 kb
Host	smart-abe737b8-dea0-45b4-94df-516097de0c6d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116077101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1116077101
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.568767211
Short name	T1135
Test name
Test status
Simulation time	26228210 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:00 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	194724 kb
Host	smart-1032304c-3841-468a-b2ac-0c6b562160e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568767211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.568767211
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2040014569
Short name	T99
Test name
Test status
Simulation time	21120399 ps
CPU time	0.64 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:58 PM PDT 24
Peak memory	195916 kb
Host	smart-ebebc890-d4f7-4217-8fc8-28b136d7d102
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040014569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.2040014569
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.401446505
Short name	T1150
Test name
Test status
Simulation time	24804986 ps
CPU time	1.16 seconds
Started	Mar 26 12:40:14 PM PDT 24
Finished	Mar 26 12:40:15 PM PDT 24
Peak memory	200244 kb
Host	smart-5beaa9c3-c4bd-41d0-b74b-b91c7804c332
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401446505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.401446505
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2109779085
Short name	T160
Test name
Test status
Simulation time	780445232 ps
CPU time	1.3 seconds
Started	Mar 26 12:40:00 PM PDT 24
Finished	Mar 26 12:40:01 PM PDT 24
Peak memory	199820 kb
Host	smart-b68b1bc5-4d88-4cde-b127-d46982bda867
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109779085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2109779085
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3252991189
Short name	T1250
Test name
Test status
Simulation time	20167742 ps
CPU time	0.95 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	200104 kb
Host	smart-0e4c3b71-28d9-4c73-903b-9c3915c387c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252991189 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3252991189
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.639509359
Short name	T1251
Test name
Test status
Simulation time	41701618 ps
CPU time	0.58 seconds
Started	Mar 26 12:40:16 PM PDT 24
Finished	Mar 26 12:40:17 PM PDT 24
Peak memory	195664 kb
Host	smart-0d18a394-c8c6-48d7-b383-f18920b4c26c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639509359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.639509359
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.4132092858
Short name	T1244
Test name
Test status
Simulation time	44538178 ps
CPU time	0.56 seconds
Started	Mar 26 12:40:08 PM PDT 24
Finished	Mar 26 12:40:09 PM PDT 24
Peak memory	194644 kb
Host	smart-3ad1a2ad-cc74-4b0a-a1e8-71065977e958
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132092858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.4132092858
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2372881542
Short name	T1163
Test name
Test status
Simulation time	24270824 ps
CPU time	0.64 seconds
Started	Mar 26 12:39:58 PM PDT 24
Finished	Mar 26 12:39:59 PM PDT 24
Peak memory	195312 kb
Host	smart-bdf33557-1633-4d27-a4ac-ffc3db917eae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372881542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.2372881542
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.1734603560
Short name	T1145
Test name
Test status
Simulation time	74200965 ps
CPU time	1.38 seconds
Started	Mar 26 12:40:11 PM PDT 24
Finished	Mar 26 12:40:13 PM PDT 24
Peak memory	200336 kb
Host	smart-47df3269-e1b3-4edb-afe9-66446a5dca46
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734603560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1734603560
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/default/0.uart_alert_test.3961754846
Short name	T663
Test name
Test status
Simulation time	61852297 ps
CPU time	0.57 seconds
Started	Mar 26 02:19:29 PM PDT 24
Finished	Mar 26 02:19:30 PM PDT 24
Peak memory	195020 kb
Host	smart-60c2d540-40ca-4173-a441-c7b6383e0681
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961754846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3961754846
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.1387793977
Short name	T563
Test name
Test status
Simulation time	20984153963 ps
CPU time	32.97 seconds
Started	Mar 26 02:19:11 PM PDT 24
Finished	Mar 26 02:19:44 PM PDT 24
Peak memory	200276 kb
Host	smart-a3ba66d1-e29c-4195-8097-9caec959892c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387793977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1387793977
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.2785581287
Short name	T880
Test name
Test status
Simulation time	180311075097 ps
CPU time	29.62 seconds
Started	Mar 26 02:19:11 PM PDT 24
Finished	Mar 26 02:19:41 PM PDT 24
Peak memory	200064 kb
Host	smart-349db78b-9d2c-483e-a92c-e7125b450cde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785581287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2785581287
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.1029269086
Short name	T325
Test name
Test status
Simulation time	134503650082 ps
CPU time	62.04 seconds
Started	Mar 26 02:19:14 PM PDT 24
Finished	Mar 26 02:20:16 PM PDT 24
Peak memory	199960 kb
Host	smart-8ca6690d-f1a6-457f-bd87-d96eed842918
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029269086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1029269086
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_intr.3886765682
Short name	T1027
Test name
Test status
Simulation time	44117195574 ps
CPU time	78.91 seconds
Started	Mar 26 02:19:11 PM PDT 24
Finished	Mar 26 02:20:31 PM PDT 24
Peak memory	200052 kb
Host	smart-b448eaf6-0d3f-4ceb-96a6-04262bedf641
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886765682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3886765682
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_loopback.1394759961
Short name	T1052
Test name
Test status
Simulation time	58723579 ps
CPU time	0.71 seconds
Started	Mar 26 02:19:17 PM PDT 24
Finished	Mar 26 02:19:18 PM PDT 24
Peak memory	195980 kb
Host	smart-430ebc6d-88ca-40a0-b796-f8e3b196a46f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394759961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1394759961
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.3772202549
Short name	T398
Test name
Test status
Simulation time	76094234559 ps
CPU time	39.29 seconds
Started	Mar 26 02:19:16 PM PDT 24
Finished	Mar 26 02:19:56 PM PDT 24
Peak memory	200376 kb
Host	smart-3c669e57-5105-4cfd-9ed8-5a2422446516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772202549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3772202549
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.3977938406
Short name	T868
Test name
Test status
Simulation time	25855422583 ps
CPU time	396.07 seconds
Started	Mar 26 02:19:15 PM PDT 24
Finished	Mar 26 02:25:51 PM PDT 24
Peak memory	199904 kb
Host	smart-57ab0424-2702-4d7a-a4af-114c99f1df0c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3977938406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3977938406
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.1361819003
Short name	T617
Test name
Test status
Simulation time	5582475892 ps
CPU time	37.88 seconds
Started	Mar 26 02:19:14 PM PDT 24
Finished	Mar 26 02:19:52 PM PDT 24
Peak memory	198832 kb
Host	smart-105ddd37-7edd-4d4e-aa1a-701ecefc9cba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1361819003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1361819003
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.3468446665
Short name	T905
Test name
Test status
Simulation time	92774958506 ps
CPU time	83.02 seconds
Started	Mar 26 02:19:16 PM PDT 24
Finished	Mar 26 02:20:39 PM PDT 24
Peak memory	200076 kb
Host	smart-4c4b0546-c801-45ec-a5f8-ea66eb1647c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468446665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3468446665
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.191399758
Short name	T757
Test name
Test status
Simulation time	56391816255 ps
CPU time	87.67 seconds
Started	Mar 26 02:19:15 PM PDT 24
Finished	Mar 26 02:20:42 PM PDT 24
Peak memory	196132 kb
Host	smart-c7713412-434b-468b-ab45-c26b1d959299
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191399758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.191399758
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.1118869180
Short name	T114
Test name
Test status
Simulation time	62912045 ps
CPU time	0.9 seconds
Started	Mar 26 02:19:26 PM PDT 24
Finished	Mar 26 02:19:28 PM PDT 24
Peak memory	218392 kb
Host	smart-03ab0d23-dd9c-41f2-811e-aa03d8e03d13
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118869180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1118869180
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/default/0.uart_smoke.3137199299
Short name	T990
Test name
Test status
Simulation time	104837729 ps
CPU time	1.03 seconds
Started	Mar 26 02:19:18 PM PDT 24
Finished	Mar 26 02:19:19 PM PDT 24
Peak memory	197184 kb
Host	smart-bf43b0a9-7ad6-4188-9512-237a1ff9a688
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137199299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3137199299
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_stress_all.2879077768
Short name	T422
Test name
Test status
Simulation time	286952030088 ps
CPU time	444.06 seconds
Started	Mar 26 02:19:26 PM PDT 24
Finished	Mar 26 02:26:50 PM PDT 24
Peak memory	199984 kb
Host	smart-2230a45a-b4fe-4c11-83ba-f4f9be206004
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879077768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2879077768
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.1230705008
Short name	T815
Test name
Test status
Simulation time	6875671257 ps
CPU time	25.05 seconds
Started	Mar 26 02:19:13 PM PDT 24
Finished	Mar 26 02:19:38 PM PDT 24
Peak memory	199572 kb
Host	smart-ce902f81-72d3-4ca8-9b57-a8245e916024
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230705008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1230705008
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.388775660
Short name	T562
Test name
Test status
Simulation time	100789687759 ps
CPU time	235.11 seconds
Started	Mar 26 02:19:14 PM PDT 24
Finished	Mar 26 02:23:09 PM PDT 24
Peak memory	200064 kb
Host	smart-ff389579-9991-4210-b1b6-1d46dd03a2ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=388775660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.388775660
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/1.uart_alert_test.3384949546
Short name	T957
Test name
Test status
Simulation time	43721437 ps
CPU time	0.58 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:19:28 PM PDT 24
Peak memory	195488 kb
Host	smart-12914cb7-1b6b-4679-a915-f2d78a6a029e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384949546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3384949546
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.3441333933
Short name	T725
Test name
Test status
Simulation time	118120725254 ps
CPU time	108.72 seconds
Started	Mar 26 02:19:26 PM PDT 24
Finished	Mar 26 02:21:16 PM PDT 24
Peak memory	200052 kb
Host	smart-d1665195-b575-4cc9-9380-e5c995ed5c12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441333933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3441333933
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.2578031737
Short name	T207
Test name
Test status
Simulation time	35499386601 ps
CPU time	14.51 seconds
Started	Mar 26 02:19:30 PM PDT 24
Finished	Mar 26 02:19:45 PM PDT 24
Peak memory	200000 kb
Host	smart-5b71c46e-32da-4608-9343-904111bebf86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578031737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2578031737
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.3492670288
Short name	T874
Test name
Test status
Simulation time	42344830855 ps
CPU time	42.32 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:20:10 PM PDT 24
Peak memory	200072 kb
Host	smart-be21f627-0008-4749-8c1a-849d3cde0191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492670288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3492670288
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_intr.4212884285
Short name	T1041
Test name
Test status
Simulation time	21885226178 ps
CPU time	7.18 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:19:35 PM PDT 24
Peak memory	199544 kb
Host	smart-d65b3e9c-b55d-443d-9540-39edb362e568
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212884285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.4212884285
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.448503076
Short name	T1039
Test name
Test status
Simulation time	59779943232 ps
CPU time	316.57 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:24:45 PM PDT 24
Peak memory	200152 kb
Host	smart-e06655fd-5f8c-4bce-8043-ccfbc60f4c90
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=448503076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.448503076
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.1957468860
Short name	T1096
Test name
Test status
Simulation time	2997847695 ps
CPU time	5.43 seconds
Started	Mar 26 02:19:26 PM PDT 24
Finished	Mar 26 02:19:32 PM PDT 24
Peak memory	198092 kb
Host	smart-8791731a-1698-4d56-8d19-24e65b27d483
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957468860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1957468860
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.3309132465
Short name	T474
Test name
Test status
Simulation time	106625003622 ps
CPU time	44.12 seconds
Started	Mar 26 02:19:26 PM PDT 24
Finished	Mar 26 02:20:11 PM PDT 24
Peak memory	198868 kb
Host	smart-81a14301-c651-445b-b37c-96d6f3b08e6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309132465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3309132465
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/1.uart_perf.2218009824
Short name	T1105
Test name
Test status
Simulation time	14658727483 ps
CPU time	110.55 seconds
Started	Mar 26 02:19:30 PM PDT 24
Finished	Mar 26 02:21:21 PM PDT 24
Peak memory	200024 kb
Host	smart-05a9ade4-ea41-43d9-9044-71dd2479998b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2218009824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2218009824
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.3275474287
Short name	T598
Test name
Test status
Simulation time	3442052974 ps
CPU time	3.02 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:19:31 PM PDT 24
Peak memory	198932 kb
Host	smart-dc01b5e8-b017-49ab-9bd4-27c6b153ea59
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3275474287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3275474287
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.3350720306
Short name	T178
Test name
Test status
Simulation time	105630125576 ps
CPU time	148.58 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:21:56 PM PDT 24
Peak memory	200020 kb
Host	smart-c5619809-f03f-426b-b3c6-5d48b8216098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350720306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3350720306
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.3526180089
Short name	T709
Test name
Test status
Simulation time	41676383677 ps
CPU time	12.18 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:19:40 PM PDT 24
Peak memory	195948 kb
Host	smart-773a3e27-a97b-48cd-aec7-ff508bc711f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526180089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3526180089
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.139263223
Short name	T115
Test name
Test status
Simulation time	165774836 ps
CPU time	0.8 seconds
Started	Mar 26 02:19:29 PM PDT 24
Finished	Mar 26 02:19:30 PM PDT 24
Peak memory	218208 kb
Host	smart-537124bc-427a-4502-8056-6c1606bf494d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139263223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.139263223
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/1.uart_smoke.1623186105
Short name	T924
Test name
Test status
Simulation time	469837316 ps
CPU time	1.7 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:19:29 PM PDT 24
Peak memory	198388 kb
Host	smart-7961321d-a5c1-487f-9d11-bef0646b6f3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623186105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1623186105
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_stress_all.2997687320
Short name	T917
Test name
Test status
Simulation time	490452390872 ps
CPU time	490.42 seconds
Started	Mar 26 02:19:29 PM PDT 24
Finished	Mar 26 02:27:40 PM PDT 24
Peak memory	200080 kb
Host	smart-73be39bf-6336-4bce-87db-d10f4e107278
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997687320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2997687320
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.1349374097
Short name	T952
Test name
Test status
Simulation time	605513562 ps
CPU time	1.97 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:19:30 PM PDT 24
Peak memory	198204 kb
Host	smart-bca80e4f-c466-4eca-b6f8-196241bd877a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349374097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1349374097
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.3545707202
Short name	T149
Test name
Test status
Simulation time	64303603044 ps
CPU time	81.69 seconds
Started	Mar 26 02:19:29 PM PDT 24
Finished	Mar 26 02:20:51 PM PDT 24
Peak memory	199988 kb
Host	smart-caba4242-8aad-4a67-91e2-54eb40b33d81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545707202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3545707202
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_alert_test.4016256616
Short name	T853
Test name
Test status
Simulation time	49093425 ps
CPU time	0.6 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:20:43 PM PDT 24
Peak memory	195512 kb
Host	smart-df733776-ed32-4a53-8c2a-7c78f2fb4a24
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016256616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.4016256616
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.3539139125
Short name	T655
Test name
Test status
Simulation time	127325724268 ps
CPU time	94.71 seconds
Started	Mar 26 02:20:43 PM PDT 24
Finished	Mar 26 02:22:18 PM PDT 24
Peak memory	200044 kb
Host	smart-124d0ecd-0f4f-4d44-a13b-09ddfc9ec7e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539139125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3539139125
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.1900023496
Short name	T624
Test name
Test status
Simulation time	165534698166 ps
CPU time	73.51 seconds
Started	Mar 26 02:20:39 PM PDT 24
Finished	Mar 26 02:21:53 PM PDT 24
Peak memory	200096 kb
Host	smart-a49c6c84-27f0-48b2-bd51-1fbc99b16c85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900023496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1900023496
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.1705637989
Short name	T754
Test name
Test status
Simulation time	79774792960 ps
CPU time	71.91 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:21:54 PM PDT 24
Peak memory	200136 kb
Host	smart-29aa3da4-141f-4a82-94d3-f676d76d1339
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705637989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1705637989
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_intr.452616012
Short name	T721
Test name
Test status
Simulation time	20596174434 ps
CPU time	17.31 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:20:59 PM PDT 24
Peak memory	198568 kb
Host	smart-6d42f590-4b59-4e7d-824f-05f356a2a607
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452616012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.452616012
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.333988546
Short name	T304
Test name
Test status
Simulation time	82516596493 ps
CPU time	285.76 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:25:27 PM PDT 24
Peak memory	199972 kb
Host	smart-17c9426c-1f42-48d6-b521-8b7131430fec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=333988546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.333988546
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.3571335874
Short name	T637
Test name
Test status
Simulation time	8413805273 ps
CPU time	8.04 seconds
Started	Mar 26 02:20:40 PM PDT 24
Finished	Mar 26 02:20:49 PM PDT 24
Peak memory	199968 kb
Host	smart-7f5c394e-90e8-40e9-ac63-0a292e5250e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3571335874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3571335874
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_noise_filter.1625210039
Short name	T1114
Test name
Test status
Simulation time	48423734998 ps
CPU time	67.35 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:21:49 PM PDT 24
Peak memory	198760 kb
Host	smart-328812b1-fb2c-4b15-abb5-a767fe7a7b0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625210039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1625210039
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/10.uart_perf.1121161210
Short name	T145
Test name
Test status
Simulation time	15655166610 ps
CPU time	480.54 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:28:43 PM PDT 24
Peak memory	200008 kb
Host	smart-c6f95a55-d259-48fa-b35b-44bd2b7e0bc3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1121161210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1121161210
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.4069192892
Short name	T910
Test name
Test status
Simulation time	6950862310 ps
CPU time	15.24 seconds
Started	Mar 26 02:20:40 PM PDT 24
Finished	Mar 26 02:20:55 PM PDT 24
Peak memory	199216 kb
Host	smart-fa7bb36f-073d-4ad4-80eb-82da712fea32
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4069192892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4069192892
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.1101055534
Short name	T732
Test name
Test status
Simulation time	56060448445 ps
CPU time	40.88 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:21:22 PM PDT 24
Peak memory	199620 kb
Host	smart-9c278f79-865f-4508-b6e3-69600e364f8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101055534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1101055534
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.1663801255
Short name	T141
Test name
Test status
Simulation time	3505886907 ps
CPU time	2.11 seconds
Started	Mar 26 02:20:47 PM PDT 24
Finished	Mar 26 02:20:49 PM PDT 24
Peak memory	196088 kb
Host	smart-0b345ccb-aa95-48ab-abeb-bedb4daf1b64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663801255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1663801255
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.2003525545
Short name	T942
Test name
Test status
Simulation time	666675508 ps
CPU time	1.88 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:20:43 PM PDT 24
Peak memory	198916 kb
Host	smart-5fd8d673-45ee-4684-b326-075f164363b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003525545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2003525545
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_stress_all.1163502035
Short name	T507
Test name
Test status
Simulation time	158668827074 ps
CPU time	1624.4 seconds
Started	Mar 26 02:20:48 PM PDT 24
Finished	Mar 26 02:47:52 PM PDT 24
Peak memory	200016 kb
Host	smart-8813d66e-21e1-4027-a8d3-d36f14a8f9a9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163502035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1163502035
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.3548138225
Short name	T514
Test name
Test status
Simulation time	1161510700 ps
CPU time	4.09 seconds
Started	Mar 26 02:20:44 PM PDT 24
Finished	Mar 26 02:20:48 PM PDT 24
Peak memory	200068 kb
Host	smart-68f35d6a-756d-4209-9966-0d3c87984c32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548138225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3548138225
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.1562966311
Short name	T974
Test name
Test status
Simulation time	41455629115 ps
CPU time	33.1 seconds
Started	Mar 26 02:20:43 PM PDT 24
Finished	Mar 26 02:21:16 PM PDT 24
Peak memory	200036 kb
Host	smart-14d36c0c-4a3d-4fc8-955d-c200ceb82a66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562966311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1562966311
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.2264270757
Short name	T370
Test name
Test status
Simulation time	99308213716 ps
CPU time	150.15 seconds
Started	Mar 26 02:28:17 PM PDT 24
Finished	Mar 26 02:30:47 PM PDT 24
Peak memory	200052 kb
Host	smart-f11a1400-75f1-475c-8354-e7fb1b7656df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264270757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2264270757
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.3682479986
Short name	T227
Test name
Test status
Simulation time	341742929165 ps
CPU time	100.88 seconds
Started	Mar 26 02:28:18 PM PDT 24
Finished	Mar 26 02:29:59 PM PDT 24
Peak memory	200124 kb
Host	smart-4304d1dc-e15b-42f9-ba05-87a754084d5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682479986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3682479986
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.2016438045
Short name	T214
Test name
Test status
Simulation time	214105822922 ps
CPU time	288.92 seconds
Started	Mar 26 02:28:17 PM PDT 24
Finished	Mar 26 02:33:06 PM PDT 24
Peak memory	200092 kb
Host	smart-417e5580-95b5-4094-84b4-945c14e358e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016438045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2016438045
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.2499742382
Short name	T1032
Test name
Test status
Simulation time	10915854483 ps
CPU time	27.32 seconds
Started	Mar 26 02:28:18 PM PDT 24
Finished	Mar 26 02:28:46 PM PDT 24
Peak memory	200124 kb
Host	smart-b8055366-b220-4a5b-9894-3f7a9f92f38f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499742382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2499742382
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.249307574
Short name	T361
Test name
Test status
Simulation time	35072671469 ps
CPU time	21.18 seconds
Started	Mar 26 02:28:17 PM PDT 24
Finished	Mar 26 02:28:38 PM PDT 24
Peak memory	199988 kb
Host	smart-8dc25f79-fa94-4a6f-a2af-cea94d3ba1fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249307574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.249307574
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.586966155
Short name	T509
Test name
Test status
Simulation time	25753521976 ps
CPU time	11.98 seconds
Started	Mar 26 02:28:17 PM PDT 24
Finished	Mar 26 02:28:29 PM PDT 24
Peak memory	199872 kb
Host	smart-ad2bd719-99ec-4c21-9fc4-22765352195b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586966155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.586966155
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.2131792689
Short name	T862
Test name
Test status
Simulation time	5445454580 ps
CPU time	8.85 seconds
Started	Mar 26 02:28:18 PM PDT 24
Finished	Mar 26 02:28:27 PM PDT 24
Peak memory	199956 kb
Host	smart-fc43641f-3aa9-4e0a-b3fa-e4b86cc135ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131792689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2131792689
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.570721210
Short name	T738
Test name
Test status
Simulation time	13324575 ps
CPU time	0.61 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:20:43 PM PDT 24
Peak memory	195552 kb
Host	smart-8cf95594-07ec-466c-9357-4efe3cb1d9e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570721210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.570721210
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.3816403438
Short name	T1079
Test name
Test status
Simulation time	30182225817 ps
CPU time	35.4 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:21:19 PM PDT 24
Peak memory	200124 kb
Host	smart-81271d2f-7407-4561-9d7f-2d5ecb6fac64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816403438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3816403438
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.3880860733
Short name	T2
Test name
Test status
Simulation time	68432460945 ps
CPU time	51.25 seconds
Started	Mar 26 02:20:40 PM PDT 24
Finished	Mar 26 02:21:32 PM PDT 24
Peak memory	200056 kb
Host	smart-4bcf6cc7-08d1-400e-aaaa-62382cebd9a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880860733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3880860733
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.1285147782
Short name	T236
Test name
Test status
Simulation time	36168729289 ps
CPU time	11.78 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:20:54 PM PDT 24
Peak memory	200016 kb
Host	smart-dd60db6a-dd9d-4498-864a-9c5f29be35f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285147782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1285147782
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_intr.2105731618
Short name	T529
Test name
Test status
Simulation time	47012341803 ps
CPU time	43.16 seconds
Started	Mar 26 02:20:40 PM PDT 24
Finished	Mar 26 02:21:24 PM PDT 24
Peak memory	200108 kb
Host	smart-b2ecb5f4-02fb-4024-b091-19ac6135126d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105731618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2105731618
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.3001804561
Short name	T1029
Test name
Test status
Simulation time	212820158839 ps
CPU time	1218.63 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:41:00 PM PDT 24
Peak memory	200128 kb
Host	smart-550eadfa-76e0-4a5e-8284-49baa212d8b0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3001804561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3001804561
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.400090509
Short name	T486
Test name
Test status
Simulation time	9242277790 ps
CPU time	22.14 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:21:05 PM PDT 24
Peak memory	199496 kb
Host	smart-58a86b2b-f6bd-493e-b912-6533782ff91e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400090509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.400090509
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.770773312
Short name	T323
Test name
Test status
Simulation time	22944441820 ps
CPU time	25.99 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:21:08 PM PDT 24
Peak memory	199460 kb
Host	smart-5ceec40c-5260-43c1-8a9c-ce5d354d44e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770773312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.770773312
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.185640280
Short name	T1104
Test name
Test status
Simulation time	18062791366 ps
CPU time	99.83 seconds
Started	Mar 26 02:20:43 PM PDT 24
Finished	Mar 26 02:22:23 PM PDT 24
Peak memory	200032 kb
Host	smart-9d73d2eb-a9d4-42dd-b398-b0a4df1f9321
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=185640280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.185640280
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.1408515537
Short name	T1119
Test name
Test status
Simulation time	7245428409 ps
CPU time	62.69 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:21:45 PM PDT 24
Peak memory	199184 kb
Host	smart-00a12cee-1544-4ce5-befe-720261aedd45
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1408515537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1408515537
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.2247972162
Short name	T144
Test name
Test status
Simulation time	44527718497 ps
CPU time	51.86 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:21:34 PM PDT 24
Peak memory	199976 kb
Host	smart-3eac6269-adaa-4e55-8ffc-3b7c907ef85c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247972162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2247972162
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.2819482268
Short name	T669
Test name
Test status
Simulation time	2479826012 ps
CPU time	4.42 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:20:47 PM PDT 24
Peak memory	196192 kb
Host	smart-f96fd3f0-0db9-4103-8875-a955ce54afe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819482268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2819482268
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.1530288853
Short name	T638
Test name
Test status
Simulation time	954305491 ps
CPU time	2.31 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:20:45 PM PDT 24
Peak memory	199960 kb
Host	smart-e26e62a2-d792-440a-b084-b22dda91a8ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530288853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1530288853
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all.3900255182
Short name	T101
Test name
Test status
Simulation time	336024259432 ps
CPU time	467.48 seconds
Started	Mar 26 02:20:40 PM PDT 24
Finished	Mar 26 02:28:28 PM PDT 24
Peak memory	208424 kb
Host	smart-f54f381e-d5bb-4fb7-ad36-6d2eba9346b1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900255182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3900255182
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.490567589
Short name	T608
Test name
Test status
Simulation time	2697177787 ps
CPU time	1.51 seconds
Started	Mar 26 02:20:43 PM PDT 24
Finished	Mar 26 02:20:45 PM PDT 24
Peak memory	198728 kb
Host	smart-0f705dda-ec8e-42e0-823e-672e6de461fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490567589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.490567589
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.179791759
Short name	T713
Test name
Test status
Simulation time	8761002149 ps
CPU time	15.29 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:20:57 PM PDT 24
Peak memory	199144 kb
Host	smart-1d509de8-a9fe-4489-9dec-5fe1d2e45a4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179791759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.179791759
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.1367811156
Short name	T792
Test name
Test status
Simulation time	69799623908 ps
CPU time	35.27 seconds
Started	Mar 26 02:28:29 PM PDT 24
Finished	Mar 26 02:29:04 PM PDT 24
Peak memory	200016 kb
Host	smart-da5c8dcb-4bc8-4322-8edb-7dc66306cd5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367811156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1367811156
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.3554487451
Short name	T213
Test name
Test status
Simulation time	117194902163 ps
CPU time	130.28 seconds
Started	Mar 26 02:28:27 PM PDT 24
Finished	Mar 26 02:30:37 PM PDT 24
Peak memory	199968 kb
Host	smart-dd4a02cc-c595-40d6-8305-a582b3ce0595
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554487451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3554487451
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.346469584
Short name	T843
Test name
Test status
Simulation time	61354149326 ps
CPU time	62.78 seconds
Started	Mar 26 02:28:26 PM PDT 24
Finished	Mar 26 02:29:29 PM PDT 24
Peak memory	200076 kb
Host	smart-23d2dd76-014c-4fc8-be9b-1e5e9478a659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346469584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.346469584
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.1967365473
Short name	T1066
Test name
Test status
Simulation time	69294770105 ps
CPU time	40.53 seconds
Started	Mar 26 02:28:27 PM PDT 24
Finished	Mar 26 02:29:08 PM PDT 24
Peak memory	199944 kb
Host	smart-ce5fd89c-44fb-4110-9d2a-61c530064230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967365473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1967365473
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.1218638734
Short name	T1053
Test name
Test status
Simulation time	91059990525 ps
CPU time	8.97 seconds
Started	Mar 26 02:28:29 PM PDT 24
Finished	Mar 26 02:28:38 PM PDT 24
Peak memory	199940 kb
Host	smart-27bd023c-b67b-456b-a4f4-7fab796f5e5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218638734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1218638734
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.3493021663
Short name	T1089
Test name
Test status
Simulation time	101797026907 ps
CPU time	129.26 seconds
Started	Mar 26 02:28:28 PM PDT 24
Finished	Mar 26 02:30:37 PM PDT 24
Peak memory	200072 kb
Host	smart-0c851d40-52fb-43d6-a81b-b2c82847cc08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493021663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3493021663
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.2484410847
Short name	T194
Test name
Test status
Simulation time	78841006372 ps
CPU time	15.46 seconds
Started	Mar 26 02:28:27 PM PDT 24
Finished	Mar 26 02:28:43 PM PDT 24
Peak memory	199976 kb
Host	smart-627b0262-f214-4cd8-bdbf-50f96afc9851
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484410847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2484410847
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.827442178
Short name	T852
Test name
Test status
Simulation time	63756965189 ps
CPU time	153.31 seconds
Started	Mar 26 02:28:26 PM PDT 24
Finished	Mar 26 02:30:59 PM PDT 24
Peak memory	199960 kb
Host	smart-3c5b0ad9-0651-4c24-a08e-db8e6006c0d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827442178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.827442178
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.2029970283
Short name	T980
Test name
Test status
Simulation time	54524175 ps
CPU time	0.59 seconds
Started	Mar 26 02:21:00 PM PDT 24
Finished	Mar 26 02:21:00 PM PDT 24
Peak memory	195596 kb
Host	smart-4a0bdc25-73cf-455b-a098-b6a01b76b51c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029970283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2029970283
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.3636719238
Short name	T61
Test name
Test status
Simulation time	182240441259 ps
CPU time	49.96 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:21:31 PM PDT 24
Peak memory	200012 kb
Host	smart-d9f8af8e-8412-4808-8a88-c5712df259b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636719238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3636719238
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.3677900065
Short name	T752
Test name
Test status
Simulation time	75438159842 ps
CPU time	22.6 seconds
Started	Mar 26 02:20:53 PM PDT 24
Finished	Mar 26 02:21:16 PM PDT 24
Peak memory	199804 kb
Host	smart-535d6f8e-da6a-47b8-8143-3e3936b9e113
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3677900065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3677900065
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_intr.2879814426
Short name	T478
Test name
Test status
Simulation time	14875922107 ps
CPU time	2.9 seconds
Started	Mar 26 02:20:57 PM PDT 24
Finished	Mar 26 02:21:00 PM PDT 24
Peak memory	197124 kb
Host	smart-622f863d-07d2-42d1-8c68-31d1fb70026e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879814426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2879814426
Directory	/workspace/12.uart_intr/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.2147854645
Short name	T82
Test name
Test status
Simulation time	86091062780 ps
CPU time	381.43 seconds
Started	Mar 26 02:20:59 PM PDT 24
Finished	Mar 26 02:27:20 PM PDT 24
Peak memory	200108 kb
Host	smart-fc167eb7-0904-4775-bda6-dbabe717c8aa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2147854645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2147854645
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_loopback.511857792
Short name	T999
Test name
Test status
Simulation time	8887056530 ps
CPU time	18.55 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:21:14 PM PDT 24
Peak memory	199948 kb
Host	smart-c44a3d7b-2f3a-476e-9d42-7ed5e3c5585c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511857792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.511857792
Directory	/workspace/12.uart_loopback/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.973034022
Short name	T961
Test name
Test status
Simulation time	19942632740 ps
CPU time	17.42 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:21:13 PM PDT 24
Peak memory	194112 kb
Host	smart-713e3b66-84ca-48f2-b9ab-973c25795b70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973034022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.973034022
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.1231434109
Short name	T1082
Test name
Test status
Simulation time	12914485062 ps
CPU time	487.36 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:29:03 PM PDT 24
Peak memory	200120 kb
Host	smart-1100dd3b-ced8-4e0d-a614-5ba6eaae56e4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1231434109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1231434109
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.4287639622
Short name	T426
Test name
Test status
Simulation time	2859091051 ps
CPU time	3.93 seconds
Started	Mar 26 02:20:57 PM PDT 24
Finished	Mar 26 02:21:01 PM PDT 24
Peak memory	198660 kb
Host	smart-fc174bfd-b0d6-4a4b-a8f0-999688a293c3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4287639622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4287639622
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.4070444935
Short name	T167
Test name
Test status
Simulation time	41285398454 ps
CPU time	32.17 seconds
Started	Mar 26 02:20:58 PM PDT 24
Finished	Mar 26 02:21:30 PM PDT 24
Peak memory	199784 kb
Host	smart-87e94795-7099-4d6d-9839-747bf1f4a130
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070444935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4070444935
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.256316088
Short name	T769
Test name
Test status
Simulation time	1691501441 ps
CPU time	3.24 seconds
Started	Mar 26 02:20:53 PM PDT 24
Finished	Mar 26 02:20:57 PM PDT 24
Peak memory	195580 kb
Host	smart-8c49288e-1217-432f-9915-b023236810b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256316088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.256316088
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.845513538
Short name	T894
Test name
Test status
Simulation time	11062784927 ps
CPU time	15.97 seconds
Started	Mar 26 02:20:47 PM PDT 24
Finished	Mar 26 02:21:03 PM PDT 24
Peak memory	199912 kb
Host	smart-a017442b-77c2-4117-8f1c-1e2c1a6564ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845513538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.845513538
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.4239561030
Short name	T789
Test name
Test status
Simulation time	942532943 ps
CPU time	2.23 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:20:58 PM PDT 24
Peak memory	198772 kb
Host	smart-ed548363-c540-4dd7-ac64-e308b38e6214
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4239561030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4239561030
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.5903605
Short name	T768
Test name
Test status
Simulation time	132490513152 ps
CPU time	147.86 seconds
Started	Mar 26 02:20:41 PM PDT 24
Finished	Mar 26 02:23:09 PM PDT 24
Peak memory	199908 kb
Host	smart-dd16f374-0424-4544-8484-2f6f16590fd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5903605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.5903605
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.33988450
Short name	T693
Test name
Test status
Simulation time	40587631529 ps
CPU time	32.97 seconds
Started	Mar 26 02:28:28 PM PDT 24
Finished	Mar 26 02:29:01 PM PDT 24
Peak memory	199976 kb
Host	smart-9c57d510-acf9-42f9-839a-fada70d8412a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33988450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.33988450
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.3041902621
Short name	T234
Test name
Test status
Simulation time	21863895834 ps
CPU time	31.15 seconds
Started	Mar 26 02:28:28 PM PDT 24
Finished	Mar 26 02:28:59 PM PDT 24
Peak memory	200016 kb
Host	smart-96907f11-f473-427c-ae64-f6d6bcc75165
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041902621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3041902621
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.1030995801
Short name	T1035
Test name
Test status
Simulation time	46869273816 ps
CPU time	16.4 seconds
Started	Mar 26 02:28:35 PM PDT 24
Finished	Mar 26 02:28:53 PM PDT 24
Peak memory	199804 kb
Host	smart-9d05c1dc-5611-4f55-aa6c-6321260fc936
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030995801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1030995801
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.157047060
Short name	T925
Test name
Test status
Simulation time	263817095586 ps
CPU time	101.14 seconds
Started	Mar 26 02:28:36 PM PDT 24
Finished	Mar 26 02:30:18 PM PDT 24
Peak memory	200104 kb
Host	smart-ddadbbce-25f3-4998-9a05-b1552086275b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157047060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.157047060
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.7356171
Short name	T1011
Test name
Test status
Simulation time	124971015334 ps
CPU time	215.01 seconds
Started	Mar 26 02:28:41 PM PDT 24
Finished	Mar 26 02:32:16 PM PDT 24
Peak memory	200084 kb
Host	smart-89df03ad-be28-43b7-8197-4813189f09a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7356171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.7356171
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.2472505674
Short name	T928
Test name
Test status
Simulation time	12135376582 ps
CPU time	22.88 seconds
Started	Mar 26 02:28:37 PM PDT 24
Finished	Mar 26 02:29:01 PM PDT 24
Peak memory	200052 kb
Host	smart-7e7fcaa9-414a-4b25-bc38-1970fce05f03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2472505674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2472505674
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.337616770
Short name	T881
Test name
Test status
Simulation time	20471693118 ps
CPU time	16.02 seconds
Started	Mar 26 02:28:37 PM PDT 24
Finished	Mar 26 02:28:54 PM PDT 24
Peak memory	200040 kb
Host	smart-62f43118-18cc-4fd3-9ba2-3c3b643130dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337616770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.337616770
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.2654787994
Short name	T341
Test name
Test status
Simulation time	10262778560 ps
CPU time	20.98 seconds
Started	Mar 26 02:28:35 PM PDT 24
Finished	Mar 26 02:28:58 PM PDT 24
Peak memory	200020 kb
Host	smart-93f5bfac-5388-4e93-b340-c05286a878c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654787994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2654787994
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_alert_test.1543461751
Short name	T831
Test name
Test status
Simulation time	25528127 ps
CPU time	0.57 seconds
Started	Mar 26 02:20:56 PM PDT 24
Finished	Mar 26 02:20:57 PM PDT 24
Peak memory	195532 kb
Host	smart-3d0d75e2-0218-4712-8272-192c9e606b3a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543461751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1543461751
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.176619229
Short name	T686
Test name
Test status
Simulation time	259964402524 ps
CPU time	357.08 seconds
Started	Mar 26 02:20:58 PM PDT 24
Finished	Mar 26 02:26:55 PM PDT 24
Peak memory	200088 kb
Host	smart-c9054b8d-3129-4432-b151-f726af39bd5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176619229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.176619229
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.2137241741
Short name	T697
Test name
Test status
Simulation time	8992254254 ps
CPU time	14.55 seconds
Started	Mar 26 02:20:59 PM PDT 24
Finished	Mar 26 02:21:14 PM PDT 24
Peak memory	200104 kb
Host	smart-d883efae-4ac5-47b1-9206-c205acfcc206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137241741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2137241741
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.1619065262
Short name	T339
Test name
Test status
Simulation time	19533328741 ps
CPU time	21.15 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:21:17 PM PDT 24
Peak memory	199188 kb
Host	smart-c72355ee-a465-44c8-ac9f-7004a0e528dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619065262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1619065262
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.3545804156
Short name	T492
Test name
Test status
Simulation time	17632785042 ps
CPU time	28.77 seconds
Started	Mar 26 02:21:00 PM PDT 24
Finished	Mar 26 02:21:29 PM PDT 24
Peak memory	197180 kb
Host	smart-5b6e5ac9-a5e1-4c1c-9d38-eb40b61aa737
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545804156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3545804156
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.1797713405
Short name	T561
Test name
Test status
Simulation time	211025807587 ps
CPU time	351.33 seconds
Started	Mar 26 02:20:56 PM PDT 24
Finished	Mar 26 02:26:48 PM PDT 24
Peak memory	200036 kb
Host	smart-d1764fcb-51fe-44b7-9391-0085047b60c7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1797713405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1797713405
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/13.uart_loopback.3485508819
Short name	T879
Test name
Test status
Simulation time	656436998 ps
CPU time	0.93 seconds
Started	Mar 26 02:20:53 PM PDT 24
Finished	Mar 26 02:20:54 PM PDT 24
Peak memory	196144 kb
Host	smart-4a1f8837-ac1a-48d1-8064-55e48e63a369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485508819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3485508819
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.1753996828
Short name	T705
Test name
Test status
Simulation time	568194905114 ps
CPU time	91.01 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:22:26 PM PDT 24
Peak memory	208400 kb
Host	smart-1396538d-0a1a-4966-a880-3874d3425044
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753996828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1753996828
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.734847301
Short name	T824
Test name
Test status
Simulation time	25979429047 ps
CPU time	1071.67 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:38:46 PM PDT 24
Peak memory	200084 kb
Host	smart-cbff3213-7e14-488c-91a7-ad49a3b9c304
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=734847301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.734847301
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.240353125
Short name	T1118
Test name
Test status
Simulation time	5794326986 ps
CPU time	12.99 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:21:08 PM PDT 24
Peak memory	199380 kb
Host	smart-36cbcd61-750a-4742-a990-72fe0ad81e49
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=240353125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.240353125
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.2639783412
Short name	T797
Test name
Test status
Simulation time	190553490556 ps
CPU time	137.02 seconds
Started	Mar 26 02:20:56 PM PDT 24
Finished	Mar 26 02:23:13 PM PDT 24
Peak memory	200088 kb
Host	smart-98ba75f9-1c88-4cd3-84b8-bc8c697e42ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639783412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2639783412
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.707115747
Short name	T572
Test name
Test status
Simulation time	2430609813 ps
CPU time	0.82 seconds
Started	Mar 26 02:20:53 PM PDT 24
Finished	Mar 26 02:20:54 PM PDT 24
Peak memory	195944 kb
Host	smart-303b71f9-8972-4c99-90bd-0aa30829e602
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707115747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.707115747
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.669192951
Short name	T465
Test name
Test status
Simulation time	307505132 ps
CPU time	1.41 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:20:55 PM PDT 24
Peak memory	199652 kb
Host	smart-b21dd208-06a2-4453-ba80-74ec76294495
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669192951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.669192951
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_stress_all.3908386176
Short name	T1028
Test name
Test status
Simulation time	125635688404 ps
CPU time	192.99 seconds
Started	Mar 26 02:20:56 PM PDT 24
Finished	Mar 26 02:24:09 PM PDT 24
Peak memory	200040 kb
Host	smart-9403b044-3067-487d-8947-d02eb80d1451
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908386176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3908386176
Directory	/workspace/13.uart_stress_all/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.4119270429
Short name	T1006
Test name
Test status
Simulation time	1027161998 ps
CPU time	2.41 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:20:57 PM PDT 24
Peak memory	198444 kb
Host	smart-c54d532b-cdb9-4113-a4a9-5a015ad86a68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119270429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4119270429
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.2180604267
Short name	T714
Test name
Test status
Simulation time	101993376699 ps
CPU time	92.26 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:22:27 PM PDT 24
Peak memory	200116 kb
Host	smart-95a4bd8c-6311-4f7c-8318-6868059d9fa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180604267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2180604267
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.3436079583
Short name	T620
Test name
Test status
Simulation time	75585425644 ps
CPU time	32.41 seconds
Started	Mar 26 02:28:36 PM PDT 24
Finished	Mar 26 02:29:11 PM PDT 24
Peak memory	199836 kb
Host	smart-0fa6b17b-3773-4060-bac5-9e17bc4fec0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436079583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3436079583
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.221783578
Short name	T244
Test name
Test status
Simulation time	225527504387 ps
CPU time	97.11 seconds
Started	Mar 26 02:28:40 PM PDT 24
Finished	Mar 26 02:30:18 PM PDT 24
Peak memory	200044 kb
Host	smart-1183debb-52db-4d49-9104-34a16107ebd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=221783578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.221783578
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.2688842976
Short name	T573
Test name
Test status
Simulation time	120088588178 ps
CPU time	180.5 seconds
Started	Mar 26 02:28:36 PM PDT 24
Finished	Mar 26 02:31:37 PM PDT 24
Peak memory	200116 kb
Host	smart-3a41dd4e-c76e-40a0-8fdc-1a55928537e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688842976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2688842976
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.928032840
Short name	T969
Test name
Test status
Simulation time	14998357165 ps
CPU time	7.41 seconds
Started	Mar 26 02:28:35 PM PDT 24
Finished	Mar 26 02:28:45 PM PDT 24
Peak memory	200068 kb
Host	smart-d8b97b38-e570-429e-bff0-2ab18ed6719a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928032840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.928032840
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.877214183
Short name	T152
Test name
Test status
Simulation time	213081469918 ps
CPU time	59.88 seconds
Started	Mar 26 02:28:35 PM PDT 24
Finished	Mar 26 02:29:37 PM PDT 24
Peak memory	200092 kb
Host	smart-c597c155-7ffd-4ad5-be78-0a0049643576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877214183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.877214183
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.3116400989
Short name	T1083
Test name
Test status
Simulation time	219378901290 ps
CPU time	82.15 seconds
Started	Mar 26 02:28:35 PM PDT 24
Finished	Mar 26 02:29:59 PM PDT 24
Peak memory	200096 kb
Host	smart-4b399b23-2a34-4662-abb4-a3afebaa8441
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116400989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3116400989
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.9421871
Short name	T371
Test name
Test status
Simulation time	44586174581 ps
CPU time	53.83 seconds
Started	Mar 26 02:28:37 PM PDT 24
Finished	Mar 26 02:29:32 PM PDT 24
Peak memory	200108 kb
Host	smart-e0786471-41ba-443f-9460-4a55eb275668
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9421871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.9421871
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.2570346227
Short name	T211
Test name
Test status
Simulation time	120202766133 ps
CPU time	32.88 seconds
Started	Mar 26 02:28:46 PM PDT 24
Finished	Mar 26 02:29:19 PM PDT 24
Peak memory	200044 kb
Host	smart-80f68cc4-5ef4-442b-8caf-633b550dd1f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2570346227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2570346227
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.3189464964
Short name	T998
Test name
Test status
Simulation time	105792508 ps
CPU time	0.59 seconds
Started	Mar 26 02:20:58 PM PDT 24
Finished	Mar 26 02:20:59 PM PDT 24
Peak memory	195572 kb
Host	smart-eca1ff07-77a7-4a7b-8549-308190232fe4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189464964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3189464964
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.1314577112
Short name	T977
Test name
Test status
Simulation time	36615128847 ps
CPU time	37.83 seconds
Started	Mar 26 02:20:59 PM PDT 24
Finished	Mar 26 02:21:37 PM PDT 24
Peak memory	200040 kb
Host	smart-1618afe0-956a-4012-8641-7b8b4e017b93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314577112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1314577112
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.1160806989
Short name	T133
Test name
Test status
Simulation time	34169480419 ps
CPU time	65.26 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:22:00 PM PDT 24
Peak memory	200032 kb
Host	smart-e3fd9754-f552-4cfd-9699-0908f2401d66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160806989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1160806989
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.157899243
Short name	T995
Test name
Test status
Simulation time	121082152067 ps
CPU time	298.18 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:25:53 PM PDT 24
Peak memory	200000 kb
Host	smart-80a4d2b1-835e-4b70-abb2-a9d9ec9ce75f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157899243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.157899243
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.3637392688
Short name	T88
Test name
Test status
Simulation time	40713109144 ps
CPU time	26.46 seconds
Started	Mar 26 02:20:59 PM PDT 24
Finished	Mar 26 02:21:26 PM PDT 24
Peak memory	200048 kb
Host	smart-8c6efb07-71a8-4fe1-ac41-debd58549d55
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637392688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3637392688
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.400846110
Short name	T312
Test name
Test status
Simulation time	51599264281 ps
CPU time	90.37 seconds
Started	Mar 26 02:20:56 PM PDT 24
Finished	Mar 26 02:22:26 PM PDT 24
Peak memory	199996 kb
Host	smart-00285302-0175-4b45-9c07-a43430337992
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=400846110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.400846110
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.2286491449
Short name	T482
Test name
Test status
Simulation time	8130908158 ps
CPU time	4.63 seconds
Started	Mar 26 02:20:58 PM PDT 24
Finished	Mar 26 02:21:03 PM PDT 24
Peak memory	198720 kb
Host	smart-b2a75fd2-b7c6-42e5-b6e8-2aced9086baf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286491449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2286491449
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.873442928
Short name	T342
Test name
Test status
Simulation time	196401060608 ps
CPU time	129.7 seconds
Started	Mar 26 02:20:56 PM PDT 24
Finished	Mar 26 02:23:06 PM PDT 24
Peak memory	200220 kb
Host	smart-9547fbd5-319b-4bc2-a912-d1a5d77eaa89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873442928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.873442928
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_perf.2555252849
Short name	T499
Test name
Test status
Simulation time	7965037178 ps
CPU time	484.55 seconds
Started	Mar 26 02:21:00 PM PDT 24
Finished	Mar 26 02:29:04 PM PDT 24
Peak memory	199980 kb
Host	smart-711af2fb-83e0-4510-85b4-535258712f99
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2555252849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2555252849
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.832235756
Short name	T27
Test name
Test status
Simulation time	3450917801 ps
CPU time	7.72 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:21:02 PM PDT 24
Peak memory	198908 kb
Host	smart-36c5b47c-a575-4bb3-a372-98e23fd44e25
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=832235756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.832235756
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.233828635
Short name	T533
Test name
Test status
Simulation time	13031044056 ps
CPU time	5.83 seconds
Started	Mar 26 02:20:59 PM PDT 24
Finished	Mar 26 02:21:05 PM PDT 24
Peak memory	198688 kb
Host	smart-60f92e1a-6b60-4400-8a74-bd7463f64267
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233828635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.233828635
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.915910669
Short name	T310
Test name
Test status
Simulation time	40867385705 ps
CPU time	5.51 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:20:59 PM PDT 24
Peak memory	196196 kb
Host	smart-2052a0fa-836b-4f39-a0bc-b8adca6018b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915910669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.915910669
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.1048245024
Short name	T673
Test name
Test status
Simulation time	270573408 ps
CPU time	1.98 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:20:57 PM PDT 24
Peak memory	198376 kb
Host	smart-64d72d75-594e-46a3-bf63-3a9f94e0dc04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048245024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1048245024
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_stress_all.1564330853
Short name	T780
Test name
Test status
Simulation time	126379681605 ps
CPU time	250 seconds
Started	Mar 26 02:20:56 PM PDT 24
Finished	Mar 26 02:25:06 PM PDT 24
Peak memory	200028 kb
Host	smart-b36d05a1-9464-431c-a8a8-e83779df10e1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564330853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1564330853
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.507959863
Short name	T556
Test name
Test status
Simulation time	1729333750 ps
CPU time	1.43 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:20:56 PM PDT 24
Peak memory	198684 kb
Host	smart-00f7b63c-95d6-4e19-8852-f9048e5d0537
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507959863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.507959863
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.4124415943
Short name	T645
Test name
Test status
Simulation time	45736353730 ps
CPU time	63.4 seconds
Started	Mar 26 02:20:53 PM PDT 24
Finished	Mar 26 02:21:57 PM PDT 24
Peak memory	199912 kb
Host	smart-7329c949-575a-4d1e-9156-52868b8c0033
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4124415943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4124415943
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.2965140300
Short name	T785
Test name
Test status
Simulation time	83551381592 ps
CPU time	178.6 seconds
Started	Mar 26 02:28:45 PM PDT 24
Finished	Mar 26 02:31:44 PM PDT 24
Peak memory	200056 kb
Host	smart-eaf998c5-be9b-4e2f-bb75-bf08a1f40c2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965140300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2965140300
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.1586770804
Short name	T887
Test name
Test status
Simulation time	234047830686 ps
CPU time	66.77 seconds
Started	Mar 26 02:28:45 PM PDT 24
Finished	Mar 26 02:29:52 PM PDT 24
Peak memory	200076 kb
Host	smart-46f9aad0-6127-473b-a56f-2e3ae6242a94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586770804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1586770804
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.686061972
Short name	T537
Test name
Test status
Simulation time	50756380248 ps
CPU time	13.47 seconds
Started	Mar 26 02:28:46 PM PDT 24
Finished	Mar 26 02:28:59 PM PDT 24
Peak memory	200044 kb
Host	smart-71e89946-02eb-43fc-a609-600ec93595a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686061972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.686061972
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.294726360
Short name	T875
Test name
Test status
Simulation time	130721810554 ps
CPU time	54.1 seconds
Started	Mar 26 02:28:44 PM PDT 24
Finished	Mar 26 02:29:39 PM PDT 24
Peak memory	200060 kb
Host	smart-0451eda3-aa78-4558-bf49-64dfd611b885
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294726360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.294726360
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.2301124291
Short name	T217
Test name
Test status
Simulation time	25273574167 ps
CPU time	39.97 seconds
Started	Mar 26 02:28:46 PM PDT 24
Finished	Mar 26 02:29:26 PM PDT 24
Peak memory	199876 kb
Host	smart-7302b8cb-00d0-4bb0-8bf5-a988b945773f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301124291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2301124291
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.1746041889
Short name	T934
Test name
Test status
Simulation time	137672238374 ps
CPU time	53.08 seconds
Started	Mar 26 02:28:45 PM PDT 24
Finished	Mar 26 02:29:38 PM PDT 24
Peak memory	200012 kb
Host	smart-c3d6313d-7973-4b3f-8e91-e25a68a57953
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746041889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1746041889
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.1021632678
Short name	T534
Test name
Test status
Simulation time	37319806075 ps
CPU time	15.61 seconds
Started	Mar 26 02:28:56 PM PDT 24
Finished	Mar 26 02:29:12 PM PDT 24
Peak memory	200056 kb
Host	smart-0aacda62-d45b-4228-8e6f-0c6909b76e4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021632678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1021632678
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.4251211765
Short name	T681
Test name
Test status
Simulation time	25197416782 ps
CPU time	19.26 seconds
Started	Mar 26 02:28:55 PM PDT 24
Finished	Mar 26 02:29:14 PM PDT 24
Peak memory	200336 kb
Host	smart-d6198daf-6e59-47f5-94a2-32ee7899fa53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251211765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4251211765
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.1474208957
Short name	T588
Test name
Test status
Simulation time	27081050 ps
CPU time	0.56 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:21:09 PM PDT 24
Peak memory	195576 kb
Host	smart-1de25fc7-3d92-4913-b195-1afbe901c86e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474208957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1474208957
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.2769829187
Short name	T870
Test name
Test status
Simulation time	40956897404 ps
CPU time	21.34 seconds
Started	Mar 26 02:20:59 PM PDT 24
Finished	Mar 26 02:21:21 PM PDT 24
Peak memory	199820 kb
Host	smart-662830a8-5958-4c86-adfa-9eebb59ec69c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769829187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2769829187
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.634500855
Short name	T667
Test name
Test status
Simulation time	70537707850 ps
CPU time	33.23 seconds
Started	Mar 26 02:20:59 PM PDT 24
Finished	Mar 26 02:21:32 PM PDT 24
Peak memory	199852 kb
Host	smart-de8d8f44-ca4f-42b6-b380-783f5703db34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634500855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.634500855
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.2044764724
Short name	T243
Test name
Test status
Simulation time	37936815846 ps
CPU time	34.58 seconds
Started	Mar 26 02:20:53 PM PDT 24
Finished	Mar 26 02:21:28 PM PDT 24
Peak memory	200008 kb
Host	smart-0b385279-dfce-445b-aa5d-2b8e02f15439
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044764724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2044764724
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_intr.2444591619
Short name	T157
Test name
Test status
Simulation time	45154060200 ps
CPU time	23.53 seconds
Started	Mar 26 02:20:58 PM PDT 24
Finished	Mar 26 02:21:22 PM PDT 24
Peak memory	200100 kb
Host	smart-fb451a03-7782-4eb6-9619-3be60a18d99f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444591619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2444591619
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.4192545063
Short name	T542
Test name
Test status
Simulation time	133359452603 ps
CPU time	301.3 seconds
Started	Mar 26 02:21:08 PM PDT 24
Finished	Mar 26 02:26:10 PM PDT 24
Peak memory	200084 kb
Host	smart-e292a9fe-0a2d-485e-97be-97b4dd03112d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4192545063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4192545063
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_loopback.738298345
Short name	T869
Test name
Test status
Simulation time	9656499959 ps
CPU time	15.85 seconds
Started	Mar 26 02:21:13 PM PDT 24
Finished	Mar 26 02:21:29 PM PDT 24
Peak memory	198920 kb
Host	smart-ba98a866-4c13-4e85-bd84-4022208dc11b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738298345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.738298345
Directory	/workspace/15.uart_loopback/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.3022332485
Short name	T307
Test name
Test status
Simulation time	139874187243 ps
CPU time	176.79 seconds
Started	Mar 26 02:20:58 PM PDT 24
Finished	Mar 26 02:23:55 PM PDT 24
Peak memory	200268 kb
Host	smart-50de6234-5f13-41a0-b43e-d65f9ae3c6e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022332485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3022332485
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_perf.1978547513
Short name	T575
Test name
Test status
Simulation time	8266834329 ps
CPU time	118.19 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:23:07 PM PDT 24
Peak memory	200064 kb
Host	smart-256c45f0-0e89-40a7-a900-4fc096102b9f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1978547513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1978547513
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.1246505218
Short name	T722
Test name
Test status
Simulation time	1573513721 ps
CPU time	8.27 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:21:03 PM PDT 24
Peak memory	198160 kb
Host	smart-4f436d1a-0d42-4fa2-beb9-6b5c8cf8b55c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1246505218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1246505218
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.3470910107
Short name	T463
Test name
Test status
Simulation time	30534387655 ps
CPU time	51 seconds
Started	Mar 26 02:21:10 PM PDT 24
Finished	Mar 26 02:22:01 PM PDT 24
Peak memory	200080 kb
Host	smart-e1cb4a0d-6be9-4637-bea1-449ba7e01a75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470910107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3470910107
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.884881688
Short name	T411
Test name
Test status
Simulation time	1732207910 ps
CPU time	1.28 seconds
Started	Mar 26 02:20:58 PM PDT 24
Finished	Mar 26 02:21:00 PM PDT 24
Peak memory	195532 kb
Host	smart-321a988e-7ba6-4f81-8538-aa412c586335
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884881688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.884881688
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.3381630626
Short name	T392
Test name
Test status
Simulation time	547378424 ps
CPU time	2.76 seconds
Started	Mar 26 02:20:55 PM PDT 24
Finished	Mar 26 02:20:58 PM PDT 24
Peak memory	199552 kb
Host	smart-63abb326-bb74-40e9-8efb-99dfd6d86cf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381630626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3381630626
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_stress_all.1292770948
Short name	T1008
Test name
Test status
Simulation time	296682928117 ps
CPU time	162.33 seconds
Started	Mar 26 02:21:10 PM PDT 24
Finished	Mar 26 02:23:53 PM PDT 24
Peak memory	208416 kb
Host	smart-043978f3-b17d-459e-87c1-4352053ae6c8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292770948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1292770948
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.2992374766
Short name	T933
Test name
Test status
Simulation time	1497876900 ps
CPU time	2.99 seconds
Started	Mar 26 02:21:10 PM PDT 24
Finished	Mar 26 02:21:13 PM PDT 24
Peak memory	199664 kb
Host	smart-36b6ae5a-8b8f-4aa8-a849-8107961c8586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992374766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2992374766
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.2300499775
Short name	T810
Test name
Test status
Simulation time	183184518048 ps
CPU time	128.23 seconds
Started	Mar 26 02:20:54 PM PDT 24
Finished	Mar 26 02:23:02 PM PDT 24
Peak memory	199992 kb
Host	smart-be8e31e5-fbe2-4f30-b81c-59816b820279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300499775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2300499775
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.2359294579
Short name	T839
Test name
Test status
Simulation time	106883359337 ps
CPU time	83.23 seconds
Started	Mar 26 02:28:55 PM PDT 24
Finished	Mar 26 02:30:18 PM PDT 24
Peak memory	200092 kb
Host	smart-0cc552f1-9563-40e8-944f-eeb12e2a1382
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359294579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2359294579
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.1905200637
Short name	T775
Test name
Test status
Simulation time	118843880792 ps
CPU time	161.72 seconds
Started	Mar 26 02:28:56 PM PDT 24
Finished	Mar 26 02:31:38 PM PDT 24
Peak memory	200092 kb
Host	smart-eca01cea-f352-406b-b1ae-0ec16f4bb7db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905200637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1905200637
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.3466537321
Short name	T198
Test name
Test status
Simulation time	115022595620 ps
CPU time	45.79 seconds
Started	Mar 26 02:28:56 PM PDT 24
Finished	Mar 26 02:29:42 PM PDT 24
Peak memory	200012 kb
Host	smart-8b29521b-bc10-44c3-b39c-e4e9656398df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466537321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3466537321
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.1940653650
Short name	T165
Test name
Test status
Simulation time	90606289441 ps
CPU time	26.84 seconds
Started	Mar 26 02:28:57 PM PDT 24
Finished	Mar 26 02:29:24 PM PDT 24
Peak memory	200124 kb
Host	smart-135f8146-361f-425d-b477-9e0a4367ccc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940653650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1940653650
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.3268958476
Short name	T717
Test name
Test status
Simulation time	99865319109 ps
CPU time	174.91 seconds
Started	Mar 26 02:28:56 PM PDT 24
Finished	Mar 26 02:31:51 PM PDT 24
Peak memory	200100 kb
Host	smart-f9309b6c-b466-4f1c-802a-a5afa05155e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3268958476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3268958476
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.3270155862
Short name	T734
Test name
Test status
Simulation time	86434161730 ps
CPU time	138.14 seconds
Started	Mar 26 02:28:56 PM PDT 24
Finished	Mar 26 02:31:14 PM PDT 24
Peak memory	200056 kb
Host	smart-80e0a4e9-bf33-4a45-a39f-c8ce38f874b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270155862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3270155862
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.1912581362
Short name	T1050
Test name
Test status
Simulation time	15921896306 ps
CPU time	29.16 seconds
Started	Mar 26 02:28:55 PM PDT 24
Finished	Mar 26 02:29:24 PM PDT 24
Peak memory	199976 kb
Host	smart-70533efa-0637-4772-b255-9773f5600ba3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912581362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1912581362
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.4216305178
Short name	T623
Test name
Test status
Simulation time	90111457634 ps
CPU time	44.62 seconds
Started	Mar 26 02:28:55 PM PDT 24
Finished	Mar 26 02:29:40 PM PDT 24
Peak memory	200116 kb
Host	smart-47eeb7b6-1868-458f-9de0-18f9cb409ef5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216305178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4216305178
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.2270462715
Short name	T1115
Test name
Test status
Simulation time	52541633361 ps
CPU time	23.25 seconds
Started	Mar 26 02:28:56 PM PDT 24
Finished	Mar 26 02:29:19 PM PDT 24
Peak memory	199896 kb
Host	smart-9769a82c-f9c2-4aa4-9671-6f3522f6dabc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270462715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2270462715
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.1800019812
Short name	T807
Test name
Test status
Simulation time	59734637002 ps
CPU time	24.27 seconds
Started	Mar 26 02:28:56 PM PDT 24
Finished	Mar 26 02:29:20 PM PDT 24
Peak memory	199816 kb
Host	smart-1f9a0db6-94ab-48f2-9fa1-a719cb999f62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800019812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1800019812
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.2565917082
Short name	T762
Test name
Test status
Simulation time	78077844 ps
CPU time	0.52 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:21:21 PM PDT 24
Peak memory	194508 kb
Host	smart-12e5d1a2-e03f-4513-b9f9-1ed7b7e622e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565917082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2565917082
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.3277413841
Short name	T439
Test name
Test status
Simulation time	84133697806 ps
CPU time	91.15 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:22:40 PM PDT 24
Peak memory	200060 kb
Host	smart-bbd200bb-3ef6-40c6-ac40-3cfa3d344d3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277413841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3277413841
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.2137546221
Short name	T680
Test name
Test status
Simulation time	57224497736 ps
CPU time	62.27 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:22:11 PM PDT 24
Peak memory	200116 kb
Host	smart-79cb1701-4969-4044-9ba6-bec6eff92f11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137546221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2137546221
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_intr.2999161617
Short name	T67
Test name
Test status
Simulation time	45941626460 ps
CPU time	34.8 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:21:44 PM PDT 24
Peak memory	200168 kb
Host	smart-9cd239c3-07b6-4b21-90b4-5434755bed0d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999161617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2999161617
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.1337531028
Short name	T829
Test name
Test status
Simulation time	283403192525 ps
CPU time	622.24 seconds
Started	Mar 26 02:21:19 PM PDT 24
Finished	Mar 26 02:31:41 PM PDT 24
Peak memory	199972 kb
Host	smart-8fee7411-902a-4a14-a655-8d602c45cb3b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1337531028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1337531028
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.2084083921
Short name	T753
Test name
Test status
Simulation time	9535730999 ps
CPU time	18.46 seconds
Started	Mar 26 02:21:10 PM PDT 24
Finished	Mar 26 02:21:29 PM PDT 24
Peak memory	200052 kb
Host	smart-a28a738d-14d8-4970-9405-f96ec85847c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084083921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2084083921
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.2277380039
Short name	T702
Test name
Test status
Simulation time	142700278316 ps
CPU time	63.16 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:22:12 PM PDT 24
Peak memory	200184 kb
Host	smart-c043ba08-1dea-427e-b1dd-900e2baac606
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2277380039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2277380039
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.432542523
Short name	T402
Test name
Test status
Simulation time	12141955329 ps
CPU time	763.73 seconds
Started	Mar 26 02:21:10 PM PDT 24
Finished	Mar 26 02:33:53 PM PDT 24
Peak memory	200116 kb
Host	smart-00699928-f965-4cd9-b44c-62cf6b48ccd1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=432542523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.432542523
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.3941028551
Short name	T671
Test name
Test status
Simulation time	2320395565 ps
CPU time	11.73 seconds
Started	Mar 26 02:21:10 PM PDT 24
Finished	Mar 26 02:21:21 PM PDT 24
Peak memory	199056 kb
Host	smart-fb827cde-ebc8-4538-87a2-e2720c5fb902
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3941028551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3941028551
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.3766452637
Short name	T643
Test name
Test status
Simulation time	19231955724 ps
CPU time	38.91 seconds
Started	Mar 26 02:21:08 PM PDT 24
Finished	Mar 26 02:21:47 PM PDT 24
Peak memory	200144 kb
Host	smart-b9c2a0f3-286c-453e-8116-186bd7ee5551
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766452637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3766452637
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.485119689
Short name	T557
Test name
Test status
Simulation time	3543418187 ps
CPU time	2.82 seconds
Started	Mar 26 02:21:08 PM PDT 24
Finished	Mar 26 02:21:11 PM PDT 24
Peak memory	195892 kb
Host	smart-a1ce7db0-ff2a-47fa-9b3e-65b13e0c26a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485119689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.485119689
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.731946095
Short name	T406
Test name
Test status
Simulation time	430626507 ps
CPU time	1.62 seconds
Started	Mar 26 02:21:08 PM PDT 24
Finished	Mar 26 02:21:10 PM PDT 24
Peak memory	199648 kb
Host	smart-32cba626-3fdd-4db3-a1c3-65dc28b7703f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731946095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.731946095
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_stress_all.3552762751
Short name	T1009
Test name
Test status
Simulation time	150947177681 ps
CPU time	764.76 seconds
Started	Mar 26 02:21:22 PM PDT 24
Finished	Mar 26 02:34:07 PM PDT 24
Peak memory	200252 kb
Host	smart-ab697866-f5c5-4611-bd26-2031d9f04252
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552762751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3552762751
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.1067355313
Short name	T539
Test name
Test status
Simulation time	7113505986 ps
CPU time	20.5 seconds
Started	Mar 26 02:21:10 PM PDT 24
Finished	Mar 26 02:21:31 PM PDT 24
Peak memory	199500 kb
Host	smart-7bb27047-08ab-4ee2-9d0a-bc6ea025d977
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067355313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1067355313
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.2505707674
Short name	T1073
Test name
Test status
Simulation time	32487373863 ps
CPU time	47.73 seconds
Started	Mar 26 02:21:09 PM PDT 24
Finished	Mar 26 02:21:57 PM PDT 24
Peak memory	200096 kb
Host	smart-de1adf62-8c41-49b0-bdc5-7e56d8f0239c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505707674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2505707674
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.2361513080
Short name	T523
Test name
Test status
Simulation time	5223048334 ps
CPU time	10.78 seconds
Started	Mar 26 02:28:55 PM PDT 24
Finished	Mar 26 02:29:06 PM PDT 24
Peak memory	198672 kb
Host	smart-70b3fa38-2714-4dbf-bdef-08d0c5ef7ec7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361513080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2361513080
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.149901850
Short name	T3
Test name
Test status
Simulation time	72729648399 ps
CPU time	30.27 seconds
Started	Mar 26 02:29:09 PM PDT 24
Finished	Mar 26 02:29:40 PM PDT 24
Peak memory	200036 kb
Host	smart-5cd626a3-44f2-4aea-bb87-9d22d5ad2145
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149901850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.149901850
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.2754622478
Short name	T1040
Test name
Test status
Simulation time	69273609479 ps
CPU time	19 seconds
Started	Mar 26 02:29:07 PM PDT 24
Finished	Mar 26 02:29:27 PM PDT 24
Peak memory	200040 kb
Host	smart-21b43847-52ec-48a8-a475-062d4e39c6cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754622478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2754622478
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.860484907
Short name	T943
Test name
Test status
Simulation time	188248592346 ps
CPU time	65.26 seconds
Started	Mar 26 02:29:08 PM PDT 24
Finished	Mar 26 02:30:14 PM PDT 24
Peak memory	200088 kb
Host	smart-d4aeba1c-1759-4481-b5f9-4f6828aadd20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860484907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.860484907
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.3093659604
Short name	T632
Test name
Test status
Simulation time	57099225623 ps
CPU time	93.19 seconds
Started	Mar 26 02:29:08 PM PDT 24
Finished	Mar 26 02:30:41 PM PDT 24
Peak memory	200152 kb
Host	smart-d8f29109-4e84-4937-9c9c-b02f3803eee3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093659604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3093659604
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.2982604495
Short name	T844
Test name
Test status
Simulation time	46311863704 ps
CPU time	80.05 seconds
Started	Mar 26 02:29:08 PM PDT 24
Finished	Mar 26 02:30:28 PM PDT 24
Peak memory	200156 kb
Host	smart-36af3a01-4b71-4801-bd44-1d7d98585bc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982604495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2982604495
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.1173317367
Short name	T670
Test name
Test status
Simulation time	94964380035 ps
CPU time	59.29 seconds
Started	Mar 26 02:29:08 PM PDT 24
Finished	Mar 26 02:30:08 PM PDT 24
Peak memory	200076 kb
Host	smart-e359c366-19c6-4e1d-8786-be9b8fc64f2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1173317367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1173317367
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.935383211
Short name	T994
Test name
Test status
Simulation time	65610614823 ps
CPU time	34.36 seconds
Started	Mar 26 02:29:08 PM PDT 24
Finished	Mar 26 02:29:42 PM PDT 24
Peak memory	200052 kb
Host	smart-8d746712-91e6-4e0a-82d0-81ac89af03c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935383211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.935383211
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.1008581931
Short name	T918
Test name
Test status
Simulation time	17834141 ps
CPU time	0.58 seconds
Started	Mar 26 02:21:19 PM PDT 24
Finished	Mar 26 02:21:20 PM PDT 24
Peak memory	195476 kb
Host	smart-b9058434-9856-46cc-b3e3-286790da6a68
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008581931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1008581931
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.1612362501
Short name	T625
Test name
Test status
Simulation time	151563797624 ps
CPU time	40.28 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:22:00 PM PDT 24
Peak memory	200120 kb
Host	smart-5db9030b-abd9-4289-9987-0af0d385cb69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612362501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1612362501
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.740053449
Short name	T763
Test name
Test status
Simulation time	68551326613 ps
CPU time	23.61 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:21:44 PM PDT 24
Peak memory	199636 kb
Host	smart-b893348f-05d7-4156-94ee-8e6f1e2c637a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=740053449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.740053449
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_fifo_reset.3342945341
Short name	T475
Test name
Test status
Simulation time	109793773941 ps
CPU time	117.19 seconds
Started	Mar 26 02:21:19 PM PDT 24
Finished	Mar 26 02:23:17 PM PDT 24
Peak memory	200056 kb
Host	smart-de217a66-2b93-40e3-8970-47ae84ffe07b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342945341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3342945341
Directory	/workspace/17.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_intr.2358076422
Short name	T958
Test name
Test status
Simulation time	11203621896 ps
CPU time	17.13 seconds
Started	Mar 26 02:21:19 PM PDT 24
Finished	Mar 26 02:21:36 PM PDT 24
Peak memory	198012 kb
Host	smart-fe6de1ab-a7ab-4d5e-af94-a4bebacb00d2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358076422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2358076422
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.3784882687
Short name	T1103
Test name
Test status
Simulation time	82135646256 ps
CPU time	251.64 seconds
Started	Mar 26 02:21:22 PM PDT 24
Finished	Mar 26 02:25:34 PM PDT 24
Peak memory	200128 kb
Host	smart-2c0e275d-3dea-4b8e-861d-62bb0e493bf6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3784882687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3784882687
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.1095238793
Short name	T378
Test name
Test status
Simulation time	11182785083 ps
CPU time	7.2 seconds
Started	Mar 26 02:21:17 PM PDT 24
Finished	Mar 26 02:21:25 PM PDT 24
Peak memory	199752 kb
Host	smart-ecfd209a-0598-44ca-b731-1f38817cd7f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095238793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1095238793
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.3639580804
Short name	T1023
Test name
Test status
Simulation time	77209132700 ps
CPU time	91.68 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:22:51 PM PDT 24
Peak memory	200196 kb
Host	smart-a14f75f1-2a1b-4959-a5ba-27ab4036c5e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639580804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3639580804
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.2549439369
Short name	T119
Test name
Test status
Simulation time	30194521486 ps
CPU time	1701.97 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:49:42 PM PDT 24
Peak memory	200140 kb
Host	smart-e340ef20-7cfd-4660-b4f4-9eae290c9377
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2549439369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2549439369
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.3575863315
Short name	T373
Test name
Test status
Simulation time	4824163918 ps
CPU time	4.68 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:21:24 PM PDT 24
Peak memory	198764 kb
Host	smart-00c79d19-9c4c-4551-a38c-f4e0bd1ccb2d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3575863315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3575863315
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.4126982714
Short name	T661
Test name
Test status
Simulation time	121414908056 ps
CPU time	333.1 seconds
Started	Mar 26 02:21:22 PM PDT 24
Finished	Mar 26 02:26:56 PM PDT 24
Peak memory	200076 kb
Host	smart-a9a68730-83f0-4ebb-920c-bcdf2d40f7f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126982714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4126982714
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.504673534
Short name	T287
Test name
Test status
Simulation time	3883703712 ps
CPU time	6.09 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:21:26 PM PDT 24
Peak memory	196376 kb
Host	smart-307b62cc-c5d0-424e-a73c-756053276821
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504673534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.504673534
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.4008650930
Short name	T58
Test name
Test status
Simulation time	6276380457 ps
CPU time	15.89 seconds
Started	Mar 26 02:21:20 PM PDT 24
Finished	Mar 26 02:21:36 PM PDT 24
Peak memory	200060 kb
Host	smart-cfaadd77-e356-41e6-a5a2-fed67c13a8a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008650930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4008650930
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.1534378759
Short name	T908
Test name
Test status
Simulation time	2088883130 ps
CPU time	1.67 seconds
Started	Mar 26 02:21:21 PM PDT 24
Finished	Mar 26 02:21:22 PM PDT 24
Peak memory	198388 kb
Host	smart-12d29c33-42be-48e9-bb15-0e2a2c4fa5ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534378759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1534378759
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.97352815
Short name	T360
Test name
Test status
Simulation time	11549556594 ps
CPU time	4.37 seconds
Started	Mar 26 02:21:18 PM PDT 24
Finished	Mar 26 02:21:23 PM PDT 24
Peak memory	197748 kb
Host	smart-88566f1b-697d-4507-835e-0acc70a12d60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97352815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.97352815
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.599157382
Short name	T589
Test name
Test status
Simulation time	19118621857 ps
CPU time	34.16 seconds
Started	Mar 26 02:29:08 PM PDT 24
Finished	Mar 26 02:29:43 PM PDT 24
Peak memory	200048 kb
Host	smart-4b6d7a58-3b78-4fbd-9793-67d17f52e3bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599157382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.599157382
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.2339417064
Short name	T1019
Test name
Test status
Simulation time	249390703996 ps
CPU time	615.43 seconds
Started	Mar 26 02:29:07 PM PDT 24
Finished	Mar 26 02:39:23 PM PDT 24
Peak memory	200080 kb
Host	smart-162ece16-1a29-4ae1-887c-c43e65382b26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339417064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2339417064
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/172.uart_fifo_reset.2823461698
Short name	T945
Test name
Test status
Simulation time	131769576704 ps
CPU time	249.16 seconds
Started	Mar 26 02:29:07 PM PDT 24
Finished	Mar 26 02:33:16 PM PDT 24
Peak memory	199980 kb
Host	smart-79d205d7-2216-4d7f-ba04-ee6ed2de6cc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823461698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2823461698
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.959646019
Short name	T931
Test name
Test status
Simulation time	127153344978 ps
CPU time	51.75 seconds
Started	Mar 26 02:29:18 PM PDT 24
Finished	Mar 26 02:30:10 PM PDT 24
Peak memory	200108 kb
Host	smart-455b6b1a-6293-47ae-8547-f81a08edfa2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959646019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.959646019
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.3265066190
Short name	T491
Test name
Test status
Simulation time	17063119530 ps
CPU time	29.64 seconds
Started	Mar 26 02:29:22 PM PDT 24
Finished	Mar 26 02:29:52 PM PDT 24
Peak memory	199944 kb
Host	smart-ec2a94cc-5568-4a96-b84b-f93f1cb6cf3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3265066190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3265066190
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.771108664
Short name	T593
Test name
Test status
Simulation time	70332860864 ps
CPU time	122.71 seconds
Started	Mar 26 02:29:16 PM PDT 24
Finished	Mar 26 02:31:19 PM PDT 24
Peak memory	200064 kb
Host	smart-7c1cd69f-a79d-47cc-9025-b0eaa58a0da1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771108664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.771108664
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.3337450844
Short name	T185
Test name
Test status
Simulation time	100878442301 ps
CPU time	153.57 seconds
Started	Mar 26 02:29:17 PM PDT 24
Finished	Mar 26 02:31:51 PM PDT 24
Peak memory	200056 kb
Host	smart-fb91e269-24d8-416d-a703-fb0a46f9cd26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337450844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3337450844
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.1098332765
Short name	T272
Test name
Test status
Simulation time	17264226028 ps
CPU time	22.59 seconds
Started	Mar 26 02:29:18 PM PDT 24
Finished	Mar 26 02:29:40 PM PDT 24
Peak memory	200120 kb
Host	smart-ba52b054-63f8-4e36-b5c2-6639efb464c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098332765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1098332765
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.3897216353
Short name	T1038
Test name
Test status
Simulation time	148300048924 ps
CPU time	137.27 seconds
Started	Mar 26 02:29:17 PM PDT 24
Finished	Mar 26 02:31:35 PM PDT 24
Peak memory	200072 kb
Host	smart-55b30d7a-40f3-4cde-8e97-4435a3bbfb96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897216353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3897216353
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_alert_test.1717723542
Short name	T1097
Test name
Test status
Simulation time	44808765 ps
CPU time	0.58 seconds
Started	Mar 26 02:21:34 PM PDT 24
Finished	Mar 26 02:21:35 PM PDT 24
Peak memory	195576 kb
Host	smart-b1099724-9b23-481a-a578-d65f63f1dbe6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717723542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1717723542
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.4040303523
Short name	T613
Test name
Test status
Simulation time	130698221163 ps
CPU time	56.1 seconds
Started	Mar 26 02:21:32 PM PDT 24
Finished	Mar 26 02:22:29 PM PDT 24
Peak memory	200012 kb
Host	smart-d0555903-bbe3-40ef-a893-c11f0e37719e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040303523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.4040303523
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.1397395564
Short name	T190
Test name
Test status
Simulation time	347930238412 ps
CPU time	85.2 seconds
Started	Mar 26 02:21:33 PM PDT 24
Finished	Mar 26 02:22:58 PM PDT 24
Peak memory	200076 kb
Host	smart-f6168412-3e70-491a-8df5-3c73983890c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397395564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1397395564
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_intr.1840187570
Short name	T295
Test name
Test status
Simulation time	182416067546 ps
CPU time	266.86 seconds
Started	Mar 26 02:21:32 PM PDT 24
Finished	Mar 26 02:26:00 PM PDT 24
Peak memory	200112 kb
Host	smart-832b797a-d4a4-4fe5-80a0-bd5087d4eb5c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840187570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1840187570
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_loopback.1870373158
Short name	T889
Test name
Test status
Simulation time	6528546699 ps
CPU time	10.38 seconds
Started	Mar 26 02:21:32 PM PDT 24
Finished	Mar 26 02:21:42 PM PDT 24
Peak memory	198860 kb
Host	smart-a43e0b84-a40d-4029-ae3b-3842668a1d25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870373158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1870373158
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.347493686
Short name	T764
Test name
Test status
Simulation time	42041445120 ps
CPU time	74.31 seconds
Started	Mar 26 02:21:33 PM PDT 24
Finished	Mar 26 02:22:48 PM PDT 24
Peak memory	199020 kb
Host	smart-9a9c8f42-f132-45ed-879d-6b0a3dbdb5df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347493686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.347493686
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.2586757866
Short name	T317
Test name
Test status
Simulation time	3545671137 ps
CPU time	186.48 seconds
Started	Mar 26 02:21:34 PM PDT 24
Finished	Mar 26 02:24:41 PM PDT 24
Peak memory	200128 kb
Host	smart-56ecb397-0fcb-4d24-a6e6-1a71aa8a3692
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2586757866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2586757866
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.3397395593
Short name	T517
Test name
Test status
Simulation time	2230007923 ps
CPU time	12.18 seconds
Started	Mar 26 02:21:32 PM PDT 24
Finished	Mar 26 02:21:45 PM PDT 24
Peak memory	198244 kb
Host	smart-50fbfe3d-b799-46f5-b6d6-37b4187c091b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3397395593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3397395593
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.782513005
Short name	T804
Test name
Test status
Simulation time	196547924035 ps
CPU time	340.8 seconds
Started	Mar 26 02:21:33 PM PDT 24
Finished	Mar 26 02:27:14 PM PDT 24
Peak memory	199952 kb
Host	smart-b1d0fce0-0c77-43f4-8421-d1c2d787699a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782513005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.782513005
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.1000234809
Short name	T504
Test name
Test status
Simulation time	4814110683 ps
CPU time	2.36 seconds
Started	Mar 26 02:21:34 PM PDT 24
Finished	Mar 26 02:21:36 PM PDT 24
Peak memory	196196 kb
Host	smart-0b0e7bea-d1ec-4b07-88cd-b3b36236b1c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000234809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1000234809
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.801796929
Short name	T425
Test name
Test status
Simulation time	5762288791 ps
CPU time	18.94 seconds
Started	Mar 26 02:21:33 PM PDT 24
Finished	Mar 26 02:21:52 PM PDT 24
Peak memory	199924 kb
Host	smart-9c8afff1-9a7b-4044-804c-a19eec97d63a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801796929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.801796929
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_stress_all.1873556704
Short name	T772
Test name
Test status
Simulation time	382510851957 ps
CPU time	146.06 seconds
Started	Mar 26 02:21:32 PM PDT 24
Finished	Mar 26 02:23:59 PM PDT 24
Peak memory	208404 kb
Host	smart-eaa23e8f-66de-4562-8a09-24932e68a42e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873556704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1873556704
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.2976709632
Short name	T540
Test name
Test status
Simulation time	8473629159 ps
CPU time	9.67 seconds
Started	Mar 26 02:21:32 PM PDT 24
Finished	Mar 26 02:21:42 PM PDT 24
Peak memory	200056 kb
Host	smart-887e6546-264a-495b-88a6-4b54f9272930
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976709632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2976709632
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.1114187404
Short name	T263
Test name
Test status
Simulation time	85688414161 ps
CPU time	127.53 seconds
Started	Mar 26 02:29:17 PM PDT 24
Finished	Mar 26 02:31:25 PM PDT 24
Peak memory	200036 kb
Host	smart-38fa3bbf-5e63-405d-900b-b7666059a45b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114187404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1114187404
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.3966248899
Short name	T197
Test name
Test status
Simulation time	74277633425 ps
CPU time	17.17 seconds
Started	Mar 26 02:29:16 PM PDT 24
Finished	Mar 26 02:29:34 PM PDT 24
Peak memory	200084 kb
Host	smart-cc34aa08-1fd5-406a-a30f-581d09c90596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966248899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3966248899
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.2924013048
Short name	T235
Test name
Test status
Simulation time	74030440236 ps
CPU time	39.57 seconds
Started	Mar 26 02:29:17 PM PDT 24
Finished	Mar 26 02:29:57 PM PDT 24
Peak memory	200128 kb
Host	smart-d8db9d44-b1e1-437d-b7b4-68d9e4ac59cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924013048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2924013048
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.1443973396
Short name	T500
Test name
Test status
Simulation time	31917082487 ps
CPU time	24.92 seconds
Started	Mar 26 02:29:18 PM PDT 24
Finished	Mar 26 02:29:43 PM PDT 24
Peak memory	200044 kb
Host	smart-31f98473-bc8a-481c-9aba-1a246a907d0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443973396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1443973396
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.588101534
Short name	T983
Test name
Test status
Simulation time	18383027763 ps
CPU time	29.95 seconds
Started	Mar 26 02:29:17 PM PDT 24
Finished	Mar 26 02:29:47 PM PDT 24
Peak memory	200000 kb
Host	smart-034b7ec8-522e-48a5-8724-a8e0686d39d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588101534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.588101534
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.1913943539
Short name	T1098
Test name
Test status
Simulation time	115793653355 ps
CPU time	280.78 seconds
Started	Mar 26 02:29:27 PM PDT 24
Finished	Mar 26 02:34:08 PM PDT 24
Peak memory	200040 kb
Host	smart-926a9f32-e2cf-44ae-8a4c-9ca2ff91930d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913943539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1913943539
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.3018737413
Short name	T245
Test name
Test status
Simulation time	114996748611 ps
CPU time	42.09 seconds
Started	Mar 26 02:29:25 PM PDT 24
Finished	Mar 26 02:30:07 PM PDT 24
Peak memory	200100 kb
Host	smart-be198260-ada3-48e3-a94d-50164e76509a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018737413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3018737413
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.3655929538
Short name	T257
Test name
Test status
Simulation time	15038626000 ps
CPU time	6.91 seconds
Started	Mar 26 02:29:26 PM PDT 24
Finished	Mar 26 02:29:33 PM PDT 24
Peak memory	198580 kb
Host	smart-30789606-3b6a-4871-b005-8a9d874647d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655929538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3655929538
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.1966324781
Short name	T809
Test name
Test status
Simulation time	14321884 ps
CPU time	0.57 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:21:45 PM PDT 24
Peak memory	194924 kb
Host	smart-cc8e05e1-9a04-4382-8968-612db28e89f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966324781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1966324781
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.2576187331
Short name	T1045
Test name
Test status
Simulation time	87025355918 ps
CPU time	158.46 seconds
Started	Mar 26 02:21:33 PM PDT 24
Finished	Mar 26 02:24:12 PM PDT 24
Peak memory	200120 kb
Host	smart-ceb74b4a-226d-4242-b3ba-b2e8d9757cc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576187331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2576187331
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.954926630
Short name	T184
Test name
Test status
Simulation time	35892662260 ps
CPU time	61.38 seconds
Started	Mar 26 02:21:44 PM PDT 24
Finished	Mar 26 02:22:46 PM PDT 24
Peak memory	199912 kb
Host	smart-33453047-8748-4ef6-91eb-b34c2db1ea25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954926630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.954926630
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_intr.3577382117
Short name	T28
Test name
Test status
Simulation time	182869269096 ps
CPU time	156.41 seconds
Started	Mar 26 02:21:44 PM PDT 24
Finished	Mar 26 02:24:21 PM PDT 24
Peak memory	200020 kb
Host	smart-a376143c-c41c-4597-a956-e1c822d3d326
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577382117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3577382117
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.831655197
Short name	T389
Test name
Test status
Simulation time	84954361279 ps
CPU time	204.22 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:25:10 PM PDT 24
Peak memory	200044 kb
Host	smart-ed6e2eed-9eb9-4a09-92b8-fa620aef3803
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=831655197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.831655197
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/19.uart_loopback.1065197609
Short name	T1067
Test name
Test status
Simulation time	3045036267 ps
CPU time	6.04 seconds
Started	Mar 26 02:21:43 PM PDT 24
Finished	Mar 26 02:21:50 PM PDT 24
Peak memory	198564 kb
Host	smart-6351eeab-fb81-406a-adad-1bee62391fd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065197609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1065197609
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.4102999842
Short name	T793
Test name
Test status
Simulation time	24331685707 ps
CPU time	55.24 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:22:41 PM PDT 24
Peak memory	199280 kb
Host	smart-c02f973c-a3f9-4cd2-b9f8-8a00cbf0fe6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102999842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4102999842
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/19.uart_perf.432847731
Short name	T758
Test name
Test status
Simulation time	16108033677 ps
CPU time	870.9 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:36:16 PM PDT 24
Peak memory	200028 kb
Host	smart-1a7f6666-8a4c-406f-958b-38ab455bf3f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=432847731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.432847731
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.470550250
Short name	T1109
Test name
Test status
Simulation time	2877810678 ps
CPU time	4.64 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:21:51 PM PDT 24
Peak memory	198092 kb
Host	smart-de4b674e-0c30-42dd-8fff-031bdd2b1cd8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=470550250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.470550250
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.3015315374
Short name	T130
Test name
Test status
Simulation time	35555345740 ps
CPU time	35.9 seconds
Started	Mar 26 02:21:48 PM PDT 24
Finished	Mar 26 02:22:24 PM PDT 24
Peak memory	199928 kb
Host	smart-370f396d-832d-4d3c-a592-6d8ac446aaaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015315374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3015315374
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.1894536878
Short name	T320
Test name
Test status
Simulation time	1841803185 ps
CPU time	1.66 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:21:48 PM PDT 24
Peak memory	195556 kb
Host	smart-7593fe1b-fe07-4d5d-a2bc-f2518d85360e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894536878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1894536878
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.1578891618
Short name	T328
Test name
Test status
Simulation time	309342140 ps
CPU time	1.85 seconds
Started	Mar 26 02:21:30 PM PDT 24
Finished	Mar 26 02:21:33 PM PDT 24
Peak memory	198848 kb
Host	smart-39b36c66-b90c-46e5-9d39-4b5a9f43582a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578891618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1578891618
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_stress_all.1075079018
Short name	T821
Test name
Test status
Simulation time	19487373398 ps
CPU time	16.74 seconds
Started	Mar 26 02:21:44 PM PDT 24
Finished	Mar 26 02:22:01 PM PDT 24
Peak memory	200084 kb
Host	smart-ce977c39-7ac4-47d3-84fe-a0d7a4d8d79f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075079018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1075079018
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/19.uart_stress_all_with_rand_reset.1824549504
Short name	T45
Test name
Test status
Simulation time	182029306679 ps
CPU time	692.25 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:33:18 PM PDT 24
Peak memory	229740 kb
Host	smart-c718ffa5-27d4-4180-91a4-32c67c6a2515
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824549504 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1824549504
Directory	/workspace/19.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.1349036976
Short name	T22
Test name
Test status
Simulation time	1790195692 ps
CPU time	2.51 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:21:48 PM PDT 24
Peak memory	198388 kb
Host	smart-f2d5cabf-5286-45d5-b8fc-0f38b9fe4a59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349036976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1349036976
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.2979058651
Short name	T719
Test name
Test status
Simulation time	40417660810 ps
CPU time	69.08 seconds
Started	Mar 26 02:21:35 PM PDT 24
Finished	Mar 26 02:22:45 PM PDT 24
Peak memory	200072 kb
Host	smart-840caada-4dfe-4b28-a6ae-2b125047f091
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979058651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2979058651
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.3038068958
Short name	T898
Test name
Test status
Simulation time	29643129659 ps
CPU time	45.57 seconds
Started	Mar 26 02:29:24 PM PDT 24
Finished	Mar 26 02:30:10 PM PDT 24
Peak memory	200088 kb
Host	smart-3d26bcab-0fc7-4c2f-849c-2019dd0dc268
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038068958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3038068958
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.1194447318
Short name	T845
Test name
Test status
Simulation time	51930147034 ps
CPU time	92.18 seconds
Started	Mar 26 02:29:24 PM PDT 24
Finished	Mar 26 02:30:57 PM PDT 24
Peak memory	200008 kb
Host	smart-5b010f1c-8fe4-42ea-8544-c21294108652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194447318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1194447318
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.3530754192
Short name	T9
Test name
Test status
Simulation time	58327935432 ps
CPU time	43.64 seconds
Started	Mar 26 02:29:24 PM PDT 24
Finished	Mar 26 02:30:07 PM PDT 24
Peak memory	200076 kb
Host	smart-13d21e06-0986-4a01-96f9-4aded6757757
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530754192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3530754192
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.2892310290
Short name	T1121
Test name
Test status
Simulation time	14906343251 ps
CPU time	30.76 seconds
Started	Mar 26 02:29:25 PM PDT 24
Finished	Mar 26 02:29:56 PM PDT 24
Peak memory	200064 kb
Host	smart-d877022e-2f21-493c-a947-d7d7fecc0901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892310290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2892310290
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.2114441290
Short name	T438
Test name
Test status
Simulation time	24553459448 ps
CPU time	41.69 seconds
Started	Mar 26 02:29:26 PM PDT 24
Finished	Mar 26 02:30:07 PM PDT 24
Peak memory	200044 kb
Host	smart-e5c00f98-07da-4f98-b96b-17122ada043f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114441290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2114441290
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.4065755636
Short name	T827
Test name
Test status
Simulation time	11003793759 ps
CPU time	10.96 seconds
Started	Mar 26 02:29:26 PM PDT 24
Finished	Mar 26 02:29:37 PM PDT 24
Peak memory	199964 kb
Host	smart-9b283ca2-4932-418d-9e60-69e6a2edfb3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065755636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4065755636
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.1522049045
Short name	T808
Test name
Test status
Simulation time	121332008968 ps
CPU time	44.44 seconds
Started	Mar 26 02:29:26 PM PDT 24
Finished	Mar 26 02:30:10 PM PDT 24
Peak memory	200084 kb
Host	smart-456d4e31-688a-4a9f-b0a9-764e3442ce5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522049045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1522049045
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.1933117774
Short name	T805
Test name
Test status
Simulation time	97770324587 ps
CPU time	79.65 seconds
Started	Mar 26 02:29:33 PM PDT 24
Finished	Mar 26 02:30:53 PM PDT 24
Peak memory	200048 kb
Host	smart-fc67089c-981b-466e-8ea2-dbb0c28440fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933117774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1933117774
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.1712841301
Short name	T953
Test name
Test status
Simulation time	13734092 ps
CPU time	0.58 seconds
Started	Mar 26 02:19:45 PM PDT 24
Finished	Mar 26 02:19:45 PM PDT 24
Peak memory	195276 kb
Host	smart-ff58a038-dc18-47f4-a70d-438bebb565f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712841301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1712841301
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.900220433
Short name	T656
Test name
Test status
Simulation time	65257213365 ps
CPU time	27.34 seconds
Started	Mar 26 02:19:37 PM PDT 24
Finished	Mar 26 02:20:04 PM PDT 24
Peak memory	200152 kb
Host	smart-a260d482-45fc-4483-82fe-c56177147c7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900220433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.900220433
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.1814338568
Short name	T864
Test name
Test status
Simulation time	42291805728 ps
CPU time	72.43 seconds
Started	Mar 26 02:19:31 PM PDT 24
Finished	Mar 26 02:20:43 PM PDT 24
Peak memory	199920 kb
Host	smart-863ee7ec-ee54-4617-a1aa-bac931b22e2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814338568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1814338568
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.3682706457
Short name	T652
Test name
Test status
Simulation time	71862011315 ps
CPU time	46.42 seconds
Started	Mar 26 02:19:26 PM PDT 24
Finished	Mar 26 02:20:13 PM PDT 24
Peak memory	199924 kb
Host	smart-a24a78e0-8828-460b-8878-bc132cef83f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682706457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3682706457
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_intr.2275636549
Short name	T627
Test name
Test status
Simulation time	88471525212 ps
CPU time	36.35 seconds
Started	Mar 26 02:19:26 PM PDT 24
Finished	Mar 26 02:20:03 PM PDT 24
Peak memory	200044 kb
Host	smart-fc209cea-f34e-40f5-b5c2-f91c8f94c5d8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275636549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2275636549
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.2264486377
Short name	T729
Test name
Test status
Simulation time	163801908650 ps
CPU time	659.98 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:30:28 PM PDT 24
Peak memory	200092 kb
Host	smart-95c1c320-fcec-4065-a545-9d4f934e8d39
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2264486377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2264486377
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.2871307202
Short name	T751
Test name
Test status
Simulation time	14323266359 ps
CPU time	21.08 seconds
Started	Mar 26 02:19:36 PM PDT 24
Finished	Mar 26 02:19:58 PM PDT 24
Peak memory	200052 kb
Host	smart-70c534c2-0c1b-48cf-a0b8-a29fc938b317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871307202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2871307202
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.2428016593
Short name	T979
Test name
Test status
Simulation time	80297115434 ps
CPU time	56.79 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:20:24 PM PDT 24
Peak memory	200060 kb
Host	smart-4286ee2f-13ca-420f-be14-312255c44983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428016593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2428016593
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.3837872641
Short name	T292
Test name
Test status
Simulation time	14106277167 ps
CPU time	801.4 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:32:50 PM PDT 24
Peak memory	200092 kb
Host	smart-81ab412c-9983-4109-9460-85c4159ea03a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3837872641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3837872641
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.1880339574
Short name	T372
Test name
Test status
Simulation time	2208995622 ps
CPU time	12.23 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:19:39 PM PDT 24
Peak memory	198192 kb
Host	smart-beb81afa-f260-42c3-9a12-2e26cf8ff45c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1880339574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1880339574
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.3994195026
Short name	T457
Test name
Test status
Simulation time	39820265077 ps
CPU time	58.14 seconds
Started	Mar 26 02:19:36 PM PDT 24
Finished	Mar 26 02:20:35 PM PDT 24
Peak memory	196188 kb
Host	smart-bdabdd1e-131d-45c1-8caa-4a0e6e8561a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994195026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3994195026
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.2602111201
Short name	T38
Test name
Test status
Simulation time	61533644 ps
CPU time	0.87 seconds
Started	Mar 26 02:19:36 PM PDT 24
Finished	Mar 26 02:19:37 PM PDT 24
Peak memory	218308 kb
Host	smart-53fc0af3-e01e-4401-bc0b-8a007946c2c1
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602111201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2602111201
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/2.uart_smoke.2691892874
Short name	T379
Test name
Test status
Simulation time	631090425 ps
CPU time	2.23 seconds
Started	Mar 26 02:19:27 PM PDT 24
Finished	Mar 26 02:19:30 PM PDT 24
Peak memory	198844 kb
Host	smart-531d4e91-8732-4e28-99c9-6f7f4ae4c1af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691892874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2691892874
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_stress_all.627030574
Short name	T18
Test name
Test status
Simulation time	33203717164 ps
CPU time	68.9 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:20:37 PM PDT 24
Peak memory	200052 kb
Host	smart-87f90b23-d16d-446d-b491-c3032265a646
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627030574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.627030574
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.541947756
Short name	T1051
Test name
Test status
Simulation time	787051511 ps
CPU time	1.79 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:19:30 PM PDT 24
Peak memory	198708 kb
Host	smart-cffb3acc-b07b-480d-8059-de5e29c18e1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541947756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.541947756
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.3873400695
Short name	T531
Test name
Test status
Simulation time	28994239803 ps
CPU time	60.72 seconds
Started	Mar 26 02:19:28 PM PDT 24
Finished	Mar 26 02:20:29 PM PDT 24
Peak memory	200080 kb
Host	smart-61390191-5a3e-4d7b-a098-496a3bc4e427
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873400695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3873400695
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_alert_test.1656989918
Short name	T382
Test name
Test status
Simulation time	46207117 ps
CPU time	0.55 seconds
Started	Mar 26 02:21:47 PM PDT 24
Finished	Mar 26 02:21:48 PM PDT 24
Peak memory	195456 kb
Host	smart-eeee03b5-3df9-4db2-bc96-1d7edfbb7184
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656989918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1656989918
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.4082271883
Short name	T937
Test name
Test status
Simulation time	44305533894 ps
CPU time	44.64 seconds
Started	Mar 26 02:21:44 PM PDT 24
Finished	Mar 26 02:22:29 PM PDT 24
Peak memory	200020 kb
Host	smart-4b6e708d-6dd6-47a3-9ac5-5120e686c863
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082271883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4082271883
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.1206281266
Short name	T603
Test name
Test status
Simulation time	133791321723 ps
CPU time	541.24 seconds
Started	Mar 26 02:21:47 PM PDT 24
Finished	Mar 26 02:30:48 PM PDT 24
Peak memory	199904 kb
Host	smart-e2448abb-58b4-4169-94e5-852cdf5614c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206281266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1206281266
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.3822474599
Short name	T468
Test name
Test status
Simulation time	56311052883 ps
CPU time	49.33 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:22:35 PM PDT 24
Peak memory	200080 kb
Host	smart-bc9e206d-162d-4872-8e80-8858d6f0a2e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822474599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3822474599
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_intr.2993823171
Short name	T286
Test name
Test status
Simulation time	212661400900 ps
CPU time	335.88 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:27:22 PM PDT 24
Peak memory	200080 kb
Host	smart-8e0f4367-8539-4d6b-bd55-e71d095fcc6c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993823171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2993823171
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.3781314913
Short name	T281
Test name
Test status
Simulation time	267836529955 ps
CPU time	408.19 seconds
Started	Mar 26 02:21:49 PM PDT 24
Finished	Mar 26 02:28:37 PM PDT 24
Peak memory	200016 kb
Host	smart-78e9234b-47ee-4296-b577-5eb13f1a5e09
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3781314913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3781314913
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.3229807842
Short name	T742
Test name
Test status
Simulation time	3383088286 ps
CPU time	7.27 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:21:54 PM PDT 24
Peak memory	199172 kb
Host	smart-53c14d1a-cb38-4317-a789-d7221d7be356
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229807842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3229807842
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.1641090356
Short name	T314
Test name
Test status
Simulation time	40830978806 ps
CPU time	36.2 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:22:23 PM PDT 24
Peak memory	197360 kb
Host	smart-5e58eca9-5fcd-4eef-a551-a33a4198bce2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641090356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1641090356
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.3466849640
Short name	T877
Test name
Test status
Simulation time	17164753275 ps
CPU time	195.51 seconds
Started	Mar 26 02:21:48 PM PDT 24
Finished	Mar 26 02:25:04 PM PDT 24
Peak memory	200116 kb
Host	smart-36e23122-2ea5-42b0-8ed0-21fd57de650d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3466849640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3466849640
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.2408655310
Short name	T15
Test name
Test status
Simulation time	4291492948 ps
CPU time	4.4 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:21:51 PM PDT 24
Peak memory	199316 kb
Host	smart-52bb9e7d-015a-4ef3-b623-9ed9412037db
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2408655310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2408655310
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.1145266577
Short name	T988
Test name
Test status
Simulation time	17811582643 ps
CPU time	18.45 seconds
Started	Mar 26 02:21:47 PM PDT 24
Finished	Mar 26 02:22:06 PM PDT 24
Peak memory	199784 kb
Host	smart-3b87019f-2462-4be1-a1b0-5f8a835865d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145266577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1145266577
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.4169197760
Short name	T906
Test name
Test status
Simulation time	3368327200 ps
CPU time	5.99 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:21:52 PM PDT 24
Peak memory	196428 kb
Host	smart-c0cff4f3-14df-48c7-a63f-0e273a66abc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169197760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4169197760
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.3412070700
Short name	T428
Test name
Test status
Simulation time	466381725 ps
CPU time	2.23 seconds
Started	Mar 26 02:21:49 PM PDT 24
Finished	Mar 26 02:21:51 PM PDT 24
Peak memory	199824 kb
Host	smart-abc59b3e-c6bb-47d5-9788-5f12b63238cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412070700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3412070700
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.4201391198
Short name	T1070
Test name
Test status
Simulation time	288811064522 ps
CPU time	702 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:33:27 PM PDT 24
Peak memory	200132 kb
Host	smart-93a6176e-8313-488e-b5d5-d8f186adbf5a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201391198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4201391198
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.746029528
Short name	T631
Test name
Test status
Simulation time	966567448 ps
CPU time	3.22 seconds
Started	Mar 26 02:21:47 PM PDT 24
Finished	Mar 26 02:21:50 PM PDT 24
Peak memory	199024 kb
Host	smart-e0eff488-0171-4b8b-8fda-e91f25d45b8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746029528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.746029528
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.3666453360
Short name	T590
Test name
Test status
Simulation time	96039557022 ps
CPU time	228.37 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:25:33 PM PDT 24
Peak memory	200080 kb
Host	smart-a1e88516-b490-4a37-b135-06616516e88c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666453360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3666453360
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.1877279525
Short name	T291
Test name
Test status
Simulation time	68933266970 ps
CPU time	142.63 seconds
Started	Mar 26 02:29:33 PM PDT 24
Finished	Mar 26 02:31:56 PM PDT 24
Peak memory	199980 kb
Host	smart-1470b410-d843-4015-9a42-5c213bd1f3d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877279525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1877279525
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.949134375
Short name	T633
Test name
Test status
Simulation time	100986412998 ps
CPU time	136.1 seconds
Started	Mar 26 02:29:34 PM PDT 24
Finished	Mar 26 02:31:50 PM PDT 24
Peak memory	199968 kb
Host	smart-4f4e7592-00ba-4504-94a5-fc1795dc9d87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949134375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.949134375
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.2036828926
Short name	T1064
Test name
Test status
Simulation time	74368586090 ps
CPU time	127.8 seconds
Started	Mar 26 02:29:34 PM PDT 24
Finished	Mar 26 02:31:42 PM PDT 24
Peak memory	200084 kb
Host	smart-265d0bd0-5c27-492d-aa28-24ae14f7c859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036828926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2036828926
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.3373701652
Short name	T4
Test name
Test status
Simulation time	59377296552 ps
CPU time	22.37 seconds
Started	Mar 26 02:29:33 PM PDT 24
Finished	Mar 26 02:29:55 PM PDT 24
Peak memory	200080 kb
Host	smart-5c46a699-e0b7-488d-8ace-245866a6df6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373701652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3373701652
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.2580265185
Short name	T553
Test name
Test status
Simulation time	25866577674 ps
CPU time	45.23 seconds
Started	Mar 26 02:29:36 PM PDT 24
Finished	Mar 26 02:30:22 PM PDT 24
Peak memory	200104 kb
Host	smart-de23415b-4ac8-4ac5-bb13-851bffd39c7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580265185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2580265185
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.1463349758
Short name	T1068
Test name
Test status
Simulation time	44999428021 ps
CPU time	21.78 seconds
Started	Mar 26 02:29:33 PM PDT 24
Finished	Mar 26 02:29:55 PM PDT 24
Peak memory	200148 kb
Host	smart-b368715c-8a69-4f41-be4e-4d996733d63d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463349758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1463349758
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.3208854944
Short name	T1036
Test name
Test status
Simulation time	109005172109 ps
CPU time	47.73 seconds
Started	Mar 26 02:29:32 PM PDT 24
Finished	Mar 26 02:30:20 PM PDT 24
Peak memory	200148 kb
Host	smart-e265ed67-8168-4dac-9118-8a3a3230f61a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208854944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3208854944
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.1257826268
Short name	T1010
Test name
Test status
Simulation time	19764785 ps
CPU time	0.56 seconds
Started	Mar 26 02:21:56 PM PDT 24
Finished	Mar 26 02:21:57 PM PDT 24
Peak memory	194532 kb
Host	smart-96898f57-edbb-4e4a-b1c0-46ac301a8b6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257826268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1257826268
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.1123704587
Short name	T796
Test name
Test status
Simulation time	13440741223 ps
CPU time	6.18 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:21:53 PM PDT 24
Peak memory	199836 kb
Host	smart-62a1e10e-8a9f-40b4-bae8-bc6c402bd8e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123704587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1123704587
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.4081353573
Short name	T1091
Test name
Test status
Simulation time	83053203267 ps
CPU time	159.72 seconds
Started	Mar 26 02:21:49 PM PDT 24
Finished	Mar 26 02:24:29 PM PDT 24
Peak memory	200108 kb
Host	smart-292d90d3-de4f-448b-9ade-16ea94fd3119
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081353573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.4081353573
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.1486002302
Short name	T787
Test name
Test status
Simulation time	80359443294 ps
CPU time	13.46 seconds
Started	Mar 26 02:21:45 PM PDT 24
Finished	Mar 26 02:21:59 PM PDT 24
Peak memory	198660 kb
Host	smart-28b422a6-951d-4390-83e0-c512fc0407f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486002302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1486002302
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_intr.2325235361
Short name	T856
Test name
Test status
Simulation time	21108256827 ps
CPU time	13.8 seconds
Started	Mar 26 02:21:55 PM PDT 24
Finished	Mar 26 02:22:09 PM PDT 24
Peak memory	200092 kb
Host	smart-ab94b3b7-4152-4e0e-9ecc-7226909c3672
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325235361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2325235361
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.3635763526
Short name	T136
Test name
Test status
Simulation time	97025345436 ps
CPU time	694.21 seconds
Started	Mar 26 02:21:57 PM PDT 24
Finished	Mar 26 02:33:32 PM PDT 24
Peak memory	200040 kb
Host	smart-97b2fb75-373f-45a0-a916-a8402409f0d8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3635763526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3635763526
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.1942990269
Short name	T960
Test name
Test status
Simulation time	400893025 ps
CPU time	0.94 seconds
Started	Mar 26 02:22:05 PM PDT 24
Finished	Mar 26 02:22:06 PM PDT 24
Peak memory	195604 kb
Host	smart-2948ef15-50c0-4d65-b1fa-f78a21ad86c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942990269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1942990269
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.3001722111
Short name	T498
Test name
Test status
Simulation time	199659852796 ps
CPU time	82.13 seconds
Started	Mar 26 02:21:56 PM PDT 24
Finished	Mar 26 02:23:18 PM PDT 24
Peak memory	200168 kb
Host	smart-04d54ea3-c525-4ca9-bd34-3054d6c81a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001722111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3001722111
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_perf.1984060774
Short name	T1055
Test name
Test status
Simulation time	4069135429 ps
CPU time	198.47 seconds
Started	Mar 26 02:21:55 PM PDT 24
Finished	Mar 26 02:25:13 PM PDT 24
Peak memory	200008 kb
Host	smart-625679b0-1b1f-4449-b7e3-d9860df011f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1984060774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1984060774
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.1821601708
Short name	T819
Test name
Test status
Simulation time	5644605483 ps
CPU time	42.81 seconds
Started	Mar 26 02:21:47 PM PDT 24
Finished	Mar 26 02:22:30 PM PDT 24
Peak memory	198760 kb
Host	smart-e63f935e-7c0f-4972-b173-4bc44842df11
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1821601708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1821601708
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.4031535620
Short name	T847
Test name
Test status
Simulation time	82741464777 ps
CPU time	127.31 seconds
Started	Mar 26 02:21:55 PM PDT 24
Finished	Mar 26 02:24:02 PM PDT 24
Peak memory	200152 kb
Host	smart-84406578-430b-41e3-a734-8750b56aa094
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031535620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4031535620
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.89627115
Short name	T416
Test name
Test status
Simulation time	3815321768 ps
CPU time	6.78 seconds
Started	Mar 26 02:21:55 PM PDT 24
Finished	Mar 26 02:22:02 PM PDT 24
Peak memory	196232 kb
Host	smart-e0b87b76-574b-4938-bf8d-5f4d69b6cee9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89627115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.89627115
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.2271683826
Short name	T1071
Test name
Test status
Simulation time	455306285 ps
CPU time	1.7 seconds
Started	Mar 26 02:21:46 PM PDT 24
Finished	Mar 26 02:21:47 PM PDT 24
Peak memory	199960 kb
Host	smart-46e255ae-5c96-40fe-8695-cb2c3a4de4a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2271683826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2271683826
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_stress_all.276903688
Short name	T1099
Test name
Test status
Simulation time	70812671504 ps
CPU time	123.28 seconds
Started	Mar 26 02:21:57 PM PDT 24
Finished	Mar 26 02:24:01 PM PDT 24
Peak memory	200004 kb
Host	smart-d3d5a76b-ab3e-411b-872b-47cd98f72ef4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276903688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.276903688
Directory	/workspace/21.uart_stress_all/latest

Test location	/workspace/coverage/default/21.uart_stress_all_with_rand_reset.1349046826
Short name	T195
Test name
Test status
Simulation time	67645433226 ps
CPU time	197.66 seconds
Started	Mar 26 02:21:56 PM PDT 24
Finished	Mar 26 02:25:13 PM PDT 24
Peak memory	215508 kb
Host	smart-7d5e9d8e-bb4b-4ee1-9c7d-3f56ce9a1ba0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349046826 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1349046826
Directory	/workspace/21.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.3327237429
Short name	T708
Test name
Test status
Simulation time	579140007 ps
CPU time	2.27 seconds
Started	Mar 26 02:21:56 PM PDT 24
Finished	Mar 26 02:21:58 PM PDT 24
Peak memory	198988 kb
Host	smart-445fc55c-9deb-46da-91b4-cd8458208a2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3327237429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3327237429
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.1001941
Short name	T515
Test name
Test status
Simulation time	99567166885 ps
CPU time	43.5 seconds
Started	Mar 26 02:21:48 PM PDT 24
Finished	Mar 26 02:22:31 PM PDT 24
Peak memory	200104 kb
Host	smart-ab2b9a58-25a3-4563-87aa-165e47647da1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1001941
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.3861568393
Short name	T895
Test name
Test status
Simulation time	68943972626 ps
CPU time	26.72 seconds
Started	Mar 26 02:29:42 PM PDT 24
Finished	Mar 26 02:30:10 PM PDT 24
Peak memory	199916 kb
Host	smart-b0bffdb1-a978-4c42-b29d-e4626964cc6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861568393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3861568393
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.987209104
Short name	T846
Test name
Test status
Simulation time	66614533306 ps
CPU time	101.22 seconds
Started	Mar 26 02:29:44 PM PDT 24
Finished	Mar 26 02:31:26 PM PDT 24
Peak memory	199884 kb
Host	smart-963e76b8-b522-4bce-8e56-9f2297c3e443
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987209104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.987209104
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.3338369152
Short name	T177
Test name
Test status
Simulation time	123713544595 ps
CPU time	51.73 seconds
Started	Mar 26 02:29:42 PM PDT 24
Finished	Mar 26 02:30:34 PM PDT 24
Peak memory	199980 kb
Host	smart-7c95819a-bee4-4a30-accb-b8ce12d4865c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338369152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3338369152
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.468175858
Short name	T1090
Test name
Test status
Simulation time	16657515497 ps
CPU time	13.21 seconds
Started	Mar 26 02:29:44 PM PDT 24
Finished	Mar 26 02:29:58 PM PDT 24
Peak memory	200068 kb
Host	smart-8a02b849-5d1e-4d24-a5f9-b2d44241611c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468175858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.468175858
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.2007910104
Short name	T885
Test name
Test status
Simulation time	82189384620 ps
CPU time	27.46 seconds
Started	Mar 26 02:29:44 PM PDT 24
Finished	Mar 26 02:30:12 PM PDT 24
Peak memory	199980 kb
Host	smart-84076d03-96ce-4177-b5dd-792a2c87a507
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007910104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2007910104
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.755798565
Short name	T989
Test name
Test status
Simulation time	347159967097 ps
CPU time	50.06 seconds
Started	Mar 26 02:29:45 PM PDT 24
Finished	Mar 26 02:30:36 PM PDT 24
Peak memory	200044 kb
Host	smart-294c6747-0c65-49f6-8f20-edcb780ad008
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755798565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.755798565
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.834918635
Short name	T479
Test name
Test status
Simulation time	134341214977 ps
CPU time	71.49 seconds
Started	Mar 26 02:29:43 PM PDT 24
Finished	Mar 26 02:30:54 PM PDT 24
Peak memory	200048 kb
Host	smart-82ddc0c5-0491-4561-a15b-f8801cb08d7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834918635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.834918635
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.1122053848
Short name	T471
Test name
Test status
Simulation time	23219978796 ps
CPU time	38.38 seconds
Started	Mar 26 02:29:44 PM PDT 24
Finished	Mar 26 02:30:23 PM PDT 24
Peak memory	200140 kb
Host	smart-aedfcc33-14f2-4d95-8a4e-4f38a949e905
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122053848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1122053848
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.2448964094
Short name	T781
Test name
Test status
Simulation time	191631196614 ps
CPU time	86.03 seconds
Started	Mar 26 02:29:44 PM PDT 24
Finished	Mar 26 02:31:11 PM PDT 24
Peak memory	200068 kb
Host	smart-8abb1a08-94fd-44bd-98fe-6f6578dc12a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448964094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2448964094
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.1562101520
Short name	T782
Test name
Test status
Simulation time	17363080983 ps
CPU time	8.62 seconds
Started	Mar 26 02:29:42 PM PDT 24
Finished	Mar 26 02:29:51 PM PDT 24
Peak memory	200156 kb
Host	smart-3c48dcd1-e37e-4baf-849e-aa6ea4339513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562101520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1562101520
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.199311640
Short name	T583
Test name
Test status
Simulation time	19168804 ps
CPU time	0.54 seconds
Started	Mar 26 02:22:09 PM PDT 24
Finished	Mar 26 02:22:10 PM PDT 24
Peak memory	195540 kb
Host	smart-c81a09ae-6efb-4fa7-a02c-992fe0c272c8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199311640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.199311640
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.3017043191
Short name	T347
Test name
Test status
Simulation time	147845772229 ps
CPU time	59.82 seconds
Started	Mar 26 02:22:05 PM PDT 24
Finished	Mar 26 02:23:06 PM PDT 24
Peak memory	200100 kb
Host	smart-4469f379-1d7a-472a-9d7c-613b61bbea17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017043191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3017043191
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.4166370443
Short name	T1120
Test name
Test status
Simulation time	115883836681 ps
CPU time	47.76 seconds
Started	Mar 26 02:21:57 PM PDT 24
Finished	Mar 26 02:22:45 PM PDT 24
Peak memory	200144 kb
Host	smart-9c893d50-494a-4356-83d7-d20dec5cbb9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166370443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4166370443
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.2372838794
Short name	T512
Test name
Test status
Simulation time	10534309544 ps
CPU time	15.48 seconds
Started	Mar 26 02:21:58 PM PDT 24
Finished	Mar 26 02:22:14 PM PDT 24
Peak memory	199664 kb
Host	smart-67ad7f49-6ef9-43d2-9500-d7f3a2d83d62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372838794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2372838794
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.1256626220
Short name	T1084
Test name
Test status
Simulation time	186153174196 ps
CPU time	297.79 seconds
Started	Mar 26 02:21:54 PM PDT 24
Finished	Mar 26 02:26:52 PM PDT 24
Peak memory	199804 kb
Host	smart-9b542ce5-17a0-45d5-a9d2-058c3acd66b1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256626220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1256626220
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.2255506516
Short name	T1087
Test name
Test status
Simulation time	235433412884 ps
CPU time	153.55 seconds
Started	Mar 26 02:22:11 PM PDT 24
Finished	Mar 26 02:24:44 PM PDT 24
Peak memory	200004 kb
Host	smart-2a6342b4-f5da-407a-b2df-bf9421c4556e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2255506516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2255506516
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.2596100204
Short name	T570
Test name
Test status
Simulation time	3104812195 ps
CPU time	1.59 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:22:10 PM PDT 24
Peak memory	199020 kb
Host	smart-d0fcccb1-a210-4af7-9bc4-861e80330ba9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596100204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2596100204
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.631957223
Short name	T970
Test name
Test status
Simulation time	157404440547 ps
CPU time	192.85 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:25:21 PM PDT 24
Peak memory	208280 kb
Host	smart-4d9a77bb-f768-4e03-a651-b615d6b0709d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631957223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.631957223
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.4136391354
Short name	T822
Test name
Test status
Simulation time	25255495074 ps
CPU time	1318.98 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:44:07 PM PDT 24
Peak memory	200092 kb
Host	smart-a6e7b623-43fe-4a59-9b21-1b3ae492a5e7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4136391354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4136391354
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.2501036187
Short name	T63
Test name
Test status
Simulation time	4753412715 ps
CPU time	3.95 seconds
Started	Mar 26 02:22:05 PM PDT 24
Finished	Mar 26 02:22:10 PM PDT 24
Peak memory	198200 kb
Host	smart-50705866-f0d6-40c6-8ffd-c6354e1b4dba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2501036187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2501036187
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.1437173911
Short name	T29
Test name
Test status
Simulation time	56789300679 ps
CPU time	94.52 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:23:43 PM PDT 24
Peak memory	200056 kb
Host	smart-15f97a25-7168-4859-be24-29a006038ff9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1437173911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1437173911
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.1685543808
Short name	T322
Test name
Test status
Simulation time	7153296146 ps
CPU time	11.88 seconds
Started	Mar 26 02:22:09 PM PDT 24
Finished	Mar 26 02:22:22 PM PDT 24
Peak memory	196204 kb
Host	smart-279082de-1de0-4ec2-9183-9ce1921a02e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685543808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1685543808
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.4024654478
Short name	T735
Test name
Test status
Simulation time	5475090182 ps
CPU time	19.43 seconds
Started	Mar 26 02:22:05 PM PDT 24
Finished	Mar 26 02:22:25 PM PDT 24
Peak memory	199808 kb
Host	smart-d9ff66bf-3ea3-427c-ac1e-3667fef75000
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024654478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.4024654478
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.53504749
Short name	T946
Test name
Test status
Simulation time	2951649751 ps
CPU time	3.73 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:22:12 PM PDT 24
Peak memory	200108 kb
Host	smart-f82b7d01-3a99-41b1-8fd0-f657f6a32e4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53504749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.53504749
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.1123051229
Short name	T1111
Test name
Test status
Simulation time	197960837916 ps
CPU time	137.72 seconds
Started	Mar 26 02:21:55 PM PDT 24
Finished	Mar 26 02:24:13 PM PDT 24
Peak memory	200020 kb
Host	smart-30b6a91e-8c13-4a28-9756-04d1e5816e12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123051229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1123051229
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.4252667218
Short name	T858
Test name
Test status
Simulation time	47851035417 ps
CPU time	18.32 seconds
Started	Mar 26 02:29:43 PM PDT 24
Finished	Mar 26 02:30:02 PM PDT 24
Peak memory	200188 kb
Host	smart-293fb1fa-e8f8-4680-a2cd-0af0c1a63d90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252667218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4252667218
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.1881893803
Short name	T604
Test name
Test status
Simulation time	144058405314 ps
CPU time	72.31 seconds
Started	Mar 26 02:29:57 PM PDT 24
Finished	Mar 26 02:31:10 PM PDT 24
Peak memory	200044 kb
Host	smart-f404fa05-6c09-4767-b14b-a4aef9fb2dc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881893803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1881893803
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.3397262977
Short name	T480
Test name
Test status
Simulation time	19956924863 ps
CPU time	32.13 seconds
Started	Mar 26 02:29:52 PM PDT 24
Finished	Mar 26 02:30:25 PM PDT 24
Peak memory	200000 kb
Host	smart-0845c5e9-2379-481d-8b61-8e8a39e719eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397262977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3397262977
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.3986935443
Short name	T1113
Test name
Test status
Simulation time	16384566583 ps
CPU time	29.09 seconds
Started	Mar 26 02:29:53 PM PDT 24
Finished	Mar 26 02:30:22 PM PDT 24
Peak memory	200108 kb
Host	smart-925b78df-c2b7-48da-9d08-81fc2917ab1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986935443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3986935443
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.2793325040
Short name	T489
Test name
Test status
Simulation time	139095957714 ps
CPU time	239.6 seconds
Started	Mar 26 02:29:54 PM PDT 24
Finished	Mar 26 02:33:54 PM PDT 24
Peak memory	199820 kb
Host	smart-184dfb5e-e8c1-40a8-bc8a-318511213995
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793325040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2793325040
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.1675640673
Short name	T238
Test name
Test status
Simulation time	42207954889 ps
CPU time	22.28 seconds
Started	Mar 26 02:29:53 PM PDT 24
Finished	Mar 26 02:30:16 PM PDT 24
Peak memory	200104 kb
Host	smart-36425166-5e9f-4f4f-9e71-c6736490f467
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675640673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1675640673
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.1160041540
Short name	T996
Test name
Test status
Simulation time	38146422281 ps
CPU time	15.97 seconds
Started	Mar 26 02:29:53 PM PDT 24
Finished	Mar 26 02:30:09 PM PDT 24
Peak memory	199432 kb
Host	smart-78d746f2-0ee7-4a9e-97e3-0b489528fdac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160041540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1160041540
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.4218586608
Short name	T676
Test name
Test status
Simulation time	56962433211 ps
CPU time	21.52 seconds
Started	Mar 26 02:29:55 PM PDT 24
Finished	Mar 26 02:30:17 PM PDT 24
Peak memory	200108 kb
Host	smart-c4b412b4-b2c1-4f7d-806f-46423177a7a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218586608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4218586608
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.1269658331
Short name	T581
Test name
Test status
Simulation time	90603189601 ps
CPU time	64.3 seconds
Started	Mar 26 02:29:53 PM PDT 24
Finished	Mar 26 02:30:58 PM PDT 24
Peak memory	200008 kb
Host	smart-6a7b64ad-85ba-40c6-9d8d-0cb1d61dd65d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1269658331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1269658331
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.3161804025
Short name	T618
Test name
Test status
Simulation time	124109321609 ps
CPU time	333.48 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:27:42 PM PDT 24
Peak memory	200148 kb
Host	smart-35bf66da-6415-4aef-9ffd-70cbe8b545cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161804025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3161804025
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.4119805786
Short name	T927
Test name
Test status
Simulation time	109970571827 ps
CPU time	54.02 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:23:02 PM PDT 24
Peak memory	200028 kb
Host	smart-e652bad4-8124-4ff0-b234-e7f31af24bda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119805786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4119805786
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.3836352806
Short name	T337
Test name
Test status
Simulation time	81693690007 ps
CPU time	73.42 seconds
Started	Mar 26 02:22:07 PM PDT 24
Finished	Mar 26 02:23:21 PM PDT 24
Peak memory	199976 kb
Host	smart-f48ac352-a8d5-4192-af62-4461518f422a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836352806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3836352806
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_intr.2913500728
Short name	T459
Test name
Test status
Simulation time	55876576424 ps
CPU time	49.5 seconds
Started	Mar 26 02:22:08 PM PDT 24
Finished	Mar 26 02:22:58 PM PDT 24
Peak memory	200116 kb
Host	smart-1f984126-0d98-4ec0-aeb1-b878dc188447
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913500728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2913500728
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.2419727024
Short name	T923
Test name
Test status
Simulation time	118601714658 ps
CPU time	1223.15 seconds
Started	Mar 26 02:22:16 PM PDT 24
Finished	Mar 26 02:42:40 PM PDT 24
Peak memory	200132 kb
Host	smart-cc40f921-e4af-4f85-8a07-c139dd002217
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2419727024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2419727024
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.20415026
Short name	T929
Test name
Test status
Simulation time	12245223441 ps
CPU time	3.75 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:22:22 PM PDT 24
Peak memory	200020 kb
Host	smart-34350b51-7f0b-4c92-964d-eefd005ca670
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20415026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.20415026
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.2059666145
Short name	T642
Test name
Test status
Simulation time	63340392213 ps
CPU time	90.22 seconds
Started	Mar 26 02:22:08 PM PDT 24
Finished	Mar 26 02:23:39 PM PDT 24
Peak memory	199868 kb
Host	smart-5ce53f70-2149-4595-9fda-ab2d74f1e2c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059666145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2059666145
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_perf.3039760432
Short name	T811
Test name
Test status
Simulation time	3118315227 ps
CPU time	182.91 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:25:21 PM PDT 24
Peak memory	199956 kb
Host	smart-05f4d0bd-a97f-4a79-935f-c379d49228e9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3039760432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3039760432
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.1265898991
Short name	T530
Test name
Test status
Simulation time	2429802864 ps
CPU time	2.23 seconds
Started	Mar 26 02:22:08 PM PDT 24
Finished	Mar 26 02:22:11 PM PDT 24
Peak memory	199200 kb
Host	smart-96534c95-dc4b-4403-9f42-dcb81f9a7186
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1265898991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1265898991
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.1820112608
Short name	T584
Test name
Test status
Simulation time	103944406320 ps
CPU time	191.27 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:25:30 PM PDT 24
Peak memory	200020 kb
Host	smart-c40a3891-0b06-46c5-b916-8ac6ff34df2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820112608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1820112608
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.3196317309
Short name	T1060
Test name
Test status
Simulation time	1884714857 ps
CPU time	1.39 seconds
Started	Mar 26 02:22:16 PM PDT 24
Finished	Mar 26 02:22:18 PM PDT 24
Peak memory	195556 kb
Host	smart-7a0587d6-0a3e-4c7a-b6b6-0f1f751eda11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196317309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3196317309
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.1800965563
Short name	T326
Test name
Test status
Simulation time	705981137 ps
CPU time	1.67 seconds
Started	Mar 26 02:22:06 PM PDT 24
Finished	Mar 26 02:22:08 PM PDT 24
Peak memory	198384 kb
Host	smart-585ad1fd-9d06-402f-8636-c2357e8fd0ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800965563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1800965563
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.1922084277
Short name	T972
Test name
Test status
Simulation time	6477466454 ps
CPU time	23.52 seconds
Started	Mar 26 02:22:19 PM PDT 24
Finished	Mar 26 02:22:43 PM PDT 24
Peak memory	199992 kb
Host	smart-2cdc7f75-0ebf-4509-8403-2df614796f9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922084277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1922084277
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.2685317120
Short name	T431
Test name
Test status
Simulation time	61607203894 ps
CPU time	54.02 seconds
Started	Mar 26 02:22:08 PM PDT 24
Finished	Mar 26 02:23:03 PM PDT 24
Peak memory	200024 kb
Host	smart-063316ac-1531-43b2-9bbb-155d043ec4ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685317120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2685317120
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.162547268
Short name	T657
Test name
Test status
Simulation time	67775322367 ps
CPU time	108.23 seconds
Started	Mar 26 02:29:54 PM PDT 24
Finished	Mar 26 02:31:42 PM PDT 24
Peak memory	199996 kb
Host	smart-e17a714b-0639-4bb9-92d9-ef7d661720b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162547268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.162547268
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.2107007962
Short name	T362
Test name
Test status
Simulation time	34691856645 ps
CPU time	84.94 seconds
Started	Mar 26 02:29:52 PM PDT 24
Finished	Mar 26 02:31:17 PM PDT 24
Peak memory	200036 kb
Host	smart-5076016e-7c4d-43d5-af28-4e65ad0ec2ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107007962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2107007962
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.3123047898
Short name	T232
Test name
Test status
Simulation time	114884940564 ps
CPU time	190.36 seconds
Started	Mar 26 02:29:55 PM PDT 24
Finished	Mar 26 02:33:05 PM PDT 24
Peak memory	200104 kb
Host	smart-9ecdc3c3-edf4-4e09-a940-8419bd395df7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123047898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3123047898
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.3692877303
Short name	T798
Test name
Test status
Simulation time	71956389979 ps
CPU time	135.97 seconds
Started	Mar 26 02:29:55 PM PDT 24
Finished	Mar 26 02:32:11 PM PDT 24
Peak memory	200108 kb
Host	smart-b8091f98-e217-4f8b-9e04-d2b1022527fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692877303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3692877303
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.596648704
Short name	T947
Test name
Test status
Simulation time	19815566303 ps
CPU time	43.66 seconds
Started	Mar 26 02:30:02 PM PDT 24
Finished	Mar 26 02:30:46 PM PDT 24
Peak memory	200100 kb
Host	smart-16c93463-0e05-4ad3-b1fd-23a15e9db7df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596648704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.596648704
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.3348246164
Short name	T892
Test name
Test status
Simulation time	82753893983 ps
CPU time	86.58 seconds
Started	Mar 26 02:30:03 PM PDT 24
Finished	Mar 26 02:31:30 PM PDT 24
Peak memory	199984 kb
Host	smart-d17ca346-3550-4177-99ca-59883bf72e8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348246164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3348246164
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.1585634261
Short name	T759
Test name
Test status
Simulation time	17497801601 ps
CPU time	31 seconds
Started	Mar 26 02:30:02 PM PDT 24
Finished	Mar 26 02:30:33 PM PDT 24
Peak memory	200128 kb
Host	smart-7cb2e02a-7c75-47d1-b27e-ac3bb8f56da8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585634261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1585634261
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.2027566714
Short name	T690
Test name
Test status
Simulation time	39856373407 ps
CPU time	55.31 seconds
Started	Mar 26 02:30:05 PM PDT 24
Finished	Mar 26 02:31:00 PM PDT 24
Peak memory	200108 kb
Host	smart-bc6507da-f6ea-4e25-af7f-7403c223edae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027566714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2027566714
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.2461617598
Short name	T228
Test name
Test status
Simulation time	38556416597 ps
CPU time	35.49 seconds
Started	Mar 26 02:30:03 PM PDT 24
Finished	Mar 26 02:30:39 PM PDT 24
Peak memory	199952 kb
Host	smart-84aee4e6-2162-44d4-9ae8-0920485dfed0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461617598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2461617598
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.126317159
Short name	T384
Test name
Test status
Simulation time	16472514 ps
CPU time	0.63 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:22:29 PM PDT 24
Peak memory	195512 kb
Host	smart-09c75605-c6d0-4c1d-b7f0-f65ffb7dd28e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126317159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.126317159
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.2898843791
Short name	T600
Test name
Test status
Simulation time	83926727792 ps
CPU time	74.76 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:23:33 PM PDT 24
Peak memory	200136 kb
Host	smart-00c5d462-0b42-4e23-affa-0b8c3653bc19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898843791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2898843791
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.2726647743
Short name	T277
Test name
Test status
Simulation time	101399987643 ps
CPU time	38.56 seconds
Started	Mar 26 02:22:23 PM PDT 24
Finished	Mar 26 02:23:02 PM PDT 24
Peak memory	200012 kb
Host	smart-64a00998-0561-4d24-b6ec-b87abe94206c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726647743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2726647743
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.2997397106
Short name	T368
Test name
Test status
Simulation time	40449886736 ps
CPU time	18.68 seconds
Started	Mar 26 02:22:17 PM PDT 24
Finished	Mar 26 02:22:36 PM PDT 24
Peak memory	200088 kb
Host	smart-2679eb91-9c7d-43e6-b619-ab0187b85b8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997397106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2997397106
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_intr.4257551140
Short name	T1001
Test name
Test status
Simulation time	33770921879 ps
CPU time	27.46 seconds
Started	Mar 26 02:22:23 PM PDT 24
Finished	Mar 26 02:22:51 PM PDT 24
Peak memory	199516 kb
Host	smart-5e3d4ac6-28ce-4f17-9aac-07bee505bfdd
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257551140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4257551140
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.4087013120
Short name	T403
Test name
Test status
Simulation time	162695119620 ps
CPU time	388 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:28:56 PM PDT 24
Peak memory	200080 kb
Host	smart-2624a905-378a-4a38-b9b3-676bec3bba81
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4087013120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4087013120
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/24.uart_loopback.1493986964
Short name	T1058
Test name
Test status
Simulation time	4258503030 ps
CPU time	2.88 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:22:31 PM PDT 24
Peak memory	198324 kb
Host	smart-77a10e1e-f94e-4e69-bd1f-e284ebd2487f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493986964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1493986964
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.3526226774
Short name	T777
Test name
Test status
Simulation time	187259610273 ps
CPU time	66.57 seconds
Started	Mar 26 02:22:17 PM PDT 24
Finished	Mar 26 02:23:24 PM PDT 24
Peak memory	200348 kb
Host	smart-e908543b-2416-4986-aae2-d2ce7a88bc39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526226774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3526226774
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.373938695
Short name	T340
Test name
Test status
Simulation time	12873732857 ps
CPU time	640.19 seconds
Started	Mar 26 02:22:27 PM PDT 24
Finished	Mar 26 02:33:07 PM PDT 24
Peak memory	200080 kb
Host	smart-7f284f15-2bcb-4dd0-afb3-e1ba4a1644aa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=373938695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.373938695
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.2123383984
Short name	T404
Test name
Test status
Simulation time	3367142385 ps
CPU time	11.07 seconds
Started	Mar 26 02:22:20 PM PDT 24
Finished	Mar 26 02:22:31 PM PDT 24
Peak memory	198948 kb
Host	smart-a5f9faa1-0d1c-41b5-8c92-893b51ed6b95
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2123383984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2123383984
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.2820775511
Short name	T206
Test name
Test status
Simulation time	13641065970 ps
CPU time	26.23 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:22:44 PM PDT 24
Peak memory	200088 kb
Host	smart-b0999c48-73cc-456e-8724-733a1ef28eda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820775511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2820775511
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.1686654748
Short name	T596
Test name
Test status
Simulation time	44204280235 ps
CPU time	15.3 seconds
Started	Mar 26 02:22:20 PM PDT 24
Finished	Mar 26 02:22:35 PM PDT 24
Peak memory	196196 kb
Host	smart-40ebb6d6-02ce-4b63-848c-1ea1cc0f659f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686654748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1686654748
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.2789761416
Short name	T723
Test name
Test status
Simulation time	653816860 ps
CPU time	2.84 seconds
Started	Mar 26 02:22:20 PM PDT 24
Finished	Mar 26 02:22:23 PM PDT 24
Peak memory	198340 kb
Host	smart-afad04cb-50c3-49c9-8568-41b5b745185c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789761416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2789761416
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all.3192125044
Short name	T950
Test name
Test status
Simulation time	254761927975 ps
CPU time	634.36 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:33:03 PM PDT 24
Peak memory	200136 kb
Host	smart-7c3364be-5cf8-4322-a20e-fe4f0cbb092e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192125044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3192125044
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/24.uart_stress_all_with_rand_reset.1163025880
Short name	T59
Test name
Test status
Simulation time	76259361666 ps
CPU time	509.4 seconds
Started	Mar 26 02:22:29 PM PDT 24
Finished	Mar 26 02:30:59 PM PDT 24
Peak memory	216580 kb
Host	smart-e0ae09ab-b971-427a-b625-5688c2bd1eae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163025880 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1163025880
Directory	/workspace/24.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.4214377084
Short name	T458
Test name
Test status
Simulation time	7985405407 ps
CPU time	15.61 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:22:34 PM PDT 24
Peak memory	199940 kb
Host	smart-79ea14d4-5f7f-4674-bb0c-7f472fc9fa23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214377084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4214377084
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.3884088294
Short name	T855
Test name
Test status
Simulation time	73527394153 ps
CPU time	107.83 seconds
Started	Mar 26 02:22:18 PM PDT 24
Finished	Mar 26 02:24:06 PM PDT 24
Peak memory	199912 kb
Host	smart-e24ff9d5-8360-4eab-a8f0-a225bd32ae46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884088294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3884088294
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.521945473
Short name	T209
Test name
Test status
Simulation time	194224436061 ps
CPU time	192.02 seconds
Started	Mar 26 02:30:04 PM PDT 24
Finished	Mar 26 02:33:16 PM PDT 24
Peak memory	199956 kb
Host	smart-6bfb94a6-bb32-4c16-9c8a-f45e91318ba3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=521945473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.521945473
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.2917573729
Short name	T890
Test name
Test status
Simulation time	118204005544 ps
CPU time	95.49 seconds
Started	Mar 26 02:30:02 PM PDT 24
Finished	Mar 26 02:31:38 PM PDT 24
Peak memory	199780 kb
Host	smart-1b6ddf09-556d-4031-98bf-e50c78499c7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917573729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2917573729
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.4275323260
Short name	T773
Test name
Test status
Simulation time	101344772735 ps
CPU time	56.33 seconds
Started	Mar 26 02:30:03 PM PDT 24
Finished	Mar 26 02:31:00 PM PDT 24
Peak memory	200060 kb
Host	smart-8ebd3c47-f93c-44bd-accc-61656707383e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275323260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4275323260
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.3604655557
Short name	T812
Test name
Test status
Simulation time	22678775906 ps
CPU time	26.87 seconds
Started	Mar 26 02:30:02 PM PDT 24
Finished	Mar 26 02:30:29 PM PDT 24
Peak memory	200108 kb
Host	smart-757fd346-50b0-49af-9f7b-80c8502820d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604655557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3604655557
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.1453894325
Short name	T143
Test name
Test status
Simulation time	24542169913 ps
CPU time	11.25 seconds
Started	Mar 26 02:30:02 PM PDT 24
Finished	Mar 26 02:30:14 PM PDT 24
Peak memory	200132 kb
Host	smart-16203675-d580-4037-b78c-a7ee016288c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453894325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1453894325
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.3995045895
Short name	T336
Test name
Test status
Simulation time	37511761532 ps
CPU time	58.45 seconds
Started	Mar 26 02:30:06 PM PDT 24
Finished	Mar 26 02:31:05 PM PDT 24
Peak memory	200124 kb
Host	smart-da7a23f8-4527-4d73-9bfe-27526976fa1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995045895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3995045895
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.587154843
Short name	T168
Test name
Test status
Simulation time	69723318669 ps
CPU time	50.32 seconds
Started	Mar 26 02:30:10 PM PDT 24
Finished	Mar 26 02:31:01 PM PDT 24
Peak memory	199996 kb
Host	smart-956b6095-ee17-402b-bb72-63a77303dfd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587154843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.587154843
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.2291781280
Short name	T162
Test name
Test status
Simulation time	74045584976 ps
CPU time	231.26 seconds
Started	Mar 26 02:30:16 PM PDT 24
Finished	Mar 26 02:34:08 PM PDT 24
Peak memory	200044 kb
Host	smart-29733611-230a-4e02-8be1-0a1e083b4a00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291781280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2291781280
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.472731024
Short name	T237
Test name
Test status
Simulation time	174939013235 ps
CPU time	260.62 seconds
Started	Mar 26 02:30:12 PM PDT 24
Finished	Mar 26 02:34:33 PM PDT 24
Peak memory	200240 kb
Host	smart-f1623357-a7e3-4094-a7a9-914cefa6a28b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472731024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.472731024
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.579831821
Short name	T737
Test name
Test status
Simulation time	156120905 ps
CPU time	0.57 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:22:40 PM PDT 24
Peak memory	195524 kb
Host	smart-daa0572b-f17e-4962-98a4-69f7e7cd2fa7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579831821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.579831821
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.3539336860
Short name	T541
Test name
Test status
Simulation time	91647329255 ps
CPU time	32.93 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:23:02 PM PDT 24
Peak memory	200080 kb
Host	smart-7e8c74f4-d92b-4d6d-879a-ae90e5694a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539336860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3539336860
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.636947600
Short name	T951
Test name
Test status
Simulation time	148784560812 ps
CPU time	244.55 seconds
Started	Mar 26 02:22:29 PM PDT 24
Finished	Mar 26 02:26:33 PM PDT 24
Peak memory	199984 kb
Host	smart-f3d1791a-d2d0-439f-8465-962f461dacc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636947600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.636947600
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.1646699982
Short name	T607
Test name
Test status
Simulation time	58925029894 ps
CPU time	102.62 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:24:11 PM PDT 24
Peak memory	199972 kb
Host	smart-e60f3c7e-6ef2-430e-8635-ce2140a52d0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646699982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1646699982
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_intr.1977960360
Short name	T755
Test name
Test status
Simulation time	27032602459 ps
CPU time	12.48 seconds
Started	Mar 26 02:22:32 PM PDT 24
Finished	Mar 26 02:22:44 PM PDT 24
Peak memory	200052 kb
Host	smart-b3782ff6-7304-471c-940d-2a0f4bce68e8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977960360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1977960360
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.3878610347
Short name	T407
Test name
Test status
Simulation time	187696559344 ps
CPU time	885.71 seconds
Started	Mar 26 02:22:37 PM PDT 24
Finished	Mar 26 02:37:23 PM PDT 24
Peak memory	200092 kb
Host	smart-45d4223b-d5a0-4746-be73-8601835294c4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3878610347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3878610347
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/25.uart_loopback.463039666
Short name	T386
Test name
Test status
Simulation time	2190031037 ps
CPU time	2.64 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:22:31 PM PDT 24
Peak memory	197276 kb
Host	smart-282180ac-87ee-45f2-97f9-4e12b164afe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463039666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.463039666
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.4015208952
Short name	T338
Test name
Test status
Simulation time	153010149291 ps
CPU time	210.8 seconds
Started	Mar 26 02:22:29 PM PDT 24
Finished	Mar 26 02:26:00 PM PDT 24
Peak memory	200244 kb
Host	smart-53077c26-6d22-460e-9528-c94fad4349a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015208952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.4015208952
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.1484307744
Short name	T348
Test name
Test status
Simulation time	10036599276 ps
CPU time	264.68 seconds
Started	Mar 26 02:22:38 PM PDT 24
Finished	Mar 26 02:27:03 PM PDT 24
Peak memory	199920 kb
Host	smart-c0ff719c-707d-486e-b79e-dac56590cf90
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1484307744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1484307744
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.1615263725
Short name	T1030
Test name
Test status
Simulation time	5992684018 ps
CPU time	55.55 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:23:24 PM PDT 24
Peak memory	199208 kb
Host	smart-b79eda98-b0ce-4518-bbe4-4ea22f3a911e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1615263725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1615263725
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.303105776
Short name	T519
Test name
Test status
Simulation time	121894331847 ps
CPU time	178.83 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:25:28 PM PDT 24
Peak memory	200020 kb
Host	smart-cd2d4d67-bef3-49a2-a49d-f5df92c8e2ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=303105776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.303105776
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_smoke.2926860499
Short name	T466
Test name
Test status
Simulation time	914837386 ps
CPU time	1.87 seconds
Started	Mar 26 02:22:31 PM PDT 24
Finished	Mar 26 02:22:33 PM PDT 24
Peak memory	198352 kb
Host	smart-aba4ef2d-dd6a-4f1d-8815-09bd0a9ec927
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926860499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2926860499
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_stress_all.3301845060
Short name	T395
Test name
Test status
Simulation time	51186506065 ps
CPU time	31.57 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:23:10 PM PDT 24
Peak memory	200068 kb
Host	smart-5c16bdd9-6ee1-4a5e-9962-d0f689ce3133
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301845060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3301845060
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.56647045
Short name	T549
Test name
Test status
Simulation time	7581619147 ps
CPU time	16.97 seconds
Started	Mar 26 02:22:27 PM PDT 24
Finished	Mar 26 02:22:44 PM PDT 24
Peak memory	199864 kb
Host	smart-a40c7a5f-696e-4e06-bf9d-1eca6fb6e063
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56647045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.56647045
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.931070809
Short name	T965
Test name
Test status
Simulation time	36740583595 ps
CPU time	23.4 seconds
Started	Mar 26 02:22:28 PM PDT 24
Finished	Mar 26 02:22:51 PM PDT 24
Peak memory	200112 kb
Host	smart-dbfaed5b-0d9a-4b3e-ac80-65d1b430d90e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931070809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.931070809
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.1206868099
Short name	T369
Test name
Test status
Simulation time	237758966183 ps
CPU time	151.36 seconds
Started	Mar 26 02:30:11 PM PDT 24
Finished	Mar 26 02:32:43 PM PDT 24
Peak memory	200108 kb
Host	smart-dc733a44-167e-4e40-9589-b00cecec8db6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206868099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1206868099
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.3044637774
Short name	T226
Test name
Test status
Simulation time	24842747953 ps
CPU time	61.03 seconds
Started	Mar 26 02:30:16 PM PDT 24
Finished	Mar 26 02:31:17 PM PDT 24
Peak memory	200024 kb
Host	smart-3fb1178b-c3b9-4547-925c-6530ef7d7445
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044637774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3044637774
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.2029560393
Short name	T193
Test name
Test status
Simulation time	31157602835 ps
CPU time	74.73 seconds
Started	Mar 26 02:30:16 PM PDT 24
Finished	Mar 26 02:31:32 PM PDT 24
Peak memory	200048 kb
Host	smart-f755f4e1-0195-4417-8490-79d166aa0d02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029560393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2029560393
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.3350388484
Short name	T610
Test name
Test status
Simulation time	96764267928 ps
CPU time	85.68 seconds
Started	Mar 26 02:30:10 PM PDT 24
Finished	Mar 26 02:31:36 PM PDT 24
Peak memory	200060 kb
Host	smart-1724a6e0-a637-4311-bf88-4543db20b30e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350388484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3350388484
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.1473376957
Short name	T282
Test name
Test status
Simulation time	20052331281 ps
CPU time	16.76 seconds
Started	Mar 26 02:30:19 PM PDT 24
Finished	Mar 26 02:30:36 PM PDT 24
Peak memory	199832 kb
Host	smart-92b1575e-ca84-4015-83fd-628bd6adae15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473376957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1473376957
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.3870320129
Short name	T1117
Test name
Test status
Simulation time	46143876309 ps
CPU time	78.7 seconds
Started	Mar 26 02:30:18 PM PDT 24
Finished	Mar 26 02:31:37 PM PDT 24
Peak memory	200016 kb
Host	smart-55442fd0-46f3-4f37-b01c-c6be3e886e0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3870320129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3870320129
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.1109999039
Short name	T626
Test name
Test status
Simulation time	88263249064 ps
CPU time	223.19 seconds
Started	Mar 26 02:30:19 PM PDT 24
Finished	Mar 26 02:34:02 PM PDT 24
Peak memory	200080 kb
Host	smart-b8fd4be7-467d-4896-af94-009eb9bb8246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109999039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1109999039
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.2006781819
Short name	T251
Test name
Test status
Simulation time	191862113807 ps
CPU time	391.86 seconds
Started	Mar 26 02:30:17 PM PDT 24
Finished	Mar 26 02:36:50 PM PDT 24
Peak memory	200040 kb
Host	smart-e2bd95e4-9dfb-4ee2-9617-dad1a0660162
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006781819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2006781819
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.3877209960
Short name	T634
Test name
Test status
Simulation time	50697667 ps
CPU time	0.56 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:22:51 PM PDT 24
Peak memory	195504 kb
Host	smart-4d7494c5-a5c1-4ec7-9dbd-40e09c433ec6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877209960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3877209960
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.47410668
Short name	T1022
Test name
Test status
Simulation time	45980158273 ps
CPU time	11.62 seconds
Started	Mar 26 02:22:37 PM PDT 24
Finished	Mar 26 02:22:49 PM PDT 24
Peak memory	199992 kb
Host	smart-47861558-82c1-48b7-b097-5b5413ff5939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47410668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.47410668
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.3899741686
Short name	T1013
Test name
Test status
Simulation time	204237833048 ps
CPU time	135.74 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:24:54 PM PDT 24
Peak memory	200068 kb
Host	smart-a917ca13-8df2-4f34-8a4c-31b638e1ef5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899741686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3899741686
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.3924388626
Short name	T825
Test name
Test status
Simulation time	86855750189 ps
CPU time	55.56 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:23:35 PM PDT 24
Peak memory	199996 kb
Host	smart-5ec78ba2-34f6-44e6-8687-72d681b8d4b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924388626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3924388626
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_intr.4278150859
Short name	T692
Test name
Test status
Simulation time	39576081806 ps
CPU time	31.19 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:23:11 PM PDT 24
Peak memory	200064 kb
Host	smart-3f0b6ce7-e952-4f20-86e0-7e763424af7f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278150859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4278150859
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.516509764
Short name	T495
Test name
Test status
Simulation time	87259570355 ps
CPU time	788.15 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:35:59 PM PDT 24
Peak memory	199992 kb
Host	smart-3a8a77de-d46e-4b6e-91dd-ca1da06a6db3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=516509764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.516509764
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.764892893
Short name	T453
Test name
Test status
Simulation time	9210775488 ps
CPU time	13.82 seconds
Started	Mar 26 02:22:38 PM PDT 24
Finished	Mar 26 02:22:52 PM PDT 24
Peak memory	200060 kb
Host	smart-50cb6601-6fa1-48f2-9007-c3181a1f1eab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764892893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.764892893
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_perf.4243351391
Short name	T893
Test name
Test status
Simulation time	14852435868 ps
CPU time	205.57 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:26:05 PM PDT 24
Peak memory	200076 kb
Host	smart-b4e709fc-7710-41d0-9039-ed43fa4ab577
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4243351391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4243351391
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.3898453621
Short name	T902
Test name
Test status
Simulation time	2229379358 ps
CPU time	15.45 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:22:55 PM PDT 24
Peak memory	198200 kb
Host	smart-7de1f4fa-5caa-4f10-8430-ec40fcd216f4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3898453621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3898453621
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.2461095887
Short name	T452
Test name
Test status
Simulation time	144643451888 ps
CPU time	216.58 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:26:16 PM PDT 24
Peak memory	200080 kb
Host	smart-ec68c982-5b97-4a94-9d1a-b53b952b2666
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461095887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2461095887
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.134989202
Short name	T1112
Test name
Test status
Simulation time	3275592555 ps
CPU time	1.56 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:22:41 PM PDT 24
Peak memory	196216 kb
Host	smart-41a9c330-4eca-45b6-b531-0bc11f935f80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134989202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.134989202
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.3933248605
Short name	T417
Test name
Test status
Simulation time	431216725 ps
CPU time	3.38 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:22:43 PM PDT 24
Peak memory	198384 kb
Host	smart-75b0373a-7051-438e-a9e7-803f4617210e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933248605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3933248605
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all.2420919018
Short name	T231
Test name
Test status
Simulation time	373837957068 ps
CPU time	523.94 seconds
Started	Mar 26 02:22:54 PM PDT 24
Finished	Mar 26 02:31:38 PM PDT 24
Peak memory	208560 kb
Host	smart-6aa15b1d-a054-4d4e-bef8-f2d4712bf4f1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420919018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2420919018
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.2413645004
Short name	T799
Test name
Test status
Simulation time	6194395108 ps
CPU time	28.52 seconds
Started	Mar 26 02:22:39 PM PDT 24
Finished	Mar 26 02:23:08 PM PDT 24
Peak memory	199280 kb
Host	smart-9eab9e32-8eb7-47be-81d9-6be90a025c03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413645004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2413645004
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.2245937809
Short name	T301
Test name
Test status
Simulation time	7996500065 ps
CPU time	15.08 seconds
Started	Mar 26 02:22:37 PM PDT 24
Finished	Mar 26 02:22:52 PM PDT 24
Peak memory	200060 kb
Host	smart-2f5aac1b-f52c-4a4b-995c-d06ec169654f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245937809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2245937809
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.1224887031
Short name	T116
Test name
Test status
Simulation time	38938114605 ps
CPU time	21.65 seconds
Started	Mar 26 02:30:19 PM PDT 24
Finished	Mar 26 02:30:41 PM PDT 24
Peak memory	200108 kb
Host	smart-2b55bec1-6614-4a34-94f1-f240de19253f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224887031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1224887031
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.4291615036
Short name	T619
Test name
Test status
Simulation time	127433856729 ps
CPU time	42.26 seconds
Started	Mar 26 02:30:20 PM PDT 24
Finished	Mar 26 02:31:02 PM PDT 24
Peak memory	200020 kb
Host	smart-a8107e77-bd53-420d-94d0-25224b70470a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291615036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4291615036
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.2544165749
Short name	T121
Test name
Test status
Simulation time	12690291280 ps
CPU time	11.4 seconds
Started	Mar 26 02:30:19 PM PDT 24
Finished	Mar 26 02:30:30 PM PDT 24
Peak memory	200060 kb
Host	smart-f50b137e-e7d0-4b2d-baf7-fe99ce06c52a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544165749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2544165749
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/263.uart_fifo_reset.2061636098
Short name	T49
Test name
Test status
Simulation time	48532545877 ps
CPU time	21.06 seconds
Started	Mar 26 02:30:20 PM PDT 24
Finished	Mar 26 02:30:41 PM PDT 24
Peak memory	200128 kb
Host	smart-aa14369b-8725-4db7-9856-5f3b605454ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061636098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2061636098
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.3233622948
Short name	T12
Test name
Test status
Simulation time	18685505787 ps
CPU time	16.52 seconds
Started	Mar 26 02:30:18 PM PDT 24
Finished	Mar 26 02:30:35 PM PDT 24
Peak memory	200120 kb
Host	smart-7232699a-d923-4cff-b98f-e38546e4399f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233622948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3233622948
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.1232756454
Short name	T84
Test name
Test status
Simulation time	52920631804 ps
CPU time	29.12 seconds
Started	Mar 26 02:30:19 PM PDT 24
Finished	Mar 26 02:30:48 PM PDT 24
Peak memory	200084 kb
Host	smart-052a3a4d-52b3-4bb7-a928-2e731676f32a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232756454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1232756454
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.1537384642
Short name	T266
Test name
Test status
Simulation time	19460646223 ps
CPU time	38.81 seconds
Started	Mar 26 02:30:19 PM PDT 24
Finished	Mar 26 02:30:58 PM PDT 24
Peak memory	199976 kb
Host	smart-7924dab3-838b-4963-8007-13b3e06dd966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537384642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1537384642
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.3541785756
Short name	T591
Test name
Test status
Simulation time	184781076416 ps
CPU time	50.22 seconds
Started	Mar 26 02:30:18 PM PDT 24
Finished	Mar 26 02:31:09 PM PDT 24
Peak memory	200016 kb
Host	smart-190a4532-0081-488a-b5f1-b0bc01a1dbb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541785756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3541785756
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.1387197669
Short name	T569
Test name
Test status
Simulation time	41343864153 ps
CPU time	15.56 seconds
Started	Mar 26 02:30:18 PM PDT 24
Finished	Mar 26 02:30:34 PM PDT 24
Peak memory	200056 kb
Host	smart-6777ff09-c895-46d4-9c99-435998516df1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387197669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1387197669
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.1855714146
Short name	T585
Test name
Test status
Simulation time	49070594174 ps
CPU time	103.65 seconds
Started	Mar 26 02:30:18 PM PDT 24
Finished	Mar 26 02:32:02 PM PDT 24
Peak memory	200128 kb
Host	smart-4898ed0d-b0a1-4759-b4da-d14462f2254c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1855714146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1855714146
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.3414052561
Short name	T385
Test name
Test status
Simulation time	102068643 ps
CPU time	0.56 seconds
Started	Mar 26 02:23:01 PM PDT 24
Finished	Mar 26 02:23:02 PM PDT 24
Peak memory	195540 kb
Host	smart-4b37a1f9-3532-45ad-bfda-396216c90fad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414052561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3414052561
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.52285131
Short name	T201
Test name
Test status
Simulation time	60844390174 ps
CPU time	95.46 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:24:27 PM PDT 24
Peak memory	200032 kb
Host	smart-000c63ea-c18a-4719-9b61-3d074e3cb107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52285131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.52285131
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.3699158199
Short name	T683
Test name
Test status
Simulation time	222464283352 ps
CPU time	1235.73 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:43:27 PM PDT 24
Peak memory	200056 kb
Host	smart-f0c8056e-5318-402c-ab61-7b8aa84bd2d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699158199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3699158199
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_intr.2908736582
Short name	T432
Test name
Test status
Simulation time	20631918106 ps
CPU time	23 seconds
Started	Mar 26 02:22:52 PM PDT 24
Finished	Mar 26 02:23:15 PM PDT 24
Peak memory	200180 kb
Host	smart-4c7c7508-d290-44b7-9191-d596aa229e2e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908736582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2908736582
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.406904505
Short name	T830
Test name
Test status
Simulation time	43660403120 ps
CPU time	40.69 seconds
Started	Mar 26 02:22:52 PM PDT 24
Finished	Mar 26 02:23:33 PM PDT 24
Peak memory	200036 kb
Host	smart-fb1f2de3-7676-4896-b4c5-074713b1ba36
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=406904505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.406904505
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.1319852469
Short name	T594
Test name
Test status
Simulation time	607914002 ps
CPU time	1.63 seconds
Started	Mar 26 02:22:54 PM PDT 24
Finished	Mar 26 02:22:56 PM PDT 24
Peak memory	197460 kb
Host	smart-35548f08-2675-46e3-a229-0bbbadac038e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319852469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1319852469
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.4196451098
Short name	T309
Test name
Test status
Simulation time	162766254304 ps
CPU time	102.87 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:24:34 PM PDT 24
Peak memory	208420 kb
Host	smart-9afb1914-8a7c-403c-b635-60a5eceeb0bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196451098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.4196451098
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.2874654327
Short name	T294
Test name
Test status
Simulation time	12572536944 ps
CPU time	171.22 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:25:42 PM PDT 24
Peak memory	200124 kb
Host	smart-485ff8d8-7c66-4b44-8fb2-ae101410021b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2874654327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2874654327
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.669353980
Short name	T387
Test name
Test status
Simulation time	5865885912 ps
CPU time	50.25 seconds
Started	Mar 26 02:22:52 PM PDT 24
Finished	Mar 26 02:23:43 PM PDT 24
Peak memory	199136 kb
Host	smart-7c018d43-313b-4a27-80a4-670e42001c2f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=669353980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.669353980
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.2572614570
Short name	T493
Test name
Test status
Simulation time	116559435117 ps
CPU time	44.45 seconds
Started	Mar 26 02:22:50 PM PDT 24
Finished	Mar 26 02:23:35 PM PDT 24
Peak memory	200032 kb
Host	smart-85075f6e-213d-448c-9248-1e8df7685b9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572614570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2572614570
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.2758209273
Short name	T962
Test name
Test status
Simulation time	3757411404 ps
CPU time	2.37 seconds
Started	Mar 26 02:22:54 PM PDT 24
Finished	Mar 26 02:22:56 PM PDT 24
Peak memory	196436 kb
Host	smart-bc3ffad0-2591-4b19-a51c-75f763e5d564
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758209273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2758209273
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.747775651
Short name	T496
Test name
Test status
Simulation time	859110453 ps
CPU time	3.21 seconds
Started	Mar 26 02:22:52 PM PDT 24
Finished	Mar 26 02:22:55 PM PDT 24
Peak memory	198880 kb
Host	smart-714d2f7c-4a75-476d-a97f-d70216468bdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747775651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.747775651
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all_with_rand_reset.3479061086
Short name	T859
Test name
Test status
Simulation time	56709911435 ps
CPU time	214.47 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:26:25 PM PDT 24
Peak memory	216768 kb
Host	smart-b5342ce0-bd9f-4c1c-8c2b-59ae88a8c453
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479061086 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3479061086
Directory	/workspace/27.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.2913094721
Short name	T414
Test name
Test status
Simulation time	3038426751 ps
CPU time	1.49 seconds
Started	Mar 26 02:22:51 PM PDT 24
Finished	Mar 26 02:22:52 PM PDT 24
Peak memory	200084 kb
Host	smart-198c3204-d295-42de-b7cd-3cc0131e637e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913094721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2913094721
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.3544892445
Short name	T720
Test name
Test status
Simulation time	64807705542 ps
CPU time	174.56 seconds
Started	Mar 26 02:22:52 PM PDT 24
Finished	Mar 26 02:25:46 PM PDT 24
Peak memory	199968 kb
Host	smart-b6592647-88a2-42ff-a98b-3ddaa0b5b62f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544892445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3544892445
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.109274676
Short name	T267
Test name
Test status
Simulation time	72946770579 ps
CPU time	114.17 seconds
Started	Mar 26 02:30:29 PM PDT 24
Finished	Mar 26 02:32:23 PM PDT 24
Peak memory	200148 kb
Host	smart-93818c2a-078f-427b-96d0-927b3a803afc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109274676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.109274676
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.1813891724
Short name	T835
Test name
Test status
Simulation time	123430396887 ps
CPU time	127.14 seconds
Started	Mar 26 02:30:29 PM PDT 24
Finished	Mar 26 02:32:36 PM PDT 24
Peak memory	200056 kb
Host	smart-c517badf-6c3d-435d-bc12-b8163f8b712c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813891724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1813891724
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.3449221170
Short name	T551
Test name
Test status
Simulation time	59660773470 ps
CPU time	33.64 seconds
Started	Mar 26 02:30:29 PM PDT 24
Finished	Mar 26 02:31:03 PM PDT 24
Peak memory	200132 kb
Host	smart-88e880ef-0d9c-4fae-8871-2b7d9c408245
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449221170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3449221170
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.2413556513
Short name	T343
Test name
Test status
Simulation time	107537486532 ps
CPU time	47.83 seconds
Started	Mar 26 02:30:27 PM PDT 24
Finished	Mar 26 02:31:15 PM PDT 24
Peak memory	200100 kb
Host	smart-7891e895-1550-4b19-bc2f-92738cbed9cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413556513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2413556513
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/274.uart_fifo_reset.3198045568
Short name	T172
Test name
Test status
Simulation time	98773801920 ps
CPU time	149.02 seconds
Started	Mar 26 02:30:27 PM PDT 24
Finished	Mar 26 02:32:57 PM PDT 24
Peak memory	200120 kb
Host	smart-65dfbfa4-ebdd-44b1-b89f-b46203d60bbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198045568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3198045568
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.2484584743
Short name	T501
Test name
Test status
Simulation time	68167473948 ps
CPU time	156.82 seconds
Started	Mar 26 02:30:27 PM PDT 24
Finished	Mar 26 02:33:04 PM PDT 24
Peak memory	200064 kb
Host	smart-08b7fafa-752e-4303-b017-f00a87b900d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484584743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2484584743
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.1438415433
Short name	T302
Test name
Test status
Simulation time	78998549977 ps
CPU time	104.34 seconds
Started	Mar 26 02:30:26 PM PDT 24
Finished	Mar 26 02:32:11 PM PDT 24
Peak memory	200024 kb
Host	smart-0157aa2c-8003-424d-97c0-a8b61509871c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438415433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1438415433
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.1762071136
Short name	T921
Test name
Test status
Simulation time	25037950083 ps
CPU time	45.63 seconds
Started	Mar 26 02:30:28 PM PDT 24
Finished	Mar 26 02:31:14 PM PDT 24
Peak memory	200044 kb
Host	smart-61745be1-d1af-4f5e-a7eb-88186800e8d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762071136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1762071136
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.4078941729
Short name	T568
Test name
Test status
Simulation time	57206332082 ps
CPU time	15.48 seconds
Started	Mar 26 02:30:26 PM PDT 24
Finished	Mar 26 02:30:42 PM PDT 24
Peak memory	200028 kb
Host	smart-6aaf1145-42b3-43f8-ab8f-fb66b309955b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078941729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4078941729
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.3498520295
Short name	T255
Test name
Test status
Simulation time	8061617927 ps
CPU time	14.56 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:30:51 PM PDT 24
Peak memory	199988 kb
Host	smart-d98e935b-d688-4cb4-b55e-f70193446bb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498520295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3498520295
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.2086944057
Short name	T525
Test name
Test status
Simulation time	24463747 ps
CPU time	0.59 seconds
Started	Mar 26 02:23:15 PM PDT 24
Finished	Mar 26 02:23:16 PM PDT 24
Peak memory	195456 kb
Host	smart-73badd64-b0c4-4e75-9fc4-11ec3b2db44f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086944057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2086944057
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.2310297840
Short name	T191
Test name
Test status
Simulation time	114747596083 ps
CPU time	47.24 seconds
Started	Mar 26 02:23:01 PM PDT 24
Finished	Mar 26 02:23:49 PM PDT 24
Peak memory	200100 kb
Host	smart-8c6c936f-802b-43d7-a35a-1e3580c265b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310297840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2310297840
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.3438129988
Short name	T964
Test name
Test status
Simulation time	21803816398 ps
CPU time	9.01 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:23:11 PM PDT 24
Peak memory	199880 kb
Host	smart-fcd083f8-4a1d-4840-b665-9ff2ee18b6db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438129988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3438129988
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.2117633330
Short name	T677
Test name
Test status
Simulation time	75449377817 ps
CPU time	148.4 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:25:31 PM PDT 24
Peak memory	200060 kb
Host	smart-5faa3369-5a38-4e3c-89d0-79f149c96609
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117633330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2117633330
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.3046411407
Short name	T276
Test name
Test status
Simulation time	41216938702 ps
CPU time	63.47 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:24:06 PM PDT 24
Peak memory	200052 kb
Host	smart-40212ae6-1e6a-45e2-8efd-c48c5725d643
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046411407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3046411407
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.1893268162
Short name	T283
Test name
Test status
Simulation time	93193632266 ps
CPU time	688.36 seconds
Started	Mar 26 02:23:03 PM PDT 24
Finished	Mar 26 02:34:32 PM PDT 24
Peak memory	200104 kb
Host	smart-97ec3f50-013d-418c-8dd6-2ea3ec3534f1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1893268162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1893268162
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.2471283037
Short name	T64
Test name
Test status
Simulation time	2506858251 ps
CPU time	2.68 seconds
Started	Mar 26 02:23:03 PM PDT 24
Finished	Mar 26 02:23:06 PM PDT 24
Peak memory	196608 kb
Host	smart-b72647ce-2c96-434a-80d9-b81207c63fa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471283037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2471283037
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.1545130738
Short name	T694
Test name
Test status
Simulation time	110958030629 ps
CPU time	183.95 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:26:06 PM PDT 24
Peak memory	200260 kb
Host	smart-0c69bcf5-200d-4b3c-97e7-a70a7a89fb43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545130738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1545130738
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.1477224488
Short name	T311
Test name
Test status
Simulation time	18663897027 ps
CPU time	950.32 seconds
Started	Mar 26 02:23:03 PM PDT 24
Finished	Mar 26 02:38:54 PM PDT 24
Peak memory	199956 kb
Host	smart-2a3c7ae6-5c91-4829-a4f9-6a72888d7980
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1477224488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1477224488
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.353042845
Short name	T948
Test name
Test status
Simulation time	1713064364 ps
CPU time	2.85 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:23:05 PM PDT 24
Peak memory	199316 kb
Host	smart-f73d21bd-227e-4de5-a900-fba752fb935f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=353042845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.353042845
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.3033296939
Short name	T802
Test name
Test status
Simulation time	53241215884 ps
CPU time	51.96 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:23:54 PM PDT 24
Peak memory	200028 kb
Host	smart-96ca6194-aa0f-4d95-9d9e-282042645474
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033296939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3033296939
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.2859657703
Short name	T1085
Test name
Test status
Simulation time	1502935727 ps
CPU time	1.8 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:23:04 PM PDT 24
Peak memory	195580 kb
Host	smart-8ca158d3-5170-46e9-8af5-412ada95f337
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859657703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2859657703
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.2788623473
Short name	T973
Test name
Test status
Simulation time	751074830 ps
CPU time	1.9 seconds
Started	Mar 26 02:23:01 PM PDT 24
Finished	Mar 26 02:23:03 PM PDT 24
Peak memory	199488 kb
Host	smart-7cff905b-dc68-4688-8da2-018a7f5baa3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788623473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2788623473
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_stress_all.2599586706
Short name	T644
Test name
Test status
Simulation time	296666304467 ps
CPU time	816.16 seconds
Started	Mar 26 02:23:02 PM PDT 24
Finished	Mar 26 02:36:39 PM PDT 24
Peak memory	200124 kb
Host	smart-d3f9f1c7-5414-49a4-b19b-a54dd0bec8c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599586706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2599586706
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.629702291
Short name	T1
Test name
Test status
Simulation time	946201130 ps
CPU time	2.8 seconds
Started	Mar 26 02:23:01 PM PDT 24
Finished	Mar 26 02:23:04 PM PDT 24
Peak memory	198616 kb
Host	smart-38c698c7-0f37-49eb-b3b3-5832be5e9d77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629702291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.629702291
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.3823989456
Short name	T545
Test name
Test status
Simulation time	79221357172 ps
CPU time	38.72 seconds
Started	Mar 26 02:23:01 PM PDT 24
Finished	Mar 26 02:23:40 PM PDT 24
Peak memory	200064 kb
Host	smart-191abff8-347f-4281-9253-1c0b29f99839
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823989456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3823989456
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.642938719
Short name	T733
Test name
Test status
Simulation time	11678982791 ps
CPU time	21.31 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:30:57 PM PDT 24
Peak memory	200080 kb
Host	smart-a243dfcb-f4e1-487d-8cc8-100213c03580
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642938719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.642938719
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.2579255482
Short name	T986
Test name
Test status
Simulation time	73265059639 ps
CPU time	26.19 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:31:02 PM PDT 24
Peak memory	199836 kb
Host	smart-40d23f9d-193b-43b9-b36b-908fc98594e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579255482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2579255482
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.1886044237
Short name	T932
Test name
Test status
Simulation time	104172229331 ps
CPU time	88.11 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:32:04 PM PDT 24
Peak memory	200044 kb
Host	smart-4103d0c9-d20d-4277-abbe-891c233065da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886044237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1886044237
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.851765435
Short name	T766
Test name
Test status
Simulation time	170538626763 ps
CPU time	25.69 seconds
Started	Mar 26 02:30:38 PM PDT 24
Finished	Mar 26 02:31:04 PM PDT 24
Peak memory	200088 kb
Host	smart-99fa9864-52b9-4fc0-9393-4bf2b9f1173c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851765435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.851765435
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.3571084157
Short name	T662
Test name
Test status
Simulation time	134544295463 ps
CPU time	32.28 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:31:09 PM PDT 24
Peak memory	200028 kb
Host	smart-d0555634-abc9-4264-b807-120b3d512ae2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3571084157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3571084157
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.1129759154
Short name	T838
Test name
Test status
Simulation time	37869885791 ps
CPU time	35.49 seconds
Started	Mar 26 02:30:35 PM PDT 24
Finished	Mar 26 02:31:11 PM PDT 24
Peak memory	200040 kb
Host	smart-facae545-b119-416d-89cc-8f9e7c6e31a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129759154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1129759154
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.1046721043
Short name	T427
Test name
Test status
Simulation time	148932887849 ps
CPU time	65.39 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:31:41 PM PDT 24
Peak memory	200172 kb
Host	smart-e1fca0b3-85f0-4ac1-9996-347ddc44ffaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046721043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1046721043
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.3642595809
Short name	T922
Test name
Test status
Simulation time	77333479882 ps
CPU time	33.26 seconds
Started	Mar 26 02:30:35 PM PDT 24
Finished	Mar 26 02:31:09 PM PDT 24
Peak memory	200024 kb
Host	smart-ac49792e-4829-41f3-9dc6-e891470fed0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642595809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3642595809
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.3149197833
Short name	T1007
Test name
Test status
Simulation time	107273290608 ps
CPU time	164.34 seconds
Started	Mar 26 02:30:36 PM PDT 24
Finished	Mar 26 02:33:21 PM PDT 24
Peak memory	200092 kb
Host	smart-aa142c0e-c664-4340-ac71-a2c0111e95d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149197833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3149197833
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.933374669
Short name	T909
Test name
Test status
Simulation time	67213738 ps
CPU time	0.58 seconds
Started	Mar 26 02:23:13 PM PDT 24
Finished	Mar 26 02:23:14 PM PDT 24
Peak memory	195516 kb
Host	smart-cef85fac-5417-4e9e-86b3-f5d2a4aea7b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933374669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.933374669
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.2925940742
Short name	T488
Test name
Test status
Simulation time	82350609422 ps
CPU time	36.67 seconds
Started	Mar 26 02:23:12 PM PDT 24
Finished	Mar 26 02:23:49 PM PDT 24
Peak memory	200112 kb
Host	smart-ad8d7e88-050a-4730-a9e5-e61dc42a3fed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925940742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2925940742
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.2194267760
Short name	T689
Test name
Test status
Simulation time	199125962466 ps
CPU time	54.3 seconds
Started	Mar 26 02:23:14 PM PDT 24
Finished	Mar 26 02:24:08 PM PDT 24
Peak memory	200100 kb
Host	smart-6ae5edae-237f-4b14-b599-89ff623b3fd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194267760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2194267760
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.1300282172
Short name	T866
Test name
Test status
Simulation time	32810161726 ps
CPU time	13.08 seconds
Started	Mar 26 02:23:12 PM PDT 24
Finished	Mar 26 02:23:25 PM PDT 24
Peak memory	200020 kb
Host	smart-45b7b3fb-a09c-464d-ab24-20195aa15ecc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300282172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1300282172
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_intr.149909057
Short name	T1012
Test name
Test status
Simulation time	38449831513 ps
CPU time	59.53 seconds
Started	Mar 26 02:23:16 PM PDT 24
Finished	Mar 26 02:24:15 PM PDT 24
Peak memory	200092 kb
Host	smart-780dce7d-0313-4f1e-8333-d4bb67af6b97
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149909057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.149909057
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_loopback.2411968342
Short name	T26
Test name
Test status
Simulation time	5051392740 ps
CPU time	20.19 seconds
Started	Mar 26 02:23:18 PM PDT 24
Finished	Mar 26 02:23:38 PM PDT 24
Peak memory	199556 kb
Host	smart-f7749fad-79de-473a-9e71-bf3d5445f787
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411968342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2411968342
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.3906558233
Short name	T83
Test name
Test status
Simulation time	342944137217 ps
CPU time	73.15 seconds
Started	Mar 26 02:23:14 PM PDT 24
Finished	Mar 26 02:24:27 PM PDT 24
Peak memory	199724 kb
Host	smart-16fb0155-31f3-4d01-90fd-5ff0b656ed2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906558233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3906558233
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.1548090558
Short name	T992
Test name
Test status
Simulation time	25943784802 ps
CPU time	659.61 seconds
Started	Mar 26 02:23:17 PM PDT 24
Finished	Mar 26 02:34:18 PM PDT 24
Peak memory	200020 kb
Host	smart-8fb10571-b55b-4a93-8cdb-ccb6f91e5a7d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1548090558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1548090558
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.59606887
Short name	T1093
Test name
Test status
Simulation time	3669464860 ps
CPU time	25.18 seconds
Started	Mar 26 02:23:13 PM PDT 24
Finished	Mar 26 02:23:38 PM PDT 24
Peak memory	198892 kb
Host	smart-d8651cff-a0c1-483d-9078-6e5938b4e5a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=59606887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.59606887
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.4140043195
Short name	T761
Test name
Test status
Simulation time	25149941543 ps
CPU time	52.68 seconds
Started	Mar 26 02:23:13 PM PDT 24
Finished	Mar 26 02:24:05 PM PDT 24
Peak memory	200008 kb
Host	smart-56381379-00b9-43bb-a548-5e39e650f5e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140043195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4140043195
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.3429169060
Short name	T1048
Test name
Test status
Simulation time	41995582669 ps
CPU time	70.48 seconds
Started	Mar 26 02:23:13 PM PDT 24
Finished	Mar 26 02:24:24 PM PDT 24
Peak memory	196144 kb
Host	smart-4a8b003e-116e-46c0-b13d-4ba365c87f3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429169060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3429169060
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.3349373045
Short name	T602
Test name
Test status
Simulation time	713805446 ps
CPU time	1.63 seconds
Started	Mar 26 02:23:15 PM PDT 24
Finished	Mar 26 02:23:17 PM PDT 24
Peak memory	198304 kb
Host	smart-aa57ade7-5527-41cc-bffe-91faa1b0c9bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3349373045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3349373045
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.1764685095
Short name	T1059
Test name
Test status
Simulation time	308420219068 ps
CPU time	99.83 seconds
Started	Mar 26 02:23:17 PM PDT 24
Finished	Mar 26 02:24:58 PM PDT 24
Peak memory	200036 kb
Host	smart-5dc04e8b-aec8-45a5-a38c-40041b4b15bc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764685095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1764685095
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_stress_all_with_rand_reset.3697356658
Short name	T62
Test name
Test status
Simulation time	954550118512 ps
CPU time	541.66 seconds
Started	Mar 26 02:23:13 PM PDT 24
Finished	Mar 26 02:32:15 PM PDT 24
Peak memory	216544 kb
Host	smart-2f0af9cc-dd8a-4a2b-9117-d022d759bcb4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697356658 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3697356658
Directory	/workspace/29.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.1414675764
Short name	T907
Test name
Test status
Simulation time	743689913 ps
CPU time	4.02 seconds
Started	Mar 26 02:23:13 PM PDT 24
Finished	Mar 26 02:23:17 PM PDT 24
Peak memory	199100 kb
Host	smart-c422a3f3-2504-4ec9-b1bc-3d0bf033f41a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414675764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1414675764
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.1433961711
Short name	T823
Test name
Test status
Simulation time	16969623143 ps
CPU time	8.24 seconds
Started	Mar 26 02:23:14 PM PDT 24
Finished	Mar 26 02:23:23 PM PDT 24
Peak memory	197856 kb
Host	smart-b709915b-0fcd-4089-a4e9-5df6ef467fdb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433961711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1433961711
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.4089725876
Short name	T615
Test name
Test status
Simulation time	102304490498 ps
CPU time	86.53 seconds
Started	Mar 26 02:30:37 PM PDT 24
Finished	Mar 26 02:32:04 PM PDT 24
Peak memory	200040 kb
Host	smart-5c757776-4968-425f-92ee-f2418fe65d00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089725876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.4089725876
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.1554657366
Short name	T254
Test name
Test status
Simulation time	71421307064 ps
CPU time	20.61 seconds
Started	Mar 26 02:30:39 PM PDT 24
Finished	Mar 26 02:31:00 PM PDT 24
Peak memory	200088 kb
Host	smart-4946de0b-b9f8-429f-8ecc-088e478f487a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554657366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1554657366
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.1932658185
Short name	T647
Test name
Test status
Simulation time	36362416116 ps
CPU time	58.61 seconds
Started	Mar 26 02:30:35 PM PDT 24
Finished	Mar 26 02:31:34 PM PDT 24
Peak memory	200068 kb
Host	smart-556fcd75-6fc3-4f59-b035-493ed51190d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932658185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1932658185
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.1917208873
Short name	T911
Test name
Test status
Simulation time	183583449549 ps
CPU time	61.91 seconds
Started	Mar 26 02:30:44 PM PDT 24
Finished	Mar 26 02:31:46 PM PDT 24
Peak memory	200076 kb
Host	smart-751dedae-2356-4d3d-8099-a2938c51288d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917208873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1917208873
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.2984536296
Short name	T1018
Test name
Test status
Simulation time	241236914149 ps
CPU time	115.96 seconds
Started	Mar 26 02:30:43 PM PDT 24
Finished	Mar 26 02:32:39 PM PDT 24
Peak memory	200104 kb
Host	smart-0d504420-868e-4dd1-ac0a-a2ce17f5b29d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984536296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2984536296
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.2771403512
Short name	T1094
Test name
Test status
Simulation time	43795592840 ps
CPU time	39.21 seconds
Started	Mar 26 02:30:44 PM PDT 24
Finished	Mar 26 02:31:23 PM PDT 24
Peak memory	200032 kb
Host	smart-ebcae9a9-5cd5-4f85-9e07-61a2148ad52b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771403512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2771403512
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.1279033316
Short name	T424
Test name
Test status
Simulation time	63954196961 ps
CPU time	105.09 seconds
Started	Mar 26 02:30:45 PM PDT 24
Finished	Mar 26 02:32:31 PM PDT 24
Peak memory	200092 kb
Host	smart-d49f0130-51ec-4500-b3ea-5ad3785cbfc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279033316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1279033316
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.3571506895
Short name	T956
Test name
Test status
Simulation time	34990620992 ps
CPU time	15.93 seconds
Started	Mar 26 02:30:44 PM PDT 24
Finished	Mar 26 02:31:00 PM PDT 24
Peak memory	200036 kb
Host	smart-4e56465b-9e16-4d9c-b642-f18ca38a6af0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3571506895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3571506895
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.2332621252
Short name	T280
Test name
Test status
Simulation time	196690110226 ps
CPU time	407.34 seconds
Started	Mar 26 02:30:45 PM PDT 24
Finished	Mar 26 02:37:32 PM PDT 24
Peak memory	200104 kb
Host	smart-e74493a8-7e30-4db7-9421-fe598bd95887
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332621252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2332621252
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.465617983
Short name	T516
Test name
Test status
Simulation time	21570720 ps
CPU time	0.57 seconds
Started	Mar 26 02:19:45 PM PDT 24
Finished	Mar 26 02:19:46 PM PDT 24
Peak memory	195024 kb
Host	smart-d01c7ec5-291b-424d-bb6f-6c755a124096
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465617983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.465617983
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.2178251646
Short name	T120
Test name
Test status
Simulation time	49791684734 ps
CPU time	39.58 seconds
Started	Mar 26 02:19:45 PM PDT 24
Finished	Mar 26 02:20:25 PM PDT 24
Peak memory	200048 kb
Host	smart-beb4af3e-a04f-45c5-bc44-b20361ede8a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2178251646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2178251646
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.2363693594
Short name	T747
Test name
Test status
Simulation time	43481095816 ps
CPU time	34.99 seconds
Started	Mar 26 02:19:42 PM PDT 24
Finished	Mar 26 02:20:17 PM PDT 24
Peak memory	200096 kb
Host	smart-03306806-ea3b-41b2-9f00-ef5826fe2eb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363693594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2363693594
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/3.uart_intr.4075418422
Short name	T559
Test name
Test status
Simulation time	29300870958 ps
CPU time	51.33 seconds
Started	Mar 26 02:19:43 PM PDT 24
Finished	Mar 26 02:20:34 PM PDT 24
Peak memory	200000 kb
Host	smart-ed58f259-c748-4359-840f-a350be9b3d46
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075418422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4075418422
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.252488880
Short name	T739
Test name
Test status
Simulation time	100140438479 ps
CPU time	301.01 seconds
Started	Mar 26 02:19:43 PM PDT 24
Finished	Mar 26 02:24:44 PM PDT 24
Peak memory	200092 kb
Host	smart-24e47c6f-af10-4a06-b6f9-aedafaf964ab
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=252488880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.252488880
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.1881238268
Short name	T25
Test name
Test status
Simulation time	1721235458 ps
CPU time	3.57 seconds
Started	Mar 26 02:19:43 PM PDT 24
Finished	Mar 26 02:19:46 PM PDT 24
Peak memory	197096 kb
Host	smart-72af8a13-3887-4aff-af45-240aaef5b073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881238268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1881238268
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.2867663524
Short name	T494
Test name
Test status
Simulation time	295845794185 ps
CPU time	136.8 seconds
Started	Mar 26 02:19:41 PM PDT 24
Finished	Mar 26 02:21:58 PM PDT 24
Peak memory	200128 kb
Host	smart-78c8dfcb-c745-4fa2-ba89-7d01764a1453
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867663524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2867663524
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.1840997754
Short name	T445
Test name
Test status
Simulation time	25886567917 ps
CPU time	390.18 seconds
Started	Mar 26 02:19:42 PM PDT 24
Finished	Mar 26 02:26:12 PM PDT 24
Peak memory	199940 kb
Host	smart-c3bc2c37-4ddd-4886-9176-01f9f9bafbca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1840997754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1840997754
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.1869213
Short name	T448
Test name
Test status
Simulation time	6612454289 ps
CPU time	28.2 seconds
Started	Mar 26 02:19:43 PM PDT 24
Finished	Mar 26 02:20:11 PM PDT 24
Peak memory	198948 kb
Host	smart-1575f79a-64c4-48e0-97f2-f512a8f18689
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1869213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1869213
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.1668466559
Short name	T872
Test name
Test status
Simulation time	139458252320 ps
CPU time	410.41 seconds
Started	Mar 26 02:19:45 PM PDT 24
Finished	Mar 26 02:26:35 PM PDT 24
Peak memory	200140 kb
Host	smart-7e82fb5e-12ab-4788-9ff0-a60028d8883b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668466559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1668466559
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.36261119
Short name	T832
Test name
Test status
Simulation time	44730367540 ps
CPU time	10.57 seconds
Started	Mar 26 02:19:42 PM PDT 24
Finished	Mar 26 02:19:53 PM PDT 24
Peak memory	195856 kb
Host	smart-3b11af72-8d36-4a15-92f3-6d79e0d7b72a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36261119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.36261119
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_smoke.1569817498
Short name	T564
Test name
Test status
Simulation time	662911492 ps
CPU time	1.61 seconds
Started	Mar 26 02:19:42 PM PDT 24
Finished	Mar 26 02:19:43 PM PDT 24
Peak memory	198272 kb
Host	smart-cafb5d53-e922-432d-8fa2-f9a5b555a12f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1569817498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1569817498
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_stress_all_with_rand_reset.1674398720
Short name	T803
Test name
Test status
Simulation time	46741910120 ps
CPU time	707.16 seconds
Started	Mar 26 02:19:45 PM PDT 24
Finished	Mar 26 02:31:32 PM PDT 24
Peak memory	216708 kb
Host	smart-196ad819-944c-4907-b7d3-55075b56e43d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674398720 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1674398720
Directory	/workspace/3.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.998488476
Short name	T550
Test name
Test status
Simulation time	1938540751 ps
CPU time	2.04 seconds
Started	Mar 26 02:19:41 PM PDT 24
Finished	Mar 26 02:19:43 PM PDT 24
Peak memory	198724 kb
Host	smart-ec01de66-669f-482a-a362-b8261daddfdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998488476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.998488476
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.2176175594
Short name	T300
Test name
Test status
Simulation time	88242845065 ps
CPU time	73.91 seconds
Started	Mar 26 02:19:45 PM PDT 24
Finished	Mar 26 02:20:59 PM PDT 24
Peak memory	200052 kb
Host	smart-e29b57b6-c80a-4ed4-aa85-cbe335baa960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2176175594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2176175594
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.839243631
Short name	T786
Test name
Test status
Simulation time	12054819 ps
CPU time	0.56 seconds
Started	Mar 26 02:23:33 PM PDT 24
Finished	Mar 26 02:23:34 PM PDT 24
Peak memory	194464 kb
Host	smart-d7a7410e-636e-4e2e-9261-5ba38a104aea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839243631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.839243631
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.1719531684
Short name	T718
Test name
Test status
Simulation time	32388457200 ps
CPU time	49.71 seconds
Started	Mar 26 02:23:23 PM PDT 24
Finished	Mar 26 02:24:13 PM PDT 24
Peak memory	200044 kb
Host	smart-b2adafee-cd9f-40d1-a575-4f0ab5523d81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719531684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1719531684
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.1814280704
Short name	T54
Test name
Test status
Simulation time	84565482875 ps
CPU time	76.73 seconds
Started	Mar 26 02:23:23 PM PDT 24
Finished	Mar 26 02:24:40 PM PDT 24
Peak memory	200112 kb
Host	smart-9f0cd3aa-0f27-4e1b-808c-3703c6980915
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814280704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1814280704
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.1503539191
Short name	T1002
Test name
Test status
Simulation time	65445660819 ps
CPU time	29.24 seconds
Started	Mar 26 02:23:22 PM PDT 24
Finished	Mar 26 02:23:51 PM PDT 24
Peak memory	199920 kb
Host	smart-78866e4c-5bcf-413e-9134-cc539ab24f6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503539191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1503539191
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_intr.2533562241
Short name	T429
Test name
Test status
Simulation time	207347123994 ps
CPU time	85.27 seconds
Started	Mar 26 02:23:23 PM PDT 24
Finished	Mar 26 02:24:48 PM PDT 24
Peak memory	197000 kb
Host	smart-b78e63d1-5f73-47bb-aebe-d711b1c1dbc0
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533562241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2533562241
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.1927679846
Short name	T443
Test name
Test status
Simulation time	167760183359 ps
CPU time	1829.47 seconds
Started	Mar 26 02:23:24 PM PDT 24
Finished	Mar 26 02:53:54 PM PDT 24
Peak memory	200072 kb
Host	smart-88321731-b7ac-4cc4-8c0c-213daa8f5781
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1927679846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1927679846
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_loopback.1473418417
Short name	T883
Test name
Test status
Simulation time	8299235286 ps
CPU time	5.3 seconds
Started	Mar 26 02:23:22 PM PDT 24
Finished	Mar 26 02:23:28 PM PDT 24
Peak memory	199856 kb
Host	smart-0b942f1e-facf-4212-892b-fadad2a3e77c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473418417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1473418417
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.1719911672
Short name	T483
Test name
Test status
Simulation time	243571131393 ps
CPU time	96.1 seconds
Started	Mar 26 02:23:22 PM PDT 24
Finished	Mar 26 02:24:59 PM PDT 24
Peak memory	200096 kb
Host	smart-189a221a-63b2-410c-b6dd-a5df57eac111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719911672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1719911672
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_perf.338445390
Short name	T437
Test name
Test status
Simulation time	5902177359 ps
CPU time	302.79 seconds
Started	Mar 26 02:23:27 PM PDT 24
Finished	Mar 26 02:28:30 PM PDT 24
Peak memory	200056 kb
Host	smart-cb5d2e7c-d4f7-4b7c-9e15-60b7c1a46f33
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=338445390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.338445390
Directory	/workspace/30.uart_perf/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.1945226850
Short name	T113
Test name
Test status
Simulation time	1273934797 ps
CPU time	5.35 seconds
Started	Mar 26 02:23:23 PM PDT 24
Finished	Mar 26 02:23:28 PM PDT 24
Peak memory	197944 kb
Host	smart-2dc0109b-f2fe-478c-a9cd-2660717754f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1945226850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1945226850
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.2607159879
Short name	T335
Test name
Test status
Simulation time	3027235292 ps
CPU time	1.69 seconds
Started	Mar 26 02:23:27 PM PDT 24
Finished	Mar 26 02:23:29 PM PDT 24
Peak memory	195960 kb
Host	smart-090c039d-f3b3-43ab-898b-066af74e1163
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607159879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2607159879
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.1921514197
Short name	T55
Test name
Test status
Simulation time	462560344 ps
CPU time	2.09 seconds
Started	Mar 26 02:23:27 PM PDT 24
Finished	Mar 26 02:23:30 PM PDT 24
Peak memory	199320 kb
Host	smart-b6b3cd55-e293-470d-ab84-983189ee34af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921514197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1921514197
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all.1600686638
Short name	T333
Test name
Test status
Simulation time	259036590601 ps
CPU time	1189.8 seconds
Started	Mar 26 02:23:31 PM PDT 24
Finished	Mar 26 02:43:22 PM PDT 24
Peak memory	200144 kb
Host	smart-59e2547f-ee68-46cb-8ed6-e0b79352b713
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600686638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1600686638
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.298414543
Short name	T955
Test name
Test status
Simulation time	1040155125 ps
CPU time	2.28 seconds
Started	Mar 26 02:23:22 PM PDT 24
Finished	Mar 26 02:23:24 PM PDT 24
Peak memory	199736 kb
Host	smart-b7603979-f226-45ff-946d-e6e3fa08684e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298414543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.298414543
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.1650192687
Short name	T813
Test name
Test status
Simulation time	8079202100 ps
CPU time	13.06 seconds
Started	Mar 26 02:23:22 PM PDT 24
Finished	Mar 26 02:23:36 PM PDT 24
Peak memory	198144 kb
Host	smart-1d85458c-69ea-4721-a2c2-334f41206b4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650192687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1650192687
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.3305946209
Short name	T592
Test name
Test status
Simulation time	40620667 ps
CPU time	0.59 seconds
Started	Mar 26 02:23:44 PM PDT 24
Finished	Mar 26 02:23:45 PM PDT 24
Peak memory	195576 kb
Host	smart-efb14530-f9aa-47d5-8466-9f74263df0e2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305946209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3305946209
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.504624003
Short name	T971
Test name
Test status
Simulation time	19933321233 ps
CPU time	10.23 seconds
Started	Mar 26 02:23:32 PM PDT 24
Finished	Mar 26 02:23:43 PM PDT 24
Peak memory	200084 kb
Host	smart-c4c9433a-8a7a-4928-800d-a189631e2b9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504624003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.504624003
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.2681827849
Short name	T199
Test name
Test status
Simulation time	146922917853 ps
CPU time	100.46 seconds
Started	Mar 26 02:23:33 PM PDT 24
Finished	Mar 26 02:25:14 PM PDT 24
Peak memory	200048 kb
Host	smart-6f46ef9a-ae2e-42e7-b2a8-1b5e9a922385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681827849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2681827849
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.45652087
Short name	T1101
Test name
Test status
Simulation time	43683990301 ps
CPU time	25.25 seconds
Started	Mar 26 02:23:34 PM PDT 24
Finished	Mar 26 02:23:59 PM PDT 24
Peak memory	200060 kb
Host	smart-87db6c70-abe4-4c31-9ef5-98fd97eeedb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45652087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.45652087
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.785722807
Short name	T476
Test name
Test status
Simulation time	60429740264 ps
CPU time	85.91 seconds
Started	Mar 26 02:23:32 PM PDT 24
Finished	Mar 26 02:24:58 PM PDT 24
Peak memory	196192 kb
Host	smart-e0159b3c-2a30-4d86-ac2c-24692fb52056
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785722807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.785722807
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.2816760093
Short name	T487
Test name
Test status
Simulation time	181031003234 ps
CPU time	119.9 seconds
Started	Mar 26 02:23:44 PM PDT 24
Finished	Mar 26 02:25:44 PM PDT 24
Peak memory	200040 kb
Host	smart-d754f64b-cc6c-4dc5-be40-37510514ed1f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2816760093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2816760093
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_loopback.2455142725
Short name	T1069
Test name
Test status
Simulation time	10084344203 ps
CPU time	19.48 seconds
Started	Mar 26 02:23:31 PM PDT 24
Finished	Mar 26 02:23:51 PM PDT 24
Peak memory	200084 kb
Host	smart-1303351b-31ac-41a9-98e9-7672472265e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455142725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2455142725
Directory	/workspace/31.uart_loopback/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.2141506286
Short name	T650
Test name
Test status
Simulation time	79298496918 ps
CPU time	135.27 seconds
Started	Mar 26 02:23:31 PM PDT 24
Finished	Mar 26 02:25:48 PM PDT 24
Peak memory	215736 kb
Host	smart-499699e8-3e44-4e4e-b5df-26e27823d44b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141506286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2141506286
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.65244189
Short name	T1081
Test name
Test status
Simulation time	22936881614 ps
CPU time	465.99 seconds
Started	Mar 26 02:23:30 PM PDT 24
Finished	Mar 26 02:31:17 PM PDT 24
Peak memory	200060 kb
Host	smart-aa1ccb2c-e1f6-4983-8b25-5a7722da9e0c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=65244189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.65244189
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_oversample.3867448126
Short name	T357
Test name
Test status
Simulation time	6553770827 ps
CPU time	67.64 seconds
Started	Mar 26 02:23:32 PM PDT 24
Finished	Mar 26 02:24:40 PM PDT 24
Peak memory	199268 kb
Host	smart-0d937657-b7e6-40f7-a811-2fb494167616
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3867448126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3867448126
Directory	/workspace/31.uart_rx_oversample/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.879743762
Short name	T784
Test name
Test status
Simulation time	61430573643 ps
CPU time	11.48 seconds
Started	Mar 26 02:23:31 PM PDT 24
Finished	Mar 26 02:23:44 PM PDT 24
Peak memory	200040 kb
Host	smart-6d018461-c635-4c7c-b246-370b8da7b40c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879743762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.879743762
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.2264500337
Short name	T836
Test name
Test status
Simulation time	4584264645 ps
CPU time	2.13 seconds
Started	Mar 26 02:23:32 PM PDT 24
Finished	Mar 26 02:23:35 PM PDT 24
Peak memory	196112 kb
Host	smart-be9d6ef3-8353-4933-802a-cb868ac63c72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264500337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2264500337
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.3802147859
Short name	T611
Test name
Test status
Simulation time	862603027 ps
CPU time	1.68 seconds
Started	Mar 26 02:23:32 PM PDT 24
Finished	Mar 26 02:23:34 PM PDT 24
Peak memory	198324 kb
Host	smart-24b800bf-d3ec-4789-92e7-5444a8bf904c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802147859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3802147859
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_stress_all.2719244965
Short name	T140
Test name
Test status
Simulation time	138302115453 ps
CPU time	708.28 seconds
Started	Mar 26 02:23:42 PM PDT 24
Finished	Mar 26 02:35:31 PM PDT 24
Peak memory	216636 kb
Host	smart-e97a51d1-0bdf-4060-b434-d2123619a61c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719244965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2719244965
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.3545389778
Short name	T450
Test name
Test status
Simulation time	993085286 ps
CPU time	3.23 seconds
Started	Mar 26 02:23:31 PM PDT 24
Finished	Mar 26 02:23:34 PM PDT 24
Peak memory	198396 kb
Host	smart-4fe81431-2ed2-4f08-9ba4-434c8039f2d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545389778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3545389778
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.1638022862
Short name	T1110
Test name
Test status
Simulation time	29555733671 ps
CPU time	13.77 seconds
Started	Mar 26 02:23:34 PM PDT 24
Finished	Mar 26 02:23:48 PM PDT 24
Peak memory	198292 kb
Host	smart-845e4e1b-3c67-45db-a6b2-060f7fe6c9d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638022862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1638022862
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.3499976857
Short name	T913
Test name
Test status
Simulation time	11671113 ps
CPU time	0.56 seconds
Started	Mar 26 02:23:54 PM PDT 24
Finished	Mar 26 02:23:55 PM PDT 24
Peak memory	194964 kb
Host	smart-1183d491-8965-459c-b6d7-7c4732b2b262
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499976857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3499976857
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.2754165218
Short name	T635
Test name
Test status
Simulation time	67642592306 ps
CPU time	68.3 seconds
Started	Mar 26 02:23:44 PM PDT 24
Finished	Mar 26 02:24:52 PM PDT 24
Peak memory	200060 kb
Host	smart-c6ef61f7-768f-4fbb-90e0-6b79f85b6cf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754165218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2754165218
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.1846006218
Short name	T66
Test name
Test status
Simulation time	27269226883 ps
CPU time	10.79 seconds
Started	Mar 26 02:23:43 PM PDT 24
Finished	Mar 26 02:23:54 PM PDT 24
Peak memory	199952 kb
Host	smart-372d78b3-fc8a-4994-8619-c52bc0d6e803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846006218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1846006218
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_intr.1654734329
Short name	T544
Test name
Test status
Simulation time	11558198437 ps
CPU time	6.12 seconds
Started	Mar 26 02:23:45 PM PDT 24
Finished	Mar 26 02:23:51 PM PDT 24
Peak memory	200012 kb
Host	smart-bc14e206-d10f-454d-9688-fee4352da6d3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654734329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1654734329
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.3836317352
Short name	T289
Test name
Test status
Simulation time	136604859037 ps
CPU time	981.73 seconds
Started	Mar 26 02:23:54 PM PDT 24
Finished	Mar 26 02:40:16 PM PDT 24
Peak memory	200080 kb
Host	smart-732eb0b3-cd66-449c-9a2a-4eb3fac53897
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3836317352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3836317352
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.34294592
Short name	T532
Test name
Test status
Simulation time	4868088476 ps
CPU time	9.2 seconds
Started	Mar 26 02:23:55 PM PDT 24
Finished	Mar 26 02:24:04 PM PDT 24
Peak memory	196552 kb
Host	smart-36e5c537-c613-4465-b8bf-5a42cd9e0b66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34294592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.34294592
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_noise_filter.4061427196
Short name	T293
Test name
Test status
Simulation time	90914893045 ps
CPU time	40.49 seconds
Started	Mar 26 02:23:45 PM PDT 24
Finished	Mar 26 02:24:26 PM PDT 24
Peak memory	200244 kb
Host	smart-db64ea7a-e63d-4d1e-80d9-8ee3cfc49b08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061427196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4061427196
Directory	/workspace/32.uart_noise_filter/latest

Test location	/workspace/coverage/default/32.uart_perf.1296146678
Short name	T765
Test name
Test status
Simulation time	4691095947 ps
CPU time	50.19 seconds
Started	Mar 26 02:23:53 PM PDT 24
Finished	Mar 26 02:24:43 PM PDT 24
Peak memory	200052 kb
Host	smart-b58610c8-4dfc-4f80-83f0-06fd55d44416
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1296146678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1296146678
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.1069656767
Short name	T397
Test name
Test status
Simulation time	4959774630 ps
CPU time	22.2 seconds
Started	Mar 26 02:23:43 PM PDT 24
Finished	Mar 26 02:24:05 PM PDT 24
Peak memory	199372 kb
Host	smart-834580c6-3bfd-4a68-bb33-fe25288e03be
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1069656767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1069656767
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.3871087278
Short name	T1088
Test name
Test status
Simulation time	25096392636 ps
CPU time	15.12 seconds
Started	Mar 26 02:23:43 PM PDT 24
Finished	Mar 26 02:23:58 PM PDT 24
Peak memory	199980 kb
Host	smart-b127d530-b77d-4d5b-b4dc-4e2904b5fbd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871087278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3871087278
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.3146077191
Short name	T565
Test name
Test status
Simulation time	3121136479 ps
CPU time	5.93 seconds
Started	Mar 26 02:23:44 PM PDT 24
Finished	Mar 26 02:23:50 PM PDT 24
Peak memory	196028 kb
Host	smart-e932c8c0-f4b6-48ba-8c63-2e4740ab30a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146077191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3146077191
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.2415102084
Short name	T434
Test name
Test status
Simulation time	5355917369 ps
CPU time	9.79 seconds
Started	Mar 26 02:23:42 PM PDT 24
Finished	Mar 26 02:23:52 PM PDT 24
Peak memory	199960 kb
Host	smart-4fd6d040-2357-4eef-bc25-b8695badb96f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415102084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2415102084
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.2630890339
Short name	T86
Test name
Test status
Simulation time	533482967 ps
CPU time	1.82 seconds
Started	Mar 26 02:23:43 PM PDT 24
Finished	Mar 26 02:23:46 PM PDT 24
Peak memory	198728 kb
Host	smart-f0d94a76-3bbf-4cea-9908-a660dde27a2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630890339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2630890339
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.2622221758
Short name	T851
Test name
Test status
Simulation time	8656617868 ps
CPU time	5.99 seconds
Started	Mar 26 02:23:45 PM PDT 24
Finished	Mar 26 02:23:51 PM PDT 24
Peak memory	196824 kb
Host	smart-c016c9e2-cc5e-43dc-92c4-5d4789897bb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622221758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2622221758
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.1341651935
Short name	T1106
Test name
Test status
Simulation time	20500051 ps
CPU time	0.62 seconds
Started	Mar 26 02:24:06 PM PDT 24
Finished	Mar 26 02:24:06 PM PDT 24
Peak memory	195584 kb
Host	smart-5df1d0b3-14b0-4a89-875a-2dc2f8f21166
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341651935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1341651935
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.260887640
Short name	T285
Test name
Test status
Simulation time	102791797793 ps
CPU time	38.44 seconds
Started	Mar 26 02:23:52 PM PDT 24
Finished	Mar 26 02:24:31 PM PDT 24
Peak memory	200012 kb
Host	smart-01b20e36-b01e-495d-bd7d-b83b7504de14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260887640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.260887640
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.1696089512
Short name	T508
Test name
Test status
Simulation time	90241125777 ps
CPU time	72.39 seconds
Started	Mar 26 02:23:55 PM PDT 24
Finished	Mar 26 02:25:07 PM PDT 24
Peak memory	200008 kb
Host	smart-2483d3d3-fa16-42bc-bf88-a532e55b9557
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696089512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1696089512
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.2770653639
Short name	T163
Test name
Test status
Simulation time	22445775286 ps
CPU time	36.41 seconds
Started	Mar 26 02:23:55 PM PDT 24
Finished	Mar 26 02:24:31 PM PDT 24
Peak memory	200000 kb
Host	smart-47aaf973-2a9a-4b26-b7b4-f95dd221cb2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770653639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2770653639
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.175193138
Short name	T628
Test name
Test status
Simulation time	43165187785 ps
CPU time	36.07 seconds
Started	Mar 26 02:23:55 PM PDT 24
Finished	Mar 26 02:24:31 PM PDT 24
Peak memory	200008 kb
Host	smart-24467508-ec87-403d-8dd3-66cff13f15eb
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175193138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.175193138
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.3317583457
Short name	T1003
Test name
Test status
Simulation time	161286487257 ps
CPU time	771.41 seconds
Started	Mar 26 02:24:02 PM PDT 24
Finished	Mar 26 02:36:53 PM PDT 24
Peak memory	200272 kb
Host	smart-7dc50baa-f0da-42d9-aaf3-d56eb6aba852
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3317583457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3317583457
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.3902870051
Short name	T412
Test name
Test status
Simulation time	10583826362 ps
CPU time	4.48 seconds
Started	Mar 26 02:23:52 PM PDT 24
Finished	Mar 26 02:23:57 PM PDT 24
Peak memory	200028 kb
Host	smart-4b46b075-0b5b-4a25-bd1c-e17a81d71f4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3902870051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3902870051
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.2002314621
Short name	T464
Test name
Test status
Simulation time	227124885461 ps
CPU time	183.08 seconds
Started	Mar 26 02:23:54 PM PDT 24
Finished	Mar 26 02:26:57 PM PDT 24
Peak memory	208416 kb
Host	smart-f24c68bd-b6b2-4588-aa9c-3dd298634e21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002314621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2002314621
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.1190015500
Short name	T329
Test name
Test status
Simulation time	16393058643 ps
CPU time	213.58 seconds
Started	Mar 26 02:24:03 PM PDT 24
Finished	Mar 26 02:27:37 PM PDT 24
Peak memory	200008 kb
Host	smart-215331ef-55aa-4ab1-92f3-dede5952e7f6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1190015500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1190015500
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.3393536692
Short name	T10
Test name
Test status
Simulation time	5241586392 ps
CPU time	45.48 seconds
Started	Mar 26 02:23:52 PM PDT 24
Finished	Mar 26 02:24:38 PM PDT 24
Peak memory	198172 kb
Host	smart-d802a49a-5fe9-4db4-9711-d1590ad87f68
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3393536692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3393536692
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.3548795163
Short name	T1000
Test name
Test status
Simulation time	291038782152 ps
CPU time	44.24 seconds
Started	Mar 26 02:23:53 PM PDT 24
Finished	Mar 26 02:24:38 PM PDT 24
Peak memory	200032 kb
Host	smart-f3d6a943-7748-41fa-8c04-3d8d4979bcab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548795163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3548795163
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.4120877263
Short name	T711
Test name
Test status
Simulation time	5771292516 ps
CPU time	10.58 seconds
Started	Mar 26 02:23:53 PM PDT 24
Finished	Mar 26 02:24:04 PM PDT 24
Peak memory	196180 kb
Host	smart-5eef1aad-6d70-4baa-86d3-4eac6ece8099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120877263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4120877263
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.2867872469
Short name	T806
Test name
Test status
Simulation time	718270124 ps
CPU time	1.64 seconds
Started	Mar 26 02:23:53 PM PDT 24
Finished	Mar 26 02:23:55 PM PDT 24
Peak memory	199336 kb
Host	smart-559a8c4b-b0ee-4c1d-b5f7-1fdb2ed025be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867872469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2867872469
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all.1891957447
Short name	T220
Test name
Test status
Simulation time	149284505098 ps
CPU time	829.3 seconds
Started	Mar 26 02:24:03 PM PDT 24
Finished	Mar 26 02:37:52 PM PDT 24
Peak memory	200100 kb
Host	smart-885c94b2-f777-474d-9b4a-3dc97548dabc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891957447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1891957447
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.3698238554
Short name	T664
Test name
Test status
Simulation time	1758708171 ps
CPU time	3.08 seconds
Started	Mar 26 02:23:53 PM PDT 24
Finished	Mar 26 02:23:56 PM PDT 24
Peak memory	199512 kb
Host	smart-9f7b9257-b706-40b6-811e-7eece5c93a75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698238554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3698238554
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.1964695180
Short name	T327
Test name
Test status
Simulation time	181970166930 ps
CPU time	61.44 seconds
Started	Mar 26 02:23:53 PM PDT 24
Finished	Mar 26 02:24:54 PM PDT 24
Peak memory	200088 kb
Host	smart-0c13a425-223c-4b2c-8959-671a81252f22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964695180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1964695180
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.1519913444
Short name	T35
Test name
Test status
Simulation time	23538700 ps
CPU time	0.57 seconds
Started	Mar 26 02:24:12 PM PDT 24
Finished	Mar 26 02:24:12 PM PDT 24
Peak memory	195532 kb
Host	smart-4e538899-6bf3-4a73-b47b-d12f54fe9501
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519913444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1519913444
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.2916067608
Short name	T567
Test name
Test status
Simulation time	35485291252 ps
CPU time	59.45 seconds
Started	Mar 26 02:24:03 PM PDT 24
Finished	Mar 26 02:25:02 PM PDT 24
Peak memory	200056 kb
Host	smart-d19eb87e-285c-4af9-a8b3-94cb1f6a05ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916067608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2916067608
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.1507014059
Short name	T597
Test name
Test status
Simulation time	18846573030 ps
CPU time	52.26 seconds
Started	Mar 26 02:24:05 PM PDT 24
Finished	Mar 26 02:24:57 PM PDT 24
Peak memory	199932 kb
Host	smart-30525c4f-c26a-46d6-8371-b6651e7968f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507014059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1507014059
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.2036300269
Short name	T938
Test name
Test status
Simulation time	43647150735 ps
CPU time	32.79 seconds
Started	Mar 26 02:24:03 PM PDT 24
Finished	Mar 26 02:24:36 PM PDT 24
Peak memory	200136 kb
Host	smart-1b424d7e-aabc-49e3-a088-db207a081554
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036300269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2036300269
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_intr.3450067109
Short name	T873
Test name
Test status
Simulation time	49429668972 ps
CPU time	84.84 seconds
Started	Mar 26 02:24:11 PM PDT 24
Finished	Mar 26 02:25:36 PM PDT 24
Peak memory	199012 kb
Host	smart-8a870c6b-1ff7-4224-87d1-df3b4aedf22e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450067109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3450067109
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.2410212016
Short name	T394
Test name
Test status
Simulation time	143207305789 ps
CPU time	413.59 seconds
Started	Mar 26 02:24:10 PM PDT 24
Finished	Mar 26 02:31:04 PM PDT 24
Peak memory	200060 kb
Host	smart-e9631c41-2a48-44e9-a1d3-9ff6dd1939b9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2410212016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2410212016
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.3329405326
Short name	T1076
Test name
Test status
Simulation time	80691453 ps
CPU time	0.63 seconds
Started	Mar 26 02:24:12 PM PDT 24
Finished	Mar 26 02:24:13 PM PDT 24
Peak memory	195952 kb
Host	smart-42428603-6f53-4b6e-b70b-2fe7975cc9a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329405326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3329405326
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.2012604933
Short name	T497
Test name
Test status
Simulation time	39533837721 ps
CPU time	70.05 seconds
Started	Mar 26 02:24:10 PM PDT 24
Finished	Mar 26 02:25:21 PM PDT 24
Peak memory	200268 kb
Host	smart-6a470c66-3be9-41bd-aa2b-23477547a5e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012604933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2012604933
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_perf.3763457114
Short name	T770
Test name
Test status
Simulation time	22406433401 ps
CPU time	1078.23 seconds
Started	Mar 26 02:24:13 PM PDT 24
Finished	Mar 26 02:42:11 PM PDT 24
Peak memory	200004 kb
Host	smart-7789cc00-992e-45d9-81d5-e137c1796da6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3763457114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3763457114
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.2789469888
Short name	T976
Test name
Test status
Simulation time	5478335817 ps
CPU time	48.91 seconds
Started	Mar 26 02:24:12 PM PDT 24
Finished	Mar 26 02:25:01 PM PDT 24
Peak memory	199168 kb
Host	smart-cad8f496-b128-4cac-afdd-96fc05900662
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2789469888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2789469888
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.506356377
Short name	T20
Test name
Test status
Simulation time	50278184610 ps
CPU time	94.13 seconds
Started	Mar 26 02:24:11 PM PDT 24
Finished	Mar 26 02:25:46 PM PDT 24
Peak memory	200060 kb
Host	smart-376082d1-09ac-4fe4-8968-b2e0b91d69e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506356377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.506356377
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.335315556
Short name	T840
Test name
Test status
Simulation time	1557920518 ps
CPU time	1.77 seconds
Started	Mar 26 02:24:11 PM PDT 24
Finished	Mar 26 02:24:13 PM PDT 24
Peak memory	195836 kb
Host	smart-2d823a8b-aab1-46be-b57f-64a13a808ff8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335315556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.335315556
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.1925482819
Short name	T506
Test name
Test status
Simulation time	689626216 ps
CPU time	1.77 seconds
Started	Mar 26 02:24:02 PM PDT 24
Finished	Mar 26 02:24:03 PM PDT 24
Peak memory	199636 kb
Host	smart-8bb6afd4-d799-4854-a262-a25990d32d60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925482819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1925482819
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_stress_all.3327715664
Short name	T1077
Test name
Test status
Simulation time	273283734716 ps
CPU time	252.12 seconds
Started	Mar 26 02:24:11 PM PDT 24
Finished	Mar 26 02:28:23 PM PDT 24
Peak memory	200140 kb
Host	smart-0119eb75-5d95-4b4c-b544-d4121381cfe3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327715664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3327715664
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.1421207365
Short name	T558
Test name
Test status
Simulation time	6783118990 ps
CPU time	30.57 seconds
Started	Mar 26 02:24:10 PM PDT 24
Finished	Mar 26 02:24:41 PM PDT 24
Peak memory	200004 kb
Host	smart-a09cca9c-7c65-438f-a1e0-46d07c690682
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421207365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1421207365
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.4154904369
Short name	T449
Test name
Test status
Simulation time	68016402415 ps
CPU time	103.53 seconds
Started	Mar 26 02:24:03 PM PDT 24
Finished	Mar 26 02:25:47 PM PDT 24
Peak memory	199976 kb
Host	smart-1d4dc693-2558-4080-b62a-38bea3123512
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154904369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4154904369
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.2582951032
Short name	T376
Test name
Test status
Simulation time	39246093 ps
CPU time	0.52 seconds
Started	Mar 26 02:24:27 PM PDT 24
Finished	Mar 26 02:24:28 PM PDT 24
Peak memory	195596 kb
Host	smart-eab58170-fed0-4e2d-83eb-1b22159e54b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582951032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2582951032
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.458539428
Short name	T48
Test name
Test status
Simulation time	27868367591 ps
CPU time	47.11 seconds
Started	Mar 26 02:24:18 PM PDT 24
Finished	Mar 26 02:25:06 PM PDT 24
Peak memory	200052 kb
Host	smart-6ec9b772-c009-4256-bc9d-e4c8a56d4cdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458539428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.458539428
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.3490564621
Short name	T440
Test name
Test status
Simulation time	29859574387 ps
CPU time	39.59 seconds
Started	Mar 26 02:24:18 PM PDT 24
Finished	Mar 26 02:24:57 PM PDT 24
Peak memory	200112 kb
Host	smart-094d5fe8-0ea6-439f-a2a4-a3c5cc549c58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490564621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3490564621
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.3121557894
Short name	T684
Test name
Test status
Simulation time	25687384640 ps
CPU time	16.39 seconds
Started	Mar 26 02:24:19 PM PDT 24
Finished	Mar 26 02:24:35 PM PDT 24
Peak memory	200024 kb
Host	smart-7a195d67-f728-433f-a1b3-b60d9a4122e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121557894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3121557894
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/35.uart_intr.3261438764
Short name	T1017
Test name
Test status
Simulation time	14580196957 ps
CPU time	21.41 seconds
Started	Mar 26 02:24:19 PM PDT 24
Finished	Mar 26 02:24:40 PM PDT 24
Peak memory	200116 kb
Host	smart-055c9325-6b74-40e1-bf95-a9fbb5b85143
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261438764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3261438764
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.2065535840
Short name	T672
Test name
Test status
Simulation time	86947395250 ps
CPU time	535.32 seconds
Started	Mar 26 02:24:27 PM PDT 24
Finished	Mar 26 02:33:23 PM PDT 24
Peak memory	200060 kb
Host	smart-5f25f078-9e46-4783-b895-6bb11434fdb6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2065535840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2065535840
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.588744010
Short name	T993
Test name
Test status
Simulation time	2760614116 ps
CPU time	3.29 seconds
Started	Mar 26 02:24:27 PM PDT 24
Finished	Mar 26 02:24:31 PM PDT 24
Peak memory	197508 kb
Host	smart-f1c1e30f-c282-4fe5-94ef-bb260fb12d27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588744010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.588744010
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_noise_filter.1328840561
Short name	T305
Test name
Test status
Simulation time	101378963837 ps
CPU time	216.27 seconds
Started	Mar 26 02:24:18 PM PDT 24
Finished	Mar 26 02:27:55 PM PDT 24
Peak memory	200224 kb
Host	smart-5f970989-ce3e-4c21-b515-5de2e07e25e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1328840561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1328840561
Directory	/workspace/35.uart_noise_filter/latest

Test location	/workspace/coverage/default/35.uart_perf.1675452427
Short name	T513
Test name
Test status
Simulation time	22122538619 ps
CPU time	1379.74 seconds
Started	Mar 26 02:24:27 PM PDT 24
Finished	Mar 26 02:47:27 PM PDT 24
Peak memory	200088 kb
Host	smart-676d04c3-f118-4568-b379-84dc269844e1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1675452427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1675452427
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.4113651180
Short name	T383
Test name
Test status
Simulation time	5858619599 ps
CPU time	12.25 seconds
Started	Mar 26 02:24:19 PM PDT 24
Finished	Mar 26 02:24:31 PM PDT 24
Peak memory	199044 kb
Host	smart-fba940c2-e802-4ec7-9f1e-c8a87bb23f71
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4113651180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.4113651180
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.35292706
Short name	T653
Test name
Test status
Simulation time	53494121756 ps
CPU time	89.47 seconds
Started	Mar 26 02:24:19 PM PDT 24
Finished	Mar 26 02:25:49 PM PDT 24
Peak memory	199816 kb
Host	smart-3933f9fd-500f-4b0b-8792-5c3f45ff3b58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35292706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.35292706
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.2976594817
Short name	T940
Test name
Test status
Simulation time	1767718542 ps
CPU time	1.72 seconds
Started	Mar 26 02:24:21 PM PDT 24
Finished	Mar 26 02:24:23 PM PDT 24
Peak memory	195544 kb
Host	smart-5a16a597-0559-4b47-971c-9900b6178b29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976594817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2976594817
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.1877312783
Short name	T334
Test name
Test status
Simulation time	544515812 ps
CPU time	2.62 seconds
Started	Mar 26 02:24:14 PM PDT 24
Finished	Mar 26 02:24:16 PM PDT 24
Peak memory	198272 kb
Host	smart-dbf9714e-fb16-4e4b-904b-6017ec942963
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877312783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1877312783
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all.907873894
Short name	T274
Test name
Test status
Simulation time	27458080642 ps
CPU time	344.19 seconds
Started	Mar 26 02:24:27 PM PDT 24
Finished	Mar 26 02:30:11 PM PDT 24
Peak memory	200088 kb
Host	smart-b1b4d043-4d07-4419-8fc6-5546c77605f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907873894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.907873894
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.3956881228
Short name	T904
Test name
Test status
Simulation time	710463404 ps
CPU time	2.35 seconds
Started	Mar 26 02:24:27 PM PDT 24
Finished	Mar 26 02:24:30 PM PDT 24
Peak memory	198808 kb
Host	smart-b82a39c5-6905-4f75-af56-e96a2cb1b15c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956881228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3956881228
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.4043689874
Short name	T1072
Test name
Test status
Simulation time	89682019041 ps
CPU time	36.59 seconds
Started	Mar 26 02:24:11 PM PDT 24
Finished	Mar 26 02:24:48 PM PDT 24
Peak memory	199980 kb
Host	smart-da3c2ae1-3a22-41a5-af6e-be4dd8a7d38f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043689874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4043689874
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.310013032
Short name	T527
Test name
Test status
Simulation time	12859648 ps
CPU time	0.58 seconds
Started	Mar 26 02:24:40 PM PDT 24
Finished	Mar 26 02:24:43 PM PDT 24
Peak memory	195580 kb
Host	smart-aab3b153-fdd4-4870-8459-f2fcb01e09fc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310013032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.310013032
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.2223592754
Short name	T744
Test name
Test status
Simulation time	78509474524 ps
CPU time	32.31 seconds
Started	Mar 26 02:24:28 PM PDT 24
Finished	Mar 26 02:25:00 PM PDT 24
Peak memory	200100 kb
Host	smart-c74afb5c-844f-4f5a-9514-228152edecfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223592754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2223592754
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.2230384851
Short name	T393
Test name
Test status
Simulation time	243714209767 ps
CPU time	26.8 seconds
Started	Mar 26 02:24:27 PM PDT 24
Finished	Mar 26 02:24:54 PM PDT 24
Peak memory	200088 kb
Host	smart-27c9fe5a-3802-439b-9dc6-f60aff75ffd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230384851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2230384851
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.725078831
Short name	T704
Test name
Test status
Simulation time	130913649339 ps
CPU time	14.42 seconds
Started	Mar 26 02:24:26 PM PDT 24
Finished	Mar 26 02:24:41 PM PDT 24
Peak memory	199956 kb
Host	smart-c7029293-cd9e-4c32-8091-c7d93b6cfc6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725078831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.725078831
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_intr.2245671217
Short name	T817
Test name
Test status
Simulation time	3023760610 ps
CPU time	5.27 seconds
Started	Mar 26 02:24:37 PM PDT 24
Finished	Mar 26 02:24:43 PM PDT 24
Peak memory	200176 kb
Host	smart-583160f4-baea-4a72-aedf-3497dc0110d6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245671217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2245671217
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.2709935607
Short name	T151
Test name
Test status
Simulation time	54735675883 ps
CPU time	228.66 seconds
Started	Mar 26 02:24:38 PM PDT 24
Finished	Mar 26 02:28:27 PM PDT 24
Peak memory	199980 kb
Host	smart-66472d30-5c33-461f-8d16-74cb2694f343
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2709935607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2709935607
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.613660792
Short name	T24
Test name
Test status
Simulation time	9087095696 ps
CPU time	5.37 seconds
Started	Mar 26 02:24:43 PM PDT 24
Finished	Mar 26 02:24:49 PM PDT 24
Peak memory	200076 kb
Host	smart-283a2825-953b-4fd9-83bf-cb78b374f62b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613660792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.613660792
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.2163877581
Short name	T284
Test name
Test status
Simulation time	260116540117 ps
CPU time	176.58 seconds
Started	Mar 26 02:24:40 PM PDT 24
Finished	Mar 26 02:27:39 PM PDT 24
Peak memory	199740 kb
Host	smart-013a1b8e-6e9b-4b4d-8ff0-e48cd0cf0abf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163877581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2163877581
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.1552493421
Short name	T820
Test name
Test status
Simulation time	28933835358 ps
CPU time	1038.93 seconds
Started	Mar 26 02:24:37 PM PDT 24
Finished	Mar 26 02:41:57 PM PDT 24
Peak memory	199984 kb
Host	smart-d64f2c29-9b6e-43be-8963-eb6773ff0f99
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1552493421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1552493421
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.1992102896
Short name	T749
Test name
Test status
Simulation time	6510841549 ps
CPU time	13.85 seconds
Started	Mar 26 02:24:29 PM PDT 24
Finished	Mar 26 02:24:43 PM PDT 24
Peak memory	198996 kb
Host	smart-7e92b298-4c0e-4bcd-9b87-d7272c5bf8cb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1992102896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1992102896
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.3031403514
Short name	T641
Test name
Test status
Simulation time	45519989944 ps
CPU time	37.57 seconds
Started	Mar 26 02:24:37 PM PDT 24
Finished	Mar 26 02:25:15 PM PDT 24
Peak memory	199624 kb
Host	smart-6e2bd09f-5b93-4eaf-8ac1-12ed957ad926
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031403514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3031403514
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.3707763634
Short name	T413
Test name
Test status
Simulation time	6300996718 ps
CPU time	3.16 seconds
Started	Mar 26 02:24:38 PM PDT 24
Finished	Mar 26 02:24:41 PM PDT 24
Peak memory	196368 kb
Host	smart-2f1497ba-caba-4818-b695-03e2025defcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707763634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3707763634
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.378153083
Short name	T87
Test name
Test status
Simulation time	296320990 ps
CPU time	1.21 seconds
Started	Mar 26 02:24:28 PM PDT 24
Finished	Mar 26 02:24:30 PM PDT 24
Peak memory	198388 kb
Host	smart-d7b8c8b5-e769-4cfa-af3a-67ec451491bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378153083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.378153083
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all.481709835
Short name	T901
Test name
Test status
Simulation time	111008872185 ps
CPU time	1810.44 seconds
Started	Mar 26 02:24:37 PM PDT 24
Finished	Mar 26 02:54:48 PM PDT 24
Peak memory	200144 kb
Host	smart-bb538dda-b706-416a-8a1b-f97875ed2177
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481709835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.481709835
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.141845087
Short name	T984
Test name
Test status
Simulation time	1187461111 ps
CPU time	2.53 seconds
Started	Mar 26 02:24:38 PM PDT 24
Finished	Mar 26 02:24:41 PM PDT 24
Peak memory	199048 kb
Host	smart-35c3e18d-d643-4e38-9ef9-0b3b4d561ccd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=141845087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.141845087
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.2863524170
Short name	T409
Test name
Test status
Simulation time	62888616012 ps
CPU time	110.66 seconds
Started	Mar 26 02:24:29 PM PDT 24
Finished	Mar 26 02:26:20 PM PDT 24
Peak memory	199952 kb
Host	smart-520fe374-378b-4845-8847-4eab2cb5377d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863524170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2863524170
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.436901418
Short name	T37
Test name
Test status
Simulation time	29165760 ps
CPU time	0.55 seconds
Started	Mar 26 02:24:51 PM PDT 24
Finished	Mar 26 02:24:51 PM PDT 24
Peak memory	194492 kb
Host	smart-f465b413-b4f9-4bd0-900a-de3c489aab31
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436901418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.436901418
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.352555936
Short name	T1124
Test name
Test status
Simulation time	41751868749 ps
CPU time	48.7 seconds
Started	Mar 26 02:24:52 PM PDT 24
Finished	Mar 26 02:25:41 PM PDT 24
Peak memory	200088 kb
Host	smart-62453d6d-bd38-4b8d-bb66-1f0a6c36f232
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352555936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.352555936
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.2694654630
Short name	T454
Test name
Test status
Simulation time	89518817989 ps
CPU time	123.7 seconds
Started	Mar 26 02:24:51 PM PDT 24
Finished	Mar 26 02:26:55 PM PDT 24
Peak memory	199828 kb
Host	smart-042b4698-0fca-4f13-99a0-bc793fea8294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694654630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2694654630
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.690759906
Short name	T724
Test name
Test status
Simulation time	180861944036 ps
CPU time	300.08 seconds
Started	Mar 26 02:24:50 PM PDT 24
Finished	Mar 26 02:29:51 PM PDT 24
Peak memory	199748 kb
Host	smart-cc0e578b-eba5-43b0-95ec-5a14b3474131
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690759906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.690759906
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_intr.2762983488
Short name	T1037
Test name
Test status
Simulation time	42948932406 ps
CPU time	86.87 seconds
Started	Mar 26 02:24:51 PM PDT 24
Finished	Mar 26 02:26:18 PM PDT 24
Peak memory	200008 kb
Host	smart-743bddcf-adb8-4c4b-acc7-fa493506021a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762983488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2762983488
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.4009153315
Short name	T132
Test name
Test status
Simulation time	116773887640 ps
CPU time	665.4 seconds
Started	Mar 26 02:24:51 PM PDT 24
Finished	Mar 26 02:35:57 PM PDT 24
Peak memory	200096 kb
Host	smart-daa28b61-b4ce-4b50-a2e9-a3caf5069636
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4009153315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4009153315
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.3984518778
Short name	T455
Test name
Test status
Simulation time	766187000 ps
CPU time	1.7 seconds
Started	Mar 26 02:24:52 PM PDT 24
Finished	Mar 26 02:24:54 PM PDT 24
Peak memory	196188 kb
Host	smart-0aa416e9-9355-4af1-8b60-1d9b66dac6d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984518778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3984518778
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.233529716
Short name	T548
Test name
Test status
Simulation time	31124739256 ps
CPU time	17.14 seconds
Started	Mar 26 02:24:50 PM PDT 24
Finished	Mar 26 02:25:08 PM PDT 24
Peak memory	200024 kb
Host	smart-8ffaef17-56df-427b-bf91-cf5106ed1b1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233529716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.233529716
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.2258633631
Short name	T791
Test name
Test status
Simulation time	28810880952 ps
CPU time	368.8 seconds
Started	Mar 26 02:24:50 PM PDT 24
Finished	Mar 26 02:30:59 PM PDT 24
Peak memory	200004 kb
Host	smart-5a287157-3895-4899-9c2d-f4155bf0d5dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2258633631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2258633631
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.4199654043
Short name	T982
Test name
Test status
Simulation time	4629479629 ps
CPU time	44.72 seconds
Started	Mar 26 02:24:51 PM PDT 24
Finished	Mar 26 02:25:35 PM PDT 24
Peak memory	199408 kb
Host	smart-01afb934-be5e-4680-88de-bac71d9af975
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4199654043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.4199654043
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.3494722364
Short name	T179
Test name
Test status
Simulation time	116675361975 ps
CPU time	206.14 seconds
Started	Mar 26 02:24:50 PM PDT 24
Finished	Mar 26 02:28:17 PM PDT 24
Peak memory	199888 kb
Host	smart-135c1c9d-7096-4310-b0c8-d01910e92aac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494722364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3494722364
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.807639983
Short name	T1015
Test name
Test status
Simulation time	35499349334 ps
CPU time	15.61 seconds
Started	Mar 26 02:24:51 PM PDT 24
Finished	Mar 26 02:25:07 PM PDT 24
Peak memory	195924 kb
Host	smart-59791f7e-9f79-4235-93c0-e35911d5861b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807639983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.807639983
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.2703195767
Short name	T456
Test name
Test status
Simulation time	6282987491 ps
CPU time	37.38 seconds
Started	Mar 26 02:24:39 PM PDT 24
Finished	Mar 26 02:25:17 PM PDT 24
Peak memory	199812 kb
Host	smart-a9936b7c-5d3e-4b73-8f4b-d9c277408f6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703195767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2703195767
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_stress_all.376914498
Short name	T566
Test name
Test status
Simulation time	47611138427 ps
CPU time	106.38 seconds
Started	Mar 26 02:24:50 PM PDT 24
Finished	Mar 26 02:26:36 PM PDT 24
Peak memory	199980 kb
Host	smart-23723779-9697-4a92-af46-23c2b18497f4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376914498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.376914498
Directory	/workspace/37.uart_stress_all/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.724206796
Short name	T315
Test name
Test status
Simulation time	6298218176 ps
CPU time	13.38 seconds
Started	Mar 26 02:24:51 PM PDT 24
Finished	Mar 26 02:25:04 PM PDT 24
Peak memory	199852 kb
Host	smart-da9210ac-c512-44e0-82cd-6759939ec538
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724206796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.724206796
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.3816171748
Short name	T630
Test name
Test status
Simulation time	17167696989 ps
CPU time	7.28 seconds
Started	Mar 26 02:24:37 PM PDT 24
Finished	Mar 26 02:24:45 PM PDT 24
Peak memory	198816 kb
Host	smart-b70c630e-b2ab-418e-a821-55a830d5a534
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816171748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3816171748
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.64445556
Short name	T85
Test name
Test status
Simulation time	33746366 ps
CPU time	0.59 seconds
Started	Mar 26 02:25:01 PM PDT 24
Finished	Mar 26 02:25:03 PM PDT 24
Peak memory	195536 kb
Host	smart-a691c8f6-8a95-4bfb-ae8f-fbe8c6bbb80a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64445556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.64445556
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.1643509362
Short name	T505
Test name
Test status
Simulation time	39776083481 ps
CPU time	65.88 seconds
Started	Mar 26 02:25:01 PM PDT 24
Finished	Mar 26 02:26:07 PM PDT 24
Peak memory	200124 kb
Host	smart-e3d1d641-eda5-4702-8c7f-726ebae22074
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643509362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1643509362
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.31990682
Short name	T405
Test name
Test status
Simulation time	19016861335 ps
CPU time	34 seconds
Started	Mar 26 02:25:06 PM PDT 24
Finished	Mar 26 02:25:43 PM PDT 24
Peak memory	200120 kb
Host	smart-79266ab4-b589-4d83-b6bf-33e6a74e39b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31990682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.31990682
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.575025599
Short name	T622
Test name
Test status
Simulation time	34939896792 ps
CPU time	23.41 seconds
Started	Mar 26 02:25:01 PM PDT 24
Finished	Mar 26 02:25:26 PM PDT 24
Peak memory	200064 kb
Host	smart-70fd5968-b3fe-4ddd-9f49-e6a2fa55b312
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575025599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.575025599
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_intr.2448939933
Short name	T865
Test name
Test status
Simulation time	10713701865 ps
CPU time	2.12 seconds
Started	Mar 26 02:25:06 PM PDT 24
Finished	Mar 26 02:25:11 PM PDT 24
Peak memory	197856 kb
Host	smart-4a37833c-f829-4f13-9196-6790706da5da
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448939933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2448939933
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.679991298
Short name	T605
Test name
Test status
Simulation time	98313214639 ps
CPU time	221.98 seconds
Started	Mar 26 02:25:02 PM PDT 24
Finished	Mar 26 02:28:45 PM PDT 24
Peak memory	200080 kb
Host	smart-3373f726-9f89-45b9-a8b9-87ae8411a28e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=679991298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.679991298
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_loopback.1395070925
Short name	T876
Test name
Test status
Simulation time	7596083992 ps
CPU time	2.04 seconds
Started	Mar 26 02:25:00 PM PDT 24
Finished	Mar 26 02:25:03 PM PDT 24
Peak memory	199788 kb
Host	smart-941677be-4051-470b-829b-a0959593a2d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395070925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1395070925
Directory	/workspace/38.uart_loopback/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.3621347593
Short name	T396
Test name
Test status
Simulation time	12197835326 ps
CPU time	28.59 seconds
Started	Mar 26 02:25:01 PM PDT 24
Finished	Mar 26 02:25:29 PM PDT 24
Peak memory	198264 kb
Host	smart-9034e1c2-b11c-46c9-8ad1-0d84d35d4443
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621347593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3621347593
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.1299199736
Short name	T1095
Test name
Test status
Simulation time	21631453684 ps
CPU time	930.77 seconds
Started	Mar 26 02:25:02 PM PDT 24
Finished	Mar 26 02:40:34 PM PDT 24
Peak memory	200100 kb
Host	smart-e6f62b45-5a45-4704-98e0-e31b93fe884e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1299199736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1299199736
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_oversample.2034183645
Short name	T1100
Test name
Test status
Simulation time	2951882269 ps
CPU time	9.39 seconds
Started	Mar 26 02:25:07 PM PDT 24
Finished	Mar 26 02:25:18 PM PDT 24
Peak memory	199180 kb
Host	smart-ff1c754f-df35-4df5-a5d8-fc78ced480e0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2034183645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2034183645
Directory	/workspace/38.uart_rx_oversample/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.32832734
Short name	T154
Test name
Test status
Simulation time	119072118589 ps
CPU time	50.44 seconds
Started	Mar 26 02:25:07 PM PDT 24
Finished	Mar 26 02:25:59 PM PDT 24
Peak memory	200100 kb
Host	smart-d14cbc79-42e5-40a1-9b11-e15d917dcf2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32832734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.32832734
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.3079505493
Short name	T574
Test name
Test status
Simulation time	4433250194 ps
CPU time	4.3 seconds
Started	Mar 26 02:25:00 PM PDT 24
Finished	Mar 26 02:25:05 PM PDT 24
Peak memory	196228 kb
Host	smart-770b7e21-35c7-41a5-b1be-5b9adcb16080
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079505493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3079505493
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.2610359618
Short name	T629
Test name
Test status
Simulation time	634293791 ps
CPU time	1.79 seconds
Started	Mar 26 02:25:08 PM PDT 24
Finished	Mar 26 02:25:10 PM PDT 24
Peak memory	198340 kb
Host	smart-8668a041-15ec-4614-8f49-15b519c3347a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610359618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2610359618
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_stress_all.996569931
Short name	T621
Test name
Test status
Simulation time	14164991480 ps
CPU time	149.92 seconds
Started	Mar 26 02:25:02 PM PDT 24
Finished	Mar 26 02:27:33 PM PDT 24
Peak memory	200140 kb
Host	smart-3ea604b7-b5d6-4787-a505-78006d7faaa9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996569931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.996569931
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.975303252
Short name	T740
Test name
Test status
Simulation time	2405153760 ps
CPU time	2.31 seconds
Started	Mar 26 02:25:00 PM PDT 24
Finished	Mar 26 02:25:03 PM PDT 24
Peak memory	199568 kb
Host	smart-74622b46-c10f-417e-b9f4-69d3d0357df8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975303252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.975303252
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.3278826053
Short name	T552
Test name
Test status
Simulation time	10508334716 ps
CPU time	23.36 seconds
Started	Mar 26 02:25:05 PM PDT 24
Finished	Mar 26 02:25:32 PM PDT 24
Peak memory	200032 kb
Host	smart-d88a3340-8f11-49a8-8c8d-ab260aa27380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278826053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3278826053
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/default/39.uart_alert_test.511870755
Short name	T554
Test name
Test status
Simulation time	22795285 ps
CPU time	0.52 seconds
Started	Mar 26 02:25:17 PM PDT 24
Finished	Mar 26 02:25:18 PM PDT 24
Peak memory	195536 kb
Host	smart-41cadc9c-0ea4-4638-adee-03a073cab85f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511870755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.511870755
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.4206547502
Short name	T400
Test name
Test status
Simulation time	32609824720 ps
CPU time	57.06 seconds
Started	Mar 26 02:25:09 PM PDT 24
Finished	Mar 26 02:26:06 PM PDT 24
Peak memory	200116 kb
Host	smart-ee630003-6e81-4b5d-8dc0-fef885ae4727
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206547502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4206547502
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.2304169665
Short name	T118
Test name
Test status
Simulation time	20054607792 ps
CPU time	31.62 seconds
Started	Mar 26 02:25:11 PM PDT 24
Finished	Mar 26 02:25:44 PM PDT 24
Peak memory	199820 kb
Host	smart-ea5cfc8f-7306-4d42-984e-abb84b88f7c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304169665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2304169665
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.2721629824
Short name	T842
Test name
Test status
Simulation time	22584650525 ps
CPU time	37.23 seconds
Started	Mar 26 02:25:12 PM PDT 24
Finished	Mar 26 02:25:49 PM PDT 24
Peak memory	200116 kb
Host	smart-7ebf444a-dde1-4ec4-92ee-79ed82ac784b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721629824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2721629824
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.4114242861
Short name	T616
Test name
Test status
Simulation time	24968750712 ps
CPU time	13.99 seconds
Started	Mar 26 02:25:12 PM PDT 24
Finished	Mar 26 02:25:26 PM PDT 24
Peak memory	200104 kb
Host	smart-b9db6c22-87cd-4055-ada3-329740c202f2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114242861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4114242861
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.1161745113
Short name	T1062
Test name
Test status
Simulation time	127262966138 ps
CPU time	182.39 seconds
Started	Mar 26 02:25:09 PM PDT 24
Finished	Mar 26 02:28:13 PM PDT 24
Peak memory	200084 kb
Host	smart-c4e2b25c-2824-4811-baae-cfa7efdcd09f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1161745113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1161745113
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/39.uart_loopback.3431730731
Short name	T147
Test name
Test status
Simulation time	1840284969 ps
CPU time	0.97 seconds
Started	Mar 26 02:25:09 PM PDT 24
Finished	Mar 26 02:25:12 PM PDT 24
Peak memory	195608 kb
Host	smart-55bb36f8-9b8d-44f2-9e95-0d1b420ee644
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431730731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3431730731
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.3812704051
Short name	T599
Test name
Test status
Simulation time	83234648533 ps
CPU time	75.65 seconds
Started	Mar 26 02:25:11 PM PDT 24
Finished	Mar 26 02:26:27 PM PDT 24
Peak memory	200224 kb
Host	smart-a3601e78-5ac8-4c32-a4e8-903df37a93e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812704051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3812704051
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.408438585
Short name	T612
Test name
Test status
Simulation time	19681730384 ps
CPU time	552.32 seconds
Started	Mar 26 02:25:08 PM PDT 24
Finished	Mar 26 02:34:21 PM PDT 24
Peak memory	199984 kb
Host	smart-52a893da-4a7c-4d18-9a42-22ff25e857c2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=408438585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.408438585
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_oversample.2718613072
Short name	T609
Test name
Test status
Simulation time	1376791270 ps
CPU time	2.67 seconds
Started	Mar 26 02:25:08 PM PDT 24
Finished	Mar 26 02:25:11 PM PDT 24
Peak memory	196988 kb
Host	smart-b9403d35-0a71-4a67-89a3-3221a6e1883c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2718613072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2718613072
Directory	/workspace/39.uart_rx_oversample/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.1842652941
Short name	T1024
Test name
Test status
Simulation time	81399350125 ps
CPU time	183.21 seconds
Started	Mar 26 02:25:10 PM PDT 24
Finished	Mar 26 02:28:14 PM PDT 24
Peak memory	200108 kb
Host	smart-7906ca75-7a43-4b54-b5d8-66a0e6eb572a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842652941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1842652941
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.4185234787
Short name	T511
Test name
Test status
Simulation time	4279541436 ps
CPU time	3.9 seconds
Started	Mar 26 02:25:12 PM PDT 24
Finished	Mar 26 02:25:16 PM PDT 24
Peak memory	196128 kb
Host	smart-6a4aae3d-7b78-46b7-88bf-2a294b9fe97b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185234787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4185234787
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.2923890520
Short name	T344
Test name
Test status
Simulation time	459864561 ps
CPU time	2.09 seconds
Started	Mar 26 02:25:12 PM PDT 24
Finished	Mar 26 02:25:14 PM PDT 24
Peak memory	199564 kb
Host	smart-7a7ad1ac-6877-4f08-a790-16c92813516e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923890520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2923890520
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all.1153006516
Short name	T854
Test name
Test status
Simulation time	242099941043 ps
CPU time	527.67 seconds
Started	Mar 26 02:25:20 PM PDT 24
Finished	Mar 26 02:34:08 PM PDT 24
Peak memory	200044 kb
Host	smart-20404956-4944-4a76-8730-ee56085de424
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153006516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1153006516
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/39.uart_stress_all_with_rand_reset.641418494
Short name	T353
Test name
Test status
Simulation time	109694174253 ps
CPU time	477.67 seconds
Started	Mar 26 02:25:19 PM PDT 24
Finished	Mar 26 02:33:17 PM PDT 24
Peak memory	216088 kb
Host	smart-c9e04987-3293-4f20-84aa-00f66abc8256
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641418494 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.641418494
Directory	/workspace/39.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.3463876773
Short name	T502
Test name
Test status
Simulation time	594780633 ps
CPU time	1.37 seconds
Started	Mar 26 02:25:10 PM PDT 24
Finished	Mar 26 02:25:12 PM PDT 24
Peak memory	198816 kb
Host	smart-29696549-8c84-4458-b5d9-0c455f19ba4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3463876773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3463876773
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.661886270
Short name	T981
Test name
Test status
Simulation time	95780477231 ps
CPU time	53.3 seconds
Started	Mar 26 02:25:09 PM PDT 24
Finished	Mar 26 02:26:02 PM PDT 24
Peak memory	200080 kb
Host	smart-94a8395e-ef2d-40de-91dc-9d4e64e84b01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661886270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.661886270
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.2801167531
Short name	T587
Test name
Test status
Simulation time	13934796 ps
CPU time	0.57 seconds
Started	Mar 26 02:19:57 PM PDT 24
Finished	Mar 26 02:19:58 PM PDT 24
Peak memory	195508 kb
Host	smart-5dcf5f96-cb8a-46af-9feb-6a0543183541
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801167531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2801167531
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.2059878306
Short name	T975
Test name
Test status
Simulation time	250385970514 ps
CPU time	26.96 seconds
Started	Mar 26 02:19:41 PM PDT 24
Finished	Mar 26 02:20:08 PM PDT 24
Peak memory	199976 kb
Host	smart-0b6c6ff0-5a6c-4083-9b29-14e426ef6003
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059878306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2059878306
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.1181556024
Short name	T710
Test name
Test status
Simulation time	86339750055 ps
CPU time	130.85 seconds
Started	Mar 26 02:19:45 PM PDT 24
Finished	Mar 26 02:21:56 PM PDT 24
Peak memory	199924 kb
Host	smart-d1d31505-5c7f-496c-8179-44d7f549c05c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181556024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1181556024
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.2818202579
Short name	T665
Test name
Test status
Simulation time	120334374905 ps
CPU time	203.68 seconds
Started	Mar 26 02:19:44 PM PDT 24
Finished	Mar 26 02:23:08 PM PDT 24
Peak memory	200028 kb
Host	smart-634ac65e-0edf-4850-ae72-67de587f6061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818202579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2818202579
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_intr.3628225434
Short name	T930
Test name
Test status
Simulation time	14362618838 ps
CPU time	2.86 seconds
Started	Mar 26 02:19:41 PM PDT 24
Finished	Mar 26 02:19:44 PM PDT 24
Peak memory	198960 kb
Host	smart-edbcd4f0-6035-48ff-8ed7-c862f8fcda17
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628225434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3628225434
Directory	/workspace/4.uart_intr/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.3783883255
Short name	T1016
Test name
Test status
Simulation time	161049703440 ps
CPU time	406.74 seconds
Started	Mar 26 02:19:58 PM PDT 24
Finished	Mar 26 02:26:44 PM PDT 24
Peak memory	200092 kb
Host	smart-835856d2-317a-46ed-9435-3410b547282c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3783883255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3783883255
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.4169289149
Short name	T578
Test name
Test status
Simulation time	4417352816 ps
CPU time	3.32 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:20:00 PM PDT 24
Peak memory	198804 kb
Host	smart-d1470724-e030-4bb2-b918-f8837d31b649
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169289149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4169289149
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.2179129030
Short name	T90
Test name
Test status
Simulation time	82106916774 ps
CPU time	37.2 seconds
Started	Mar 26 02:19:44 PM PDT 24
Finished	Mar 26 02:20:21 PM PDT 24
Peak memory	199216 kb
Host	smart-a2019ae2-b129-4a6a-a5ab-2bef0e0cda60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179129030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2179129030
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.4137854445
Short name	T331
Test name
Test status
Simulation time	21098243416 ps
CPU time	851.17 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:34:08 PM PDT 24
Peak memory	200264 kb
Host	smart-a856eb57-1bf8-4e48-9832-595db9f6955b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4137854445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4137854445
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_oversample.3106742479
Short name	T1116
Test name
Test status
Simulation time	6644641830 ps
CPU time	14.29 seconds
Started	Mar 26 02:19:43 PM PDT 24
Finished	Mar 26 02:19:57 PM PDT 24
Peak memory	198204 kb
Host	smart-eda527e8-0c54-47da-9e46-c5a87da0380f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3106742479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3106742479
Directory	/workspace/4.uart_rx_oversample/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.3646120858
Short name	T117
Test name
Test status
Simulation time	4097367965 ps
CPU time	7.81 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:20:03 PM PDT 24
Peak memory	196200 kb
Host	smart-7468e867-6e31-4158-8d16-ac33cef8bf01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646120858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3646120858
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.937778096
Short name	T34
Test name
Test status
Simulation time	84740536 ps
CPU time	0.8 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:19:57 PM PDT 24
Peak memory	218596 kb
Host	smart-b652289f-5991-4556-8575-619bac6052fa
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937778096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.937778096
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/4.uart_smoke.959676708
Short name	T884
Test name
Test status
Simulation time	443202924 ps
CPU time	1.81 seconds
Started	Mar 26 02:19:44 PM PDT 24
Finished	Mar 26 02:19:46 PM PDT 24
Peak memory	198336 kb
Host	smart-d7ba0993-4409-4f1c-8d53-f4217f20e365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959676708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.959676708
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.3749832608
Short name	T1031
Test name
Test status
Simulation time	115375641118 ps
CPU time	379.39 seconds
Started	Mar 26 02:19:54 PM PDT 24
Finished	Mar 26 02:26:14 PM PDT 24
Peak memory	200056 kb
Host	smart-26a0ca77-2e8f-4fef-98ae-5111e8a9920e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749832608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3749832608
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.2847417147
Short name	T871
Test name
Test status
Simulation time	1861600191 ps
CPU time	2.03 seconds
Started	Mar 26 02:19:54 PM PDT 24
Finished	Mar 26 02:19:57 PM PDT 24
Peak memory	198580 kb
Host	smart-d1dcd848-4a95-4465-b628-e8f48f5d8987
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847417147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2847417147
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.807932532
Short name	T522
Test name
Test status
Simulation time	143461834792 ps
CPU time	177.72 seconds
Started	Mar 26 02:19:41 PM PDT 24
Finished	Mar 26 02:22:39 PM PDT 24
Peak memory	200036 kb
Host	smart-1df6bb71-d8df-4303-9e22-6e7695e36045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807932532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.807932532
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.1774791298
Short name	T706
Test name
Test status
Simulation time	35861432 ps
CPU time	0.57 seconds
Started	Mar 26 02:25:29 PM PDT 24
Finished	Mar 26 02:25:32 PM PDT 24
Peak memory	195524 kb
Host	smart-ffec8673-f5db-470f-be26-9935a3c911ed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774791298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1774791298
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.3486778912
Short name	T915
Test name
Test status
Simulation time	35934523494 ps
CPU time	76.57 seconds
Started	Mar 26 02:25:18 PM PDT 24
Finished	Mar 26 02:26:35 PM PDT 24
Peak memory	199996 kb
Host	smart-3932426d-5fb0-4b57-8e94-7d8b0f01da25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486778912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3486778912
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.799417155
Short name	T698
Test name
Test status
Simulation time	75068844996 ps
CPU time	116.97 seconds
Started	Mar 26 02:25:18 PM PDT 24
Finished	Mar 26 02:27:15 PM PDT 24
Peak memory	199960 kb
Host	smart-aabcb119-f747-40e8-acf7-74576d950d5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799417155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.799417155
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.3893833607
Short name	T364
Test name
Test status
Simulation time	128019515100 ps
CPU time	47.57 seconds
Started	Mar 26 02:25:19 PM PDT 24
Finished	Mar 26 02:26:06 PM PDT 24
Peak memory	200084 kb
Host	smart-26607730-d601-4388-b663-e4d9604ac6e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893833607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3893833607
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.1020811586
Short name	T275
Test name
Test status
Simulation time	8435587371 ps
CPU time	11.19 seconds
Started	Mar 26 02:25:28 PM PDT 24
Finished	Mar 26 02:25:41 PM PDT 24
Peak memory	199956 kb
Host	smart-0c6d567b-f28c-4dc9-af31-37d9376e5854
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020811586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1020811586
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.407871686
Short name	T837
Test name
Test status
Simulation time	55979528555 ps
CPU time	400.94 seconds
Started	Mar 26 02:25:30 PM PDT 24
Finished	Mar 26 02:32:13 PM PDT 24
Peak memory	200024 kb
Host	smart-9e856dba-1db8-4fd3-88c8-2251423f85bf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=407871686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.407871686
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.3580006911
Short name	T675
Test name
Test status
Simulation time	1932857115 ps
CPU time	1.42 seconds
Started	Mar 26 02:25:27 PM PDT 24
Finished	Mar 26 02:25:30 PM PDT 24
Peak memory	195632 kb
Host	smart-c7ca0f1b-fd26-4098-866e-8dffb6607d99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580006911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3580006911
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.1079133597
Short name	T743
Test name
Test status
Simulation time	355543215337 ps
CPU time	55.13 seconds
Started	Mar 26 02:25:28 PM PDT 24
Finished	Mar 26 02:26:25 PM PDT 24
Peak memory	200224 kb
Host	smart-661759ee-4c42-4c2a-b982-301975bf45be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079133597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1079133597
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.870818132
Short name	T53
Test name
Test status
Simulation time	7606876113 ps
CPU time	43.87 seconds
Started	Mar 26 02:25:27 PM PDT 24
Finished	Mar 26 02:26:12 PM PDT 24
Peak memory	200092 kb
Host	smart-32185b1b-1581-461d-bcf4-a08bea848b6b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=870818132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.870818132
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.2334718867
Short name	T1102
Test name
Test status
Simulation time	6154482968 ps
CPU time	51.93 seconds
Started	Mar 26 02:25:27 PM PDT 24
Finished	Mar 26 02:26:21 PM PDT 24
Peak memory	199236 kb
Host	smart-18c447d0-9123-43b8-992f-305dfdf69072
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2334718867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2334718867
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.3241993206
Short name	T11
Test name
Test status
Simulation time	43327104237 ps
CPU time	40.46 seconds
Started	Mar 26 02:25:27 PM PDT 24
Finished	Mar 26 02:26:09 PM PDT 24
Peak memory	200132 kb
Host	smart-3ff3cf8f-5cfc-4afb-bda1-05f80ce182a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241993206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3241993206
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.3665629616
Short name	T800
Test name
Test status
Simulation time	4015414098 ps
CPU time	4.22 seconds
Started	Mar 26 02:25:27 PM PDT 24
Finished	Mar 26 02:25:33 PM PDT 24
Peak memory	196048 kb
Host	smart-ba28bd63-15eb-4db6-a4c2-868bd3db4882
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665629616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3665629616
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.3901963575
Short name	T316
Test name
Test status
Simulation time	623910564 ps
CPU time	2.33 seconds
Started	Mar 26 02:25:19 PM PDT 24
Finished	Mar 26 02:25:21 PM PDT 24
Peak memory	198504 kb
Host	smart-5ea4921e-aae8-43e3-a6ee-db83b1d7f574
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3901963575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3901963575
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.3806005081
Short name	T433
Test name
Test status
Simulation time	140456014631 ps
CPU time	1030.59 seconds
Started	Mar 26 02:25:29 PM PDT 24
Finished	Mar 26 02:42:42 PM PDT 24
Peak memory	200152 kb
Host	smart-8de91205-b7a4-41f7-944b-de9be9a89f44
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806005081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3806005081
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.1093774171
Short name	T666
Test name
Test status
Simulation time	1150712239 ps
CPU time	2.26 seconds
Started	Mar 26 02:25:28 PM PDT 24
Finished	Mar 26 02:25:32 PM PDT 24
Peak memory	198424 kb
Host	smart-68a729d8-830c-42cb-ae27-e1093c52322f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093774171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1093774171
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.104444611
Short name	T776
Test name
Test status
Simulation time	49507630439 ps
CPU time	82.21 seconds
Started	Mar 26 02:25:17 PM PDT 24
Finished	Mar 26 02:26:40 PM PDT 24
Peak memory	200036 kb
Host	smart-a787e4f2-d958-436c-b339-be310867ebbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104444611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.104444611
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.104076681
Short name	T535
Test name
Test status
Simulation time	29728195 ps
CPU time	0.54 seconds
Started	Mar 26 02:25:36 PM PDT 24
Finished	Mar 26 02:25:38 PM PDT 24
Peak memory	194564 kb
Host	smart-43003e8a-6280-4ea2-84c0-b9f8eceb96ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104076681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.104076681
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.78156012
Short name	T180
Test name
Test status
Simulation time	182324509980 ps
CPU time	151.31 seconds
Started	Mar 26 02:25:28 PM PDT 24
Finished	Mar 26 02:28:02 PM PDT 24
Peak memory	200140 kb
Host	smart-632c4f53-d705-4c30-ab3c-6632dc9b0bf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78156012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.78156012
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.1067760109
Short name	T546
Test name
Test status
Simulation time	20461306649 ps
CPU time	32.46 seconds
Started	Mar 26 02:25:29 PM PDT 24
Finished	Mar 26 02:26:04 PM PDT 24
Peak memory	200152 kb
Host	smart-9813014c-6696-44cc-8720-4104ce7c4eb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067760109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1067760109
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_intr.634694106
Short name	T399
Test name
Test status
Simulation time	10377881003 ps
CPU time	9.66 seconds
Started	Mar 26 02:25:29 PM PDT 24
Finished	Mar 26 02:25:41 PM PDT 24
Peak memory	200100 kb
Host	smart-178808c7-efe0-41c5-a135-a3fb5673864c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634694106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.634694106
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_long_xfer_wo_dly.3470700017
Short name	T51
Test name
Test status
Simulation time	135195511147 ps
CPU time	367.54 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:31:45 PM PDT 24
Peak memory	199960 kb
Host	smart-58d7bcab-988a-48eb-8144-3d003c178f96
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3470700017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3470700017
Directory	/workspace/41.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/41.uart_loopback.3828535656
Short name	T423
Test name
Test status
Simulation time	8672691392 ps
CPU time	15.49 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:25:53 PM PDT 24
Peak memory	199892 kb
Host	smart-796e4671-112e-4df9-ad78-822d0d7193d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828535656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3828535656
Directory	/workspace/41.uart_loopback/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.2660886704
Short name	T401
Test name
Test status
Simulation time	21415021947 ps
CPU time	18.36 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:25:56 PM PDT 24
Peak memory	198716 kb
Host	smart-acbac0e1-bb22-4f6c-8c71-639a88215845
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660886704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2660886704
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.3431552800
Short name	T1092
Test name
Test status
Simulation time	22011747111 ps
CPU time	259.7 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:29:57 PM PDT 24
Peak memory	200084 kb
Host	smart-ab0670ab-566f-4800-bc4c-5783e5cc952f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3431552800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3431552800
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.1603547623
Short name	T467
Test name
Test status
Simulation time	1657629308 ps
CPU time	8.1 seconds
Started	Mar 26 02:25:29 PM PDT 24
Finished	Mar 26 02:25:40 PM PDT 24
Peak memory	197960 kb
Host	smart-f94d9ed0-be14-4a1d-a3a9-92011224e948
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1603547623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1603547623
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.3322157909
Short name	T891
Test name
Test status
Simulation time	60444460109 ps
CPU time	83.48 seconds
Started	Mar 26 02:25:38 PM PDT 24
Finished	Mar 26 02:27:02 PM PDT 24
Peak memory	200016 kb
Host	smart-3085d06a-71d2-46d2-bd49-3ba187594eae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322157909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3322157909
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.277932541
Short name	T481
Test name
Test status
Simulation time	28920023202 ps
CPU time	25.44 seconds
Started	Mar 26 02:25:36 PM PDT 24
Finished	Mar 26 02:26:03 PM PDT 24
Peak memory	196484 kb
Host	smart-b9564a1d-4d39-4776-9e43-aeb1cc691e54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277932541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.277932541
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.3690587427
Short name	T654
Test name
Test status
Simulation time	99044128 ps
CPU time	0.95 seconds
Started	Mar 26 02:25:28 PM PDT 24
Finished	Mar 26 02:25:31 PM PDT 24
Peak memory	197852 kb
Host	smart-da7821ca-f07d-4200-ac1e-8fbfd1ea2482
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3690587427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3690587427
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.3595937277
Short name	T313
Test name
Test status
Simulation time	518085884337 ps
CPU time	184.64 seconds
Started	Mar 26 02:25:38 PM PDT 24
Finished	Mar 26 02:28:43 PM PDT 24
Peak memory	208508 kb
Host	smart-e8bcab57-1f2c-4080-8bb9-5f39c46f2caa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595937277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3595937277
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.579379685
Short name	T1034
Test name
Test status
Simulation time	1059070053 ps
CPU time	2.39 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:25:40 PM PDT 24
Peak memory	198784 kb
Host	smart-ea2cfdf6-7f69-4da8-9400-a4f5c0570b4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579379685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.579379685
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.977692868
Short name	T345
Test name
Test status
Simulation time	40440785703 ps
CPU time	28.11 seconds
Started	Mar 26 02:25:28 PM PDT 24
Finished	Mar 26 02:25:57 PM PDT 24
Peak memory	200064 kb
Host	smart-29e99fe6-26dd-4e21-8c46-f12cf82f8a9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977692868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.977692868
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.4123741015
Short name	T555
Test name
Test status
Simulation time	65263417 ps
CPU time	0.58 seconds
Started	Mar 26 02:25:46 PM PDT 24
Finished	Mar 26 02:25:47 PM PDT 24
Peak memory	195544 kb
Host	smart-4e2439d6-456f-42b0-8a37-4469dcc7f50f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123741015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4123741015
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.3944952790
Short name	T936
Test name
Test status
Simulation time	94379910259 ps
CPU time	159.75 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:28:18 PM PDT 24
Peak memory	200048 kb
Host	smart-05c42f22-6294-44ba-9d12-56bb9f562513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944952790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3944952790
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.145062083
Short name	T278
Test name
Test status
Simulation time	43379327356 ps
CPU time	32.72 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:26:11 PM PDT 24
Peak memory	200052 kb
Host	smart-eefa6fac-05bb-4367-908f-abcc36bbfbac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145062083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.145062083
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.2069295941
Short name	T365
Test name
Test status
Simulation time	31296519164 ps
CPU time	19.1 seconds
Started	Mar 26 02:25:39 PM PDT 24
Finished	Mar 26 02:25:58 PM PDT 24
Peak memory	199184 kb
Host	smart-777323f1-56e1-468a-8848-fd5d7d8fb780
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069295941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2069295941
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_intr.3882706063
Short name	T919
Test name
Test status
Simulation time	172971591098 ps
CPU time	156.95 seconds
Started	Mar 26 02:25:38 PM PDT 24
Finished	Mar 26 02:28:15 PM PDT 24
Peak memory	200132 kb
Host	smart-2c809735-aaf5-4287-b143-96aa01371e6a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882706063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3882706063
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.4094269278
Short name	T912
Test name
Test status
Simulation time	124535187263 ps
CPU time	712.84 seconds
Started	Mar 26 02:25:48 PM PDT 24
Finished	Mar 26 02:37:41 PM PDT 24
Peak memory	200040 kb
Host	smart-5875193e-554e-422f-86d9-b90669fa9e9c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4094269278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4094269278
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.3618334256
Short name	T148
Test name
Test status
Simulation time	6151333435 ps
CPU time	4.6 seconds
Started	Mar 26 02:25:47 PM PDT 24
Finished	Mar 26 02:25:51 PM PDT 24
Peak memory	199668 kb
Host	smart-3975c080-4bc2-4d53-89b5-25436b00e947
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618334256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3618334256
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.2205076241
Short name	T750
Test name
Test status
Simulation time	70973380809 ps
CPU time	75.76 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:26:53 PM PDT 24
Peak memory	200172 kb
Host	smart-b3296900-5aef-4412-96d2-f8088544c973
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205076241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2205076241
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_perf.3360818079
Short name	T577
Test name
Test status
Simulation time	17283339274 ps
CPU time	476.21 seconds
Started	Mar 26 02:25:46 PM PDT 24
Finished	Mar 26 02:33:43 PM PDT 24
Peak memory	200056 kb
Host	smart-3dda9167-ff71-4f51-930c-4d3f551cf3da
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3360818079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3360818079
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.839438846
Short name	T985
Test name
Test status
Simulation time	6548880482 ps
CPU time	15.75 seconds
Started	Mar 26 02:25:36 PM PDT 24
Finished	Mar 26 02:25:53 PM PDT 24
Peak memory	198236 kb
Host	smart-29c5475c-5e7d-4f18-a94f-d58246ed9ac3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=839438846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.839438846
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.1668347131
Short name	T19
Test name
Test status
Simulation time	169449572208 ps
CPU time	203.19 seconds
Started	Mar 26 02:25:38 PM PDT 24
Finished	Mar 26 02:29:01 PM PDT 24
Peak memory	200140 kb
Host	smart-cc84a62a-ffe2-422c-81a7-295ade5e6039
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668347131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1668347131
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.2745405310
Short name	T32
Test name
Test status
Simulation time	7245929087 ps
CPU time	3.26 seconds
Started	Mar 26 02:25:39 PM PDT 24
Finished	Mar 26 02:25:42 PM PDT 24
Peak memory	195636 kb
Host	smart-d33c1fcd-4343-4137-a218-4bb1178edc95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745405310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2745405310
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.2793885814
Short name	T896
Test name
Test status
Simulation time	522439677 ps
CPU time	1.46 seconds
Started	Mar 26 02:25:37 PM PDT 24
Finished	Mar 26 02:25:39 PM PDT 24
Peak memory	198712 kb
Host	smart-1a002820-9daa-474f-9d4f-f9fefaab1387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793885814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2793885814
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_stress_all.70980472
Short name	T944
Test name
Test status
Simulation time	137693082607 ps
CPU time	143.67 seconds
Started	Mar 26 02:25:47 PM PDT 24
Finished	Mar 26 02:28:10 PM PDT 24
Peak memory	200072 kb
Host	smart-a95064c8-243a-4d38-911b-b420b5b6614e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70980472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.70980472
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.3730495043
Short name	T1025
Test name
Test status
Simulation time	822558937 ps
CPU time	3.31 seconds
Started	Mar 26 02:25:45 PM PDT 24
Finished	Mar 26 02:25:49 PM PDT 24
Peak memory	199100 kb
Host	smart-3f55b8ba-bbb6-4909-b2ce-99385cc188f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730495043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3730495043
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.1718726321
Short name	T926
Test name
Test status
Simulation time	40162464763 ps
CPU time	13.84 seconds
Started	Mar 26 02:25:36 PM PDT 24
Finished	Mar 26 02:25:52 PM PDT 24
Peak memory	199856 kb
Host	smart-c1cdb0e6-39b9-4b7f-8d4c-eb2a8dc27125
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718726321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1718726321
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.1497955377
Short name	T779
Test name
Test status
Simulation time	13401031 ps
CPU time	0.56 seconds
Started	Mar 26 02:25:55 PM PDT 24
Finished	Mar 26 02:25:55 PM PDT 24
Peak memory	195024 kb
Host	smart-9cc48e25-9c33-40d9-9754-a5e3973df16c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497955377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1497955377
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.4288064071
Short name	T435
Test name
Test status
Simulation time	74325998744 ps
CPU time	29.33 seconds
Started	Mar 26 02:25:47 PM PDT 24
Finished	Mar 26 02:26:16 PM PDT 24
Peak memory	200044 kb
Host	smart-0b434aa5-69fb-43a3-81d4-653d2592ac84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288064071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4288064071
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.3534132166
Short name	T687
Test name
Test status
Simulation time	118986953856 ps
CPU time	11.09 seconds
Started	Mar 26 02:25:48 PM PDT 24
Finished	Mar 26 02:25:59 PM PDT 24
Peak memory	199948 kb
Host	smart-1d3d41b9-ffbd-481c-b295-7bb7c5792b68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534132166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3534132166
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.324090909
Short name	T200
Test name
Test status
Simulation time	83514231760 ps
CPU time	62.12 seconds
Started	Mar 26 02:25:47 PM PDT 24
Finished	Mar 26 02:26:49 PM PDT 24
Peak memory	200036 kb
Host	smart-9de9fbf6-8af9-4d3d-8129-4befed326b54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324090909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.324090909
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.1982354371
Short name	T156
Test name
Test status
Simulation time	45379276898 ps
CPU time	21.79 seconds
Started	Mar 26 02:26:01 PM PDT 24
Finished	Mar 26 02:26:22 PM PDT 24
Peak memory	200008 kb
Host	smart-e914eaa4-5187-4446-8dff-ded03c32a237
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982354371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1982354371
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.245579685
Short name	T941
Test name
Test status
Simulation time	37717649028 ps
CPU time	130.58 seconds
Started	Mar 26 02:25:54 PM PDT 24
Finished	Mar 26 02:28:05 PM PDT 24
Peak memory	200096 kb
Host	smart-020a8d7d-8111-4ae5-a0ca-fb104a470bc0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=245579685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.245579685
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_loopback.2909524671
Short name	T461
Test name
Test status
Simulation time	3148556356 ps
CPU time	7.69 seconds
Started	Mar 26 02:26:01 PM PDT 24
Finished	Mar 26 02:26:09 PM PDT 24
Peak memory	198752 kb
Host	smart-72352cda-7a40-442d-a37a-f8b7a1cd090b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909524671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2909524671
Directory	/workspace/43.uart_loopback/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.1783526434
Short name	T1057
Test name
Test status
Simulation time	60494725986 ps
CPU time	107.92 seconds
Started	Mar 26 02:26:02 PM PDT 24
Finished	Mar 26 02:27:50 PM PDT 24
Peak memory	215960 kb
Host	smart-6361bb1c-19a9-4535-82a8-f60ac0c2aadd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783526434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1783526434
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.3526974569
Short name	T447
Test name
Test status
Simulation time	14492905074 ps
CPU time	347.36 seconds
Started	Mar 26 02:25:55 PM PDT 24
Finished	Mar 26 02:31:42 PM PDT 24
Peak memory	200008 kb
Host	smart-f3685341-a08a-4a6c-b709-bc46a616d994
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3526974569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3526974569
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.2853219562
Short name	T707
Test name
Test status
Simulation time	1600937913 ps
CPU time	4.8 seconds
Started	Mar 26 02:25:47 PM PDT 24
Finished	Mar 26 02:25:52 PM PDT 24
Peak memory	197964 kb
Host	smart-a640a621-bd65-47da-bc49-ed1f06f1e7a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2853219562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2853219562
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.3256660365
Short name	T646
Test name
Test status
Simulation time	43046752138 ps
CPU time	35.94 seconds
Started	Mar 26 02:26:03 PM PDT 24
Finished	Mar 26 02:26:40 PM PDT 24
Peak memory	200124 kb
Host	smart-1aad2b62-e965-4027-912c-870e84079281
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3256660365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3256660365
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.4079875555
Short name	T410
Test name
Test status
Simulation time	671073896 ps
CPU time	1.78 seconds
Started	Mar 26 02:26:01 PM PDT 24
Finished	Mar 26 02:26:03 PM PDT 24
Peak memory	195460 kb
Host	smart-0758211d-5f0b-4f26-8f00-39ba697fe780
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079875555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4079875555
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.1451679249
Short name	T1075
Test name
Test status
Simulation time	462538210 ps
CPU time	1.58 seconds
Started	Mar 26 02:25:47 PM PDT 24
Finished	Mar 26 02:25:49 PM PDT 24
Peak memory	198440 kb
Host	smart-861c4260-8ebf-49ee-bf97-ed742179b1b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451679249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1451679249
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_stress_all.3223899234
Short name	T978
Test name
Test status
Simulation time	204428365664 ps
CPU time	122.49 seconds
Started	Mar 26 02:25:59 PM PDT 24
Finished	Mar 26 02:28:02 PM PDT 24
Peak memory	200012 kb
Host	smart-954c40b2-e61a-481e-9843-c985b67beac7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223899234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3223899234
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.795877697
Short name	T826
Test name
Test status
Simulation time	2006009821 ps
CPU time	2.46 seconds
Started	Mar 26 02:25:55 PM PDT 24
Finished	Mar 26 02:25:58 PM PDT 24
Peak memory	198776 kb
Host	smart-db096a67-9116-49f8-af04-8acfe5602c3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795877697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.795877697
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/43.uart_tx_rx.490290431
Short name	T795
Test name
Test status
Simulation time	96055695054 ps
CPU time	63.42 seconds
Started	Mar 26 02:25:48 PM PDT 24
Finished	Mar 26 02:26:51 PM PDT 24
Peak memory	200060 kb
Host	smart-e5351747-3460-48c0-83d1-c4717b7a11df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490290431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.490290431
Directory	/workspace/43.uart_tx_rx/latest

Test location	/workspace/coverage/default/44.uart_alert_test.1126406119
Short name	T668
Test name
Test status
Simulation time	14172497 ps
CPU time	0.57 seconds
Started	Mar 26 02:26:06 PM PDT 24
Finished	Mar 26 02:26:06 PM PDT 24
Peak memory	195464 kb
Host	smart-718f0d76-8ab0-48b7-b084-2099b70708ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126406119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1126406119
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.1456655841
Short name	T173
Test name
Test status
Simulation time	220504898278 ps
CPU time	894.98 seconds
Started	Mar 26 02:26:02 PM PDT 24
Finished	Mar 26 02:40:57 PM PDT 24
Peak memory	200052 kb
Host	smart-4fa44237-d499-4390-bd77-8f02b457366f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456655841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1456655841
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.617549351
Short name	T359
Test name
Test status
Simulation time	138688206682 ps
CPU time	25.25 seconds
Started	Mar 26 02:25:54 PM PDT 24
Finished	Mar 26 02:26:20 PM PDT 24
Peak memory	199996 kb
Host	smart-4f02c500-1e8a-482c-a00d-290685e8749d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617549351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.617549351
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.3005604887
Short name	T660
Test name
Test status
Simulation time	35776834090 ps
CPU time	70.92 seconds
Started	Mar 26 02:26:01 PM PDT 24
Finished	Mar 26 02:27:12 PM PDT 24
Peak memory	200096 kb
Host	smart-f517d6a4-6933-4078-89d3-bb21f6f6d4b4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005604887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3005604887
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.1341397556
Short name	T303
Test name
Test status
Simulation time	59629965634 ps
CPU time	169.85 seconds
Started	Mar 26 02:26:06 PM PDT 24
Finished	Mar 26 02:28:56 PM PDT 24
Peak memory	200052 kb
Host	smart-965df6f6-6913-41f0-b356-8212abb49e21
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1341397556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1341397556
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_loopback.81761764
Short name	T636
Test name
Test status
Simulation time	8963900939 ps
CPU time	16.52 seconds
Started	Mar 26 02:26:05 PM PDT 24
Finished	Mar 26 02:26:22 PM PDT 24
Peak memory	200032 kb
Host	smart-41cae513-e5f3-42d1-bcc2-1c1876879735
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81761764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.81761764
Directory	/workspace/44.uart_loopback/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.1543158443
Short name	T298
Test name
Test status
Simulation time	8628409598 ps
CPU time	15.52 seconds
Started	Mar 26 02:26:01 PM PDT 24
Finished	Mar 26 02:26:16 PM PDT 24
Peak memory	197072 kb
Host	smart-2f035ab1-44e2-4fbb-9958-a865be953dee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543158443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1543158443
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.3106986281
Short name	T914
Test name
Test status
Simulation time	7356316649 ps
CPU time	98.38 seconds
Started	Mar 26 02:26:06 PM PDT 24
Finished	Mar 26 02:27:45 PM PDT 24
Peak memory	199960 kb
Host	smart-b682da16-ed89-460d-b464-f59ad8c9549a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3106986281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3106986281
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.697437899
Short name	T1026
Test name
Test status
Simulation time	6212115743 ps
CPU time	13.59 seconds
Started	Mar 26 02:25:58 PM PDT 24
Finished	Mar 26 02:26:12 PM PDT 24
Peak memory	197944 kb
Host	smart-9f192838-7221-482d-9479-ad520769f3f1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=697437899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.697437899
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.2479448529
Short name	T1056
Test name
Test status
Simulation time	180120560319 ps
CPU time	126.58 seconds
Started	Mar 26 02:26:05 PM PDT 24
Finished	Mar 26 02:28:11 PM PDT 24
Peak memory	199784 kb
Host	smart-307bfd71-9503-4901-a38d-982e5d9dba02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479448529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2479448529
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.1631128573
Short name	T659
Test name
Test status
Simulation time	1572938387 ps
CPU time	3.39 seconds
Started	Mar 26 02:26:01 PM PDT 24
Finished	Mar 26 02:26:05 PM PDT 24
Peak memory	195464 kb
Host	smart-fcd62a5f-7ac8-4482-acdd-43186319898b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631128573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1631128573
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.4062559296
Short name	T712
Test name
Test status
Simulation time	649638017 ps
CPU time	2.81 seconds
Started	Mar 26 02:25:55 PM PDT 24
Finished	Mar 26 02:25:58 PM PDT 24
Peak memory	199764 kb
Host	smart-9d7db947-f9a9-419b-8f4d-a677be9416bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062559296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4062559296
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_stress_all.2771155143
Short name	T419
Test name
Test status
Simulation time	250948567611 ps
CPU time	695.07 seconds
Started	Mar 26 02:26:04 PM PDT 24
Finished	Mar 26 02:37:40 PM PDT 24
Peak memory	200260 kb
Host	smart-e14f79ab-ba6b-456f-898c-f53093e37f89
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771155143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2771155143
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.2274570621
Short name	T788
Test name
Test status
Simulation time	1654856388 ps
CPU time	1.46 seconds
Started	Mar 26 02:26:04 PM PDT 24
Finished	Mar 26 02:26:06 PM PDT 24
Peak memory	197536 kb
Host	smart-77638ed3-a162-4615-b758-e62da57da0de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274570621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2274570621
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.257143351
Short name	T699
Test name
Test status
Simulation time	139126430691 ps
CPU time	61.14 seconds
Started	Mar 26 02:26:01 PM PDT 24
Finished	Mar 26 02:27:03 PM PDT 24
Peak memory	200060 kb
Host	smart-13094670-bde4-441f-9f2a-18cd6a9bba09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257143351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.257143351
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.1739905503
Short name	T727
Test name
Test status
Simulation time	43131998 ps
CPU time	0.54 seconds
Started	Mar 26 02:26:13 PM PDT 24
Finished	Mar 26 02:26:13 PM PDT 24
Peak memory	194920 kb
Host	smart-e43e8075-4b9d-425c-a836-5e9e820d4609
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739905503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1739905503
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.524921170
Short name	T1021
Test name
Test status
Simulation time	27776170924 ps
CPU time	48.18 seconds
Started	Mar 26 02:26:05 PM PDT 24
Finished	Mar 26 02:26:53 PM PDT 24
Peak memory	200060 kb
Host	smart-15ba2aea-3421-4a1e-90c7-88e5936a2519
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524921170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.524921170
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.2323612418
Short name	T1125
Test name
Test status
Simulation time	91798879392 ps
CPU time	147.67 seconds
Started	Mar 26 02:26:04 PM PDT 24
Finished	Mar 26 02:28:32 PM PDT 24
Peak memory	200068 kb
Host	smart-00302906-4eb0-41ee-a98e-b6644f180678
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323612418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2323612418
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.2152906544
Short name	T900
Test name
Test status
Simulation time	65019704807 ps
CPU time	113.76 seconds
Started	Mar 26 02:26:05 PM PDT 24
Finished	Mar 26 02:27:59 PM PDT 24
Peak memory	200108 kb
Host	smart-659561d5-9b24-4712-82ef-828ff72434d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152906544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2152906544
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/45.uart_intr.963247475
Short name	T997
Test name
Test status
Simulation time	232219895419 ps
CPU time	105.38 seconds
Started	Mar 26 02:26:13 PM PDT 24
Finished	Mar 26 02:27:59 PM PDT 24
Peak memory	199996 kb
Host	smart-aa7ff595-ca60-4ec2-a0db-8d12caab1577
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963247475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.963247475
Directory	/workspace/45.uart_intr/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.3938755419
Short name	T290
Test name
Test status
Simulation time	70809349743 ps
CPU time	442.73 seconds
Started	Mar 26 02:26:14 PM PDT 24
Finished	Mar 26 02:33:37 PM PDT 24
Peak memory	200056 kb
Host	smart-46276809-b097-46bc-ab91-65a18fdab879
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3938755419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3938755419
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.1639476534
Short name	T391
Test name
Test status
Simulation time	13241491447 ps
CPU time	4.93 seconds
Started	Mar 26 02:26:13 PM PDT 24
Finished	Mar 26 02:26:18 PM PDT 24
Peak memory	200060 kb
Host	smart-b0c2b8a2-8762-4b32-a002-db999ee4d55e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639476534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1639476534
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.1722325563
Short name	T318
Test name
Test status
Simulation time	144296764859 ps
CPU time	55.52 seconds
Started	Mar 26 02:26:14 PM PDT 24
Finished	Mar 26 02:27:09 PM PDT 24
Peak memory	208320 kb
Host	smart-1d8fc0ef-ed02-40f1-8f8d-315aebf76040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722325563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1722325563
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.4197287400
Short name	T521
Test name
Test status
Simulation time	10778236305 ps
CPU time	293.79 seconds
Started	Mar 26 02:26:14 PM PDT 24
Finished	Mar 26 02:31:08 PM PDT 24
Peak memory	200044 kb
Host	smart-3074a68e-2037-4925-8928-348642a3763f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4197287400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4197287400
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_oversample.4079247588
Short name	T728
Test name
Test status
Simulation time	7875466060 ps
CPU time	15.58 seconds
Started	Mar 26 02:26:15 PM PDT 24
Finished	Mar 26 02:26:31 PM PDT 24
Peak memory	198224 kb
Host	smart-feea3837-6147-4be6-b293-8be5b77cd06c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4079247588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4079247588
Directory	/workspace/45.uart_rx_oversample/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.3451408074
Short name	T582
Test name
Test status
Simulation time	45470304006 ps
CPU time	41.14 seconds
Started	Mar 26 02:26:14 PM PDT 24
Finished	Mar 26 02:26:55 PM PDT 24
Peak memory	200052 kb
Host	smart-0d993b04-93df-4efe-bc39-dd0f3fe9d543
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451408074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3451408074
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.3108368815
Short name	T790
Test name
Test status
Simulation time	38412921348 ps
CPU time	31.27 seconds
Started	Mar 26 02:26:15 PM PDT 24
Finished	Mar 26 02:26:46 PM PDT 24
Peak memory	196184 kb
Host	smart-abd36349-26fc-4515-8878-1d726ac4b48b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3108368815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3108368815
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.269634899
Short name	T1004
Test name
Test status
Simulation time	5971199100 ps
CPU time	15.47 seconds
Started	Mar 26 02:26:05 PM PDT 24
Finished	Mar 26 02:26:21 PM PDT 24
Peak memory	199760 kb
Host	smart-3f798301-561a-44d5-a9af-3569eaf45c7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269634899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.269634899
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_stress_all.1876229288
Short name	T920
Test name
Test status
Simulation time	20551850029 ps
CPU time	1063.1 seconds
Started	Mar 26 02:26:16 PM PDT 24
Finished	Mar 26 02:43:59 PM PDT 24
Peak memory	200000 kb
Host	smart-4069cf63-5144-41c8-a7df-9dbeb64b496b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876229288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1876229288
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/45.uart_stress_all_with_rand_reset.3769294473
Short name	T124
Test name
Test status
Simulation time	458177016823 ps
CPU time	299.79 seconds
Started	Mar 26 02:26:13 PM PDT 24
Finished	Mar 26 02:31:13 PM PDT 24
Peak memory	216544 kb
Host	smart-5cb24f7b-00d0-4a43-91ed-a669e41e6fa9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769294473 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3769294473
Directory	/workspace/45.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.3457622469
Short name	T701
Test name
Test status
Simulation time	1703806094 ps
CPU time	1.76 seconds
Started	Mar 26 02:26:13 PM PDT 24
Finished	Mar 26 02:26:15 PM PDT 24
Peak memory	198284 kb
Host	smart-a11ff735-b171-41f7-b723-db7193336bb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457622469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3457622469
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.3187933591
Short name	T703
Test name
Test status
Simulation time	90613326334 ps
CPU time	18.35 seconds
Started	Mar 26 02:26:07 PM PDT 24
Finished	Mar 26 02:26:25 PM PDT 24
Peak memory	200052 kb
Host	smart-0e3e9d9d-2192-4f4a-97d5-8e40d8aa8281
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3187933591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3187933591
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.2282219010
Short name	T748
Test name
Test status
Simulation time	40396293 ps
CPU time	0.55 seconds
Started	Mar 26 02:26:23 PM PDT 24
Finished	Mar 26 02:26:24 PM PDT 24
Peak memory	194564 kb
Host	smart-4217f0c7-f7ed-4ce4-98f2-6461ef7825d1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282219010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2282219010
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.1000743125
Short name	T814
Test name
Test status
Simulation time	19062588302 ps
CPU time	28.35 seconds
Started	Mar 26 02:26:15 PM PDT 24
Finished	Mar 26 02:26:43 PM PDT 24
Peak memory	199144 kb
Host	smart-626ec56b-340f-4a30-9019-e4d8f8d85ca4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000743125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1000743125
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.852266304
Short name	T601
Test name
Test status
Simulation time	39075070059 ps
CPU time	50.31 seconds
Started	Mar 26 02:26:13 PM PDT 24
Finished	Mar 26 02:27:04 PM PDT 24
Peak memory	200012 kb
Host	smart-5c32a307-7c33-4f39-afbd-9398f3fc8904
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852266304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.852266304
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.193004739
Short name	T358
Test name
Test status
Simulation time	32249032382 ps
CPU time	23.73 seconds
Started	Mar 26 02:26:22 PM PDT 24
Finished	Mar 26 02:26:46 PM PDT 24
Peak memory	199984 kb
Host	smart-46fa43d8-4fcc-41ff-bb54-907e3443179c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193004739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.193004739
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/default/46.uart_intr.3301094399
Short name	T442
Test name
Test status
Simulation time	37626118246 ps
CPU time	51.59 seconds
Started	Mar 26 02:26:24 PM PDT 24
Finished	Mar 26 02:27:16 PM PDT 24
Peak memory	200160 kb
Host	smart-87ad7db7-e424-479d-b13e-b49dce90e76c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301094399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3301094399
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.4245178273
Short name	T1049
Test name
Test status
Simulation time	167105781576 ps
CPU time	478.42 seconds
Started	Mar 26 02:26:22 PM PDT 24
Finished	Mar 26 02:34:20 PM PDT 24
Peak memory	200072 kb
Host	smart-dde663dc-4309-4d85-9853-7d585de722c4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4245178273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4245178273
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.3974984212
Short name	T987
Test name
Test status
Simulation time	6197031347 ps
CPU time	12.08 seconds
Started	Mar 26 02:26:22 PM PDT 24
Finished	Mar 26 02:26:34 PM PDT 24
Peak memory	200104 kb
Host	smart-6bbbb8f7-723e-4e97-ab88-2dd0eefae2f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974984212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3974984212
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.1893235653
Short name	T1065
Test name
Test status
Simulation time	10391950367 ps
CPU time	17.04 seconds
Started	Mar 26 02:26:22 PM PDT 24
Finished	Mar 26 02:26:39 PM PDT 24
Peak memory	200152 kb
Host	smart-bcb747b2-f572-492d-86d6-a42564b78ef7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893235653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1893235653
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.3924879860
Short name	T296
Test name
Test status
Simulation time	12435128323 ps
CPU time	326.4 seconds
Started	Mar 26 02:26:24 PM PDT 24
Finished	Mar 26 02:31:51 PM PDT 24
Peak memory	200008 kb
Host	smart-e819e106-66dc-4392-b153-6606e5606282
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3924879860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3924879860
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.1686734884
Short name	T685
Test name
Test status
Simulation time	6106429941 ps
CPU time	16.87 seconds
Started	Mar 26 02:26:22 PM PDT 24
Finished	Mar 26 02:26:39 PM PDT 24
Peak memory	199960 kb
Host	smart-05c2cd95-5b28-435e-a6ce-fb6632156286
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1686734884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1686734884
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.2051342537
Short name	T954
Test name
Test status
Simulation time	75212762049 ps
CPU time	170.72 seconds
Started	Mar 26 02:26:23 PM PDT 24
Finished	Mar 26 02:29:14 PM PDT 24
Peak memory	199976 kb
Host	smart-8e8891c9-2181-497d-bd53-86d63d923eed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051342537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2051342537
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.809705645
Short name	T524
Test name
Test status
Simulation time	1989529164 ps
CPU time	1.36 seconds
Started	Mar 26 02:26:21 PM PDT 24
Finished	Mar 26 02:26:22 PM PDT 24
Peak memory	195856 kb
Host	smart-1515e21f-85af-4a61-869e-cf3e136c6434
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809705645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.809705645
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.44911845
Short name	T959
Test name
Test status
Simulation time	6229022837 ps
CPU time	8.15 seconds
Started	Mar 26 02:26:14 PM PDT 24
Finished	Mar 26 02:26:22 PM PDT 24
Peak memory	199328 kb
Host	smart-501ef95b-68d0-40f6-8ec3-30af6554ca96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44911845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.44911845
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.1533079304
Short name	T139
Test name
Test status
Simulation time	92354252405 ps
CPU time	134.42 seconds
Started	Mar 26 02:26:22 PM PDT 24
Finished	Mar 26 02:28:36 PM PDT 24
Peak memory	200192 kb
Host	smart-cedd851d-613a-4019-b390-c00e407b0c8b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533079304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1533079304
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.579183587
Short name	T688
Test name
Test status
Simulation time	1301892091 ps
CPU time	2.53 seconds
Started	Mar 26 02:26:24 PM PDT 24
Finished	Mar 26 02:26:27 PM PDT 24
Peak memory	199916 kb
Host	smart-ff69b1f6-70eb-4161-981f-8693e0c070b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579183587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.579183587
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.1989071451
Short name	T469
Test name
Test status
Simulation time	28072767967 ps
CPU time	9.19 seconds
Started	Mar 26 02:26:15 PM PDT 24
Finished	Mar 26 02:26:24 PM PDT 24
Peak memory	197656 kb
Host	smart-03a5e8b2-3dbd-420d-9c5b-9713f85ccdb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989071451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1989071451
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.2034926720
Short name	T1078
Test name
Test status
Simulation time	41156216 ps
CPU time	0.58 seconds
Started	Mar 26 02:26:30 PM PDT 24
Finished	Mar 26 02:26:31 PM PDT 24
Peak memory	195592 kb
Host	smart-7dea3ac6-447d-46d3-aaa5-fc44a9260513
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034926720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2034926720
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.3521594391
Short name	T142
Test name
Test status
Simulation time	12177587741 ps
CPU time	20.96 seconds
Started	Mar 26 02:26:36 PM PDT 24
Finished	Mar 26 02:26:57 PM PDT 24
Peak memory	199048 kb
Host	smart-ad199466-1eb2-45bd-b1d8-4928bb0e853a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521594391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3521594391
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.3091779330
Short name	T189
Test name
Test status
Simulation time	32978498465 ps
CPU time	17.17 seconds
Started	Mar 26 02:26:29 PM PDT 24
Finished	Mar 26 02:26:47 PM PDT 24
Peak memory	199668 kb
Host	smart-de61b98d-6344-470a-b4ad-127cf784b71c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091779330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3091779330
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.3353585806
Short name	T536
Test name
Test status
Simulation time	36563042706 ps
CPU time	31.18 seconds
Started	Mar 26 02:26:30 PM PDT 24
Finished	Mar 26 02:27:01 PM PDT 24
Peak memory	200076 kb
Host	smart-1b9c7786-c1b0-4b01-8f36-e4fefb596414
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353585806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3353585806
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/47.uart_intr.3177977898
Short name	T897
Test name
Test status
Simulation time	21344280143 ps
CPU time	34.64 seconds
Started	Mar 26 02:26:30 PM PDT 24
Finished	Mar 26 02:27:05 PM PDT 24
Peak memory	197960 kb
Host	smart-24b0ccf1-83d2-4528-b60d-d9e21ffae9f3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177977898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3177977898
Directory	/workspace/47.uart_intr/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.3084159135
Short name	T490
Test name
Test status
Simulation time	106832805933 ps
CPU time	243.46 seconds
Started	Mar 26 02:26:35 PM PDT 24
Finished	Mar 26 02:30:39 PM PDT 24
Peak memory	200036 kb
Host	smart-9af8ed1e-de55-4dcb-b4b7-e1bbd0f6631a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3084159135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3084159135
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_loopback.2836754172
Short name	T528
Test name
Test status
Simulation time	1598706087 ps
CPU time	3.41 seconds
Started	Mar 26 02:26:29 PM PDT 24
Finished	Mar 26 02:26:33 PM PDT 24
Peak memory	198524 kb
Host	smart-8ef76e19-033b-420c-a30f-99ef5b064dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836754172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2836754172
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.2792919254
Short name	T848
Test name
Test status
Simulation time	34995480820 ps
CPU time	58.93 seconds
Started	Mar 26 02:26:36 PM PDT 24
Finished	Mar 26 02:27:35 PM PDT 24
Peak memory	199348 kb
Host	smart-2fa00165-c99d-4833-9d22-69d2be88b713
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2792919254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2792919254
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.732081962
Short name	T518
Test name
Test status
Simulation time	21935146505 ps
CPU time	1079.04 seconds
Started	Mar 26 02:26:30 PM PDT 24
Finished	Mar 26 02:44:29 PM PDT 24
Peak memory	200076 kb
Host	smart-911aa04b-6800-4887-bda5-aef044220bdc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=732081962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.732081962
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.4161004408
Short name	T462
Test name
Test status
Simulation time	5065710555 ps
CPU time	24.44 seconds
Started	Mar 26 02:26:29 PM PDT 24
Finished	Mar 26 02:26:54 PM PDT 24
Peak memory	199308 kb
Host	smart-f0bb4d3b-3154-4786-be56-5b9875104b5e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4161004408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4161004408
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.3689839339
Short name	T1063
Test name
Test status
Simulation time	36218762089 ps
CPU time	71.25 seconds
Started	Mar 26 02:26:30 PM PDT 24
Finished	Mar 26 02:27:42 PM PDT 24
Peak memory	200048 kb
Host	smart-cee6e3d6-de6e-42a7-b894-ba70a73ff3ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689839339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3689839339
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.1932866541
Short name	T576
Test name
Test status
Simulation time	37595719537 ps
CPU time	55.84 seconds
Started	Mar 26 02:26:31 PM PDT 24
Finished	Mar 26 02:27:27 PM PDT 24
Peak memory	195952 kb
Host	smart-e8534c4e-5a7b-4ffa-848f-8eca15805a5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932866541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1932866541
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.2034475928
Short name	T882
Test name
Test status
Simulation time	941219019 ps
CPU time	2.5 seconds
Started	Mar 26 02:26:23 PM PDT 24
Finished	Mar 26 02:26:26 PM PDT 24
Peak memory	199532 kb
Host	smart-3e87f5ba-25ad-4b69-958b-86d785387758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034475928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2034475928
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.2567442933
Short name	T778
Test name
Test status
Simulation time	314032812426 ps
CPU time	224.19 seconds
Started	Mar 26 02:26:36 PM PDT 24
Finished	Mar 26 02:30:20 PM PDT 24
Peak memory	200076 kb
Host	smart-f43d70f2-4bb2-4f22-bd73-70b0f1a23760
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567442933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2567442933
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.3962554287
Short name	T377
Test name
Test status
Simulation time	831685312 ps
CPU time	2.59 seconds
Started	Mar 26 02:26:30 PM PDT 24
Finished	Mar 26 02:26:33 PM PDT 24
Peak memory	198364 kb
Host	smart-dee73971-6759-4e6b-973a-1c99f3727b42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962554287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3962554287
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.2847644763
Short name	T828
Test name
Test status
Simulation time	16154388733 ps
CPU time	12.56 seconds
Started	Mar 26 02:26:36 PM PDT 24
Finished	Mar 26 02:26:49 PM PDT 24
Peak memory	197996 kb
Host	smart-e5d72908-6191-4b8a-8ea2-1f16825fcc93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847644763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2847644763
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.2924782143
Short name	T451
Test name
Test status
Simulation time	86277338 ps
CPU time	0.56 seconds
Started	Mar 26 02:26:51 PM PDT 24
Finished	Mar 26 02:26:51 PM PDT 24
Peak memory	195468 kb
Host	smart-ce6bbb56-8e1a-41dc-8b6d-95c2fa5b3740
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924782143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2924782143
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.2172404462
Short name	T510
Test name
Test status
Simulation time	83273706440 ps
CPU time	19.45 seconds
Started	Mar 26 02:26:39 PM PDT 24
Finished	Mar 26 02:26:59 PM PDT 24
Peak memory	200136 kb
Host	smart-9345bfd6-4771-4210-8016-9a58d11517f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172404462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2172404462
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.1110494357
Short name	T818
Test name
Test status
Simulation time	33842977858 ps
CPU time	73.42 seconds
Started	Mar 26 02:26:39 PM PDT 24
Finished	Mar 26 02:27:53 PM PDT 24
Peak memory	200176 kb
Host	smart-5442b85a-1900-45ae-9b7e-2e0a98e5d7c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110494357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1110494357
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_intr.4134000130
Short name	T916
Test name
Test status
Simulation time	334424184769 ps
CPU time	505.11 seconds
Started	Mar 26 02:26:41 PM PDT 24
Finished	Mar 26 02:35:07 PM PDT 24
Peak memory	200188 kb
Host	smart-891efcd8-788e-4128-b6c3-e9204be4463e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134000130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4134000130
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.4066295195
Short name	T547
Test name
Test status
Simulation time	91966099669 ps
CPU time	668.68 seconds
Started	Mar 26 02:26:48 PM PDT 24
Finished	Mar 26 02:37:57 PM PDT 24
Peak memory	200040 kb
Host	smart-8c72c7c1-ce71-4972-aaff-eb32cceb5380
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4066295195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4066295195
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.1977610776
Short name	T949
Test name
Test status
Simulation time	183876778 ps
CPU time	0.73 seconds
Started	Mar 26 02:26:39 PM PDT 24
Finished	Mar 26 02:26:40 PM PDT 24
Peak memory	195976 kb
Host	smart-6630ae90-254c-44c8-b0cb-d35b4f78ba7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977610776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1977610776
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.1194412843
Short name	T679
Test name
Test status
Simulation time	53634525753 ps
CPU time	23.99 seconds
Started	Mar 26 02:26:40 PM PDT 24
Finished	Mar 26 02:27:04 PM PDT 24
Peak memory	200108 kb
Host	smart-95ad35b1-fd8d-484a-a7eb-22359623aa35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194412843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1194412843
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.1056605106
Short name	T850
Test name
Test status
Simulation time	16124290472 ps
CPU time	331.04 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:32:20 PM PDT 24
Peak memory	200068 kb
Host	smart-494a004a-443e-45a9-881d-87a7c1211430
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1056605106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1056605106
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_oversample.183207277
Short name	T716
Test name
Test status
Simulation time	7202475079 ps
CPU time	63.13 seconds
Started	Mar 26 02:26:39 PM PDT 24
Finished	Mar 26 02:27:42 PM PDT 24
Peak memory	199304 kb
Host	smart-17c11744-5f77-4d3f-b758-0cf072a666a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=183207277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.183207277
Directory	/workspace/48.uart_rx_oversample/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.2847356795
Short name	T860
Test name
Test status
Simulation time	1201123236 ps
CPU time	2.82 seconds
Started	Mar 26 02:26:40 PM PDT 24
Finished	Mar 26 02:26:43 PM PDT 24
Peak memory	195584 kb
Host	smart-1629a08d-eb5c-45f8-a92d-e6e7a87a40ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847356795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2847356795
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.3309695021
Short name	T444
Test name
Test status
Simulation time	450006165 ps
CPU time	2.33 seconds
Started	Mar 26 02:26:30 PM PDT 24
Finished	Mar 26 02:26:32 PM PDT 24
Peak memory	198848 kb
Host	smart-22a4bd6c-c187-4390-b785-1db7aad961aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309695021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3309695021
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_stress_all.135818484
Short name	T240
Test name
Test status
Simulation time	254578828645 ps
CPU time	262.22 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:31:11 PM PDT 24
Peak memory	200240 kb
Host	smart-b51d3c3f-3724-4460-9a65-6a1f0c3974a9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135818484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.135818484
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.2617205300
Short name	T1054
Test name
Test status
Simulation time	1222428958 ps
CPU time	4.91 seconds
Started	Mar 26 02:26:40 PM PDT 24
Finished	Mar 26 02:26:46 PM PDT 24
Peak memory	199568 kb
Host	smart-a381c4c4-7b4f-47a8-95e4-39299604d84c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617205300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2617205300
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.2329392128
Short name	T472
Test name
Test status
Simulation time	15967278065 ps
CPU time	30.86 seconds
Started	Mar 26 02:26:39 PM PDT 24
Finished	Mar 26 02:27:11 PM PDT 24
Peak memory	200096 kb
Host	smart-64d8be3f-6354-404a-939e-c55f133ebefb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329392128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2329392128
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.836939793
Short name	T726
Test name
Test status
Simulation time	76092725 ps
CPU time	0.6 seconds
Started	Mar 26 02:27:01 PM PDT 24
Finished	Mar 26 02:27:02 PM PDT 24
Peak memory	194508 kb
Host	smart-af9352e0-ed4a-491a-9597-1826339ab646
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836939793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.836939793
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.810970043
Short name	T321
Test name
Test status
Simulation time	81438184497 ps
CPU time	91.71 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:28:21 PM PDT 24
Peak memory	200088 kb
Host	smart-385517fe-7eff-4e28-bfc9-c91139ae2d96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810970043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.810970043
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.3702608646
Short name	T886
Test name
Test status
Simulation time	45269292518 ps
CPU time	21.18 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:27:11 PM PDT 24
Peak memory	200096 kb
Host	smart-083ade3d-990c-4263-861e-093438bf10e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702608646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3702608646
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.3038472614
Short name	T230
Test name
Test status
Simulation time	24879969252 ps
CPU time	51.04 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:27:40 PM PDT 24
Peak memory	200076 kb
Host	smart-29d3e74e-0e4b-46de-b68e-3f9950a6289c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038472614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3038472614
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_intr.1564261349
Short name	T861
Test name
Test status
Simulation time	93247863244 ps
CPU time	86.35 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:28:15 PM PDT 24
Peak memory	200180 kb
Host	smart-95660055-64d2-40ab-bff0-4b96d6f6cee9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564261349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1564261349
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.172197418
Short name	T56
Test name
Test status
Simulation time	68808178103 ps
CPU time	128.95 seconds
Started	Mar 26 02:27:01 PM PDT 24
Finished	Mar 26 02:29:10 PM PDT 24
Peak memory	200032 kb
Host	smart-fb0ee2cd-3411-4bd2-8be3-6e3bba0e19ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=172197418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.172197418
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/49.uart_loopback.652596684
Short name	T415
Test name
Test status
Simulation time	9052891459 ps
CPU time	4.25 seconds
Started	Mar 26 02:26:48 PM PDT 24
Finished	Mar 26 02:26:53 PM PDT 24
Peak memory	199872 kb
Host	smart-b2b8d5ac-e6a5-4ecc-b971-18cf6fb30eb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652596684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.652596684
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.2001806557
Short name	T381
Test name
Test status
Simulation time	10227764111 ps
CPU time	17.17 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:27:07 PM PDT 24
Peak memory	196176 kb
Host	smart-a012d2a8-38e9-4ee9-a5c2-6da607608918
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001806557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2001806557
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.1632710894
Short name	T774
Test name
Test status
Simulation time	16523154721 ps
CPU time	230.19 seconds
Started	Mar 26 02:26:50 PM PDT 24
Finished	Mar 26 02:30:41 PM PDT 24
Peak memory	200096 kb
Host	smart-6ee8e84a-533a-4b8f-8488-1ecc68d1267c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1632710894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1632710894
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.570876506
Short name	T14
Test name
Test status
Simulation time	6235534917 ps
CPU time	58.92 seconds
Started	Mar 26 02:26:50 PM PDT 24
Finished	Mar 26 02:27:49 PM PDT 24
Peak memory	198076 kb
Host	smart-596e6a52-d878-4da0-bdf0-453091323444
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=570876506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.570876506
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.1118580857
Short name	T68
Test name
Test status
Simulation time	49647442047 ps
CPU time	20.56 seconds
Started	Mar 26 02:26:50 PM PDT 24
Finished	Mar 26 02:27:11 PM PDT 24
Peak memory	200176 kb
Host	smart-9f3bfa6d-f3c8-426a-947f-d49de664e116
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118580857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1118580857
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.1578593862
Short name	T857
Test name
Test status
Simulation time	2344060633 ps
CPU time	2.64 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:26:51 PM PDT 24
Peak memory	196152 kb
Host	smart-7ed126cd-8845-4a17-b4dc-d6257da440ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578593862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1578593862
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.337725511
Short name	T968
Test name
Test status
Simulation time	5643552393 ps
CPU time	17.12 seconds
Started	Mar 26 02:26:50 PM PDT 24
Finished	Mar 26 02:27:07 PM PDT 24
Peak memory	199744 kb
Host	smart-e31daeee-54a2-4d5c-a601-36862419d3c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337725511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.337725511
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_stress_all.3187959102
Short name	T421
Test name
Test status
Simulation time	107356229159 ps
CPU time	53.4 seconds
Started	Mar 26 02:27:03 PM PDT 24
Finished	Mar 26 02:27:57 PM PDT 24
Peak memory	216124 kb
Host	smart-92238ac2-7f05-4f61-b25b-7d4798ef82ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187959102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3187959102
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.1684339198
Short name	T560
Test name
Test status
Simulation time	1143939982 ps
CPU time	3.58 seconds
Started	Mar 26 02:26:48 PM PDT 24
Finished	Mar 26 02:26:52 PM PDT 24
Peak memory	199940 kb
Host	smart-a2e620d5-9ae0-49a4-aa0a-089ea219085c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684339198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1684339198
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.3152404618
Short name	T674
Test name
Test status
Simulation time	163050723659 ps
CPU time	51.03 seconds
Started	Mar 26 02:26:49 PM PDT 24
Finished	Mar 26 02:27:41 PM PDT 24
Peak memory	200084 kb
Host	smart-2c6bb5f9-3ac2-49c8-bbcb-b9e921271b6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152404618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3152404618
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.296915496
Short name	T903
Test name
Test status
Simulation time	21667624 ps
CPU time	0.57 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:19:57 PM PDT 24
Peak memory	195512 kb
Host	smart-d473d424-56f9-4bc7-9a9d-5fee3d035377
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296915496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.296915496
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.416304364
Short name	T963
Test name
Test status
Simulation time	21043848886 ps
CPU time	14.62 seconds
Started	Mar 26 02:19:54 PM PDT 24
Finished	Mar 26 02:20:08 PM PDT 24
Peak memory	200124 kb
Host	smart-6a065591-067d-4dde-8457-0cc4b380caa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416304364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.416304364
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.3419458226
Short name	T137
Test name
Test status
Simulation time	186022554989 ps
CPU time	321.47 seconds
Started	Mar 26 02:19:58 PM PDT 24
Finished	Mar 26 02:25:20 PM PDT 24
Peak memory	200092 kb
Host	smart-5eeb231f-6616-4f93-add7-cfcf4201a001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419458226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3419458226
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.3996377195
Short name	T658
Test name
Test status
Simulation time	21881424788 ps
CPU time	45.86 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:20:41 PM PDT 24
Peak memory	199988 kb
Host	smart-02c492a7-b958-4aa2-89c0-dfa26cd74c70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996377195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3996377195
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.3558681410
Short name	T23
Test name
Test status
Simulation time	68017176940 ps
CPU time	123.63 seconds
Started	Mar 26 02:19:57 PM PDT 24
Finished	Mar 26 02:22:01 PM PDT 24
Peak memory	200092 kb
Host	smart-926f264e-f002-4321-9e36-03ce706acd39
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558681410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3558681410
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.821784512
Short name	T446
Test name
Test status
Simulation time	72766252979 ps
CPU time	244.6 seconds
Started	Mar 26 02:19:55 PM PDT 24
Finished	Mar 26 02:23:59 PM PDT 24
Peak memory	200052 kb
Host	smart-5fd92e98-a9f4-4cbc-9a72-0e620fb393eb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=821784512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.821784512
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.2514990294
Short name	T520
Test name
Test status
Simulation time	9304723828 ps
CPU time	19.77 seconds
Started	Mar 26 02:19:58 PM PDT 24
Finished	Mar 26 02:20:18 PM PDT 24
Peak memory	200064 kb
Host	smart-87df3bfe-cb9d-431e-96fc-f76bf17754a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514990294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2514990294
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.1863282558
Short name	T346
Test name
Test status
Simulation time	1349085907 ps
CPU time	2.79 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:19:59 PM PDT 24
Peak memory	200056 kb
Host	smart-ef0477a4-a2d8-4b6e-8277-53ff0dffc54e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863282558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1863282558
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.3361974584
Short name	T745
Test name
Test status
Simulation time	12828568898 ps
CPU time	124.18 seconds
Started	Mar 26 02:19:57 PM PDT 24
Finished	Mar 26 02:22:01 PM PDT 24
Peak memory	199956 kb
Host	smart-87c8965b-bc2a-4da0-883e-e15c4b679b0d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3361974584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3361974584
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.16450646
Short name	T374
Test name
Test status
Simulation time	5472087072 ps
CPU time	6.47 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:20:02 PM PDT 24
Peak memory	199084 kb
Host	smart-462d950b-aeb9-4155-94fa-0545617da745
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=16450646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.16450646
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.4186303438
Short name	T65
Test name
Test status
Simulation time	94931095666 ps
CPU time	48.46 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:20:45 PM PDT 24
Peak memory	200012 kb
Host	smart-b6f259f7-6981-4e3c-9616-4e7caeb67bc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186303438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4186303438
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.426438191
Short name	T526
Test name
Test status
Simulation time	1709354315 ps
CPU time	3.56 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:19:59 PM PDT 24
Peak memory	195456 kb
Host	smart-51025634-b45f-4d84-ae3e-842fb050b39b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426438191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.426438191
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.677552552
Short name	T1047
Test name
Test status
Simulation time	5345798344 ps
CPU time	11.6 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:20:07 PM PDT 24
Peak memory	200012 kb
Host	smart-70c3f39b-c214-4a90-a55a-55a683076a27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677552552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.677552552
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all.1493617878
Short name	T651
Test name
Test status
Simulation time	170092895011 ps
CPU time	299.53 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:24:56 PM PDT 24
Peak memory	200044 kb
Host	smart-a8069e66-de15-48b3-8f65-083164a93f6e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493617878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1493617878
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.3269246686
Short name	T586
Test name
Test status
Simulation time	7205453144 ps
CPU time	22.52 seconds
Started	Mar 26 02:19:56 PM PDT 24
Finished	Mar 26 02:20:18 PM PDT 24
Peak memory	200032 kb
Host	smart-a0cdf1f7-c771-4d60-aafe-53b2baa60cfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269246686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3269246686
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.1946734904
Short name	T783
Test name
Test status
Simulation time	74868304904 ps
CPU time	136.65 seconds
Started	Mar 26 02:19:55 PM PDT 24
Finished	Mar 26 02:22:12 PM PDT 24
Peak memory	200028 kb
Host	smart-96413f64-2225-47b6-9278-0e052e1ae854
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946734904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1946734904
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.2946283603
Short name	T816
Test name
Test status
Simulation time	69396412148 ps
CPU time	31.47 seconds
Started	Mar 26 02:27:02 PM PDT 24
Finished	Mar 26 02:27:33 PM PDT 24
Peak memory	200080 kb
Host	smart-4fd0f109-1216-4931-b18c-644c8c083215
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946283603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2946283603
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.3996871896
Short name	T863
Test name
Test status
Simulation time	149867437974 ps
CPU time	57.24 seconds
Started	Mar 26 02:27:01 PM PDT 24
Finished	Mar 26 02:27:59 PM PDT 24
Peak memory	199980 kb
Host	smart-10ba9077-acf1-4d0d-aff4-569cb02501dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996871896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3996871896
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.2681669911
Short name	T363
Test name
Test status
Simulation time	200757511522 ps
CPU time	334.76 seconds
Started	Mar 26 02:27:03 PM PDT 24
Finished	Mar 26 02:32:38 PM PDT 24
Peak memory	200024 kb
Host	smart-ecf6ddce-5110-4f26-9145-d53924650a8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681669911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2681669911
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/52.uart_stress_all_with_rand_reset.1658619196
Short name	T354
Test name
Test status
Simulation time	197475200451 ps
CPU time	585.28 seconds
Started	Mar 26 02:27:01 PM PDT 24
Finished	Mar 26 02:36:47 PM PDT 24
Peak memory	214152 kb
Host	smart-c63fa500-0bac-4572-91f6-87b62b17a590
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658619196 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1658619196
Directory	/workspace/52.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.1516998805
Short name	T715
Test name
Test status
Simulation time	88024864108 ps
CPU time	194.99 seconds
Started	Mar 26 02:27:03 PM PDT 24
Finished	Mar 26 02:30:18 PM PDT 24
Peak memory	200032 kb
Host	smart-26dafa4e-e523-48d3-9244-0f8130ed3fb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516998805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1516998805
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.2777026889
Short name	T367
Test name
Test status
Simulation time	165501941382 ps
CPU time	244.04 seconds
Started	Mar 26 02:27:02 PM PDT 24
Finished	Mar 26 02:31:06 PM PDT 24
Peak memory	200004 kb
Host	smart-273ca6ee-2c93-4b6e-aa9c-c4f0e424f7dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777026889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2777026889
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_stress_all_with_rand_reset.2322319308
Short name	T69
Test name
Test status
Simulation time	68416120173 ps
CPU time	436.34 seconds
Started	Mar 26 02:27:02 PM PDT 24
Finished	Mar 26 02:34:19 PM PDT 24
Peak memory	214604 kb
Host	smart-a506c1b2-7997-43e9-a81f-3c92af6ca494
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322319308 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2322319308
Directory	/workspace/54.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.1390785141
Short name	T878
Test name
Test status
Simulation time	30998459690 ps
CPU time	50.01 seconds
Started	Mar 26 02:27:18 PM PDT 24
Finished	Mar 26 02:28:08 PM PDT 24
Peak memory	199964 kb
Host	smart-5b4feb27-af00-4601-922d-69a9d054979d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390785141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1390785141
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.1994757255
Short name	T484
Test name
Test status
Simulation time	88739624881 ps
CPU time	140.7 seconds
Started	Mar 26 02:27:12 PM PDT 24
Finished	Mar 26 02:29:33 PM PDT 24
Peak memory	200040 kb
Host	smart-58bd55d9-af4e-46bc-88fc-fe71989d537b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994757255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1994757255
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/56.uart_stress_all_with_rand_reset.2074101330
Short name	T129
Test name
Test status
Simulation time	629779466073 ps
CPU time	477.7 seconds
Started	Mar 26 02:27:13 PM PDT 24
Finished	Mar 26 02:35:12 PM PDT 24
Peak memory	216484 kb
Host	smart-42d99467-132e-4097-b436-78ca6d34a6d0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074101330 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2074101330
Directory	/workspace/56.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.1727621350
Short name	T418
Test name
Test status
Simulation time	100263619458 ps
CPU time	41.88 seconds
Started	Mar 26 02:27:11 PM PDT 24
Finished	Mar 26 02:27:54 PM PDT 24
Peak memory	200028 kb
Host	smart-67373ae3-fc70-43a2-8b86-ff097de98f44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727621350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1727621350
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.2175325306
Short name	T470
Test name
Test status
Simulation time	234679437875 ps
CPU time	32.9 seconds
Started	Mar 26 02:27:14 PM PDT 24
Finished	Mar 26 02:27:47 PM PDT 24
Peak memory	200108 kb
Host	smart-cda94dfc-ccc3-4818-95f1-750513655009
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175325306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2175325306
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_stress_all_with_rand_reset.402110357
Short name	T356
Test name
Test status
Simulation time	325392659498 ps
CPU time	703.27 seconds
Started	Mar 26 02:27:12 PM PDT 24
Finished	Mar 26 02:38:56 PM PDT 24
Peak memory	224912 kb
Host	smart-b42577b9-60c4-44d6-90e3-e9b890935f43
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402110357 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.402110357
Directory	/workspace/58.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.1161649173
Short name	T183
Test name
Test status
Simulation time	73594801438 ps
CPU time	119.02 seconds
Started	Mar 26 02:27:13 PM PDT 24
Finished	Mar 26 02:29:14 PM PDT 24
Peak memory	200024 kb
Host	smart-c3d5d160-e60b-4bd7-9520-61ffb049a862
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161649173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1161649173
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.3034175273
Short name	T1046
Test name
Test status
Simulation time	97754474 ps
CPU time	0.58 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:20:10 PM PDT 24
Peak memory	195576 kb
Host	smart-f002e814-065b-4f82-bfc9-0afec6ea04ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034175273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3034175273
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.2971565134
Short name	T175
Test name
Test status
Simulation time	96650068934 ps
CPU time	42.21 seconds
Started	Mar 26 02:20:10 PM PDT 24
Finished	Mar 26 02:20:53 PM PDT 24
Peak memory	200060 kb
Host	smart-d1ccae37-7b1b-4f39-b8df-2866de0ca54e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971565134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2971565134
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.2113040398
Short name	T192
Test name
Test status
Simulation time	82988657875 ps
CPU time	245.08 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:24:14 PM PDT 24
Peak memory	199896 kb
Host	smart-942a30f8-147f-46f4-aef1-068b8eebd7b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113040398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2113040398
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_fifo_reset.1006227952
Short name	T1043
Test name
Test status
Simulation time	28415184914 ps
CPU time	27.01 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:20:36 PM PDT 24
Peak memory	199932 kb
Host	smart-89916610-d2ad-4da4-a97a-d2e563abea59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006227952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1006227952
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_intr.25916842
Short name	T760
Test name
Test status
Simulation time	359164752957 ps
CPU time	611.3 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:30:20 PM PDT 24
Peak memory	199952 kb
Host	smart-626b582e-29bb-4971-be61-60edc265d623
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25916842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.25916842
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.972193528
Short name	T1108
Test name
Test status
Simulation time	247919542603 ps
CPU time	276.08 seconds
Started	Mar 26 02:20:11 PM PDT 24
Finished	Mar 26 02:24:47 PM PDT 24
Peak memory	200096 kb
Host	smart-cd6649fc-f150-44e0-9389-31c409a60d3f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=972193528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.972193528
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.3936081744
Short name	T408
Test name
Test status
Simulation time	4035707877 ps
CPU time	6.11 seconds
Started	Mar 26 02:20:07 PM PDT 24
Finished	Mar 26 02:20:14 PM PDT 24
Peak memory	200104 kb
Host	smart-b4f35d95-fc19-475c-8c4f-68998ebc27ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936081744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3936081744
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.1432622861
Short name	T736
Test name
Test status
Simulation time	42611369037 ps
CPU time	75.87 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:21:26 PM PDT 24
Peak memory	200228 kb
Host	smart-600c8e34-33b7-442c-a12f-b940a1a3a861
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432622861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1432622861
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.673158821
Short name	T640
Test name
Test status
Simulation time	14044444255 ps
CPU time	53.84 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:21:02 PM PDT 24
Peak memory	200116 kb
Host	smart-888abec4-7975-4123-bc5a-e6cda14574e7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=673158821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.673158821
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.3360692731
Short name	T606
Test name
Test status
Simulation time	4231306195 ps
CPU time	38.41 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:20:47 PM PDT 24
Peak memory	199488 kb
Host	smart-01d26731-7011-44b3-ad8d-17b372c1b0eb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3360692731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3360692731
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.700400361
Short name	T441
Test name
Test status
Simulation time	200826036148 ps
CPU time	309.78 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:25:20 PM PDT 24
Peak memory	200084 kb
Host	smart-c9f6e3bb-9423-47c0-b385-f14f7427419f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700400361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.700400361
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.2863614826
Short name	T580
Test name
Test status
Simulation time	2112821118 ps
CPU time	1.49 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:20:10 PM PDT 24
Peak memory	195524 kb
Host	smart-92a50c3d-1228-4c64-981e-5b9d3288a1de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863614826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2863614826
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.3264554342
Short name	T319
Test name
Test status
Simulation time	674479093 ps
CPU time	1.45 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:20:10 PM PDT 24
Peak memory	198264 kb
Host	smart-15ed6dba-4fe2-4bb5-9e77-37f2196b0b5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264554342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3264554342
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.3951579490
Short name	T756
Test name
Test status
Simulation time	173192281628 ps
CPU time	99.37 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:21:49 PM PDT 24
Peak memory	200100 kb
Host	smart-0b30680a-b735-414e-8099-cd250d44fd1f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951579490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3951579490
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_stress_all_with_rand_reset.2239325326
Short name	T128
Test name
Test status
Simulation time	40149143937 ps
CPU time	118.63 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:22:08 PM PDT 24
Peak memory	216032 kb
Host	smart-d14842aa-a6da-4588-a53f-709528f09032
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239325326 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2239325326
Directory	/workspace/6.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.1176975676
Short name	T595
Test name
Test status
Simulation time	1582367512 ps
CPU time	5.05 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:20:15 PM PDT 24
Peak memory	198716 kb
Host	smart-f1ac3106-c2a1-4ad8-8998-ecbba0008f19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176975676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1176975676
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.3991669222
Short name	T649
Test name
Test status
Simulation time	59252904100 ps
CPU time	14.04 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:20:24 PM PDT 24
Peak memory	197960 kb
Host	smart-5ebee841-d482-4a07-be53-7e66ff8d9e55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3991669222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3991669222
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.2158598940
Short name	T700
Test name
Test status
Simulation time	17120200000 ps
CPU time	15.51 seconds
Started	Mar 26 02:27:15 PM PDT 24
Finished	Mar 26 02:27:30 PM PDT 24
Peak memory	200112 kb
Host	smart-399b5272-0a81-4863-91ff-f5825669a01c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158598940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2158598940
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/60.uart_stress_all_with_rand_reset.2715271190
Short name	T125
Test name
Test status
Simulation time	200298890091 ps
CPU time	205.52 seconds
Started	Mar 26 02:27:12 PM PDT 24
Finished	Mar 26 02:30:38 PM PDT 24
Peak memory	216476 kb
Host	smart-0d6449b0-96d1-4403-bdd1-3ac3ff831605
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715271190 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2715271190
Directory	/workspace/60.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.827060698
Short name	T223
Test name
Test status
Simulation time	27812703677 ps
CPU time	69.94 seconds
Started	Mar 26 02:27:12 PM PDT 24
Finished	Mar 26 02:28:23 PM PDT 24
Peak memory	200024 kb
Host	smart-a44bc644-79de-4d37-a1ce-d72aee74954a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827060698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.827060698
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_fifo_reset.2314544131
Short name	T174
Test name
Test status
Simulation time	89053606767 ps
CPU time	40.82 seconds
Started	Mar 26 02:27:11 PM PDT 24
Finished	Mar 26 02:27:52 PM PDT 24
Peak memory	200040 kb
Host	smart-d7bc0a2f-4dd3-4843-809c-db92625e3227
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314544131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2314544131
Directory	/workspace/63.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.2913305620
Short name	T849
Test name
Test status
Simulation time	19412748378 ps
CPU time	26.09 seconds
Started	Mar 26 02:27:23 PM PDT 24
Finished	Mar 26 02:27:49 PM PDT 24
Peak memory	199828 kb
Host	smart-e5b3b6af-e2cb-4d0c-9045-f9cb883415e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913305620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2913305620
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.2750263832
Short name	T176
Test name
Test status
Simulation time	74441850331 ps
CPU time	41.01 seconds
Started	Mar 26 02:27:12 PM PDT 24
Finished	Mar 26 02:27:54 PM PDT 24
Peak memory	199912 kb
Host	smart-6f07693f-d2d3-4803-ba3e-b82694adc928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750263832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2750263832
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_stress_all_with_rand_reset.306012779
Short name	T258
Test name
Test status
Simulation time	21246221593 ps
CPU time	585.09 seconds
Started	Mar 26 02:27:12 PM PDT 24
Finished	Mar 26 02:36:59 PM PDT 24
Peak memory	216536 kb
Host	smart-731763b5-b8ac-4d24-8b32-e51008e05448
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306012779 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.306012779
Directory	/workspace/65.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.4082657662
Short name	T1033
Test name
Test status
Simulation time	32513216823 ps
CPU time	50.78 seconds
Started	Mar 26 02:27:21 PM PDT 24
Finished	Mar 26 02:28:12 PM PDT 24
Peak memory	200040 kb
Host	smart-eff0d484-ad91-4ab1-9be7-2a29016a8591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082657662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4082657662
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_stress_all_with_rand_reset.2793008557
Short name	T123
Test name
Test status
Simulation time	76060075165 ps
CPU time	149 seconds
Started	Mar 26 02:27:21 PM PDT 24
Finished	Mar 26 02:29:50 PM PDT 24
Peak memory	213560 kb
Host	smart-ff5e5352-5d2a-4609-a56a-8607b2934951
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793008557 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2793008557
Directory	/workspace/67.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.2051187123
Short name	T1107
Test name
Test status
Simulation time	63082249167 ps
CPU time	44.62 seconds
Started	Mar 26 02:27:21 PM PDT 24
Finished	Mar 26 02:28:06 PM PDT 24
Peak memory	200036 kb
Host	smart-487a94c4-8191-44e4-a6d6-52f138e2fb57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051187123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2051187123
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.1602792420
Short name	T241
Test name
Test status
Simulation time	41632114925 ps
CPU time	19.96 seconds
Started	Mar 26 02:27:22 PM PDT 24
Finished	Mar 26 02:27:42 PM PDT 24
Peak memory	200104 kb
Host	smart-0ff09e12-4460-4798-a54b-827f2158cb8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602792420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1602792420
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.3939503358
Short name	T436
Test name
Test status
Simulation time	14819744 ps
CPU time	0.58 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:20:24 PM PDT 24
Peak memory	195552 kb
Host	smart-c50f2e11-191e-4580-b0c5-81bb134ef192
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939503358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3939503358
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.2411809386
Short name	T1014
Test name
Test status
Simulation time	93490297207 ps
CPU time	69.37 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:21:19 PM PDT 24
Peak memory	200068 kb
Host	smart-c64aa8af-136a-4ac3-9e77-8548832f9016
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411809386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2411809386
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.1714151184
Short name	T801
Test name
Test status
Simulation time	37749931175 ps
CPU time	15.75 seconds
Started	Mar 26 02:20:11 PM PDT 24
Finished	Mar 26 02:20:27 PM PDT 24
Peak memory	200004 kb
Host	smart-62928078-c1e6-4d38-b9ee-ab1936cdb19c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714151184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1714151184
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.4000447107
Short name	T170
Test name
Test status
Simulation time	29230125446 ps
CPU time	48.51 seconds
Started	Mar 26 02:20:11 PM PDT 24
Finished	Mar 26 02:20:59 PM PDT 24
Peak memory	200040 kb
Host	smart-8bd6d446-dcf1-4ece-aea2-a63daf491542
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000447107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4000447107
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_intr.2511734296
Short name	T135
Test name
Test status
Simulation time	14080162504 ps
CPU time	3.73 seconds
Started	Mar 26 02:20:07 PM PDT 24
Finished	Mar 26 02:20:11 PM PDT 24
Peak memory	197940 kb
Host	smart-470fcd5c-cb17-4cc2-a946-2f1b92262111
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511734296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2511734296
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.500528616
Short name	T1061
Test name
Test status
Simulation time	88898682308 ps
CPU time	878.27 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:35:03 PM PDT 24
Peak memory	200044 kb
Host	smart-f5f6d444-2af6-4e04-8fc3-802774e6a5a2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=500528616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.500528616
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_loopback.2264909418
Short name	T741
Test name
Test status
Simulation time	5370355348 ps
CPU time	5.65 seconds
Started	Mar 26 02:20:26 PM PDT 24
Finished	Mar 26 02:20:31 PM PDT 24
Peak memory	198872 kb
Host	smart-eb388f85-c664-44c1-bd8a-83b31a2ec457
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264909418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2264909418
Directory	/workspace/7.uart_loopback/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.1762518710
Short name	T473
Test name
Test status
Simulation time	44034095699 ps
CPU time	71.62 seconds
Started	Mar 26 02:20:10 PM PDT 24
Finished	Mar 26 02:21:21 PM PDT 24
Peak memory	199132 kb
Host	smart-1276f604-4e7c-4fe8-85cc-1209eb45405b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762518710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1762518710
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.3980325158
Short name	T639
Test name
Test status
Simulation time	20674592182 ps
CPU time	549.98 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:29:35 PM PDT 24
Peak memory	200028 kb
Host	smart-5414c725-4d48-48d7-9318-2f8807850287
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3980325158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3980325158
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_oversample.1798226183
Short name	T991
Test name
Test status
Simulation time	5929258891 ps
CPU time	53.45 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:21:01 PM PDT 24
Peak memory	200012 kb
Host	smart-84dc55f4-e028-4286-a3b8-520c0400ba8a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1798226183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1798226183
Directory	/workspace/7.uart_rx_oversample/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.1930845929
Short name	T682
Test name
Test status
Simulation time	3223862910 ps
CPU time	2.09 seconds
Started	Mar 26 02:20:08 PM PDT 24
Finished	Mar 26 02:20:11 PM PDT 24
Peak memory	196220 kb
Host	smart-2d31a842-a7c5-4682-a601-1e2c5b44046a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930845929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1930845929
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.1133711334
Short name	T485
Test name
Test status
Simulation time	451659359 ps
CPU time	1.19 seconds
Started	Mar 26 02:20:10 PM PDT 24
Finished	Mar 26 02:20:11 PM PDT 24
Peak memory	198552 kb
Host	smart-ef90f235-4918-4561-bd8b-ac564ce5be73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133711334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1133711334
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_stress_all.1177712476
Short name	T138
Test name
Test status
Simulation time	67346841372 ps
CPU time	303.93 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:25:28 PM PDT 24
Peak memory	200096 kb
Host	smart-7b4e0c38-8547-49f8-b814-7baae3f02e73
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177712476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1177712476
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.2596123214
Short name	T834
Test name
Test status
Simulation time	7903476335 ps
CPU time	9.91 seconds
Started	Mar 26 02:20:27 PM PDT 24
Finished	Mar 26 02:20:37 PM PDT 24
Peak memory	200288 kb
Host	smart-666daa09-4f43-4fe9-a724-745f9ce96deb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596123214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2596123214
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.4210111895
Short name	T571
Test name
Test status
Simulation time	38510813851 ps
CPU time	67.63 seconds
Started	Mar 26 02:20:09 PM PDT 24
Finished	Mar 26 02:21:17 PM PDT 24
Peak memory	200004 kb
Host	smart-dae07f8c-4628-4ba0-9a6a-79cdd73c668f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4210111895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4210111895
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.2027149486
Short name	T225
Test name
Test status
Simulation time	45484954177 ps
CPU time	68.6 seconds
Started	Mar 26 02:27:21 PM PDT 24
Finished	Mar 26 02:28:30 PM PDT 24
Peak memory	200100 kb
Host	smart-b88577a3-f4c1-452e-8f50-5a951b28c527
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027149486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2027149486
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/default/70.uart_stress_all_with_rand_reset.1197328847
Short name	T1086
Test name
Test status
Simulation time	158290885987 ps
CPU time	334.3 seconds
Started	Mar 26 02:27:22 PM PDT 24
Finished	Mar 26 02:32:56 PM PDT 24
Peak memory	216588 kb
Host	smart-242dfc7c-88a9-4586-9c95-9838a21e968b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197328847 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1197328847
Directory	/workspace/70.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.3413424048
Short name	T1074
Test name
Test status
Simulation time	59420371960 ps
CPU time	26.49 seconds
Started	Mar 26 02:27:21 PM PDT 24
Finished	Mar 26 02:27:48 PM PDT 24
Peak memory	200128 kb
Host	smart-bef6a7ae-edda-456c-aa14-0112eb2fc645
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413424048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3413424048
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_stress_all_with_rand_reset.1115872697
Short name	T350
Test name
Test status
Simulation time	75468273020 ps
CPU time	309.31 seconds
Started	Mar 26 02:27:29 PM PDT 24
Finished	Mar 26 02:32:38 PM PDT 24
Peak memory	210408 kb
Host	smart-dbfe4139-21ff-42d4-a87f-4a754e87513a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115872697 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1115872697
Directory	/workspace/72.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/73.uart_stress_all_with_rand_reset.2459011874
Short name	T355
Test name
Test status
Simulation time	49858087093 ps
CPU time	652.74 seconds
Started	Mar 26 02:27:32 PM PDT 24
Finished	Mar 26 02:38:25 PM PDT 24
Peak memory	205456 kb
Host	smart-923265a7-5ea1-4e1b-a692-ef2f8e42b82e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459011874 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2459011874
Directory	/workspace/73.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.2599642936
Short name	T196
Test name
Test status
Simulation time	42814926493 ps
CPU time	39.31 seconds
Started	Mar 26 02:27:35 PM PDT 24
Finished	Mar 26 02:28:14 PM PDT 24
Peak memory	200104 kb
Host	smart-6ad18c8a-7d78-4146-ba0f-fc7beb7c40f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599642936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2599642936
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.337499833
Short name	T967
Test name
Test status
Simulation time	120188843066 ps
CPU time	57.5 seconds
Started	Mar 26 02:27:30 PM PDT 24
Finished	Mar 26 02:28:27 PM PDT 24
Peak memory	200096 kb
Host	smart-30d05135-a56a-4ee7-bf0b-ef2d738742a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337499833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.337499833
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.1463507055
Short name	T146
Test name
Test status
Simulation time	110639082576 ps
CPU time	95.64 seconds
Started	Mar 26 02:27:36 PM PDT 24
Finished	Mar 26 02:29:12 PM PDT 24
Peak memory	199692 kb
Host	smart-295b40e0-cb28-4086-bb4b-e99aaa2c5913
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463507055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1463507055
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_stress_all_with_rand_reset.3539399831
Short name	T70
Test name
Test status
Simulation time	233657027619 ps
CPU time	770.77 seconds
Started	Mar 26 02:27:32 PM PDT 24
Finished	Mar 26 02:40:23 PM PDT 24
Peak memory	216688 kb
Host	smart-9b8ec0f6-e353-446c-a1e2-eed718c140a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539399831 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3539399831
Directory	/workspace/78.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.2188433780
Short name	T219
Test name
Test status
Simulation time	12175933996 ps
CPU time	22.36 seconds
Started	Mar 26 02:27:30 PM PDT 24
Finished	Mar 26 02:27:52 PM PDT 24
Peak memory	200056 kb
Host	smart-aef96535-5cdb-4a24-8406-8339fd0df58a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188433780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2188433780
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_stress_all_with_rand_reset.3198396595
Short name	T44
Test name
Test status
Simulation time	70485502299 ps
CPU time	187.1 seconds
Started	Mar 26 02:27:29 PM PDT 24
Finished	Mar 26 02:30:36 PM PDT 24
Peak memory	216616 kb
Host	smart-fb0157f2-7ba5-47b3-aa5a-4d71a0a12620
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198396595 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3198396595
Directory	/workspace/79.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.3982339451
Short name	T47
Test name
Test status
Simulation time	44884476 ps
CPU time	0.55 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:20:24 PM PDT 24
Peak memory	195596 kb
Host	smart-eed464f7-26a0-404d-b13a-9c1a34918e9f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982339451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3982339451
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.487956861
Short name	T388
Test name
Test status
Simulation time	57506921501 ps
CPU time	17.27 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:20:41 PM PDT 24
Peak memory	199816 kb
Host	smart-9151cc56-344e-4476-a037-0258c14e6290
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487956861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.487956861
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.2113627023
Short name	T1042
Test name
Test status
Simulation time	119806444958 ps
CPU time	104.44 seconds
Started	Mar 26 02:20:26 PM PDT 24
Finished	Mar 26 02:22:11 PM PDT 24
Peak memory	199940 kb
Host	smart-1f39e012-511d-493f-9039-37d2fce03695
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113627023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2113627023
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.1933831438
Short name	T833
Test name
Test status
Simulation time	38386859411 ps
CPU time	33.6 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:20:58 PM PDT 24
Peak memory	200056 kb
Host	smart-3cb29d35-932d-4214-b015-25fd71c7ae08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933831438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1933831438
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.2524621711
Short name	T614
Test name
Test status
Simulation time	18362905542 ps
CPU time	9.59 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:35 PM PDT 24
Peak memory	199416 kb
Host	smart-fd116854-ac91-4046-ac1a-752f7e1c58b8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524621711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2524621711
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.83093607
Short name	T888
Test name
Test status
Simulation time	57265023342 ps
CPU time	165.08 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:23:09 PM PDT 24
Peak memory	199952 kb
Host	smart-2ee3ca01-8b45-43ed-9cbd-4162d624d3c6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=83093607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.83093607
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/8.uart_loopback.2787769336
Short name	T648
Test name
Test status
Simulation time	2720426439 ps
CPU time	5.27 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:31 PM PDT 24
Peak memory	196468 kb
Host	smart-3994f114-d813-43be-be32-fb96c04e8c8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2787769336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2787769336
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.2325267607
Short name	T1122
Test name
Test status
Simulation time	38688726433 ps
CPU time	16.84 seconds
Started	Mar 26 02:20:26 PM PDT 24
Finished	Mar 26 02:20:43 PM PDT 24
Peak memory	199424 kb
Host	smart-3cf41bbb-92cd-4374-9df7-a82144d89659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2325267607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2325267607
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.4103617028
Short name	T288
Test name
Test status
Simulation time	16773965016 ps
CPU time	980.59 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:36:44 PM PDT 24
Peak memory	200112 kb
Host	smart-0e9be98c-91aa-4463-afd1-a80f5b61b1b4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4103617028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.4103617028
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_oversample.176462258
Short name	T390
Test name
Test status
Simulation time	7645791156 ps
CPU time	7.11 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:20:31 PM PDT 24
Peak memory	198244 kb
Host	smart-79bf8662-c8a4-47ba-8164-28a31ae67496
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=176462258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.176462258
Directory	/workspace/8.uart_rx_oversample/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.195343365
Short name	T460
Test name
Test status
Simulation time	69110845200 ps
CPU time	36.48 seconds
Started	Mar 26 02:20:26 PM PDT 24
Finished	Mar 26 02:21:03 PM PDT 24
Peak memory	200240 kb
Host	smart-d2730ecd-6fa0-4f9f-a726-4a74b4bd20ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195343365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.195343365
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.2545681593
Short name	T691
Test name
Test status
Simulation time	4004121316 ps
CPU time	7.93 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:33 PM PDT 24
Peak memory	196160 kb
Host	smart-19d371e3-f9d9-46ff-b5f0-68231f828bde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545681593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2545681593
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.1163035732
Short name	T935
Test name
Test status
Simulation time	292442181 ps
CPU time	1.15 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:20:26 PM PDT 24
Peak memory	198556 kb
Host	smart-961b41d0-9404-4783-9000-c75d9f95f895
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163035732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1163035732
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all.2187641798
Short name	T696
Test name
Test status
Simulation time	234635792566 ps
CPU time	460.22 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:28:04 PM PDT 24
Peak memory	200040 kb
Host	smart-cd2763e2-b084-4c2e-9a83-ea70d1078478
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187641798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2187641798
Directory	/workspace/8.uart_stress_all/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.3672845094
Short name	T678
Test name
Test status
Simulation time	1571907633 ps
CPU time	2.47 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:28 PM PDT 24
Peak memory	198420 kb
Host	smart-35194a80-8570-40dd-843b-3db991aa14a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672845094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3672845094
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.3711043016
Short name	T330
Test name
Test status
Simulation time	18430967881 ps
CPU time	33.8 seconds
Started	Mar 26 02:20:28 PM PDT 24
Finished	Mar 26 02:21:02 PM PDT 24
Peak memory	200236 kb
Host	smart-517a6222-2da3-438b-b77f-c79a1e9d3856
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711043016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3711043016
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.3133869734
Short name	T1020
Test name
Test status
Simulation time	40271692081 ps
CPU time	65.95 seconds
Started	Mar 26 02:27:32 PM PDT 24
Finished	Mar 26 02:28:38 PM PDT 24
Peak memory	200044 kb
Host	smart-78a447cb-8516-4d80-ba88-6895ecd48ce6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133869734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3133869734
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.2979194027
Short name	T899
Test name
Test status
Simulation time	87650041009 ps
CPU time	76.3 seconds
Started	Mar 26 02:27:30 PM PDT 24
Finished	Mar 26 02:28:46 PM PDT 24
Peak memory	200060 kb
Host	smart-5a8ccc75-b6ee-44a2-8121-bf7a26c926da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979194027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2979194027
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.1101080140
Short name	T186
Test name
Test status
Simulation time	68415450767 ps
CPU time	108.48 seconds
Started	Mar 26 02:27:30 PM PDT 24
Finished	Mar 26 02:29:18 PM PDT 24
Peak memory	200080 kb
Host	smart-243247fa-385a-4011-9199-ff2478ba454b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101080140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1101080140
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.2662873315
Short name	T273
Test name
Test status
Simulation time	89633689660 ps
CPU time	45.52 seconds
Started	Mar 26 02:27:40 PM PDT 24
Finished	Mar 26 02:28:25 PM PDT 24
Peak memory	199972 kb
Host	smart-6399bae3-1743-4b31-895f-103e29b02239
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662873315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2662873315
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.222294599
Short name	T215
Test name
Test status
Simulation time	214161878969 ps
CPU time	324.03 seconds
Started	Mar 26 02:27:38 PM PDT 24
Finished	Mar 26 02:33:03 PM PDT 24
Peak memory	200104 kb
Host	smart-1007ed2a-4e43-41bc-9177-4a1758ee650e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=222294599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.222294599
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.3174613075
Short name	T221
Test name
Test status
Simulation time	102177897521 ps
CPU time	178.24 seconds
Started	Mar 26 02:27:38 PM PDT 24
Finished	Mar 26 02:30:36 PM PDT 24
Peak memory	200080 kb
Host	smart-6e69f705-8927-4ef7-ac10-1242abe46c96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174613075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3174613075
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.3436006494
Short name	T767
Test name
Test status
Simulation time	48178582074 ps
CPU time	74.27 seconds
Started	Mar 26 02:27:38 PM PDT 24
Finished	Mar 26 02:28:52 PM PDT 24
Peak memory	199996 kb
Host	smart-7742b8d9-db09-4fa4-87af-6068ddab2908
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436006494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3436006494
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_stress_all_with_rand_reset.6765748
Short name	T939
Test name
Test status
Simulation time	69695579681 ps
CPU time	220.06 seconds
Started	Mar 26 02:27:49 PM PDT 24
Finished	Mar 26 02:31:30 PM PDT 24
Peak memory	215836 kb
Host	smart-6d74a3e0-25d2-4ce2-a7e1-4978c55fd79c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6765748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.6765748
Directory	/workspace/87.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.1243337753
Short name	T867
Test name
Test status
Simulation time	83428886921 ps
CPU time	36.75 seconds
Started	Mar 26 02:27:51 PM PDT 24
Finished	Mar 26 02:28:28 PM PDT 24
Peak memory	200044 kb
Host	smart-1ac21d25-1152-4e64-8a44-e6aac4dfab08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243337753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1243337753
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.2686976896
Short name	T233
Test name
Test status
Simulation time	126811454498 ps
CPU time	148.47 seconds
Started	Mar 26 02:27:52 PM PDT 24
Finished	Mar 26 02:30:21 PM PDT 24
Peak memory	200100 kb
Host	smart-ea07362f-5979-46de-9f29-02fcaeb8e773
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686976896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2686976896
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_stress_all_with_rand_reset.4120605340
Short name	T126
Test name
Test status
Simulation time	13073583493 ps
CPU time	112.16 seconds
Started	Mar 26 02:27:51 PM PDT 24
Finished	Mar 26 02:29:43 PM PDT 24
Peak memory	215696 kb
Host	smart-09fe6155-50c2-4f22-9aa1-ed5d728dcd7e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120605340 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.4120605340
Directory	/workspace/89.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.4123743744
Short name	T36
Test name
Test status
Simulation time	13580401 ps
CPU time	0.64 seconds
Started	Mar 26 02:20:42 PM PDT 24
Finished	Mar 26 02:20:43 PM PDT 24
Peak memory	195056 kb
Host	smart-b5a33a42-9154-492f-9cdb-f6a374e31a6c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123743744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4123743744
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.75791909
Short name	T746
Test name
Test status
Simulation time	6453550739 ps
CPU time	10.4 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:36 PM PDT 24
Peak memory	200104 kb
Host	smart-65e8f96d-ea89-459e-b3f7-384b4720c3ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75791909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.75791909
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.383302643
Short name	T324
Test name
Test status
Simulation time	94433607698 ps
CPU time	116.33 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:22:21 PM PDT 24
Peak memory	200044 kb
Host	smart-4a21d9eb-f979-48f4-b897-239036946141
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383302643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.383302643
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.1066027723
Short name	T89
Test name
Test status
Simulation time	8840803404 ps
CPU time	16.48 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:20:41 PM PDT 24
Peak memory	200040 kb
Host	smart-94991adc-d589-4084-a348-cb1544bde3c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066027723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1066027723
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_intr.3675024778
Short name	T503
Test name
Test status
Simulation time	32631633351 ps
CPU time	68.22 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:21:34 PM PDT 24
Peak memory	199840 kb
Host	smart-6f574a86-b8c7-49c8-800e-fa0977716c09
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675024778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3675024778
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.2804199044
Short name	T430
Test name
Test status
Simulation time	105479693603 ps
CPU time	603.09 seconds
Started	Mar 26 02:20:24 PM PDT 24
Finished	Mar 26 02:30:27 PM PDT 24
Peak memory	199940 kb
Host	smart-ec8d2465-7827-43a9-9a57-af1511081d13
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2804199044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2804199044
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.3202946224
Short name	T375
Test name
Test status
Simulation time	5405997096 ps
CPU time	8.1 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:20:32 PM PDT 24
Peak memory	200032 kb
Host	smart-e9722fc3-a17b-44cb-9713-4504a71c07dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202946224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3202946224
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.1376563753
Short name	T731
Test name
Test status
Simulation time	30990438263 ps
CPU time	69.75 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:21:35 PM PDT 24
Peak memory	200272 kb
Host	smart-65cf9dca-1c1b-4727-9d6d-33fb816e6690
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376563753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1376563753
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.1045552179
Short name	T1005
Test name
Test status
Simulation time	15746466635 ps
CPU time	121.74 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:22:25 PM PDT 24
Peak memory	200064 kb
Host	smart-25aadab3-04da-4def-8546-210282dcfed0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1045552179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1045552179
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_oversample.4254652288
Short name	T420
Test name
Test status
Simulation time	3459630823 ps
CPU time	28.64 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:20:52 PM PDT 24
Peak memory	198216 kb
Host	smart-d920c3e0-d099-4296-ad2c-01c57eb371da
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4254652288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4254652288
Directory	/workspace/9.uart_rx_oversample/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.2981294017
Short name	T841
Test name
Test status
Simulation time	5130949034 ps
CPU time	9.91 seconds
Started	Mar 26 02:20:26 PM PDT 24
Finished	Mar 26 02:20:36 PM PDT 24
Peak memory	200100 kb
Host	smart-927e5c51-99f2-4b41-b333-b00cb364670d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981294017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2981294017
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.2607631529
Short name	T794
Test name
Test status
Simulation time	4630513660 ps
CPU time	7.74 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:32 PM PDT 24
Peak memory	196116 kb
Host	smart-9ee8d353-a980-45c2-8681-1b0732a92bc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607631529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2607631529
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.4132878425
Short name	T1044
Test name
Test status
Simulation time	507231041 ps
CPU time	2.47 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:28 PM PDT 24
Peak memory	198260 kb
Host	smart-9edad129-aaf7-429a-8f04-81feb623bf3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132878425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4132878425
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all.3073473415
Short name	T538
Test name
Test status
Simulation time	170601458136 ps
CPU time	268.84 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:24:54 PM PDT 24
Peak memory	208436 kb
Host	smart-f782a625-f595-4762-abeb-5c6b91a6b6b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073473415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3073473415
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.3442186759
Short name	T695
Test name
Test status
Simulation time	402182109 ps
CPU time	1.5 seconds
Started	Mar 26 02:20:23 PM PDT 24
Finished	Mar 26 02:20:25 PM PDT 24
Peak memory	198512 kb
Host	smart-c6b8b58b-99f8-4d43-b86a-6d668da68323
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442186759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3442186759
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.1769790316
Short name	T306
Test name
Test status
Simulation time	21111778889 ps
CPU time	33.05 seconds
Started	Mar 26 02:20:25 PM PDT 24
Finished	Mar 26 02:20:58 PM PDT 24
Peak memory	197936 kb
Host	smart-54e01b88-2ff8-4ec9-9d29-752921c46bb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769790316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1769790316
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.1152282566
Short name	T249
Test name
Test status
Simulation time	17798854708 ps
CPU time	12.27 seconds
Started	Mar 26 02:27:49 PM PDT 24
Finished	Mar 26 02:28:01 PM PDT 24
Peak memory	198512 kb
Host	smart-f16fd3b8-4d31-4bbb-9f2c-14668acaffc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152282566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1152282566
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.9299006
Short name	T1080
Test name
Test status
Simulation time	33363753968 ps
CPU time	54.46 seconds
Started	Mar 26 02:27:51 PM PDT 24
Finished	Mar 26 02:28:46 PM PDT 24
Peak memory	199936 kb
Host	smart-d66c4d8f-bcfd-4576-88c9-9b5667873f83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9299006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.9299006
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.3356561959
Short name	T250
Test name
Test status
Simulation time	41236992547 ps
CPU time	77.45 seconds
Started	Mar 26 02:27:53 PM PDT 24
Finished	Mar 26 02:29:11 PM PDT 24
Peak memory	200048 kb
Host	smart-35e3b93a-1555-45fb-ade2-40589c97395f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356561959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3356561959
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.857691578
Short name	T222
Test name
Test status
Simulation time	22902239631 ps
CPU time	33.2 seconds
Started	Mar 26 02:27:49 PM PDT 24
Finished	Mar 26 02:28:22 PM PDT 24
Peak memory	200080 kb
Host	smart-0e19ee2c-9d19-4e00-888a-f6b38e452cf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857691578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.857691578
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_stress_all_with_rand_reset.3937382003
Short name	T349
Test name
Test status
Simulation time	30346909391 ps
CPU time	80 seconds
Started	Mar 26 02:28:00 PM PDT 24
Finished	Mar 26 02:29:20 PM PDT 24
Peak memory	216772 kb
Host	smart-1d235e13-1a15-434e-8f32-3f6bbfc27aa0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937382003 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3937382003
Directory	/workspace/93.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.1867283323
Short name	T543
Test name
Test status
Simulation time	8989179402 ps
CPU time	14.62 seconds
Started	Mar 26 02:28:00 PM PDT 24
Finished	Mar 26 02:28:15 PM PDT 24
Peak memory	200016 kb
Host	smart-f9a3908f-1288-4f6a-a0f8-d8820144043d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867283323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1867283323
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.1899461371
Short name	T1123
Test name
Test status
Simulation time	42989719745 ps
CPU time	21.4 seconds
Started	Mar 26 02:28:00 PM PDT 24
Finished	Mar 26 02:28:22 PM PDT 24
Peak memory	200016 kb
Host	smart-35d93fc7-954c-4b00-9b11-4cf9c76a2924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899461371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1899461371
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.3145712340
Short name	T477
Test name
Test status
Simulation time	101843528428 ps
CPU time	79.22 seconds
Started	Mar 26 02:27:58 PM PDT 24
Finished	Mar 26 02:29:17 PM PDT 24
Peak memory	200000 kb
Host	smart-107ee76b-8f81-4058-a21e-bd8c6a25b67e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145712340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3145712340
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/96.uart_stress_all_with_rand_reset.2685336917
Short name	T127
Test name
Test status
Simulation time	25993234158 ps
CPU time	115.73 seconds
Started	Mar 26 02:27:58 PM PDT 24
Finished	Mar 26 02:29:54 PM PDT 24
Peak memory	209724 kb
Host	smart-05b37e7b-42f5-49bf-801b-f741e1f71819
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685336917 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2685336917
Directory	/workspace/96.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.1083440984
Short name	T966
Test name
Test status
Simulation time	226957653276 ps
CPU time	85.22 seconds
Started	Mar 26 02:27:59 PM PDT 24
Finished	Mar 26 02:29:25 PM PDT 24
Peak memory	200040 kb
Host	smart-c5fe89af-a405-46a3-a6ef-4cff2df3c062
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083440984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1083440984
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_stress_all_with_rand_reset.1977943663
Short name	T122
Test name
Test status
Simulation time	49679301945 ps
CPU time	311.2 seconds
Started	Mar 26 02:28:06 PM PDT 24
Finished	Mar 26 02:33:18 PM PDT 24
Peak memory	213668 kb
Host	smart-5a7111ea-edcc-4daf-bd92-b2a7bc9e5bec
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977943663 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1977943663
Directory	/workspace/97.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.2606509637
Short name	T366
Test name
Test status
Simulation time	34772249695 ps
CPU time	12.81 seconds
Started	Mar 26 02:28:09 PM PDT 24
Finished	Mar 26 02:28:22 PM PDT 24
Peak memory	200040 kb
Host	smart-7aca27c6-a978-41cd-a2de-080db3d3f3aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606509637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2606509637
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_stress_all_with_rand_reset.676027049
Short name	T352
Test name
Test status
Simulation time	54028886224 ps
CPU time	660.48 seconds
Started	Mar 26 02:28:08 PM PDT 24
Finished	Mar 26 02:39:08 PM PDT 24
Peak memory	224944 kb
Host	smart-ad3a29bc-0831-4e8a-9787-a5ddc04ec4b4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676027049 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.676027049
Directory	/workspace/98.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.525136643
Short name	T248
Test name
Test status
Simulation time	95280100120 ps
CPU time	41.96 seconds
Started	Mar 26 02:28:09 PM PDT 24
Finished	Mar 26 02:28:51 PM PDT 24
Peak memory	199932 kb
Host	smart-eb42ac1f-d82d-482b-8843-508223dfb5a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525136643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.525136643
Directory	/workspace/99.uart_fifo_reset/latest

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