Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78102679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31195294

1

T1

98

T2

89

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	98538211	1			T1	324		T2	1144		T3	32
values[0x0]	5083720	1			T1	76		T2	99		T3	10
values[0x1]	5676042	1			T1	77		T2	100		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54127047	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

55170926

1

T1

200

T2

471

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	387498	1			T1	2		T2	5		T4	10
valid_sources[0x01]	456849	1			T1	2		T2	7		T4	12
valid_sources[0x02]	390376	1			T2	6		T3	7		T4	11
valid_sources[0x03]	403380	1			T1	2		T2	5		T4	7
valid_sources[0x04]	419607	1			T1	2		T2	6		T4	15
valid_sources[0x05]	407468	1			T1	1		T2	12		T4	8
valid_sources[0x06]	623290	1			T1	4		T2	7		T3	3
valid_sources[0x07]	449596	1			T1	1		T2	5		T4	8
valid_sources[0x08]	405081	1			T1	3		T2	2		T4	9
valid_sources[0x09]	400656	1			T1	4		T2	2		T4	10
valid_sources[0x0a]	424731	1			T1	1		T2	5		T4	12
valid_sources[0x0b]	403893	1			T1	8		T2	6		T4	7
valid_sources[0x0c]	448744	1			T2	3		T4	15		T5	30
valid_sources[0x0d]	400067	1			T1	1		T2	6		T4	5
valid_sources[0x0e]	442562	1			T1	4		T2	5		T4	18
valid_sources[0x0f]	406505	1			T1	6		T2	10		T4	8
valid_sources[0x10]	412430	1			T1	1		T2	5		T4	14
valid_sources[0x11]	391092	1			T1	1		T2	7		T4	18
valid_sources[0x12]	401424	1			T1	1		T2	3		T4	14
valid_sources[0x13]	445678	1			T1	2		T2	7		T3	2
valid_sources[0x14]	421008	1			T1	1		T2	5		T4	13
valid_sources[0x15]	389163	1			T1	1		T2	4		T4	8
valid_sources[0x16]	394424	1			T1	1		T2	6		T4	11
valid_sources[0x17]	414829	1			T2	7		T4	7		T5	22
valid_sources[0x18]	471405	1			T1	9		T2	10		T4	10
valid_sources[0x19]	429429	1			T1	2		T2	4		T4	8
valid_sources[0x1a]	419630	1			T1	1		T2	7		T4	17
valid_sources[0x1b]	449846	1			T1	3		T2	3		T4	15
valid_sources[0x1c]	406599	1			T1	1		T2	3		T4	6
valid_sources[0x1d]	428740	1			T1	3		T2	6		T4	11
valid_sources[0x1e]	443671	1			T1	5		T2	7		T4	10
valid_sources[0x1f]	437978	1			T1	1		T2	4		T4	4
valid_sources[0x20]	399891	1			T1	2		T2	6		T4	7
valid_sources[0x21]	413979	1			T1	3		T2	4		T4	14
valid_sources[0x22]	436073	1			T1	1		T2	4		T4	12
valid_sources[0x23]	446016	1			T2	3		T4	15		T5	29
valid_sources[0x24]	399346	1			T1	1		T2	7		T4	2
valid_sources[0x25]	462697	1			T2	4		T4	9		T5	24
valid_sources[0x26]	421230	1			T2	6		T4	8		T5	33
valid_sources[0x27]	491554	1			T1	3		T2	4		T4	4
valid_sources[0x28]	396784	1			T1	2		T2	7		T4	13
valid_sources[0x29]	432744	1			T1	2		T2	4		T4	9
valid_sources[0x2a]	400328	1			T2	6		T4	5		T5	44
valid_sources[0x2b]	418352	1			T2	4		T4	11		T5	33
valid_sources[0x2c]	437285	1			T1	2		T4	10		T5	27
valid_sources[0x2d]	432854	1			T1	3		T2	1		T4	12
valid_sources[0x2e]	410857	1			T2	7		T4	15		T5	31
valid_sources[0x2f]	448198	1			T2	3		T4	7		T5	23
valid_sources[0x30]	406282	1			T2	9		T4	17		T5	30
valid_sources[0x31]	389351	1			T1	2		T2	4		T4	7
valid_sources[0x32]	402419	1			T2	6		T4	6		T5	33
valid_sources[0x33]	411030	1			T1	2		T2	7		T4	14
valid_sources[0x34]	395453	1			T1	1		T2	4		T4	3
valid_sources[0x35]	395364	1			T2	4		T4	11		T5	30
valid_sources[0x36]	389367	1			T1	4		T2	3		T4	9
valid_sources[0x37]	398354	1			T1	2		T2	5		T4	4
valid_sources[0x38]	420878	1			T1	1		T2	3		T4	6
valid_sources[0x39]	437724	1			T1	2		T2	4		T4	6
valid_sources[0x3a]	447145	1			T1	2		T2	6		T4	7
valid_sources[0x3b]	389926	1			T1	1		T2	4		T3	1
valid_sources[0x3c]	419907	1			T1	6		T2	6		T4	10
valid_sources[0x3d]	421408	1			T1	3		T2	3		T4	13
valid_sources[0x3e]	516604	1			T1	4		T2	2		T4	14
valid_sources[0x3f]	496825	1			T1	1		T2	9		T4	3
valid_sources[0x40]	433461	1			T1	3		T2	6		T4	11
valid_sources[0x41]	396729	1			T1	2		T2	7		T4	4
valid_sources[0x42]	386342	1			T2	6		T4	7		T5	34
valid_sources[0x43]	397069	1			T1	1		T2	5		T4	4
valid_sources[0x44]	425339	1			T1	3		T2	5		T4	6
valid_sources[0x45]	397027	1			T2	6		T4	9		T5	33
valid_sources[0x46]	530895	1			T1	3		T2	4		T4	10
valid_sources[0x47]	449444	1			T1	4		T2	5		T4	13
valid_sources[0x48]	468787	1			T1	2		T2	6		T3	1
valid_sources[0x49]	403486	1			T1	4		T2	4		T4	13
valid_sources[0x4a]	402428	1			T1	1		T2	12		T4	14
valid_sources[0x4b]	421205	1			T2	5		T4	5		T5	28
valid_sources[0x4c]	563724	1			T1	1		T2	10		T3	2
valid_sources[0x4d]	407643	1			T1	3		T2	8		T4	4
valid_sources[0x4e]	409784	1			T2	1		T4	7		T5	29
valid_sources[0x4f]	396089	1			T2	3		T3	1		T4	13
valid_sources[0x50]	422621	1			T1	7		T2	6		T4	10
valid_sources[0x51]	403723	1			T1	3		T2	7		T4	10
valid_sources[0x52]	423417	1			T1	1		T2	7		T4	10
valid_sources[0x53]	403911	1			T1	3		T2	8		T4	6
valid_sources[0x54]	416196	1			T2	4		T3	2		T4	9
valid_sources[0x55]	417533	1			T1	4		T2	5		T3	3
valid_sources[0x56]	391564	1			T1	4		T2	4		T4	3
valid_sources[0x57]	421458	1			T1	1		T2	5		T4	4
valid_sources[0x58]	417241	1			T1	1		T2	2		T4	5
valid_sources[0x59]	485747	1			T2	3		T4	10		T5	29
valid_sources[0x5a]	393712	1			T2	9		T4	19		T5	37
valid_sources[0x5b]	404455	1			T1	5		T2	4		T4	12
valid_sources[0x5c]	401941	1			T1	4		T2	3		T4	7
valid_sources[0x5d]	449122	1			T2	6		T4	12		T5	42
valid_sources[0x5e]	442661	1			T1	3		T2	2		T4	7
valid_sources[0x5f]	400515	1			T1	2		T2	5		T4	5
valid_sources[0x60]	454703	1			T1	1		T2	9		T4	10
valid_sources[0x61]	452536	1			T1	3		T2	7		T4	4
valid_sources[0x62]	448565	1			T1	4		T2	7		T4	11
valid_sources[0x63]	414505	1			T1	1		T2	5		T4	14
valid_sources[0x64]	393116	1			T2	4		T4	8		T5	24
valid_sources[0x65]	407575	1			T1	1		T2	7		T4	5
valid_sources[0x66]	500458	1			T1	4		T2	4		T4	8
valid_sources[0x67]	392678	1			T2	6		T4	15		T5	37
valid_sources[0x68]	467081	1			T1	1		T2	4		T4	5
valid_sources[0x69]	424790	1			T1	4		T2	4		T4	9
valid_sources[0x6a]	389483	1			T1	4		T2	6		T4	4
valid_sources[0x6b]	395782	1			T1	2		T2	4		T4	21
valid_sources[0x6c]	418836	1			T2	6		T3	1		T4	9
valid_sources[0x6d]	456218	1			T1	5		T2	4		T4	8
valid_sources[0x6e]	477848	1			T1	1		T2	1		T4	7
valid_sources[0x6f]	416466	1			T1	3		T2	5		T4	9
valid_sources[0x70]	399705	1			T1	5		T2	6		T4	7
valid_sources[0x71]	389949	1			T1	3		T2	7		T4	10
valid_sources[0x72]	396918	1			T1	4		T2	6		T4	22
valid_sources[0x73]	398513	1			T1	2		T2	1		T4	7
valid_sources[0x74]	421299	1			T1	3		T2	7		T4	5
valid_sources[0x75]	422060	1			T2	6		T3	2		T4	11
valid_sources[0x76]	383784	1			T1	2		T2	10		T4	19
valid_sources[0x77]	435091	1			T1	1		T2	10		T4	7
valid_sources[0x78]	734339	1			T1	1		T2	5		T4	10
valid_sources[0x79]	406658	1			T1	3		T2	3		T4	7
valid_sources[0x7a]	594298	1			T1	3		T2	2		T4	10
valid_sources[0x7b]	395099	1			T1	2		T2	2		T4	10
valid_sources[0x7c]	421586	1			T1	1		T2	4		T4	9
valid_sources[0x7d]	444688	1			T1	1		T2	5		T4	11
valid_sources[0x7e]	382327	1			T1	1		T2	5		T4	6
valid_sources[0x7f]	397114	1			T1	1		T2	6		T4	11
valid_sources[0x80]	420543	1			T1	3		T2	5		T4	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21643015

1

T1

46

T2

27

T3

6

values[0x0]

all_enables

biggest_size

4804284

1

T1

31

T2

41

T3

4

values[0x1]

all_enables

biggest_size

4747995

1

T1

21

T2

21

T3

1