Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15724593	0	0
ctrl_rd_A	2147483647	347385	0	0
intr_enable_rd_A	2147483647	305392	0	0
ovrd_rd_A	2147483647	345825	0	0
timeout_ctrl_rd_A	2147483647	343775	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15724593	0	0
T7	620987	247086	0	0
T8	502527	163216	0	0
T9	495839	0	0	0
T10	137243	0	0	0
T11	617293	85151	0	0
T12	0	56931	0	0
T13	0	423080	0	0
T18	507822	0	0	0
T21	189907	77608	0	0
T22	264289	86311	0	0
T29	0	146766	0	0
T30	0	73873	0	0
T31	0	162664	0	0
T32	240112	0	0	0
T33	131776	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347385	0	0
T8	502527	7278	0	0
T9	495839	0	0	0
T10	137243	0	0	0
T11	617293	9829	0	0
T12	0	6509	0	0
T18	507822	0	0	0
T21	189907	0	0	0
T22	264289	3514	0	0
T31	0	19134	0	0
T32	240112	0	0	0
T33	131776	0	0	0
T34	973872	0	0	0
T41	0	16193	0	0
T97	0	4043	0	0
T98	0	8819	0	0
T99	0	9962	0	0
T100	0	8788	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	305392	0	0
T8	502527	6357	0	0
T9	495839	0	0	0
T10	137243	0	0	0
T11	617293	8911	0	0
T12	0	5581	0	0
T18	507822	0	0	0
T21	189907	0	0	0
T22	264289	3421	0	0
T31	0	16633	0	0
T32	240112	0	0	0
T33	131776	0	0	0
T34	973872	0	0	0
T41	0	15034	0	0
T97	0	3596	0	0
T98	0	7546	0	0
T99	0	8523	0	0
T100	0	7984	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345825	0	0
T8	502527	7254	0	0
T9	495839	0	0	0
T10	137243	0	0	0
T11	617293	10097	0	0
T12	0	6726	0	0
T18	507822	0	0	0
T21	189907	0	0	0
T22	264289	3419	0	0
T31	0	18623	0	0
T32	240112	0	0	0
T33	131776	0	0	0
T34	973872	0	0	0
T41	0	16561	0	0
T97	0	4410	0	0
T98	0	8713	0	0
T99	0	10692	0	0
T100	0	8820	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	343775	0	0
T8	502527	7434	0	0
T9	495839	0	0	0
T10	137243	0	0	0
T11	617293	10305	0	0
T12	0	6279	0	0
T18	507822	0	0	0
T21	189907	0	0	0
T22	264289	3826	0	0
T31	0	18601	0	0
T32	240112	0	0	0
T33	131776	0	0	0
T34	973872	0	0	0
T41	0	15863	0	0
T97	0	4058	0	0
T98	0	8968	0	0
T99	0	10067	0	0
T100	0	8858	0	0