Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.59


Total test records in report: 1319
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T1260 /workspace/coverage/cover_reg_top/20.uart_intr_test.4291016197 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:37 PM PDT 24 27337637 ps
T1261 /workspace/coverage/cover_reg_top/5.uart_intr_test.562074788 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:37 PM PDT 24 51769847 ps
T1262 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3420150699 Mar 28 12:31:35 PM PDT 24 Mar 28 12:31:42 PM PDT 24 44502853 ps
T1263 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3114107708 Mar 28 12:31:35 PM PDT 24 Mar 28 12:31:35 PM PDT 24 52053756 ps
T1264 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3941984682 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:37 PM PDT 24 76062966 ps
T1265 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3808519006 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:38 PM PDT 24 105798376 ps
T1266 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3186528648 Mar 28 12:31:32 PM PDT 24 Mar 28 12:31:34 PM PDT 24 396863448 ps
T1267 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2215200292 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:29 PM PDT 24 20001626 ps
T1268 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1883650206 Mar 28 12:31:32 PM PDT 24 Mar 28 12:31:32 PM PDT 24 11653564 ps
T1269 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3897670446 Mar 28 12:31:38 PM PDT 24 Mar 28 12:31:39 PM PDT 24 14827225 ps
T1270 /workspace/coverage/cover_reg_top/31.uart_intr_test.2289170223 Mar 28 12:32:03 PM PDT 24 Mar 28 12:32:03 PM PDT 24 47914995 ps
T1271 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4277547681 Mar 28 12:31:24 PM PDT 24 Mar 28 12:31:25 PM PDT 24 37161274 ps
T1272 /workspace/coverage/cover_reg_top/18.uart_intr_test.1396223925 Mar 28 12:31:33 PM PDT 24 Mar 28 12:31:34 PM PDT 24 38596869 ps
T1273 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2523365080 Mar 28 12:31:26 PM PDT 24 Mar 28 12:31:29 PM PDT 24 26930127 ps
T1274 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1866149929 Mar 28 12:31:29 PM PDT 24 Mar 28 12:31:30 PM PDT 24 31927642 ps
T1275 /workspace/coverage/cover_reg_top/26.uart_intr_test.1999867343 Mar 28 12:32:15 PM PDT 24 Mar 28 12:32:19 PM PDT 24 12534746 ps
T1276 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3243138821 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:39 PM PDT 24 980507714 ps
T1277 /workspace/coverage/cover_reg_top/40.uart_intr_test.3350895770 Mar 28 12:31:51 PM PDT 24 Mar 28 12:31:52 PM PDT 24 23276013 ps
T1278 /workspace/coverage/cover_reg_top/49.uart_intr_test.2224465955 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:37 PM PDT 24 12426065 ps
T60 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1878579797 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:40 PM PDT 24 47126058 ps
T65 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1361344952 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:35 PM PDT 24 27713560 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.288940640 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:29 PM PDT 24 75265409 ps
T1280 /workspace/coverage/cover_reg_top/6.uart_intr_test.3591063317 Mar 28 12:31:22 PM PDT 24 Mar 28 12:31:23 PM PDT 24 35816111 ps
T1281 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3793760403 Mar 28 12:31:25 PM PDT 24 Mar 28 12:31:27 PM PDT 24 42724970 ps
T1282 /workspace/coverage/cover_reg_top/45.uart_intr_test.547413045 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:41 PM PDT 24 49978228 ps
T1283 /workspace/coverage/cover_reg_top/36.uart_intr_test.2810834784 Mar 28 12:31:32 PM PDT 24 Mar 28 12:31:32 PM PDT 24 10782124 ps
T1284 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2159774936 Mar 28 12:31:27 PM PDT 24 Mar 28 12:31:28 PM PDT 24 89439245 ps
T1285 /workspace/coverage/cover_reg_top/32.uart_intr_test.3153306775 Mar 28 12:31:41 PM PDT 24 Mar 28 12:31:42 PM PDT 24 15903042 ps
T1286 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2587320801 Mar 28 12:31:40 PM PDT 24 Mar 28 12:31:42 PM PDT 24 32816357 ps
T1287 /workspace/coverage/cover_reg_top/23.uart_intr_test.200746365 Mar 28 12:31:38 PM PDT 24 Mar 28 12:31:39 PM PDT 24 30671972 ps
T1288 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.620182208 Mar 28 12:31:27 PM PDT 24 Mar 28 12:31:28 PM PDT 24 65898448 ps
T1289 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2082574211 Mar 28 12:31:26 PM PDT 24 Mar 28 12:31:27 PM PDT 24 15946658 ps
T1290 /workspace/coverage/cover_reg_top/3.uart_intr_test.1052130883 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:41 PM PDT 24 12266857 ps
T1291 /workspace/coverage/cover_reg_top/17.uart_intr_test.1792479550 Mar 28 12:31:59 PM PDT 24 Mar 28 12:31:59 PM PDT 24 45351519 ps
T1292 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2843614924 Mar 28 12:31:35 PM PDT 24 Mar 28 12:31:35 PM PDT 24 10928779 ps
T1293 /workspace/coverage/cover_reg_top/44.uart_intr_test.4281583408 Mar 28 12:31:35 PM PDT 24 Mar 28 12:31:35 PM PDT 24 33969870 ps
T1294 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3902743731 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:38 PM PDT 24 18856492 ps
T1295 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2467942954 Mar 28 12:31:30 PM PDT 24 Mar 28 12:31:31 PM PDT 24 16200355 ps
T1296 /workspace/coverage/cover_reg_top/28.uart_intr_test.3258304220 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:39 PM PDT 24 13507451 ps
T1297 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2506155691 Mar 28 12:31:31 PM PDT 24 Mar 28 12:31:32 PM PDT 24 93793946 ps
T1298 /workspace/coverage/cover_reg_top/4.uart_intr_test.3608054098 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:34 PM PDT 24 29735009 ps
T1299 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3102246833 Mar 28 12:31:25 PM PDT 24 Mar 28 12:31:27 PM PDT 24 36887435 ps
T61 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.392908735 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:38 PM PDT 24 37241882 ps
T1300 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2049248754 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:34 PM PDT 24 43175456 ps
T1301 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2423595168 Mar 28 12:31:30 PM PDT 24 Mar 28 12:31:31 PM PDT 24 78907146 ps
T1302 /workspace/coverage/cover_reg_top/11.uart_tl_errors.888104236 Mar 28 12:31:24 PM PDT 24 Mar 28 12:31:26 PM PDT 24 473458320 ps
T1303 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2432415549 Mar 28 12:31:23 PM PDT 24 Mar 28 12:31:24 PM PDT 24 24423703 ps
T1304 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3924788440 Mar 28 12:31:44 PM PDT 24 Mar 28 12:31:45 PM PDT 24 176307886 ps
T85 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.301183092 Mar 28 12:31:27 PM PDT 24 Mar 28 12:31:28 PM PDT 24 146114195 ps
T1305 /workspace/coverage/cover_reg_top/42.uart_intr_test.1588462954 Mar 28 12:31:59 PM PDT 24 Mar 28 12:32:00 PM PDT 24 20099097 ps
T62 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2386887802 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:35 PM PDT 24 37056271 ps
T1306 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.776777576 Mar 28 12:31:40 PM PDT 24 Mar 28 12:31:42 PM PDT 24 19345593 ps
T1307 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3475936653 Mar 28 12:31:32 PM PDT 24 Mar 28 12:31:33 PM PDT 24 69548955 ps
T1308 /workspace/coverage/cover_reg_top/41.uart_intr_test.2289307630 Mar 28 12:31:32 PM PDT 24 Mar 28 12:31:33 PM PDT 24 53817545 ps
T1309 /workspace/coverage/cover_reg_top/10.uart_intr_test.209184824 Mar 28 12:31:28 PM PDT 24 Mar 28 12:31:28 PM PDT 24 13069770 ps
T1310 /workspace/coverage/cover_reg_top/48.uart_intr_test.170620753 Mar 28 12:31:41 PM PDT 24 Mar 28 12:31:42 PM PDT 24 18621325 ps
T1311 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1943202875 Mar 28 12:31:38 PM PDT 24 Mar 28 12:31:39 PM PDT 24 33202501 ps
T1312 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2380028666 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:38 PM PDT 24 20111865 ps
T1313 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3939657680 Mar 28 12:31:33 PM PDT 24 Mar 28 12:31:34 PM PDT 24 65805672 ps
T81 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3187462817 Mar 28 12:31:33 PM PDT 24 Mar 28 12:31:34 PM PDT 24 76199666 ps
T1314 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2784882320 Mar 28 12:31:40 PM PDT 24 Mar 28 12:31:46 PM PDT 24 64654505 ps
T1315 /workspace/coverage/cover_reg_top/14.uart_tl_errors.689311801 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:38 PM PDT 24 20662579 ps
T63 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3774511745 Mar 28 12:31:33 PM PDT 24 Mar 28 12:31:34 PM PDT 24 46565842 ps
T1316 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2527399095 Mar 28 12:31:40 PM PDT 24 Mar 28 12:31:43 PM PDT 24 168834493 ps
T1317 /workspace/coverage/cover_reg_top/22.uart_intr_test.801484992 Mar 28 12:31:45 PM PDT 24 Mar 28 12:31:46 PM PDT 24 22514042 ps
T64 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.577455642 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:39 PM PDT 24 1038294532 ps
T80 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3311541702 Mar 28 12:31:40 PM PDT 24 Mar 28 12:31:42 PM PDT 24 84183924 ps
T1318 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1160001236 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:37 PM PDT 24 15819596 ps
T1319 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3200948870 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:11 PM PDT 24 52347974 ps

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3899119528
Short name T7
Test name
Test status
Simulation time 258746787694 ps
CPU time 1044.35 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 02:04:18 PM PDT 24
Peak memory 225588 kb
Host smart-5ce3e4eb-0989-4e67-9dcf-3fd85987cf8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899119528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3899119528
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2966910602
Short name T13
Test name
Test status
Simulation time 546570765401 ps
CPU time 1521.64 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 02:12:27 PM PDT 24
Peak memory 230620 kb
Host smart-369eada7-12ef-4d60-bfb0-a796c34f4dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966910602 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2966910602
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.811006414
Short name T10
Test name
Test status
Simulation time 137243192102 ps
CPU time 1146.14 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 02:04:46 PM PDT 24
Peak memory 200560 kb
Host smart-18f81a64-dc2b-44e1-bacd-282168c0a992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811006414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.811006414
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2950131257
Short name T31
Test name
Test status
Simulation time 77336599491 ps
CPU time 676.19 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 02:00:02 PM PDT 24
Peak memory 216908 kb
Host smart-5c256b1d-6e7c-41ea-8e4b-0931621ce08d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950131257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2950131257
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.216015060
Short name T20
Test name
Test status
Simulation time 410160627148 ps
CPU time 144.03 seconds
Started Mar 28 01:46:48 PM PDT 24
Finished Mar 28 01:49:12 PM PDT 24
Peak memory 200444 kb
Host smart-74b6e1bc-7445-415e-ae08-eaa98b65a7b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216015060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.216015060
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_sec_cm.234272991
Short name T26
Test name
Test status
Simulation time 222257619 ps
CPU time 0.92 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 01:44:57 PM PDT 24
Peak memory 218944 kb
Host smart-2ad70546-27db-462c-8287-5bfcbdd1554e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234272991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.234272991
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2638854381
Short name T11
Test name
Test status
Simulation time 257207616643 ps
CPU time 373.04 seconds
Started Mar 28 01:48:57 PM PDT 24
Finished Mar 28 01:55:10 PM PDT 24
Peak memory 216992 kb
Host smart-7fe997b1-ef72-4c5f-a474-36de38a893d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638854381 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2638854381
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.969811378
Short name T100
Test name
Test status
Simulation time 352929272053 ps
CPU time 1152.96 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 02:08:04 PM PDT 24
Peak memory 225824 kb
Host smart-ea690463-60d0-4af7-909e-3fa57e083eb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969811378 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.969811378
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.746802063
Short name T125
Test name
Test status
Simulation time 162691833080 ps
CPU time 348.48 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:55:38 PM PDT 24
Peak memory 200500 kb
Host smart-1ceecbe6-8ca5-44e7-acdb-69ad823eba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746802063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.746802063
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.776334665
Short name T277
Test name
Test status
Simulation time 298018661401 ps
CPU time 32.16 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:47:24 PM PDT 24
Peak memory 200528 kb
Host smart-f937cea4-427c-4952-a97a-14d4ec610101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776334665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.776334665
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1725493300
Short name T99
Test name
Test status
Simulation time 228150089771 ps
CPU time 939.49 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 02:04:30 PM PDT 24
Peak memory 225444 kb
Host smart-3b30723a-88eb-4e97-87d0-dce40961b0a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725493300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1725493300
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.370138042
Short name T175
Test name
Test status
Simulation time 211000220989 ps
CPU time 1273.44 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 02:10:00 PM PDT 24
Peak memory 230116 kb
Host smart-5590678d-bc63-4980-ad6f-69767a106da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370138042 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.370138042
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2971000974
Short name T183
Test name
Test status
Simulation time 133710524442 ps
CPU time 47.93 seconds
Started Mar 28 01:49:12 PM PDT 24
Finished Mar 28 01:50:00 PM PDT 24
Peak memory 200564 kb
Host smart-cb9c13f9-5e5e-4835-a67b-af8ca5cdea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971000974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2971000974
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3191959736
Short name T79
Test name
Test status
Simulation time 172123999 ps
CPU time 1.26 seconds
Started Mar 28 12:31:52 PM PDT 24
Finished Mar 28 12:31:53 PM PDT 24
Peak memory 198916 kb
Host smart-b5112e47-b206-434d-8ea8-00241cc8b503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191959736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3191959736
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3257981738
Short name T245
Test name
Test status
Simulation time 284975412514 ps
CPU time 158.12 seconds
Started Mar 28 01:50:07 PM PDT 24
Finished Mar 28 01:52:46 PM PDT 24
Peak memory 200528 kb
Host smart-45e80660-2475-4cba-917d-e135386b94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257981738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3257981738
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3217122765
Short name T46
Test name
Test status
Simulation time 93150794140 ps
CPU time 182.63 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:52:34 PM PDT 24
Peak memory 200512 kb
Host smart-065f94d1-41c4-46c5-96c5-0fcf6f7ca4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217122765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3217122765
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.415317888
Short name T371
Test name
Test status
Simulation time 10697493 ps
CPU time 0.56 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:45:41 PM PDT 24
Peak memory 195792 kb
Host smart-89ef3de1-367f-45a1-a243-30d2e6f6b5eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415317888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.415317888
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.447647670
Short name T5
Test name
Test status
Simulation time 28378097685 ps
CPU time 49.16 seconds
Started Mar 28 01:49:19 PM PDT 24
Finished Mar 28 01:50:08 PM PDT 24
Peak memory 200488 kb
Host smart-9954eb94-f57c-4495-a4d1-4565f276e031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447647670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.447647670
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2817335887
Short name T89
Test name
Test status
Simulation time 111111446702 ps
CPU time 126.22 seconds
Started Mar 28 01:49:22 PM PDT 24
Finished Mar 28 01:51:28 PM PDT 24
Peak memory 200432 kb
Host smart-524143e9-8df5-4f73-a5ac-9b98a923c9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817335887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2817335887
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.446924424
Short name T153
Test name
Test status
Simulation time 39491653557 ps
CPU time 17.5 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:49:49 PM PDT 24
Peak memory 200484 kb
Host smart-b79528b7-5c87-409b-bdcb-673b5017f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446924424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.446924424
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2964487774
Short name T268
Test name
Test status
Simulation time 48660986892 ps
CPU time 48.89 seconds
Started Mar 28 01:45:49 PM PDT 24
Finished Mar 28 01:46:38 PM PDT 24
Peak memory 200096 kb
Host smart-388a42c1-77d1-4ef0-8619-5dbc4bd7e98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964487774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2964487774
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2497970355
Short name T30
Test name
Test status
Simulation time 64340151375 ps
CPU time 396.49 seconds
Started Mar 28 01:48:53 PM PDT 24
Finished Mar 28 01:55:29 PM PDT 24
Peak memory 209576 kb
Host smart-b0ca7b8d-c65c-46d9-b149-75e1afb1e950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497970355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2497970355
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1878579797
Short name T60
Test name
Test status
Simulation time 47126058 ps
CPU time 0.82 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:40 PM PDT 24
Peak memory 196468 kb
Host smart-bad90594-2371-4c6c-8974-9b1177bfad22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878579797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1878579797
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.614478558
Short name T55
Test name
Test status
Simulation time 33825079 ps
CPU time 0.64 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 195472 kb
Host smart-92463ff1-23fb-4dd4-a896-1f35766d37b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614478558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.614478558
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2746621854
Short name T184
Test name
Test status
Simulation time 154908581443 ps
CPU time 100.47 seconds
Started Mar 28 01:49:48 PM PDT 24
Finished Mar 28 01:51:29 PM PDT 24
Peak memory 200436 kb
Host smart-8678aa40-89e6-4976-981c-d44cd4124772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746621854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2746621854
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.301183092
Short name T85
Test name
Test status
Simulation time 146114195 ps
CPU time 1.24 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 199048 kb
Host smart-a0c54d98-fea6-4709-b542-f47455957d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301183092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.301183092
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2359495908
Short name T103
Test name
Test status
Simulation time 229059295445 ps
CPU time 439.5 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:54:09 PM PDT 24
Peak memory 216880 kb
Host smart-62c9a5ec-5de7-4ebd-adf8-807f4fcda23f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359495908 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2359495908
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.448811863
Short name T161
Test name
Test status
Simulation time 22554475351 ps
CPU time 38.56 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:48:21 PM PDT 24
Peak memory 200504 kb
Host smart-51366196-ad69-49af-bb86-57ed7ea3deb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448811863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.448811863
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1414532320
Short name T171
Test name
Test status
Simulation time 59002551927 ps
CPU time 41.5 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 01:49:30 PM PDT 24
Peak memory 200356 kb
Host smart-7247b03f-366c-45fd-9aeb-0019e2a2ae94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414532320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1414532320
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.898139279
Short name T515
Test name
Test status
Simulation time 286021975068 ps
CPU time 298.69 seconds
Started Mar 28 01:44:58 PM PDT 24
Finished Mar 28 01:49:57 PM PDT 24
Peak memory 200392 kb
Host smart-6bc6257c-c85e-4fc1-a48d-70be2d531e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898139279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.898139279
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2809497889
Short name T110
Test name
Test status
Simulation time 321261082649 ps
CPU time 1515.01 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 02:14:04 PM PDT 24
Peak memory 217832 kb
Host smart-4a8c2246-6f02-4bfb-b2f0-d6b9ca21a579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809497889 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2809497889
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2007723301
Short name T589
Test name
Test status
Simulation time 80073319461 ps
CPU time 110.17 seconds
Started Mar 28 01:47:10 PM PDT 24
Finished Mar 28 01:49:01 PM PDT 24
Peak memory 200380 kb
Host smart-089c8d76-b3c3-44ab-82c0-133e98e5dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007723301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2007723301
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3187462817
Short name T81
Test name
Test status
Simulation time 76199666 ps
CPU time 1.25 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 198864 kb
Host smart-7e3fc092-2236-4dab-abf9-2e1295148d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187462817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3187462817
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2700728600
Short name T187
Test name
Test status
Simulation time 121423452846 ps
CPU time 113.74 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:50:57 PM PDT 24
Peak memory 200512 kb
Host smart-e3c2b81c-380e-449d-b945-cf483f248fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700728600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2700728600
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1016316531
Short name T149
Test name
Test status
Simulation time 144583279048 ps
CPU time 691.6 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:57:52 PM PDT 24
Peak memory 217000 kb
Host smart-289cc2b7-9f48-4591-8253-f83cc0518052
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016316531 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1016316531
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1618115709
Short name T168
Test name
Test status
Simulation time 115532824457 ps
CPU time 282.43 seconds
Started Mar 28 01:49:14 PM PDT 24
Finished Mar 28 01:53:57 PM PDT 24
Peak memory 200292 kb
Host smart-945fd5e3-1a46-40f7-9008-7a4c56a74e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618115709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1618115709
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_full.526882070
Short name T255
Test name
Test status
Simulation time 90112896827 ps
CPU time 43.21 seconds
Started Mar 28 01:47:26 PM PDT 24
Finished Mar 28 01:48:09 PM PDT 24
Peak memory 200436 kb
Host smart-1c5189a2-1f1b-4fcd-a5c2-e68a79b63248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526882070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.526882070
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_perf.3930138060
Short name T299
Test name
Test status
Simulation time 20794544189 ps
CPU time 157.64 seconds
Started Mar 28 01:44:43 PM PDT 24
Finished Mar 28 01:47:20 PM PDT 24
Peak memory 200428 kb
Host smart-93a2c77c-2c23-4bb9-b02a-837d01468793
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930138060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3930138060
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/13.uart_fifo_full.530107732
Short name T118
Test name
Test status
Simulation time 237559342648 ps
CPU time 116.25 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:47:38 PM PDT 24
Peak memory 200412 kb
Host smart-52e2e139-6e2c-4c53-89dc-ef8a605a7928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530107732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.530107732
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2908377429
Short name T157
Test name
Test status
Simulation time 31518913010 ps
CPU time 13.6 seconds
Started Mar 28 01:49:05 PM PDT 24
Finished Mar 28 01:49:19 PM PDT 24
Peak memory 200432 kb
Host smart-70909e11-a97f-401d-b9fd-10a0f6feb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908377429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2908377429
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_full.615973632
Short name T115
Test name
Test status
Simulation time 172788059020 ps
CPU time 82.88 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:48:19 PM PDT 24
Peak memory 200468 kb
Host smart-ef0764c1-c33e-4329-a657-e4f2301eb95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615973632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.615973632
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1655617403
Short name T225
Test name
Test status
Simulation time 192078749815 ps
CPU time 65.13 seconds
Started Mar 28 01:49:11 PM PDT 24
Finished Mar 28 01:50:17 PM PDT 24
Peak memory 200460 kb
Host smart-e599bcf7-01e8-41fb-8c6d-100c85a644c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655617403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1655617403
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3855506108
Short name T365
Test name
Test status
Simulation time 41314923581 ps
CPU time 44.67 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:46:32 PM PDT 24
Peak memory 200376 kb
Host smart-047558bd-a510-4f2f-a113-4805be3e3f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855506108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3855506108
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3781057402
Short name T275
Test name
Test status
Simulation time 236319872243 ps
CPU time 454.57 seconds
Started Mar 28 01:47:24 PM PDT 24
Finished Mar 28 01:54:59 PM PDT 24
Peak memory 200296 kb
Host smart-294f5b70-2701-492c-9d50-9a84408caf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781057402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3781057402
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1793597667
Short name T188
Test name
Test status
Simulation time 29942355286 ps
CPU time 49.53 seconds
Started Mar 28 01:48:35 PM PDT 24
Finished Mar 28 01:49:25 PM PDT 24
Peak memory 200292 kb
Host smart-07cf762a-d738-46d0-817c-adcbe4df21ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793597667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1793597667
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2264033925
Short name T237
Test name
Test status
Simulation time 61167451659 ps
CPU time 32.67 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:49:34 PM PDT 24
Peak memory 200424 kb
Host smart-567bfe67-b861-4ee8-96e6-9485c04f5207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264033925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2264033925
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3818546139
Short name T144
Test name
Test status
Simulation time 129565332558 ps
CPU time 95.51 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:50:38 PM PDT 24
Peak memory 200512 kb
Host smart-ac4680bb-4a36-40cb-a89e-6378ddd3ddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818546139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3818546139
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3028936084
Short name T206
Test name
Test status
Simulation time 40768874032 ps
CPU time 32.77 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:49:36 PM PDT 24
Peak memory 200476 kb
Host smart-4919efc9-a1b1-4407-80f7-45227e502299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028936084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3028936084
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1889524618
Short name T148
Test name
Test status
Simulation time 32729760417 ps
CPU time 14.06 seconds
Started Mar 28 01:46:18 PM PDT 24
Finished Mar 28 01:46:32 PM PDT 24
Peak memory 200396 kb
Host smart-84fde9b8-26ca-4ce9-b64b-af6883db7c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889524618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1889524618
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2626032095
Short name T265
Test name
Test status
Simulation time 105733457428 ps
CPU time 87.45 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:47:47 PM PDT 24
Peak memory 200476 kb
Host smart-0e43d69c-4dff-4aad-a5b5-ef4b4a662b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626032095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2626032095
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2548482301
Short name T123
Test name
Test status
Simulation time 37683170326 ps
CPU time 22.02 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:49:54 PM PDT 24
Peak memory 200536 kb
Host smart-b5175eb2-3b38-4294-bb3b-063aa5af150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548482301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2548482301
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3369425929
Short name T214
Test name
Test status
Simulation time 139889930661 ps
CPU time 61.61 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:46:02 PM PDT 24
Peak memory 200440 kb
Host smart-bd7c1c19-79e4-4d76-ad06-65b73cdfc0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369425929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3369425929
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2355804966
Short name T98
Test name
Test status
Simulation time 68482893300 ps
CPU time 428.34 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:54:54 PM PDT 24
Peak memory 217144 kb
Host smart-be9ceea7-d4aa-441f-a63e-e9a679878e75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355804966 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2355804966
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_rx.44041306
Short name T47
Test name
Test status
Simulation time 83212498459 ps
CPU time 50.71 seconds
Started Mar 28 01:44:45 PM PDT 24
Finished Mar 28 01:45:36 PM PDT 24
Peak memory 200520 kb
Host smart-b73ea070-d26f-4704-8b1a-84e90d89bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44041306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.44041306
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1504898028
Short name T229
Test name
Test status
Simulation time 133190485074 ps
CPU time 175.85 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:51:57 PM PDT 24
Peak memory 200504 kb
Host smart-460526e3-76e8-48e3-b7e8-ba0bb7ba6f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504898028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1504898028
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1836472092
Short name T111
Test name
Test status
Simulation time 37003618646 ps
CPU time 390.66 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:52:12 PM PDT 24
Peak memory 216452 kb
Host smart-8b1daa31-d16f-463a-bf83-f7cd270bde53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836472092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1836472092
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3484696288
Short name T196
Test name
Test status
Simulation time 9762272767 ps
CPU time 17.64 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:49:19 PM PDT 24
Peak memory 200500 kb
Host smart-3c1af11a-1fee-4c65-96ea-33a20099da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484696288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3484696288
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2376044175
Short name T219
Test name
Test status
Simulation time 93968773105 ps
CPU time 150.1 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:48:13 PM PDT 24
Peak memory 200268 kb
Host smart-13b472d5-1721-43bf-b5ae-b6cab99263ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376044175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2376044175
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2264783356
Short name T224
Test name
Test status
Simulation time 41903276876 ps
CPU time 16.13 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:49:02 PM PDT 24
Peak memory 200504 kb
Host smart-c02a3d7c-d250-47c5-b4cb-813619c90305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264783356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2264783356
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.619063121
Short name T243
Test name
Test status
Simulation time 232259469622 ps
CPU time 19.75 seconds
Started Mar 28 01:49:14 PM PDT 24
Finished Mar 28 01:49:34 PM PDT 24
Peak memory 200580 kb
Host smart-5b92f64b-b189-4192-bf6f-64ad57245352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619063121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.619063121
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1411603936
Short name T205
Test name
Test status
Simulation time 30779201495 ps
CPU time 9.35 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:45:52 PM PDT 24
Peak memory 200260 kb
Host smart-c23851ef-0017-491d-98d8-64dd686b159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411603936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1411603936
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1633487099
Short name T635
Test name
Test status
Simulation time 60433532367 ps
CPU time 39.21 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:46:19 PM PDT 24
Peak memory 200768 kb
Host smart-230b64b4-135a-4bd4-8393-6972b1471296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633487099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1633487099
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.545202261
Short name T8
Test name
Test status
Simulation time 54036846833 ps
CPU time 546.83 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:55:28 PM PDT 24
Peak memory 217216 kb
Host smart-fdfa8fbf-e204-40f3-9aaf-b25b89ef9618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545202261 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.545202261
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1735899496
Short name T232
Test name
Test status
Simulation time 203557893546 ps
CPU time 29.49 seconds
Started Mar 28 01:49:22 PM PDT 24
Finished Mar 28 01:49:52 PM PDT 24
Peak memory 199652 kb
Host smart-f646fa4d-2bcd-4b99-9380-5b22f9b1e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735899496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1735899496
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.1219471328
Short name T221
Test name
Test status
Simulation time 251078132372 ps
CPU time 96.62 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:47:58 PM PDT 24
Peak memory 200428 kb
Host smart-0ed00b41-5f3e-4e8f-b542-5a029b8d8091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219471328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1219471328
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2107760976
Short name T227
Test name
Test status
Simulation time 421423401068 ps
CPU time 86.74 seconds
Started Mar 28 01:49:17 PM PDT 24
Finished Mar 28 01:50:44 PM PDT 24
Peak memory 200428 kb
Host smart-ebbe19af-5889-44b1-9c3f-ad89d666037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107760976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2107760976
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1743924501
Short name T230
Test name
Test status
Simulation time 15807752555 ps
CPU time 14.42 seconds
Started Mar 28 01:49:34 PM PDT 24
Finished Mar 28 01:49:49 PM PDT 24
Peak memory 200484 kb
Host smart-d4861e4a-7fce-4023-aa0f-e67fa65f468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743924501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1743924501
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.20490353
Short name T174
Test name
Test status
Simulation time 101090289450 ps
CPU time 46.89 seconds
Started Mar 28 01:50:13 PM PDT 24
Finished Mar 28 01:51:00 PM PDT 24
Peak memory 200372 kb
Host smart-b4d89b12-be13-45ae-bbe1-9bd51e66245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20490353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.20490353
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3518724661
Short name T211
Test name
Test status
Simulation time 76941829362 ps
CPU time 59.26 seconds
Started Mar 28 01:47:34 PM PDT 24
Finished Mar 28 01:48:34 PM PDT 24
Peak memory 200392 kb
Host smart-6d667312-8a5d-4cfd-b396-e2e640f7c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518724661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3518724661
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.567152073
Short name T222
Test name
Test status
Simulation time 17362207633 ps
CPU time 40.07 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:49:13 PM PDT 24
Peak memory 200504 kb
Host smart-a88b05a0-f7d3-4573-a2cb-49e2b178a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567152073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.567152073
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.236642121
Short name T204
Test name
Test status
Simulation time 17661223599 ps
CPU time 27.82 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:49:18 PM PDT 24
Peak memory 200460 kb
Host smart-066530df-a6da-42ba-a33b-bd1253917226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236642121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.236642121
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1793953467
Short name T231
Test name
Test status
Simulation time 69803653339 ps
CPU time 21.59 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:45:45 PM PDT 24
Peak memory 200412 kb
Host smart-6834eff6-6d37-485c-9485-e8ef419e915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793953467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1793953467
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2445462918
Short name T235
Test name
Test status
Simulation time 79168187166 ps
CPU time 37.28 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:49:28 PM PDT 24
Peak memory 200432 kb
Host smart-882eed9d-9207-4007-be1f-7faceed99d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445462918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2445462918
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.885203280
Short name T57
Test name
Test status
Simulation time 264284685 ps
CPU time 2.6 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 197460 kb
Host smart-f02cef14-32c3-4c66-8a6b-02069ad1b1eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885203280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.885203280
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.392908735
Short name T61
Test name
Test status
Simulation time 37241882 ps
CPU time 0.58 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 195108 kb
Host smart-b396d0a1-2820-46bc-83f0-897cf8d770d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392908735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.392908735
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3099923516
Short name T1233
Test name
Test status
Simulation time 23765330 ps
CPU time 0.76 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 198896 kb
Host smart-1155b8de-6a3c-4148-a27b-6dabc13c44d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099923516 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3099923516
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.709048
Short name T1228
Test name
Test status
Simulation time 49660038 ps
CPU time 0.65 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:27 PM PDT 24
Peak memory 194096 kb
Host smart-eee04680-5a9d-4bd3-9ff9-5858acd103b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.709048
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3861016362
Short name T73
Test name
Test status
Simulation time 33129045 ps
CPU time 0.74 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 197228 kb
Host smart-6d595ef2-b6e1-4d42-ba24-62d17dbfbe01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861016362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3861016362
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1902423675
Short name T1234
Test name
Test status
Simulation time 316666101 ps
CPU time 1.7 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 199752 kb
Host smart-4e2a0cf9-59ee-41bf-9cdd-ba66f9e24272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902423675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1902423675
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2254715027
Short name T106
Test name
Test status
Simulation time 89934059 ps
CPU time 1.25 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 198992 kb
Host smart-58b752d6-fa9e-423a-a473-38cb2832bc52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254715027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2254715027
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2467942954
Short name T1295
Test name
Test status
Simulation time 16200355 ps
CPU time 0.81 seconds
Started Mar 28 12:31:30 PM PDT 24
Finished Mar 28 12:31:31 PM PDT 24
Peak memory 195944 kb
Host smart-7e5909a1-fee2-4360-8064-8eeb489e53c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467942954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2467942954
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3243138821
Short name T1276
Test name
Test status
Simulation time 980507714 ps
CPU time 2.55 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 197464 kb
Host smart-dde05477-57f4-4a02-8971-b3850335e0fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243138821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3243138821
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2895325023
Short name T1249
Test name
Test status
Simulation time 25022366 ps
CPU time 0.56 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:21 PM PDT 24
Peak memory 195040 kb
Host smart-65423baf-cbfa-4387-8eab-52453c831a99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895325023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2895325023
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4277547681
Short name T1271
Test name
Test status
Simulation time 37161274 ps
CPU time 0.71 seconds
Started Mar 28 12:31:24 PM PDT 24
Finished Mar 28 12:31:25 PM PDT 24
Peak memory 197584 kb
Host smart-47717c64-8035-478f-b121-cbcafeabd274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277547681 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.4277547681
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3102246833
Short name T1299
Test name
Test status
Simulation time 36887435 ps
CPU time 0.59 seconds
Started Mar 28 12:31:25 PM PDT 24
Finished Mar 28 12:31:27 PM PDT 24
Peak memory 195080 kb
Host smart-6ba2c5ba-88a1-4d2d-8f95-e91545859f52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102246833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3102246833
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3564827651
Short name T1257
Test name
Test status
Simulation time 11652905 ps
CPU time 0.56 seconds
Started Mar 28 12:31:31 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 194108 kb
Host smart-cf6c29ee-f1af-4062-9773-bbeb78e934ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564827651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3564827651
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.12513137
Short name T67
Test name
Test status
Simulation time 14573857 ps
CPU time 0.65 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 195632 kb
Host smart-4d1a04e2-32c1-4f0f-bc58-38c3feabb00e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12513137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_o
utstanding.12513137
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.625315115
Short name T1225
Test name
Test status
Simulation time 143023359 ps
CPU time 2.31 seconds
Started Mar 28 12:31:30 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 199772 kb
Host smart-6e06cf1a-6546-4823-8848-636b109d7ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625315115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.625315115
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.288940640
Short name T1279
Test name
Test status
Simulation time 75265409 ps
CPU time 1 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 198460 kb
Host smart-6146e9e3-4a84-4592-9647-83aa3b002f40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288940640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.288940640
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3373067827
Short name T1220
Test name
Test status
Simulation time 86639848 ps
CPU time 0.71 seconds
Started Mar 28 12:31:30 PM PDT 24
Finished Mar 28 12:31:31 PM PDT 24
Peak memory 198836 kb
Host smart-78344e80-f303-42a6-b048-2e6b38772c28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373067827 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3373067827
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3967815544
Short name T1240
Test name
Test status
Simulation time 14740922 ps
CPU time 0.6 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 195068 kb
Host smart-4ba6e6cd-c220-432b-b31b-7839e8902bdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967815544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3967815544
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.209184824
Short name T1309
Test name
Test status
Simulation time 13069770 ps
CPU time 0.55 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 194148 kb
Host smart-78508607-1f45-4653-a474-bbc6bf395bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209184824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.209184824
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2049248754
Short name T1300
Test name
Test status
Simulation time 43175456 ps
CPU time 0.76 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 196900 kb
Host smart-e688ba8d-551c-4f68-b654-43d09460c8e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049248754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2049248754
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3010517247
Short name T1217
Test name
Test status
Simulation time 38644315 ps
CPU time 1.03 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 199536 kb
Host smart-e5c6c434-08b4-4636-aaac-7e148ac84c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010517247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3010517247
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1040823414
Short name T1242
Test name
Test status
Simulation time 87311931 ps
CPU time 1.27 seconds
Started Mar 28 12:31:30 PM PDT 24
Finished Mar 28 12:31:31 PM PDT 24
Peak memory 198964 kb
Host smart-9929d214-1edd-4b15-b99e-d2afcc71ac36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040823414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1040823414
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.669310127
Short name T1236
Test name
Test status
Simulation time 21349135 ps
CPU time 0.71 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 198432 kb
Host smart-95dc05da-bb5e-47b1-a792-b11621b2d218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669310127 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.669310127
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3154877459
Short name T1231
Test name
Test status
Simulation time 24265343 ps
CPU time 0.57 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 195024 kb
Host smart-9512419d-b9db-4475-927e-b03df2b2a626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154877459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3154877459
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1500792022
Short name T1235
Test name
Test status
Simulation time 18828654 ps
CPU time 0.53 seconds
Started Mar 28 12:31:31 PM PDT 24
Finished Mar 28 12:31:31 PM PDT 24
Peak memory 194016 kb
Host smart-3fafd078-5ccb-48c4-8f39-6ce83ee96bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500792022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1500792022
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3114107708
Short name T1263
Test name
Test status
Simulation time 52053756 ps
CPU time 0.63 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 195388 kb
Host smart-1b75ea45-72db-4d00-8ae2-fc758676ab36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114107708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3114107708
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.888104236
Short name T1302
Test name
Test status
Simulation time 473458320 ps
CPU time 2.17 seconds
Started Mar 28 12:31:24 PM PDT 24
Finished Mar 28 12:31:26 PM PDT 24
Peak memory 199788 kb
Host smart-5ef4a1b8-c397-467c-82fb-3c37a2505a05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888104236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.888104236
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.109898431
Short name T84
Test name
Test status
Simulation time 135583203 ps
CPU time 1.27 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 198884 kb
Host smart-512ede7c-925a-49c0-87e7-eb0d6cb36146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109898431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.109898431
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1674461140
Short name T1259
Test name
Test status
Simulation time 57793093 ps
CPU time 0.76 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 198984 kb
Host smart-35ad17f2-2280-4fb0-8765-fc075aa74886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674461140 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1674461140
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1160001236
Short name T1318
Test name
Test status
Simulation time 15819596 ps
CPU time 0.55 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 195100 kb
Host smart-52510fe1-478a-4972-8ff0-b4f8aec161f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160001236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1160001236
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3225778438
Short name T1195
Test name
Test status
Simulation time 17652077 ps
CPU time 0.6 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:36 PM PDT 24
Peak memory 194000 kb
Host smart-2185283c-aadb-4c75-9fbb-f9f7955766da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225778438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3225778438
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2215200292
Short name T1267
Test name
Test status
Simulation time 20001626 ps
CPU time 0.77 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 197236 kb
Host smart-627ca95e-de35-461d-be5d-2c8a71fbafd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215200292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2215200292
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3186528648
Short name T1266
Test name
Test status
Simulation time 396863448 ps
CPU time 2.13 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 199712 kb
Host smart-4dbc4d4e-2266-464f-9147-da4150b12d61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186528648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3186528648
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3219489470
Short name T76
Test name
Test status
Simulation time 155113928 ps
CPU time 0.88 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 198476 kb
Host smart-d206faeb-ee21-4b6c-87c8-5c2714a710b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219489470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3219489470
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.524619123
Short name T1197
Test name
Test status
Simulation time 73196833 ps
CPU time 0.68 seconds
Started Mar 28 12:31:51 PM PDT 24
Finished Mar 28 12:31:52 PM PDT 24
Peak memory 197604 kb
Host smart-ad1c4966-d598-42a5-8a15-940c0a7acbdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524619123 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.524619123
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2386887802
Short name T62
Test name
Test status
Simulation time 37056271 ps
CPU time 0.6 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 195080 kb
Host smart-f681d23c-7d9b-47e4-b21b-2a8ee4643b60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386887802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2386887802
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1712128727
Short name T1212
Test name
Test status
Simulation time 25667808 ps
CPU time 0.58 seconds
Started Mar 28 12:31:47 PM PDT 24
Finished Mar 28 12:31:53 PM PDT 24
Peak memory 194052 kb
Host smart-7bb2a56c-53fe-40cf-b276-356b0a227ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712128727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1712128727
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1288078320
Short name T74
Test name
Test status
Simulation time 20924864 ps
CPU time 0.66 seconds
Started Mar 28 12:31:42 PM PDT 24
Finished Mar 28 12:31:43 PM PDT 24
Peak memory 195584 kb
Host smart-f7cae2c1-3a9f-4150-b3e5-06b3d55f95fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288078320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1288078320
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2523365080
Short name T1273
Test name
Test status
Simulation time 26930127 ps
CPU time 1.34 seconds
Started Mar 28 12:31:26 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 199700 kb
Host smart-281c3a70-7447-4b28-8f49-a27823a51fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523365080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2523365080
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1534060198
Short name T1258
Test name
Test status
Simulation time 49125730 ps
CPU time 0.99 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 198812 kb
Host smart-2ea5dba5-797d-42ce-9949-e4dba87e4abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534060198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1534060198
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4035769000
Short name T1226
Test name
Test status
Simulation time 154715317 ps
CPU time 1.2 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 199740 kb
Host smart-7f3cc31f-ed88-4343-8623-342f4379c1b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035769000 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4035769000
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3817201117
Short name T1229
Test name
Test status
Simulation time 12043167 ps
CPU time 0.59 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 195088 kb
Host smart-d83f7c52-70cc-4a1d-b7d1-81363aa39684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817201117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3817201117
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2352570792
Short name T1207
Test name
Test status
Simulation time 13151695 ps
CPU time 0.57 seconds
Started Mar 28 12:32:08 PM PDT 24
Finished Mar 28 12:32:09 PM PDT 24
Peak memory 194000 kb
Host smart-5048b7d4-69bf-43e2-8021-ad89355756fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352570792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2352570792
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3941984682
Short name T1264
Test name
Test status
Simulation time 76062966 ps
CPU time 0.69 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 196692 kb
Host smart-ff77f342-a01d-4066-b23f-618ddb523317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941984682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3941984682
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.689311801
Short name T1315
Test name
Test status
Simulation time 20662579 ps
CPU time 0.98 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 199140 kb
Host smart-fb1c6c7d-168f-4b67-ade8-5073053e24ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689311801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.689311801
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3311541702
Short name T80
Test name
Test status
Simulation time 84183924 ps
CPU time 1.34 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 199156 kb
Host smart-6a520e06-9175-4dbe-ac65-866cd263b696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311541702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3311541702
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2587320801
Short name T1286
Test name
Test status
Simulation time 32816357 ps
CPU time 0.82 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 199544 kb
Host smart-719d2cb7-d42b-4d9b-be83-898255dd578f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587320801 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2587320801
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1700773061
Short name T58
Test name
Test status
Simulation time 12574122 ps
CPU time 0.59 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:36 PM PDT 24
Peak memory 195100 kb
Host smart-5cf68a5a-4bb0-4e1a-a6d7-99dab5de644b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700773061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1700773061
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2948180403
Short name T1243
Test name
Test status
Simulation time 12951030 ps
CPU time 0.56 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 194032 kb
Host smart-ddf7dd36-6dfc-472f-9970-0723e1cad755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948180403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2948180403
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2053105852
Short name T1230
Test name
Test status
Simulation time 51728662 ps
CPU time 0.73 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:43 PM PDT 24
Peak memory 195804 kb
Host smart-57efe031-2069-466d-946b-6993b907a799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053105852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2053105852
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.684628254
Short name T1254
Test name
Test status
Simulation time 77587824 ps
CPU time 2.22 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 199872 kb
Host smart-1783e7a1-31e9-4e5e-b3a3-fc2bb0721b19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684628254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.684628254
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3924788440
Short name T1304
Test name
Test status
Simulation time 176307886 ps
CPU time 0.97 seconds
Started Mar 28 12:31:44 PM PDT 24
Finished Mar 28 12:31:45 PM PDT 24
Peak memory 198744 kb
Host smart-e2db3cef-f7bb-41ea-8358-5aa75044dd8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924788440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3924788440
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1953045822
Short name T1252
Test name
Test status
Simulation time 165577767 ps
CPU time 0.87 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 199552 kb
Host smart-b13d1a4f-15f9-497f-8c92-982ddd53625e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953045822 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1953045822
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1128763513
Short name T1238
Test name
Test status
Simulation time 15780310 ps
CPU time 0.6 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 195268 kb
Host smart-f447e1dd-bb24-4277-9a1c-b602a469c74a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128763513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1128763513
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1045694055
Short name T1239
Test name
Test status
Simulation time 29748414 ps
CPU time 0.58 seconds
Started Mar 28 12:32:03 PM PDT 24
Finished Mar 28 12:32:04 PM PDT 24
Peak memory 194052 kb
Host smart-cba36892-f497-465d-9691-d6cef70c09b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045694055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1045694055
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2656909039
Short name T1237
Test name
Test status
Simulation time 24907731 ps
CPU time 0.73 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 197296 kb
Host smart-0c241c0b-8a31-49ad-b0be-c361bb5ffc8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656909039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2656909039
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3200948870
Short name T1319
Test name
Test status
Simulation time 52347974 ps
CPU time 1.33 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:11 PM PDT 24
Peak memory 199748 kb
Host smart-a28aa4d6-90b3-4e89-a5c2-1d537dd1b2af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200948870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3200948870
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2799255354
Short name T1199
Test name
Test status
Simulation time 266286003 ps
CPU time 1.2 seconds
Started Mar 28 12:31:59 PM PDT 24
Finished Mar 28 12:32:00 PM PDT 24
Peak memory 198864 kb
Host smart-bd274d12-fd26-4ea0-983b-dad3775f1af3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799255354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2799255354
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3808519006
Short name T1265
Test name
Test status
Simulation time 105798376 ps
CPU time 1.24 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 199776 kb
Host smart-f834372a-4dd8-452b-8806-3d51c4df77e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808519006 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3808519006
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2784882320
Short name T1314
Test name
Test status
Simulation time 64654505 ps
CPU time 0.58 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:46 PM PDT 24
Peak memory 195040 kb
Host smart-014913e7-0f9a-42e7-8852-b7cf6851d5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784882320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2784882320
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1792479550
Short name T1291
Test name
Test status
Simulation time 45351519 ps
CPU time 0.57 seconds
Started Mar 28 12:31:59 PM PDT 24
Finished Mar 28 12:31:59 PM PDT 24
Peak memory 194152 kb
Host smart-af15f273-ada1-42b1-bf3a-7423e7174733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792479550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1792479550
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2085774935
Short name T72
Test name
Test status
Simulation time 96939614 ps
CPU time 0.75 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 196560 kb
Host smart-0891fc00-5aec-4ec2-b975-5a99ecfbeabe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085774935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2085774935
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2738268837
Short name T1209
Test name
Test status
Simulation time 99645317 ps
CPU time 2.09 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:44 PM PDT 24
Peak memory 199708 kb
Host smart-fdb7cd36-2ecc-4f67-8536-136de6922535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738268837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2738268837
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3549625940
Short name T1191
Test name
Test status
Simulation time 58090764 ps
CPU time 1.49 seconds
Started Mar 28 12:31:38 PM PDT 24
Finished Mar 28 12:31:40 PM PDT 24
Peak memory 199780 kb
Host smart-27341bfd-55f9-4b94-9697-6aa72ef9ef26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549625940 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3549625940
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3897670446
Short name T1269
Test name
Test status
Simulation time 14827225 ps
CPU time 0.61 seconds
Started Mar 28 12:31:38 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 195296 kb
Host smart-7c9dafbd-145b-4908-bea9-6812ec511fa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897670446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3897670446
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1396223925
Short name T1272
Test name
Test status
Simulation time 38596869 ps
CPU time 0.57 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 194008 kb
Host smart-ad9a6ab0-3cbd-418e-ac24-ab66ba223b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396223925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1396223925
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2409017161
Short name T1248
Test name
Test status
Simulation time 30900797 ps
CPU time 0.84 seconds
Started Mar 28 12:32:05 PM PDT 24
Finished Mar 28 12:32:06 PM PDT 24
Peak memory 195820 kb
Host smart-27d4b81d-9ba5-4077-b7e5-a8af882f6e1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409017161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2409017161
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1943202875
Short name T1311
Test name
Test status
Simulation time 33202501 ps
CPU time 1.01 seconds
Started Mar 28 12:31:38 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 199488 kb
Host smart-ba9a0408-7451-4ec2-977d-24a9beaa4599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943202875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1943202875
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1691661807
Short name T108
Test name
Test status
Simulation time 586164797 ps
CPU time 0.91 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 198532 kb
Host smart-5b8d8856-d1ba-4d52-8d9a-0d4d6252fe61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691661807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1691661807
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.776777576
Short name T1306
Test name
Test status
Simulation time 19345593 ps
CPU time 0.65 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 197356 kb
Host smart-200a0acd-05b6-447c-9337-8380dcedf5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776777576 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.776777576
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.431540952
Short name T68
Test name
Test status
Simulation time 15507598 ps
CPU time 0.62 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 195168 kb
Host smart-f0a2c276-59d2-4716-b093-f97388ab9c0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431540952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.431540952
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4093274594
Short name T1205
Test name
Test status
Simulation time 14089941 ps
CPU time 0.56 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 194128 kb
Host smart-837d3e05-5f7a-40f4-8949-bbc3df589c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093274594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4093274594
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3732838299
Short name T69
Test name
Test status
Simulation time 34102509 ps
CPU time 0.72 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 196796 kb
Host smart-9aa29b40-28c7-4b20-90c9-adac21d66efe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732838299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3732838299
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2527399095
Short name T1316
Test name
Test status
Simulation time 168834493 ps
CPU time 2.31 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:43 PM PDT 24
Peak memory 199884 kb
Host smart-ad0ddda2-3dc9-401e-bc56-287711afd019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527399095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2527399095
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1322756007
Short name T83
Test name
Test status
Simulation time 539440168 ps
CPU time 1.34 seconds
Started Mar 28 12:31:38 PM PDT 24
Finished Mar 28 12:31:40 PM PDT 24
Peak memory 199040 kb
Host smart-4f754982-a200-47f3-a163-511871660fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322756007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1322756007
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2423595168
Short name T1301
Test name
Test status
Simulation time 78907146 ps
CPU time 0.66 seconds
Started Mar 28 12:31:30 PM PDT 24
Finished Mar 28 12:31:31 PM PDT 24
Peak memory 195040 kb
Host smart-e3f01c14-e42b-4f42-8509-44aa9f8de421
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423595168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2423595168
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3157876781
Short name T1203
Test name
Test status
Simulation time 580002942 ps
CPU time 2.37 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 197572 kb
Host smart-6294c88a-b0be-4499-accc-fdaf62825944
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157876781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3157876781
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.577455642
Short name T64
Test name
Test status
Simulation time 1038294532 ps
CPU time 1.63 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 195036 kb
Host smart-b299a80b-ca7c-4afd-8ccd-35f596341c85
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577455642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.577455642
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2929606813
Short name T1204
Test name
Test status
Simulation time 46066019 ps
CPU time 0.77 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 198516 kb
Host smart-7518842e-6ad4-4e2c-95af-da4a94b9c23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929606813 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2929606813
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3902743731
Short name T1294
Test name
Test status
Simulation time 18856492 ps
CPU time 0.61 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 195208 kb
Host smart-fd4acbd4-aadd-4ccf-9bb4-e806e41b67cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902743731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3902743731
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2235347947
Short name T1227
Test name
Test status
Simulation time 20028811 ps
CPU time 0.56 seconds
Started Mar 28 12:31:26 PM PDT 24
Finished Mar 28 12:31:27 PM PDT 24
Peak memory 194072 kb
Host smart-96daeff7-2ac3-43fe-95b0-663fc4ea4db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235347947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2235347947
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.317067487
Short name T66
Test name
Test status
Simulation time 13460886 ps
CPU time 0.67 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 194448 kb
Host smart-a9ed5901-2b43-45b9-b416-46018a076c25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317067487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.317067487
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4032642343
Short name T1222
Test name
Test status
Simulation time 292694358 ps
CPU time 1.21 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 199720 kb
Host smart-ebc08e10-995c-4ba8-b6ea-1268ce176414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032642343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4032642343
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.4291016197
Short name T1260
Test name
Test status
Simulation time 27337637 ps
CPU time 0.58 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 194088 kb
Host smart-decb6ef6-ec07-47b4-9d71-149ae94b79aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291016197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4291016197
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2560894455
Short name T1206
Test name
Test status
Simulation time 14457641 ps
CPU time 0.57 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 194152 kb
Host smart-2292dfe8-627c-4dfa-935f-7d53955a4c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560894455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2560894455
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.801484992
Short name T1317
Test name
Test status
Simulation time 22514042 ps
CPU time 0.55 seconds
Started Mar 28 12:31:45 PM PDT 24
Finished Mar 28 12:31:46 PM PDT 24
Peak memory 194000 kb
Host smart-efddb368-ef72-4116-83b7-4302bc48bf55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801484992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.801484992
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.200746365
Short name T1287
Test name
Test status
Simulation time 30671972 ps
CPU time 0.54 seconds
Started Mar 28 12:31:38 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 194096 kb
Host smart-a9ac88f4-9e5e-4a31-9bb4-cb6c1b4665d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200746365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.200746365
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4213276492
Short name T1200
Test name
Test status
Simulation time 44952679 ps
CPU time 0.54 seconds
Started Mar 28 12:31:43 PM PDT 24
Finished Mar 28 12:31:44 PM PDT 24
Peak memory 194080 kb
Host smart-56168ef6-cc89-4676-ab5d-e992a11fb3ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213276492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4213276492
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2470836642
Short name T1218
Test name
Test status
Simulation time 11614389 ps
CPU time 0.57 seconds
Started Mar 28 12:32:13 PM PDT 24
Finished Mar 28 12:32:18 PM PDT 24
Peak memory 194064 kb
Host smart-1a23fa7f-5f02-48c8-9e34-61415758ce9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470836642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2470836642
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1999867343
Short name T1275
Test name
Test status
Simulation time 12534746 ps
CPU time 0.55 seconds
Started Mar 28 12:32:15 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 194016 kb
Host smart-c6b75709-221e-4efb-9a40-67a2b29ac837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999867343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1999867343
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.679801970
Short name T1250
Test name
Test status
Simulation time 43066839 ps
CPU time 0.59 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 194060 kb
Host smart-fb6e9def-b0e0-4a43-816a-7bc5ee8119a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679801970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.679801970
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3258304220
Short name T1296
Test name
Test status
Simulation time 13507451 ps
CPU time 0.59 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 194084 kb
Host smart-5bf37281-fc62-4fe3-a07d-5bf59179fac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258304220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3258304220
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1160095713
Short name T1210
Test name
Test status
Simulation time 12649235 ps
CPU time 0.53 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 194108 kb
Host smart-451780f4-3631-4c52-97e1-cf4260d91226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160095713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1160095713
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3774511745
Short name T63
Test name
Test status
Simulation time 46565842 ps
CPU time 0.66 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 195092 kb
Host smart-9f162a26-781f-4426-8888-44966dce4733
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774511745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3774511745
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1532865992
Short name T1246
Test name
Test status
Simulation time 93322871 ps
CPU time 1.47 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 197284 kb
Host smart-51de04c7-228b-48a0-8467-c21a740e6fe4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532865992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1532865992
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2031277783
Short name T1198
Test name
Test status
Simulation time 50639863 ps
CPU time 0.72 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 195056 kb
Host smart-0e4b767e-9e6e-4c6d-88b8-87bcb5133606
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031277783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2031277783
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2159774936
Short name T1284
Test name
Test status
Simulation time 89439245 ps
CPU time 1.37 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 199792 kb
Host smart-7fa4df15-c06c-4e93-bdc8-b590448b6825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159774936 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2159774936
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3764555556
Short name T59
Test name
Test status
Simulation time 18113993 ps
CPU time 0.64 seconds
Started Mar 28 12:31:21 PM PDT 24
Finished Mar 28 12:31:22 PM PDT 24
Peak memory 195228 kb
Host smart-2a94e77c-2c44-4c23-b99d-548b4dd45464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764555556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3764555556
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1052130883
Short name T1290
Test name
Test status
Simulation time 12266857 ps
CPU time 0.63 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 194064 kb
Host smart-cd6c4180-ab99-4888-8e00-327967b5595f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052130883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1052130883
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1866149929
Short name T1274
Test name
Test status
Simulation time 31927642 ps
CPU time 0.74 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:30 PM PDT 24
Peak memory 195704 kb
Host smart-6b85516e-8868-4616-9ade-4fb25a5c2d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866149929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1866149929
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3552695219
Short name T1189
Test name
Test status
Simulation time 422973592 ps
CPU time 1.9 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 199668 kb
Host smart-ca9034a0-4778-4213-9d4a-8500fa736ef2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552695219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3552695219
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3272432837
Short name T107
Test name
Test status
Simulation time 354865771 ps
CPU time 0.93 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 198680 kb
Host smart-308543c4-23c1-432e-be9d-7d4652838b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272432837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3272432837
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1205292427
Short name T1244
Test name
Test status
Simulation time 26337017 ps
CPU time 0.59 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 194052 kb
Host smart-0e78dda7-010f-4e7b-b431-5b437eeeb1ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205292427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1205292427
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2289170223
Short name T1270
Test name
Test status
Simulation time 47914995 ps
CPU time 0.56 seconds
Started Mar 28 12:32:03 PM PDT 24
Finished Mar 28 12:32:03 PM PDT 24
Peak memory 194064 kb
Host smart-5b5eb017-cfd0-4978-9667-9256913623c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289170223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2289170223
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3153306775
Short name T1285
Test name
Test status
Simulation time 15903042 ps
CPU time 0.59 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 194092 kb
Host smart-412a6065-f046-48f0-9d78-05ea49ba963b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153306775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3153306775
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2456914786
Short name T1241
Test name
Test status
Simulation time 31202214 ps
CPU time 0.58 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 194072 kb
Host smart-29c5106c-4f38-413b-8ec6-c4b983efce51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456914786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2456914786
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1817934971
Short name T1251
Test name
Test status
Simulation time 69834830 ps
CPU time 0.55 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:36 PM PDT 24
Peak memory 194068 kb
Host smart-da0bf770-b6fe-42bc-a48a-55897cfbcb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817934971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1817934971
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1878446392
Short name T1224
Test name
Test status
Simulation time 18673391 ps
CPU time 0.58 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 194044 kb
Host smart-f357eb00-4372-41db-bcb0-a62e29749b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878446392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1878446392
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2810834784
Short name T1283
Test name
Test status
Simulation time 10782124 ps
CPU time 0.55 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 194116 kb
Host smart-3a8647fe-a091-48d1-9888-b8667fa2c686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810834784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2810834784
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3402770801
Short name T1190
Test name
Test status
Simulation time 49554441 ps
CPU time 0.58 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:36 PM PDT 24
Peak memory 194088 kb
Host smart-67634201-2062-4ab1-87e7-db51f332973b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402770801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3402770801
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.598814367
Short name T1201
Test name
Test status
Simulation time 13986342 ps
CPU time 0.61 seconds
Started Mar 28 12:32:08 PM PDT 24
Finished Mar 28 12:32:09 PM PDT 24
Peak memory 194140 kb
Host smart-3cee1d4d-10e2-4b45-9b26-63df14e6588a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598814367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.598814367
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3999591735
Short name T1223
Test name
Test status
Simulation time 16453353 ps
CPU time 0.57 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 194024 kb
Host smart-7bcdaa53-d600-4b68-a935-76007ed1e620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999591735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3999591735
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2925306241
Short name T56
Test name
Test status
Simulation time 143844384 ps
CPU time 0.75 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 195996 kb
Host smart-e2cb0f61-5aeb-4d22-a658-8673635c6ed6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925306241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2925306241
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1281414293
Short name T1214
Test name
Test status
Simulation time 1974849316 ps
CPU time 2.74 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:36 PM PDT 24
Peak memory 197376 kb
Host smart-936a6d42-4a94-4bbf-b4ed-ddf2720d0fb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281414293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1281414293
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1157548573
Short name T1232
Test name
Test status
Simulation time 12308500 ps
CPU time 0.57 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 195068 kb
Host smart-c791d863-635f-4444-a455-5deb7af9a535
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157548573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1157548573
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.620182208
Short name T1288
Test name
Test status
Simulation time 65898448 ps
CPU time 0.94 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 199568 kb
Host smart-bf218423-191b-4133-b360-5c7e9c9d79fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620182208 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.620182208
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2843614924
Short name T1292
Test name
Test status
Simulation time 10928779 ps
CPU time 0.59 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 195020 kb
Host smart-df58f986-413e-4f4f-915b-fe850638dccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843614924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2843614924
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3608054098
Short name T1298
Test name
Test status
Simulation time 29735009 ps
CPU time 0.61 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 194092 kb
Host smart-eef1f1c5-9105-4241-a8b6-17e33b9273cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608054098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3608054098
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2380028666
Short name T1312
Test name
Test status
Simulation time 20111865 ps
CPU time 0.63 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 195400 kb
Host smart-8bc9449c-a9dc-4e94-b877-0d89d973195e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380028666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2380028666
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1952548890
Short name T1221
Test name
Test status
Simulation time 367042685 ps
CPU time 1.25 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 199728 kb
Host smart-ff14fbe5-f1c9-40bb-bdde-226c5ee43bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952548890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1952548890
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.839179604
Short name T77
Test name
Test status
Simulation time 373883194 ps
CPU time 1.35 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 199160 kb
Host smart-95fd25bb-0d68-4857-a5a2-6197be8de584
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839179604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.839179604
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3350895770
Short name T1277
Test name
Test status
Simulation time 23276013 ps
CPU time 0.57 seconds
Started Mar 28 12:31:51 PM PDT 24
Finished Mar 28 12:31:52 PM PDT 24
Peak memory 194156 kb
Host smart-37e700ce-fb6f-459d-ab2e-c93438f4bbf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350895770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3350895770
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2289307630
Short name T1308
Test name
Test status
Simulation time 53817545 ps
CPU time 0.57 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 194120 kb
Host smart-4354d6eb-d86f-4f79-aa66-5a8a19d4083d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289307630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2289307630
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1588462954
Short name T1305
Test name
Test status
Simulation time 20099097 ps
CPU time 0.55 seconds
Started Mar 28 12:31:59 PM PDT 24
Finished Mar 28 12:32:00 PM PDT 24
Peak memory 194128 kb
Host smart-183c1d63-0552-4d18-be24-e07b236fc09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588462954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1588462954
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4001187870
Short name T1193
Test name
Test status
Simulation time 28523476 ps
CPU time 0.53 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 194012 kb
Host smart-a5e4b31f-a094-4079-96e3-b499cacc46ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001187870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4001187870
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.4281583408
Short name T1293
Test name
Test status
Simulation time 33969870 ps
CPU time 0.57 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 194024 kb
Host smart-5f8a6a2e-e24b-48e4-adbd-3ef8557a257c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281583408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.4281583408
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.547413045
Short name T1282
Test name
Test status
Simulation time 49978228 ps
CPU time 0.58 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 194004 kb
Host smart-f11bb99f-a12a-4652-8a3a-8d201c2b63e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547413045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.547413045
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.145436014
Short name T1255
Test name
Test status
Simulation time 35746633 ps
CPU time 0.55 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 194060 kb
Host smart-c451b177-89fe-48b5-aab8-b1c8c5ec10c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145436014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.145436014
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.585888008
Short name T1256
Test name
Test status
Simulation time 22919304 ps
CPU time 0.56 seconds
Started Mar 28 12:31:43 PM PDT 24
Finished Mar 28 12:31:45 PM PDT 24
Peak memory 194124 kb
Host smart-92868509-caf4-4547-92f4-ad473017dbc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585888008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.585888008
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.170620753
Short name T1310
Test name
Test status
Simulation time 18621325 ps
CPU time 0.57 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 194124 kb
Host smart-dce35115-54f6-4cc7-a9d7-414e57632883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170620753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.170620753
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2224465955
Short name T1278
Test name
Test status
Simulation time 12426065 ps
CPU time 0.55 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 194120 kb
Host smart-0cd69d07-7c49-40c9-ac54-970bce23a0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224465955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2224465955
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3939657680
Short name T1313
Test name
Test status
Simulation time 65805672 ps
CPU time 0.63 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 197420 kb
Host smart-bdaf8b70-ddb8-45c1-8b4d-2f04bc335b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939657680 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3939657680
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2082574211
Short name T1289
Test name
Test status
Simulation time 15946658 ps
CPU time 0.55 seconds
Started Mar 28 12:31:26 PM PDT 24
Finished Mar 28 12:31:27 PM PDT 24
Peak memory 195044 kb
Host smart-aa4011be-46ad-44b6-8737-e27fa16aa937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082574211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2082574211
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.562074788
Short name T1261
Test name
Test status
Simulation time 51769847 ps
CPU time 0.58 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 194048 kb
Host smart-7f3abb87-ba42-46b0-87ac-324a9ef81264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562074788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.562074788
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2432415549
Short name T1303
Test name
Test status
Simulation time 24423703 ps
CPU time 0.73 seconds
Started Mar 28 12:31:23 PM PDT 24
Finished Mar 28 12:31:24 PM PDT 24
Peak memory 196532 kb
Host smart-ceaad77c-81c6-444e-a547-1903218919b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432415549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2432415549
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4288137456
Short name T1196
Test name
Test status
Simulation time 151009020 ps
CPU time 1.03 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 199396 kb
Host smart-901faeff-0411-45ea-9eb3-f4c952167866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288137456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4288137456
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3793760403
Short name T1281
Test name
Test status
Simulation time 42724970 ps
CPU time 1.03 seconds
Started Mar 28 12:31:25 PM PDT 24
Finished Mar 28 12:31:27 PM PDT 24
Peak memory 199656 kb
Host smart-5724fa6c-c75a-4661-946b-1b43f5d1b3b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793760403 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3793760403
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1883650206
Short name T1268
Test name
Test status
Simulation time 11653564 ps
CPU time 0.57 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 195020 kb
Host smart-d045ce29-16d5-4623-9276-6e3de894efca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883650206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1883650206
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3591063317
Short name T1280
Test name
Test status
Simulation time 35816111 ps
CPU time 0.58 seconds
Started Mar 28 12:31:22 PM PDT 24
Finished Mar 28 12:31:23 PM PDT 24
Peak memory 194072 kb
Host smart-35344a8a-86b3-4c6c-aa84-38dcbbfcb6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591063317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3591063317
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2506155691
Short name T1297
Test name
Test status
Simulation time 93793946 ps
CPU time 0.74 seconds
Started Mar 28 12:31:31 PM PDT 24
Finished Mar 28 12:31:32 PM PDT 24
Peak memory 196884 kb
Host smart-bef547bb-8307-4607-b73f-481dcc1a42bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506155691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2506155691
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2444873639
Short name T1219
Test name
Test status
Simulation time 445582964 ps
CPU time 2.2 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:31 PM PDT 24
Peak memory 199728 kb
Host smart-57e9fe16-f562-4fbd-a173-611814e0c5c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444873639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2444873639
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3692514737
Short name T82
Test name
Test status
Simulation time 93877251 ps
CPU time 1.01 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:40 PM PDT 24
Peak memory 198636 kb
Host smart-93bbc223-6399-4839-a2e6-cfa8718f0326
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692514737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3692514737
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3475936653
Short name T1307
Test name
Test status
Simulation time 69548955 ps
CPU time 1.06 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 199528 kb
Host smart-2ebb4029-93ea-4ed0-95bc-ae4efd0ac89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475936653 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3475936653
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2741057236
Short name T71
Test name
Test status
Simulation time 61974340 ps
CPU time 0.6 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 195308 kb
Host smart-add21b42-9ec2-49c4-9915-0be73cc925c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741057236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2741057236
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3064862831
Short name T1208
Test name
Test status
Simulation time 12144396 ps
CPU time 0.56 seconds
Started Mar 28 12:31:29 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 194004 kb
Host smart-ead34e91-7edd-4aa1-b96e-e6c6608ceb71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064862831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3064862831
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1493493529
Short name T1245
Test name
Test status
Simulation time 87203411 ps
CPU time 0.65 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 195168 kb
Host smart-38f99c88-9236-4841-8a2f-dd71cb83b0ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493493529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1493493529
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.985468756
Short name T1194
Test name
Test status
Simulation time 357563299 ps
CPU time 1.92 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 199672 kb
Host smart-1f4b4fb3-cea4-4f08-a536-5ed589a6cade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985468756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.985468756
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.230520620
Short name T109
Test name
Test status
Simulation time 166403872 ps
CPU time 0.91 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 198640 kb
Host smart-bc5d39b3-b50f-4e17-bc73-25595ae89660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230520620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.230520620
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.679761197
Short name T1202
Test name
Test status
Simulation time 23793523 ps
CPU time 0.75 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:34 PM PDT 24
Peak memory 197784 kb
Host smart-58d4aa04-2054-4e78-984e-3d8a9ded7b30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679761197 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.679761197
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1361344952
Short name T65
Test name
Test status
Simulation time 27713560 ps
CPU time 0.63 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 195184 kb
Host smart-51945007-6fc6-432c-9dc9-5c9a72cacdf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361344952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1361344952
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3361045270
Short name T1213
Test name
Test status
Simulation time 48141445 ps
CPU time 0.6 seconds
Started Mar 28 12:31:28 PM PDT 24
Finished Mar 28 12:31:29 PM PDT 24
Peak memory 194032 kb
Host smart-6612a31e-b725-46da-8399-c4331f01bb58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361045270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3361045270
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4049522444
Short name T1247
Test name
Test status
Simulation time 15221089 ps
CPU time 0.63 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 195360 kb
Host smart-8a5a69fe-18d3-41c8-b8a5-b3b49661bf8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049522444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4049522444
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2055207849
Short name T1216
Test name
Test status
Simulation time 40946260 ps
CPU time 1.21 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:36 PM PDT 24
Peak memory 199732 kb
Host smart-7c39cfed-5913-4afd-934c-729bb669e471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055207849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2055207849
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.915444087
Short name T1211
Test name
Test status
Simulation time 73925951 ps
CPU time 0.91 seconds
Started Mar 28 12:31:32 PM PDT 24
Finished Mar 28 12:31:33 PM PDT 24
Peak memory 199592 kb
Host smart-4b55f1d8-b7d4-4c12-ade0-7bdb6354bb47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915444087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.915444087
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1259286610
Short name T1192
Test name
Test status
Simulation time 49658287 ps
CPU time 1.22 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 199712 kb
Host smart-defa9356-a66a-4279-8132-adf2d907b5bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259286610 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1259286610
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3420150699
Short name T1262
Test name
Test status
Simulation time 44502853 ps
CPU time 0.58 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 195056 kb
Host smart-378f2c9d-10c0-4c3a-9111-d7d791fe880a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420150699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3420150699
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2444931041
Short name T1215
Test name
Test status
Simulation time 17134476 ps
CPU time 0.61 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 194124 kb
Host smart-d93bac7e-5aaf-489a-8440-42a9580a60c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444931041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2444931041
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2421406248
Short name T70
Test name
Test status
Simulation time 28616842 ps
CPU time 0.76 seconds
Started Mar 28 12:31:27 PM PDT 24
Finished Mar 28 12:31:28 PM PDT 24
Peak memory 196780 kb
Host smart-73f1849a-2871-4a8a-94ef-7c3f014d88c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421406248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2421406248
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.76002087
Short name T1253
Test name
Test status
Simulation time 201698970 ps
CPU time 2.23 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 199848 kb
Host smart-37b6837a-c965-404f-bab9-6f21a8c1a94a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76002087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.76002087
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2819756964
Short name T78
Test name
Test status
Simulation time 136486646 ps
CPU time 0.93 seconds
Started Mar 28 12:31:31 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 198476 kb
Host smart-cbdb0818-9ca2-495e-9bae-dd62d06657af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819756964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2819756964
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.14050284
Short name T485
Test name
Test status
Simulation time 44896107 ps
CPU time 0.55 seconds
Started Mar 28 01:44:48 PM PDT 24
Finished Mar 28 01:44:49 PM PDT 24
Peak memory 195868 kb
Host smart-e188c752-a2e4-40b4-b277-4d74d4981a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14050284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.14050284
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4232818097
Short name T387
Test name
Test status
Simulation time 49127940021 ps
CPU time 75.66 seconds
Started Mar 28 01:44:38 PM PDT 24
Finished Mar 28 01:45:54 PM PDT 24
Peak memory 200488 kb
Host smart-c51c6697-3f18-48c4-830c-b16bf20b98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232818097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4232818097
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3551640752
Short name T539
Test name
Test status
Simulation time 63880645205 ps
CPU time 111.28 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:46:39 PM PDT 24
Peak memory 200260 kb
Host smart-780c5aea-e2c4-49d0-8b9a-34e3bdaab36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551640752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3551640752
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1579611522
Short name T1006
Test name
Test status
Simulation time 72402378394 ps
CPU time 135.33 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:47:03 PM PDT 24
Peak memory 200244 kb
Host smart-8aaa4b48-2fd2-4e53-a681-6a19e2b00052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579611522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1579611522
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3684594444
Short name T733
Test name
Test status
Simulation time 35392556255 ps
CPU time 59.34 seconds
Started Mar 28 01:44:39 PM PDT 24
Finished Mar 28 01:45:38 PM PDT 24
Peak memory 200464 kb
Host smart-139d338b-6237-4814-ade7-fc8b8c767702
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684594444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3684594444
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2605461232
Short name T1096
Test name
Test status
Simulation time 136811283935 ps
CPU time 388.62 seconds
Started Mar 28 01:44:42 PM PDT 24
Finished Mar 28 01:51:11 PM PDT 24
Peak memory 200492 kb
Host smart-d30ad864-3443-4764-aca5-f000805f3737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605461232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2605461232
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.474708790
Short name T349
Test name
Test status
Simulation time 4716531836 ps
CPU time 5.22 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:44:53 PM PDT 24
Peak memory 199088 kb
Host smart-b3fc0de7-d512-4c2b-898c-1ca0bc4372da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474708790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.474708790
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3083932494
Short name T851
Test name
Test status
Simulation time 107013745222 ps
CPU time 160.25 seconds
Started Mar 28 01:44:39 PM PDT 24
Finished Mar 28 01:47:19 PM PDT 24
Peak memory 200040 kb
Host smart-aff9594f-da11-4759-95ff-d6601a7164de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083932494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3083932494
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3965157216
Short name T495
Test name
Test status
Simulation time 6737819310 ps
CPU time 59.86 seconds
Started Mar 28 01:44:38 PM PDT 24
Finished Mar 28 01:45:38 PM PDT 24
Peak memory 199288 kb
Host smart-45aa5b8d-d0c7-4d61-9875-55f5d42a35e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965157216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3965157216
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.561886046
Short name T844
Test name
Test status
Simulation time 27002513347 ps
CPU time 41.12 seconds
Started Mar 28 01:44:43 PM PDT 24
Finished Mar 28 01:45:25 PM PDT 24
Peak memory 200228 kb
Host smart-e9637631-6c11-48c1-b8d9-3b77b02cd0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561886046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.561886046
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1955413668
Short name T1045
Test name
Test status
Simulation time 44435263559 ps
CPU time 37.83 seconds
Started Mar 28 01:44:43 PM PDT 24
Finished Mar 28 01:45:21 PM PDT 24
Peak memory 196508 kb
Host smart-1707c3b1-e09c-49fb-a5e4-6c7d07d4b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955413668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1955413668
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1887581334
Short name T87
Test name
Test status
Simulation time 509352491 ps
CPU time 0.88 seconds
Started Mar 28 01:44:41 PM PDT 24
Finished Mar 28 01:44:42 PM PDT 24
Peak memory 218964 kb
Host smart-64f7b041-184e-403e-9289-80ffb395e167
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887581334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1887581334
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.261033660
Short name T700
Test name
Test status
Simulation time 5825438317 ps
CPU time 11.18 seconds
Started Mar 28 01:44:42 PM PDT 24
Finished Mar 28 01:44:54 PM PDT 24
Peak memory 200244 kb
Host smart-ba983e4c-a619-401a-a478-ba4f7639fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261033660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.261033660
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.4140721039
Short name T533
Test name
Test status
Simulation time 296713816264 ps
CPU time 303.23 seconds
Started Mar 28 01:44:45 PM PDT 24
Finished Mar 28 01:49:49 PM PDT 24
Peak memory 200468 kb
Host smart-35b26e5a-b1b6-48e1-bd21-64b57471c911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140721039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4140721039
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3987110396
Short name T981
Test name
Test status
Simulation time 948820061647 ps
CPU time 808.34 seconds
Started Mar 28 01:44:49 PM PDT 24
Finished Mar 28 01:58:17 PM PDT 24
Peak memory 225436 kb
Host smart-c5c7f9b9-1dae-46e4-b637-b58d3d36dc6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987110396 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3987110396
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1771341983
Short name T868
Test name
Test status
Simulation time 509882942 ps
CPU time 2.14 seconds
Started Mar 28 01:44:45 PM PDT 24
Finished Mar 28 01:44:48 PM PDT 24
Peak memory 199040 kb
Host smart-39433a5e-30d2-4758-971b-e37637db7ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771341983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1771341983
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.3277931730
Short name T638
Test name
Test status
Simulation time 41826613 ps
CPU time 0.58 seconds
Started Mar 28 01:44:58 PM PDT 24
Finished Mar 28 01:44:58 PM PDT 24
Peak memory 195892 kb
Host smart-b296194c-8588-4ed6-ac3c-c346e3c3677c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277931730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3277931730
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2714033208
Short name T1069
Test name
Test status
Simulation time 40102713883 ps
CPU time 17.44 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:45:04 PM PDT 24
Peak memory 200436 kb
Host smart-e81c6e3f-b707-4bf4-b6ba-f882ffeaac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714033208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2714033208
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.467500313
Short name T143
Test name
Test status
Simulation time 143912732538 ps
CPU time 41.03 seconds
Started Mar 28 01:44:47 PM PDT 24
Finished Mar 28 01:45:29 PM PDT 24
Peak memory 200504 kb
Host smart-d920b055-0399-4032-a0a2-e14384a02a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467500313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.467500313
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.818122454
Short name T1072
Test name
Test status
Simulation time 35416483009 ps
CPU time 65.78 seconds
Started Mar 28 01:44:47 PM PDT 24
Finished Mar 28 01:45:53 PM PDT 24
Peak memory 200304 kb
Host smart-be1aed51-51f2-4aa5-a2b5-a4ada251a692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818122454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.818122454
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2865557781
Short name T432
Test name
Test status
Simulation time 26477479136 ps
CPU time 42.19 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:45:30 PM PDT 24
Peak memory 198192 kb
Host smart-ba0da10d-3c16-4c95-8aff-7786ec074139
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865557781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2865557781
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3017584593
Short name T914
Test name
Test status
Simulation time 195076374945 ps
CPU time 589.74 seconds
Started Mar 28 01:45:06 PM PDT 24
Finished Mar 28 01:54:56 PM PDT 24
Peak memory 200428 kb
Host smart-7099c50a-1025-42fc-b0ba-29ed66f8b39d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017584593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3017584593
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1398897805
Short name T955
Test name
Test status
Simulation time 8989494483 ps
CPU time 32.55 seconds
Started Mar 28 01:44:51 PM PDT 24
Finished Mar 28 01:45:25 PM PDT 24
Peak memory 200208 kb
Host smart-e983c38f-f01e-4d14-b411-6123cbe778af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398897805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1398897805
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2049059409
Short name T849
Test name
Test status
Simulation time 9895046305 ps
CPU time 13.29 seconds
Started Mar 28 01:44:45 PM PDT 24
Finished Mar 28 01:44:59 PM PDT 24
Peak memory 200556 kb
Host smart-0fd87964-775c-4547-9c5e-b8383a7a7737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049059409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2049059409
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.243876272
Short name T382
Test name
Test status
Simulation time 13990606509 ps
CPU time 640.74 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:55:40 PM PDT 24
Peak memory 200456 kb
Host smart-b0e53148-9f50-41c6-8f40-20e58b0a2099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243876272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.243876272
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3951053485
Short name T684
Test name
Test status
Simulation time 7612014508 ps
CPU time 61.75 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:45:47 PM PDT 24
Peak memory 199696 kb
Host smart-6f609a1e-94b2-4407-88b4-03beff977a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951053485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3951053485
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3494329321
Short name T124
Test name
Test status
Simulation time 84470779496 ps
CPU time 25.11 seconds
Started Mar 28 01:44:48 PM PDT 24
Finished Mar 28 01:45:13 PM PDT 24
Peak memory 200432 kb
Host smart-99bc255b-dd49-417d-8112-320f428a3ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494329321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3494329321
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4010443848
Short name T246
Test name
Test status
Simulation time 37146076067 ps
CPU time 4.28 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:44:52 PM PDT 24
Peak memory 196020 kb
Host smart-38efcd4c-095c-4b72-86d8-a18a6d8262df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010443848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4010443848
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1060260204
Short name T86
Test name
Test status
Simulation time 348830302 ps
CPU time 0.82 seconds
Started Mar 28 01:44:57 PM PDT 24
Finished Mar 28 01:44:58 PM PDT 24
Peak memory 219008 kb
Host smart-ac683ed6-0684-4a09-b382-3b6b1c056887
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060260204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1060260204
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1951182385
Short name T788
Test name
Test status
Simulation time 406439631 ps
CPU time 2.42 seconds
Started Mar 28 01:44:40 PM PDT 24
Finished Mar 28 01:44:43 PM PDT 24
Peak memory 200296 kb
Host smart-7282a808-f9a6-4651-b974-fbcc36ada33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951182385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1951182385
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.400290785
Short name T655
Test name
Test status
Simulation time 85903557284 ps
CPU time 1598.15 seconds
Started Mar 28 01:44:59 PM PDT 24
Finished Mar 28 02:11:37 PM PDT 24
Peak memory 200480 kb
Host smart-0f19fe43-400c-4e78-ad11-59ab57e9ba03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400290785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.400290785
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.545029917
Short name T52
Test name
Test status
Simulation time 1147967220103 ps
CPU time 1134.94 seconds
Started Mar 28 01:44:57 PM PDT 24
Finished Mar 28 02:03:52 PM PDT 24
Peak memory 225416 kb
Host smart-d683b914-cda8-4fe2-8d38-f38f717b3d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545029917 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.545029917
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3724851377
Short name T389
Test name
Test status
Simulation time 4020403681 ps
CPU time 2.14 seconds
Started Mar 28 01:44:41 PM PDT 24
Finished Mar 28 01:44:44 PM PDT 24
Peak memory 200476 kb
Host smart-3298a293-36e5-4449-ba67-790e348d1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724851377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3724851377
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1505683505
Short name T393
Test name
Test status
Simulation time 69157073477 ps
CPU time 36.62 seconds
Started Mar 28 01:44:46 PM PDT 24
Finished Mar 28 01:45:24 PM PDT 24
Peak memory 200468 kb
Host smart-e055c22b-00fa-4c4d-aac0-8615d2a62783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505683505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1505683505
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3786053412
Short name T1011
Test name
Test status
Simulation time 94779042 ps
CPU time 0.53 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:22 PM PDT 24
Peak memory 195872 kb
Host smart-e4f015a9-5283-4ac8-a92f-0da5d72c1603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786053412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3786053412
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.314333663
Short name T928
Test name
Test status
Simulation time 92545075805 ps
CPU time 135.64 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:47:35 PM PDT 24
Peak memory 200476 kb
Host smart-50101439-5597-47a8-a58c-2508166e170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314333663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.314333663
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4224027991
Short name T934
Test name
Test status
Simulation time 116194607547 ps
CPU time 45.52 seconds
Started Mar 28 01:45:27 PM PDT 24
Finished Mar 28 01:46:13 PM PDT 24
Peak memory 200148 kb
Host smart-d39b05a8-6411-4827-8ee6-442ae2640c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224027991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4224027991
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2598079406
Short name T568
Test name
Test status
Simulation time 67408847951 ps
CPU time 14.53 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:45:38 PM PDT 24
Peak memory 200480 kb
Host smart-6235f83a-5978-41ca-9012-43b35bef09b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598079406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2598079406
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.87823821
Short name T854
Test name
Test status
Simulation time 36977988857 ps
CPU time 15.29 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 01:45:35 PM PDT 24
Peak memory 198068 kb
Host smart-dd50764c-7fe6-43ab-b3f7-04b0b4383e91
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87823821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.87823821
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4154246821
Short name T801
Test name
Test status
Simulation time 128594780056 ps
CPU time 800.77 seconds
Started Mar 28 01:45:29 PM PDT 24
Finished Mar 28 01:58:50 PM PDT 24
Peak memory 200496 kb
Host smart-c855ba01-3436-4a16-a634-c44592ea7516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4154246821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4154246821
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1189964124
Short name T353
Test name
Test status
Simulation time 7974021980 ps
CPU time 17.63 seconds
Started Mar 28 01:45:27 PM PDT 24
Finished Mar 28 01:45:45 PM PDT 24
Peak memory 199948 kb
Host smart-18b84e9d-8fdd-480f-9939-dba4d0f69353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189964124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1189964124
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2824182870
Short name T782
Test name
Test status
Simulation time 100850092465 ps
CPU time 134.58 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:47:33 PM PDT 24
Peak memory 200744 kb
Host smart-a4f471da-fd18-4bbe-b962-8d29fee7809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824182870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2824182870
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2672344202
Short name T924
Test name
Test status
Simulation time 11234797811 ps
CPU time 176.33 seconds
Started Mar 28 01:45:26 PM PDT 24
Finished Mar 28 01:48:22 PM PDT 24
Peak memory 200388 kb
Host smart-986158ea-e32b-432b-8243-a872a74346fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672344202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2672344202
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.873614856
Short name T607
Test name
Test status
Simulation time 7127370613 ps
CPU time 59.62 seconds
Started Mar 28 01:45:30 PM PDT 24
Finished Mar 28 01:46:30 PM PDT 24
Peak memory 198532 kb
Host smart-58a4bc27-a091-40ce-9c9d-a5ffe339b1e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873614856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.873614856
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3409337741
Short name T465
Test name
Test status
Simulation time 89016965089 ps
CPU time 170.89 seconds
Started Mar 28 01:45:26 PM PDT 24
Finished Mar 28 01:48:17 PM PDT 24
Peak memory 200420 kb
Host smart-4b550dfd-b521-403f-a8ee-14b2a0c1b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409337741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3409337741
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1345392332
Short name T449
Test name
Test status
Simulation time 3097716009 ps
CPU time 1.79 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:24 PM PDT 24
Peak memory 196512 kb
Host smart-df4271af-4fb0-4378-8f61-33dfed2b153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345392332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1345392332
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3974952548
Short name T306
Test name
Test status
Simulation time 6243685796 ps
CPU time 14.15 seconds
Started Mar 28 01:45:26 PM PDT 24
Finished Mar 28 01:45:41 PM PDT 24
Peak memory 200444 kb
Host smart-6fc6de45-cc91-4aef-8930-4c4aa1fe8acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974952548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3974952548
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.206754838
Short name T578
Test name
Test status
Simulation time 303454340471 ps
CPU time 1066.59 seconds
Started Mar 28 01:45:29 PM PDT 24
Finished Mar 28 02:03:16 PM PDT 24
Peak memory 200520 kb
Host smart-8dd02699-ad5d-438a-99fa-e97a3fcbb328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206754838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.206754838
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.903759839
Short name T795
Test name
Test status
Simulation time 225877575427 ps
CPU time 922.21 seconds
Started Mar 28 01:45:29 PM PDT 24
Finished Mar 28 02:00:52 PM PDT 24
Peak memory 217040 kb
Host smart-cc724fc4-69f6-4dac-a118-153a053ac5d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903759839 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.903759839
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.979342324
Short name T569
Test name
Test status
Simulation time 1012334361 ps
CPU time 4.38 seconds
Started Mar 28 01:45:29 PM PDT 24
Finished Mar 28 01:45:34 PM PDT 24
Peak memory 200224 kb
Host smart-7f2a579c-910a-4328-849e-6ef5a3cd03c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979342324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.979342324
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3925640691
Short name T710
Test name
Test status
Simulation time 99140175133 ps
CPU time 38.33 seconds
Started Mar 28 01:45:30 PM PDT 24
Finished Mar 28 01:46:08 PM PDT 24
Peak memory 200260 kb
Host smart-88a7b52c-6c7d-4bef-bd6c-455041a295ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925640691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3925640691
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3688621466
Short name T133
Test name
Test status
Simulation time 38329161110 ps
CPU time 13.94 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:49:03 PM PDT 24
Peak memory 200472 kb
Host smart-ec2ebf41-4679-49cf-84ee-e15ad50a9042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688621466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3688621466
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3538760469
Short name T668
Test name
Test status
Simulation time 235839518116 ps
CPU time 42.75 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:49:32 PM PDT 24
Peak memory 200412 kb
Host smart-a7540cd0-fb7c-4f5d-aaa3-5d7b69e2e19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538760469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3538760469
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3641400856
Short name T395
Test name
Test status
Simulation time 155316129613 ps
CPU time 118.67 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:50:51 PM PDT 24
Peak memory 200508 kb
Host smart-64a03c21-ff0c-4e69-a980-2c6333efd3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641400856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3641400856
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1112621455
Short name T323
Test name
Test status
Simulation time 140837737842 ps
CPU time 51.74 seconds
Started Mar 28 01:48:57 PM PDT 24
Finished Mar 28 01:49:49 PM PDT 24
Peak memory 200456 kb
Host smart-49eb0322-6929-411b-8b42-5d9c45782d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112621455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1112621455
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2376960263
Short name T122
Test name
Test status
Simulation time 37029569128 ps
CPU time 32.07 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:49:33 PM PDT 24
Peak memory 200364 kb
Host smart-7773042a-4e94-4eca-a9d4-aa8187f36185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376960263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2376960263
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.324077369
Short name T963
Test name
Test status
Simulation time 38970464599 ps
CPU time 58.77 seconds
Started Mar 28 01:49:00 PM PDT 24
Finished Mar 28 01:50:00 PM PDT 24
Peak memory 200456 kb
Host smart-fd37805e-a222-42ce-8c16-7d062abf1292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324077369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.324077369
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3439878050
Short name T837
Test name
Test status
Simulation time 8817502478 ps
CPU time 26.74 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:49:19 PM PDT 24
Peak memory 200496 kb
Host smart-0664b6a8-2682-4ae6-a7bf-1b9257bf1ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439878050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3439878050
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3475706317
Short name T836
Test name
Test status
Simulation time 110663250519 ps
CPU time 56.7 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:49:58 PM PDT 24
Peak memory 200504 kb
Host smart-220fcf85-fa83-4cea-a608-c416e4b27949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475706317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3475706317
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.467375661
Short name T735
Test name
Test status
Simulation time 46736602210 ps
CPU time 39.37 seconds
Started Mar 28 01:45:29 PM PDT 24
Finished Mar 28 01:46:09 PM PDT 24
Peak memory 200416 kb
Host smart-e3333958-5bb8-443c-89d0-4bf4c17c70fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467375661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.467375661
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.513943736
Short name T307
Test name
Test status
Simulation time 133096993644 ps
CPU time 188.01 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 01:48:28 PM PDT 24
Peak memory 200492 kb
Host smart-d3d4d052-6b56-4542-a15d-3119d797e0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513943736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.513943736
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2042524387
Short name T258
Test name
Test status
Simulation time 22522996389 ps
CPU time 23.41 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:45 PM PDT 24
Peak memory 200444 kb
Host smart-d4eb34ce-eb2d-40f6-a2be-0e64aacc78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042524387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2042524387
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1820256088
Short name T384
Test name
Test status
Simulation time 22049194107 ps
CPU time 15.63 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:38 PM PDT 24
Peak memory 199336 kb
Host smart-82506c64-2769-4602-b727-e8b658ee7fb4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820256088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1820256088
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2998617352
Short name T1123
Test name
Test status
Simulation time 77078660804 ps
CPU time 202.22 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:49:03 PM PDT 24
Peak memory 200400 kb
Host smart-4ec3288e-da72-4299-b4ab-25139b6e58cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998617352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2998617352
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.907213422
Short name T599
Test name
Test status
Simulation time 5560810986 ps
CPU time 11.07 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:45:35 PM PDT 24
Peak memory 199404 kb
Host smart-ec8ed5cf-e682-41fd-a048-43dfa9506336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907213422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.907213422
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1170951650
Short name T248
Test name
Test status
Simulation time 205688553298 ps
CPU time 125.39 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:47:29 PM PDT 24
Peak memory 200828 kb
Host smart-ab6ac73b-1c89-4498-9c5f-9823715af4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170951650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1170951650
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3062470729
Short name T301
Test name
Test status
Simulation time 16248746793 ps
CPU time 481.23 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:53:41 PM PDT 24
Peak memory 200472 kb
Host smart-7dd3f7b7-4835-4469-b744-7239818fddcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062470729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3062470729
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4215488693
Short name T362
Test name
Test status
Simulation time 4506180890 ps
CPU time 20.48 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:45:43 PM PDT 24
Peak memory 199732 kb
Host smart-a2bd1cc4-7529-478d-927c-27f87b6a9003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215488693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4215488693
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3274061633
Short name T666
Test name
Test status
Simulation time 248322704513 ps
CPU time 28.84 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:45:52 PM PDT 24
Peak memory 200508 kb
Host smart-b0f8fd22-a837-4e19-8d27-ce19891e92af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274061633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3274061633
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.98836367
Short name T971
Test name
Test status
Simulation time 4246288829 ps
CPU time 4.16 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:45:28 PM PDT 24
Peak memory 196528 kb
Host smart-7375c6f7-bfad-47bd-8a1a-b337a25ec7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98836367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.98836367
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1292585679
Short name T726
Test name
Test status
Simulation time 6218031260 ps
CPU time 20.28 seconds
Started Mar 28 01:45:26 PM PDT 24
Finished Mar 28 01:45:46 PM PDT 24
Peak memory 200424 kb
Host smart-5e05dc77-6dfc-4c95-9ee4-8aba461ef4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292585679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1292585679
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1603789401
Short name T1171
Test name
Test status
Simulation time 167667574776 ps
CPU time 76.13 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:46:57 PM PDT 24
Peak memory 200548 kb
Host smart-7b7f30dd-d866-4719-9101-3fe4a3ae3c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603789401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1603789401
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.35186164
Short name T880
Test name
Test status
Simulation time 611474448 ps
CPU time 2.3 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:25 PM PDT 24
Peak memory 200420 kb
Host smart-f7930a2e-0286-46d2-b1ff-ffd7a0a3c31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35186164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.35186164
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.142418991
Short name T902
Test name
Test status
Simulation time 61823615013 ps
CPU time 31.25 seconds
Started Mar 28 01:45:26 PM PDT 24
Finished Mar 28 01:45:57 PM PDT 24
Peak memory 200452 kb
Host smart-3cc3f8c7-ad59-40bb-9c15-cae397f97062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142418991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.142418991
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2634633599
Short name T583
Test name
Test status
Simulation time 33913461994 ps
CPU time 55.71 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:49:48 PM PDT 24
Peak memory 200460 kb
Host smart-bd426c4d-4bc8-4f35-ad5c-b1cd61120ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634633599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2634633599
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2710146442
Short name T833
Test name
Test status
Simulation time 25498222886 ps
CPU time 31.26 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:49:20 PM PDT 24
Peak memory 200488 kb
Host smart-acc975d2-dd9d-49e5-bec6-1e36ffe1f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710146442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2710146442
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.988310043
Short name T786
Test name
Test status
Simulation time 81639847669 ps
CPU time 209.24 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:52:30 PM PDT 24
Peak memory 200460 kb
Host smart-4c486825-c558-4158-bf41-d4593de58246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988310043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.988310043
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.536132331
Short name T832
Test name
Test status
Simulation time 29524356642 ps
CPU time 45.83 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:49:37 PM PDT 24
Peak memory 200440 kb
Host smart-57423719-da19-4547-b634-d7bbb1987a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536132331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.536132331
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2230163154
Short name T937
Test name
Test status
Simulation time 80854386860 ps
CPU time 43.17 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 01:49:31 PM PDT 24
Peak memory 200508 kb
Host smart-ab2da028-2af1-4832-99df-37ff1dbe321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230163154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2230163154
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.952427574
Short name T321
Test name
Test status
Simulation time 173681039195 ps
CPU time 304.08 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:53:53 PM PDT 24
Peak memory 200420 kb
Host smart-68f5ec80-2896-4ceb-9079-ee90f59677af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952427574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.952427574
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1512091601
Short name T489
Test name
Test status
Simulation time 140558403020 ps
CPU time 70.61 seconds
Started Mar 28 01:48:54 PM PDT 24
Finished Mar 28 01:50:05 PM PDT 24
Peak memory 200492 kb
Host smart-1a5462ec-98f2-42c7-ad00-92d0ce31e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512091601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1512091601
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4176282696
Short name T847
Test name
Test status
Simulation time 42186254105 ps
CPU time 56.27 seconds
Started Mar 28 01:48:54 PM PDT 24
Finished Mar 28 01:49:51 PM PDT 24
Peak memory 200516 kb
Host smart-716380e5-69b0-4c90-a8f1-6fac9235579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176282696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4176282696
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2411246460
Short name T238
Test name
Test status
Simulation time 41418194757 ps
CPU time 20.41 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:49:07 PM PDT 24
Peak memory 200404 kb
Host smart-c20dd83e-1352-4b3d-9cb4-2e560dd4da4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411246460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2411246460
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2100437392
Short name T410
Test name
Test status
Simulation time 10862322 ps
CPU time 0.54 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:45:40 PM PDT 24
Peak memory 195332 kb
Host smart-f9b45b0e-8fa2-48d3-ad11-df7def460f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100437392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2100437392
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2078944622
Short name T857
Test name
Test status
Simulation time 62137386024 ps
CPU time 66.01 seconds
Started Mar 28 01:45:37 PM PDT 24
Finished Mar 28 01:46:44 PM PDT 24
Peak memory 200532 kb
Host smart-6c1b0b12-d98d-4518-94a6-fabf250707e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078944622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2078944622
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2764602610
Short name T372
Test name
Test status
Simulation time 57997694545 ps
CPU time 93.37 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:47:15 PM PDT 24
Peak memory 200476 kb
Host smart-e6453e6c-2eee-487d-82f1-71dce1990445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764602610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2764602610
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.64522572
Short name T1118
Test name
Test status
Simulation time 45124526572 ps
CPU time 29.95 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:46:11 PM PDT 24
Peak memory 200440 kb
Host smart-909f9a0e-e644-48ec-b163-8be839a0e3b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64522572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.64522572
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_loopback.41287653
Short name T910
Test name
Test status
Simulation time 878678996 ps
CPU time 1.87 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:45:44 PM PDT 24
Peak memory 196544 kb
Host smart-f83e94fd-f830-4edb-890c-a4136c977d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41287653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.41287653
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.907888003
Short name T256
Test name
Test status
Simulation time 231100059629 ps
CPU time 205.04 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:49:06 PM PDT 24
Peak memory 216200 kb
Host smart-83f383bc-6c9e-4180-a5f6-18472a38d7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907888003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.907888003
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2702945338
Short name T373
Test name
Test status
Simulation time 11401353067 ps
CPU time 516.53 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:54:18 PM PDT 24
Peak memory 200508 kb
Host smart-71aac095-f1e0-4233-a5c2-dd93f851eedb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702945338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2702945338
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3114290065
Short name T1174
Test name
Test status
Simulation time 3389510836 ps
CPU time 23.42 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:46:04 PM PDT 24
Peak memory 199348 kb
Host smart-2c73d336-ddd5-40d7-800f-c41f46a2e4d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114290065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3114290065
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3142959637
Short name T391
Test name
Test status
Simulation time 60611239818 ps
CPU time 30.99 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:46:13 PM PDT 24
Peak memory 200504 kb
Host smart-935a92a9-a20c-45c8-a438-0327116302ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142959637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3142959637
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1198531405
Short name T761
Test name
Test status
Simulation time 3174241934 ps
CPU time 6.01 seconds
Started Mar 28 01:45:44 PM PDT 24
Finished Mar 28 01:45:51 PM PDT 24
Peak memory 196100 kb
Host smart-e609d277-2c45-4623-a6ac-176afabc0f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198531405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1198531405
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2388069982
Short name T591
Test name
Test status
Simulation time 288451185 ps
CPU time 1.82 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:45:42 PM PDT 24
Peak memory 199524 kb
Host smart-a24a9018-e4f3-4508-90d7-e7b8d72fff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388069982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2388069982
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3713383410
Short name T1122
Test name
Test status
Simulation time 106685687879 ps
CPU time 254.75 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:49:56 PM PDT 24
Peak memory 200492 kb
Host smart-a1888f6a-b4da-4c11-951c-c3b2c09db3d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713383410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3713383410
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4104492263
Short name T717
Test name
Test status
Simulation time 55847577975 ps
CPU time 1862.81 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 02:16:45 PM PDT 24
Peak memory 217384 kb
Host smart-bdcee7ba-5452-4faf-97fd-3955884b67a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104492263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4104492263
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.119234519
Short name T459
Test name
Test status
Simulation time 1614592572 ps
CPU time 1.94 seconds
Started Mar 28 01:45:45 PM PDT 24
Finished Mar 28 01:45:47 PM PDT 24
Peak memory 199176 kb
Host smart-3791aea8-9a18-4c66-a54c-4a2a40ed1fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119234519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.119234519
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2733026127
Short name T36
Test name
Test status
Simulation time 81445714101 ps
CPU time 110.2 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:47:31 PM PDT 24
Peak memory 200428 kb
Host smart-6b6c31f9-d419-43c2-ae22-73796744ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733026127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2733026127
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3740988018
Short name T556
Test name
Test status
Simulation time 13670254974 ps
CPU time 25.02 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:49:16 PM PDT 24
Peak memory 200480 kb
Host smart-e73a4225-d59f-4578-940b-fb0192e203f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740988018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3740988018
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3193085632
Short name T137
Test name
Test status
Simulation time 40052580332 ps
CPU time 18.26 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:49:08 PM PDT 24
Peak memory 200132 kb
Host smart-23d1e663-ff9a-4900-82aa-7489f4f2a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193085632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3193085632
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3274608450
Short name T476
Test name
Test status
Simulation time 28919262349 ps
CPU time 12.44 seconds
Started Mar 28 01:49:09 PM PDT 24
Finished Mar 28 01:49:22 PM PDT 24
Peak memory 200420 kb
Host smart-a7444796-038b-45f2-bd9c-9d47b157f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274608450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3274608450
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3059271034
Short name T936
Test name
Test status
Simulation time 180140042923 ps
CPU time 26.87 seconds
Started Mar 28 01:49:11 PM PDT 24
Finished Mar 28 01:49:38 PM PDT 24
Peak memory 200504 kb
Host smart-91328a50-2d7e-420c-a17d-363645d52fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059271034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3059271034
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3209870349
Short name T897
Test name
Test status
Simulation time 114194876769 ps
CPU time 230.62 seconds
Started Mar 28 01:49:13 PM PDT 24
Finished Mar 28 01:53:04 PM PDT 24
Peak memory 200500 kb
Host smart-9d469590-9452-46b1-b158-ad7c21345583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209870349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3209870349
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3804906962
Short name T713
Test name
Test status
Simulation time 44032096763 ps
CPU time 59.26 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:50:03 PM PDT 24
Peak memory 200520 kb
Host smart-a5a26e9e-ea54-4f51-a2b1-5759ebf5b53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804906962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3804906962
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1659712508
Short name T823
Test name
Test status
Simulation time 58040000679 ps
CPU time 211.41 seconds
Started Mar 28 01:49:12 PM PDT 24
Finished Mar 28 01:52:44 PM PDT 24
Peak memory 200528 kb
Host smart-556d73c1-8cce-413d-80e2-4c0c27df04c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659712508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1659712508
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3439765107
Short name T388
Test name
Test status
Simulation time 16187632 ps
CPU time 0.56 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:45:43 PM PDT 24
Peak memory 195880 kb
Host smart-f280fbdf-4dc6-4a3a-b6fe-0cbeda186aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439765107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3439765107
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2861462807
Short name T417
Test name
Test status
Simulation time 35060530145 ps
CPU time 54.79 seconds
Started Mar 28 01:45:44 PM PDT 24
Finished Mar 28 01:46:39 PM PDT 24
Peak memory 200524 kb
Host smart-97e9f662-0340-4fdb-a56f-002625ab788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861462807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2861462807
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2410729878
Short name T748
Test name
Test status
Simulation time 16381108384 ps
CPU time 13.31 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:45:54 PM PDT 24
Peak memory 200436 kb
Host smart-2a310320-45b3-42c2-9ae4-f4cb0a6a7750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410729878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2410729878
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.195644050
Short name T992
Test name
Test status
Simulation time 323993148569 ps
CPU time 285.9 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:50:27 PM PDT 24
Peak memory 199704 kb
Host smart-934c8cec-d59d-4b1a-831c-f0bc1c74e243
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195644050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.195644050
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1934160555
Short name T741
Test name
Test status
Simulation time 246718047072 ps
CPU time 462.04 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:53:22 PM PDT 24
Peak memory 200516 kb
Host smart-42a36434-4544-449e-a4f3-497be214fd10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934160555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1934160555
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.4278459188
Short name T961
Test name
Test status
Simulation time 7839684026 ps
CPU time 7.62 seconds
Started Mar 28 01:45:38 PM PDT 24
Finished Mar 28 01:45:46 PM PDT 24
Peak memory 199184 kb
Host smart-2e7090d7-2be6-49e9-a4d8-2288d8e56dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278459188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.4278459188
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2837876821
Short name T1158
Test name
Test status
Simulation time 178339076266 ps
CPU time 126.2 seconds
Started Mar 28 01:45:37 PM PDT 24
Finished Mar 28 01:47:43 PM PDT 24
Peak memory 200752 kb
Host smart-c401a8cd-4960-4303-91e6-8584779425d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837876821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2837876821
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2888553072
Short name T1127
Test name
Test status
Simulation time 12426214976 ps
CPU time 658.58 seconds
Started Mar 28 01:45:45 PM PDT 24
Finished Mar 28 01:56:44 PM PDT 24
Peak memory 200360 kb
Host smart-ca16a3ef-1873-432c-ae6e-40cc161e2ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888553072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2888553072
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2721058744
Short name T632
Test name
Test status
Simulation time 3815512465 ps
CPU time 6.47 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:45:46 PM PDT 24
Peak memory 199596 kb
Host smart-82df1453-0e06-4cc7-a164-05004781c65b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721058744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2721058744
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.202292301
Short name T884
Test name
Test status
Simulation time 19777585135 ps
CPU time 27.47 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:46:07 PM PDT 24
Peak memory 200460 kb
Host smart-80a4ac5e-7ca8-4a12-97b4-83686e49a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202292301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.202292301
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3645267553
Short name T437
Test name
Test status
Simulation time 45472602737 ps
CPU time 8.89 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:45:49 PM PDT 24
Peak memory 196204 kb
Host smart-c2abfe6a-1909-40c7-a687-c3caf12f8616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645267553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3645267553
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3995362923
Short name T751
Test name
Test status
Simulation time 823326775 ps
CPU time 1.1 seconds
Started Mar 28 01:45:44 PM PDT 24
Finished Mar 28 01:45:45 PM PDT 24
Peak memory 199232 kb
Host smart-34a15608-c14a-48f5-a212-569050f336b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995362923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3995362923
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2840750707
Short name T1175
Test name
Test status
Simulation time 33173309291 ps
CPU time 1086.7 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 02:03:48 PM PDT 24
Peak memory 200468 kb
Host smart-0b1cad8e-fd74-4747-88c4-0ec01452bfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840750707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2840750707
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4190497687
Short name T797
Test name
Test status
Simulation time 319521244610 ps
CPU time 629.99 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:56:10 PM PDT 24
Peak memory 225420 kb
Host smart-8945d610-d584-4215-a5fb-adaeb03204e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190497687 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4190497687
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1650896586
Short name T595
Test name
Test status
Simulation time 1261556940 ps
CPU time 2.09 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:45:45 PM PDT 24
Peak memory 199268 kb
Host smart-79e3cfb3-4cda-49d9-a465-d892b2a505ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650896586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1650896586
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1853051682
Short name T812
Test name
Test status
Simulation time 31970961125 ps
CPU time 65.86 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:46:47 PM PDT 24
Peak memory 200480 kb
Host smart-1712d5aa-1202-4596-95e3-f9f6dfe21e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853051682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1853051682
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.834399528
Short name T587
Test name
Test status
Simulation time 41591168309 ps
CPU time 81.77 seconds
Started Mar 28 01:49:12 PM PDT 24
Finished Mar 28 01:50:35 PM PDT 24
Peak memory 200540 kb
Host smart-77cf3d22-b8c2-40c3-94a1-2fad49c075c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834399528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.834399528
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4269257265
Short name T170
Test name
Test status
Simulation time 121374211190 ps
CPU time 212.09 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:52:34 PM PDT 24
Peak memory 200504 kb
Host smart-bc170db2-b57d-4518-83c0-0932f84f5f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269257265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4269257265
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3995786603
Short name T185
Test name
Test status
Simulation time 168451770402 ps
CPU time 192.85 seconds
Started Mar 28 01:49:11 PM PDT 24
Finished Mar 28 01:52:25 PM PDT 24
Peak memory 200448 kb
Host smart-7685440c-099c-49c2-bda5-4b33e36b64bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995786603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3995786603
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1848429456
Short name T594
Test name
Test status
Simulation time 24486909502 ps
CPU time 9.48 seconds
Started Mar 28 01:49:04 PM PDT 24
Finished Mar 28 01:49:14 PM PDT 24
Peak memory 200472 kb
Host smart-790aafd8-f33b-4ff3-ba16-0def4de48a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848429456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1848429456
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2988399998
Short name T716
Test name
Test status
Simulation time 63536694638 ps
CPU time 26.48 seconds
Started Mar 28 01:49:11 PM PDT 24
Finished Mar 28 01:49:38 PM PDT 24
Peak memory 200456 kb
Host smart-c6460d47-0e7c-4631-958e-db3219842cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988399998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2988399998
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2391039882
Short name T423
Test name
Test status
Simulation time 111939785340 ps
CPU time 101.42 seconds
Started Mar 28 01:49:10 PM PDT 24
Finished Mar 28 01:50:52 PM PDT 24
Peak memory 200512 kb
Host smart-2fb20db1-4f01-4dc7-901e-8845a398f365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391039882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2391039882
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1770876416
Short name T670
Test name
Test status
Simulation time 51029367231 ps
CPU time 22.25 seconds
Started Mar 28 01:49:06 PM PDT 24
Finished Mar 28 01:49:29 PM PDT 24
Peak memory 200432 kb
Host smart-50a47bb1-3e0c-4e78-9aac-b73d15a7a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770876416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1770876416
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3751305896
Short name T999
Test name
Test status
Simulation time 53636405045 ps
CPU time 43.77 seconds
Started Mar 28 01:49:06 PM PDT 24
Finished Mar 28 01:49:50 PM PDT 24
Peak memory 200488 kb
Host smart-eed3684b-e9cc-475b-9320-2135249e3c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751305896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3751305896
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2185861464
Short name T240
Test name
Test status
Simulation time 49203922350 ps
CPU time 33.72 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:49:36 PM PDT 24
Peak memory 200476 kb
Host smart-8cfe1e0a-68ea-4dee-bf20-8350d169b8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185861464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2185861464
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1833617041
Short name T390
Test name
Test status
Simulation time 27903131 ps
CPU time 0.58 seconds
Started Mar 28 01:45:49 PM PDT 24
Finished Mar 28 01:45:50 PM PDT 24
Peak memory 195612 kb
Host smart-8d3bfa6b-1f71-43d0-8a75-816a331dd60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833617041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1833617041
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2960368967
Short name T803
Test name
Test status
Simulation time 82613964867 ps
CPU time 39.32 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:46:23 PM PDT 24
Peak memory 200428 kb
Host smart-be10b50a-7a31-4f43-b6d3-426dff02c473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960368967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2960368967
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.774774455
Short name T499
Test name
Test status
Simulation time 14825195822 ps
CPU time 33.94 seconds
Started Mar 28 01:45:44 PM PDT 24
Finished Mar 28 01:46:18 PM PDT 24
Peak memory 200304 kb
Host smart-e9d5487f-9696-4e43-ab5d-eb46e94c556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774774455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.774774455
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.2349656403
Short name T780
Test name
Test status
Simulation time 376476051283 ps
CPU time 544.26 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:54:47 PM PDT 24
Peak memory 198768 kb
Host smart-6066230c-937b-4695-8156-4a638022ad39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349656403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2349656403
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1638853628
Short name T898
Test name
Test status
Simulation time 149933692906 ps
CPU time 722.61 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:57:49 PM PDT 24
Peak memory 200440 kb
Host smart-f74b7825-c991-4574-a33b-0cb56f08afae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638853628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1638853628
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.685714047
Short name T652
Test name
Test status
Simulation time 10872609500 ps
CPU time 34.28 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:46:16 PM PDT 24
Peak memory 200480 kb
Host smart-96281991-9860-42d4-8809-ee4963859cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685714047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.685714047
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.1798607162
Short name T766
Test name
Test status
Simulation time 13321994811 ps
CPU time 375.95 seconds
Started Mar 28 01:45:45 PM PDT 24
Finished Mar 28 01:52:02 PM PDT 24
Peak memory 200464 kb
Host smart-39849582-6172-4569-a6ae-eed33044575d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798607162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1798607162
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1729165010
Short name T480
Test name
Test status
Simulation time 5785868509 ps
CPU time 31.25 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:46:14 PM PDT 24
Peak memory 199748 kb
Host smart-fefb3ed8-196d-4307-8e72-d448ce4891d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729165010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1729165010
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2506494285
Short name T1163
Test name
Test status
Simulation time 28610223842 ps
CPU time 7.92 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:45:47 PM PDT 24
Peak memory 200472 kb
Host smart-e744e284-5b1e-42dc-990c-324300f8afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506494285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2506494285
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2042388833
Short name T787
Test name
Test status
Simulation time 34545310118 ps
CPU time 56.79 seconds
Started Mar 28 01:45:44 PM PDT 24
Finished Mar 28 01:46:41 PM PDT 24
Peak memory 196304 kb
Host smart-3d95bc59-106a-495e-b1c6-676dec84c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042388833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2042388833
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3009798717
Short name T304
Test name
Test status
Simulation time 5670785685 ps
CPU time 11.67 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:45:53 PM PDT 24
Peak memory 200488 kb
Host smart-f6fadb24-4bf6-4f1e-833f-c12648ce9333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009798717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3009798717
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2416161377
Short name T973
Test name
Test status
Simulation time 268000707246 ps
CPU time 214.01 seconds
Started Mar 28 01:45:51 PM PDT 24
Finished Mar 28 01:49:25 PM PDT 24
Peak memory 208872 kb
Host smart-d7440460-e50b-49f4-b26b-f57df67e1166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416161377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2416161377
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2245378002
Short name T552
Test name
Test status
Simulation time 127220339736 ps
CPU time 565.13 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:55:11 PM PDT 24
Peak memory 225408 kb
Host smart-81756764-8022-4666-998a-a55d8f2486be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245378002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2245378002
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.470909244
Short name T601
Test name
Test status
Simulation time 1211380713 ps
CPU time 4.46 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:45:48 PM PDT 24
Peak memory 200372 kb
Host smart-7dc77554-2cd8-4be5-9d83-0bdefea165fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470909244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.470909244
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.771212693
Short name T1144
Test name
Test status
Simulation time 140679505657 ps
CPU time 16.03 seconds
Started Mar 28 01:45:39 PM PDT 24
Finished Mar 28 01:45:56 PM PDT 24
Peak memory 200512 kb
Host smart-024ba8f8-b5ef-47f4-a3b8-d6705f8ec866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771212693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.771212693
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.4170509457
Short name T380
Test name
Test status
Simulation time 18765412689 ps
CPU time 14.82 seconds
Started Mar 28 01:49:06 PM PDT 24
Finished Mar 28 01:49:21 PM PDT 24
Peak memory 200204 kb
Host smart-a0109e42-cf73-4c06-a41b-4e57a0d6dc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170509457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4170509457
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.962364125
Short name T203
Test name
Test status
Simulation time 33184596009 ps
CPU time 19.5 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:49:22 PM PDT 24
Peak memory 200492 kb
Host smart-d6b9fc7c-96c7-4cb4-83aa-79c71238ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962364125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.962364125
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3124145679
Short name T746
Test name
Test status
Simulation time 146647182910 ps
CPU time 98.23 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:50:40 PM PDT 24
Peak memory 200500 kb
Host smart-83dd28f1-bd4c-4435-b9a2-a102a1032394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124145679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3124145679
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2860210951
Short name T474
Test name
Test status
Simulation time 46913726987 ps
CPU time 121.31 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:51:03 PM PDT 24
Peak memory 200308 kb
Host smart-40a1a089-fe84-4944-b8d2-d87c015d9dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860210951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2860210951
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1329286619
Short name T659
Test name
Test status
Simulation time 29236663189 ps
CPU time 33.01 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:49:36 PM PDT 24
Peak memory 200524 kb
Host smart-878c1a8d-e033-48d1-b51c-6f5b9b1e140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329286619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1329286619
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2664228451
Short name T831
Test name
Test status
Simulation time 155672902525 ps
CPU time 94.2 seconds
Started Mar 28 01:49:13 PM PDT 24
Finished Mar 28 01:50:47 PM PDT 24
Peak memory 200564 kb
Host smart-5901e85d-47a0-445c-a534-d31866e6c17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664228451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2664228451
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1105801597
Short name T757
Test name
Test status
Simulation time 115666871811 ps
CPU time 170.84 seconds
Started Mar 28 01:49:08 PM PDT 24
Finished Mar 28 01:52:00 PM PDT 24
Peak memory 200480 kb
Host smart-ff221396-4fbc-4fda-9a78-2050731f4f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105801597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1105801597
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.856064189
Short name T1036
Test name
Test status
Simulation time 20169370529 ps
CPU time 20.4 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:49:24 PM PDT 24
Peak memory 200220 kb
Host smart-e0cb238c-4a99-4254-b8f0-d254ae62cb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856064189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.856064189
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2608648068
Short name T1094
Test name
Test status
Simulation time 25971817 ps
CPU time 0.55 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:45:47 PM PDT 24
Peak memory 195844 kb
Host smart-c807f020-dbad-4080-89fa-a9f708397379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608648068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2608648068
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.839606040
Short name T698
Test name
Test status
Simulation time 70753859669 ps
CPU time 51.9 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:46:35 PM PDT 24
Peak memory 200496 kb
Host smart-9218a0b2-3f0e-4441-9c0b-4148530a5113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839606040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.839606040
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2538990487
Short name T889
Test name
Test status
Simulation time 23042111162 ps
CPU time 44.34 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:46:31 PM PDT 24
Peak memory 200484 kb
Host smart-070c4df8-2b4c-4e44-97c3-4b80533ad68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538990487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2538990487
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2686447245
Short name T683
Test name
Test status
Simulation time 30942952935 ps
CPU time 13.89 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:46:01 PM PDT 24
Peak memory 200180 kb
Host smart-d1818a6b-a716-4624-a1be-19cdb7f7d716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686447245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2686447245
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3565297149
Short name T750
Test name
Test status
Simulation time 30794879502 ps
CPU time 14.41 seconds
Started Mar 28 01:45:44 PM PDT 24
Finished Mar 28 01:45:59 PM PDT 24
Peak memory 200424 kb
Host smart-a132300f-ffa0-4bfc-b7b9-ecf90d404f77
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565297149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3565297149
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2334192518
Short name T398
Test name
Test status
Simulation time 119947549058 ps
CPU time 411.04 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:52:39 PM PDT 24
Peak memory 200456 kb
Host smart-48a2d87e-6dd2-4582-8d22-44b63660e49d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334192518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2334192518
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3576689216
Short name T764
Test name
Test status
Simulation time 16666837174 ps
CPU time 4.63 seconds
Started Mar 28 01:45:45 PM PDT 24
Finished Mar 28 01:45:49 PM PDT 24
Peak memory 199788 kb
Host smart-c2384232-d0ec-499b-8e2a-1fe7aff0f33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576689216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3576689216
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3160352098
Short name T269
Test name
Test status
Simulation time 131611399149 ps
CPU time 109.36 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:47:36 PM PDT 24
Peak memory 217084 kb
Host smart-f6bd9086-ca6c-4c40-b9d0-737cf575bb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160352098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3160352098
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4195345155
Short name T618
Test name
Test status
Simulation time 13875077429 ps
CPU time 63.45 seconds
Started Mar 28 01:45:45 PM PDT 24
Finished Mar 28 01:46:48 PM PDT 24
Peak memory 200504 kb
Host smart-b33ce361-9656-4dbc-950e-65807a749349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195345155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4195345155
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1352358989
Short name T581
Test name
Test status
Simulation time 4317408131 ps
CPU time 33.92 seconds
Started Mar 28 01:45:41 PM PDT 24
Finished Mar 28 01:46:15 PM PDT 24
Peak memory 198684 kb
Host smart-8caabc45-4fb2-4275-b05b-414fabe34d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352358989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1352358989
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1677870524
Short name T1116
Test name
Test status
Simulation time 30346288071 ps
CPU time 21.84 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:46:09 PM PDT 24
Peak memory 200500 kb
Host smart-bc1f6dc7-9d8a-428b-9cf2-c827bad7f036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677870524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1677870524
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.4042187582
Short name T368
Test name
Test status
Simulation time 511592776 ps
CPU time 1.45 seconds
Started Mar 28 01:45:48 PM PDT 24
Finished Mar 28 01:45:50 PM PDT 24
Peak memory 195916 kb
Host smart-92294d88-4bd6-4414-8be7-1159d1c0b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042187582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.4042187582
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.940899456
Short name T575
Test name
Test status
Simulation time 5906041320 ps
CPU time 8.32 seconds
Started Mar 28 01:45:51 PM PDT 24
Finished Mar 28 01:46:00 PM PDT 24
Peak memory 200148 kb
Host smart-f1555422-3a0c-425d-aa78-85cf301a3f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940899456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.940899456
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.380959583
Short name T1003
Test name
Test status
Simulation time 243216363610 ps
CPU time 580.66 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:55:27 PM PDT 24
Peak memory 200484 kb
Host smart-7db80740-a465-4a82-a292-ecb3b6ae3fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380959583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.380959583
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3865068508
Short name T460
Test name
Test status
Simulation time 181226949825 ps
CPU time 377.56 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:52:05 PM PDT 24
Peak memory 217212 kb
Host smart-3b671675-e194-4993-b813-561ed968a4b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865068508 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3865068508
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1149990570
Short name T433
Test name
Test status
Simulation time 6960820865 ps
CPU time 10.9 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:45:57 PM PDT 24
Peak memory 200188 kb
Host smart-b867a302-c221-45a0-98b8-ff5cb6ead158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149990570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1149990570
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.191731323
Short name T1121
Test name
Test status
Simulation time 145288602312 ps
CPU time 60.39 seconds
Started Mar 28 01:49:04 PM PDT 24
Finished Mar 28 01:50:04 PM PDT 24
Peak memory 200436 kb
Host smart-95a07c92-8f68-457d-8c1b-c49168bd24e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191731323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.191731323
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.224751180
Short name T1013
Test name
Test status
Simulation time 16843346953 ps
CPU time 17.99 seconds
Started Mar 28 01:49:06 PM PDT 24
Finished Mar 28 01:49:24 PM PDT 24
Peak memory 200236 kb
Host smart-d4023e7b-2d11-4439-bd8b-14fe206eb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224751180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.224751180
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2528426143
Short name T102
Test name
Test status
Simulation time 38275944134 ps
CPU time 25.64 seconds
Started Mar 28 01:49:07 PM PDT 24
Finished Mar 28 01:49:33 PM PDT 24
Peak memory 200496 kb
Host smart-9e794b01-6e89-4f70-bda5-59b5390bc023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528426143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2528426143
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4133569138
Short name T308
Test name
Test status
Simulation time 38627100401 ps
CPU time 80.4 seconds
Started Mar 28 01:49:07 PM PDT 24
Finished Mar 28 01:50:28 PM PDT 24
Peak memory 200528 kb
Host smart-53a093db-9bef-4099-b079-cfb7151e2abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133569138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4133569138
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1356261200
Short name T186
Test name
Test status
Simulation time 106625932237 ps
CPU time 162.56 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:51:44 PM PDT 24
Peak memory 200432 kb
Host smart-f7957138-f973-4401-84c7-da4789ee9aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356261200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1356261200
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1146628756
Short name T950
Test name
Test status
Simulation time 169832044158 ps
CPU time 300.94 seconds
Started Mar 28 01:49:07 PM PDT 24
Finished Mar 28 01:54:08 PM PDT 24
Peak memory 200492 kb
Host smart-e4538b93-f3be-459f-9774-4fb68527ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146628756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1146628756
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3478638650
Short name T991
Test name
Test status
Simulation time 181325639308 ps
CPU time 172.8 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:51:55 PM PDT 24
Peak memory 200472 kb
Host smart-62bf7f30-fdfb-4e16-ac5d-81ed391237a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478638650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3478638650
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2702081724
Short name T354
Test name
Test status
Simulation time 120374625483 ps
CPU time 45.96 seconds
Started Mar 28 01:49:22 PM PDT 24
Finished Mar 28 01:50:08 PM PDT 24
Peak memory 200372 kb
Host smart-371c0aa5-d3ea-42c7-a8ab-8edfba3e1bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702081724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2702081724
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.463242869
Short name T771
Test name
Test status
Simulation time 43990728 ps
CPU time 0.54 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:45:43 PM PDT 24
Peak memory 195856 kb
Host smart-1db660cb-fcca-424a-af22-b8e5510915af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463242869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.463242869
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.365673036
Short name T951
Test name
Test status
Simulation time 112460274506 ps
CPU time 201.8 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:49:09 PM PDT 24
Peak memory 200488 kb
Host smart-36f0468d-75ec-455b-8357-2a734e221e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365673036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.365673036
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2433617816
Short name T920
Test name
Test status
Simulation time 69855429811 ps
CPU time 40.86 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:46:28 PM PDT 24
Peak memory 200328 kb
Host smart-dcd98683-6bf8-43c2-b38a-0075f908c028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433617816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2433617816
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3534590743
Short name T1039
Test name
Test status
Simulation time 42070967582 ps
CPU time 38.27 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:46:25 PM PDT 24
Peak memory 200416 kb
Host smart-6bee7951-1367-4185-8734-a5056716b949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534590743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3534590743
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.632238935
Short name T631
Test name
Test status
Simulation time 61712068207 ps
CPU time 34.59 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:46:22 PM PDT 24
Peak memory 200484 kb
Host smart-4a8fdeb4-d33f-4f9b-83a9-6b25dc901e82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632238935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.632238935
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2138432220
Short name T825
Test name
Test status
Simulation time 79893507763 ps
CPU time 202.71 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:49:05 PM PDT 24
Peak memory 200500 kb
Host smart-f3eb0d51-a3a5-4abc-a0fb-16dc608482da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138432220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2138432220
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1381506364
Short name T1115
Test name
Test status
Simulation time 3799058955 ps
CPU time 7.73 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:45:50 PM PDT 24
Peak memory 199956 kb
Host smart-55be97b3-d7f5-46c6-afd5-f0f58f8785f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381506364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1381506364
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2170260335
Short name T1008
Test name
Test status
Simulation time 54206309540 ps
CPU time 34.1 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:46:15 PM PDT 24
Peak memory 200080 kb
Host smart-51598caa-ea4a-43ef-9557-eaa70de06049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170260335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2170260335
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3377039147
Short name T1165
Test name
Test status
Simulation time 7632020074 ps
CPU time 394.3 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:52:18 PM PDT 24
Peak memory 200440 kb
Host smart-264987b7-754c-4a4c-bc1d-d8ae4c1d7097
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377039147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3377039147
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2452001102
Short name T334
Test name
Test status
Simulation time 4259090211 ps
CPU time 17.59 seconds
Started Mar 28 01:45:31 PM PDT 24
Finished Mar 28 01:45:49 PM PDT 24
Peak memory 198476 kb
Host smart-b0c1619b-baa7-4ec1-b6d2-acaca4ff7d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452001102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2452001102
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2422329201
Short name T40
Test name
Test status
Simulation time 83354208944 ps
CPU time 124.37 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:47:47 PM PDT 24
Peak memory 200424 kb
Host smart-c9412e63-060c-4378-b6b0-4f1921f565d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422329201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2422329201
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1875939919
Short name T894
Test name
Test status
Simulation time 40070015817 ps
CPU time 17.03 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:45:59 PM PDT 24
Peak memory 196524 kb
Host smart-3ffa0121-5301-4a06-a769-54cefd45f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875939919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1875939919
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.322789797
Short name T907
Test name
Test status
Simulation time 5543451109 ps
CPU time 42.69 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:46:29 PM PDT 24
Peak memory 200344 kb
Host smart-b6940f2a-8074-4fff-a549-b892836cc4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322789797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.322789797
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2676551842
Short name T14
Test name
Test status
Simulation time 105127673936 ps
CPU time 71.97 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:46:55 PM PDT 24
Peak memory 200524 kb
Host smart-78954740-699e-4fe5-a4cd-6e999f882e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676551842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2676551842
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3752757659
Short name T329
Test name
Test status
Simulation time 105579199016 ps
CPU time 615.82 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:55:58 PM PDT 24
Peak memory 217004 kb
Host smart-d8276b39-e02d-448f-a3d2-08a43a1d8a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752757659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3752757659
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2605783768
Short name T484
Test name
Test status
Simulation time 904501581 ps
CPU time 1.56 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:45:42 PM PDT 24
Peak memory 200348 kb
Host smart-56d8685e-d437-44de-b416-478a4e58d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605783768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2605783768
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.795256164
Short name T113
Test name
Test status
Simulation time 116453295142 ps
CPU time 161.91 seconds
Started Mar 28 01:49:01 PM PDT 24
Finished Mar 28 01:51:43 PM PDT 24
Peak memory 200404 kb
Host smart-c90e9f5b-bde1-4540-9737-0de1ee02a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795256164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.795256164
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.511490102
Short name T128
Test name
Test status
Simulation time 155311928551 ps
CPU time 247.69 seconds
Started Mar 28 01:49:08 PM PDT 24
Finished Mar 28 01:53:16 PM PDT 24
Peak memory 200440 kb
Host smart-9c413706-a051-4528-892e-2d1725e52729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511490102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.511490102
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.617846226
Short name T198
Test name
Test status
Simulation time 377662341584 ps
CPU time 90.2 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:50:33 PM PDT 24
Peak memory 200504 kb
Host smart-e52a34f4-c906-4032-aa1f-9a20acd57fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617846226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.617846226
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2121176
Short name T6
Test name
Test status
Simulation time 218216439025 ps
CPU time 111.34 seconds
Started Mar 28 01:49:11 PM PDT 24
Finished Mar 28 01:51:03 PM PDT 24
Peak memory 200484 kb
Host smart-4cd37ec9-b8c6-430c-9438-be2696a099a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2121176
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3980112706
Short name T588
Test name
Test status
Simulation time 214366225281 ps
CPU time 27.6 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:49:30 PM PDT 24
Peak memory 200464 kb
Host smart-8267baaf-5c6a-47e4-9f8f-6a90f4c98013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980112706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3980112706
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3765586443
Short name T37
Test name
Test status
Simulation time 22396851464 ps
CPU time 9.92 seconds
Started Mar 28 01:49:04 PM PDT 24
Finished Mar 28 01:49:15 PM PDT 24
Peak memory 200376 kb
Host smart-1c983f3c-3994-403f-979c-c8a81c99002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765586443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3765586443
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3228070974
Short name T178
Test name
Test status
Simulation time 32989728206 ps
CPU time 13.96 seconds
Started Mar 28 01:49:03 PM PDT 24
Finished Mar 28 01:49:17 PM PDT 24
Peak memory 200436 kb
Host smart-cd80a280-dece-4c59-a681-0003f0e16a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228070974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3228070974
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3553327462
Short name T119
Test name
Test status
Simulation time 133642899757 ps
CPU time 197.7 seconds
Started Mar 28 01:49:06 PM PDT 24
Finished Mar 28 01:52:24 PM PDT 24
Peak memory 200364 kb
Host smart-1b10e5dd-3147-473f-8975-cf8c339cb4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553327462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3553327462
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.316529071
Short name T869
Test name
Test status
Simulation time 127907385782 ps
CPU time 32.18 seconds
Started Mar 28 01:49:06 PM PDT 24
Finished Mar 28 01:49:39 PM PDT 24
Peak memory 200316 kb
Host smart-96759b64-3686-410f-916d-a7eba138fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316529071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.316529071
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2616617658
Short name T1161
Test name
Test status
Simulation time 104203674317 ps
CPU time 158.42 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:51:40 PM PDT 24
Peak memory 200532 kb
Host smart-ee7e3d24-4941-4f02-b983-ec3ed1d70279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616617658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2616617658
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.643721614
Short name T1005
Test name
Test status
Simulation time 12619679 ps
CPU time 0.56 seconds
Started Mar 28 01:46:23 PM PDT 24
Finished Mar 28 01:46:24 PM PDT 24
Peak memory 195316 kb
Host smart-55c02e8f-178d-4609-9348-e170788da9ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643721614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.643721614
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1659594475
Short name T254
Test name
Test status
Simulation time 46345081077 ps
CPU time 73.67 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:47:01 PM PDT 24
Peak memory 200432 kb
Host smart-28ac9a65-ba06-42f4-bf59-397199e2aa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659594475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1659594475
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2379096597
Short name T492
Test name
Test status
Simulation time 17337603315 ps
CPU time 28.01 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:46:11 PM PDT 24
Peak memory 200456 kb
Host smart-8fb044f3-7875-48f1-b5c4-69630c4813ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379096597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2379096597
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2071054595
Short name T176
Test name
Test status
Simulation time 55204154175 ps
CPU time 81.78 seconds
Started Mar 28 01:45:49 PM PDT 24
Finished Mar 28 01:47:11 PM PDT 24
Peak memory 200452 kb
Host smart-93c4b208-100b-4aec-accb-a164eb3b589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071054595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2071054595
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1905410462
Short name T922
Test name
Test status
Simulation time 23514700807 ps
CPU time 4.05 seconds
Started Mar 28 01:45:43 PM PDT 24
Finished Mar 28 01:45:48 PM PDT 24
Peak memory 200344 kb
Host smart-867062fc-1d5a-4e5b-93e9-35231594da20
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905410462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1905410462
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2650246467
Short name T272
Test name
Test status
Simulation time 237761917246 ps
CPU time 309.82 seconds
Started Mar 28 01:45:45 PM PDT 24
Finished Mar 28 01:50:55 PM PDT 24
Peak memory 200520 kb
Host smart-cdfdc791-ca5c-45e5-8e76-a1f5a7dfe02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650246467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2650246467
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.16033888
Short name T603
Test name
Test status
Simulation time 9493185644 ps
CPU time 11.34 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:45:59 PM PDT 24
Peak memory 200532 kb
Host smart-441b8159-becf-466c-8ceb-6d1beb5144be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16033888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.16033888
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1885998932
Short name T1101
Test name
Test status
Simulation time 13869835370 ps
CPU time 23.37 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:46:10 PM PDT 24
Peak memory 200752 kb
Host smart-f27484c2-79b1-41dc-80d3-feddceb3c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885998932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1885998932
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.576347417
Short name T610
Test name
Test status
Simulation time 15707917791 ps
CPU time 445.77 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:53:13 PM PDT 24
Peak memory 200372 kb
Host smart-a80b8d0a-e758-4216-bd80-9fdb2b4f1d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576347417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.576347417
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3586879501
Short name T477
Test name
Test status
Simulation time 1514898809 ps
CPU time 2.66 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:45:50 PM PDT 24
Peak memory 199612 kb
Host smart-68818959-76c9-40ea-97bf-afdaf8bd88c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586879501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3586879501
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1444898443
Short name T1055
Test name
Test status
Simulation time 54741527172 ps
CPU time 44.29 seconds
Started Mar 28 01:45:42 PM PDT 24
Finished Mar 28 01:46:26 PM PDT 24
Peak memory 200264 kb
Host smart-5655d890-5dfe-4bf3-8028-fe54a32fb363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444898443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1444898443
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3147641241
Short name T1102
Test name
Test status
Simulation time 4472386083 ps
CPU time 6.5 seconds
Started Mar 28 01:45:48 PM PDT 24
Finished Mar 28 01:45:54 PM PDT 24
Peak memory 196552 kb
Host smart-a7063954-88c4-49e5-aa59-d79fc46f19a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147641241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3147641241
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.337122040
Short name T738
Test name
Test status
Simulation time 875886025 ps
CPU time 1.52 seconds
Started Mar 28 01:45:51 PM PDT 24
Finished Mar 28 01:45:53 PM PDT 24
Peak memory 199220 kb
Host smart-2a266bce-3ab6-4b0a-b816-c7b5b625e777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337122040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.337122040
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.61115254
Short name T322
Test name
Test status
Simulation time 177592883449 ps
CPU time 688.71 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:57:51 PM PDT 24
Peak memory 200408 kb
Host smart-cb9c9e13-8228-4f76-8150-ff692f6f867e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61115254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.61115254
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3606640287
Short name T404
Test name
Test status
Simulation time 1697360340 ps
CPU time 2.02 seconds
Started Mar 28 01:45:47 PM PDT 24
Finished Mar 28 01:45:50 PM PDT 24
Peak memory 200388 kb
Host smart-4b57a476-b86e-4fca-9004-6b11aa43bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606640287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3606640287
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2966844144
Short name T421
Test name
Test status
Simulation time 68541635728 ps
CPU time 107 seconds
Started Mar 28 01:45:46 PM PDT 24
Finished Mar 28 01:47:33 PM PDT 24
Peak memory 200420 kb
Host smart-040e5d4e-88cc-42b9-a1a5-18b376c74df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966844144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2966844144
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.694613480
Short name T1098
Test name
Test status
Simulation time 53741155238 ps
CPU time 20.14 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:49:23 PM PDT 24
Peak memory 200560 kb
Host smart-a0bde1a8-4680-4314-b7c7-71114f6ccca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694613480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.694613480
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1329330658
Short name T572
Test name
Test status
Simulation time 188711735021 ps
CPU time 37.77 seconds
Started Mar 28 01:49:08 PM PDT 24
Finished Mar 28 01:49:46 PM PDT 24
Peak memory 200524 kb
Host smart-bbad6ef1-4421-4526-8a31-1fd4d72b73c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329330658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1329330658
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2075194296
Short name T216
Test name
Test status
Simulation time 14619812146 ps
CPU time 28.41 seconds
Started Mar 28 01:49:08 PM PDT 24
Finished Mar 28 01:49:37 PM PDT 24
Peak memory 200516 kb
Host smart-16fde7e0-3e7c-4d95-841c-9880c20fad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075194296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2075194296
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2722972642
Short name T680
Test name
Test status
Simulation time 39218009435 ps
CPU time 22.31 seconds
Started Mar 28 01:49:10 PM PDT 24
Finished Mar 28 01:49:32 PM PDT 24
Peak memory 200488 kb
Host smart-d6b1cb33-6def-4514-9f0a-30dd9af5e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722972642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2722972642
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2008614727
Short name T818
Test name
Test status
Simulation time 77824405004 ps
CPU time 21.7 seconds
Started Mar 28 01:49:08 PM PDT 24
Finished Mar 28 01:49:30 PM PDT 24
Peak memory 200464 kb
Host smart-3d1a444b-91b3-4c44-b5bf-fde6b71ef414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008614727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2008614727
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2798846662
Short name T648
Test name
Test status
Simulation time 35291848621 ps
CPU time 38.07 seconds
Started Mar 28 01:49:06 PM PDT 24
Finished Mar 28 01:49:45 PM PDT 24
Peak memory 200464 kb
Host smart-0e6f356f-8989-4e14-98fb-58511ee2ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798846662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2798846662
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3912578160
Short name T220
Test name
Test status
Simulation time 33653298916 ps
CPU time 55.41 seconds
Started Mar 28 01:49:13 PM PDT 24
Finished Mar 28 01:50:09 PM PDT 24
Peak memory 200504 kb
Host smart-46ec80f0-0b86-46d0-a2fa-db1ac0751b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912578160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3912578160
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3126167624
Short name T1128
Test name
Test status
Simulation time 88630694303 ps
CPU time 129.35 seconds
Started Mar 28 01:49:22 PM PDT 24
Finished Mar 28 01:51:31 PM PDT 24
Peak memory 200408 kb
Host smart-e4090787-2565-4f2c-a5e2-dc9b5b8e50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126167624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3126167624
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1181958405
Short name T1046
Test name
Test status
Simulation time 11515888781 ps
CPU time 22.45 seconds
Started Mar 28 01:49:20 PM PDT 24
Finished Mar 28 01:49:43 PM PDT 24
Peak memory 200372 kb
Host smart-aca06caa-865b-49e6-91cc-132c749ad6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181958405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1181958405
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3605700556
Short name T1106
Test name
Test status
Simulation time 14652720 ps
CPU time 0.57 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:46:21 PM PDT 24
Peak memory 195888 kb
Host smart-6ca78c66-18dc-4e7b-8eba-bb3d39852557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605700556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3605700556
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3175744352
Short name T470
Test name
Test status
Simulation time 106913182109 ps
CPU time 180.4 seconds
Started Mar 28 01:46:18 PM PDT 24
Finished Mar 28 01:49:19 PM PDT 24
Peak memory 200428 kb
Host smart-d0a8c2b7-f4a9-42bd-a6ab-e5b11e11af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175744352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3175744352
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2491158301
Short name T667
Test name
Test status
Simulation time 13229478078 ps
CPU time 23.6 seconds
Started Mar 28 01:46:17 PM PDT 24
Finished Mar 28 01:46:41 PM PDT 24
Peak memory 200448 kb
Host smart-0bbc2421-8e67-4ca0-afc7-d9738263c5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491158301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2491158301
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3413216008
Short name T693
Test name
Test status
Simulation time 38631533273 ps
CPU time 7.91 seconds
Started Mar 28 01:46:17 PM PDT 24
Finished Mar 28 01:46:25 PM PDT 24
Peak memory 200492 kb
Host smart-99d5812e-8b0b-4e2c-8a9d-fb39dfe41ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413216008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3413216008
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.9646524
Short name T926
Test name
Test status
Simulation time 25074018774 ps
CPU time 4.75 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:46:23 PM PDT 24
Peak memory 200228 kb
Host smart-e14683ca-0025-45cf-bf4c-4035f8101222
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9646524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.9646524
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2519423312
Short name T800
Test name
Test status
Simulation time 81448490220 ps
CPU time 226.41 seconds
Started Mar 28 01:46:18 PM PDT 24
Finished Mar 28 01:50:05 PM PDT 24
Peak memory 200408 kb
Host smart-2f06cdf0-e075-435b-80f7-c8f68c7c88d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519423312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2519423312
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1838523358
Short name T445
Test name
Test status
Simulation time 8387015679 ps
CPU time 8.08 seconds
Started Mar 28 01:46:18 PM PDT 24
Finished Mar 28 01:46:27 PM PDT 24
Peak memory 200424 kb
Host smart-1f600676-4732-4a2a-aabd-fe0ae65cf4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838523358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1838523358
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1341991388
Short name T662
Test name
Test status
Simulation time 301640754175 ps
CPU time 57.63 seconds
Started Mar 28 01:46:23 PM PDT 24
Finished Mar 28 01:47:21 PM PDT 24
Peak memory 200788 kb
Host smart-822c4317-323a-45a3-aed4-1492b00910e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341991388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1341991388
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1648526112
Short name T729
Test name
Test status
Simulation time 17376805584 ps
CPU time 207.67 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:49:47 PM PDT 24
Peak memory 200464 kb
Host smart-0712d8bd-a0d3-401b-b75b-42c505f8f2c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648526112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1648526112
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3962988452
Short name T718
Test name
Test status
Simulation time 7042502288 ps
CPU time 35.72 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:46:55 PM PDT 24
Peak memory 199324 kb
Host smart-587fe8dd-bcc8-436c-b723-7c2dab041ea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962988452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3962988452
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1079224154
Short name T858
Test name
Test status
Simulation time 18915880145 ps
CPU time 28.54 seconds
Started Mar 28 01:46:17 PM PDT 24
Finished Mar 28 01:46:46 PM PDT 24
Peak memory 200500 kb
Host smart-8a6f34a3-3a5e-4821-8c20-e5b2422cc35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079224154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1079224154
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1712686988
Short name T574
Test name
Test status
Simulation time 27152466171 ps
CPU time 42.54 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:47:02 PM PDT 24
Peak memory 196512 kb
Host smart-7789a4ce-19d5-4f64-885b-dc95a28e6ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712686988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1712686988
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3408320322
Short name T399
Test name
Test status
Simulation time 291197188 ps
CPU time 1.28 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:46:21 PM PDT 24
Peak memory 199148 kb
Host smart-c1bc5456-a4e0-4197-bc35-476ab8f72ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408320322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3408320322
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3341321938
Short name T33
Test name
Test status
Simulation time 133107354851 ps
CPU time 558.22 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:55:40 PM PDT 24
Peak memory 200648 kb
Host smart-bfa518a1-be43-4667-9cd6-d36b67d00fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341321938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3341321938
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.737924745
Short name T418
Test name
Test status
Simulation time 154160486586 ps
CPU time 189.74 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:49:30 PM PDT 24
Peak memory 216928 kb
Host smart-1d9aca82-e5f7-4f2a-94dd-24c2aa9b1c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737924745 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.737924745
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3003402564
Short name T679
Test name
Test status
Simulation time 7326535208 ps
CPU time 22.71 seconds
Started Mar 28 01:46:17 PM PDT 24
Finished Mar 28 01:46:41 PM PDT 24
Peak memory 200212 kb
Host smart-d6d493ec-0b57-4696-aa26-3225c8c7a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003402564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3003402564
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.468098510
Short name T878
Test name
Test status
Simulation time 97867067681 ps
CPU time 175.92 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:49:16 PM PDT 24
Peak memory 200396 kb
Host smart-3abea6de-1b52-4da1-adb1-6536c8e4117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468098510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.468098510
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3305075787
Short name T217
Test name
Test status
Simulation time 55894135411 ps
CPU time 39.72 seconds
Started Mar 28 01:49:12 PM PDT 24
Finished Mar 28 01:49:52 PM PDT 24
Peak memory 200464 kb
Host smart-3f5d9d9b-7ac1-47f6-a003-81dc27780aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305075787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3305075787
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1624989737
Short name T1099
Test name
Test status
Simulation time 67178173809 ps
CPU time 102.28 seconds
Started Mar 28 01:49:10 PM PDT 24
Finished Mar 28 01:50:52 PM PDT 24
Peak memory 200488 kb
Host smart-8ebad125-5bce-4b10-9388-9dd3e2b9a3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624989737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1624989737
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.757461867
Short name T696
Test name
Test status
Simulation time 80244454505 ps
CPU time 132.77 seconds
Started Mar 28 01:49:22 PM PDT 24
Finished Mar 28 01:51:35 PM PDT 24
Peak memory 200348 kb
Host smart-b2db317c-8962-4f9a-8fce-a98c181bf8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757461867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.757461867
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1706584717
Short name T1002
Test name
Test status
Simulation time 21410343975 ps
CPU time 36.82 seconds
Started Mar 28 01:49:09 PM PDT 24
Finished Mar 28 01:49:46 PM PDT 24
Peak memory 200424 kb
Host smart-fa9571bd-39d7-40c8-bfb8-77634fc9eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706584717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1706584717
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.227379729
Short name T500
Test name
Test status
Simulation time 247206356633 ps
CPU time 54.21 seconds
Started Mar 28 01:49:22 PM PDT 24
Finished Mar 28 01:50:17 PM PDT 24
Peak memory 200232 kb
Host smart-320e6fc9-efbf-4760-b30b-cf92439eb2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227379729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.227379729
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1749527519
Short name T145
Test name
Test status
Simulation time 162296460219 ps
CPU time 122.18 seconds
Started Mar 28 01:49:09 PM PDT 24
Finished Mar 28 01:51:12 PM PDT 24
Peak memory 200484 kb
Host smart-f8887cb2-69d2-4f56-bc96-b7e4f1557310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749527519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1749527519
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.357871436
Short name T644
Test name
Test status
Simulation time 7926523059 ps
CPU time 13.78 seconds
Started Mar 28 01:49:02 PM PDT 24
Finished Mar 28 01:49:16 PM PDT 24
Peak memory 200584 kb
Host smart-6384d338-3684-44e0-aa1f-663f4fc80772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357871436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.357871436
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2463804238
Short name T150
Test name
Test status
Simulation time 88409159057 ps
CPU time 43.03 seconds
Started Mar 28 01:49:22 PM PDT 24
Finished Mar 28 01:50:05 PM PDT 24
Peak memory 200136 kb
Host smart-0c7e9afc-de66-47d6-b49e-fed9ff48919f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463804238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2463804238
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1972773251
Short name T705
Test name
Test status
Simulation time 25130664 ps
CPU time 0.56 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:46:21 PM PDT 24
Peak memory 195888 kb
Host smart-d9cc38f7-5a16-4e21-a922-6b31541d2b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972773251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1972773251
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2172474195
Short name T876
Test name
Test status
Simulation time 61231612427 ps
CPU time 51.71 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:47:12 PM PDT 24
Peak memory 200488 kb
Host smart-600be304-513a-4634-a816-39aeecfbf05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172474195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2172474195
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.889578931
Short name T1079
Test name
Test status
Simulation time 47983681928 ps
CPU time 77.83 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:47:40 PM PDT 24
Peak memory 200272 kb
Host smart-4a012b4e-6098-446d-aa88-ce5304ae3c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889578931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.889578931
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.1317529756
Short name T863
Test name
Test status
Simulation time 22462558489 ps
CPU time 37.1 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:46:56 PM PDT 24
Peak memory 200448 kb
Host smart-908ff24a-6d12-4a27-b2a3-fee7128c2a4e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317529756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1317529756
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.543828024
Short name T43
Test name
Test status
Simulation time 299558588170 ps
CPU time 113.57 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:48:14 PM PDT 24
Peak memory 200428 kb
Host smart-5790334e-25d9-43a5-9a93-87b73d8befb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543828024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.543828024
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3368001066
Short name T1124
Test name
Test status
Simulation time 3645056891 ps
CPU time 1.4 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:23 PM PDT 24
Peak memory 199028 kb
Host smart-488e8979-dd05-4b07-8361-ee6cb054d042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368001066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3368001066
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1254305274
Short name T740
Test name
Test status
Simulation time 62502098956 ps
CPU time 132.75 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:48:34 PM PDT 24
Peak memory 200444 kb
Host smart-b9426af7-43d3-4d45-8da1-f5342242862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254305274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1254305274
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3446361390
Short name T617
Test name
Test status
Simulation time 19545261939 ps
CPU time 164.47 seconds
Started Mar 28 01:46:18 PM PDT 24
Finished Mar 28 01:49:03 PM PDT 24
Peak memory 200472 kb
Host smart-72848479-beb4-4c26-919d-d6e58933a66b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3446361390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3446361390
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1692971994
Short name T903
Test name
Test status
Simulation time 6153739109 ps
CPU time 57.19 seconds
Started Mar 28 01:46:18 PM PDT 24
Finished Mar 28 01:47:16 PM PDT 24
Peak memory 199692 kb
Host smart-8b5e4d96-8c3a-4b6f-9af6-d7621851e22d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692971994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1692971994
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3252554395
Short name T760
Test name
Test status
Simulation time 40405167832 ps
CPU time 17.41 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:46:37 PM PDT 24
Peak memory 200464 kb
Host smart-1f2438ca-d712-418e-951b-e5d45ec52748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252554395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3252554395
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2961712705
Short name T597
Test name
Test status
Simulation time 4248046829 ps
CPU time 3.96 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:46:24 PM PDT 24
Peak memory 196492 kb
Host smart-cfee9821-b6fb-4d78-99e3-c9aae5528f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961712705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2961712705
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.966072978
Short name T291
Test name
Test status
Simulation time 5546089731 ps
CPU time 6.53 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:29 PM PDT 24
Peak memory 200444 kb
Host smart-b064763a-44c3-4e39-a6d6-4a8a5dac3f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966072978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.966072978
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3302268267
Short name T890
Test name
Test status
Simulation time 615929596054 ps
CPU time 1490.64 seconds
Started Mar 28 01:46:23 PM PDT 24
Finished Mar 28 02:11:14 PM PDT 24
Peak memory 200536 kb
Host smart-4d63720f-5a8f-4ee5-a477-0958934939bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302268267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3302268267
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.665063020
Short name T424
Test name
Test status
Simulation time 42272776628 ps
CPU time 520 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:55:02 PM PDT 24
Peak memory 215892 kb
Host smart-40b65184-081a-4ff1-b590-e7b28d3b07bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665063020 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.665063020
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.878248443
Short name T1052
Test name
Test status
Simulation time 9691332675 ps
CPU time 4.96 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:46:25 PM PDT 24
Peak memory 199940 kb
Host smart-0ec999b3-909c-4584-9ef1-cc6c23a9e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878248443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.878248443
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.832033141
Short name T126
Test name
Test status
Simulation time 29649483931 ps
CPU time 61.51 seconds
Started Mar 28 01:49:14 PM PDT 24
Finished Mar 28 01:50:16 PM PDT 24
Peak memory 200492 kb
Host smart-10136361-69b7-4c28-ba43-29ab903bbd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832033141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.832033141
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.397892518
Short name T191
Test name
Test status
Simulation time 25613854128 ps
CPU time 19.83 seconds
Started Mar 28 01:49:18 PM PDT 24
Finished Mar 28 01:49:38 PM PDT 24
Peak memory 200316 kb
Host smart-4520a976-76da-4cdb-8576-320f77cc8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397892518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.397892518
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3731573566
Short name T887
Test name
Test status
Simulation time 107499237783 ps
CPU time 25.25 seconds
Started Mar 28 01:49:16 PM PDT 24
Finished Mar 28 01:49:41 PM PDT 24
Peak memory 200524 kb
Host smart-cba0bf1e-d326-4aa6-809a-bae4e8252930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731573566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3731573566
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2468181166
Short name T756
Test name
Test status
Simulation time 45329072261 ps
CPU time 8.41 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:49:24 PM PDT 24
Peak memory 200488 kb
Host smart-ebca2acb-78ed-427f-bdcd-437301730366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468181166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2468181166
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2305488180
Short name T493
Test name
Test status
Simulation time 105230516715 ps
CPU time 53.24 seconds
Started Mar 28 01:49:14 PM PDT 24
Finished Mar 28 01:50:08 PM PDT 24
Peak memory 200528 kb
Host smart-0345ff35-9ca5-455c-afba-66c92123b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305488180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2305488180
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3512792153
Short name T158
Test name
Test status
Simulation time 24503525367 ps
CPU time 36.24 seconds
Started Mar 28 01:49:16 PM PDT 24
Finished Mar 28 01:49:53 PM PDT 24
Peak memory 200472 kb
Host smart-7b1b8f82-825c-4c64-ad66-a270d4c76710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512792153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3512792153
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2900060687
Short name T1025
Test name
Test status
Simulation time 84926716688 ps
CPU time 27.17 seconds
Started Mar 28 01:49:14 PM PDT 24
Finished Mar 28 01:49:41 PM PDT 24
Peak memory 200472 kb
Host smart-b2aae468-cd1f-45f6-9102-352d4eb59816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900060687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2900060687
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3346421616
Short name T593
Test name
Test status
Simulation time 12215168547 ps
CPU time 21.86 seconds
Started Mar 28 01:49:14 PM PDT 24
Finished Mar 28 01:49:36 PM PDT 24
Peak memory 200472 kb
Host smart-ddfbdedc-3f8a-47ce-a949-281624148b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346421616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3346421616
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3635955525
Short name T1125
Test name
Test status
Simulation time 31125905373 ps
CPU time 54.91 seconds
Started Mar 28 01:49:17 PM PDT 24
Finished Mar 28 01:50:12 PM PDT 24
Peak memory 200400 kb
Host smart-baa05dcb-7871-4f76-b8cf-60028c7e804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635955525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3635955525
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3429044717
Short name T1026
Test name
Test status
Simulation time 74361865719 ps
CPU time 178.02 seconds
Started Mar 28 01:49:16 PM PDT 24
Finished Mar 28 01:52:14 PM PDT 24
Peak memory 200508 kb
Host smart-fb59cec0-0ef6-498a-89a1-63682d5bf4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429044717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3429044717
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1566430311
Short name T517
Test name
Test status
Simulation time 20972596 ps
CPU time 0.59 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 01:44:57 PM PDT 24
Peak memory 195876 kb
Host smart-b59045b9-4fe8-4f04-a5ce-7b5b73cb25f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566430311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1566430311
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2710173929
Short name T805
Test name
Test status
Simulation time 41356166286 ps
CPU time 17.51 seconds
Started Mar 28 01:44:58 PM PDT 24
Finished Mar 28 01:45:15 PM PDT 24
Peak memory 200448 kb
Host smart-6f1481b0-4c71-44b4-8311-f0236f114fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710173929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2710173929
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1267170197
Short name T156
Test name
Test status
Simulation time 190925437588 ps
CPU time 21.41 seconds
Started Mar 28 01:45:40 PM PDT 24
Finished Mar 28 01:46:02 PM PDT 24
Peak memory 200428 kb
Host smart-9a235478-4cb5-4732-951e-cc8997d60338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267170197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1267170197
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1350354731
Short name T1081
Test name
Test status
Simulation time 42987779602 ps
CPU time 78.69 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:46:19 PM PDT 24
Peak memory 200468 kb
Host smart-6d301cfe-cb19-4b2a-ba71-cfa5d36e6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350354731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1350354731
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2179255401
Short name T1038
Test name
Test status
Simulation time 303172148827 ps
CPU time 144.42 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:47:27 PM PDT 24
Peak memory 200324 kb
Host smart-2a9c3403-6c97-4274-b496-df415f386ffc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179255401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2179255401
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1302731116
Short name T412
Test name
Test status
Simulation time 59344222681 ps
CPU time 61.21 seconds
Started Mar 28 01:45:04 PM PDT 24
Finished Mar 28 01:46:05 PM PDT 24
Peak memory 200416 kb
Host smart-e3f206e5-83ad-43eb-9b70-2f117c45a350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302731116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1302731116
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3908339046
Short name T941
Test name
Test status
Simulation time 5853600910 ps
CPU time 4.22 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:45:07 PM PDT 24
Peak memory 199352 kb
Host smart-3c46c9e5-4b0b-407a-a04c-ed5f1d134e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908339046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3908339046
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3107554181
Short name T313
Test name
Test status
Simulation time 4818657904 ps
CPU time 8.74 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 01:45:04 PM PDT 24
Peak memory 200568 kb
Host smart-a64be15e-33eb-4c9e-ac55-9272e07967a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107554181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3107554181
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2858154723
Short name T292
Test name
Test status
Simulation time 17451562601 ps
CPU time 233.96 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:48:56 PM PDT 24
Peak memory 200508 kb
Host smart-abe5ab30-301e-4f5d-95c9-7f37ebca7ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858154723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2858154723
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.600337941
Short name T1090
Test name
Test status
Simulation time 6091760225 ps
CPU time 13.85 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:45:15 PM PDT 24
Peak memory 199516 kb
Host smart-314094cd-7339-4468-847e-c3b20c74b07c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600337941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.600337941
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1427941038
Short name T164
Test name
Test status
Simulation time 75085749438 ps
CPU time 27.31 seconds
Started Mar 28 01:44:58 PM PDT 24
Finished Mar 28 01:45:26 PM PDT 24
Peak memory 200176 kb
Host smart-83ba405e-8c93-48e4-af28-779bc517d21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427941038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1427941038
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.542356058
Short name T357
Test name
Test status
Simulation time 4255577140 ps
CPU time 3.03 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:45:05 PM PDT 24
Peak memory 196492 kb
Host smart-614ae270-90f7-4560-b56c-7022cfc04fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542356058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.542356058
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.886464454
Short name T28
Test name
Test status
Simulation time 45763870 ps
CPU time 0.78 seconds
Started Mar 28 01:44:59 PM PDT 24
Finished Mar 28 01:45:00 PM PDT 24
Peak memory 218924 kb
Host smart-e850b3ef-6c8d-4d44-8526-7136cd80f428
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886464454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.886464454
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2409588739
Short name T93
Test name
Test status
Simulation time 497094617 ps
CPU time 1.6 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:45:02 PM PDT 24
Peak memory 198816 kb
Host smart-0169ef99-80ec-4bfc-923d-868d1cf9c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409588739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2409588739
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3316723614
Short name T139
Test name
Test status
Simulation time 994172033866 ps
CPU time 611.1 seconds
Started Mar 28 01:45:07 PM PDT 24
Finished Mar 28 01:55:18 PM PDT 24
Peak memory 216944 kb
Host smart-dd65cb6d-791d-4ba3-b935-baae192b3a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316723614 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3316723614
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.730418594
Short name T727
Test name
Test status
Simulation time 1284233744 ps
CPU time 2.37 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:45:04 PM PDT 24
Peak memory 200320 kb
Host smart-9c0af816-bc08-4c04-be66-04a1e11fd6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730418594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.730418594
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3367356907
Short name T808
Test name
Test status
Simulation time 88655299921 ps
CPU time 143.19 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:47:24 PM PDT 24
Peak memory 200424 kb
Host smart-c2daf6da-0be1-4d39-b7b7-a7faca1282c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367356907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3367356907
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1147606817
Short name T1105
Test name
Test status
Simulation time 13390491 ps
CPU time 0.56 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:22 PM PDT 24
Peak memory 195868 kb
Host smart-fe342ad3-10cb-4468-ab1d-50b44acb8fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147606817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1147606817
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1726666658
Short name T721
Test name
Test status
Simulation time 279286388093 ps
CPU time 623.66 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:56:43 PM PDT 24
Peak memory 200388 kb
Host smart-4d0822b6-dd45-47e3-906b-327ede7e855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726666658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1726666658
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2599007848
Short name T677
Test name
Test status
Simulation time 23521980846 ps
CPU time 41.14 seconds
Started Mar 28 01:46:17 PM PDT 24
Finished Mar 28 01:46:59 PM PDT 24
Peak memory 200496 kb
Host smart-9cf091c8-9203-4e20-a794-87799d42d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599007848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2599007848
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.80090223
Short name T234
Test name
Test status
Simulation time 69034328406 ps
CPU time 52.3 seconds
Started Mar 28 01:46:24 PM PDT 24
Finished Mar 28 01:47:16 PM PDT 24
Peak memory 200456 kb
Host smart-8930296f-73cf-4bd4-ab6b-919154a4a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80090223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.80090223
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1821846678
Short name T247
Test name
Test status
Simulation time 21159489839 ps
CPU time 19.11 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:46:39 PM PDT 24
Peak memory 200444 kb
Host smart-3239d79a-2cc4-44d0-accd-1dc99c1856c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821846678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1821846678
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2089579733
Short name T913
Test name
Test status
Simulation time 56655621869 ps
CPU time 161.82 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:49:04 PM PDT 24
Peak memory 200424 kb
Host smart-267f4a25-4a02-41aa-8cdb-5c3a510445e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089579733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2089579733
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3644911921
Short name T346
Test name
Test status
Simulation time 8615751521 ps
CPU time 5.39 seconds
Started Mar 28 01:46:23 PM PDT 24
Finished Mar 28 01:46:29 PM PDT 24
Peak memory 198792 kb
Host smart-1add4faa-f23e-4021-ad2d-13580b7f39f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644911921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3644911921
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2003187691
Short name T1035
Test name
Test status
Simulation time 215503747134 ps
CPU time 35.86 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:46:56 PM PDT 24
Peak memory 199920 kb
Host smart-c6c8dc0f-3f33-4182-957d-19ef2b6721ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003187691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2003187691
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1178230483
Short name T997
Test name
Test status
Simulation time 17128417095 ps
CPU time 77.56 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:47:38 PM PDT 24
Peak memory 200436 kb
Host smart-84d8fe48-0cbf-4a2b-bcb2-c69a7da28b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178230483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1178230483
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.785380566
Short name T565
Test name
Test status
Simulation time 3271498591 ps
CPU time 5.54 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:28 PM PDT 24
Peak memory 198560 kb
Host smart-d006299d-c6d5-4887-9789-1d75f1325872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785380566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.785380566
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2625701454
Short name T512
Test name
Test status
Simulation time 78328808927 ps
CPU time 31.07 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:46:51 PM PDT 24
Peak memory 200492 kb
Host smart-ecd655ee-21ea-4129-8414-431a078da3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625701454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2625701454
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.679410401
Short name T742
Test name
Test status
Simulation time 6443727577 ps
CPU time 2.04 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:24 PM PDT 24
Peak memory 196744 kb
Host smart-b981ad09-45e9-4fc4-9ec6-6e8537de3ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679410401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.679410401
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.329117065
Short name T75
Test name
Test status
Simulation time 125448062 ps
CPU time 1.22 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:46:23 PM PDT 24
Peak memory 199132 kb
Host smart-d048bf03-25b1-48bb-b52a-7433e4cb0aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329117065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.329117065
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.456089458
Short name T151
Test name
Test status
Simulation time 172131378227 ps
CPU time 143.07 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:48:46 PM PDT 24
Peak memory 200536 kb
Host smart-9480fd3f-fbc5-441e-a24c-f25692453390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456089458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.456089458
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1561305123
Short name T426
Test name
Test status
Simulation time 70955771228 ps
CPU time 426.95 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:53:28 PM PDT 24
Peak memory 216080 kb
Host smart-435d4324-eb25-4717-97c9-2b2b215f1abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561305123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1561305123
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1583041743
Short name T1154
Test name
Test status
Simulation time 6572326005 ps
CPU time 20.46 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:46:42 PM PDT 24
Peak memory 200208 kb
Host smart-c3bd0088-163f-42dd-b0e0-ab523c9fe569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583041743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1583041743
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2310759600
Short name T279
Test name
Test status
Simulation time 197994774892 ps
CPU time 47.59 seconds
Started Mar 28 01:46:24 PM PDT 24
Finished Mar 28 01:47:11 PM PDT 24
Peak memory 200440 kb
Host smart-31265301-8723-4a2f-b0eb-8456b007b712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310759600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2310759600
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1303430345
Short name T972
Test name
Test status
Simulation time 49772758797 ps
CPU time 20.85 seconds
Started Mar 28 01:49:24 PM PDT 24
Finished Mar 28 01:49:45 PM PDT 24
Peak memory 199876 kb
Host smart-4d5530af-68c9-4492-aecb-45e7d5a29168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303430345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1303430345
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1129198443
Short name T518
Test name
Test status
Simulation time 44840777822 ps
CPU time 75.03 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:50:30 PM PDT 24
Peak memory 200508 kb
Host smart-24fd22dd-6c80-4db7-998f-cddafe284e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129198443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1129198443
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1029849181
Short name T1064
Test name
Test status
Simulation time 79065195322 ps
CPU time 31.26 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:49:46 PM PDT 24
Peak memory 200532 kb
Host smart-b2cfd9e4-3132-47a9-8516-f7225d0730da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029849181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1029849181
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2949217544
Short name T282
Test name
Test status
Simulation time 103744642175 ps
CPU time 134.76 seconds
Started Mar 28 01:49:17 PM PDT 24
Finished Mar 28 01:51:32 PM PDT 24
Peak memory 200240 kb
Host smart-7c93afa4-1b2e-489a-ad7e-f03cfd10c5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949217544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2949217544
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2454546085
Short name T501
Test name
Test status
Simulation time 72277194892 ps
CPU time 28.69 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:49:44 PM PDT 24
Peak memory 200468 kb
Host smart-7f73a605-81af-4555-b4a2-9473e0cc1c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454546085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2454546085
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.4031067808
Short name T888
Test name
Test status
Simulation time 31732043615 ps
CPU time 30.16 seconds
Started Mar 28 01:49:16 PM PDT 24
Finished Mar 28 01:49:46 PM PDT 24
Peak memory 200456 kb
Host smart-acf610ff-ba58-4f28-88c5-afa5a0970a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031067808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.4031067808
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3317818064
Short name T697
Test name
Test status
Simulation time 89456461558 ps
CPU time 30.5 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:49:46 PM PDT 24
Peak memory 200532 kb
Host smart-7514e973-0ec8-487a-bfd8-e578f67f637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317818064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3317818064
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.444974036
Short name T294
Test name
Test status
Simulation time 117001335961 ps
CPU time 167.1 seconds
Started Mar 28 01:49:13 PM PDT 24
Finished Mar 28 01:52:00 PM PDT 24
Peak memory 200432 kb
Host smart-6820f77b-2fc0-46d3-9c78-3b1522bb0ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444974036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.444974036
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2901362375
Short name T165
Test name
Test status
Simulation time 17533474778 ps
CPU time 27.32 seconds
Started Mar 28 01:49:17 PM PDT 24
Finished Mar 28 01:49:44 PM PDT 24
Peak memory 200500 kb
Host smart-dbe3991b-a61d-47ff-b047-46b11dcaeb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901362375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2901362375
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2196005433
Short name T233
Test name
Test status
Simulation time 162414727882 ps
CPU time 44.77 seconds
Started Mar 28 01:49:16 PM PDT 24
Finished Mar 28 01:50:01 PM PDT 24
Peak memory 200488 kb
Host smart-a9e3eefa-6970-457f-8ff2-0ea2d4133a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196005433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2196005433
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.463183478
Short name T24
Test name
Test status
Simulation time 20096566 ps
CPU time 0.55 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:46:22 PM PDT 24
Peak memory 195848 kb
Host smart-a4fc9451-f1ba-4851-8f8d-9950dc50a868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463183478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.463183478
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2155402887
Short name T1166
Test name
Test status
Simulation time 61891194293 ps
CPU time 90.19 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:47:50 PM PDT 24
Peak memory 200404 kb
Host smart-b2f1dc31-5f75-462c-a129-ea8cb4b93938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155402887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2155402887
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2740702189
Short name T708
Test name
Test status
Simulation time 8220094303 ps
CPU time 14.28 seconds
Started Mar 28 01:46:25 PM PDT 24
Finished Mar 28 01:46:39 PM PDT 24
Peak memory 198740 kb
Host smart-631e4484-7467-4fad-a9e2-6a63be774599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740702189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2740702189
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4225589237
Short name T629
Test name
Test status
Simulation time 65115935306 ps
CPU time 46.3 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:47:08 PM PDT 24
Peak memory 200432 kb
Host smart-dbedd120-7984-4d7b-bedb-a45dae4fd83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225589237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4225589237
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2153839078
Short name T1017
Test name
Test status
Simulation time 152553014897 ps
CPU time 77.65 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:47:39 PM PDT 24
Peak memory 200476 kb
Host smart-45a051b5-0821-47ab-9df6-c3ef6a1871fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153839078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2153839078
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3485685793
Short name T483
Test name
Test status
Simulation time 122099455823 ps
CPU time 496.92 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:54:36 PM PDT 24
Peak memory 200428 kb
Host smart-8d640618-a86c-4b79-8a87-6bb030219af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485685793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3485685793
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.228456135
Short name T694
Test name
Test status
Simulation time 8312947498 ps
CPU time 3.55 seconds
Started Mar 28 01:46:24 PM PDT 24
Finished Mar 28 01:46:27 PM PDT 24
Peak memory 200360 kb
Host smart-42cb6d88-f96b-49ce-b639-43faaff4855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228456135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.228456135
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2726923761
Short name T734
Test name
Test status
Simulation time 204484645272 ps
CPU time 75.22 seconds
Started Mar 28 01:46:21 PM PDT 24
Finished Mar 28 01:47:37 PM PDT 24
Peak memory 208732 kb
Host smart-a81c477a-e655-497c-a7f0-e4b7609ee1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726923761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2726923761
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1954834148
Short name T998
Test name
Test status
Simulation time 16328511384 ps
CPU time 959.17 seconds
Started Mar 28 01:46:24 PM PDT 24
Finished Mar 28 02:02:24 PM PDT 24
Peak memory 200440 kb
Host smart-2d189b26-34b2-4d2c-a07c-d5b5efc267ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954834148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1954834148
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.980732858
Short name T1170
Test name
Test status
Simulation time 2452869993 ps
CPU time 3.2 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:25 PM PDT 24
Peak memory 198832 kb
Host smart-6f327bf3-9a6f-40ef-943b-bd0c9d9d5ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980732858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.980732858
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.68760725
Short name T977
Test name
Test status
Simulation time 61677562107 ps
CPU time 100.39 seconds
Started Mar 28 01:46:15 PM PDT 24
Finished Mar 28 01:47:56 PM PDT 24
Peak memory 200464 kb
Host smart-83f4d57d-11d1-4dec-b97a-31074acd51a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68760725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.68760725
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.19786484
Short name T430
Test name
Test status
Simulation time 723792533 ps
CPU time 1.77 seconds
Started Mar 28 01:46:24 PM PDT 24
Finished Mar 28 01:46:26 PM PDT 24
Peak memory 196128 kb
Host smart-ca2be86b-b67e-4cf2-9e10-d890ca51a9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19786484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.19786484
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.952166434
Short name T763
Test name
Test status
Simulation time 738066943 ps
CPU time 3.11 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:25 PM PDT 24
Peak memory 198692 kb
Host smart-89cdd75f-a34b-4f4d-88ad-1758ed0725af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952166434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.952166434
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1264959645
Short name T754
Test name
Test status
Simulation time 6526073825 ps
CPU time 14.4 seconds
Started Mar 28 01:46:12 PM PDT 24
Finished Mar 28 01:46:28 PM PDT 24
Peak memory 200332 kb
Host smart-863a3b1e-1b5a-466f-b4ff-d72d52bc58eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264959645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1264959645
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1513639545
Short name T491
Test name
Test status
Simulation time 57166217766 ps
CPU time 104.88 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:48:05 PM PDT 24
Peak memory 200496 kb
Host smart-89ae1a50-f7b8-4ef2-b124-00fc388880aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513639545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1513639545
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3631430449
Short name T142
Test name
Test status
Simulation time 23273570631 ps
CPU time 33.64 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:49:49 PM PDT 24
Peak memory 200512 kb
Host smart-88f9b6e7-6723-4980-a20e-b40bed10988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631430449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3631430449
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3884725369
Short name T673
Test name
Test status
Simulation time 70497329341 ps
CPU time 120.61 seconds
Started Mar 28 01:49:24 PM PDT 24
Finished Mar 28 01:51:25 PM PDT 24
Peak memory 200028 kb
Host smart-98b001fd-01bd-4a1c-b81f-e58d7f4c37a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884725369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3884725369
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2614402056
Short name T319
Test name
Test status
Simulation time 36333230732 ps
CPU time 27.47 seconds
Started Mar 28 01:49:17 PM PDT 24
Finished Mar 28 01:49:44 PM PDT 24
Peak memory 200416 kb
Host smart-67de57bd-1625-484b-a5c0-0fea38a694da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614402056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2614402056
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3479367046
Short name T173
Test name
Test status
Simulation time 20598642874 ps
CPU time 35.97 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:49:51 PM PDT 24
Peak memory 200504 kb
Host smart-82402856-a86a-4bd9-846a-a06b27d31f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479367046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3479367046
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2363135261
Short name T244
Test name
Test status
Simulation time 240107679445 ps
CPU time 21.73 seconds
Started Mar 28 01:49:14 PM PDT 24
Finished Mar 28 01:49:36 PM PDT 24
Peak memory 200464 kb
Host smart-33929b64-b0c7-4782-9329-6696904a9849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363135261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2363135261
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1415737002
Short name T970
Test name
Test status
Simulation time 42109782994 ps
CPU time 68.28 seconds
Started Mar 28 01:49:15 PM PDT 24
Finished Mar 28 01:50:23 PM PDT 24
Peak memory 200488 kb
Host smart-63192adc-44fc-4e09-a1c5-e67ef96df74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415737002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1415737002
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2039121837
Short name T1103
Test name
Test status
Simulation time 68380767146 ps
CPU time 101.08 seconds
Started Mar 28 01:49:36 PM PDT 24
Finished Mar 28 01:51:18 PM PDT 24
Peak memory 200480 kb
Host smart-6c6c8d32-2a9b-464a-9a91-674da37ce7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039121837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2039121837
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2078461093
Short name T646
Test name
Test status
Simulation time 31094855 ps
CPU time 0.54 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:46:51 PM PDT 24
Peak memory 194852 kb
Host smart-fa1475bd-bde2-4bbe-97fa-e6a6f3f9fa71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078461093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2078461093
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2902786944
Short name T1179
Test name
Test status
Simulation time 126336827696 ps
CPU time 191.41 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:49:30 PM PDT 24
Peak memory 200304 kb
Host smart-5b3db237-47ae-4abe-be9a-4ceb3746004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902786944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2902786944
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.983404242
Short name T434
Test name
Test status
Simulation time 24396858256 ps
CPU time 12.52 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:35 PM PDT 24
Peak memory 200272 kb
Host smart-e864f433-1d30-467a-9d84-4dbf8f25c0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983404242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.983404242
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1889828029
Short name T980
Test name
Test status
Simulation time 8739390660 ps
CPU time 18.91 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:41 PM PDT 24
Peak memory 200448 kb
Host smart-a79e9861-5aaf-4a95-bdd4-d1eb7b0ac026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889828029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1889828029
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1824929931
Short name T1071
Test name
Test status
Simulation time 49631320994 ps
CPU time 10.93 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:33 PM PDT 24
Peak memory 200464 kb
Host smart-2504cf14-85cd-482d-826c-fab702a2cd8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824929931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1824929931
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3969149197
Short name T516
Test name
Test status
Simulation time 88917232195 ps
CPU time 418.63 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:53:48 PM PDT 24
Peak memory 200496 kb
Host smart-45b15bd6-4947-4b26-a661-051310dbbe0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969149197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3969149197
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1662255908
Short name T1014
Test name
Test status
Simulation time 2769289320 ps
CPU time 1.4 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:46:49 PM PDT 24
Peak memory 199208 kb
Host smart-19a6c4c0-cbec-44e9-8a1a-6518ba937728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662255908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1662255908
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.29735417
Short name T32
Test name
Test status
Simulation time 8575383860 ps
CPU time 5.14 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:28 PM PDT 24
Peak memory 200500 kb
Host smart-b902256d-2058-458e-9d57-5cf024043476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29735417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.29735417
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3244184924
Short name T278
Test name
Test status
Simulation time 7849612757 ps
CPU time 23.04 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:47:13 PM PDT 24
Peak memory 200468 kb
Host smart-d3d9b41e-96eb-44ea-9811-f2f140bf2069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244184924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3244184924
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.253989410
Short name T1030
Test name
Test status
Simulation time 5313983795 ps
CPU time 50.44 seconds
Started Mar 28 01:46:19 PM PDT 24
Finished Mar 28 01:47:10 PM PDT 24
Peak memory 199940 kb
Host smart-79159b8e-1d8c-4bdb-9918-118d77eeaada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253989410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.253989410
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.42374049
Short name T260
Test name
Test status
Simulation time 59136131197 ps
CPU time 86.53 seconds
Started Mar 28 01:46:46 PM PDT 24
Finished Mar 28 01:48:13 PM PDT 24
Peak memory 200460 kb
Host smart-db46b79d-ec30-42eb-a80c-1fc0517502c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42374049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.42374049
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.435452220
Short name T865
Test name
Test status
Simulation time 2673380097 ps
CPU time 1.79 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:46:23 PM PDT 24
Peak memory 196228 kb
Host smart-59625ce8-c641-441b-bf81-a32f076534ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435452220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.435452220
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.169003227
Short name T374
Test name
Test status
Simulation time 666154307 ps
CPU time 1.61 seconds
Started Mar 28 01:46:22 PM PDT 24
Finished Mar 28 01:46:24 PM PDT 24
Peak memory 198728 kb
Host smart-5c6e8b99-2395-434e-8171-379c7c4378ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169003227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.169003227
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2422901852
Short name T535
Test name
Test status
Simulation time 3397849452 ps
CPU time 2.84 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:46:50 PM PDT 24
Peak memory 199852 kb
Host smart-907777b9-217b-4276-ae18-19c0e355ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422901852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2422901852
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3715632530
Short name T1152
Test name
Test status
Simulation time 123571582031 ps
CPU time 187.33 seconds
Started Mar 28 01:46:20 PM PDT 24
Finished Mar 28 01:49:28 PM PDT 24
Peak memory 200452 kb
Host smart-60d2bd8d-2004-47e8-b227-fa2f51d54335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715632530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3715632530
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1918836562
Short name T908
Test name
Test status
Simulation time 21500732430 ps
CPU time 40.18 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:50:13 PM PDT 24
Peak memory 200404 kb
Host smart-198ae68c-bd1d-4659-8a27-fc26fedb4a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918836562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1918836562
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3397174528
Short name T228
Test name
Test status
Simulation time 190249280728 ps
CPU time 110.95 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:51:23 PM PDT 24
Peak memory 200496 kb
Host smart-1145ef99-771c-4b34-89fd-083983bbebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397174528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3397174528
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.102539226
Short name T557
Test name
Test status
Simulation time 35498567875 ps
CPU time 55.15 seconds
Started Mar 28 01:49:30 PM PDT 24
Finished Mar 28 01:50:25 PM PDT 24
Peak memory 200512 kb
Host smart-007f8619-280d-49ae-a097-fe484f887799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102539226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.102539226
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.872352965
Short name T886
Test name
Test status
Simulation time 178757275584 ps
CPU time 582.36 seconds
Started Mar 28 01:49:33 PM PDT 24
Finished Mar 28 01:59:15 PM PDT 24
Peak memory 200476 kb
Host smart-3c67b066-34c8-4c39-b53c-fcd4b665ec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872352965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.872352965
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1811817201
Short name T848
Test name
Test status
Simulation time 6301956006 ps
CPU time 5.85 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:49:38 PM PDT 24
Peak memory 199188 kb
Host smart-a488073f-0b24-4d07-935a-cf2a9dae70a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811817201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1811817201
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3575361135
Short name T236
Test name
Test status
Simulation time 74007648243 ps
CPU time 20.34 seconds
Started Mar 28 01:49:37 PM PDT 24
Finished Mar 28 01:49:57 PM PDT 24
Peak memory 200396 kb
Host smart-b7165bc3-3b46-49f1-862c-989a647fc2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575361135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3575361135
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1263681784
Short name T1016
Test name
Test status
Simulation time 16934082019 ps
CPU time 13.49 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:49:45 PM PDT 24
Peak memory 198944 kb
Host smart-e127877a-dd80-4bc3-9275-c5ec0598e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263681784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1263681784
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.466314756
Short name T209
Test name
Test status
Simulation time 203172687867 ps
CPU time 384.89 seconds
Started Mar 28 01:49:34 PM PDT 24
Finished Mar 28 01:55:59 PM PDT 24
Peak memory 200480 kb
Host smart-90b6fafd-8589-4ec7-b2a9-3405453f4d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466314756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.466314756
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2806111364
Short name T634
Test name
Test status
Simulation time 52974825793 ps
CPU time 21.52 seconds
Started Mar 28 01:49:33 PM PDT 24
Finished Mar 28 01:49:55 PM PDT 24
Peak memory 200528 kb
Host smart-192ce411-d7e9-436f-a9d3-56d8d0c1c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806111364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2806111364
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1719170983
Short name T213
Test name
Test status
Simulation time 12632435393 ps
CPU time 11.8 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:49:43 PM PDT 24
Peak memory 200512 kb
Host smart-0f711313-0102-45e0-966e-91bdd9573f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719170983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1719170983
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.745769399
Short name T904
Test name
Test status
Simulation time 12646132 ps
CPU time 0.58 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:46:52 PM PDT 24
Peak memory 195900 kb
Host smart-02576bc7-e36c-4149-9ec3-39b1585ccfd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745769399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.745769399
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.4016732942
Short name T814
Test name
Test status
Simulation time 114875504548 ps
CPU time 194.14 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:50:05 PM PDT 24
Peak memory 200308 kb
Host smart-3f0150b3-c7da-4855-84aa-d3c62cdf8cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016732942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.4016732942
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.671191777
Short name T350
Test name
Test status
Simulation time 60885422932 ps
CPU time 24.83 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:47:12 PM PDT 24
Peak memory 199864 kb
Host smart-3f6ee98a-6a83-4f18-83c5-163a46ea0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671191777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.671191777
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1651432943
Short name T861
Test name
Test status
Simulation time 9342406652 ps
CPU time 13.11 seconds
Started Mar 28 01:46:45 PM PDT 24
Finished Mar 28 01:46:59 PM PDT 24
Peak memory 200256 kb
Host smart-078c1656-9644-4da2-b8a1-53de10723eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651432943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1651432943
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2176349678
Short name T776
Test name
Test status
Simulation time 26102947372 ps
CPU time 39.57 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:47:27 PM PDT 24
Peak memory 200408 kb
Host smart-0fcc6786-c6eb-42bd-9fb8-e9fa2d696f09
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176349678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2176349678
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1456570576
Short name T431
Test name
Test status
Simulation time 118685191515 ps
CPU time 263.75 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:51:14 PM PDT 24
Peak memory 200472 kb
Host smart-8ab929bc-c966-43ec-8a3b-7c225bcdcc3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456570576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1456570576
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1982075373
Short name T627
Test name
Test status
Simulation time 2541905129 ps
CPU time 4.53 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:46:52 PM PDT 24
Peak memory 198544 kb
Host smart-7f090bfe-1432-4b50-b3cb-fbf4e7307f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982075373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1982075373
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1822269653
Short name T366
Test name
Test status
Simulation time 48376892576 ps
CPU time 94.59 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:48:21 PM PDT 24
Peak memory 200704 kb
Host smart-381d2225-f46a-4f19-9137-d6cc4ef1997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822269653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1822269653
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1890690387
Short name T990
Test name
Test status
Simulation time 9801157300 ps
CPU time 278.5 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:51:29 PM PDT 24
Peak memory 200340 kb
Host smart-35a73354-0897-4407-b83e-1843c7652819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890690387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1890690387
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2412621357
Short name T630
Test name
Test status
Simulation time 2727340505 ps
CPU time 6.64 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:46:56 PM PDT 24
Peak memory 199476 kb
Host smart-08778e17-3b3a-4d76-a146-bd3416a3b305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412621357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2412621357
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.604377144
Short name T1089
Test name
Test status
Simulation time 117368619614 ps
CPU time 262.33 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:51:09 PM PDT 24
Peak memory 200448 kb
Host smart-0b34ad45-38be-424b-ade6-eca9f222936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604377144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.604377144
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2471369240
Short name T263
Test name
Test status
Simulation time 4023381375 ps
CPU time 3.72 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:46:54 PM PDT 24
Peak memory 196480 kb
Host smart-af2bb848-4968-407b-994c-3f654462bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471369240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2471369240
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1326755754
Short name T295
Test name
Test status
Simulation time 5515456439 ps
CPU time 6.13 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:46:56 PM PDT 24
Peak memory 199736 kb
Host smart-3f157697-c828-481e-9bd7-977380ffff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326755754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1326755754
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.203496905
Short name T416
Test name
Test status
Simulation time 66847704582 ps
CPU time 28.92 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:47:18 PM PDT 24
Peak memory 200516 kb
Host smart-542dcf3b-d240-4e25-965a-2d911346447e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203496905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.203496905
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1410540708
Short name T783
Test name
Test status
Simulation time 309865429081 ps
CPU time 950.8 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 02:02:38 PM PDT 24
Peak memory 225424 kb
Host smart-c35fd331-1523-4f86-b147-9850cb3a0138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410540708 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1410540708
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4251119343
Short name T414
Test name
Test status
Simulation time 373390234 ps
CPU time 1.97 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 01:46:55 PM PDT 24
Peak memory 200100 kb
Host smart-e7f99795-979f-4595-8ec0-7769a5bbe31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251119343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4251119343
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3789590865
Short name T309
Test name
Test status
Simulation time 114386207522 ps
CPU time 18.61 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:47:05 PM PDT 24
Peak memory 200480 kb
Host smart-47b2c09f-1f54-45fd-b336-5c6a9cd631d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789590865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3789590865
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1092413095
Short name T241
Test name
Test status
Simulation time 198477968564 ps
CPU time 39.19 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:50:11 PM PDT 24
Peak memory 200536 kb
Host smart-4dfcac45-1299-4edb-b2e0-4841ed8b5bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092413095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1092413095
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.605084646
Short name T207
Test name
Test status
Simulation time 7722861901 ps
CPU time 14.07 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:49:45 PM PDT 24
Peak memory 200480 kb
Host smart-526231c4-12f9-4320-931a-05cc39b5c613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605084646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.605084646
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2904010017
Short name T318
Test name
Test status
Simulation time 65078412427 ps
CPU time 24.3 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:49:57 PM PDT 24
Peak memory 200484 kb
Host smart-c6ac5c49-2a31-4e95-ab0b-1e450ac7530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904010017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2904010017
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.994136681
Short name T555
Test name
Test status
Simulation time 74489903880 ps
CPU time 114.87 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:51:26 PM PDT 24
Peak memory 200444 kb
Host smart-d06ad0d3-b6f8-4020-ba59-1f7372257094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994136681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.994136681
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3253553948
Short name T1169
Test name
Test status
Simulation time 40469344721 ps
CPU time 34.69 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:50:07 PM PDT 24
Peak memory 200448 kb
Host smart-4a632ba0-c054-4669-99c3-2d9448bf4441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253553948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3253553948
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1089291101
Short name T201
Test name
Test status
Simulation time 89116624921 ps
CPU time 119.5 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:51:31 PM PDT 24
Peak memory 200440 kb
Host smart-e7e6c024-4736-4700-bb39-583822cabf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089291101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1089291101
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.799379223
Short name T298
Test name
Test status
Simulation time 148505698716 ps
CPU time 27.22 seconds
Started Mar 28 01:49:33 PM PDT 24
Finished Mar 28 01:50:00 PM PDT 24
Peak memory 200248 kb
Host smart-30dd6b2c-a1b5-4579-84a2-872cd1e73355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799379223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.799379223
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4265672597
Short name T641
Test name
Test status
Simulation time 20227321718 ps
CPU time 33.89 seconds
Started Mar 28 01:49:37 PM PDT 24
Finished Mar 28 01:50:11 PM PDT 24
Peak memory 200484 kb
Host smart-8bd27e83-0d5a-49e6-bf6e-438a375893ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265672597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4265672597
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3297795290
Short name T1086
Test name
Test status
Simulation time 13904500 ps
CPU time 0.56 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:46:50 PM PDT 24
Peak memory 195840 kb
Host smart-5b1dee8d-4040-4f80-8b77-f7d672494b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297795290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3297795290
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2769921848
Short name T919
Test name
Test status
Simulation time 43321360743 ps
CPU time 16.99 seconds
Started Mar 28 01:46:48 PM PDT 24
Finished Mar 28 01:47:05 PM PDT 24
Peak memory 200528 kb
Host smart-7356eda5-1261-492b-8b9e-ab01ed8b2b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769921848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2769921848
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.274432629
Short name T160
Test name
Test status
Simulation time 147328850072 ps
CPU time 31 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:47:20 PM PDT 24
Peak memory 200136 kb
Host smart-fa93a197-7267-44d4-a397-176f297849b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274432629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.274432629
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1148865045
Short name T624
Test name
Test status
Simulation time 26868354700 ps
CPU time 22.03 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:47:13 PM PDT 24
Peak memory 200456 kb
Host smart-0d14c2a7-10ea-4496-80e5-434d8335f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148865045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1148865045
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3411032745
Short name T879
Test name
Test status
Simulation time 39118128814 ps
CPU time 71.02 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:48:06 PM PDT 24
Peak memory 200544 kb
Host smart-1ac8d973-2cfa-4603-9377-568175822015
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411032745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3411032745
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3243374410
Short name T488
Test name
Test status
Simulation time 119731472150 ps
CPU time 199.84 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:50:11 PM PDT 24
Peak memory 200412 kb
Host smart-06fda7ee-04ba-4afc-bd3a-8de2424f28dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243374410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3243374410
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2509774222
Short name T478
Test name
Test status
Simulation time 2946923589 ps
CPU time 5.61 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:46:55 PM PDT 24
Peak memory 199184 kb
Host smart-8b6b9bec-5607-490e-a9eb-4e7a6648227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509774222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2509774222
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3129161928
Short name T1150
Test name
Test status
Simulation time 49769243201 ps
CPU time 42.35 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:47:30 PM PDT 24
Peak memory 200552 kb
Host smart-6b2475d8-9b57-491a-a879-fee4851b7444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129161928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3129161928
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3679061115
Short name T473
Test name
Test status
Simulation time 27589435400 ps
CPU time 1280.67 seconds
Started Mar 28 01:46:48 PM PDT 24
Finished Mar 28 02:08:09 PM PDT 24
Peak memory 200484 kb
Host smart-8fbcd4a9-262c-4c6a-9574-e70f4d0d64cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679061115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3679061115
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3843470397
Short name T856
Test name
Test status
Simulation time 6332526174 ps
CPU time 56.05 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:47:47 PM PDT 24
Peak memory 200472 kb
Host smart-f3ea1b9f-2925-4dc0-9264-a29105b6e85e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843470397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3843470397
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2799476042
Short name T34
Test name
Test status
Simulation time 100396493153 ps
CPU time 191.61 seconds
Started Mar 28 01:46:48 PM PDT 24
Finished Mar 28 01:49:59 PM PDT 24
Peak memory 200464 kb
Host smart-932b8e80-a5df-4c0c-a7b5-273ec89933aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799476042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2799476042
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.262110317
Short name T1184
Test name
Test status
Simulation time 40169263944 ps
CPU time 57.5 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 196172 kb
Host smart-6d7b88e8-f69b-4aec-87a7-640f27850256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262110317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.262110317
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.146699799
Short name T649
Test name
Test status
Simulation time 298705481 ps
CPU time 1.3 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:46:51 PM PDT 24
Peak memory 198792 kb
Host smart-93059475-e534-4fc5-99e2-461264c66ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146699799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.146699799
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3633309353
Short name T159
Test name
Test status
Simulation time 667352212737 ps
CPU time 842.15 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 02:00:52 PM PDT 24
Peak memory 210860 kb
Host smart-a98b445b-a802-4dfc-b8c5-3e6f29d28a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633309353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3633309353
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.331368979
Short name T505
Test name
Test status
Simulation time 56559134352 ps
CPU time 690.52 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:58:18 PM PDT 24
Peak memory 217092 kb
Host smart-719a913e-a06b-469a-bc4d-f2e591b62376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331368979 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.331368979
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2247119490
Short name T542
Test name
Test status
Simulation time 275288391 ps
CPU time 1.85 seconds
Started Mar 28 01:46:48 PM PDT 24
Finished Mar 28 01:46:50 PM PDT 24
Peak memory 200036 kb
Host smart-789e1a35-182f-4b45-bdc9-a807f5758125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247119490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2247119490
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1260203840
Short name T715
Test name
Test status
Simulation time 47360088097 ps
CPU time 28.45 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:47:18 PM PDT 24
Peak memory 200472 kb
Host smart-91bddb1a-31c7-4661-96bb-8e204a5f34a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260203840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1260203840
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.605696085
Short name T974
Test name
Test status
Simulation time 35119160311 ps
CPU time 15.25 seconds
Started Mar 28 01:49:36 PM PDT 24
Finished Mar 28 01:49:51 PM PDT 24
Peak memory 200492 kb
Host smart-f5fdd79b-e40f-4046-8a05-1bb76af5aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605696085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.605696085
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.574225966
Short name T316
Test name
Test status
Simulation time 34642390523 ps
CPU time 29.51 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:50:01 PM PDT 24
Peak memory 200472 kb
Host smart-5c6d427a-ee66-4741-b58e-c33c20cafc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574225966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.574225966
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.353718239
Short name T358
Test name
Test status
Simulation time 12059364118 ps
CPU time 18.3 seconds
Started Mar 28 01:49:30 PM PDT 24
Finished Mar 28 01:49:49 PM PDT 24
Peak memory 200236 kb
Host smart-0210a6ce-68b7-41eb-ab1d-6cdee8cea5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353718239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.353718239
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.564949525
Short name T1048
Test name
Test status
Simulation time 48138516946 ps
CPU time 69.07 seconds
Started Mar 28 01:49:37 PM PDT 24
Finished Mar 28 01:50:46 PM PDT 24
Peak memory 200452 kb
Host smart-e843dea3-de84-4eb7-bed3-8c3bb6fa72ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564949525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.564949525
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2423174099
Short name T1172
Test name
Test status
Simulation time 88159570574 ps
CPU time 34.86 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:50:06 PM PDT 24
Peak memory 200432 kb
Host smart-b5581c93-4a80-48db-bcdf-539927403dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423174099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2423174099
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1532656926
Short name T957
Test name
Test status
Simulation time 28102897710 ps
CPU time 33.27 seconds
Started Mar 28 01:49:34 PM PDT 24
Finished Mar 28 01:50:08 PM PDT 24
Peak memory 200536 kb
Host smart-78fe6635-e999-445e-b8b5-f32adc3215ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532656926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1532656926
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1026869063
Short name T223
Test name
Test status
Simulation time 28209915764 ps
CPU time 45.68 seconds
Started Mar 28 01:49:33 PM PDT 24
Finished Mar 28 01:50:19 PM PDT 24
Peak memory 200524 kb
Host smart-9237d807-1b0a-4d51-ade2-65dd4741c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026869063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1026869063
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3335924354
Short name T189
Test name
Test status
Simulation time 23152993252 ps
CPU time 39.93 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:50:12 PM PDT 24
Peak memory 200544 kb
Host smart-448f3f91-37a5-4a49-aee1-2b9fe9e0d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335924354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3335924354
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.33940397
Short name T779
Test name
Test status
Simulation time 24164101768 ps
CPU time 16.2 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:49:49 PM PDT 24
Peak memory 200416 kb
Host smart-913ba55c-d423-48c3-bb39-402b66882410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33940397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.33940397
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2997743558
Short name T528
Test name
Test status
Simulation time 13805983 ps
CPU time 0.57 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:46:55 PM PDT 24
Peak memory 195896 kb
Host smart-67b2b356-52ee-4699-bbf0-b270be42fa42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997743558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2997743558
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3861677692
Short name T90
Test name
Test status
Simulation time 277207310691 ps
CPU time 51.86 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:47:42 PM PDT 24
Peak memory 200244 kb
Host smart-b2ed463f-48a7-4e0a-8320-ae9faa131703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861677692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3861677692
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1727719291
Short name T379
Test name
Test status
Simulation time 48783564667 ps
CPU time 23.51 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:47:15 PM PDT 24
Peak memory 200312 kb
Host smart-d9d563d1-afbd-460c-aedb-5bcd9629b7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727719291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1727719291
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.234048372
Short name T1153
Test name
Test status
Simulation time 18839078557 ps
CPU time 30.94 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 01:47:24 PM PDT 24
Peak memory 200432 kb
Host smart-7653bad4-4450-488d-9fcd-2177a1161177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234048372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.234048372
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2721826437
Short name T1067
Test name
Test status
Simulation time 9814168529 ps
CPU time 13.64 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:47:04 PM PDT 24
Peak memory 197080 kb
Host smart-691a04f6-d29d-4b93-b2e1-2071fe0a7be1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721826437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2721826437
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4159990553
Short name T249
Test name
Test status
Simulation time 254174334647 ps
CPU time 242.69 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:50:53 PM PDT 24
Peak memory 200420 kb
Host smart-e0cb8f28-5a84-4ca7-9966-ef2d99cb22c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159990553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4159990553
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2330758246
Short name T1178
Test name
Test status
Simulation time 8621454992 ps
CPU time 18.5 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 01:47:12 PM PDT 24
Peak memory 200424 kb
Host smart-a595aa0b-d0b4-4359-a165-41fc2ffe37c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330758246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2330758246
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.4225305246
Short name T1074
Test name
Test status
Simulation time 27485839340 ps
CPU time 47.96 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:47:41 PM PDT 24
Peak memory 198296 kb
Host smart-ce1ab1b4-3bed-4541-b1e5-0efb8d43ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225305246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.4225305246
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1388258506
Short name T762
Test name
Test status
Simulation time 21446588306 ps
CPU time 1291.54 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 02:08:21 PM PDT 24
Peak memory 200500 kb
Host smart-0a4de99a-f7bb-4518-a666-958697866e5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388258506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1388258506
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3175406084
Short name T509
Test name
Test status
Simulation time 2866654439 ps
CPU time 5.53 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:46:57 PM PDT 24
Peak memory 199056 kb
Host smart-7b546639-e378-45a8-8945-a69bb71db370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175406084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3175406084
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1774886649
Short name T147
Test name
Test status
Simulation time 25749958797 ps
CPU time 18.64 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:47:09 PM PDT 24
Peak memory 199076 kb
Host smart-c7496889-877d-498a-93d2-eab12b5144d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774886649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1774886649
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3802120655
Short name T514
Test name
Test status
Simulation time 43234699653 ps
CPU time 59.21 seconds
Started Mar 28 01:46:47 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 196524 kb
Host smart-9a838411-e0a9-4a4a-85fa-8baf64cc73b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802120655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3802120655
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.768572400
Short name T364
Test name
Test status
Simulation time 516328592 ps
CPU time 1.34 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:46:53 PM PDT 24
Peak memory 199096 kb
Host smart-45613eee-47b3-4314-b1c4-2d278565d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768572400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.768572400
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1398957353
Short name T408
Test name
Test status
Simulation time 10646204560 ps
CPU time 10.3 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:47:01 PM PDT 24
Peak memory 200492 kb
Host smart-ab6f7d0c-ba2e-4aa0-914d-0a9066b170c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398957353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1398957353
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1574628808
Short name T29
Test name
Test status
Simulation time 36500707066 ps
CPU time 655.06 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:57:46 PM PDT 24
Peak memory 216004 kb
Host smart-dbf4f595-0f86-47f5-8e28-9ce61ce57edd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574628808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1574628808
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3162153249
Short name T1059
Test name
Test status
Simulation time 6223143801 ps
CPU time 19.05 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:47:09 PM PDT 24
Peak memory 200308 kb
Host smart-11f7008f-a0e7-4195-b376-bb46c321c359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162153249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3162153249
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.4181437627
Short name T743
Test name
Test status
Simulation time 43648764426 ps
CPU time 21.43 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:47:12 PM PDT 24
Peak memory 200484 kb
Host smart-eb5705de-6859-4044-adfc-c4bdd2f66345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181437627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4181437627
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3809148491
Short name T688
Test name
Test status
Simulation time 76176114627 ps
CPU time 41.49 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:50:14 PM PDT 24
Peak memory 200508 kb
Host smart-3c4e7835-a0be-4dc7-bb87-3f1301091860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809148491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3809148491
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1873524137
Short name T190
Test name
Test status
Simulation time 72317391665 ps
CPU time 43.33 seconds
Started Mar 28 01:49:38 PM PDT 24
Finished Mar 28 01:50:22 PM PDT 24
Peak memory 200444 kb
Host smart-961d8a80-9698-42f4-a0e9-3f1662b63931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873524137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1873524137
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2888616206
Short name T736
Test name
Test status
Simulation time 147614057814 ps
CPU time 218.58 seconds
Started Mar 28 01:49:30 PM PDT 24
Finished Mar 28 01:53:08 PM PDT 24
Peak memory 200436 kb
Host smart-2a0b17b3-e590-401b-a414-60220f688791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888616206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2888616206
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.4115876178
Short name T327
Test name
Test status
Simulation time 222839283419 ps
CPU time 304.79 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:54:37 PM PDT 24
Peak memory 200556 kb
Host smart-471bdadf-1009-47d3-a4f8-a1cda1bbaaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115876178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.4115876178
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.120443153
Short name T152
Test name
Test status
Simulation time 32952073674 ps
CPU time 49.44 seconds
Started Mar 28 01:49:31 PM PDT 24
Finished Mar 28 01:50:21 PM PDT 24
Peak memory 200488 kb
Host smart-30466336-f039-4660-b07c-04d37bd0f6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120443153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.120443153
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3292838101
Short name T117
Test name
Test status
Simulation time 90747334351 ps
CPU time 42.52 seconds
Started Mar 28 01:49:32 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 200408 kb
Host smart-e022e922-ce70-433e-977b-ce2a3e21c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292838101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3292838101
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1048069991
Short name T182
Test name
Test status
Simulation time 115789528937 ps
CPU time 170.92 seconds
Started Mar 28 01:49:47 PM PDT 24
Finished Mar 28 01:52:38 PM PDT 24
Peak memory 200524 kb
Host smart-3490a87d-e112-4a77-a5cd-34090d45efc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048069991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1048069991
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3632404918
Short name T564
Test name
Test status
Simulation time 28194108223 ps
CPU time 43.95 seconds
Started Mar 28 01:49:47 PM PDT 24
Finished Mar 28 01:50:31 PM PDT 24
Peak memory 200460 kb
Host smart-e4de4685-12fd-4a74-9a51-06115ace9526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632404918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3632404918
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3833406203
Short name T1119
Test name
Test status
Simulation time 14881376690 ps
CPU time 14.46 seconds
Started Mar 28 01:49:46 PM PDT 24
Finished Mar 28 01:50:01 PM PDT 24
Peak memory 200520 kb
Host smart-05977c4f-bd84-4b57-a764-1f1ab67e9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833406203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3833406203
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.225106567
Short name T531
Test name
Test status
Simulation time 14358544 ps
CPU time 0.57 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:46:58 PM PDT 24
Peak memory 195872 kb
Host smart-3b87f577-88fc-460a-8d13-a4584d9ef010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225106567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.225106567
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1334807553
Short name T690
Test name
Test status
Simulation time 32537474806 ps
CPU time 51.2 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 200452 kb
Host smart-13f1e768-822b-45a9-ac52-7e16a9b118a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334807553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1334807553
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3522901843
Short name T1143
Test name
Test status
Simulation time 260150398758 ps
CPU time 105.39 seconds
Started Mar 28 01:46:50 PM PDT 24
Finished Mar 28 01:48:35 PM PDT 24
Peak memory 200508 kb
Host smart-956e4107-c8b7-427b-b984-e399f93529ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522901843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3522901843
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1689118367
Short name T210
Test name
Test status
Simulation time 116337895554 ps
CPU time 33.55 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:31 PM PDT 24
Peak memory 200456 kb
Host smart-ec1b81a7-97c1-43f8-a6a7-b67f9c2da428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689118367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1689118367
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3355426402
Short name T104
Test name
Test status
Simulation time 79120651159 ps
CPU time 70.93 seconds
Started Mar 28 01:47:01 PM PDT 24
Finished Mar 28 01:48:12 PM PDT 24
Peak memory 200428 kb
Host smart-51582206-ebb0-4c3d-b8d0-21b5d1dd238c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355426402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3355426402
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.389968118
Short name T989
Test name
Test status
Simulation time 136620867760 ps
CPU time 427.21 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:54:04 PM PDT 24
Peak memory 200448 kb
Host smart-b11abea9-8aaf-4d70-895a-54ed64d23dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389968118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.389968118
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1883460236
Short name T18
Test name
Test status
Simulation time 5290017100 ps
CPU time 11.87 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:47:07 PM PDT 24
Peak memory 198960 kb
Host smart-a2d0c206-57c8-405b-8f5a-b3f79afece20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883460236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1883460236
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1111971683
Short name T1186
Test name
Test status
Simulation time 9266264288 ps
CPU time 14.82 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:12 PM PDT 24
Peak memory 195292 kb
Host smart-26bea02e-25c3-4f44-ab11-bda6634b1a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111971683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1111971683
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.928963215
Short name T942
Test name
Test status
Simulation time 5599942769 ps
CPU time 293.39 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:51:49 PM PDT 24
Peak memory 200436 kb
Host smart-8f483dc7-e5f4-4e86-b735-e0121743c0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928963215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.928963215
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1471274264
Short name T867
Test name
Test status
Simulation time 4001915013 ps
CPU time 17.42 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:47:13 PM PDT 24
Peak memory 199580 kb
Host smart-2bfcb86a-5465-4582-be63-21d951492fc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471274264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1471274264
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3890371087
Short name T744
Test name
Test status
Simulation time 47915054880 ps
CPU time 74.08 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:48:11 PM PDT 24
Peak memory 200248 kb
Host smart-8ec5a89b-1611-4fb8-a411-df6d5732d4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890371087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3890371087
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2862790506
Short name T475
Test name
Test status
Simulation time 2913276537 ps
CPU time 1.92 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:46:59 PM PDT 24
Peak memory 196516 kb
Host smart-11826f2f-33b0-4d42-aeee-926b85bd6782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862790506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2862790506
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2490622396
Short name T614
Test name
Test status
Simulation time 6419352246 ps
CPU time 6.61 seconds
Started Mar 28 01:46:54 PM PDT 24
Finished Mar 28 01:47:01 PM PDT 24
Peak memory 200372 kb
Host smart-5f847cb2-b581-4429-8bac-6a9bcc5e9ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490622396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2490622396
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3961449582
Short name T503
Test name
Test status
Simulation time 322886894298 ps
CPU time 542 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:55:59 PM PDT 24
Peak memory 208948 kb
Host smart-8b12f2dd-019b-4ff5-8469-c62c8820793b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961449582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3961449582
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.830610666
Short name T1111
Test name
Test status
Simulation time 12391689301 ps
CPU time 141.46 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:49:18 PM PDT 24
Peak memory 208776 kb
Host smart-25bc63bf-fdf2-4a64-8a6c-a62655d6c36f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830610666 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.830610666
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2889972153
Short name T439
Test name
Test status
Simulation time 1100007783 ps
CPU time 1.98 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:46:59 PM PDT 24
Peak memory 198616 kb
Host smart-9f61d456-6187-42de-bf7d-8db9d4706ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889972153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2889972153
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2274759394
Short name T541
Test name
Test status
Simulation time 54052612156 ps
CPU time 25.87 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:47:21 PM PDT 24
Peak memory 200576 kb
Host smart-9d86280d-e1cf-45f4-acb0-12a839e16561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274759394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2274759394
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1504936613
Short name T988
Test name
Test status
Simulation time 14687889993 ps
CPU time 26.7 seconds
Started Mar 28 01:49:48 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 200496 kb
Host smart-172f712d-0329-40dd-9756-836f0c94e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504936613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1504936613
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2385703412
Short name T835
Test name
Test status
Simulation time 50020245534 ps
CPU time 27.01 seconds
Started Mar 28 01:49:47 PM PDT 24
Finished Mar 28 01:50:14 PM PDT 24
Peak memory 200508 kb
Host smart-5ede04d0-f2b1-4d93-9c76-bfce7879c5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385703412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2385703412
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.799365257
Short name T324
Test name
Test status
Simulation time 93483534047 ps
CPU time 38.91 seconds
Started Mar 28 01:49:48 PM PDT 24
Finished Mar 28 01:50:27 PM PDT 24
Peak memory 200508 kb
Host smart-bd9d3f22-1b5b-421e-9f7e-17d25bb3495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799365257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.799365257
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3571636886
Short name T739
Test name
Test status
Simulation time 42062328069 ps
CPU time 76.12 seconds
Started Mar 28 01:49:48 PM PDT 24
Finished Mar 28 01:51:04 PM PDT 24
Peak memory 200472 kb
Host smart-956d64d2-21e8-456e-8cae-bafd7c298cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571636886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3571636886
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.4164731126
Short name T850
Test name
Test status
Simulation time 96305573170 ps
CPU time 134.96 seconds
Started Mar 28 01:49:46 PM PDT 24
Finished Mar 28 01:52:01 PM PDT 24
Peak memory 200512 kb
Host smart-15f2e2a9-8f7e-48af-bf76-054c0649abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164731126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.4164731126
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3178338870
Short name T864
Test name
Test status
Simulation time 83342294724 ps
CPU time 127.74 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:51:57 PM PDT 24
Peak memory 200492 kb
Host smart-2a3cb28f-7fe5-41b0-83f1-b416953f6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178338870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3178338870
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1661742317
Short name T1137
Test name
Test status
Simulation time 137781768035 ps
CPU time 199.9 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:53:09 PM PDT 24
Peak memory 200524 kb
Host smart-a9f4d5ed-419c-4b8a-8afc-11e76b431d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661742317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1661742317
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.291077776
Short name T949
Test name
Test status
Simulation time 17855878357 ps
CPU time 8.32 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:49:57 PM PDT 24
Peak memory 200500 kb
Host smart-902d09fd-6640-449a-9eda-7a1f46f4b97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291077776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.291077776
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2157442861
Short name T778
Test name
Test status
Simulation time 130380885798 ps
CPU time 130.09 seconds
Started Mar 28 01:49:48 PM PDT 24
Finished Mar 28 01:51:58 PM PDT 24
Peak memory 200484 kb
Host smart-58dd92c3-c3ed-4457-b3d9-92283f50b204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157442861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2157442861
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1666531032
Short name T467
Test name
Test status
Simulation time 17380439427 ps
CPU time 26.81 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:16 PM PDT 24
Peak memory 200532 kb
Host smart-517f1af1-7304-4b66-8a45-7aae21f1b6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666531032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1666531032
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4205920776
Short name T798
Test name
Test status
Simulation time 69798509 ps
CPU time 0.57 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:46:52 PM PDT 24
Peak memory 195876 kb
Host smart-2a839f17-8cbf-402a-a987-c340ab4deb3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205920776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4205920776
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3301709706
Short name T131
Test name
Test status
Simulation time 29052478581 ps
CPU time 48.37 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:45 PM PDT 24
Peak memory 200516 kb
Host smart-71f1c305-3be1-409f-920f-411928befc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301709706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3301709706
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1247704722
Short name T983
Test name
Test status
Simulation time 55286198635 ps
CPU time 9.6 seconds
Started Mar 28 01:46:59 PM PDT 24
Finished Mar 28 01:47:09 PM PDT 24
Peak memory 200452 kb
Host smart-939b7a8d-7d67-4d4d-9bec-89728ef79c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247704722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1247704722
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2320669627
Short name T199
Test name
Test status
Simulation time 78918304437 ps
CPU time 38.58 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:36 PM PDT 24
Peak memory 200484 kb
Host smart-58964fb1-1437-4562-9333-f92bc2e0e398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320669627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2320669627
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3485400801
Short name T636
Test name
Test status
Simulation time 28479815354 ps
CPU time 23.78 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:47:19 PM PDT 24
Peak memory 197592 kb
Host smart-a9a05a3b-de5b-4e5f-8ee1-240d2d7e0f19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485400801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3485400801
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2172277229
Short name T781
Test name
Test status
Simulation time 73888390890 ps
CPU time 124.41 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:49:02 PM PDT 24
Peak memory 200492 kb
Host smart-e146ceeb-2503-43e6-8cfa-b3ac0dbc0608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172277229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2172277229
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1769612530
Short name T1146
Test name
Test status
Simulation time 1124271665 ps
CPU time 2.46 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:00 PM PDT 24
Peak memory 196544 kb
Host smart-8c7bf373-b9bf-4112-ba6c-35aa6391c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769612530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1769612530
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3960775407
Short name T250
Test name
Test status
Simulation time 74686018696 ps
CPU time 152.52 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:49:29 PM PDT 24
Peak memory 200664 kb
Host smart-b6d536fd-03e0-45af-8762-32bfbd896661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960775407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3960775407
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.410661999
Short name T1155
Test name
Test status
Simulation time 17391298062 ps
CPU time 189.07 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:50:07 PM PDT 24
Peak memory 200436 kb
Host smart-8bd573b5-9f43-4b14-a575-c29fa4e1ea6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410661999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.410661999
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.855050898
Short name T370
Test name
Test status
Simulation time 5471117076 ps
CPU time 52.72 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:49 PM PDT 24
Peak memory 199708 kb
Host smart-38ad9388-89f0-4d55-a662-42dfd77b5f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855050898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.855050898
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3401670750
Short name T130
Test name
Test status
Simulation time 46949871521 ps
CPU time 37.28 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 01:47:31 PM PDT 24
Peak memory 200464 kb
Host smart-dac14c27-3980-479f-97de-49149f8e9a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401670750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3401670750
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2779106148
Short name T731
Test name
Test status
Simulation time 35985792470 ps
CPU time 56.52 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:54 PM PDT 24
Peak memory 196796 kb
Host smart-6668935c-86c0-4ad2-8ac4-44cdc6e39d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779106148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2779106148
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1373855076
Short name T1147
Test name
Test status
Simulation time 817413974 ps
CPU time 1.22 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:46:58 PM PDT 24
Peak memory 199204 kb
Host smart-fe7d7f0f-189a-489a-a834-7d7d981fe4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373855076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1373855076
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1486891142
Short name T504
Test name
Test status
Simulation time 185210650288 ps
CPU time 328.31 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:52:26 PM PDT 24
Peak memory 208912 kb
Host smart-090dee6d-73c2-4e96-b753-075f0d3fd4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486891142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1486891142
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3770313294
Short name T732
Test name
Test status
Simulation time 315902466750 ps
CPU time 1146.35 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 02:06:03 PM PDT 24
Peak memory 217432 kb
Host smart-f415cae1-eaf9-4b97-b9a9-b702df5650e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770313294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3770313294
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2348397519
Short name T563
Test name
Test status
Simulation time 929233353 ps
CPU time 1.88 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:00 PM PDT 24
Peak memory 198736 kb
Host smart-b193429e-b2b2-41c7-9edf-d043a97d48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348397519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2348397519
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2923568956
Short name T628
Test name
Test status
Simulation time 84307269591 ps
CPU time 60.14 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:57 PM PDT 24
Peak memory 200516 kb
Host smart-08c9c944-9b31-4b79-90bc-480e09826134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923568956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2923568956
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.758465792
Short name T181
Test name
Test status
Simulation time 17306135071 ps
CPU time 28.01 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:17 PM PDT 24
Peak memory 200444 kb
Host smart-69d14af2-a741-445f-9b6a-9362f2aa5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758465792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.758465792
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.931216467
Short name T896
Test name
Test status
Simulation time 15868415928 ps
CPU time 12.98 seconds
Started Mar 28 01:49:47 PM PDT 24
Finished Mar 28 01:50:00 PM PDT 24
Peak memory 200256 kb
Host smart-72ac161e-e42f-4e35-930d-375f85e55c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931216467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.931216467
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1143048402
Short name T1009
Test name
Test status
Simulation time 32052584658 ps
CPU time 24.81 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:14 PM PDT 24
Peak memory 200532 kb
Host smart-0b0108d6-0f61-47b4-9161-f6e27a080c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143048402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1143048402
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2034525558
Short name T172
Test name
Test status
Simulation time 72324896578 ps
CPU time 118.07 seconds
Started Mar 28 01:49:50 PM PDT 24
Finished Mar 28 01:51:48 PM PDT 24
Peak memory 200472 kb
Host smart-7d99d2c2-d541-4726-9940-b7ca1b337803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034525558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2034525558
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3285383314
Short name T549
Test name
Test status
Simulation time 14101499989 ps
CPU time 6.51 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:49:55 PM PDT 24
Peak memory 199324 kb
Host smart-56f9960e-2a9c-4d98-998e-92b7d9632ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285383314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3285383314
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.4147198703
Short name T799
Test name
Test status
Simulation time 22731098637 ps
CPU time 18.33 seconds
Started Mar 28 01:49:50 PM PDT 24
Finished Mar 28 01:50:09 PM PDT 24
Peak memory 200492 kb
Host smart-f2bd3651-d907-48c1-8d57-358f1b831e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147198703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4147198703
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2909994654
Short name T462
Test name
Test status
Simulation time 188919470160 ps
CPU time 39.02 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:28 PM PDT 24
Peak memory 200468 kb
Host smart-29155627-fb6f-44ac-8129-5962c297bb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909994654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2909994654
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1976130431
Short name T845
Test name
Test status
Simulation time 18722232498 ps
CPU time 46.83 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:36 PM PDT 24
Peak memory 200452 kb
Host smart-ded56b9b-27d0-4670-aace-0ecd87aa8aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976130431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1976130431
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.4153603520
Short name T704
Test name
Test status
Simulation time 17293110 ps
CPU time 0.58 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:46:57 PM PDT 24
Peak memory 195868 kb
Host smart-b85bb032-bc3e-47e8-9135-eef1f9ef8ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153603520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.4153603520
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4265519874
Short name T1168
Test name
Test status
Simulation time 16769658972 ps
CPU time 13.78 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:11 PM PDT 24
Peak memory 200500 kb
Host smart-3adb8ce9-e792-4a8a-b6f3-3a451f9fce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265519874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4265519874
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.867952090
Short name T317
Test name
Test status
Simulation time 43562395132 ps
CPU time 17.06 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:47:09 PM PDT 24
Peak memory 200492 kb
Host smart-62d2751c-af85-41af-920f-c1538fdc61c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867952090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.867952090
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.20985092
Short name T466
Test name
Test status
Simulation time 58244059602 ps
CPU time 286.54 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:51:38 PM PDT 24
Peak memory 200524 kb
Host smart-b496f71f-bfbc-496a-8f76-7828b547fd5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20985092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.20985092
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3632804389
Short name T755
Test name
Test status
Simulation time 9699573244 ps
CPU time 7.29 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:47:02 PM PDT 24
Peak memory 200448 kb
Host smart-d6b2d8bb-51c5-471a-ac55-a1f569422b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632804389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3632804389
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.40945978
Short name T843
Test name
Test status
Simulation time 109571121197 ps
CPU time 37.23 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 01:47:30 PM PDT 24
Peak memory 200320 kb
Host smart-df5f8001-a8aa-492b-8203-95f3658cad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40945978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.40945978
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.412278405
Short name T1047
Test name
Test status
Simulation time 11507243504 ps
CPU time 449.33 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 01:54:22 PM PDT 24
Peak memory 200508 kb
Host smart-f1b44d23-8047-4430-a4fc-4288cefa96bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412278405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.412278405
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.4101885533
Short name T1120
Test name
Test status
Simulation time 6792148470 ps
CPU time 60.62 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:47:53 PM PDT 24
Peak memory 199776 kb
Host smart-fd3fee37-44f8-4bb0-ae5b-d242463b2ca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101885533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4101885533
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.71609103
Short name T303
Test name
Test status
Simulation time 137904525180 ps
CPU time 242.52 seconds
Started Mar 28 01:46:51 PM PDT 24
Finished Mar 28 01:50:54 PM PDT 24
Peak memory 200492 kb
Host smart-28a64bf0-0b9b-4309-b929-0d1665b49bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71609103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.71609103
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3457030732
Short name T289
Test name
Test status
Simulation time 28970827585 ps
CPU time 50.23 seconds
Started Mar 28 01:46:53 PM PDT 24
Finished Mar 28 01:47:43 PM PDT 24
Peak memory 196508 kb
Host smart-7f95a27d-b3bd-411d-844b-95df3c60d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457030732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3457030732
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3635343025
Short name T982
Test name
Test status
Simulation time 531895423 ps
CPU time 1.97 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:46:58 PM PDT 24
Peak memory 199236 kb
Host smart-6ddf6b00-8005-4586-b345-226ff0106515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635343025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3635343025
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3168083
Short name T892
Test name
Test status
Simulation time 210801330245 ps
CPU time 22.53 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:19 PM PDT 24
Peak memory 200436 kb
Host smart-0ba183f2-86a5-43b5-9dd5-517800b94e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3168083
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3567890565
Short name T802
Test name
Test status
Simulation time 1654176053 ps
CPU time 2.84 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:01 PM PDT 24
Peak memory 198972 kb
Host smart-c4d91071-e4c6-4902-b25e-03b6f41fe2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567890565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3567890565
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2476045401
Short name T1134
Test name
Test status
Simulation time 52718763124 ps
CPU time 38.89 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:47:35 PM PDT 24
Peak memory 200468 kb
Host smart-43eb96c9-c1e3-459b-8ad0-f90dffd03923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476045401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2476045401
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3278861462
Short name T654
Test name
Test status
Simulation time 19205169908 ps
CPU time 15.99 seconds
Started Mar 28 01:49:50 PM PDT 24
Finished Mar 28 01:50:06 PM PDT 24
Peak memory 200232 kb
Host smart-c32e216e-32da-4f03-be37-9ca80e602b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278861462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3278861462
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2203926787
Short name T605
Test name
Test status
Simulation time 50541564420 ps
CPU time 19.34 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:09 PM PDT 24
Peak memory 200460 kb
Host smart-ded19c6e-83ce-4f87-a182-2d30c31f0e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203926787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2203926787
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2321708924
Short name T155
Test name
Test status
Simulation time 75786605197 ps
CPU time 133.12 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:52:02 PM PDT 24
Peak memory 200476 kb
Host smart-38ec94ad-e171-427d-91b7-db35ae32a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321708924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2321708924
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.756490876
Short name T714
Test name
Test status
Simulation time 25912196167 ps
CPU time 15.03 seconds
Started Mar 28 01:49:50 PM PDT 24
Finished Mar 28 01:50:06 PM PDT 24
Peak memory 200524 kb
Host smart-d14e34dc-6105-493c-beed-3791dba8793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756490876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.756490876
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3565693046
Short name T534
Test name
Test status
Simulation time 35282086713 ps
CPU time 58.08 seconds
Started Mar 28 01:49:47 PM PDT 24
Finished Mar 28 01:50:46 PM PDT 24
Peak memory 200188 kb
Host smart-4adbd0d3-3f10-4e4b-82d7-5ff772cfa118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565693046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3565693046
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2360554537
Short name T911
Test name
Test status
Simulation time 51050020568 ps
CPU time 41.71 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:31 PM PDT 24
Peak memory 200464 kb
Host smart-e5a60fd0-1b65-4846-bcc4-09faef382ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360554537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2360554537
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2186701295
Short name T200
Test name
Test status
Simulation time 164169987689 ps
CPU time 164.79 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:52:34 PM PDT 24
Peak memory 200472 kb
Host smart-66e2e9f1-73ac-44d6-9756-1b7324663a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186701295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2186701295
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3004719185
Short name T177
Test name
Test status
Simulation time 30859231017 ps
CPU time 74.75 seconds
Started Mar 28 01:49:50 PM PDT 24
Finished Mar 28 01:51:05 PM PDT 24
Peak memory 200472 kb
Host smart-a22eccf4-4c75-40e4-a7c1-8c010c9691a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004719185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3004719185
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.527982625
Short name T1113
Test name
Test status
Simulation time 37989600362 ps
CPU time 60.32 seconds
Started Mar 28 01:49:55 PM PDT 24
Finished Mar 28 01:50:55 PM PDT 24
Peak memory 200500 kb
Host smart-fa2784e0-d3fd-4520-afe5-bf93298fc113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527982625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.527982625
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1147367153
Short name T893
Test name
Test status
Simulation time 28375877837 ps
CPU time 50.81 seconds
Started Mar 28 01:49:48 PM PDT 24
Finished Mar 28 01:50:39 PM PDT 24
Peak memory 200536 kb
Host smart-e883a849-8f0b-496b-80b4-773bc9fea5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147367153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1147367153
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2064501507
Short name T1004
Test name
Test status
Simulation time 212115986 ps
CPU time 0.56 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:46:58 PM PDT 24
Peak memory 195868 kb
Host smart-30ae1331-07eb-4f60-a30a-5ad4c6b173a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064501507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2064501507
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3790605583
Short name T377
Test name
Test status
Simulation time 37664452121 ps
CPU time 67.45 seconds
Started Mar 28 01:47:00 PM PDT 24
Finished Mar 28 01:48:07 PM PDT 24
Peak memory 200396 kb
Host smart-6df274b0-d9a7-4efe-8b96-2b9cd53838a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790605583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3790605583
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1342681545
Short name T116
Test name
Test status
Simulation time 132895266845 ps
CPU time 134.68 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:49:13 PM PDT 24
Peak memory 200464 kb
Host smart-6f26f0a8-0db9-4dea-8c9c-45772871f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342681545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1342681545
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2190586529
Short name T458
Test name
Test status
Simulation time 62711595320 ps
CPU time 106.97 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:48:42 PM PDT 24
Peak memory 200416 kb
Host smart-41d8a899-fd6b-4bd7-94c9-4bf8ae7218f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190586529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2190586529
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3218289083
Short name T1023
Test name
Test status
Simulation time 142313247872 ps
CPU time 213.81 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:50:33 PM PDT 24
Peak memory 200492 kb
Host smart-29fee8ae-b20a-4a38-a776-f9b3295133c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218289083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3218289083
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1928592680
Short name T1100
Test name
Test status
Simulation time 74460737449 ps
CPU time 425.87 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:54:03 PM PDT 24
Peak memory 200524 kb
Host smart-829da424-e593-4611-9a23-61d6cd9cd593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928592680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1928592680
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3709696414
Short name T827
Test name
Test status
Simulation time 162627935 ps
CPU time 0.63 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:46:56 PM PDT 24
Peak memory 196256 kb
Host smart-3c27110b-9b22-4d92-bf3e-3fbb93302ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709696414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3709696414
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3934157991
Short name T855
Test name
Test status
Simulation time 7159300458 ps
CPU time 11.02 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:09 PM PDT 24
Peak memory 197556 kb
Host smart-727c7aea-d635-4877-888d-cc5dadffb756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934157991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3934157991
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.800401073
Short name T507
Test name
Test status
Simulation time 1943502956 ps
CPU time 113.4 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:48:50 PM PDT 24
Peak memory 200432 kb
Host smart-c5259823-766e-4500-beeb-b65749c3a99f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800401073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.800401073
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1110389461
Short name T360
Test name
Test status
Simulation time 3356364930 ps
CPU time 5.93 seconds
Started Mar 28 01:46:55 PM PDT 24
Finished Mar 28 01:47:01 PM PDT 24
Peak memory 199552 kb
Host smart-4e52c366-7266-4cf2-a1ad-911a6984c528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110389461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1110389461
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1058079233
Short name T162
Test name
Test status
Simulation time 128298034124 ps
CPU time 57.18 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:55 PM PDT 24
Peak memory 200472 kb
Host smart-5676dc4c-e499-41ff-9382-5336f839fce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058079233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1058079233
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1679361425
Short name T1135
Test name
Test status
Simulation time 7185063258 ps
CPU time 3.35 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:00 PM PDT 24
Peak memory 196844 kb
Host smart-906353ba-4320-411b-a839-8edfce523c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679361425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1679361425
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1159884736
Short name T909
Test name
Test status
Simulation time 625852265 ps
CPU time 3.41 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:01 PM PDT 24
Peak memory 198736 kb
Host smart-4cece604-16a2-4937-8a10-cfd39422b9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159884736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1159884736
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.645172393
Short name T266
Test name
Test status
Simulation time 301161650634 ps
CPU time 1265.08 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 02:08:03 PM PDT 24
Peak memory 200448 kb
Host smart-c096369e-c45f-4ef9-8ebb-4a91a11e0836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645172393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.645172393
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1807136010
Short name T626
Test name
Test status
Simulation time 74384594165 ps
CPU time 493.71 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:55:03 PM PDT 24
Peak memory 216908 kb
Host smart-367b43be-827b-4f1c-8ac1-328d998c6ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807136010 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1807136010
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1273578502
Short name T643
Test name
Test status
Simulation time 571976242 ps
CPU time 1.5 seconds
Started Mar 28 01:47:00 PM PDT 24
Finished Mar 28 01:47:01 PM PDT 24
Peak memory 198944 kb
Host smart-fd627696-ece4-4750-8495-ae7c136b196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273578502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1273578502
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4032576985
Short name T621
Test name
Test status
Simulation time 97097577659 ps
CPU time 198.16 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 200448 kb
Host smart-5fad56a9-7aca-408c-8117-2b0909685d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032576985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4032576985
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1945673892
Short name T826
Test name
Test status
Simulation time 8463274216 ps
CPU time 10.02 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:49:59 PM PDT 24
Peak memory 200440 kb
Host smart-3dd3b0f9-55f2-40b8-b682-bf24e3c9540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945673892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1945673892
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2824968566
Short name T954
Test name
Test status
Simulation time 17533688802 ps
CPU time 25.64 seconds
Started Mar 28 01:49:49 PM PDT 24
Finished Mar 28 01:50:14 PM PDT 24
Peak memory 200068 kb
Host smart-a3e13d04-5d4e-4f62-ae99-01eb70df7e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824968566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2824968566
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1966515446
Short name T302
Test name
Test status
Simulation time 101908792963 ps
CPU time 172.78 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:53:02 PM PDT 24
Peak memory 200424 kb
Host smart-fb9708af-ffc8-4841-bcfd-8d23f0c5b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966515446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1966515446
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2009262953
Short name T406
Test name
Test status
Simulation time 18599648995 ps
CPU time 27.44 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:50:37 PM PDT 24
Peak memory 199756 kb
Host smart-8cb79993-5de2-43e4-9fd8-529b867c8be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009262953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2009262953
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3228350081
Short name T609
Test name
Test status
Simulation time 20069798025 ps
CPU time 32.21 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:50:40 PM PDT 24
Peak memory 200268 kb
Host smart-06de6a76-c487-4c4b-88cd-9876ab6b7014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228350081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3228350081
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.356655849
Short name T348
Test name
Test status
Simulation time 13364838772 ps
CPU time 20.58 seconds
Started Mar 28 01:50:07 PM PDT 24
Finished Mar 28 01:50:28 PM PDT 24
Peak memory 200252 kb
Host smart-9d5bcf3d-d1b7-46dc-a4a3-24f55afab371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356655849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.356655849
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1762944935
Short name T604
Test name
Test status
Simulation time 97105133903 ps
CPU time 38.68 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:50:48 PM PDT 24
Peak memory 200440 kb
Host smart-6e4ceb0c-4133-4cd2-be4f-fff73115255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762944935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1762944935
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3593692226
Short name T1082
Test name
Test status
Simulation time 25750373850 ps
CPU time 44.47 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:50:52 PM PDT 24
Peak memory 200480 kb
Host smart-7d84df9f-38fa-4c1e-9f80-a982ed86cc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593692226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3593692226
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3471448562
Short name T367
Test name
Test status
Simulation time 38438155 ps
CPU time 0.57 seconds
Started Mar 28 01:45:03 PM PDT 24
Finished Mar 28 01:45:04 PM PDT 24
Peak memory 195860 kb
Host smart-7f67031b-0942-4356-a674-6633522b154f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471448562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3471448562
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.985524678
Short name T140
Test name
Test status
Simulation time 41274112852 ps
CPU time 9.7 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 01:45:05 PM PDT 24
Peak memory 200484 kb
Host smart-2f956d17-fbcf-4fda-883f-e9bc6ad42cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985524678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.985524678
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.855931965
Short name T562
Test name
Test status
Simulation time 70486424624 ps
CPU time 54.26 seconds
Started Mar 28 01:44:57 PM PDT 24
Finished Mar 28 01:45:51 PM PDT 24
Peak memory 200084 kb
Host smart-39ea5576-e0a5-429d-b411-741efec56fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855931965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.855931965
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4131982843
Short name T1157
Test name
Test status
Simulation time 74292846791 ps
CPU time 17.83 seconds
Started Mar 28 01:45:03 PM PDT 24
Finished Mar 28 01:45:21 PM PDT 24
Peak memory 200472 kb
Host smart-34c29658-59d5-4a7d-b6e2-c67108888ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131982843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4131982843
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4232212383
Short name T519
Test name
Test status
Simulation time 11546548320 ps
CPU time 27.42 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 01:45:23 PM PDT 24
Peak memory 200476 kb
Host smart-5c1d2b41-6446-4737-b78a-806868f97abe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232212383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4232212383
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.768739960
Short name T526
Test name
Test status
Simulation time 134876490100 ps
CPU time 394.04 seconds
Started Mar 28 01:45:09 PM PDT 24
Finished Mar 28 01:51:44 PM PDT 24
Peak memory 200412 kb
Host smart-9ccb6d5f-ec7d-4248-99f9-30c526a8ed0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=768739960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.768739960
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3464008513
Short name T657
Test name
Test status
Simulation time 5712297457 ps
CPU time 7.9 seconds
Started Mar 28 01:45:04 PM PDT 24
Finished Mar 28 01:45:12 PM PDT 24
Peak memory 200416 kb
Host smart-1c5d433e-171e-4cfe-9ed8-7f025bf7217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464008513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3464008513
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.41086561
Short name T1181
Test name
Test status
Simulation time 9175334487 ps
CPU time 15.68 seconds
Started Mar 28 01:45:08 PM PDT 24
Finished Mar 28 01:45:24 PM PDT 24
Peak memory 195032 kb
Host smart-e2fcf735-6ac1-4642-85a3-4cec8e6c56bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41086561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.41086561
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1512602605
Short name T262
Test name
Test status
Simulation time 17750370333 ps
CPU time 1003.39 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 02:01:39 PM PDT 24
Peak memory 200432 kb
Host smart-d5d9c341-a204-404b-96c3-c4b6fcf58d01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512602605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1512602605
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3144899909
Short name T611
Test name
Test status
Simulation time 5689358231 ps
CPU time 13.68 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:45:14 PM PDT 24
Peak memory 198636 kb
Host smart-154dab10-15d5-44da-962c-f527c9e2cb54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144899909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3144899909
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1412267090
Short name T725
Test name
Test status
Simulation time 30091734851 ps
CPU time 13.44 seconds
Started Mar 28 01:44:59 PM PDT 24
Finished Mar 28 01:45:13 PM PDT 24
Peak memory 198852 kb
Host smart-5ea2f214-bcb5-4861-9419-19dff2ae79d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412267090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1412267090
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2729207771
Short name T570
Test name
Test status
Simulation time 2937814237 ps
CPU time 5.76 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:45:06 PM PDT 24
Peak memory 196488 kb
Host smart-0563df2a-998d-4157-83de-b1db1e5d8d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729207771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2729207771
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.330621827
Short name T1104
Test name
Test status
Simulation time 696059137 ps
CPU time 3.46 seconds
Started Mar 28 01:44:57 PM PDT 24
Finished Mar 28 01:45:01 PM PDT 24
Peak memory 199388 kb
Host smart-dcf89bc9-6f2d-4ed6-82b1-ea6b1b57a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330621827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.330621827
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.354603187
Short name T330
Test name
Test status
Simulation time 51069820003 ps
CPU time 139.1 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:47:22 PM PDT 24
Peak memory 200444 kb
Host smart-def9c7c2-bd89-4b4a-869b-ef4e2c7e38cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354603187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.354603187
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2261357585
Short name T986
Test name
Test status
Simulation time 179890385029 ps
CPU time 1244.91 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 02:05:45 PM PDT 24
Peak memory 216952 kb
Host smart-32932990-7179-47f5-9dae-952ae35186eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261357585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2261357585
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3911680419
Short name T271
Test name
Test status
Simulation time 7104588291 ps
CPU time 11.34 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:45:13 PM PDT 24
Peak memory 200544 kb
Host smart-4be543ef-27e0-49a4-9f14-e6e8da00b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911680419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3911680419
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3831826553
Short name T1159
Test name
Test status
Simulation time 241319423690 ps
CPU time 84.28 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 01:46:21 PM PDT 24
Peak memory 200472 kb
Host smart-c45e96a1-9fd4-46b9-823e-f19f936673d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831826553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3831826553
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4244598385
Short name T1060
Test name
Test status
Simulation time 26680178 ps
CPU time 0.56 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:46:57 PM PDT 24
Peak memory 195884 kb
Host smart-6adc3e77-becf-47ad-a97d-be08486fb2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244598385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4244598385
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1080878129
Short name T606
Test name
Test status
Simulation time 39290320952 ps
CPU time 52.58 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:51 PM PDT 24
Peak memory 200400 kb
Host smart-fb3da58c-c245-4a46-8a75-a08dc3e7811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080878129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1080878129
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4282108877
Short name T663
Test name
Test status
Simulation time 115586592791 ps
CPU time 48.22 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:45 PM PDT 24
Peak memory 200424 kb
Host smart-a916d5b6-5200-4d50-8774-9d46c8c8b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282108877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4282108877
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1091793258
Short name T676
Test name
Test status
Simulation time 42155382709 ps
CPU time 254.29 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:51:12 PM PDT 24
Peak memory 200464 kb
Host smart-75ca718c-a13b-4ef7-8693-530899db049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091793258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1091793258
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4025416976
Short name T551
Test name
Test status
Simulation time 20136437203 ps
CPU time 31.02 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:29 PM PDT 24
Peak memory 198260 kb
Host smart-a6d38cd7-798e-453a-a960-1d9bcab599da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025416976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4025416976
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.4169017689
Short name T1063
Test name
Test status
Simulation time 122082910162 ps
CPU time 321.38 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:52:18 PM PDT 24
Peak memory 200468 kb
Host smart-d9976c3d-64f7-4b73-b43a-b22ac4aca146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169017689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.4169017689
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.524319945
Short name T612
Test name
Test status
Simulation time 287303448 ps
CPU time 1.09 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:46:59 PM PDT 24
Peak memory 196480 kb
Host smart-79144b42-d85c-4c0d-a905-6528735a332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524319945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.524319945
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.676961918
Short name T709
Test name
Test status
Simulation time 62858632417 ps
CPU time 57.23 seconds
Started Mar 28 01:46:59 PM PDT 24
Finished Mar 28 01:47:56 PM PDT 24
Peak memory 208896 kb
Host smart-4596988b-6fcc-4d58-94cb-487c01fcb925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676961918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.676961918
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1373317189
Short name T1028
Test name
Test status
Simulation time 13341403407 ps
CPU time 317.14 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:52:16 PM PDT 24
Peak memory 200512 kb
Host smart-2babc821-f09d-4723-a889-b30450563655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373317189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1373317189
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1926483407
Short name T1183
Test name
Test status
Simulation time 7729619760 ps
CPU time 16.56 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:13 PM PDT 24
Peak memory 198604 kb
Host smart-14529eb0-6430-48ac-9092-2e532388cf71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926483407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1926483407
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3637388370
Short name T135
Test name
Test status
Simulation time 18704245973 ps
CPU time 52.34 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 200404 kb
Host smart-c8382205-9b0c-405b-9731-ae87f68f9207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637388370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3637388370
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1178214832
Short name T932
Test name
Test status
Simulation time 3315818488 ps
CPU time 1.82 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:00 PM PDT 24
Peak memory 196276 kb
Host smart-24be715a-648b-418f-a7eb-c3ff7a6b4e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178214832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1178214832
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3643763938
Short name T915
Test name
Test status
Simulation time 5301161869 ps
CPU time 7.69 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:47:04 PM PDT 24
Peak memory 200244 kb
Host smart-8ba029b8-46f0-4dda-a71a-4161e6b7804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643763938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3643763938
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3178750622
Short name T326
Test name
Test status
Simulation time 83406335528 ps
CPU time 557.21 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:56:09 PM PDT 24
Peak memory 200540 kb
Host smart-fca4a8e4-f992-45dc-9d7a-456300375a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178750622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3178750622
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2310299124
Short name T871
Test name
Test status
Simulation time 517722023640 ps
CPU time 705.68 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:58:42 PM PDT 24
Peak memory 225444 kb
Host smart-321bcf11-05b6-4a90-9013-513e0d2704ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310299124 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2310299124
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2553466354
Short name T96
Test name
Test status
Simulation time 1519827569 ps
CPU time 2.45 seconds
Started Mar 28 01:46:56 PM PDT 24
Finished Mar 28 01:46:58 PM PDT 24
Peak memory 199124 kb
Host smart-6695d05b-f58c-4bb6-b1f5-ce73932e994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553466354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2553466354
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2767390419
Short name T573
Test name
Test status
Simulation time 89211690635 ps
CPU time 39.13 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:37 PM PDT 24
Peak memory 200488 kb
Host smart-6476aad3-25d9-4140-8678-09e85e1217a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767390419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2767390419
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1489852201
Short name T335
Test name
Test status
Simulation time 37181771 ps
CPU time 0.6 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:47:11 PM PDT 24
Peak memory 195904 kb
Host smart-d8cd350e-28c6-4333-bdc6-53e1d58162b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489852201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1489852201
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3326727207
Short name T860
Test name
Test status
Simulation time 108854000594 ps
CPU time 41.99 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:40 PM PDT 24
Peak memory 200436 kb
Host smart-d85a5faf-b2d1-4b7d-b9d9-164b9044d527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326727207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3326727207
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.252024257
Short name T870
Test name
Test status
Simulation time 99566586767 ps
CPU time 83.02 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:48:15 PM PDT 24
Peak memory 200464 kb
Host smart-3b7770ce-700f-4ca2-9708-c9926cfe2a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252024257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.252024257
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.4156517204
Short name T944
Test name
Test status
Simulation time 48231917486 ps
CPU time 103.97 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:48:36 PM PDT 24
Peak memory 200520 kb
Host smart-c7bc9634-ffed-42ac-81cb-c213dea597a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156517204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.4156517204
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3155813888
Short name T451
Test name
Test status
Simulation time 33703653496 ps
CPU time 47.56 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:45 PM PDT 24
Peak memory 199604 kb
Host smart-2537d9ea-a74c-47c1-bb73-e701f3540878
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155813888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3155813888
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.693605446
Short name T767
Test name
Test status
Simulation time 101918770604 ps
CPU time 554.95 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:56:12 PM PDT 24
Peak memory 200448 kb
Host smart-b66217c6-74a0-4c1e-8d24-e400db699a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693605446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.693605446
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1707468817
Short name T752
Test name
Test status
Simulation time 2378123722 ps
CPU time 4.96 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:03 PM PDT 24
Peak memory 197960 kb
Host smart-046cb786-ca90-4deb-b6cc-6657a50f9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707468817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1707468817
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2165992723
Short name T446
Test name
Test status
Simulation time 36959610192 ps
CPU time 29.73 seconds
Started Mar 28 01:46:49 PM PDT 24
Finished Mar 28 01:47:19 PM PDT 24
Peak memory 199536 kb
Host smart-2191f159-7d2a-425c-b03a-db2577c76168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165992723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2165992723
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1184570105
Short name T1001
Test name
Test status
Simulation time 28530864569 ps
CPU time 137.6 seconds
Started Mar 28 01:46:57 PM PDT 24
Finished Mar 28 01:49:15 PM PDT 24
Peak memory 200112 kb
Host smart-9b51a00e-deb8-421e-951b-a0fb0200cbb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184570105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1184570105
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2137274339
Short name T947
Test name
Test status
Simulation time 6912585727 ps
CPU time 63.08 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:47:55 PM PDT 24
Peak memory 199852 kb
Host smart-8770621b-c351-408d-af0e-254cde971286
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137274339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2137274339
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.814214856
Short name T968
Test name
Test status
Simulation time 22134159843 ps
CPU time 38.51 seconds
Started Mar 28 01:46:54 PM PDT 24
Finished Mar 28 01:47:32 PM PDT 24
Peak memory 200464 kb
Host smart-c6c0ce08-4a1c-43b2-a9a7-4c5ad8e2f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814214856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.814214856
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.898637518
Short name T1012
Test name
Test status
Simulation time 5959378352 ps
CPU time 5.43 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:46:57 PM PDT 24
Peak memory 196532 kb
Host smart-b71011b6-be8b-4099-a720-9c21c9bfc8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898637518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.898637518
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3783089683
Short name T280
Test name
Test status
Simulation time 11636238700 ps
CPU time 40.25 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:47:39 PM PDT 24
Peak memory 200016 kb
Host smart-3c6462a2-4934-4709-994b-ac4580306f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783089683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3783089683
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2045784420
Short name T212
Test name
Test status
Simulation time 374469517482 ps
CPU time 304.16 seconds
Started Mar 28 01:47:05 PM PDT 24
Finished Mar 28 01:52:10 PM PDT 24
Peak memory 200784 kb
Host smart-05785439-db11-4c59-969e-b253c22c0e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045784420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2045784420
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.75440700
Short name T995
Test name
Test status
Simulation time 19856478719 ps
CPU time 13.26 seconds
Started Mar 28 01:46:52 PM PDT 24
Finished Mar 28 01:47:05 PM PDT 24
Peak memory 200460 kb
Host smart-d190e822-f250-4185-94fe-a4287d701013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75440700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.75440700
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2116972600
Short name T305
Test name
Test status
Simulation time 138447835751 ps
CPU time 109.48 seconds
Started Mar 28 01:46:58 PM PDT 24
Finished Mar 28 01:48:48 PM PDT 24
Peak memory 200464 kb
Host smart-54df6a6c-a425-4289-917c-47af9fabbea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116972600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2116972600
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3960023524
Short name T758
Test name
Test status
Simulation time 41361662 ps
CPU time 0.56 seconds
Started Mar 28 01:47:08 PM PDT 24
Finished Mar 28 01:47:09 PM PDT 24
Peak memory 195872 kb
Host smart-89f8a2eb-0ffe-4d48-9973-4464c3da3fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960023524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3960023524
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1788441441
Short name T121
Test name
Test status
Simulation time 81788280457 ps
CPU time 55.17 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 01:48:02 PM PDT 24
Peak memory 200508 kb
Host smart-09ffeae9-67e3-46dc-92cf-b90e24c9c6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788441441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1788441441
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.675774299
Short name T166
Test name
Test status
Simulation time 52235825710 ps
CPU time 99.49 seconds
Started Mar 28 01:47:04 PM PDT 24
Finished Mar 28 01:48:44 PM PDT 24
Peak memory 200412 kb
Host smart-bc96723d-3032-4dd8-8d89-c6c17ec3d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675774299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.675774299
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.227450941
Short name T320
Test name
Test status
Simulation time 24399753884 ps
CPU time 41.97 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:49 PM PDT 24
Peak memory 200088 kb
Host smart-6d6e292e-6009-4b9c-89d2-febd7a4b583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227450941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.227450941
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3323855180
Short name T428
Test name
Test status
Simulation time 11962902869 ps
CPU time 45.44 seconds
Started Mar 28 01:47:10 PM PDT 24
Finished Mar 28 01:47:56 PM PDT 24
Peak memory 200088 kb
Host smart-757aa7e2-b1ed-41a1-8483-bc20ab618b5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323855180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3323855180
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.890592961
Short name T691
Test name
Test status
Simulation time 153399482470 ps
CPU time 412.21 seconds
Started Mar 28 01:47:08 PM PDT 24
Finished Mar 28 01:54:01 PM PDT 24
Peak memory 200436 kb
Host smart-9e161699-a58b-44ee-9884-0ce18001a85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890592961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.890592961
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.762973414
Short name T810
Test name
Test status
Simulation time 4085246266 ps
CPU time 7.26 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:15 PM PDT 24
Peak memory 199824 kb
Host smart-fcd77e4b-4c34-42a0-ac93-028be8c8ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762973414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.762973414
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1220219200
Short name T315
Test name
Test status
Simulation time 72185378212 ps
CPU time 63.77 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:48:11 PM PDT 24
Peak memory 200388 kb
Host smart-58fbeb7e-3ed3-40e8-8cdb-c9099544be1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220219200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1220219200
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2409475177
Short name T985
Test name
Test status
Simulation time 29613578785 ps
CPU time 937.74 seconds
Started Mar 28 01:47:05 PM PDT 24
Finished Mar 28 02:02:43 PM PDT 24
Peak memory 200472 kb
Host smart-daf59e9a-8ada-4f2b-83f1-749fc246ce6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409475177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2409475177
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2534018492
Short name T815
Test name
Test status
Simulation time 2819292113 ps
CPU time 13.07 seconds
Started Mar 28 01:47:04 PM PDT 24
Finished Mar 28 01:47:17 PM PDT 24
Peak memory 198264 kb
Host smart-3ae5e6d0-b43d-447b-8181-2de1e9406de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534018492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2534018492
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.968293063
Short name T413
Test name
Test status
Simulation time 243741573161 ps
CPU time 39.11 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:47:52 PM PDT 24
Peak memory 200284 kb
Host smart-966bb053-9cf6-4885-8a6c-7e53d828466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968293063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.968293063
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.103282791
Short name T1078
Test name
Test status
Simulation time 41700039014 ps
CPU time 62.5 seconds
Started Mar 28 01:47:05 PM PDT 24
Finished Mar 28 01:48:08 PM PDT 24
Peak memory 196232 kb
Host smart-3b234eac-a907-40cd-afaa-c2860f749e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103282791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.103282791
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2352516484
Short name T506
Test name
Test status
Simulation time 99242582 ps
CPU time 0.95 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 01:47:07 PM PDT 24
Peak memory 199656 kb
Host smart-32c9d4d9-4d92-499f-a5e5-34ffc9dd3527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352516484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2352516484
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1861046291
Short name T35
Test name
Test status
Simulation time 715422217407 ps
CPU time 95.6 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:48:42 PM PDT 24
Peak memory 200868 kb
Host smart-9b3d74d3-e2d9-484b-ba4a-ee16e88efee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861046291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1861046291
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.626402795
Short name T134
Test name
Test status
Simulation time 122364813992 ps
CPU time 809.38 seconds
Started Mar 28 01:47:08 PM PDT 24
Finished Mar 28 02:00:38 PM PDT 24
Peak memory 216972 kb
Host smart-48d0e68c-294d-4bee-b16e-d8114921274b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626402795 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.626402795
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2118381740
Short name T436
Test name
Test status
Simulation time 7153317149 ps
CPU time 20.21 seconds
Started Mar 28 01:47:04 PM PDT 24
Finished Mar 28 01:47:25 PM PDT 24
Peak memory 200444 kb
Host smart-befc154d-ab01-4cd9-b06f-621e0a1d70bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118381740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2118381740
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1628583217
Short name T975
Test name
Test status
Simulation time 94648144120 ps
CPU time 18.6 seconds
Started Mar 28 01:47:05 PM PDT 24
Finished Mar 28 01:47:24 PM PDT 24
Peak memory 200420 kb
Host smart-f3215713-48d5-443f-8ff4-6881925e6f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628583217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1628583217
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.366009794
Short name T522
Test name
Test status
Simulation time 64080476 ps
CPU time 0.54 seconds
Started Mar 28 01:47:08 PM PDT 24
Finished Mar 28 01:47:08 PM PDT 24
Peak memory 195884 kb
Host smart-e81df7b5-d22b-4779-a0f2-1f3d3f47b206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366009794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.366009794
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.824708910
Short name T261
Test name
Test status
Simulation time 48911899909 ps
CPU time 82.08 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 01:48:28 PM PDT 24
Peak memory 200412 kb
Host smart-f9f96f24-f572-480c-bd82-45b5d9417d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824708910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.824708910
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4212836314
Short name T707
Test name
Test status
Simulation time 115991033408 ps
CPU time 53.35 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 01:48:00 PM PDT 24
Peak memory 200440 kb
Host smart-111522c6-743f-4c74-b908-36c94274b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212836314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4212836314
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2879084547
Short name T1
Test name
Test status
Simulation time 11301263690 ps
CPU time 20.12 seconds
Started Mar 28 01:47:11 PM PDT 24
Finished Mar 28 01:47:32 PM PDT 24
Peak memory 200372 kb
Host smart-e70ef8d3-5095-4ff1-9154-40ebab99a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879084547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2879084547
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3308704318
Short name T1140
Test name
Test status
Simulation time 26271854886 ps
CPU time 11.46 seconds
Started Mar 28 01:47:11 PM PDT 24
Finished Mar 28 01:47:23 PM PDT 24
Peak memory 200540 kb
Host smart-2afdf0fa-c783-435a-a7b4-aa1c0f920f94
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308704318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3308704318
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3720047537
Short name T804
Test name
Test status
Simulation time 100615559522 ps
CPU time 180.62 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:50:13 PM PDT 24
Peak memory 200488 kb
Host smart-d986ff34-65cf-4715-bd26-19510a786568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720047537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3720047537
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2873388933
Short name T88
Test name
Test status
Simulation time 3744184777 ps
CPU time 6.93 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:47:16 PM PDT 24
Peak memory 198856 kb
Host smart-09aeaebf-9df6-40fa-aafb-1fc581b847f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873388933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2873388933
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2032559762
Short name T1087
Test name
Test status
Simulation time 299401169094 ps
CPU time 78.87 seconds
Started Mar 28 01:47:10 PM PDT 24
Finished Mar 28 01:48:29 PM PDT 24
Peak memory 200660 kb
Host smart-360f1dcf-cb03-422e-98e9-bd2b41f035c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032559762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2032559762
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.614280818
Short name T807
Test name
Test status
Simulation time 18088248412 ps
CPU time 680.72 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:58:30 PM PDT 24
Peak memory 200504 kb
Host smart-972d904d-f3c7-4710-bf02-84edf88b4c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614280818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.614280818
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1795509204
Short name T806
Test name
Test status
Simulation time 3515539314 ps
CPU time 3 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 01:47:09 PM PDT 24
Peak memory 198772 kb
Host smart-b69a116a-57c0-464e-99d6-670aab5377cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795509204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1795509204
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1323975362
Short name T773
Test name
Test status
Simulation time 4550809253 ps
CPU time 1.41 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:08 PM PDT 24
Peak memory 196644 kb
Host smart-7536383a-4ca2-478e-8acd-19cb63693e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323975362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1323975362
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1911690417
Short name T438
Test name
Test status
Simulation time 884007891 ps
CPU time 3.95 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:11 PM PDT 24
Peak memory 200324 kb
Host smart-b57a1fcc-1079-4e02-a31f-1ef86e49589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911690417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1911690417
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.662754108
Short name T722
Test name
Test status
Simulation time 179031540219 ps
CPU time 76.86 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:48:30 PM PDT 24
Peak memory 200452 kb
Host smart-286010e7-f0f0-4f5f-bfb6-f7a8b15d7247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662754108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.662754108
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1515275007
Short name T129
Test name
Test status
Simulation time 8715252267 ps
CPU time 108.07 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:49:01 PM PDT 24
Peak memory 208664 kb
Host smart-5cbacee6-81ea-4745-8e7f-4a562c18816e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515275007 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1515275007
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2476097778
Short name T285
Test name
Test status
Simulation time 666956390 ps
CPU time 1.74 seconds
Started Mar 28 01:47:10 PM PDT 24
Finished Mar 28 01:47:12 PM PDT 24
Peak memory 199984 kb
Host smart-29fd8211-3fbd-4b9c-aacb-8a907b5a5cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476097778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2476097778
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2657337942
Short name T490
Test name
Test status
Simulation time 51085257158 ps
CPU time 49.59 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 01:47:56 PM PDT 24
Peak memory 200524 kb
Host smart-0e5288d3-5702-442b-af52-f063ed05aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657337942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2657337942
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2625326436
Short name T935
Test name
Test status
Simulation time 13094790 ps
CPU time 0.56 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:07 PM PDT 24
Peak memory 195900 kb
Host smart-deb8dd3b-ee73-4cce-96bd-b439a1d300be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625326436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2625326436
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1841349296
Short name T918
Test name
Test status
Simulation time 92353917044 ps
CPU time 50.76 seconds
Started Mar 28 01:47:08 PM PDT 24
Finished Mar 28 01:47:59 PM PDT 24
Peak memory 200484 kb
Host smart-bab97411-581a-43f2-b2c7-73ab53d3238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841349296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1841349296
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.4132180087
Short name T686
Test name
Test status
Simulation time 98531130673 ps
CPU time 38 seconds
Started Mar 28 01:47:08 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 200488 kb
Host smart-6241298c-a031-4071-ba1d-2e8a77fff2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132180087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.4132180087
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2367943287
Short name T590
Test name
Test status
Simulation time 66061075723 ps
CPU time 34.54 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:47:47 PM PDT 24
Peak memory 200472 kb
Host smart-c15d8493-f9f1-45ed-b8e0-1781ae640872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367943287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2367943287
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3078427756
Short name T873
Test name
Test status
Simulation time 15482779450 ps
CPU time 25.92 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:47:39 PM PDT 24
Peak memory 199568 kb
Host smart-9f994a33-c7c8-457a-996a-d92f68301851
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078427756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3078427756
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.505648015
Short name T775
Test name
Test status
Simulation time 106111697903 ps
CPU time 233.54 seconds
Started Mar 28 01:47:05 PM PDT 24
Finished Mar 28 01:50:58 PM PDT 24
Peak memory 200408 kb
Host smart-3f641d17-492a-4d18-a81e-b1bdf5fdc736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505648015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.505648015
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3601694959
Short name T770
Test name
Test status
Simulation time 8116600083 ps
CPU time 6.04 seconds
Started Mar 28 01:47:11 PM PDT 24
Finished Mar 28 01:47:18 PM PDT 24
Peak memory 199836 kb
Host smart-8d968580-47de-4ce6-805b-a7709fad1140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601694959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3601694959
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1346990922
Short name T559
Test name
Test status
Simulation time 111797489295 ps
CPU time 188.18 seconds
Started Mar 28 01:47:10 PM PDT 24
Finished Mar 28 01:50:18 PM PDT 24
Peak memory 200908 kb
Host smart-10b79d95-1376-409e-8702-54c6fb3532d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346990922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1346990922
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.438910363
Short name T341
Test name
Test status
Simulation time 12021030999 ps
CPU time 169.85 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:50:00 PM PDT 24
Peak memory 200600 kb
Host smart-2fac38f5-1b8d-40cc-9c81-73419d4a0788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438910363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.438910363
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.965537650
Short name T675
Test name
Test status
Simulation time 4300681251 ps
CPU time 29.03 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:47:42 PM PDT 24
Peak memory 199176 kb
Host smart-eb737454-cddf-4272-909e-2cee2fd3ff11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965537650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.965537650
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2003725958
Short name T984
Test name
Test status
Simulation time 81476902123 ps
CPU time 33.14 seconds
Started Mar 28 01:47:12 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 200428 kb
Host smart-3b344150-0eb2-4514-8a11-792eb660ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003725958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2003725958
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3203568505
Short name T671
Test name
Test status
Simulation time 3018407698 ps
CPU time 1.96 seconds
Started Mar 28 01:47:11 PM PDT 24
Finished Mar 28 01:47:14 PM PDT 24
Peak memory 196520 kb
Host smart-534f863e-56c4-4e3f-811f-800bd9b8ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203568505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3203568505
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.67756072
Short name T1007
Test name
Test status
Simulation time 520696407 ps
CPU time 1.33 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:47:11 PM PDT 24
Peak memory 199360 kb
Host smart-4f2a668e-7e33-4902-aa62-d1099cf1275a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67756072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.67756072
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.804681520
Short name T328
Test name
Test status
Simulation time 209751089930 ps
CPU time 176.03 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:50:05 PM PDT 24
Peak memory 200480 kb
Host smart-22058fb0-76b4-444f-a56a-d747870c9068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804681520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.804681520
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1820712251
Short name T1049
Test name
Test status
Simulation time 55990770234 ps
CPU time 183 seconds
Started Mar 28 01:47:04 PM PDT 24
Finished Mar 28 01:50:07 PM PDT 24
Peak memory 215932 kb
Host smart-31e63c6a-7f09-4c88-8e32-65c9e8d2d456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820712251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1820712251
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3820216484
Short name T345
Test name
Test status
Simulation time 907134535 ps
CPU time 1.73 seconds
Started Mar 28 01:47:11 PM PDT 24
Finished Mar 28 01:47:14 PM PDT 24
Peak memory 198328 kb
Host smart-6b72b5f3-d8ba-4747-9bd4-bd31da45e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820216484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3820216484
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.348871187
Short name T653
Test name
Test status
Simulation time 8354365588 ps
CPU time 11.93 seconds
Started Mar 28 01:47:08 PM PDT 24
Finished Mar 28 01:47:20 PM PDT 24
Peak memory 200436 kb
Host smart-c77612a9-c482-4b57-be2b-2279803c53f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348871187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.348871187
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1062808345
Short name T674
Test name
Test status
Simulation time 22524418 ps
CPU time 0.54 seconds
Started Mar 28 01:47:34 PM PDT 24
Finished Mar 28 01:47:35 PM PDT 24
Peak memory 194852 kb
Host smart-2ff530e8-c758-46eb-ab31-8a6a0ef231c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062808345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1062808345
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2726026082
Short name T956
Test name
Test status
Simulation time 168616899358 ps
CPU time 67.95 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:48:17 PM PDT 24
Peak memory 200464 kb
Host smart-d3677967-be75-4a3d-960b-8348d69b8ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726026082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2726026082
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1543907436
Short name T536
Test name
Test status
Simulation time 54672369382 ps
CPU time 116.22 seconds
Started Mar 28 01:47:05 PM PDT 24
Finished Mar 28 01:49:02 PM PDT 24
Peak memory 200496 kb
Host smart-9d6522c3-7d20-4156-949a-e98eb22d4b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543907436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1543907436
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.794394601
Short name T127
Test name
Test status
Simulation time 121162439666 ps
CPU time 93.11 seconds
Started Mar 28 01:47:03 PM PDT 24
Finished Mar 28 01:48:36 PM PDT 24
Peak memory 200480 kb
Host smart-aaeeaead-9bbd-4324-9429-0c8945fd3a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794394601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.794394601
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3911609369
Short name T917
Test name
Test status
Simulation time 246368380025 ps
CPU time 126.4 seconds
Started Mar 28 01:47:09 PM PDT 24
Finished Mar 28 01:49:15 PM PDT 24
Peak memory 200460 kb
Host smart-83273279-16fe-4efa-b9e1-2a1c054752cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911609369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3911609369
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4053189020
Short name T9
Test name
Test status
Simulation time 177084173621 ps
CPU time 378.02 seconds
Started Mar 28 01:47:22 PM PDT 24
Finished Mar 28 01:53:40 PM PDT 24
Peak memory 200376 kb
Host smart-5376bbe5-15a6-4493-8a50-5da86838175a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053189020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4053189020
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.809912309
Short name T450
Test name
Test status
Simulation time 8568021246 ps
CPU time 7.05 seconds
Started Mar 28 01:47:26 PM PDT 24
Finished Mar 28 01:47:34 PM PDT 24
Peak memory 200240 kb
Host smart-4503ace0-c768-4e15-bca6-fe6a95835b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809912309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.809912309
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.31310479
Short name T875
Test name
Test status
Simulation time 15740177571 ps
CPU time 190.02 seconds
Started Mar 28 01:47:36 PM PDT 24
Finished Mar 28 01:50:48 PM PDT 24
Peak memory 200536 kb
Host smart-11b8f955-4188-4e34-aa92-737c39243c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31310479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.31310479
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3367763495
Short name T15
Test name
Test status
Simulation time 5265612576 ps
CPU time 11.11 seconds
Started Mar 28 01:47:06 PM PDT 24
Finished Mar 28 01:47:17 PM PDT 24
Peak memory 199592 kb
Host smart-2b8876b2-da95-4dee-b38d-d8b692f20ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367763495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3367763495
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3375347462
Short name T882
Test name
Test status
Simulation time 42030979667 ps
CPU time 32.95 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:40 PM PDT 24
Peak memory 200452 kb
Host smart-6b860e3b-1fef-4ab7-8b11-3bab84cf951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375347462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3375347462
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3878325428
Short name T554
Test name
Test status
Simulation time 550859247 ps
CPU time 1.12 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:08 PM PDT 24
Peak memory 195888 kb
Host smart-3745c53a-13dc-4a28-893b-787be4aa463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878325428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3878325428
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2612143222
Short name T455
Test name
Test status
Simulation time 845966413 ps
CPU time 3.35 seconds
Started Mar 28 01:47:07 PM PDT 24
Finished Mar 28 01:47:10 PM PDT 24
Peak memory 199932 kb
Host smart-ce68d4fe-3327-4922-8ba7-a67384a3d436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612143222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2612143222
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1871342892
Short name T859
Test name
Test status
Simulation time 61818345372 ps
CPU time 168.59 seconds
Started Mar 28 01:47:27 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 200760 kb
Host smart-5778502b-bbac-41d2-a71b-d8d5e9d99be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871342892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1871342892
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1150837310
Short name T1131
Test name
Test status
Simulation time 39088283520 ps
CPU time 444.61 seconds
Started Mar 28 01:47:24 PM PDT 24
Finished Mar 28 01:54:49 PM PDT 24
Peak memory 216940 kb
Host smart-14f04891-cce4-45b9-bde4-ab39bfb579ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150837310 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1150837310
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2730021510
Short name T276
Test name
Test status
Simulation time 7036709074 ps
CPU time 19.84 seconds
Started Mar 28 01:47:22 PM PDT 24
Finished Mar 28 01:47:42 PM PDT 24
Peak memory 200292 kb
Host smart-273b8951-5b2a-4b38-a090-919a5546d426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730021510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2730021510
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1933096124
Short name T508
Test name
Test status
Simulation time 28250608581 ps
CPU time 14.3 seconds
Started Mar 28 01:47:05 PM PDT 24
Finished Mar 28 01:47:20 PM PDT 24
Peak memory 200216 kb
Host smart-fb1b2a36-9891-42eb-b445-b40bf5c39bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933096124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1933096124
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3977093886
Short name T351
Test name
Test status
Simulation time 36219000 ps
CPU time 0.55 seconds
Started Mar 28 01:47:24 PM PDT 24
Finished Mar 28 01:47:24 PM PDT 24
Peak memory 195876 kb
Host smart-b66de635-81b6-4e40-912a-64bf8b445113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977093886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3977093886
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.465598003
Short name T386
Test name
Test status
Simulation time 135546965808 ps
CPU time 106.26 seconds
Started Mar 28 01:47:26 PM PDT 24
Finished Mar 28 01:49:13 PM PDT 24
Peak memory 200476 kb
Host smart-8a59eacb-8dfb-4202-b4e5-df0a2b30e3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465598003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.465598003
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3632756372
Short name T44
Test name
Test status
Simulation time 171376550263 ps
CPU time 139.58 seconds
Started Mar 28 01:47:24 PM PDT 24
Finished Mar 28 01:49:44 PM PDT 24
Peak memory 200444 kb
Host smart-bfebcba6-43bf-49d0-bdf2-c2e9ced99b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632756372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3632756372
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.185597220
Short name T829
Test name
Test status
Simulation time 15179685123 ps
CPU time 23.38 seconds
Started Mar 28 01:47:22 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 200528 kb
Host smart-cd182867-6ca7-4029-b402-56742824a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185597220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.185597220
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3035803170
Short name T392
Test name
Test status
Simulation time 11117407185 ps
CPU time 5.93 seconds
Started Mar 28 01:47:26 PM PDT 24
Finished Mar 28 01:47:33 PM PDT 24
Peak memory 200484 kb
Host smart-596623d5-12cb-400d-8e35-7a900790948b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035803170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3035803170
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.454051797
Short name T407
Test name
Test status
Simulation time 116242116373 ps
CPU time 521.71 seconds
Started Mar 28 01:47:23 PM PDT 24
Finished Mar 28 01:56:05 PM PDT 24
Peak memory 200560 kb
Host smart-8886a348-8b03-4595-972f-6389db06e778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454051797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.454051797
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3356041814
Short name T337
Test name
Test status
Simulation time 6333153006 ps
CPU time 12.62 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 199560 kb
Host smart-aec6d2ad-fb70-4b19-ba5b-b7cfd9610b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356041814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3356041814
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3998098497
Short name T497
Test name
Test status
Simulation time 54800187544 ps
CPU time 97.06 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:49:02 PM PDT 24
Peak memory 199368 kb
Host smart-6b89adf6-1b2b-429f-9427-1d4670ff0325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998098497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3998098497
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1436096098
Short name T866
Test name
Test status
Simulation time 15032776474 ps
CPU time 876.35 seconds
Started Mar 28 01:47:21 PM PDT 24
Finished Mar 28 02:01:58 PM PDT 24
Peak memory 200452 kb
Host smart-80cf567b-2ce7-4d57-bd75-a13ee0597369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436096098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1436096098
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2099084403
Short name T92
Test name
Test status
Simulation time 5112505610 ps
CPU time 11.43 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 199568 kb
Host smart-10d7191b-d6a1-4f40-8296-77b0d9900194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099084403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2099084403
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3112266718
Short name T633
Test name
Test status
Simulation time 20163522650 ps
CPU time 30.73 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:48:07 PM PDT 24
Peak memory 198924 kb
Host smart-751c7d32-0b65-4eeb-8b6b-ac363b31f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112266718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3112266718
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1877828087
Short name T293
Test name
Test status
Simulation time 40883645674 ps
CPU time 15.94 seconds
Started Mar 28 01:47:21 PM PDT 24
Finished Mar 28 01:47:37 PM PDT 24
Peak memory 196220 kb
Host smart-d36e41de-8aa2-4a42-b3b1-773affc31716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877828087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1877828087
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2238254574
Short name T1142
Test name
Test status
Simulation time 701389757 ps
CPU time 2.67 seconds
Started Mar 28 01:47:26 PM PDT 24
Finished Mar 28 01:47:29 PM PDT 24
Peak memory 198784 kb
Host smart-02c7c094-f55d-4a0e-bddb-261a36f1f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238254574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2238254574
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3080521982
Short name T862
Test name
Test status
Simulation time 340357723580 ps
CPU time 256.33 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:51:42 PM PDT 24
Peak memory 208752 kb
Host smart-74c47288-374a-45c4-a45e-4479cef96401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080521982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3080521982
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2908298203
Short name T314
Test name
Test status
Simulation time 22647200001 ps
CPU time 521.47 seconds
Started Mar 28 01:47:36 PM PDT 24
Finished Mar 28 01:56:18 PM PDT 24
Peak memory 217108 kb
Host smart-d86ee66c-0584-499c-b58a-7f0acdec5aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908298203 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2908298203
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.928422620
Short name T1114
Test name
Test status
Simulation time 847065122 ps
CPU time 2.26 seconds
Started Mar 28 01:47:37 PM PDT 24
Finished Mar 28 01:47:40 PM PDT 24
Peak memory 198624 kb
Host smart-8ca7116f-8d2c-432f-a7ce-0f93210a4808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928422620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.928422620
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.359972294
Short name T1057
Test name
Test status
Simulation time 35377647077 ps
CPU time 14.42 seconds
Started Mar 28 01:47:23 PM PDT 24
Finished Mar 28 01:47:37 PM PDT 24
Peak memory 200332 kb
Host smart-4de750c0-5f4d-4451-9d80-80ee8fad9b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359972294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.359972294
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1746768227
Short name T769
Test name
Test status
Simulation time 14872022 ps
CPU time 0.56 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:47:26 PM PDT 24
Peak memory 195908 kb
Host smart-7c3359c7-eed0-4dbe-9c8c-de61ae58340b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746768227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1746768227
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2073784612
Short name T101
Test name
Test status
Simulation time 38970414031 ps
CPU time 35.5 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:48:10 PM PDT 24
Peak memory 200456 kb
Host smart-7657308a-5fdc-4829-ade6-3937d9ecc9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073784612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2073784612
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3745627414
Short name T824
Test name
Test status
Simulation time 16542217563 ps
CPU time 16.25 seconds
Started Mar 28 01:47:36 PM PDT 24
Finished Mar 28 01:47:54 PM PDT 24
Peak memory 200256 kb
Host smart-66e1f221-595a-4f55-919f-b05cfcba63cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745627414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3745627414
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4100121882
Short name T582
Test name
Test status
Simulation time 87855089337 ps
CPU time 35.43 seconds
Started Mar 28 01:47:21 PM PDT 24
Finished Mar 28 01:47:57 PM PDT 24
Peak memory 200492 kb
Host smart-4362e111-ad6d-4af1-8c2e-7631c7bba215
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100121882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4100121882
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1066262380
Short name T340
Test name
Test status
Simulation time 60659930267 ps
CPU time 241.53 seconds
Started Mar 28 01:47:21 PM PDT 24
Finished Mar 28 01:51:22 PM PDT 24
Peak memory 200448 kb
Host smart-1531ac64-30ea-4833-a07a-3287d48fea31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066262380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1066262380
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2850983128
Short name T813
Test name
Test status
Simulation time 5249949362 ps
CPU time 4.63 seconds
Started Mar 28 01:47:20 PM PDT 24
Finished Mar 28 01:47:25 PM PDT 24
Peak memory 200400 kb
Host smart-dd123ef9-1a2c-4475-853e-c17160f21106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850983128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2850983128
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.248460800
Short name T425
Test name
Test status
Simulation time 55135662323 ps
CPU time 112.76 seconds
Started Mar 28 01:47:36 PM PDT 24
Finished Mar 28 01:49:29 PM PDT 24
Peak memory 200784 kb
Host smart-7e631d3e-e432-4588-b6b4-a6d7cb1258c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248460800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.248460800
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3494200945
Short name T511
Test name
Test status
Simulation time 5189226674 ps
CPU time 230.46 seconds
Started Mar 28 01:47:23 PM PDT 24
Finished Mar 28 01:51:14 PM PDT 24
Peak memory 200440 kb
Host smart-48e7e152-f22f-4861-a12e-86d85753e61f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494200945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3494200945
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.980459869
Short name T1054
Test name
Test status
Simulation time 4855304907 ps
CPU time 18.06 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:47:43 PM PDT 24
Peak memory 199720 kb
Host smart-9a67062f-f83c-49eb-bf96-98bb8e0a3ffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980459869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.980459869
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2988344242
Short name T747
Test name
Test status
Simulation time 99172026117 ps
CPU time 33.51 seconds
Started Mar 28 01:47:21 PM PDT 24
Finished Mar 28 01:47:55 PM PDT 24
Peak memory 200436 kb
Host smart-a6f65a0c-5124-4405-9694-fac92a466131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988344242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2988344242
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3705185242
Short name T396
Test name
Test status
Simulation time 2082097427 ps
CPU time 2.63 seconds
Started Mar 28 01:47:24 PM PDT 24
Finished Mar 28 01:47:27 PM PDT 24
Peak memory 195848 kb
Host smart-45b5e7b8-8f90-4dbe-9cd5-3c1a11e9246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705185242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3705185242
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3136867440
Short name T819
Test name
Test status
Simulation time 900063182 ps
CPU time 2.56 seconds
Started Mar 28 01:47:22 PM PDT 24
Finished Mar 28 01:47:25 PM PDT 24
Peak memory 199296 kb
Host smart-d09f693e-e9bc-4b27-aa83-16597fef8b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136867440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3136867440
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2766325734
Short name T685
Test name
Test status
Simulation time 256269760105 ps
CPU time 636.31 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:58:12 PM PDT 24
Peak memory 208924 kb
Host smart-749b9072-4c90-4c2a-908c-96d99481b769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766325734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2766325734
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1888391833
Short name T1187
Test name
Test status
Simulation time 178148465639 ps
CPU time 801.25 seconds
Started Mar 28 01:47:37 PM PDT 24
Finished Mar 28 02:00:59 PM PDT 24
Peak memory 217268 kb
Host smart-7b63d010-118f-4353-a2c4-2db96d678321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888391833 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1888391833
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.830265808
Short name T1061
Test name
Test status
Simulation time 1583893359 ps
CPU time 1.9 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:47:27 PM PDT 24
Peak memory 199472 kb
Host smart-c6534a24-88ed-4c7a-b70f-83838da87ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830265808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.830265808
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3917857194
Short name T510
Test name
Test status
Simulation time 54358738601 ps
CPU time 62.84 seconds
Started Mar 28 01:47:36 PM PDT 24
Finished Mar 28 01:48:41 PM PDT 24
Peak memory 200500 kb
Host smart-243ba3df-d994-4e00-81e8-cfe617855741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917857194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3917857194
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4014047319
Short name T620
Test name
Test status
Simulation time 42708642 ps
CPU time 0.56 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:47:26 PM PDT 24
Peak memory 195840 kb
Host smart-19a196e7-1fb0-4bd7-8368-f1f4676f0aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014047319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4014047319
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.492739302
Short name T138
Test name
Test status
Simulation time 17242935973 ps
CPU time 9.52 seconds
Started Mar 28 01:47:34 PM PDT 24
Finished Mar 28 01:47:44 PM PDT 24
Peak memory 200500 kb
Host smart-f5f856c4-11e3-4e97-a668-3de12c669296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492739302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.492739302
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3259567690
Short name T502
Test name
Test status
Simulation time 185342194432 ps
CPU time 104.03 seconds
Started Mar 28 01:47:22 PM PDT 24
Finished Mar 28 01:49:06 PM PDT 24
Peak memory 200480 kb
Host smart-846a56ea-52de-49e9-a0f6-56c1d1b625d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259567690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3259567690
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2309518937
Short name T964
Test name
Test status
Simulation time 13134666944 ps
CPU time 11.17 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 200200 kb
Host smart-5c16f63e-6218-47b9-bb3e-9b98f4ab8838
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309518937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2309518937
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1592534221
Short name T38
Test name
Test status
Simulation time 101305441565 ps
CPU time 955.4 seconds
Started Mar 28 01:47:34 PM PDT 24
Finished Mar 28 02:03:30 PM PDT 24
Peak memory 200412 kb
Host smart-f640d63d-f7c8-4c2d-afe3-c319616220e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592534221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1592534221
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.279456604
Short name T333
Test name
Test status
Simulation time 248072185 ps
CPU time 0.67 seconds
Started Mar 28 01:47:22 PM PDT 24
Finished Mar 28 01:47:23 PM PDT 24
Peak memory 196368 kb
Host smart-3196ba0e-1226-4a8c-8c1f-4abde98fe6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279456604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.279456604
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.497715927
Short name T925
Test name
Test status
Simulation time 133858883089 ps
CPU time 145.74 seconds
Started Mar 28 01:47:24 PM PDT 24
Finished Mar 28 01:49:50 PM PDT 24
Peak memory 200852 kb
Host smart-bba53b34-e9de-4a8a-8b51-17e51e47b360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497715927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.497715927
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2280843646
Short name T901
Test name
Test status
Simulation time 11365288730 ps
CPU time 319.69 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:52:55 PM PDT 24
Peak memory 200404 kb
Host smart-5c955a0a-830f-4262-9a08-935264aaf6bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280843646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2280843646
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4285168158
Short name T481
Test name
Test status
Simulation time 3790943166 ps
CPU time 32.04 seconds
Started Mar 28 01:47:20 PM PDT 24
Finished Mar 28 01:47:52 PM PDT 24
Peak memory 199448 kb
Host smart-9cccc787-3aa6-4e56-8e9c-0ce07d650aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285168158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4285168158
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.319954813
Short name T960
Test name
Test status
Simulation time 114102145442 ps
CPU time 173.74 seconds
Started Mar 28 01:47:22 PM PDT 24
Finished Mar 28 01:50:16 PM PDT 24
Peak memory 200316 kb
Host smart-c1b51eb5-544a-49d3-a35d-2bcde0026142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319954813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.319954813
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.4111193901
Short name T1041
Test name
Test status
Simulation time 44987048310 ps
CPU time 17.93 seconds
Started Mar 28 01:47:36 PM PDT 24
Finished Mar 28 01:47:55 PM PDT 24
Peak memory 196144 kb
Host smart-acc3e408-2d53-4bcd-915a-7f1f82fba351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111193901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.4111193901
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2146019104
Short name T640
Test name
Test status
Simulation time 657722357 ps
CPU time 1.87 seconds
Started Mar 28 01:47:26 PM PDT 24
Finished Mar 28 01:47:28 PM PDT 24
Peak memory 199248 kb
Host smart-87e1ee34-f72d-4d04-bf76-557afdf3aabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146019104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2146019104
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1124544688
Short name T579
Test name
Test status
Simulation time 129092204629 ps
CPU time 245.6 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:51:41 PM PDT 24
Peak memory 200500 kb
Host smart-258d45e8-8db1-4faa-8e3b-e099f94c9845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124544688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1124544688
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3147582675
Short name T397
Test name
Test status
Simulation time 4830156091 ps
CPU time 39.41 seconds
Started Mar 28 01:47:37 PM PDT 24
Finished Mar 28 01:48:16 PM PDT 24
Peak memory 208780 kb
Host smart-6ed3cd27-e858-430c-94ed-1aacdf529202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147582675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3147582675
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3379743583
Short name T1151
Test name
Test status
Simulation time 1239292507 ps
CPU time 2.49 seconds
Started Mar 28 01:47:21 PM PDT 24
Finished Mar 28 01:47:24 PM PDT 24
Peak memory 199084 kb
Host smart-2af70c9a-76d9-433c-a355-2e5047828bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379743583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3379743583
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2408427418
Short name T602
Test name
Test status
Simulation time 107701156294 ps
CPU time 176.85 seconds
Started Mar 28 01:47:23 PM PDT 24
Finished Mar 28 01:50:20 PM PDT 24
Peak memory 200432 kb
Host smart-80846779-47fd-49f9-89fe-183df75b0409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408427418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2408427418
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.697244813
Short name T419
Test name
Test status
Simulation time 12235518 ps
CPU time 0.57 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 195336 kb
Host smart-9ebf7f98-bce0-4d9f-821b-3ccc56707d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697244813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.697244813
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3705797756
Short name T943
Test name
Test status
Simulation time 76765867873 ps
CPU time 128.67 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:49:34 PM PDT 24
Peak memory 200428 kb
Host smart-20ee9491-1ed3-48f7-a9b2-3ddbf5fc4065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705797756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3705797756
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.6845254
Short name T448
Test name
Test status
Simulation time 76142329469 ps
CPU time 36.52 seconds
Started Mar 28 01:47:25 PM PDT 24
Finished Mar 28 01:48:02 PM PDT 24
Peak memory 200584 kb
Host smart-49f0695a-cdc2-4734-9ac6-c61d3cb84110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6845254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.6845254
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.1894825426
Short name T91
Test name
Test status
Simulation time 6480964888 ps
CPU time 3.67 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 197136 kb
Host smart-749cf223-3101-427c-8594-ad94f2d3b20f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894825426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1894825426
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.485140237
Short name T290
Test name
Test status
Simulation time 185271542189 ps
CPU time 1294.76 seconds
Started Mar 28 01:47:45 PM PDT 24
Finished Mar 28 02:09:21 PM PDT 24
Peak memory 200504 kb
Host smart-1d2bf74e-6617-409c-b759-9b0b3d9d4517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485140237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.485140237
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4130873650
Short name T45
Test name
Test status
Simulation time 5776441437 ps
CPU time 13.89 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:47:57 PM PDT 24
Peak memory 199380 kb
Host smart-f0155891-5325-4ae7-b61f-da63a215ef48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130873650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4130873650
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3883403757
Short name T403
Test name
Test status
Simulation time 146515307423 ps
CPU time 37.04 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:48:19 PM PDT 24
Peak memory 200016 kb
Host smart-f28a64d0-6fd0-4f85-93f8-1620833d27d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883403757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3883403757
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1977556576
Short name T259
Test name
Test status
Simulation time 24284128151 ps
CPU time 530.79 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:56:33 PM PDT 24
Peak memory 200480 kb
Host smart-94cc298a-9944-405a-8daf-4bdb803c9d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977556576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1977556576
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1022554242
Short name T1068
Test name
Test status
Simulation time 6347569000 ps
CPU time 11.16 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 199796 kb
Host smart-b925ffad-534b-4b0b-8cbc-92b923f5b46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022554242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1022554242
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3625106980
Short name T394
Test name
Test status
Simulation time 38904877768 ps
CPU time 17.67 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:47:59 PM PDT 24
Peak memory 200560 kb
Host smart-c1fed86b-2eb3-4401-b054-7107d0eb3ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625106980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3625106980
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1102240617
Short name T753
Test name
Test status
Simulation time 2504029270 ps
CPU time 1.71 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:47:47 PM PDT 24
Peak memory 196476 kb
Host smart-4ed73c99-3030-46ae-9cd8-60e7a63d6068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102240617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1102240617
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.260663659
Short name T464
Test name
Test status
Simulation time 415112493 ps
CPU time 1.6 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:47:37 PM PDT 24
Peak memory 200324 kb
Host smart-a730799d-8abb-49a5-8243-d88d5a011680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260663659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.260663659
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.4269777739
Short name T239
Test name
Test status
Simulation time 174005510840 ps
CPU time 61.14 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:48:45 PM PDT 24
Peak memory 200480 kb
Host smart-9cccf0ff-60a2-4c1c-8fcf-bdbeabbea12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269777739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4269777739
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.833742041
Short name T411
Test name
Test status
Simulation time 132881749800 ps
CPU time 920.9 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 02:03:05 PM PDT 24
Peak memory 216888 kb
Host smart-e73b9030-c506-4df4-a235-52e69d12a453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833742041 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.833742041
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3171163742
Short name T529
Test name
Test status
Simulation time 8326504495 ps
CPU time 9.04 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:47:51 PM PDT 24
Peak memory 199764 kb
Host smart-03139814-d460-43f9-9a55-0964423daf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171163742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3171163742
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2022894474
Short name T482
Test name
Test status
Simulation time 56522667440 ps
CPU time 19.36 seconds
Started Mar 28 01:47:35 PM PDT 24
Finished Mar 28 01:47:54 PM PDT 24
Peak memory 200412 kb
Host smart-1febf424-d251-437d-8774-750c388d8873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022894474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2022894474
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.61927985
Short name T916
Test name
Test status
Simulation time 13258008 ps
CPU time 0.6 seconds
Started Mar 28 01:45:08 PM PDT 24
Finished Mar 28 01:45:09 PM PDT 24
Peak memory 195320 kb
Host smart-934bb55b-254d-4bef-b26c-a87b014e439a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61927985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.61927985
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1442026060
Short name T692
Test name
Test status
Simulation time 156809401062 ps
CPU time 55.64 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:45:55 PM PDT 24
Peak memory 200516 kb
Host smart-8b841fb9-e6cb-4939-a604-33cc15e6b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442026060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1442026060
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.68190079
Short name T874
Test name
Test status
Simulation time 18142798994 ps
CPU time 32.97 seconds
Started Mar 28 01:44:56 PM PDT 24
Finished Mar 28 01:45:29 PM PDT 24
Peak memory 200488 kb
Host smart-98bf303d-1c15-4bfc-b23d-3af830761b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68190079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.68190079
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_intr.4198161495
Short name T1138
Test name
Test status
Simulation time 36137742147 ps
CPU time 52.58 seconds
Started Mar 28 01:44:59 PM PDT 24
Finished Mar 28 01:45:52 PM PDT 24
Peak memory 200244 kb
Host smart-ee951283-6786-49da-9b5a-c93f9f6375b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198161495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.4198161495
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3994881618
Short name T615
Test name
Test status
Simulation time 198591841572 ps
CPU time 1209.71 seconds
Started Mar 28 01:45:07 PM PDT 24
Finished Mar 28 02:05:17 PM PDT 24
Peak memory 200488 kb
Host smart-039faac3-de24-4886-a58a-8d3e5e5843f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994881618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3994881618
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4047348931
Short name T1065
Test name
Test status
Simulation time 6448085056 ps
CPU time 11.68 seconds
Started Mar 28 01:45:09 PM PDT 24
Finished Mar 28 01:45:21 PM PDT 24
Peak memory 199760 kb
Host smart-8b3fbae4-6eed-4330-8226-0147dc4314e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047348931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4047348931
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3674395234
Short name T270
Test name
Test status
Simulation time 22303947191 ps
CPU time 9.62 seconds
Started Mar 28 01:44:57 PM PDT 24
Finished Mar 28 01:45:06 PM PDT 24
Peak memory 197548 kb
Host smart-663708c7-186f-495e-b6e9-fabe6dc530ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674395234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3674395234
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1415188711
Short name T264
Test name
Test status
Simulation time 8284591334 ps
CPU time 223.27 seconds
Started Mar 28 01:45:08 PM PDT 24
Finished Mar 28 01:48:52 PM PDT 24
Peak memory 200360 kb
Host smart-46c890cc-f8ff-456f-81d9-e5fff051c380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415188711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1415188711
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4159175041
Short name T794
Test name
Test status
Simulation time 5136556706 ps
CPU time 46.76 seconds
Started Mar 28 01:44:59 PM PDT 24
Finished Mar 28 01:45:46 PM PDT 24
Peak memory 198668 kb
Host smart-16da2116-9637-4d44-8f25-77949d512da9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159175041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4159175041
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.618981017
Short name T4
Test name
Test status
Simulation time 25434333363 ps
CPU time 22.82 seconds
Started Mar 28 01:44:59 PM PDT 24
Finished Mar 28 01:45:22 PM PDT 24
Peak memory 200448 kb
Host smart-a865f7bd-9daf-47c6-b181-59c698e1e0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618981017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.618981017
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.427725493
Short name T288
Test name
Test status
Simulation time 1887669718 ps
CPU time 3.74 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:45:05 PM PDT 24
Peak memory 195848 kb
Host smart-12b67b31-136a-4508-b2da-04d1d4fc4f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427725493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.427725493
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1709841220
Short name T27
Test name
Test status
Simulation time 223389373 ps
CPU time 0.9 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:45:03 PM PDT 24
Peak memory 219092 kb
Host smart-3d4bf2ed-3a81-4bd5-99ac-938dbd809bac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709841220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1709841220
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1815142891
Short name T1117
Test name
Test status
Simulation time 5672809611 ps
CPU time 18.08 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:45:20 PM PDT 24
Peak memory 200132 kb
Host smart-4fa61eb3-131b-45db-a563-25fde6154034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815142891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1815142891
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2727092588
Short name T281
Test name
Test status
Simulation time 339574144214 ps
CPU time 633.74 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:55:35 PM PDT 24
Peak memory 208904 kb
Host smart-670bef97-9752-447f-a87b-2ffe1c3efdfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727092588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2727092588
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2184603086
Short name T952
Test name
Test status
Simulation time 135176463901 ps
CPU time 630.17 seconds
Started Mar 28 01:45:06 PM PDT 24
Finished Mar 28 01:55:37 PM PDT 24
Peak memory 225364 kb
Host smart-438922b0-3543-4e07-afcf-12cdc9457f1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184603086 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2184603086
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3358482278
Short name T959
Test name
Test status
Simulation time 744904400 ps
CPU time 2.37 seconds
Started Mar 28 01:45:03 PM PDT 24
Finished Mar 28 01:45:05 PM PDT 24
Peak memory 199264 kb
Host smart-6ae8aa4c-7eea-42a0-817a-189d5feff27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358482278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3358482278
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2242058409
Short name T383
Test name
Test status
Simulation time 55006375067 ps
CPU time 100.4 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:46:41 PM PDT 24
Peak memory 200484 kb
Host smart-bb3c31df-9e60-4094-9f52-6ae8e5635001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242058409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2242058409
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1167914759
Short name T468
Test name
Test status
Simulation time 198614909 ps
CPU time 0.55 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:47:45 PM PDT 24
Peak memory 195852 kb
Host smart-d4c26a57-2128-4d00-9441-15cae18bc3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167914759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1167914759
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3627029701
Short name T409
Test name
Test status
Simulation time 175981766532 ps
CPU time 549.99 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:56:55 PM PDT 24
Peak memory 200400 kb
Host smart-59f8359f-5788-494f-a3e0-d42d83edf8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627029701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3627029701
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3095438455
Short name T749
Test name
Test status
Simulation time 37659588553 ps
CPU time 16.87 seconds
Started Mar 28 01:47:47 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 200308 kb
Host smart-59648d9a-8c8e-4d16-9d46-905b8d21dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095438455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3095438455
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.966302755
Short name T1182
Test name
Test status
Simulation time 65230529936 ps
CPU time 101.33 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:49:27 PM PDT 24
Peak memory 200420 kb
Host smart-56cd3f33-3073-48e1-ba6f-c880a60ea9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966302755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.966302755
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2347951444
Short name T1085
Test name
Test status
Simulation time 10427612670 ps
CPU time 4.62 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:47:49 PM PDT 24
Peak memory 198420 kb
Host smart-0fdd7269-6285-4541-85a5-2657c2e23103
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347951444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2347951444
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1061201821
Short name T523
Test name
Test status
Simulation time 59865909597 ps
CPU time 143.97 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:50:08 PM PDT 24
Peak memory 200440 kb
Host smart-18a1876e-0988-41dd-b255-c0df302c69c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1061201821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1061201821
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.4225151255
Short name T494
Test name
Test status
Simulation time 1520014685 ps
CPU time 2.25 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 199140 kb
Host smart-c078d5d3-084e-4467-a246-0122941489fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225151255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4225151255
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1213093829
Short name T347
Test name
Test status
Simulation time 7692873672 ps
CPU time 13.37 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:47:56 PM PDT 24
Peak memory 198556 kb
Host smart-734ca2dc-bd3c-40ab-82d9-7721fa87a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213093829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1213093829
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1118484807
Short name T993
Test name
Test status
Simulation time 12388697463 ps
CPU time 356.66 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:53:38 PM PDT 24
Peak memory 200408 kb
Host smart-de26b6d0-d15c-4ace-ba57-a5323076b63a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118484807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1118484807
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.301688571
Short name T402
Test name
Test status
Simulation time 1393649015 ps
CPU time 1.26 seconds
Started Mar 28 01:47:40 PM PDT 24
Finished Mar 28 01:47:43 PM PDT 24
Peak memory 196144 kb
Host smart-3a00b410-43a2-4fbc-9f8b-d76e226ee3bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301688571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.301688571
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1746552755
Short name T881
Test name
Test status
Simulation time 105636219664 ps
CPU time 82.23 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:49:06 PM PDT 24
Peak memory 200472 kb
Host smart-52a27bb3-7b88-4dd3-8289-0474025b4e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746552755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1746552755
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.129490866
Short name T940
Test name
Test status
Simulation time 3773932158 ps
CPU time 2.18 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 196528 kb
Host smart-38931fe2-44b0-4803-951b-0265446ec2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129490866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.129490866
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.832144534
Short name T479
Test name
Test status
Simulation time 5666670377 ps
CPU time 25.14 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:48:07 PM PDT 24
Peak memory 199792 kb
Host smart-38cc1a0a-b2c0-4093-8f72-84bf85d48541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832144534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.832144534
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2932904797
Short name T1066
Test name
Test status
Simulation time 145451201518 ps
CPU time 262.89 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:52:05 PM PDT 24
Peak memory 200436 kb
Host smart-45819c64-5aa7-428e-a4af-4dfbcf863c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932904797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2932904797
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2156305092
Short name T452
Test name
Test status
Simulation time 61513823797 ps
CPU time 504.89 seconds
Started Mar 28 01:47:45 PM PDT 24
Finished Mar 28 01:56:11 PM PDT 24
Peak memory 215912 kb
Host smart-5a6399fd-1775-4845-a5f1-24814950b6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156305092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2156305092
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.415114091
Short name T472
Test name
Test status
Simulation time 1802483279 ps
CPU time 3.15 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:47:45 PM PDT 24
Peak memory 199984 kb
Host smart-9dc640e5-8925-4ed2-97bc-ac5ab7c1e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415114091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.415114091
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3271429190
Short name T577
Test name
Test status
Simulation time 64596129928 ps
CPU time 29.75 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:48:12 PM PDT 24
Peak memory 200412 kb
Host smart-4c293799-df9c-4c69-8d94-f8de35651904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271429190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3271429190
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2481051072
Short name T637
Test name
Test status
Simulation time 23329997 ps
CPU time 0.57 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 195840 kb
Host smart-264c21b1-93ad-4db6-9f43-88b2ad301d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481051072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2481051072
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1987009105
Short name T682
Test name
Test status
Simulation time 55686873989 ps
CPU time 22.97 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:48:05 PM PDT 24
Peak memory 200556 kb
Host smart-488b1c63-a49f-43c8-b2c3-c6adbee4e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987009105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1987009105
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2713752052
Short name T469
Test name
Test status
Simulation time 46133976931 ps
CPU time 10.03 seconds
Started Mar 28 01:47:41 PM PDT 24
Finished Mar 28 01:47:52 PM PDT 24
Peak memory 198856 kb
Host smart-5e8db734-237d-4bdb-a2c2-1a85139ccf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713752052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2713752052
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3645710501
Short name T567
Test name
Test status
Simulation time 106200693417 ps
CPU time 91.68 seconds
Started Mar 28 01:47:40 PM PDT 24
Finished Mar 28 01:49:14 PM PDT 24
Peak memory 200304 kb
Host smart-c84c045c-7b3d-4769-baec-d611a5c570af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645710501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3645710501
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3759499253
Short name T1018
Test name
Test status
Simulation time 37527938104 ps
CPU time 28.76 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:48:13 PM PDT 24
Peak memory 198364 kb
Host smart-a76b16b0-af4e-45f5-97e1-0daa7bb5b64d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759499253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3759499253
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1501013453
Short name T39
Test name
Test status
Simulation time 65533479247 ps
CPU time 410.72 seconds
Started Mar 28 01:47:40 PM PDT 24
Finished Mar 28 01:54:33 PM PDT 24
Peak memory 200508 kb
Host smart-45a856cf-59d7-427d-a9d8-4f9dba277e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501013453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1501013453
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.449449189
Short name T530
Test name
Test status
Simulation time 6638348843 ps
CPU time 8.05 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:47:52 PM PDT 24
Peak memory 200316 kb
Host smart-fbe4f62e-3021-4eac-aab8-a26bc34302d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449449189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.449449189
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1167298160
Short name T287
Test name
Test status
Simulation time 138950473860 ps
CPU time 254.55 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:51:59 PM PDT 24
Peak memory 200712 kb
Host smart-2a03eb63-9544-4374-ab09-dac4055c9733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167298160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1167298160
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1531583972
Short name T1053
Test name
Test status
Simulation time 30764181341 ps
CPU time 393.06 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:54:17 PM PDT 24
Peak memory 200432 kb
Host smart-cc741a82-adfe-4063-bc7f-e2365a18cddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531583972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1531583972
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.670674836
Short name T532
Test name
Test status
Simulation time 5469268733 ps
CPU time 11.48 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:47:57 PM PDT 24
Peak memory 199480 kb
Host smart-46c3ef55-a4ff-4710-8c57-7096300d3577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670674836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.670674836
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3066948709
Short name T945
Test name
Test status
Simulation time 15569594901 ps
CPU time 25.11 seconds
Started Mar 28 01:47:43 PM PDT 24
Finished Mar 28 01:48:09 PM PDT 24
Peak memory 200416 kb
Host smart-e2efe16f-14e6-4012-9bee-5d5e04b5d3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066948709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3066948709
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.196479478
Short name T300
Test name
Test status
Simulation time 531511564 ps
CPU time 1.64 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:47:44 PM PDT 24
Peak memory 195924 kb
Host smart-36c5df5a-7c01-43de-9e16-994ac81260ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196479478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.196479478
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1590652973
Short name T872
Test name
Test status
Simulation time 5380001806 ps
CPU time 20.21 seconds
Started Mar 28 01:47:47 PM PDT 24
Finished Mar 28 01:48:08 PM PDT 24
Peak memory 200256 kb
Host smart-2e714dd6-aaaa-4ae1-9809-ce0d3b77a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590652973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1590652973
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.51536154
Short name T585
Test name
Test status
Simulation time 302140988956 ps
CPU time 984.26 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 02:04:10 PM PDT 24
Peak memory 200436 kb
Host smart-9ec53d80-5218-4d4e-bc93-de59744a8686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51536154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.51536154
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3935445891
Short name T378
Test name
Test status
Simulation time 631669837 ps
CPU time 2.48 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:47:45 PM PDT 24
Peak memory 199352 kb
Host smart-3d8f7a48-021f-4fd1-a39c-676a49cddc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935445891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3935445891
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2458294407
Short name T699
Test name
Test status
Simulation time 67444723254 ps
CPU time 24.64 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:48:08 PM PDT 24
Peak memory 200504 kb
Host smart-6528e55c-9bcd-4f23-8f00-fdd06aadbb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458294407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2458294407
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1909727388
Short name T23
Test name
Test status
Simulation time 14240514 ps
CPU time 0.56 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:48:03 PM PDT 24
Peak memory 195868 kb
Host smart-2801480f-f358-4530-893a-06bac25330c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909727388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1909727388
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3516413027
Short name T672
Test name
Test status
Simulation time 108546287631 ps
CPU time 571.72 seconds
Started Mar 28 01:47:46 PM PDT 24
Finished Mar 28 01:57:18 PM PDT 24
Peak memory 200384 kb
Host smart-497104ef-e475-4b85-a42a-ef4ef9621d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516413027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3516413027
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1975617448
Short name T1149
Test name
Test status
Simulation time 43146922373 ps
CPU time 20.67 seconds
Started Mar 28 01:47:42 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 200488 kb
Host smart-c2092a14-4758-4e78-ba2c-7e1d50e4c338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975617448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1975617448
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.518951554
Short name T695
Test name
Test status
Simulation time 540431294065 ps
CPU time 264.1 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:52:24 PM PDT 24
Peak memory 200516 kb
Host smart-ccdac84b-d7dc-4717-b2fc-99123e0f7423
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518951554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.518951554
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.715782336
Short name T929
Test name
Test status
Simulation time 90847465956 ps
CPU time 98.3 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:49:40 PM PDT 24
Peak memory 200228 kb
Host smart-559ab704-bdbf-49d5-b3de-6b7e370df6c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715782336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.715782336
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.699926450
Short name T400
Test name
Test status
Simulation time 5105694227 ps
CPU time 11.49 seconds
Started Mar 28 01:48:01 PM PDT 24
Finished Mar 28 01:48:12 PM PDT 24
Peak memory 198708 kb
Host smart-4683e884-fd85-4849-8786-61a6874348a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699926450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.699926450
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.304386160
Short name T592
Test name
Test status
Simulation time 105213274060 ps
CPU time 166.15 seconds
Started Mar 28 01:48:01 PM PDT 24
Finished Mar 28 01:50:47 PM PDT 24
Peak memory 200752 kb
Host smart-378ae7ac-e4d0-4ce5-9f5b-977b406cd15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304386160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.304386160
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3510966282
Short name T356
Test name
Test status
Simulation time 14897994631 ps
CPU time 732.99 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 02:00:16 PM PDT 24
Peak memory 200452 kb
Host smart-0343e311-34f1-4316-9cb4-f063535e1959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510966282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3510966282
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.4280223500
Short name T785
Test name
Test status
Simulation time 1292420372 ps
CPU time 1.03 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:48:01 PM PDT 24
Peak memory 196028 kb
Host smart-f7468ae8-0e45-4425-859a-ed1ac5712334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280223500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.4280223500
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3566701787
Short name T560
Test name
Test status
Simulation time 128535481451 ps
CPU time 15.25 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:48:16 PM PDT 24
Peak memory 199880 kb
Host smart-3f95833a-f1c3-456b-9c59-6219f0959a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566701787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3566701787
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3485732670
Short name T3
Test name
Test status
Simulation time 4613472025 ps
CPU time 2.26 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:48:03 PM PDT 24
Peak memory 196772 kb
Host smart-0c54cee0-ed6a-42cb-b17c-9fc6bcfb3b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485732670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3485732670
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3275466010
Short name T545
Test name
Test status
Simulation time 683957581 ps
CPU time 1.54 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:47:46 PM PDT 24
Peak memory 200144 kb
Host smart-08a4ce97-31bd-4b3d-9c64-e156b579a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275466010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3275466010
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1969817128
Short name T1091
Test name
Test status
Simulation time 188298278095 ps
CPU time 669.89 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:59:14 PM PDT 24
Peak memory 200492 kb
Host smart-a15eb3c6-d8a7-4c81-884f-bfb095439179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969817128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1969817128
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3141542832
Short name T665
Test name
Test status
Simulation time 39571087667 ps
CPU time 346.27 seconds
Started Mar 28 01:48:01 PM PDT 24
Finished Mar 28 01:53:47 PM PDT 24
Peak memory 216940 kb
Host smart-dee061fe-9337-402d-bd3f-a988c023e0cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141542832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3141542832
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1395570220
Short name T361
Test name
Test status
Simulation time 1594491211 ps
CPU time 1.78 seconds
Started Mar 28 01:48:01 PM PDT 24
Finished Mar 28 01:48:02 PM PDT 24
Peak memory 199728 kb
Host smart-becde6e1-6068-445b-b704-b6d104377991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395570220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1395570220
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3463786872
Short name T938
Test name
Test status
Simulation time 9624501701 ps
CPU time 16.71 seconds
Started Mar 28 01:47:44 PM PDT 24
Finished Mar 28 01:48:01 PM PDT 24
Peak memory 197132 kb
Host smart-943a292e-2e3c-4ba8-8c5b-9ffde9a055fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463786872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3463786872
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3239502716
Short name T25
Test name
Test status
Simulation time 19415144 ps
CPU time 0.56 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 195848 kb
Host smart-8122290b-7f4e-47c2-8726-d4abc8fbc760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239502716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3239502716
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1646014323
Short name T312
Test name
Test status
Simulation time 67604500905 ps
CPU time 122.39 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:50:05 PM PDT 24
Peak memory 200500 kb
Host smart-9d01ce93-7efa-4ffa-a079-904fb6c038fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646014323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1646014323
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2247112172
Short name T994
Test name
Test status
Simulation time 10967151316 ps
CPU time 5.93 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:48:09 PM PDT 24
Peak memory 200396 kb
Host smart-ce03b0b2-b268-4ed7-8312-bbc59f9b8a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247112172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2247112172
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.391941425
Short name T658
Test name
Test status
Simulation time 49835563993 ps
CPU time 19.32 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:22 PM PDT 24
Peak memory 200444 kb
Host smart-e70a1468-81e1-46d9-b30d-d37af88bb152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391941425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.391941425
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3571604658
Short name T1029
Test name
Test status
Simulation time 26054415482 ps
CPU time 22.33 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:24 PM PDT 24
Peak memory 200124 kb
Host smart-b52db6a1-c54f-47e8-9184-4cbf403c2d67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571604658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3571604658
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4293426312
Short name T385
Test name
Test status
Simulation time 82391588687 ps
CPU time 432.45 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:55:19 PM PDT 24
Peak memory 200368 kb
Host smart-eca2af5b-ff4a-40a8-98a9-16369f1bd538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293426312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4293426312
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1416327506
Short name T853
Test name
Test status
Simulation time 3941615678 ps
CPU time 4.44 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:48:09 PM PDT 24
Peak memory 199960 kb
Host smart-9780df30-74d6-4952-865c-d4ee8d34b775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416327506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1416327506
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2758981883
Short name T1180
Test name
Test status
Simulation time 39444045139 ps
CPU time 67.94 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:49:12 PM PDT 24
Peak memory 200776 kb
Host smart-c0c97d7d-877d-43d1-b1f8-19bf196c2b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758981883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2758981883
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3986863252
Short name T471
Test name
Test status
Simulation time 9974934481 ps
CPU time 492.24 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:56:16 PM PDT 24
Peak memory 200504 kb
Host smart-c2456e5c-527d-4985-8ba2-06f2d6b680b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986863252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3986863252
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2157501780
Short name T895
Test name
Test status
Simulation time 3491513396 ps
CPU time 7.49 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:48:08 PM PDT 24
Peak memory 198572 kb
Host smart-8ef51a10-a50c-4bf6-be74-b6fa89e962c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157501780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2157501780
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3315688451
Short name T169
Test name
Test status
Simulation time 160031646744 ps
CPU time 71.08 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:49:17 PM PDT 24
Peak memory 200256 kb
Host smart-d3b0f85d-ddce-467f-b5b0-bb0f92e58603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315688451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3315688451
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4272007499
Short name T745
Test name
Test status
Simulation time 5532518141 ps
CPU time 10.26 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:48:15 PM PDT 24
Peak memory 196736 kb
Host smart-8fddc384-3a79-47a2-945f-c71c9a01cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272007499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4272007499
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.863285048
Short name T996
Test name
Test status
Simulation time 292124934 ps
CPU time 1.11 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 198860 kb
Host smart-181a2a9e-ee9e-49f0-a3c3-2f01ea4ea5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863285048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.863285048
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3256924098
Short name T1075
Test name
Test status
Simulation time 155289233888 ps
CPU time 237.71 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:52:03 PM PDT 24
Peak memory 209012 kb
Host smart-8aa3d4b4-0506-4326-ac1a-a8c8c8fb358f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256924098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3256924098
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.995210823
Short name T728
Test name
Test status
Simulation time 34311256776 ps
CPU time 540.33 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:57:05 PM PDT 24
Peak memory 217200 kb
Host smart-52baab71-d5ef-4234-afd7-282ea4412042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995210823 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.995210823
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1142944308
Short name T948
Test name
Test status
Simulation time 7196690814 ps
CPU time 12.8 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:48:18 PM PDT 24
Peak memory 200516 kb
Host smart-f3a9695a-8b20-44ee-b4b8-9c4325541628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142944308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1142944308
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1539971467
Short name T1015
Test name
Test status
Simulation time 35064655822 ps
CPU time 50.09 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:52 PM PDT 24
Peak memory 200496 kb
Host smart-9db972fb-d543-487b-8c0a-96b704c1194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539971467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1539971467
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1354387636
Short name T359
Test name
Test status
Simulation time 37391541 ps
CPU time 0.54 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 195904 kb
Host smart-89ef9185-72ea-4887-93c3-1a73f92617de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354387636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1354387636
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3382796078
Short name T1077
Test name
Test status
Simulation time 35986547509 ps
CPU time 29.7 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:48:34 PM PDT 24
Peak memory 200532 kb
Host smart-a1875c11-4c0e-4660-bd3d-300ec500f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382796078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3382796078
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4196683199
Short name T774
Test name
Test status
Simulation time 107426499862 ps
CPU time 41.49 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:48:46 PM PDT 24
Peak memory 200120 kb
Host smart-ca7e931f-ae8e-4f47-9ab9-3e1d7f0ef749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196683199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4196683199
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3828590697
Short name T840
Test name
Test status
Simulation time 67475553475 ps
CPU time 25.04 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:48:30 PM PDT 24
Peak memory 200560 kb
Host smart-d433bd40-10ef-4be5-b6bf-4e6e2c7d4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828590697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3828590697
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3151910764
Short name T105
Test name
Test status
Simulation time 54151901094 ps
CPU time 73.6 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:49:19 PM PDT 24
Peak memory 200176 kb
Host smart-8fc3bfea-83f8-4478-b65e-6dcde8d60e5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151910764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3151910764
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3647144454
Short name T496
Test name
Test status
Simulation time 92858192028 ps
CPU time 307.5 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:53:14 PM PDT 24
Peak memory 200420 kb
Host smart-e280bee9-9c57-4201-b893-3f0765943ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647144454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3647144454
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1969010796
Short name T1133
Test name
Test status
Simulation time 4654293073 ps
CPU time 3.33 seconds
Started Mar 28 01:48:07 PM PDT 24
Finished Mar 28 01:48:10 PM PDT 24
Peak memory 199684 kb
Host smart-58873a49-221d-4c90-9790-549a17734572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969010796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1969010796
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2231347069
Short name T1093
Test name
Test status
Simulation time 159170768277 ps
CPU time 159.52 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:50:44 PM PDT 24
Peak memory 200816 kb
Host smart-8c032ae9-d112-47ca-9ac2-59d62affacee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231347069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2231347069
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.4277771693
Short name T538
Test name
Test status
Simulation time 8205148799 ps
CPU time 384.83 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:54:31 PM PDT 24
Peak memory 200480 kb
Host smart-b1f9ae5c-2216-4cbc-b283-63ba9c313f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277771693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4277771693
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2510308229
Short name T566
Test name
Test status
Simulation time 5787227587 ps
CPU time 49.75 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:48:55 PM PDT 24
Peak memory 199528 kb
Host smart-8cb70d00-dfc4-4104-9b1f-5d575d4f5780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510308229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2510308229
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3266861574
Short name T1110
Test name
Test status
Simulation time 80564634326 ps
CPU time 24.68 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:48:31 PM PDT 24
Peak memory 200376 kb
Host smart-07b62ba8-2de5-464d-9d78-e4eefc18b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266861574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3266861574
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1182338804
Short name T1108
Test name
Test status
Simulation time 3130230089 ps
CPU time 1.43 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 196276 kb
Host smart-c6012bf6-ce45-4532-9511-2d7679267697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182338804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1182338804
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3925839723
Short name T1173
Test name
Test status
Simulation time 454593932 ps
CPU time 1.99 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:48:08 PM PDT 24
Peak memory 198808 kb
Host smart-0cc00343-3665-4057-a460-742c667f584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925839723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3925839723
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2846875794
Short name T311
Test name
Test status
Simulation time 841369203116 ps
CPU time 353.85 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:54:00 PM PDT 24
Peak memory 208948 kb
Host smart-4daa4c08-6432-4073-81a3-bc428ebf3b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846875794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2846875794
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3898176108
Short name T784
Test name
Test status
Simulation time 103837649745 ps
CPU time 471.37 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:55:58 PM PDT 24
Peak memory 228368 kb
Host smart-fa8db560-4641-452a-b754-8dbe6c71630c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898176108 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3898176108
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1589607769
Short name T441
Test name
Test status
Simulation time 6605067803 ps
CPU time 11.82 seconds
Started Mar 28 01:48:07 PM PDT 24
Finished Mar 28 01:48:19 PM PDT 24
Peak memory 199832 kb
Host smart-c92368ef-5531-4eea-aa8c-e7170880dbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589607769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1589607769
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3050204796
Short name T905
Test name
Test status
Simulation time 474489173 ps
CPU time 1.43 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:48:05 PM PDT 24
Peak memory 198160 kb
Host smart-17943dff-dd07-4acc-8a5f-ba5f605a0690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050204796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3050204796
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2160686422
Short name T1043
Test name
Test status
Simulation time 22576894 ps
CPU time 0.57 seconds
Started Mar 28 01:48:01 PM PDT 24
Finished Mar 28 01:48:01 PM PDT 24
Peak memory 195868 kb
Host smart-91356fce-0843-4c55-9e37-bbae5e7ef070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160686422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2160686422
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.674659272
Short name T834
Test name
Test status
Simulation time 147450755062 ps
CPU time 112.89 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:49:59 PM PDT 24
Peak memory 200528 kb
Host smart-3549869d-e42e-435a-9b14-9b26cbb9cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674659272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.674659272
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1346159365
Short name T1024
Test name
Test status
Simulation time 32709569676 ps
CPU time 15.88 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:18 PM PDT 24
Peak memory 200288 kb
Host smart-6c4d277f-16b0-453e-b297-bb07f9be5453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346159365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1346159365
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3015312750
Short name T114
Test name
Test status
Simulation time 21477425263 ps
CPU time 38.44 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:48:38 PM PDT 24
Peak memory 200504 kb
Host smart-a498ad58-1cd2-4929-9704-fbf225541c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015312750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3015312750
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.934544352
Short name T660
Test name
Test status
Simulation time 51794308928 ps
CPU time 41.35 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:48:44 PM PDT 24
Peak memory 200400 kb
Host smart-9160b044-a9bd-42be-949b-65c4cf5a4919
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934544352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.934544352
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1792579121
Short name T1084
Test name
Test status
Simulation time 156851821807 ps
CPU time 511.1 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:56:34 PM PDT 24
Peak memory 200508 kb
Host smart-32c427ac-417e-4a4a-b575-44728cc12980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792579121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1792579121
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2488554336
Short name T1031
Test name
Test status
Simulation time 10464908529 ps
CPU time 23.24 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:48:24 PM PDT 24
Peak memory 200400 kb
Host smart-bd7abac0-945a-4096-adaa-a8437d1f3391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488554336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2488554336
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1933525060
Short name T661
Test name
Test status
Simulation time 114524317242 ps
CPU time 54.8 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:48:55 PM PDT 24
Peak memory 199804 kb
Host smart-dfa33f17-03db-4bfc-bc19-82673f17f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933525060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1933525060
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2019917958
Short name T687
Test name
Test status
Simulation time 14213271186 ps
CPU time 660.68 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:59:03 PM PDT 24
Peak memory 200484 kb
Host smart-4f106edc-cec8-4845-923a-ad9ab5ac3da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019917958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2019917958
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.646077879
Short name T1027
Test name
Test status
Simulation time 4191514501 ps
CPU time 35.48 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:38 PM PDT 24
Peak memory 198812 kb
Host smart-51a09ce8-3045-4950-b9a6-0923058947c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646077879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.646077879
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3830017015
Short name T443
Test name
Test status
Simulation time 229441823264 ps
CPU time 172.86 seconds
Started Mar 28 01:48:00 PM PDT 24
Finished Mar 28 01:50:53 PM PDT 24
Peak memory 200212 kb
Host smart-ef3c9a9a-7a12-4017-b2dc-966655cd0b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830017015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3830017015
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4145851859
Short name T1033
Test name
Test status
Simulation time 78138132337 ps
CPU time 28.67 seconds
Started Mar 28 01:47:59 PM PDT 24
Finished Mar 28 01:48:28 PM PDT 24
Peak memory 196476 kb
Host smart-3e35019c-e890-49f5-b510-172ce49fcbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145851859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4145851859
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3484256931
Short name T664
Test name
Test status
Simulation time 282097809 ps
CPU time 1.01 seconds
Started Mar 28 01:48:07 PM PDT 24
Finished Mar 28 01:48:08 PM PDT 24
Peak memory 198712 kb
Host smart-78bf019f-dc45-4f86-87f3-b32c50127989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484256931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3484256931
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3775991362
Short name T457
Test name
Test status
Simulation time 150402054342 ps
CPU time 85.45 seconds
Started Mar 28 01:48:01 PM PDT 24
Finished Mar 28 01:49:26 PM PDT 24
Peak memory 200516 kb
Host smart-9b5ae0b1-ad1d-4627-9636-057a28bfab95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775991362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3775991362
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1773985679
Short name T167
Test name
Test status
Simulation time 45351002994 ps
CPU time 455.97 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:55:39 PM PDT 24
Peak memory 216960 kb
Host smart-92a1c661-63e1-4375-a2c5-085080c86711
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773985679 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1773985679
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1889222309
Short name T442
Test name
Test status
Simulation time 854618178 ps
CPU time 2.54 seconds
Started Mar 28 01:48:01 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 199192 kb
Host smart-171da846-37c4-4caa-ab17-c6f515d10d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889222309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1889222309
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.4039722318
Short name T375
Test name
Test status
Simulation time 85187242674 ps
CPU time 100.55 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:49:44 PM PDT 24
Peak memory 200480 kb
Host smart-b0d5b4aa-6896-4dc0-b18a-36c534bdfc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039722318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4039722318
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1340824352
Short name T1107
Test name
Test status
Simulation time 20178747 ps
CPU time 0.56 seconds
Started Mar 28 01:48:06 PM PDT 24
Finished Mar 28 01:48:06 PM PDT 24
Peak memory 195884 kb
Host smart-2000df18-bd64-44d7-9ea0-fc159ddd2339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340824352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1340824352
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.775609655
Short name T154
Test name
Test status
Simulation time 116781505867 ps
CPU time 47.56 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:50 PM PDT 24
Peak memory 200448 kb
Host smart-1d3fbc8d-1aed-4745-b224-105b081be0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775609655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.775609655
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2927999339
Short name T132
Test name
Test status
Simulation time 244634170616 ps
CPU time 450.07 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:55:35 PM PDT 24
Peak memory 200464 kb
Host smart-b68bd84c-aab0-427f-8f28-e20f325ba9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927999339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2927999339
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3455375877
Short name T193
Test name
Test status
Simulation time 190932371006 ps
CPU time 33.34 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:35 PM PDT 24
Peak memory 200460 kb
Host smart-fccc4035-2a6e-4ca7-9ead-276e346ed514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455375877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3455375877
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2685321960
Short name T912
Test name
Test status
Simulation time 76847294024 ps
CPU time 68.19 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:49:11 PM PDT 24
Peak memory 200524 kb
Host smart-38104c14-3343-48ab-9c45-c91ab984fbf4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685321960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2685321960
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.461494719
Short name T809
Test name
Test status
Simulation time 98105928407 ps
CPU time 231.8 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:51:56 PM PDT 24
Peak memory 200444 kb
Host smart-83521b3e-93b1-4e72-8656-2d5abe2d7e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461494719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.461494719
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3965230030
Short name T537
Test name
Test status
Simulation time 9720128574 ps
CPU time 17.82 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:48:23 PM PDT 24
Peak memory 199400 kb
Host smart-b92045f7-acb3-46b4-9d03-15f984e65fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965230030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3965230030
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3845753869
Short name T821
Test name
Test status
Simulation time 573712825304 ps
CPU time 85.95 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:49:30 PM PDT 24
Peak memory 200904 kb
Host smart-8ead4736-dc7d-4b77-9df9-928476f306ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845753869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3845753869
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.959648708
Short name T702
Test name
Test status
Simulation time 17451097225 ps
CPU time 239.85 seconds
Started Mar 28 01:48:07 PM PDT 24
Finished Mar 28 01:52:07 PM PDT 24
Peak memory 200448 kb
Host smart-b38b4aac-6197-402d-8a48-cf4da6c9b8cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959648708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.959648708
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2679813646
Short name T791
Test name
Test status
Simulation time 4783845004 ps
CPU time 45.96 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:48 PM PDT 24
Peak memory 199228 kb
Host smart-0965f24f-97a2-4ce5-803f-d68569df447c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679813646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2679813646
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2666829294
Short name T136
Test name
Test status
Simulation time 24595769861 ps
CPU time 77.83 seconds
Started Mar 28 01:48:07 PM PDT 24
Finished Mar 28 01:49:25 PM PDT 24
Peak memory 200448 kb
Host smart-e8d41b05-f7ca-4c24-b486-876fbbbdff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666829294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2666829294
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1683341240
Short name T486
Test name
Test status
Simulation time 44892831157 ps
CPU time 74.71 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:49:18 PM PDT 24
Peak memory 196244 kb
Host smart-16f881f9-ad87-4ba0-af1a-816c15249bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683341240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1683341240
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.489659594
Short name T284
Test name
Test status
Simulation time 553128683 ps
CPU time 2 seconds
Started Mar 28 01:48:02 PM PDT 24
Finished Mar 28 01:48:04 PM PDT 24
Peak memory 199904 kb
Host smart-484b70b6-658d-4e75-aa39-d2f4243551dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489659594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.489659594
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2234895179
Short name T456
Test name
Test status
Simulation time 192530956039 ps
CPU time 187.66 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:51:11 PM PDT 24
Peak memory 200536 kb
Host smart-f87f6eff-0435-45da-8d0c-1c522c6afc74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234895179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2234895179
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.504888338
Short name T1034
Test name
Test status
Simulation time 40414444979 ps
CPU time 472.11 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:55:56 PM PDT 24
Peak memory 217200 kb
Host smart-05d5a0c7-4e9b-4386-8dd2-6799bd72993d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504888338 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.504888338
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3377268427
Short name T796
Test name
Test status
Simulation time 1354681688 ps
CPU time 1.96 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:48:07 PM PDT 24
Peak memory 200040 kb
Host smart-7328a21f-2bc8-497a-a3a5-fbf25f743d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377268427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3377268427
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.898211389
Short name T1176
Test name
Test status
Simulation time 55650589573 ps
CPU time 42.8 seconds
Started Mar 28 01:48:04 PM PDT 24
Finished Mar 28 01:48:47 PM PDT 24
Peak memory 200468 kb
Host smart-fc5ca81d-d35e-4f1f-aca0-73ca8058a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898211389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.898211389
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.980588457
Short name T427
Test name
Test status
Simulation time 72208943 ps
CPU time 0.56 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:48:31 PM PDT 24
Peak memory 195876 kb
Host smart-6b0a3db9-a08f-4196-9f24-3aff553d05e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980588457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.980588457
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3267955714
Short name T251
Test name
Test status
Simulation time 27152305995 ps
CPU time 26.1 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:48:56 PM PDT 24
Peak memory 200432 kb
Host smart-78baf9ac-5710-432d-aa4e-673255a07db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267955714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3267955714
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1545722807
Short name T622
Test name
Test status
Simulation time 6576859869 ps
CPU time 9.37 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:48:40 PM PDT 24
Peak memory 199588 kb
Host smart-60e7991c-75a1-4d90-924e-c94a51070b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545722807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1545722807
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.622907750
Short name T286
Test name
Test status
Simulation time 63549974574 ps
CPU time 31.32 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:49:02 PM PDT 24
Peak memory 200436 kb
Host smart-b06339fd-9e31-464f-b7d1-e394ca1a7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622907750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.622907750
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.747151122
Short name T596
Test name
Test status
Simulation time 13080155934 ps
CPU time 5.38 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:48:36 PM PDT 24
Peak memory 198800 kb
Host smart-0471325c-f05f-44dd-b6c7-0ff9cb00bb6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747151122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.747151122
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4134513972
Short name T1092
Test name
Test status
Simulation time 127573572201 ps
CPU time 893.18 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 02:03:24 PM PDT 24
Peak memory 200492 kb
Host smart-6f9f724c-4da0-4beb-8227-8bed6c26cbc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134513972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4134513972
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.288231875
Short name T571
Test name
Test status
Simulation time 6930197964 ps
CPU time 11.39 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:48:41 PM PDT 24
Peak memory 200036 kb
Host smart-1c606c68-e3b2-4e87-8e3b-485bc4a180e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288231875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.288231875
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3128051576
Short name T586
Test name
Test status
Simulation time 59472223019 ps
CPU time 87.24 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:49:59 PM PDT 24
Peak memory 200688 kb
Host smart-78920a4c-0999-42c2-b974-448872bbd49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128051576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3128051576
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1366958653
Short name T1141
Test name
Test status
Simulation time 25910556472 ps
CPU time 1538.64 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 02:14:09 PM PDT 24
Peak memory 200364 kb
Host smart-f15a02a7-9c7d-4c52-b1ad-9b7da3c634a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1366958653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1366958653
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4294600397
Short name T344
Test name
Test status
Simulation time 2760610217 ps
CPU time 11.05 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:48:46 PM PDT 24
Peak memory 198560 kb
Host smart-a6caebdd-e6ea-4d0a-8c40-29e941b3b76c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294600397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4294600397
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1751926969
Short name T253
Test name
Test status
Simulation time 183522776355 ps
CPU time 307.47 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:53:37 PM PDT 24
Peak memory 200472 kb
Host smart-267f5f9a-b80c-45f0-af9d-d4fd274f7ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751926969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1751926969
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4072892580
Short name T719
Test name
Test status
Simulation time 3524805701 ps
CPU time 6.22 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:48:37 PM PDT 24
Peak memory 196276 kb
Host smart-cce095b7-c64e-4fc5-b85c-07b3ed153864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072892580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4072892580
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.498250057
Short name T608
Test name
Test status
Simulation time 652148662 ps
CPU time 2.48 seconds
Started Mar 28 01:48:03 PM PDT 24
Finished Mar 28 01:48:06 PM PDT 24
Peak memory 199164 kb
Host smart-39cc06e5-d63f-4c4d-814a-d8d01fcb6d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498250057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.498250057
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2593845844
Short name T678
Test name
Test status
Simulation time 322308846680 ps
CPU time 544.88 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:57:35 PM PDT 24
Peak memory 200524 kb
Host smart-d106bd53-bdfb-4695-bdd2-b37a36e59880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593845844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2593845844
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1787530231
Short name T1080
Test name
Test status
Simulation time 20855434129 ps
CPU time 406.85 seconds
Started Mar 28 01:48:28 PM PDT 24
Finished Mar 28 01:55:15 PM PDT 24
Peak memory 216336 kb
Host smart-fbbc1cc5-9402-41d7-836c-f286b821fb0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787530231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1787530231
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1823110235
Short name T730
Test name
Test status
Simulation time 2850394814 ps
CPU time 1.88 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:48:36 PM PDT 24
Peak memory 198692 kb
Host smart-be699ec6-3695-4111-88c7-4cf468d853fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823110235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1823110235
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1047798428
Short name T852
Test name
Test status
Simulation time 44141682855 ps
CPU time 40.52 seconds
Started Mar 28 01:48:05 PM PDT 24
Finished Mar 28 01:48:46 PM PDT 24
Peak memory 200448 kb
Host smart-4db7bd0e-22f6-4c7b-9105-1c127c5b7459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047798428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1047798428
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2523658933
Short name T342
Test name
Test status
Simulation time 21500509 ps
CPU time 0.56 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:48:35 PM PDT 24
Peak memory 195884 kb
Host smart-e202bf98-2574-4de2-a0b9-b9a7f8fa4b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523658933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2523658933
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.4225013448
Short name T415
Test name
Test status
Simulation time 24883490102 ps
CPU time 52.56 seconds
Started Mar 28 01:48:31 PM PDT 24
Finished Mar 28 01:49:23 PM PDT 24
Peak memory 200492 kb
Host smart-7065839e-c95f-4dc1-aebd-28928abac464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225013448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4225013448
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2787746248
Short name T645
Test name
Test status
Simulation time 75216116922 ps
CPU time 124.03 seconds
Started Mar 28 01:48:29 PM PDT 24
Finished Mar 28 01:50:34 PM PDT 24
Peak memory 200400 kb
Host smart-cef704c4-15cd-4315-8783-694d3b1eb90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787746248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2787746248
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3898429408
Short name T1130
Test name
Test status
Simulation time 18699747609 ps
CPU time 36.78 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:49:09 PM PDT 24
Peak memory 200436 kb
Host smart-dc736f41-5c80-4166-8c1f-9d028b42f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898429408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3898429408
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1991548891
Short name T1126
Test name
Test status
Simulation time 42930461228 ps
CPU time 39.63 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:49:10 PM PDT 24
Peak memory 200408 kb
Host smart-6d0c7376-1633-42a8-902c-42bc7a2e483c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991548891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1991548891
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.433371237
Short name T369
Test name
Test status
Simulation time 114987118429 ps
CPU time 346.51 seconds
Started Mar 28 01:48:28 PM PDT 24
Finished Mar 28 01:54:15 PM PDT 24
Peak memory 200328 kb
Host smart-2b86e96a-b3af-4fb8-828c-69b39640606a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433371237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.433371237
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1608487066
Short name T689
Test name
Test status
Simulation time 3943384086 ps
CPU time 4.97 seconds
Started Mar 28 01:48:31 PM PDT 24
Finished Mar 28 01:48:36 PM PDT 24
Peak memory 199456 kb
Host smart-9144a06b-e7f1-4080-aeeb-165591066e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608487066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1608487066
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3987840032
Short name T1021
Test name
Test status
Simulation time 77326855578 ps
CPU time 55.21 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:49:25 PM PDT 24
Peak memory 199196 kb
Host smart-d5b21ee2-f609-42dc-b938-2a72940f9396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987840032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3987840032
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2414667017
Short name T1070
Test name
Test status
Simulation time 21013505758 ps
CPU time 615.56 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:58:48 PM PDT 24
Peak memory 200476 kb
Host smart-0090f642-d877-43ab-9851-a9e065ca048e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414667017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2414667017
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3050254513
Short name T376
Test name
Test status
Simulation time 5569038262 ps
CPU time 48.7 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:49:21 PM PDT 24
Peak memory 199660 kb
Host smart-30cb3b54-6e99-4e29-95b5-e47fc073e9c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050254513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3050254513
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1982905641
Short name T616
Test name
Test status
Simulation time 52019805639 ps
CPU time 71.24 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:49:43 PM PDT 24
Peak memory 200528 kb
Host smart-60aba6d0-f638-473f-bbb4-eb8d853f4e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982905641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1982905641
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3818304509
Short name T343
Test name
Test status
Simulation time 5634106409 ps
CPU time 2.57 seconds
Started Mar 28 01:48:31 PM PDT 24
Finished Mar 28 01:48:33 PM PDT 24
Peak memory 196772 kb
Host smart-e7127318-2825-4278-a85d-f9ddbe04248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818304509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3818304509
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3313512517
Short name T273
Test name
Test status
Simulation time 5689874579 ps
CPU time 42.2 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:49:17 PM PDT 24
Peak memory 199632 kb
Host smart-82c81de9-8783-4bf7-9a5e-6da6ae7d9eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313512517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3313512517
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3431378482
Short name T487
Test name
Test status
Simulation time 124068101791 ps
CPU time 36.82 seconds
Started Mar 28 01:48:31 PM PDT 24
Finished Mar 28 01:49:08 PM PDT 24
Peak memory 200516 kb
Host smart-480906a7-3dcc-48cf-8ccf-1dd307fd23a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431378482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3431378482
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4234331206
Short name T1112
Test name
Test status
Simulation time 474407927026 ps
CPU time 332.85 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:54:05 PM PDT 24
Peak memory 217196 kb
Host smart-682a4d51-d10b-41f7-9878-6e011e070806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234331206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4234331206
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2200518608
Short name T1073
Test name
Test status
Simulation time 7227024125 ps
CPU time 13.31 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:48:46 PM PDT 24
Peak memory 199688 kb
Host smart-c363c7ef-b42f-4747-a356-821e3579e160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200518608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2200518608
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2227503988
Short name T332
Test name
Test status
Simulation time 47455003364 ps
CPU time 71.49 seconds
Started Mar 28 01:48:30 PM PDT 24
Finished Mar 28 01:49:41 PM PDT 24
Peak memory 200504 kb
Host smart-9dfccb43-19a1-45f0-b59d-03880e19427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227503988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2227503988
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1489426999
Short name T792
Test name
Test status
Simulation time 14395105 ps
CPU time 0.57 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:48:33 PM PDT 24
Peak memory 195828 kb
Host smart-08bd4e96-068b-4738-a436-aee8e3a18189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489426999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1489426999
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1607064451
Short name T1050
Test name
Test status
Simulation time 293280624892 ps
CPU time 81.28 seconds
Started Mar 28 01:48:35 PM PDT 24
Finished Mar 28 01:49:56 PM PDT 24
Peak memory 200416 kb
Host smart-046e97c2-a50c-48c7-9ac8-884f882d6acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607064451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1607064451
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.123934288
Short name T939
Test name
Test status
Simulation time 82704340723 ps
CPU time 64.92 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:49:39 PM PDT 24
Peak memory 200404 kb
Host smart-a5fd394c-e103-41ea-8e20-cd1891e54291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123934288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.123934288
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.4214822243
Short name T706
Test name
Test status
Simulation time 13436657935 ps
CPU time 14.68 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:48:49 PM PDT 24
Peak memory 200428 kb
Host smart-1bf5ad63-9033-4200-9a88-36ade6db42ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214822243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.4214822243
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.346451092
Short name T669
Test name
Test status
Simulation time 309987458253 ps
CPU time 56.17 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:49:29 PM PDT 24
Peak memory 200380 kb
Host smart-077687d4-9675-4a72-92db-6b0cc8f7083c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346451092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.346451092
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.898594653
Short name T703
Test name
Test status
Simulation time 72754159552 ps
CPU time 611.25 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:58:44 PM PDT 24
Peak memory 200412 kb
Host smart-886b99a9-915a-4a5c-8768-f72c09651992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898594653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.898594653
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2812050931
Short name T338
Test name
Test status
Simulation time 1881977053 ps
CPU time 3.69 seconds
Started Mar 28 01:48:35 PM PDT 24
Finished Mar 28 01:48:39 PM PDT 24
Peak memory 197660 kb
Host smart-582b31af-569f-4e92-8ced-774416eaa7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812050931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2812050931
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3887538915
Short name T1020
Test name
Test status
Simulation time 81057463266 ps
CPU time 120.65 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:50:34 PM PDT 24
Peak memory 200604 kb
Host smart-a247b468-c51c-4821-b754-41934e69b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887538915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3887538915
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.498995674
Short name T524
Test name
Test status
Simulation time 23824123213 ps
CPU time 596.32 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:58:29 PM PDT 24
Peak memory 200472 kb
Host smart-58b78b24-d517-4e0d-ba95-25b2e3a33da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=498995674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.498995674
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.889325152
Short name T16
Test name
Test status
Simulation time 5843812274 ps
CPU time 12.81 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:48:47 PM PDT 24
Peak memory 199904 kb
Host smart-3794c0c9-c122-43a4-8f38-9e673cf6e26e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889325152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.889325152
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1604570782
Short name T723
Test name
Test status
Simulation time 60547878288 ps
CPU time 43.21 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:49:16 PM PDT 24
Peak memory 200404 kb
Host smart-ff78ea89-5417-423e-86e2-2d1220290388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604570782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1604570782
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3946399933
Short name T711
Test name
Test status
Simulation time 747278344 ps
CPU time 1.21 seconds
Started Mar 28 01:48:31 PM PDT 24
Finished Mar 28 01:48:33 PM PDT 24
Peak memory 195908 kb
Host smart-5a2d81e7-549a-465b-baf2-896d6d83f77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946399933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3946399933
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2600008366
Short name T352
Test name
Test status
Simulation time 5429175588 ps
CPU time 14.72 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:48:48 PM PDT 24
Peak memory 200320 kb
Host smart-ba1bc1bf-534f-409b-a68f-b51fb174d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600008366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2600008366
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2016875031
Short name T923
Test name
Test status
Simulation time 860764890901 ps
CPU time 220.06 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:52:14 PM PDT 24
Peak memory 208988 kb
Host smart-4798443d-c130-47e2-b645-731ab6b0f912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016875031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2016875031
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1621981631
Short name T50
Test name
Test status
Simulation time 127314755547 ps
CPU time 994.76 seconds
Started Mar 28 01:48:35 PM PDT 24
Finished Mar 28 02:05:10 PM PDT 24
Peak memory 217064 kb
Host smart-53a5eb01-130c-4f6a-944e-5a8ce5b2a8ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621981631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1621981631
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1702976166
Short name T461
Test name
Test status
Simulation time 2476525429 ps
CPU time 2.09 seconds
Started Mar 28 01:48:32 PM PDT 24
Finished Mar 28 01:48:34 PM PDT 24
Peak memory 200476 kb
Host smart-6b71d4ff-569e-497b-accf-43fc05e66ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702976166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1702976166
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3416409529
Short name T310
Test name
Test status
Simulation time 36954031225 ps
CPU time 60.34 seconds
Started Mar 28 01:48:31 PM PDT 24
Finished Mar 28 01:49:32 PM PDT 24
Peak memory 200492 kb
Host smart-dafbd6f7-9323-470f-866a-22ff938ce2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416409529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3416409529
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2185124836
Short name T420
Test name
Test status
Simulation time 14649749 ps
CPU time 0.61 seconds
Started Mar 28 01:45:16 PM PDT 24
Finished Mar 28 01:45:17 PM PDT 24
Peak memory 195888 kb
Host smart-30e58b52-57ce-4f96-84d0-d753ee763d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185124836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2185124836
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1962419764
Short name T1177
Test name
Test status
Simulation time 123850729507 ps
CPU time 18.13 seconds
Started Mar 28 01:45:04 PM PDT 24
Finished Mar 28 01:45:22 PM PDT 24
Peak memory 200484 kb
Host smart-1293c825-7c81-4e48-a884-ae129f657e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962419764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1962419764
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3032404776
Short name T95
Test name
Test status
Simulation time 161558584329 ps
CPU time 25.24 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:45:26 PM PDT 24
Peak memory 200436 kb
Host smart-12e13eb5-e361-4a28-8e63-ccd0ff804029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032404776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3032404776
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1175256417
Short name T195
Test name
Test status
Simulation time 159889201603 ps
CPU time 244.8 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:49:05 PM PDT 24
Peak memory 200460 kb
Host smart-cc661c56-6826-45d4-a38d-ec7c98b7f13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175256417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1175256417
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3564506119
Short name T520
Test name
Test status
Simulation time 403774182663 ps
CPU time 165.14 seconds
Started Mar 28 01:45:02 PM PDT 24
Finished Mar 28 01:47:48 PM PDT 24
Peak memory 198744 kb
Host smart-d4d30b66-71ff-4d4d-8a35-f48ceb665789
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564506119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3564506119
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3586239305
Short name T296
Test name
Test status
Simulation time 113904940543 ps
CPU time 291 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 200428 kb
Host smart-14c15d6d-c490-4966-a534-3c2885d44095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586239305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3586239305
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4190303328
Short name T969
Test name
Test status
Simulation time 4990207640 ps
CPU time 7.34 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:27 PM PDT 24
Peak memory 199008 kb
Host smart-5047d764-f3b2-45fc-8fb5-8b893aece278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190303328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4190303328
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.840898813
Short name T283
Test name
Test status
Simulation time 223999467675 ps
CPU time 142.35 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:47:22 PM PDT 24
Peak memory 200752 kb
Host smart-8f33637d-015e-4c38-9d40-194114809908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840898813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.840898813
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2072098557
Short name T405
Test name
Test status
Simulation time 11225061741 ps
CPU time 607.82 seconds
Started Mar 28 01:45:16 PM PDT 24
Finished Mar 28 01:55:24 PM PDT 24
Peak memory 200468 kb
Host smart-0f603d43-bc27-4518-9521-4efd3087bdb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072098557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2072098557
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3798986214
Short name T1156
Test name
Test status
Simulation time 5377722073 ps
CPU time 48.28 seconds
Started Mar 28 01:44:59 PM PDT 24
Finished Mar 28 01:45:47 PM PDT 24
Peak memory 199772 kb
Host smart-964a52ba-8e2f-4b33-b1a1-e2f763c461b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798986214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3798986214
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.692332412
Short name T966
Test name
Test status
Simulation time 12564965276 ps
CPU time 21.65 seconds
Started Mar 28 01:45:03 PM PDT 24
Finished Mar 28 01:45:25 PM PDT 24
Peak memory 200452 kb
Host smart-93cb352f-1a91-426a-9a6b-88e91c83170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692332412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.692332412
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1511968981
Short name T846
Test name
Test status
Simulation time 4036449619 ps
CPU time 1.05 seconds
Started Mar 28 01:45:00 PM PDT 24
Finished Mar 28 01:45:01 PM PDT 24
Peak memory 196524 kb
Host smart-b019f988-9c9f-4105-84ea-da7591e37419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511968981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1511968981
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1763078890
Short name T1040
Test name
Test status
Simulation time 688199744 ps
CPU time 3.11 seconds
Started Mar 28 01:45:09 PM PDT 24
Finished Mar 28 01:45:12 PM PDT 24
Peak memory 198748 kb
Host smart-940381f5-9850-49df-b1ce-f7182d8926a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763078890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1763078890
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.576565106
Short name T267
Test name
Test status
Simulation time 126016392124 ps
CPU time 503.26 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:53:41 PM PDT 24
Peak memory 200484 kb
Host smart-710a9c7d-6aba-4399-b502-088974264f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576565106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.576565106
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1400262914
Short name T22
Test name
Test status
Simulation time 26428953247 ps
CPU time 284.83 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:50:03 PM PDT 24
Peak memory 213560 kb
Host smart-0296deb1-f6ce-4b97-b82f-b8f3d1456639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400262914 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1400262914
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2595761511
Short name T1095
Test name
Test status
Simulation time 1327283821 ps
CPU time 2.3 seconds
Started Mar 28 01:45:01 PM PDT 24
Finished Mar 28 01:45:03 PM PDT 24
Peak memory 199080 kb
Host smart-52d108fc-179b-422b-b647-9b4a39c8d165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595761511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2595761511
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3134631125
Short name T639
Test name
Test status
Simulation time 48689537218 ps
CPU time 92.6 seconds
Started Mar 28 01:45:07 PM PDT 24
Finished Mar 28 01:46:39 PM PDT 24
Peak memory 200480 kb
Host smart-366d7816-862a-4101-8bec-942b99426770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134631125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3134631125
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2234200090
Short name T550
Test name
Test status
Simulation time 102288941550 ps
CPU time 70.91 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:49:45 PM PDT 24
Peak memory 200440 kb
Host smart-a008bc9c-3e22-4650-ad4e-e21d9fc80adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234200090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2234200090
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3151593654
Short name T613
Test name
Test status
Simulation time 75570929669 ps
CPU time 612.94 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:58:47 PM PDT 24
Peak memory 227412 kb
Host smart-c49fa6a5-ba4b-41e0-8dad-16f1719260ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151593654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3151593654
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1355977005
Short name T447
Test name
Test status
Simulation time 40334850367 ps
CPU time 35.99 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:49:10 PM PDT 24
Peak memory 200464 kb
Host smart-e08d8112-dc43-4d6c-abd5-59b925f039a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355977005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1355977005
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2480845458
Short name T49
Test name
Test status
Simulation time 253520402955 ps
CPU time 1096.49 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 02:06:50 PM PDT 24
Peak memory 217000 kb
Host smart-901ffee5-9347-4ae1-a698-85939e3ff07d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480845458 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2480845458
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3355511852
Short name T1032
Test name
Test status
Simulation time 205426613876 ps
CPU time 1950.6 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 02:21:04 PM PDT 24
Peak memory 241852 kb
Host smart-13ae682c-a675-498a-8a1a-10de6233a596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355511852 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3355511852
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.4150344593
Short name T257
Test name
Test status
Simulation time 55983413892 ps
CPU time 32.08 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:49:06 PM PDT 24
Peak memory 200512 kb
Host smart-b62ef564-f3d7-4c00-a8ff-da8dd240880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150344593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4150344593
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.902883298
Short name T625
Test name
Test status
Simulation time 83585905559 ps
CPU time 276.9 seconds
Started Mar 28 01:48:35 PM PDT 24
Finished Mar 28 01:53:12 PM PDT 24
Peak memory 216376 kb
Host smart-5662d7b8-b0e4-49e0-bb0e-0a9aee267d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902883298 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.902883298
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2694383849
Short name T841
Test name
Test status
Simulation time 145507749433 ps
CPU time 443.23 seconds
Started Mar 28 01:48:35 PM PDT 24
Finished Mar 28 01:55:58 PM PDT 24
Peak memory 216700 kb
Host smart-4bc3a037-fe85-4d30-90ee-adc33f52d224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694383849 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2694383849
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1381229987
Short name T194
Test name
Test status
Simulation time 40918182725 ps
CPU time 61.87 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 01:49:35 PM PDT 24
Peak memory 200404 kb
Host smart-ff87b62b-94cd-4268-9710-6434eaf4e134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381229987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1381229987
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.4224657762
Short name T1056
Test name
Test status
Simulation time 90529078345 ps
CPU time 827.54 seconds
Started Mar 28 01:48:35 PM PDT 24
Finished Mar 28 02:02:23 PM PDT 24
Peak memory 232836 kb
Host smart-8731814b-e6ae-431a-bc35-c7fbf237308a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224657762 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.4224657762
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1596264232
Short name T580
Test name
Test status
Simulation time 37127224665 ps
CPU time 54.27 seconds
Started Mar 28 01:48:34 PM PDT 24
Finished Mar 28 01:49:29 PM PDT 24
Peak memory 200448 kb
Host smart-9e36af72-f69d-484c-90c0-8881b9c56466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596264232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1596264232
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1464722667
Short name T987
Test name
Test status
Simulation time 87974785277 ps
CPU time 842.46 seconds
Started Mar 28 01:48:33 PM PDT 24
Finished Mar 28 02:02:36 PM PDT 24
Peak memory 216932 kb
Host smart-c9934d8b-48d5-4215-ac07-de347a66cd2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464722667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1464722667
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.874986419
Short name T120
Test name
Test status
Simulation time 9287840104 ps
CPU time 16.59 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:49:07 PM PDT 24
Peak memory 200420 kb
Host smart-7d3bdab5-9400-46a5-9058-ea0dea0f4b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874986419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.874986419
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2051524969
Short name T540
Test name
Test status
Simulation time 100905853088 ps
CPU time 232.06 seconds
Started Mar 28 01:48:45 PM PDT 24
Finished Mar 28 01:52:37 PM PDT 24
Peak memory 208696 kb
Host smart-80d27be3-c539-4d2f-a54b-4aeb34162986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051524969 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2051524969
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1209457600
Short name T931
Test name
Test status
Simulation time 32822379792 ps
CPU time 55.08 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:49:42 PM PDT 24
Peak memory 200500 kb
Host smart-9b0fa1d8-2efc-415e-ac94-5f7c129fd2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209457600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1209457600
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.494086224
Short name T842
Test name
Test status
Simulation time 27431030337 ps
CPU time 264.24 seconds
Started Mar 28 01:48:45 PM PDT 24
Finished Mar 28 01:53:10 PM PDT 24
Peak memory 216328 kb
Host smart-19fd3d36-5e19-47fe-a4e6-9235ab3e754c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494086224 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.494086224
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1699354465
Short name T1083
Test name
Test status
Simulation time 39873338 ps
CPU time 0.55 seconds
Started Mar 28 01:45:17 PM PDT 24
Finished Mar 28 01:45:18 PM PDT 24
Peak memory 195852 kb
Host smart-eaa1860b-626f-45eb-8f4b-c70d54653220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699354465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1699354465
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3689333273
Short name T547
Test name
Test status
Simulation time 24282050022 ps
CPU time 11.69 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:45:30 PM PDT 24
Peak memory 200520 kb
Host smart-a6a3611b-62dc-4bf0-8152-126373e5748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689333273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3689333273
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3214173192
Short name T681
Test name
Test status
Simulation time 34197468267 ps
CPU time 59.66 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 01:46:20 PM PDT 24
Peak memory 200484 kb
Host smart-8d587429-10ff-4de3-9624-5ba5ec9ce119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214173192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3214173192
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.294051567
Short name T521
Test name
Test status
Simulation time 88729836248 ps
CPU time 37.76 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 01:45:58 PM PDT 24
Peak memory 200484 kb
Host smart-d8219c38-86e9-49fe-8a3e-9a32683114f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294051567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.294051567
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.427002775
Short name T946
Test name
Test status
Simulation time 69033757687 ps
CPU time 18.68 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:45:37 PM PDT 24
Peak memory 200412 kb
Host smart-15c61a91-ee1a-44f1-8dbe-e784d95298f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427002775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.427002775
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1073577981
Short name T891
Test name
Test status
Simulation time 130699155211 ps
CPU time 701.51 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:57:04 PM PDT 24
Peak memory 200440 kb
Host smart-84a83ad7-d85e-4943-a2cb-06c5cf7af46d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073577981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1073577981
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.270556626
Short name T958
Test name
Test status
Simulation time 13264854308 ps
CPU time 8.91 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 01:45:29 PM PDT 24
Peak memory 200428 kb
Host smart-b79e23f4-d951-472c-a40d-ebf7c1633bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270556626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.270556626
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.961446685
Short name T381
Test name
Test status
Simulation time 12253557923 ps
CPU time 16.84 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:45:41 PM PDT 24
Peak memory 196552 kb
Host smart-427cf3bc-b59f-4438-a150-8927e1339d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961446685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.961446685
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4294516731
Short name T962
Test name
Test status
Simulation time 14405131199 ps
CPU time 779.79 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:58:22 PM PDT 24
Peak memory 200436 kb
Host smart-bd252fcd-cfad-46c8-8b4d-023afd04aa78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294516731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4294516731
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3458395323
Short name T899
Test name
Test status
Simulation time 3793443059 ps
CPU time 16.49 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:35 PM PDT 24
Peak memory 198860 kb
Host smart-72eecc88-afa9-4039-b6b3-938f1945226e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458395323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3458395323
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.649992640
Short name T619
Test name
Test status
Simulation time 217321617746 ps
CPU time 227.37 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:49:11 PM PDT 24
Peak memory 200392 kb
Host smart-a97b4e41-88c3-4f67-a658-15b370759480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649992640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.649992640
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2661163916
Short name T900
Test name
Test status
Simulation time 20565313661 ps
CPU time 9.74 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:45:28 PM PDT 24
Peak memory 196556 kb
Host smart-a2ef80d4-b828-4c35-b900-0b5018d62b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661163916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2661163916
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3599175869
Short name T513
Test name
Test status
Simulation time 725736424 ps
CPU time 1.24 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:20 PM PDT 24
Peak memory 198748 kb
Host smart-082d70b0-3c30-40db-9645-5f27009beae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599175869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3599175869
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3065679538
Short name T112
Test name
Test status
Simulation time 170938661148 ps
CPU time 1192.91 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 02:05:13 PM PDT 24
Peak memory 200524 kb
Host smart-57583d41-99b0-4480-ab05-62725a08e5e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065679538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3065679538
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2837056696
Short name T525
Test name
Test status
Simulation time 103221662896 ps
CPU time 435.96 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 01:52:37 PM PDT 24
Peak memory 216868 kb
Host smart-3e635d4e-b84c-43fe-8807-b869e1643b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837056696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2837056696
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3629260036
Short name T820
Test name
Test status
Simulation time 6462590681 ps
CPU time 11.54 seconds
Started Mar 28 01:45:17 PM PDT 24
Finished Mar 28 01:45:29 PM PDT 24
Peak memory 200204 kb
Host smart-8582ce4a-584a-4460-a8df-3e5789befc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629260036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3629260036
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4177560471
Short name T650
Test name
Test status
Simulation time 59451385876 ps
CPU time 104.36 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:47:02 PM PDT 24
Peak memory 200480 kb
Host smart-1060d960-ce10-46b0-b220-1c54e50768e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177560471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4177560471
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.109579971
Short name T218
Test name
Test status
Simulation time 87837887717 ps
CPU time 767.77 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 02:01:34 PM PDT 24
Peak memory 200428 kb
Host smart-a4d634cb-7d24-438c-911a-cf1a235b63b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109579971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.109579971
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2425415378
Short name T163
Test name
Test status
Simulation time 165194390020 ps
CPU time 518.03 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:57:29 PM PDT 24
Peak memory 225456 kb
Host smart-968e467b-91d7-413a-b96a-f8eb8ef477ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425415378 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2425415378
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1824936097
Short name T215
Test name
Test status
Simulation time 75814869312 ps
CPU time 257.3 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:53:04 PM PDT 24
Peak memory 200528 kb
Host smart-810584f0-a00e-42b5-9e89-8c53f28a82cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824936097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1824936097
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2385703854
Short name T12
Test name
Test status
Simulation time 24244248038 ps
CPU time 212.45 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:52:23 PM PDT 24
Peak memory 216272 kb
Host smart-9f90b244-6ac0-4cb8-aa5c-9acccaa3d804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385703854 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2385703854
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4062042051
Short name T965
Test name
Test status
Simulation time 66135030858 ps
CPU time 101.77 seconds
Started Mar 28 01:48:43 PM PDT 24
Finished Mar 28 01:50:25 PM PDT 24
Peak memory 200496 kb
Host smart-dbcea8b0-5a6a-469e-82fe-c1d745b8ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062042051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4062042051
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2713997568
Short name T422
Test name
Test status
Simulation time 32511288309 ps
CPU time 202.12 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:52:11 PM PDT 24
Peak memory 216976 kb
Host smart-97c7452e-6084-4b3a-9015-a9c2f14fd3dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713997568 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2713997568
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3918003668
Short name T242
Test name
Test status
Simulation time 32790746214 ps
CPU time 78.2 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 01:50:06 PM PDT 24
Peak memory 200460 kb
Host smart-517c37b0-061f-421e-8a38-1142775afba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918003668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3918003668
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3253168534
Short name T830
Test name
Test status
Simulation time 343646362697 ps
CPU time 1013.19 seconds
Started Mar 28 01:48:45 PM PDT 24
Finished Mar 28 02:05:38 PM PDT 24
Peak memory 226352 kb
Host smart-088b8002-8534-4bb9-8668-9aa2a7dbcfaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253168534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3253168534
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1937771448
Short name T546
Test name
Test status
Simulation time 75274922555 ps
CPU time 32 seconds
Started Mar 28 01:48:47 PM PDT 24
Finished Mar 28 01:49:19 PM PDT 24
Peak memory 200528 kb
Host smart-89f1b6f3-842b-42ac-b6ac-541d83079a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937771448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1937771448
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2610261587
Short name T623
Test name
Test status
Simulation time 87205983527 ps
CPU time 698.05 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 02:00:24 PM PDT 24
Peak memory 217248 kb
Host smart-4611d1f2-6cd4-4832-9bd2-fda4c90a867e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610261587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2610261587
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.169965075
Short name T527
Test name
Test status
Simulation time 206891818516 ps
CPU time 24.32 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:49:14 PM PDT 24
Peak memory 200420 kb
Host smart-35235500-763a-4056-88a1-03c0b164f574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169965075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.169965075
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.960223841
Short name T544
Test name
Test status
Simulation time 58246315820 ps
CPU time 671.5 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:59:58 PM PDT 24
Peak memory 215464 kb
Host smart-183ab4a4-89b8-4179-bb48-a3635d858e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960223841 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.960223841
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1545409552
Short name T180
Test name
Test status
Simulation time 86317185138 ps
CPU time 131.24 seconds
Started Mar 28 01:48:45 PM PDT 24
Finished Mar 28 01:50:57 PM PDT 24
Peak memory 200432 kb
Host smart-9c801117-afb8-4880-b6f2-48309a715d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545409552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1545409552
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1201618213
Short name T141
Test name
Test status
Simulation time 146805921154 ps
CPU time 827.56 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 02:02:36 PM PDT 24
Peak memory 225388 kb
Host smart-0849d6d2-bae7-40ff-904e-279613945f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201618213 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1201618213
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2207127673
Short name T401
Test name
Test status
Simulation time 98426682142 ps
CPU time 34.54 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:49:27 PM PDT 24
Peak memory 200552 kb
Host smart-37400288-686d-48ba-969b-868f6fa70c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207127673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2207127673
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1190986806
Short name T1097
Test name
Test status
Simulation time 63272020448 ps
CPU time 123.33 seconds
Started Mar 28 01:48:45 PM PDT 24
Finished Mar 28 01:50:49 PM PDT 24
Peak memory 216888 kb
Host smart-eb98ba3c-1de6-4df5-bc0a-8c404bcc72de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190986806 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1190986806
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3802099154
Short name T777
Test name
Test status
Simulation time 41372942684 ps
CPU time 19.6 seconds
Started Mar 28 01:48:47 PM PDT 24
Finished Mar 28 01:49:06 PM PDT 24
Peak memory 200448 kb
Host smart-759c310e-db99-4746-b193-0306e2db0a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802099154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3802099154
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.97042316
Short name T811
Test name
Test status
Simulation time 28313911811 ps
CPU time 466.96 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:56:37 PM PDT 24
Peak memory 216952 kb
Host smart-9bd01894-fbf5-412b-8afc-f4dfa9fa927c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97042316 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.97042316
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.831717927
Short name T192
Test name
Test status
Simulation time 21823095354 ps
CPU time 16.47 seconds
Started Mar 28 01:48:47 PM PDT 24
Finished Mar 28 01:49:04 PM PDT 24
Peak memory 200520 kb
Host smart-d97b68cf-22d1-4b5c-9507-fbad146e8ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831717927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.831717927
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.619106001
Short name T883
Test name
Test status
Simulation time 67325451046 ps
CPU time 441.7 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:56:11 PM PDT 24
Peak memory 216284 kb
Host smart-9de4ae00-8a69-4d68-805e-55d9bfed6b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619106001 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.619106001
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.758994653
Short name T336
Test name
Test status
Simulation time 12439689 ps
CPU time 0.57 seconds
Started Mar 28 01:45:21 PM PDT 24
Finished Mar 28 01:45:21 PM PDT 24
Peak memory 195880 kb
Host smart-3428adf6-0b9d-47fe-83d4-21fd9187d042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758994653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.758994653
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3717292341
Short name T355
Test name
Test status
Simulation time 30320920473 ps
CPU time 53.19 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:46:12 PM PDT 24
Peak memory 200436 kb
Host smart-fbc1e43d-7db1-4a7f-ad89-7649df474c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717292341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3717292341
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.601727823
Short name T1185
Test name
Test status
Simulation time 71540565984 ps
CPU time 28.45 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:47 PM PDT 24
Peak memory 200500 kb
Host smart-574fc29a-c524-4eee-8838-851e9f7bfcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601727823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.601727823
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.2987546312
Short name T558
Test name
Test status
Simulation time 19008706086 ps
CPU time 5 seconds
Started Mar 28 01:45:21 PM PDT 24
Finished Mar 28 01:45:26 PM PDT 24
Peak memory 200408 kb
Host smart-acf04d4b-672e-4b01-9a5a-971adbfc7548
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987546312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2987546312
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1576820408
Short name T463
Test name
Test status
Simulation time 87736485612 ps
CPU time 152.28 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:47:51 PM PDT 24
Peak memory 200468 kb
Host smart-87da8b10-33c6-4b1f-80b2-38e7cfd3ac04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576820408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1576820408
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3088543536
Short name T19
Test name
Test status
Simulation time 775634078 ps
CPU time 1.07 seconds
Started Mar 28 01:45:15 PM PDT 24
Finished Mar 28 01:45:16 PM PDT 24
Peak memory 196840 kb
Host smart-d0b1d80c-a129-4db1-87ad-bdf2750fb4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088543536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3088543536
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3058288238
Short name T1062
Test name
Test status
Simulation time 49285259723 ps
CPU time 76.72 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:46:36 PM PDT 24
Peak memory 200732 kb
Host smart-51ad31a5-8580-4d98-aa73-7a6d4c55242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058288238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3058288238
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.428029189
Short name T363
Test name
Test status
Simulation time 10450606573 ps
CPU time 657.64 seconds
Started Mar 28 01:45:21 PM PDT 24
Finished Mar 28 01:56:19 PM PDT 24
Peak memory 200396 kb
Host smart-3202ddff-5565-43f5-9ff4-60bb4fec1753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428029189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.428029189
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1437891520
Short name T440
Test name
Test status
Simulation time 4229158438 ps
CPU time 2.74 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 01:45:23 PM PDT 24
Peak memory 198656 kb
Host smart-f3cfff1b-f8e1-4941-aff4-0ca177a2763e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437891520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1437891520
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1332117290
Short name T94
Test name
Test status
Simulation time 67332065858 ps
CPU time 66.14 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:46:29 PM PDT 24
Peak memory 200448 kb
Host smart-fa4ead6c-6735-44dc-82d7-c2f852102bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332117290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1332117290
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1214150836
Short name T822
Test name
Test status
Simulation time 3340347587 ps
CPU time 5.84 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:45:24 PM PDT 24
Peak memory 196236 kb
Host smart-6b0c7f9c-89ae-4ed8-bf7d-2deefb4c597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214150836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1214150836
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3827234327
Short name T927
Test name
Test status
Simulation time 314420191 ps
CPU time 1.17 seconds
Started Mar 28 01:45:21 PM PDT 24
Finished Mar 28 01:45:22 PM PDT 24
Peak memory 199112 kb
Host smart-380f0b14-1cc0-42b1-89d2-8c0f899a9154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827234327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3827234327
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2623282388
Short name T651
Test name
Test status
Simulation time 296622848616 ps
CPU time 161.62 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:48:05 PM PDT 24
Peak memory 200496 kb
Host smart-2c90f8c6-1a43-4b0b-bf9b-093845e25a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623282388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2623282388
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.818425107
Short name T41
Test name
Test status
Simulation time 60409237646 ps
CPU time 609.1 seconds
Started Mar 28 01:45:18 PM PDT 24
Finished Mar 28 01:55:27 PM PDT 24
Peak memory 216956 kb
Host smart-0d9f8a72-96bb-48b4-9dc6-6abcd2bcdc61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818425107 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.818425107
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1581090386
Short name T1109
Test name
Test status
Simulation time 692381369 ps
CPU time 2.5 seconds
Started Mar 28 01:45:21 PM PDT 24
Finished Mar 28 01:45:23 PM PDT 24
Peak memory 198708 kb
Host smart-80eeb05c-d59a-4297-a7e7-53b1df3210e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581090386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1581090386
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.697834422
Short name T325
Test name
Test status
Simulation time 26559391726 ps
CPU time 22.87 seconds
Started Mar 28 01:45:17 PM PDT 24
Finished Mar 28 01:45:40 PM PDT 24
Peak memory 200500 kb
Host smart-6dd1385e-aafd-4edb-98ec-cb30d563650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697834422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.697834422
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2745239239
Short name T1139
Test name
Test status
Simulation time 273288646302 ps
CPU time 296.31 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:53:49 PM PDT 24
Peak memory 200516 kb
Host smart-10ebb46d-24a2-4c27-9192-8998eecf16d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745239239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2745239239
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1120529464
Short name T790
Test name
Test status
Simulation time 47671397066 ps
CPU time 664.39 seconds
Started Mar 28 01:48:45 PM PDT 24
Finished Mar 28 01:59:50 PM PDT 24
Peak memory 228192 kb
Host smart-89d23865-6781-4745-866d-c9fa36faa2c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120529464 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1120529464
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.254753795
Short name T712
Test name
Test status
Simulation time 11814235547 ps
CPU time 19.98 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:49:11 PM PDT 24
Peak memory 200332 kb
Host smart-9acf3916-5b53-43c8-952e-cc41b1f51064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254753795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.254753795
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2174481069
Short name T51
Test name
Test status
Simulation time 42829248052 ps
CPU time 424.82 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 01:55:53 PM PDT 24
Peak memory 215924 kb
Host smart-efa0e246-d626-4d59-8044-15b0a78715a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174481069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2174481069
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3083596946
Short name T42
Test name
Test status
Simulation time 176131815196 ps
CPU time 30.65 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:49:17 PM PDT 24
Peak memory 200488 kb
Host smart-8dfd974d-698e-400d-98e1-f6d7648e905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083596946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3083596946
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2509364664
Short name T768
Test name
Test status
Simulation time 95117565917 ps
CPU time 82.56 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:50:11 PM PDT 24
Peak memory 200344 kb
Host smart-f4bb412e-7e56-4a26-bfdb-048e53459d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509364664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2509364664
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1691787656
Short name T1164
Test name
Test status
Simulation time 202780687161 ps
CPU time 34.45 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 01:49:23 PM PDT 24
Peak memory 200580 kb
Host smart-389acc5e-8f8a-44f6-9247-cd8702d6d5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691787656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1691787656
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3472583817
Short name T1010
Test name
Test status
Simulation time 688519761019 ps
CPU time 857.73 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 02:03:06 PM PDT 24
Peak memory 225448 kb
Host smart-0f171b9c-5c07-4d40-936c-15b5bc7db7e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472583817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3472583817
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.4111943393
Short name T789
Test name
Test status
Simulation time 147378988082 ps
CPU time 112.37 seconds
Started Mar 28 01:48:47 PM PDT 24
Finished Mar 28 01:50:40 PM PDT 24
Peak memory 200412 kb
Host smart-91c9092e-f805-456d-82c1-8e9c777cf12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111943393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4111943393
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.4096671933
Short name T584
Test name
Test status
Simulation time 15128573520 ps
CPU time 394.11 seconds
Started Mar 28 01:48:47 PM PDT 24
Finished Mar 28 01:55:21 PM PDT 24
Peak memory 208784 kb
Host smart-243a9c49-1e68-4c71-839a-8edef0a14038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096671933 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.4096671933
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2952530143
Short name T202
Test name
Test status
Simulation time 12984407087 ps
CPU time 25.08 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:49:14 PM PDT 24
Peak memory 200424 kb
Host smart-ba70da51-b6e3-4daa-980c-65801e6f5a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952530143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2952530143
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2367818063
Short name T720
Test name
Test status
Simulation time 6197130957 ps
CPU time 78.6 seconds
Started Mar 28 01:48:53 PM PDT 24
Finished Mar 28 01:50:12 PM PDT 24
Peak memory 216356 kb
Host smart-5ba42910-d912-467d-85f8-a3fd23cb144f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367818063 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2367818063
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4128846145
Short name T1136
Test name
Test status
Simulation time 160252507234 ps
CPU time 229.05 seconds
Started Mar 28 01:48:53 PM PDT 24
Finished Mar 28 01:52:42 PM PDT 24
Peak memory 200512 kb
Host smart-9a390e9a-3b74-4db2-9a1b-24138a0470c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128846145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4128846145
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2151461391
Short name T1000
Test name
Test status
Simulation time 76565940152 ps
CPU time 909.52 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 02:03:58 PM PDT 24
Peak memory 212348 kb
Host smart-0cd1ed73-7943-4322-8a17-84e0a1962df5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151461391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2151461391
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3162544802
Short name T1088
Test name
Test status
Simulation time 71962314141 ps
CPU time 78.55 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 01:50:07 PM PDT 24
Peak memory 200416 kb
Host smart-a178feaa-d851-4c2c-a18e-fb79ee75c581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162544802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3162544802
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2689909735
Short name T97
Test name
Test status
Simulation time 30916220634 ps
CPU time 340.28 seconds
Started Mar 28 01:48:48 PM PDT 24
Finished Mar 28 01:54:29 PM PDT 24
Peak memory 208708 kb
Host smart-5f3686df-9f87-4e8a-8052-7d943740ea31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689909735 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2689909735
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1750172876
Short name T979
Test name
Test status
Simulation time 35562068705 ps
CPU time 36.63 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:49:22 PM PDT 24
Peak memory 200468 kb
Host smart-71eda2d0-b70c-4c5f-a36e-33c9787d9001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750172876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1750172876
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.475891673
Short name T453
Test name
Test status
Simulation time 6945696944 ps
CPU time 122.05 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:50:48 PM PDT 24
Peak memory 209548 kb
Host smart-036502de-e06a-42cd-81aa-392572e49043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475891673 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.475891673
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.392110237
Short name T906
Test name
Test status
Simulation time 14302744 ps
CPU time 0.55 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 01:45:24 PM PDT 24
Peak memory 195356 kb
Host smart-c9d5ab2d-a06a-4f5a-aeab-0da69c4c8235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392110237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.392110237
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1250118145
Short name T1148
Test name
Test status
Simulation time 129431779776 ps
CPU time 52.33 seconds
Started Mar 28 01:45:17 PM PDT 24
Finished Mar 28 01:46:10 PM PDT 24
Peak memory 200428 kb
Host smart-9b906471-5fbb-442a-9499-d3379c6c3382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250118145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1250118145
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.203719650
Short name T967
Test name
Test status
Simulation time 44861536177 ps
CPU time 37.74 seconds
Started Mar 28 01:45:16 PM PDT 24
Finished Mar 28 01:45:54 PM PDT 24
Peak memory 200404 kb
Host smart-ed12c057-14ae-4747-b101-c65b3906ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203719650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.203719650
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.155794998
Short name T197
Test name
Test status
Simulation time 21564785247 ps
CPU time 62.76 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:46:22 PM PDT 24
Peak memory 200480 kb
Host smart-5fce6bfb-f0dc-4914-a49a-bfd3f1758208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155794998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.155794998
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.7406781
Short name T444
Test name
Test status
Simulation time 17177968124 ps
CPU time 33.66 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:55 PM PDT 24
Peak memory 200496 kb
Host smart-48238b62-0f1f-425e-83d8-d681733d835e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7406781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.7406781
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2955719906
Short name T543
Test name
Test status
Simulation time 186937355714 ps
CPU time 1119.11 seconds
Started Mar 28 01:45:20 PM PDT 24
Finished Mar 28 02:04:00 PM PDT 24
Peak memory 200464 kb
Host smart-ac581ca2-382b-48fc-9400-27142dbfc5dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955719906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2955719906
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1026963630
Short name T877
Test name
Test status
Simulation time 5576470794 ps
CPU time 10.91 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:33 PM PDT 24
Peak memory 199996 kb
Host smart-6b8f2add-07de-4f83-90cb-2aeffbb8587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026963630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1026963630
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3694427585
Short name T1188
Test name
Test status
Simulation time 41518116948 ps
CPU time 82.02 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:46:46 PM PDT 24
Peak memory 200740 kb
Host smart-c4ddb568-88ec-41f7-b2c2-f2fdb1c94dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694427585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3694427585
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3416922568
Short name T498
Test name
Test status
Simulation time 25409075818 ps
CPU time 465.84 seconds
Started Mar 28 01:45:21 PM PDT 24
Finished Mar 28 01:53:07 PM PDT 24
Peak memory 200456 kb
Host smart-310b4cc7-7f3a-47a4-b7fc-0e55ef52bdb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416922568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3416922568
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3260193614
Short name T17
Test name
Test status
Simulation time 5625084362 ps
CPU time 12.98 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:35 PM PDT 24
Peak memory 198632 kb
Host smart-ad0e95f3-6613-4c65-8a2a-a209194e913e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260193614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3260193614
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.10540039
Short name T429
Test name
Test status
Simulation time 87346054949 ps
CPU time 145.37 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:47:49 PM PDT 24
Peak memory 200468 kb
Host smart-05558578-8810-4f82-bb8f-cbb49da4948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10540039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.10540039
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.956052453
Short name T435
Test name
Test status
Simulation time 4055565705 ps
CPU time 4.69 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:45:28 PM PDT 24
Peak memory 196800 kb
Host smart-aa523641-7009-4602-a7b5-6fa5aeacc29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956052453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.956052453
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.381681968
Short name T1058
Test name
Test status
Simulation time 915902981 ps
CPU time 2.39 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:21 PM PDT 24
Peak memory 199324 kb
Host smart-7404badc-a9b0-4efb-a2f4-08a5ff63e372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381681968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.381681968
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1069438735
Short name T885
Test name
Test status
Simulation time 315268948383 ps
CPU time 400.03 seconds
Started Mar 28 01:45:21 PM PDT 24
Finished Mar 28 01:52:01 PM PDT 24
Peak memory 208976 kb
Host smart-e71fe578-a22e-4491-a3d2-341ae508f070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069438735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1069438735
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.4243861900
Short name T1044
Test name
Test status
Simulation time 272808404405 ps
CPU time 943.7 seconds
Started Mar 28 01:45:23 PM PDT 24
Finished Mar 28 02:01:07 PM PDT 24
Peak memory 216980 kb
Host smart-d93164ad-16ba-4ee6-9698-f0c9a7c43dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243861900 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.4243861900
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1043836107
Short name T1167
Test name
Test status
Simulation time 6044053534 ps
CPU time 14.61 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:34 PM PDT 24
Peak memory 199944 kb
Host smart-82db05ad-6d7b-4213-b5b3-387359037911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043836107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1043836107
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1088362347
Short name T297
Test name
Test status
Simulation time 124288146044 ps
CPU time 36.17 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:45:58 PM PDT 24
Peak memory 200484 kb
Host smart-cce142e3-a309-45c2-bfd2-35a1e4e9d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088362347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1088362347
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3347089663
Short name T600
Test name
Test status
Simulation time 271840464885 ps
CPU time 21.83 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:49:13 PM PDT 24
Peak memory 199096 kb
Host smart-b141ab2b-0c6c-4371-a9d9-f305dd327e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347089663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3347089663
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3521506696
Short name T642
Test name
Test status
Simulation time 307085875527 ps
CPU time 851.66 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 02:03:04 PM PDT 24
Peak memory 231136 kb
Host smart-d36d3d3d-b754-435c-aa4c-cfa5ee20e73b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521506696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3521506696
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1219587264
Short name T2
Test name
Test status
Simulation time 22498826476 ps
CPU time 35.78 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:49:28 PM PDT 24
Peak memory 200492 kb
Host smart-59a37b6b-74a9-4a50-9a50-a3e8504665b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219587264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1219587264
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2604876090
Short name T54
Test name
Test status
Simulation time 83028792557 ps
CPU time 755.74 seconds
Started Mar 28 01:48:45 PM PDT 24
Finished Mar 28 02:01:21 PM PDT 24
Peak memory 229908 kb
Host smart-42d69b53-b8ae-4ec7-a3a4-f8e7fc20e27f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604876090 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2604876090
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1434176427
Short name T331
Test name
Test status
Simulation time 80923803753 ps
CPU time 116.35 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:50:45 PM PDT 24
Peak memory 200440 kb
Host smart-6340808f-9c1f-40fe-a633-740caf0c7e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434176427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1434176427
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3794303960
Short name T53
Test name
Test status
Simulation time 107971584957 ps
CPU time 871.83 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 02:03:18 PM PDT 24
Peak memory 225368 kb
Host smart-19135493-6d40-4ba6-bed8-cb6a8c6584e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794303960 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3794303960
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1818199147
Short name T179
Test name
Test status
Simulation time 84345597944 ps
CPU time 132.45 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:51:02 PM PDT 24
Peak memory 200448 kb
Host smart-4400f03a-a8ae-4a97-9c72-52a93564a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818199147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1818199147
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3424619846
Short name T1076
Test name
Test status
Simulation time 25783940700 ps
CPU time 17.71 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:49:09 PM PDT 24
Peak memory 200324 kb
Host smart-597a8907-a025-4962-8358-d3dc041637e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424619846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3424619846
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3495785655
Short name T226
Test name
Test status
Simulation time 223959897707 ps
CPU time 450.51 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:56:20 PM PDT 24
Peak memory 216964 kb
Host smart-75216b8d-78fd-4e03-862c-e8e129ba4abe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495785655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3495785655
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3997551623
Short name T816
Test name
Test status
Simulation time 41766320647 ps
CPU time 64.09 seconds
Started Mar 28 01:48:53 PM PDT 24
Finished Mar 28 01:49:57 PM PDT 24
Peak memory 200512 kb
Host smart-f3c0dd7a-78e1-4c37-8ba6-3f9b4e410dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997551623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3997551623
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3722614353
Short name T978
Test name
Test status
Simulation time 39638425022 ps
CPU time 229.96 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:52:43 PM PDT 24
Peak memory 208884 kb
Host smart-211d2aed-5015-42bb-8390-7bcb5f1ec5a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722614353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3722614353
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3267451502
Short name T252
Test name
Test status
Simulation time 20221108477 ps
CPU time 10.85 seconds
Started Mar 28 01:48:47 PM PDT 24
Finished Mar 28 01:48:58 PM PDT 24
Peak memory 200524 kb
Host smart-5fca7104-7228-4e50-b841-0df0c27d5bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267451502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3267451502
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.4174004335
Short name T976
Test name
Test status
Simulation time 25738474634 ps
CPU time 25.08 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:49:18 PM PDT 24
Peak memory 200480 kb
Host smart-de406531-2c0d-4a61-bdcd-4943824f7997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174004335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4174004335
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.4285721798
Short name T647
Test name
Test status
Simulation time 70130899139 ps
CPU time 1096.65 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 02:07:09 PM PDT 24
Peak memory 233616 kb
Host smart-ec044f52-fdbc-450b-afd7-0478608f268b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285721798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.4285721798
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3513027815
Short name T548
Test name
Test status
Simulation time 49877302515 ps
CPU time 78.79 seconds
Started Mar 28 01:48:46 PM PDT 24
Finished Mar 28 01:50:04 PM PDT 24
Peak memory 200448 kb
Host smart-4bdd36d3-a488-4081-befd-4ff3facff5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513027815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3513027815
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3364265287
Short name T1042
Test name
Test status
Simulation time 66969016419 ps
CPU time 169.82 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:51:39 PM PDT 24
Peak memory 216968 kb
Host smart-1edad754-5003-4a2d-9a35-e383c079c278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364265287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3364265287
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1901721898
Short name T656
Test name
Test status
Simulation time 13916210 ps
CPU time 0.58 seconds
Started Mar 28 01:45:27 PM PDT 24
Finished Mar 28 01:45:27 PM PDT 24
Peak memory 195900 kb
Host smart-5ef76890-2d0a-4ad6-9ae2-8e3cfd2a2cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901721898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1901721898
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2880600383
Short name T930
Test name
Test status
Simulation time 148617323817 ps
CPU time 83.79 seconds
Started Mar 28 01:45:30 PM PDT 24
Finished Mar 28 01:46:54 PM PDT 24
Peak memory 200316 kb
Host smart-9bee8eb6-2af6-4f20-9699-9153452aa502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880600383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2880600383
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.608508541
Short name T576
Test name
Test status
Simulation time 372590619646 ps
CPU time 35.22 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:45:59 PM PDT 24
Peak memory 200328 kb
Host smart-6267e5f0-d0a1-4066-a2ef-9656a20b9f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608508541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.608508541
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1223152671
Short name T1022
Test name
Test status
Simulation time 117474876196 ps
CPU time 51.67 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:46:16 PM PDT 24
Peak memory 200384 kb
Host smart-8eacb76d-11da-4508-9dda-8e121fe53149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223152671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1223152671
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2516940049
Short name T1019
Test name
Test status
Simulation time 35454568676 ps
CPU time 30.86 seconds
Started Mar 28 01:45:25 PM PDT 24
Finished Mar 28 01:45:56 PM PDT 24
Peak memory 200452 kb
Host smart-2234b6b4-c1e3-4902-a962-3c6b08546436
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516940049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2516940049
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1550823931
Short name T553
Test name
Test status
Simulation time 56120389015 ps
CPU time 287.47 seconds
Started Mar 28 01:45:27 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 200252 kb
Host smart-22ab3d0e-ad91-4eb4-9984-19859a4f0552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550823931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1550823931
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1421269525
Short name T1162
Test name
Test status
Simulation time 5789352434 ps
CPU time 9.7 seconds
Started Mar 28 01:45:30 PM PDT 24
Finished Mar 28 01:45:40 PM PDT 24
Peak memory 198440 kb
Host smart-94a0beaa-4f6e-4a00-ad6f-2912b3406e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421269525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1421269525
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2954615781
Short name T737
Test name
Test status
Simulation time 75386488766 ps
CPU time 81.45 seconds
Started Mar 28 01:45:30 PM PDT 24
Finished Mar 28 01:46:51 PM PDT 24
Peak memory 200576 kb
Host smart-9bf875fa-2e2c-420c-ba8a-f76d676633d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954615781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2954615781
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2922944554
Short name T1145
Test name
Test status
Simulation time 4944694435 ps
CPU time 141.45 seconds
Started Mar 28 01:45:30 PM PDT 24
Finished Mar 28 01:47:52 PM PDT 24
Peak memory 200344 kb
Host smart-9f738a84-a5f0-42f8-adfe-84ccfac504ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922944554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2922944554
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.867776285
Short name T339
Test name
Test status
Simulation time 5446181606 ps
CPU time 45.54 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:46:09 PM PDT 24
Peak memory 199112 kb
Host smart-cbf24751-3dd9-4b3c-8f77-6799cfe876a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867776285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.867776285
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3524204028
Short name T759
Test name
Test status
Simulation time 138636000877 ps
CPU time 84.79 seconds
Started Mar 28 01:45:26 PM PDT 24
Finished Mar 28 01:46:51 PM PDT 24
Peak memory 200336 kb
Host smart-8d44c326-5ccd-490c-abc8-62ecc49a36ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524204028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3524204028
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2271640995
Short name T724
Test name
Test status
Simulation time 4036549342 ps
CPU time 2.28 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:21 PM PDT 24
Peak memory 196796 kb
Host smart-b5bc1f60-b323-480f-b221-14b6d02c851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271640995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2271640995
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.287238703
Short name T1037
Test name
Test status
Simulation time 460469365 ps
CPU time 1.87 seconds
Started Mar 28 01:45:19 PM PDT 24
Finished Mar 28 01:45:21 PM PDT 24
Peak memory 199104 kb
Host smart-8a9c6e6c-d517-42b3-adb9-07bf263e9a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287238703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.287238703
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3158013341
Short name T598
Test name
Test status
Simulation time 296775038129 ps
CPU time 1104.49 seconds
Started Mar 28 01:45:27 PM PDT 24
Finished Mar 28 02:03:52 PM PDT 24
Peak memory 200164 kb
Host smart-b4cf2bba-b342-4046-8c3f-d9a2df8370e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158013341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3158013341
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2204349362
Short name T921
Test name
Test status
Simulation time 26980308047 ps
CPU time 394.68 seconds
Started Mar 28 01:45:26 PM PDT 24
Finished Mar 28 01:52:00 PM PDT 24
Peak memory 216128 kb
Host smart-c95661ac-6ef0-4683-ace9-655b85a98a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204349362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2204349362
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1271318608
Short name T1129
Test name
Test status
Simulation time 6310972874 ps
CPU time 9.36 seconds
Started Mar 28 01:45:24 PM PDT 24
Finished Mar 28 01:45:33 PM PDT 24
Peak memory 200480 kb
Host smart-a8019701-8138-440b-b4a9-49c2e616f38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271318608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1271318608
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2541309871
Short name T1051
Test name
Test status
Simulation time 80738601747 ps
CPU time 134.62 seconds
Started Mar 28 01:45:22 PM PDT 24
Finished Mar 28 01:47:36 PM PDT 24
Peak memory 200488 kb
Host smart-322d4a52-6327-4089-8c39-3ad2e7674773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541309871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2541309871
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3607106092
Short name T274
Test name
Test status
Simulation time 54258934347 ps
CPU time 75.99 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:50:08 PM PDT 24
Peak memory 200452 kb
Host smart-f769e579-f3ce-489e-b4e4-97da93ba6cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607106092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3607106092
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.784363987
Short name T561
Test name
Test status
Simulation time 49770667079 ps
CPU time 310.42 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:54:02 PM PDT 24
Peak memory 217000 kb
Host smart-04d0fb9d-8586-433d-8629-d5d5a6081c18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784363987 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.784363987
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1598110027
Short name T1132
Test name
Test status
Simulation time 27667334361 ps
CPU time 19.64 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 01:49:09 PM PDT 24
Peak memory 200440 kb
Host smart-14528890-2065-4d74-9552-cfd357918b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598110027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1598110027
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1177222012
Short name T953
Test name
Test status
Simulation time 69581127721 ps
CPU time 1227.41 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 02:09:19 PM PDT 24
Peak memory 225444 kb
Host smart-cca7eee3-930f-42fb-9884-5ec42ca57f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177222012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1177222012
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2197974404
Short name T454
Test name
Test status
Simulation time 23196194258 ps
CPU time 9.48 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:49:02 PM PDT 24
Peak memory 200492 kb
Host smart-39152192-64d5-4d46-acc0-4db5bacc1bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197974404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2197974404
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3888895370
Short name T701
Test name
Test status
Simulation time 187260968279 ps
CPU time 987.32 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 02:05:19 PM PDT 24
Peak memory 217172 kb
Host smart-a4cb135e-0a1c-41f4-b3b2-6c59bcbfa40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888895370 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3888895370
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1972973610
Short name T828
Test name
Test status
Simulation time 53404484484 ps
CPU time 21.14 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:49:12 PM PDT 24
Peak memory 200408 kb
Host smart-cd3d440d-3baa-4032-a110-ed1f7a73cf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972973610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1972973610
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.739759808
Short name T48
Test name
Test status
Simulation time 104176460335 ps
CPU time 1760.89 seconds
Started Mar 28 01:48:49 PM PDT 24
Finished Mar 28 02:18:10 PM PDT 24
Peak memory 227408 kb
Host smart-6aa2d994-2146-4c72-8ed8-08663697c314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739759808 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.739759808
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2127797982
Short name T765
Test name
Test status
Simulation time 89181010540 ps
CPU time 29.87 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:49:21 PM PDT 24
Peak memory 200308 kb
Host smart-0debbab2-ea81-4aec-80b7-f75681eddab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127797982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2127797982
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.4080439315
Short name T839
Test name
Test status
Simulation time 54453053162 ps
CPU time 278.82 seconds
Started Mar 28 01:48:57 PM PDT 24
Finished Mar 28 01:53:36 PM PDT 24
Peak memory 208672 kb
Host smart-3bf5f31d-812c-40a3-8884-1e994de510ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080439315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4080439315
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.171146663
Short name T1160
Test name
Test status
Simulation time 58437787816 ps
CPU time 87.66 seconds
Started Mar 28 01:48:56 PM PDT 24
Finished Mar 28 01:50:24 PM PDT 24
Peak memory 200496 kb
Host smart-a7c57e06-0c25-44ad-8588-067e5c8b22eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171146663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.171146663
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.872030114
Short name T933
Test name
Test status
Simulation time 29396230514 ps
CPU time 326.95 seconds
Started Mar 28 01:48:57 PM PDT 24
Finished Mar 28 01:54:24 PM PDT 24
Peak memory 217076 kb
Host smart-c4b7a82a-ea35-4f58-9811-9e75edb7305f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872030114 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.872030114
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1181640776
Short name T838
Test name
Test status
Simulation time 87905039694 ps
CPU time 81.11 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:50:12 PM PDT 24
Peak memory 200448 kb
Host smart-40ade5ed-57f8-49f9-84d6-2da8f95d2985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181640776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1181640776
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.981055414
Short name T21
Test name
Test status
Simulation time 19182577431 ps
CPU time 247.59 seconds
Started Mar 28 01:48:57 PM PDT 24
Finished Mar 28 01:53:05 PM PDT 24
Peak memory 216904 kb
Host smart-9f0d25ff-2108-48bb-9e0d-4fcf0839ee0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981055414 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.981055414
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2171801026
Short name T208
Test name
Test status
Simulation time 100510656219 ps
CPU time 71.81 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 01:50:02 PM PDT 24
Peak memory 200472 kb
Host smart-db4be57e-77d7-43f2-8018-162b68a73053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171801026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2171801026
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4291268556
Short name T146
Test name
Test status
Simulation time 219887545532 ps
CPU time 2046.74 seconds
Started Mar 28 01:48:50 PM PDT 24
Finished Mar 28 02:22:58 PM PDT 24
Peak memory 225300 kb
Host smart-c0ea4258-df36-42b7-85de-32a88baf19e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291268556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4291268556
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.939156458
Short name T772
Test name
Test status
Simulation time 104136943492 ps
CPU time 188.99 seconds
Started Mar 28 01:48:57 PM PDT 24
Finished Mar 28 01:52:06 PM PDT 24
Peak memory 200412 kb
Host smart-0410dd8f-303a-445a-8256-c7af87d2e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939156458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.939156458
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2354571148
Short name T793
Test name
Test status
Simulation time 185171766312 ps
CPU time 540.04 seconds
Started Mar 28 01:48:51 PM PDT 24
Finished Mar 28 01:57:51 PM PDT 24
Peak memory 217168 kb
Host smart-0a3cd8d3-b7f4-4e69-b084-ce15a7b5e500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354571148 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2354571148
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1908843959
Short name T817
Test name
Test status
Simulation time 18024119520 ps
CPU time 16.83 seconds
Started Mar 28 01:48:52 PM PDT 24
Finished Mar 28 01:49:09 PM PDT 24
Peak memory 200464 kb
Host smart-95384448-0c82-4024-8746-98ea94375464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908843959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1908843959
Directory /workspace/99.uart_fifo_reset/latest
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