Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	76155618	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26220406

1

T1

129

T2

75

T3

305227

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	92337888	1			T1	2377		T2	2744		T3	221001
values[0x0]	4746539	1			T1	196		T2	44		T3	108827
values[0x1]	5291597	1			T1	191		T2	43		T3	122003

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52359193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50016831

1

T1

934

T2

979

T3

356392

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	505361	1			T1	8		T2	8		T3	1736
valid_sources[0x01]	372935	1			T1	15		T2	7		T3	1743
valid_sources[0x02]	424883	1			T1	13		T2	5		T3	1811
valid_sources[0x03]	401870	1			T1	6		T2	8		T3	1771
valid_sources[0x04]	379044	1			T1	8		T2	10		T3	1767
valid_sources[0x05]	387931	1			T1	5		T2	9		T3	1797
valid_sources[0x06]	391630	1			T1	13		T2	15		T3	1759
valid_sources[0x07]	388331	1			T1	14		T2	10		T3	1756
valid_sources[0x08]	375549	1			T1	9		T2	10		T3	1754
valid_sources[0x09]	400590	1			T1	6		T2	13		T3	1749
valid_sources[0x0a]	391675	1			T1	12		T2	10		T3	1680
valid_sources[0x0b]	366604	1			T1	10		T2	10		T3	1815
valid_sources[0x0c]	391034	1			T1	10		T2	6		T3	1726
valid_sources[0x0d]	437530	1			T1	15		T2	18		T3	1772
valid_sources[0x0e]	402948	1			T1	14		T2	7		T3	1698
valid_sources[0x0f]	391981	1			T1	6		T2	12		T3	1826
valid_sources[0x10]	379856	1			T1	10		T2	13		T3	1775
valid_sources[0x11]	374058	1			T1	10		T2	10		T3	1774
valid_sources[0x12]	382725	1			T1	12		T2	20		T3	1801
valid_sources[0x13]	393022	1			T1	11		T2	8		T3	1684
valid_sources[0x14]	373841	1			T1	6		T2	10		T3	1743
valid_sources[0x15]	409869	1			T1	12		T2	7		T3	1753
valid_sources[0x16]	386334	1			T1	8		T2	13		T3	1668
valid_sources[0x17]	385709	1			T1	9		T2	11		T3	1812
valid_sources[0x18]	385450	1			T1	7		T2	12		T3	1827
valid_sources[0x19]	385893	1			T1	21		T2	14		T3	1793
valid_sources[0x1a]	395136	1			T1	16		T2	10		T3	1720
valid_sources[0x1b]	399862	1			T1	9		T2	17		T3	1699
valid_sources[0x1c]	364942	1			T1	13		T2	12		T3	1809
valid_sources[0x1d]	396635	1			T1	9		T2	9		T3	1804
valid_sources[0x1e]	416295	1			T1	10		T2	13		T3	1737
valid_sources[0x1f]	377423	1			T1	15		T2	13		T3	1780
valid_sources[0x20]	379390	1			T1	11		T2	14		T3	1810
valid_sources[0x21]	466082	1			T1	14		T2	13		T3	1813
valid_sources[0x22]	418092	1			T1	15		T2	8		T3	1708
valid_sources[0x23]	376138	1			T1	12		T2	6		T3	1794
valid_sources[0x24]	377514	1			T1	13		T2	5		T3	1773
valid_sources[0x25]	384651	1			T1	12		T2	5		T3	1797
valid_sources[0x26]	391381	1			T1	13		T2	12		T3	1801
valid_sources[0x27]	521294	1			T1	18		T2	9		T3	1698
valid_sources[0x28]	416360	1			T1	13		T2	17		T3	1761
valid_sources[0x29]	371997	1			T1	8		T2	9		T3	1788
valid_sources[0x2a]	431119	1			T1	7		T2	9		T3	1823
valid_sources[0x2b]	387053	1			T1	14		T2	9		T3	1734
valid_sources[0x2c]	422022	1			T1	7		T2	5		T3	1759
valid_sources[0x2d]	398697	1			T1	6		T2	5		T3	1769
valid_sources[0x2e]	382982	1			T1	10		T2	10		T3	1800
valid_sources[0x2f]	417920	1			T1	15		T2	9		T3	1718
valid_sources[0x30]	414533	1			T1	12		T2	3		T3	1729
valid_sources[0x31]	382059	1			T1	16		T2	6		T3	1792
valid_sources[0x32]	390186	1			T1	10		T2	15		T3	1782
valid_sources[0x33]	385526	1			T1	14		T2	12		T3	1786
valid_sources[0x34]	366404	1			T1	8		T2	11		T3	1732
valid_sources[0x35]	386090	1			T1	10		T2	17		T3	1669
valid_sources[0x36]	423230	1			T1	13		T2	9		T3	1823
valid_sources[0x37]	434794	1			T1	10		T2	12		T3	1717
valid_sources[0x38]	392634	1			T1	7		T2	10		T3	1802
valid_sources[0x39]	397553	1			T1	13		T2	17		T3	1727
valid_sources[0x3a]	382346	1			T1	13		T2	13		T3	1707
valid_sources[0x3b]	416191	1			T1	9		T2	6		T3	1698
valid_sources[0x3c]	400443	1			T1	9		T2	7		T3	1701
valid_sources[0x3d]	379667	1			T1	11		T2	12		T3	1745
valid_sources[0x3e]	404671	1			T1	13		T2	8		T3	1787
valid_sources[0x3f]	391323	1			T1	7		T2	13		T3	1757
valid_sources[0x40]	404982	1			T1	14		T2	9		T3	1806
valid_sources[0x41]	389004	1			T1	11		T2	7		T3	1714
valid_sources[0x42]	383832	1			T1	13		T2	7		T3	1816
valid_sources[0x43]	403556	1			T1	15		T2	10		T3	1766
valid_sources[0x44]	390557	1			T1	9		T2	13		T3	1803
valid_sources[0x45]	372332	1			T1	8		T2	8		T3	1758
valid_sources[0x46]	385217	1			T1	14		T2	14		T3	1779
valid_sources[0x47]	410267	1			T1	14		T2	6		T3	1750
valid_sources[0x48]	460474	1			T1	5		T2	10		T3	1783
valid_sources[0x49]	398242	1			T1	10		T2	19		T3	1780
valid_sources[0x4a]	374905	1			T1	20		T2	8		T3	1777
valid_sources[0x4b]	426670	1			T1	5		T2	15		T3	1701
valid_sources[0x4c]	375231	1			T1	13		T2	17		T3	1807
valid_sources[0x4d]	414539	1			T1	9		T2	8		T3	1758
valid_sources[0x4e]	463060	1			T1	14		T2	17		T3	1827
valid_sources[0x4f]	385535	1			T1	12		T2	7		T3	1745
valid_sources[0x50]	465890	1			T1	12		T2	17		T3	1746
valid_sources[0x51]	399402	1			T1	6		T2	12		T3	1763
valid_sources[0x52]	375592	1			T1	14		T2	18		T3	1725
valid_sources[0x53]	381211	1			T1	10		T2	13		T3	1773
valid_sources[0x54]	372449	1			T1	13		T2	12		T3	1776
valid_sources[0x55]	384481	1			T1	17		T2	6		T3	1806
valid_sources[0x56]	407482	1			T1	10		T2	6		T3	1714
valid_sources[0x57]	412905	1			T1	11		T2	18		T3	1787
valid_sources[0x58]	401898	1			T1	7		T2	8		T3	1788
valid_sources[0x59]	377496	1			T1	8		T2	11		T3	1795
valid_sources[0x5a]	389557	1			T1	3		T2	10		T3	1819
valid_sources[0x5b]	474876	1			T1	11		T2	7		T3	1787
valid_sources[0x5c]	399140	1			T1	11		T2	9		T3	1739
valid_sources[0x5d]	411388	1			T1	16		T2	15		T3	1725
valid_sources[0x5e]	405051	1			T1	13		T2	9		T3	1723
valid_sources[0x5f]	397544	1			T1	4		T2	6		T3	1718
valid_sources[0x60]	374856	1			T1	14		T2	14		T3	1797
valid_sources[0x61]	396117	1			T1	23		T2	8		T3	1807
valid_sources[0x62]	373450	1			T1	7		T2	15		T3	1709
valid_sources[0x63]	383287	1			T1	8		T2	16		T3	1836
valid_sources[0x64]	409302	1			T1	10		T2	15		T3	1690
valid_sources[0x65]	443684	1			T1	9		T2	12		T3	1770
valid_sources[0x66]	375800	1			T1	13		T2	7		T3	1826
valid_sources[0x67]	399157	1			T1	7		T2	7		T3	1713
valid_sources[0x68]	385683	1			T1	5		T2	14		T3	1766
valid_sources[0x69]	508973	1			T1	8		T2	8		T3	1724
valid_sources[0x6a]	378042	1			T1	13		T2	7		T3	1789
valid_sources[0x6b]	371634	1			T1	6		T2	11		T3	1824
valid_sources[0x6c]	369247	1			T1	9		T2	9		T3	1873
valid_sources[0x6d]	454101	1			T1	18		T2	10		T3	1758
valid_sources[0x6e]	402267	1			T1	15		T2	7		T3	1710
valid_sources[0x6f]	393836	1			T1	21		T2	21		T3	1694
valid_sources[0x70]	393340	1			T1	6		T2	11		T3	1807
valid_sources[0x71]	394467	1			T1	11		T2	11		T3	1817
valid_sources[0x72]	407871	1			T1	16		T2	13		T3	1720
valid_sources[0x73]	396146	1			T1	13		T2	10		T3	1789
valid_sources[0x74]	396039	1			T1	14		T2	13		T3	1827
valid_sources[0x75]	385137	1			T1	4		T2	4		T3	1830
valid_sources[0x76]	381770	1			T1	18		T2	17		T3	1759
valid_sources[0x77]	398972	1			T1	12		T2	12		T3	1712
valid_sources[0x78]	391813	1			T1	5		T2	13		T3	1865
valid_sources[0x79]	390311	1			T1	15		T2	14		T3	1771
valid_sources[0x7a]	375413	1			T1	14		T2	13		T3	1818
valid_sources[0x7b]	389595	1			T1	5		T2	9		T3	1777
valid_sources[0x7c]	366479	1			T1	8		T2	8		T3	1814
valid_sources[0x7d]	374148	1			T1	5		T2	7		T3	1841
valid_sources[0x7e]	418250	1			T1	11		T2	11		T3	1774
valid_sources[0x7f]	416320	1			T1	6		T2	5		T3	1774
valid_sources[0x80]	377337	1			T1	18		T2	11		T3	1773

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17332534

1

T1

22

T2

14

T3

92083

values[0x0]

all_enables

biggest_size

4474207

1

T1

79

T2

29

T3

107189

values[0x1]

all_enables

biggest_size

4413665

1

T1

28

T2

32

T3

105955