Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14636184	0	0
ctrl_rd_A	2147483647	287876	0	0
intr_enable_rd_A	2147483647	257580	0	0
ovrd_rd_A	2147483647	289642	0	0
timeout_ctrl_rd_A	2147483647	288536	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14636184	0	0
T3	917709	377219	0	0
T4	7975	0	0	0
T5	626673	0	0	0
T6	683601	0	0	0
T7	155117	0	0	0
T8	357199	0	0	0
T9	247539	0	0	0
T10	357429	0	0	0
T12	0	197228	0	0
T15	659059	0	0	0
T17	0	156699	0	0
T25	0	106126	0	0
T26	0	124603	0	0
T27	0	194238	0	0
T28	0	30223	0	0
T29	0	46994	0	0
T30	0	149134	0	0
T31	0	57312	0	0
T32	621855	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	287876	0	0
T26	551532	13862	0	0
T27	0	10380	0	0
T28	0	3476	0	0
T29	0	4758	0	0
T30	0	16900	0	0
T31	0	6433	0	0
T64	141159	0	0	0
T82	0	6791	0	0
T83	0	10139	0	0
T84	0	8785	0	0
T85	0	13372	0	0
T86	858110	0	0	0
T87	132929	0	0	0
T88	371725	0	0	0
T89	166394	0	0	0
T90	263899	0	0	0
T91	284772	0	0	0
T92	397401	0	0	0
T93	994936	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	257580	0	0
T26	551532	12235	0	0
T27	0	8932	0	0
T28	0	2985	0	0
T29	0	4306	0	0
T30	0	14612	0	0
T31	0	5761	0	0
T64	141159	0	0	0
T82	0	6358	0	0
T83	0	9171	0	0
T84	0	8315	0	0
T85	0	11512	0	0
T86	858110	0	0	0
T87	132929	0	0	0
T88	371725	0	0	0
T89	166394	0	0	0
T90	263899	0	0	0
T91	284772	0	0	0
T92	397401	0	0	0
T93	994936	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	289642	0	0
T26	551532	13563	0	0
T27	0	10659	0	0
T28	0	3485	0	0
T29	0	5028	0	0
T30	0	16610	0	0
T31	0	6514	0	0
T64	141159	0	0	0
T82	0	6925	0	0
T83	0	9943	0	0
T84	0	9085	0	0
T85	0	13642	0	0
T86	858110	0	0	0
T87	132929	0	0	0
T88	371725	0	0	0
T89	166394	0	0	0
T90	263899	0	0	0
T91	284772	0	0	0
T92	397401	0	0	0
T93	994936	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	288536	0	0
T26	551532	13787	0	0
T27	0	10123	0	0
T28	0	3262	0	0
T29	0	5076	0	0
T30	0	16645	0	0
T31	0	6364	0	0
T64	141159	0	0	0
T82	0	6556	0	0
T83	0	10051	0	0
T84	0	9199	0	0
T85	0	13527	0	0
T86	858110	0	0	0
T87	132929	0	0	0
T88	371725	0	0	0
T89	166394	0	0	0
T90	263899	0	0	0
T91	284772	0	0	0
T92	397401	0	0	0
T93	994936	0	0	0