Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.59


Total test records in report: 1320
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T1254 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2119728752 Mar 31 12:33:16 PM PDT 24 Mar 31 12:33:17 PM PDT 24 65496781 ps
T1255 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1675926014 Mar 31 12:33:04 PM PDT 24 Mar 31 12:33:06 PM PDT 24 354203619 ps
T101 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1780272991 Mar 31 12:33:30 PM PDT 24 Mar 31 12:33:31 PM PDT 24 334381701 ps
T1256 /workspace/coverage/cover_reg_top/46.uart_intr_test.2931063542 Mar 31 12:33:37 PM PDT 24 Mar 31 12:33:38 PM PDT 24 11709875 ps
T1257 /workspace/coverage/cover_reg_top/8.uart_intr_test.4150177842 Mar 31 12:33:15 PM PDT 24 Mar 31 12:33:16 PM PDT 24 22023641 ps
T1258 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2443394492 Mar 31 12:32:58 PM PDT 24 Mar 31 12:32:59 PM PDT 24 27645127 ps
T1259 /workspace/coverage/cover_reg_top/23.uart_intr_test.1032773952 Mar 31 12:33:32 PM PDT 24 Mar 31 12:33:32 PM PDT 24 16682496 ps
T1260 /workspace/coverage/cover_reg_top/0.uart_intr_test.1111635519 Mar 31 12:33:02 PM PDT 24 Mar 31 12:33:03 PM PDT 24 14597912 ps
T1261 /workspace/coverage/cover_reg_top/40.uart_intr_test.2347027214 Mar 31 12:33:40 PM PDT 24 Mar 31 12:33:41 PM PDT 24 14890363 ps
T1262 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1801115042 Mar 31 12:33:27 PM PDT 24 Mar 31 12:33:28 PM PDT 24 28884063 ps
T1263 /workspace/coverage/cover_reg_top/5.uart_tl_errors.995309740 Mar 31 12:33:12 PM PDT 24 Mar 31 12:33:14 PM PDT 24 99963977 ps
T1264 /workspace/coverage/cover_reg_top/10.uart_intr_test.3256612727 Mar 31 12:33:18 PM PDT 24 Mar 31 12:33:19 PM PDT 24 55685740 ps
T1265 /workspace/coverage/cover_reg_top/37.uart_intr_test.1845926406 Mar 31 12:33:40 PM PDT 24 Mar 31 12:33:41 PM PDT 24 15624307 ps
T1266 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3370024393 Mar 31 12:33:34 PM PDT 24 Mar 31 12:33:35 PM PDT 24 53381097 ps
T1267 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1106471520 Mar 31 12:33:25 PM PDT 24 Mar 31 12:33:26 PM PDT 24 35836900 ps
T1268 /workspace/coverage/cover_reg_top/49.uart_intr_test.3170076278 Mar 31 12:33:43 PM PDT 24 Mar 31 12:33:43 PM PDT 24 13749306 ps
T1269 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3333873199 Mar 31 12:33:21 PM PDT 24 Mar 31 12:33:23 PM PDT 24 66569551 ps
T1270 /workspace/coverage/cover_reg_top/27.uart_intr_test.2600891241 Mar 31 12:33:43 PM PDT 24 Mar 31 12:33:43 PM PDT 24 16353843 ps
T1271 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2645339148 Mar 31 12:33:01 PM PDT 24 Mar 31 12:33:02 PM PDT 24 110060227 ps
T1272 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.647316999 Mar 31 12:33:11 PM PDT 24 Mar 31 12:33:12 PM PDT 24 26372440 ps
T1273 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3552000230 Mar 31 12:33:01 PM PDT 24 Mar 31 12:33:02 PM PDT 24 182349755 ps
T1274 /workspace/coverage/cover_reg_top/36.uart_intr_test.2020294098 Mar 31 12:33:40 PM PDT 24 Mar 31 12:33:40 PM PDT 24 67025732 ps
T1275 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1753438545 Mar 31 12:33:15 PM PDT 24 Mar 31 12:33:17 PM PDT 24 150958062 ps
T1276 /workspace/coverage/cover_reg_top/26.uart_intr_test.841564339 Mar 31 12:33:37 PM PDT 24 Mar 31 12:33:38 PM PDT 24 90991574 ps
T1277 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3722114498 Mar 31 12:33:07 PM PDT 24 Mar 31 12:33:09 PM PDT 24 182585908 ps
T1278 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1594207340 Mar 31 12:33:17 PM PDT 24 Mar 31 12:33:18 PM PDT 24 50497323 ps
T1279 /workspace/coverage/cover_reg_top/9.uart_intr_test.3309035356 Mar 31 12:33:18 PM PDT 24 Mar 31 12:33:19 PM PDT 24 13390948 ps
T1280 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1450820213 Mar 31 12:33:06 PM PDT 24 Mar 31 12:33:08 PM PDT 24 68789232 ps
T102 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3385925741 Mar 31 12:33:09 PM PDT 24 Mar 31 12:33:10 PM PDT 24 141089915 ps
T1281 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1615434429 Mar 31 12:33:11 PM PDT 24 Mar 31 12:33:12 PM PDT 24 41104488 ps
T1282 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1464208430 Mar 31 12:33:31 PM PDT 24 Mar 31 12:33:32 PM PDT 24 170662995 ps
T1283 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1127516235 Mar 31 12:33:09 PM PDT 24 Mar 31 12:33:10 PM PDT 24 13448820 ps
T1284 /workspace/coverage/cover_reg_top/25.uart_intr_test.2673526889 Mar 31 12:33:39 PM PDT 24 Mar 31 12:33:40 PM PDT 24 24257515 ps
T1285 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2392387240 Mar 31 12:33:31 PM PDT 24 Mar 31 12:33:32 PM PDT 24 56301369 ps
T1286 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2827291358 Mar 31 12:33:27 PM PDT 24 Mar 31 12:33:28 PM PDT 24 51832573 ps
T1287 /workspace/coverage/cover_reg_top/3.uart_intr_test.3687136432 Mar 31 12:33:08 PM PDT 24 Mar 31 12:33:09 PM PDT 24 27932637 ps
T1288 /workspace/coverage/cover_reg_top/6.uart_intr_test.3287929532 Mar 31 12:33:10 PM PDT 24 Mar 31 12:33:11 PM PDT 24 14761018 ps
T1289 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2141326143 Mar 31 12:33:22 PM PDT 24 Mar 31 12:33:23 PM PDT 24 119996064 ps
T1290 /workspace/coverage/cover_reg_top/48.uart_intr_test.2044379921 Mar 31 12:33:42 PM PDT 24 Mar 31 12:33:42 PM PDT 24 32139271 ps
T1291 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1690867245 Mar 31 12:33:07 PM PDT 24 Mar 31 12:33:08 PM PDT 24 40112093 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3136412615 Mar 31 12:33:17 PM PDT 24 Mar 31 12:33:19 PM PDT 24 58585762 ps
T1293 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1549117573 Mar 31 12:33:28 PM PDT 24 Mar 31 12:33:30 PM PDT 24 251793074 ps
T1294 /workspace/coverage/cover_reg_top/41.uart_intr_test.3406618722 Mar 31 12:33:39 PM PDT 24 Mar 31 12:33:40 PM PDT 24 13728024 ps
T1295 /workspace/coverage/cover_reg_top/12.uart_intr_test.2071368270 Mar 31 12:33:26 PM PDT 24 Mar 31 12:33:26 PM PDT 24 18240646 ps
T1296 /workspace/coverage/cover_reg_top/19.uart_intr_test.3242783944 Mar 31 12:33:32 PM PDT 24 Mar 31 12:33:32 PM PDT 24 39324065 ps
T1297 /workspace/coverage/cover_reg_top/39.uart_intr_test.633525383 Mar 31 12:33:37 PM PDT 24 Mar 31 12:33:38 PM PDT 24 70625493 ps
T1298 /workspace/coverage/cover_reg_top/4.uart_intr_test.1204955894 Mar 31 12:33:10 PM PDT 24 Mar 31 12:33:11 PM PDT 24 43817086 ps
T1299 /workspace/coverage/cover_reg_top/18.uart_intr_test.3490729155 Mar 31 12:33:36 PM PDT 24 Mar 31 12:33:37 PM PDT 24 14570812 ps
T1300 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2320731472 Mar 31 12:33:31 PM PDT 24 Mar 31 12:33:32 PM PDT 24 50760850 ps
T1301 /workspace/coverage/cover_reg_top/13.uart_intr_test.869149690 Mar 31 12:33:23 PM PDT 24 Mar 31 12:33:24 PM PDT 24 15448624 ps
T1302 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2498678034 Mar 31 12:33:28 PM PDT 24 Mar 31 12:33:30 PM PDT 24 133898710 ps
T1303 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4260262381 Mar 31 12:32:59 PM PDT 24 Mar 31 12:32:59 PM PDT 24 15864904 ps
T1304 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.426911880 Mar 31 12:33:08 PM PDT 24 Mar 31 12:33:09 PM PDT 24 37669498 ps
T1305 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3967306133 Mar 31 12:33:15 PM PDT 24 Mar 31 12:33:15 PM PDT 24 67211043 ps
T1306 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.558546727 Mar 31 12:33:23 PM PDT 24 Mar 31 12:33:24 PM PDT 24 166372054 ps
T53 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2658960849 Mar 31 12:33:23 PM PDT 24 Mar 31 12:33:23 PM PDT 24 81617692 ps
T1307 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1193674747 Mar 31 12:33:06 PM PDT 24 Mar 31 12:33:07 PM PDT 24 20059694 ps
T1308 /workspace/coverage/cover_reg_top/31.uart_intr_test.3375110950 Mar 31 12:33:40 PM PDT 24 Mar 31 12:33:41 PM PDT 24 30656590 ps
T1309 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3089246567 Mar 31 12:33:30 PM PDT 24 Mar 31 12:33:30 PM PDT 24 19527508 ps
T1310 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.462911908 Mar 31 12:33:02 PM PDT 24 Mar 31 12:33:03 PM PDT 24 30974516 ps
T1311 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.507903152 Mar 31 12:33:33 PM PDT 24 Mar 31 12:33:34 PM PDT 24 66337012 ps
T1312 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.889071132 Mar 31 12:33:27 PM PDT 24 Mar 31 12:33:28 PM PDT 24 52484562 ps
T1313 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1732368315 Mar 31 12:33:14 PM PDT 24 Mar 31 12:33:15 PM PDT 24 32955846 ps
T1314 /workspace/coverage/cover_reg_top/44.uart_intr_test.2310738186 Mar 31 12:33:42 PM PDT 24 Mar 31 12:33:43 PM PDT 24 27157705 ps
T1315 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2696281596 Mar 31 12:33:00 PM PDT 24 Mar 31 12:33:01 PM PDT 24 56681547 ps
T1316 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3750829753 Mar 31 12:33:25 PM PDT 24 Mar 31 12:33:26 PM PDT 24 23722014 ps
T1317 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.495513470 Mar 31 12:33:11 PM PDT 24 Mar 31 12:33:12 PM PDT 24 59916633 ps
T1318 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2993408477 Mar 31 12:33:04 PM PDT 24 Mar 31 12:33:05 PM PDT 24 66033078 ps
T1319 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3191103201 Mar 31 12:33:31 PM PDT 24 Mar 31 12:33:32 PM PDT 24 29924500 ps
T1320 /workspace/coverage/cover_reg_top/45.uart_intr_test.2913875547 Mar 31 12:33:40 PM PDT 24 Mar 31 12:33:41 PM PDT 24 17720601 ps

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2155648982
Short name T3
Test name
Test status
Simulation time 382382197772 ps
CPU time 1136.74 seconds
Started Mar 31 03:21:48 PM PDT 24
Finished Mar 31 03:40:45 PM PDT 24
Peak memory 229292 kb
Host smart-5c355cc0-3de8-490f-bf66-14292fb4e616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155648982 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2155648982
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2597436393
Short name T30
Test name
Test status
Simulation time 564174922352 ps
CPU time 670.47 seconds
Started Mar 31 03:25:09 PM PDT 24
Finished Mar 31 03:36:20 PM PDT 24
Peak memory 214292 kb
Host smart-426ea306-75f1-4de3-97b0-fd031c12f0e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597436393 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2597436393
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.3567575976
Short name T111
Test name
Test status
Simulation time 116375870977 ps
CPU time 460.15 seconds
Started Mar 31 03:23:21 PM PDT 24
Finished Mar 31 03:31:02 PM PDT 24
Peak memory 200748 kb
Host smart-c17a2e76-ab08-454d-8bc4-366c61fbfa92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567575976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3567575976
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3707101626
Short name T12
Test name
Test status
Simulation time 92370366499 ps
CPU time 607.58 seconds
Started Mar 31 03:21:19 PM PDT 24
Finished Mar 31 03:31:27 PM PDT 24
Peak memory 215152 kb
Host smart-5d6961ed-7977-4450-8728-13de9253d522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707101626 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3707101626
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2666142802
Short name T25
Test name
Test status
Simulation time 109233451372 ps
CPU time 735.38 seconds
Started Mar 31 03:24:44 PM PDT 24
Finished Mar 31 03:37:00 PM PDT 24
Peak memory 217248 kb
Host smart-32138b55-8386-4c19-9097-54ca1da92fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666142802 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2666142802
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.1536102112
Short name T163
Test name
Test status
Simulation time 1502139050159 ps
CPU time 312.23 seconds
Started Mar 31 03:14:59 PM PDT 24
Finished Mar 31 03:20:12 PM PDT 24
Peak memory 216520 kb
Host smart-1a204549-84a6-4825-927e-b43c97a24495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536102112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1536102112
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3393661068
Short name T17
Test name
Test status
Simulation time 279679897136 ps
CPU time 598.26 seconds
Started Mar 31 03:25:04 PM PDT 24
Finished Mar 31 03:35:02 PM PDT 24
Peak memory 225464 kb
Host smart-6a4f4d04-6b8b-4ba6-b8c4-6904b634438e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393661068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3393661068
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2753829600
Short name T106
Test name
Test status
Simulation time 299643842513 ps
CPU time 829.01 seconds
Started Mar 31 03:25:10 PM PDT 24
Finished Mar 31 03:38:59 PM PDT 24
Peak memory 217220 kb
Host smart-b7f6d30d-5688-42ca-9665-dd5a4d6e9023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753829600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2753829600
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_alert_test.133154844
Short name T19
Test name
Test status
Simulation time 14040467 ps
CPU time 0.57 seconds
Started Mar 31 03:19:31 PM PDT 24
Finished Mar 31 03:19:32 PM PDT 24
Peak memory 195900 kb
Host smart-b48abbe8-5805-44c8-bb11-cb109cf65eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133154844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.133154844
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.257160546
Short name T26
Test name
Test status
Simulation time 112556770946 ps
CPU time 630.62 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:35:17 PM PDT 24
Peak memory 225788 kb
Host smart-8dd52d7d-410b-47a5-91a4-9c9ec98db2b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257160546 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.257160546
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3838101923
Short name T73
Test name
Test status
Simulation time 543566520 ps
CPU time 0.84 seconds
Started Mar 31 03:14:21 PM PDT 24
Finished Mar 31 03:14:22 PM PDT 24
Peak memory 218932 kb
Host smart-bc6ca3ea-1d61-4d43-829d-70fb324744ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838101923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3838101923
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/32.uart_stress_all.1440455511
Short name T104
Test name
Test status
Simulation time 207405579376 ps
CPU time 504.74 seconds
Started Mar 31 03:21:48 PM PDT 24
Finished Mar 31 03:30:13 PM PDT 24
Peak memory 200528 kb
Host smart-04d00983-5a6b-4b75-ba25-8c8ff703e656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440455511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1440455511
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.784694709
Short name T96
Test name
Test status
Simulation time 223925056228 ps
CPU time 220.44 seconds
Started Mar 31 03:28:00 PM PDT 24
Finished Mar 31 03:31:41 PM PDT 24
Peak memory 200456 kb
Host smart-e5651a47-6286-43b8-968b-fbbee93ea6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784694709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.784694709
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1226715360
Short name T70
Test name
Test status
Simulation time 639891858 ps
CPU time 1.23 seconds
Started Mar 31 12:33:14 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 199152 kb
Host smart-f83050c1-508c-4c7f-aa99-62d07704122c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226715360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1226715360
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/36.uart_stress_all.2811206717
Short name T134
Test name
Test status
Simulation time 329642748738 ps
CPU time 152.77 seconds
Started Mar 31 03:22:27 PM PDT 24
Finished Mar 31 03:25:00 PM PDT 24
Peak memory 200416 kb
Host smart-ec8aeb6c-2548-4df2-916d-911045fad344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811206717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2811206717
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2883398820
Short name T35
Test name
Test status
Simulation time 149099997174 ps
CPU time 707.6 seconds
Started Mar 31 03:19:03 PM PDT 24
Finished Mar 31 03:30:52 PM PDT 24
Peak memory 200484 kb
Host smart-af10b656-39b0-43f1-bd30-c9a9677954c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883398820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2883398820
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.232834879
Short name T184
Test name
Test status
Simulation time 101974872068 ps
CPU time 54.36 seconds
Started Mar 31 03:25:52 PM PDT 24
Finished Mar 31 03:26:46 PM PDT 24
Peak memory 200500 kb
Host smart-19788bb7-45c4-40d1-a725-d8c2bd94ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232834879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.232834879
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2006144033
Short name T48
Test name
Test status
Simulation time 94282292 ps
CPU time 0.55 seconds
Started Mar 31 12:33:29 PM PDT 24
Finished Mar 31 12:33:30 PM PDT 24
Peak memory 195264 kb
Host smart-a18d81a9-df3a-46ad-907e-95b838e209af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006144033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2006144033
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3079859825
Short name T113
Test name
Test status
Simulation time 43218774087 ps
CPU time 37.9 seconds
Started Mar 31 03:27:13 PM PDT 24
Finished Mar 31 03:27:51 PM PDT 24
Peak memory 200624 kb
Host smart-57beb531-4a46-4a2b-93d0-d4e47a889bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079859825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3079859825
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3382148569
Short name T126
Test name
Test status
Simulation time 428351961604 ps
CPU time 662.96 seconds
Started Mar 31 03:20:11 PM PDT 24
Finished Mar 31 03:31:14 PM PDT 24
Peak memory 228124 kb
Host smart-dd5f99a9-8b17-4182-b9f4-5e07c34518e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382148569 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3382148569
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1020272002
Short name T116
Test name
Test status
Simulation time 36648425476 ps
CPU time 17.47 seconds
Started Mar 31 03:18:16 PM PDT 24
Finished Mar 31 03:18:33 PM PDT 24
Peak memory 200396 kb
Host smart-49527333-7e72-4119-9d90-e716f66c7dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020272002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1020272002
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.705012679
Short name T99
Test name
Test status
Simulation time 331640445428 ps
CPU time 1207.28 seconds
Started Mar 31 03:19:04 PM PDT 24
Finished Mar 31 03:39:12 PM PDT 24
Peak memory 228444 kb
Host smart-447ddd1d-2f64-492b-8f8e-e362d9ad1cf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705012679 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.705012679
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.758674908
Short name T148
Test name
Test status
Simulation time 99302290026 ps
CPU time 37.84 seconds
Started Mar 31 03:27:52 PM PDT 24
Finished Mar 31 03:28:30 PM PDT 24
Peak memory 200512 kb
Host smart-652d2c70-d46c-482e-849a-a6d3ac7ad9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758674908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.758674908
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1088831023
Short name T131
Test name
Test status
Simulation time 208162499731 ps
CPU time 977.67 seconds
Started Mar 31 03:23:54 PM PDT 24
Finished Mar 31 03:40:11 PM PDT 24
Peak memory 225620 kb
Host smart-676ba80b-5e18-4369-ad50-aeca9fd885bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088831023 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1088831023
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3398050739
Short name T242
Test name
Test status
Simulation time 133578968121 ps
CPU time 240.46 seconds
Started Mar 31 03:16:13 PM PDT 24
Finished Mar 31 03:20:14 PM PDT 24
Peak memory 200420 kb
Host smart-e160f0a6-7071-4237-8bbf-bd995f694c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398050739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3398050739
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3593404717
Short name T280
Test name
Test status
Simulation time 74381232538 ps
CPU time 247.13 seconds
Started Mar 31 03:26:23 PM PDT 24
Finished Mar 31 03:30:30 PM PDT 24
Peak memory 200524 kb
Host smart-31a5a140-6739-49c8-8ad4-0c26e3ea4b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593404717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3593404717
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3032264144
Short name T92
Test name
Test status
Simulation time 39740191060 ps
CPU time 69.08 seconds
Started Mar 31 03:15:56 PM PDT 24
Finished Mar 31 03:17:06 PM PDT 24
Peak memory 200512 kb
Host smart-735ce783-d5c3-4c8c-89a2-9eaf0d4f4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032264144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3032264144
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1536363428
Short name T221
Test name
Test status
Simulation time 115793799843 ps
CPU time 387.68 seconds
Started Mar 31 03:18:33 PM PDT 24
Finished Mar 31 03:25:01 PM PDT 24
Peak memory 200516 kb
Host smart-fcc71003-f8d4-42b5-9fdb-b21a4f730df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536363428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1536363428
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2520684456
Short name T144
Test name
Test status
Simulation time 88294022463 ps
CPU time 77.11 seconds
Started Mar 31 03:28:03 PM PDT 24
Finished Mar 31 03:29:21 PM PDT 24
Peak memory 200496 kb
Host smart-d9bda705-6a5d-444a-8436-486fccee072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520684456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2520684456
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3425933516
Short name T136
Test name
Test status
Simulation time 182230829884 ps
CPU time 854.05 seconds
Started Mar 31 03:23:05 PM PDT 24
Finished Mar 31 03:37:19 PM PDT 24
Peak memory 200504 kb
Host smart-858ffa63-111a-4444-b02d-9deeb1024d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425933516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3425933516
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.316342844
Short name T161
Test name
Test status
Simulation time 177313727131 ps
CPU time 79.78 seconds
Started Mar 31 03:20:54 PM PDT 24
Finished Mar 31 03:22:14 PM PDT 24
Peak memory 200472 kb
Host smart-330b060c-100c-4940-b68e-13d74a45a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316342844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.316342844
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2185458104
Short name T69
Test name
Test status
Simulation time 159438743 ps
CPU time 0.95 seconds
Started Mar 31 12:33:11 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 198860 kb
Host smart-08c9683e-40cb-415f-ad29-f989742bb618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185458104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2185458104
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.58619171
Short name T209
Test name
Test status
Simulation time 31825640651 ps
CPU time 37.4 seconds
Started Mar 31 03:18:59 PM PDT 24
Finished Mar 31 03:19:36 PM PDT 24
Peak memory 200456 kb
Host smart-ee97a32d-bee8-4d44-9323-3eb79d0c4ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58619171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.58619171
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2998634053
Short name T118
Test name
Test status
Simulation time 18420310468 ps
CPU time 13.66 seconds
Started Mar 31 03:26:04 PM PDT 24
Finished Mar 31 03:26:18 PM PDT 24
Peak memory 200532 kb
Host smart-8a796fd0-b14f-447c-a0b0-da1568fb78bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998634053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2998634053
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1053283960
Short name T168
Test name
Test status
Simulation time 158492154746 ps
CPU time 75.23 seconds
Started Mar 31 03:26:29 PM PDT 24
Finished Mar 31 03:27:45 PM PDT 24
Peak memory 200476 kb
Host smart-581396eb-52e5-403c-88f8-d0d62c085c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053283960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1053283960
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.30909329
Short name T112
Test name
Test status
Simulation time 157866946796 ps
CPU time 39.67 seconds
Started Mar 31 03:27:19 PM PDT 24
Finished Mar 31 03:27:59 PM PDT 24
Peak memory 200488 kb
Host smart-91e6a9af-80ea-46aa-bc9c-8ba20c5930f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30909329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.30909329
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1222390512
Short name T139
Test name
Test status
Simulation time 106755922195 ps
CPU time 47.56 seconds
Started Mar 31 03:26:39 PM PDT 24
Finished Mar 31 03:27:27 PM PDT 24
Peak memory 200520 kb
Host smart-48b04494-30d0-4750-8a8b-911725e00889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222390512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1222390512
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3792624537
Short name T120
Test name
Test status
Simulation time 161187588551 ps
CPU time 354.73 seconds
Started Mar 31 03:26:58 PM PDT 24
Finished Mar 31 03:32:53 PM PDT 24
Peak memory 200564 kb
Host smart-3aa4f370-6399-4089-bfb3-5cd42a9260f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792624537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3792624537
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3930136861
Short name T127
Test name
Test status
Simulation time 84620326801 ps
CPU time 152.32 seconds
Started Mar 31 03:22:38 PM PDT 24
Finished Mar 31 03:25:10 PM PDT 24
Peak memory 200416 kb
Host smart-a0bcd5d5-bfea-4377-9836-1e9d6cc9c322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930136861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3930136861
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_stress_all.1601357785
Short name T155
Test name
Test status
Simulation time 199266247491 ps
CPU time 167.72 seconds
Started Mar 31 03:16:29 PM PDT 24
Finished Mar 31 03:19:17 PM PDT 24
Peak memory 216672 kb
Host smart-33c859a1-0195-48cc-a20c-6d75d04b9c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601357785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1601357785
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all.3414185564
Short name T167
Test name
Test status
Simulation time 97615252192 ps
CPU time 62.82 seconds
Started Mar 31 03:17:26 PM PDT 24
Finished Mar 31 03:18:29 PM PDT 24
Peak memory 200444 kb
Host smart-6986a9a0-c6d9-444e-acff-3aad1cae8c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414185564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3414185564
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1943918197
Short name T238
Test name
Test status
Simulation time 9997423684 ps
CPU time 22.9 seconds
Started Mar 31 03:25:53 PM PDT 24
Finished Mar 31 03:26:16 PM PDT 24
Peak memory 200504 kb
Host smart-d9d317ce-2ed6-4aa0-92cd-77d316e24270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943918197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1943918197
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1062069983
Short name T43
Test name
Test status
Simulation time 378180330610 ps
CPU time 799.16 seconds
Started Mar 31 03:19:17 PM PDT 24
Finished Mar 31 03:32:37 PM PDT 24
Peak memory 225380 kb
Host smart-86a8cca4-a367-4fad-af1b-e850d5f2e4e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062069983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1062069983
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2575354290
Short name T201
Test name
Test status
Simulation time 129709652516 ps
CPU time 66.97 seconds
Started Mar 31 03:20:34 PM PDT 24
Finished Mar 31 03:21:41 PM PDT 24
Peak memory 200496 kb
Host smart-47f471e5-a0d9-44ab-a26e-c3aa1709c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575354290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2575354290
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3404521203
Short name T122
Test name
Test status
Simulation time 212758874490 ps
CPU time 286.36 seconds
Started Mar 31 03:27:47 PM PDT 24
Finished Mar 31 03:32:33 PM PDT 24
Peak memory 200500 kb
Host smart-c48a1924-5309-4536-92df-8ea6d613d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404521203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3404521203
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2654782050
Short name T212
Test name
Test status
Simulation time 133935117599 ps
CPU time 136.59 seconds
Started Mar 31 03:26:05 PM PDT 24
Finished Mar 31 03:28:22 PM PDT 24
Peak memory 200536 kb
Host smart-1afe0c14-82aa-4c89-a8f0-7a1a1ab6c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654782050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2654782050
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.356394146
Short name T194
Test name
Test status
Simulation time 34040045665 ps
CPU time 55.74 seconds
Started Mar 31 03:17:44 PM PDT 24
Finished Mar 31 03:18:40 PM PDT 24
Peak memory 200528 kb
Host smart-92198cff-7543-4e4f-a5e7-9b9e2a2f2a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356394146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.356394146
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2723168922
Short name T1016
Test name
Test status
Simulation time 27698322971 ps
CPU time 53.63 seconds
Started Mar 31 03:26:09 PM PDT 24
Finished Mar 31 03:27:03 PM PDT 24
Peak memory 200452 kb
Host smart-6666adf5-7ef6-40aa-b72f-91f017d25f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723168922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2723168922
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2396072868
Short name T82
Test name
Test status
Simulation time 277589091802 ps
CPU time 296.47 seconds
Started Mar 31 03:18:31 PM PDT 24
Finished Mar 31 03:23:28 PM PDT 24
Peak memory 209288 kb
Host smart-3cda9f3b-5814-4031-8771-1f5aa31932d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396072868 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2396072868
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1923030732
Short name T172
Test name
Test status
Simulation time 246820463606 ps
CPU time 29.76 seconds
Started Mar 31 03:26:38 PM PDT 24
Finished Mar 31 03:27:08 PM PDT 24
Peak memory 200484 kb
Host smart-d24d1e1b-4543-4f87-b23b-e0699919d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923030732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1923030732
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.4158354206
Short name T230
Test name
Test status
Simulation time 203793347033 ps
CPU time 542.21 seconds
Started Mar 31 03:27:31 PM PDT 24
Finished Mar 31 03:36:33 PM PDT 24
Peak memory 200452 kb
Host smart-0d2da32c-0c75-4612-9c2f-a3f1556f8e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158354206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4158354206
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1060511598
Short name T214
Test name
Test status
Simulation time 109485700392 ps
CPU time 82.25 seconds
Started Mar 31 03:25:10 PM PDT 24
Finished Mar 31 03:26:32 PM PDT 24
Peak memory 200408 kb
Host smart-f48d4d8b-2847-47c4-a0b4-5600d118d369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060511598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1060511598
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3006390185
Short name T225
Test name
Test status
Simulation time 124813390953 ps
CPU time 170.14 seconds
Started Mar 31 03:14:03 PM PDT 24
Finished Mar 31 03:16:53 PM PDT 24
Peak memory 200532 kb
Host smart-61ebe8c4-ead0-4ddf-b701-2a9a4acef13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006390185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3006390185
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2855126047
Short name T156
Test name
Test status
Simulation time 170002000249 ps
CPU time 253.52 seconds
Started Mar 31 03:26:02 PM PDT 24
Finished Mar 31 03:30:15 PM PDT 24
Peak memory 200540 kb
Host smart-ecfcecf2-00bc-4f8e-bec3-f7505ee69ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855126047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2855126047
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.10702970
Short name T193
Test name
Test status
Simulation time 23493590105 ps
CPU time 35.11 seconds
Started Mar 31 03:26:04 PM PDT 24
Finished Mar 31 03:26:40 PM PDT 24
Peak memory 200424 kb
Host smart-a319691e-f562-4116-b8da-2263fc73d036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10702970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.10702970
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.4182355367
Short name T202
Test name
Test status
Simulation time 53616384966 ps
CPU time 81.39 seconds
Started Mar 31 03:26:17 PM PDT 24
Finished Mar 31 03:27:39 PM PDT 24
Peak memory 200416 kb
Host smart-81da13cc-8c9f-4f16-ad14-4dbec0afbb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182355367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4182355367
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2939234394
Short name T185
Test name
Test status
Simulation time 33194973841 ps
CPU time 49.29 seconds
Started Mar 31 03:26:28 PM PDT 24
Finished Mar 31 03:27:18 PM PDT 24
Peak memory 200404 kb
Host smart-145e5740-b273-4d01-a037-d733b1017dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939234394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2939234394
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2504302623
Short name T845
Test name
Test status
Simulation time 31545491368 ps
CPU time 37.26 seconds
Started Mar 31 03:26:29 PM PDT 24
Finished Mar 31 03:27:07 PM PDT 24
Peak memory 200436 kb
Host smart-dc4d5c12-b4f1-41bb-8a73-11a30a096785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504302623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2504302623
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2867971603
Short name T226
Test name
Test status
Simulation time 27922539098 ps
CPU time 44.86 seconds
Started Mar 31 03:26:42 PM PDT 24
Finished Mar 31 03:27:27 PM PDT 24
Peak memory 200496 kb
Host smart-83af3d21-f7f7-45fd-baeb-88f3434c3a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867971603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2867971603
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4002935027
Short name T235
Test name
Test status
Simulation time 129393839079 ps
CPU time 88.83 seconds
Started Mar 31 03:14:47 PM PDT 24
Finished Mar 31 03:16:16 PM PDT 24
Peak memory 200436 kb
Host smart-1d3852bf-bbf9-4f47-8515-d1ae41eaef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002935027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4002935027
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1255069307
Short name T228
Test name
Test status
Simulation time 38579253659 ps
CPU time 63.57 seconds
Started Mar 31 03:27:14 PM PDT 24
Finished Mar 31 03:28:18 PM PDT 24
Peak memory 200472 kb
Host smart-b41e2e46-a600-4c7d-a24c-8b781ffdc82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255069307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1255069307
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.233524253
Short name T110
Test name
Test status
Simulation time 23901879765 ps
CPU time 40.2 seconds
Started Mar 31 03:27:13 PM PDT 24
Finished Mar 31 03:27:53 PM PDT 24
Peak memory 200512 kb
Host smart-82630d0c-d079-4162-a2dd-0018ca9186a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233524253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.233524253
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2029481291
Short name T233
Test name
Test status
Simulation time 36465530923 ps
CPU time 57.4 seconds
Started Mar 31 03:27:24 PM PDT 24
Finished Mar 31 03:28:22 PM PDT 24
Peak memory 200340 kb
Host smart-715cef20-bd3f-4bb3-8e2c-191256477e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029481291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2029481291
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1830643722
Short name T240
Test name
Test status
Simulation time 14562088805 ps
CPU time 12.98 seconds
Started Mar 31 03:27:35 PM PDT 24
Finished Mar 31 03:27:48 PM PDT 24
Peak memory 200528 kb
Host smart-1feb6f76-4a31-4ffe-9866-ceefb28ce434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830643722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1830643722
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1579821254
Short name T234
Test name
Test status
Simulation time 153142912683 ps
CPU time 279.47 seconds
Started Mar 31 03:27:40 PM PDT 24
Finished Mar 31 03:32:20 PM PDT 24
Peak memory 200444 kb
Host smart-445e2a73-100e-4227-bda3-c4275db6930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579821254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1579821254
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3958055746
Short name T182
Test name
Test status
Simulation time 67872707912 ps
CPU time 35.02 seconds
Started Mar 31 03:28:05 PM PDT 24
Finished Mar 31 03:28:40 PM PDT 24
Peak memory 200464 kb
Host smart-27c481ef-e808-47d6-a399-20ad2c78344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958055746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3958055746
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.796840051
Short name T215
Test name
Test status
Simulation time 251797710194 ps
CPU time 31.1 seconds
Started Mar 31 03:21:34 PM PDT 24
Finished Mar 31 03:22:05 PM PDT 24
Peak memory 200508 kb
Host smart-035c2524-e4b8-474b-9574-29a8efb4f3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796840051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.796840051
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1976829955
Short name T239
Test name
Test status
Simulation time 80414332356 ps
CPU time 21.51 seconds
Started Mar 31 03:21:49 PM PDT 24
Finished Mar 31 03:22:11 PM PDT 24
Peak memory 200400 kb
Host smart-359d86ff-d4ff-474b-85ef-a92473254a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976829955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1976829955
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3192073209
Short name T231
Test name
Test status
Simulation time 251850814177 ps
CPU time 650.4 seconds
Started Mar 31 03:24:49 PM PDT 24
Finished Mar 31 03:35:40 PM PDT 24
Peak memory 217240 kb
Host smart-ff93b49c-5c55-4820-bbb6-9518240bab86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192073209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3192073209
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1711818210
Short name T186
Test name
Test status
Simulation time 19681964651 ps
CPU time 16.59 seconds
Started Mar 31 03:16:15 PM PDT 24
Finished Mar 31 03:16:32 PM PDT 24
Peak memory 200492 kb
Host smart-ceaa09a8-34b9-4dc4-ad2b-949525f9867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711818210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1711818210
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.897559568
Short name T166
Test name
Test status
Simulation time 6469138598 ps
CPU time 12.17 seconds
Started Mar 31 03:24:55 PM PDT 24
Finished Mar 31 03:25:08 PM PDT 24
Peak memory 200392 kb
Host smart-e4665827-9b03-462b-921e-b161a1ee692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897559568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.897559568
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2796437952
Short name T1216
Test name
Test status
Simulation time 57676769 ps
CPU time 0.65 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 194420 kb
Host smart-9608370a-d2e8-43e7-9e3b-5c05011bd9e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796437952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2796437952
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3408689069
Short name T1185
Test name
Test status
Simulation time 35059677 ps
CPU time 1.34 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:33:01 PM PDT 24
Peak memory 197396 kb
Host smart-c03fe0dd-a8cd-42d5-9750-56fef9ef672e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408689069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3408689069
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4260262381
Short name T1303
Test name
Test status
Simulation time 15864904 ps
CPU time 0.58 seconds
Started Mar 31 12:32:59 PM PDT 24
Finished Mar 31 12:32:59 PM PDT 24
Peak memory 195292 kb
Host smart-b75d1bc0-651a-4dc0-b6e8-107f28c7561c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260262381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4260262381
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2645339148
Short name T1271
Test name
Test status
Simulation time 110060227 ps
CPU time 0.94 seconds
Started Mar 31 12:33:01 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 199684 kb
Host smart-64ccbb22-8e25-4e16-915d-e95cb26eebe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645339148 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2645339148
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1554497075
Short name T1245
Test name
Test status
Simulation time 19954284 ps
CPU time 0.61 seconds
Started Mar 31 12:33:03 PM PDT 24
Finished Mar 31 12:33:04 PM PDT 24
Peak memory 195256 kb
Host smart-920f3d37-f5d4-4c2c-bfaf-868f65fc77ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554497075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1554497075
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1111635519
Short name T1260
Test name
Test status
Simulation time 14597912 ps
CPU time 0.64 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 193984 kb
Host smart-c89727ef-ce39-4091-a56a-2295dadef98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111635519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1111635519
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1884027247
Short name T56
Test name
Test status
Simulation time 130185715 ps
CPU time 0.7 seconds
Started Mar 31 12:33:06 PM PDT 24
Finished Mar 31 12:33:08 PM PDT 24
Peak memory 196952 kb
Host smart-24818f7d-7135-4f7f-b3cb-f280d1ebf6bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884027247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1884027247
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1675926014
Short name T1255
Test name
Test status
Simulation time 354203619 ps
CPU time 1.96 seconds
Started Mar 31 12:33:04 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 199660 kb
Host smart-e2364cca-fbbe-4efd-9c23-ed5255f2dac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675926014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1675926014
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3564953084
Short name T66
Test name
Test status
Simulation time 286044561 ps
CPU time 1.23 seconds
Started Mar 31 12:32:58 PM PDT 24
Finished Mar 31 12:32:59 PM PDT 24
Peak memory 199044 kb
Host smart-f2ea7382-d56a-48b6-8598-b9d3fc469ade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564953084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3564953084
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.462911908
Short name T1310
Test name
Test status
Simulation time 30974516 ps
CPU time 0.77 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 196048 kb
Host smart-4336c649-3364-447e-bad1-639a6f5cb38a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462911908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.462911908
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1767592162
Short name T49
Test name
Test status
Simulation time 227383654 ps
CPU time 2.45 seconds
Started Mar 31 12:33:07 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 197672 kb
Host smart-b76d2c47-2ed3-456b-a478-efbd69df0f27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767592162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1767592162
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.337558534
Short name T1243
Test name
Test status
Simulation time 26868785 ps
CPU time 0.59 seconds
Started Mar 31 12:33:05 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 195252 kb
Host smart-5afdc9d1-7b27-45d1-bed2-e7e01ef16ccf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337558534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.337558534
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2696281596
Short name T1315
Test name
Test status
Simulation time 56681547 ps
CPU time 0.66 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:33:01 PM PDT 24
Peak memory 197828 kb
Host smart-7b73caf9-90eb-4598-934b-c735e8804edf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696281596 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2696281596
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2915406557
Short name T1209
Test name
Test status
Simulation time 29152430 ps
CPU time 0.56 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 195284 kb
Host smart-0334c160-65cf-409d-824f-3f648563a18e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915406557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2915406557
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2286542005
Short name T1205
Test name
Test status
Simulation time 15604125 ps
CPU time 0.64 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 194196 kb
Host smart-2d4ee517-98a4-4faa-bfc7-db70b10afb2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286542005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2286542005
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2330093157
Short name T1213
Test name
Test status
Simulation time 58503909 ps
CPU time 0.74 seconds
Started Mar 31 12:33:05 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 196788 kb
Host smart-2670e959-ec9e-400b-9331-77b0d674d87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330093157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2330093157
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3009837342
Short name T1230
Test name
Test status
Simulation time 133135562 ps
CPU time 1.17 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:04 PM PDT 24
Peak memory 199876 kb
Host smart-ceed2012-c272-48cc-899f-671044d27c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009837342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3009837342
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3552000230
Short name T1273
Test name
Test status
Simulation time 182349755 ps
CPU time 1.38 seconds
Started Mar 31 12:33:01 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 199252 kb
Host smart-b6aa4896-fc52-480a-a8be-6fe934e8e0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552000230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3552000230
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3750829753
Short name T1316
Test name
Test status
Simulation time 23722014 ps
CPU time 0.77 seconds
Started Mar 31 12:33:25 PM PDT 24
Finished Mar 31 12:33:26 PM PDT 24
Peak memory 199256 kb
Host smart-404065a2-c2d0-4a58-824c-08aae97ecfc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750829753 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3750829753
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1730476965
Short name T1211
Test name
Test status
Simulation time 43156026 ps
CPU time 0.64 seconds
Started Mar 31 12:33:13 PM PDT 24
Finished Mar 31 12:33:14 PM PDT 24
Peak memory 195432 kb
Host smart-ef51a7cb-30c5-4b11-966a-73265488fbb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730476965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1730476965
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3256612727
Short name T1264
Test name
Test status
Simulation time 55685740 ps
CPU time 0.61 seconds
Started Mar 31 12:33:18 PM PDT 24
Finished Mar 31 12:33:19 PM PDT 24
Peak memory 194256 kb
Host smart-1ed4f644-88da-4dc5-9c31-612a73eee5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256612727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3256612727
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2758352226
Short name T57
Test name
Test status
Simulation time 16105707 ps
CPU time 0.64 seconds
Started Mar 31 12:33:27 PM PDT 24
Finished Mar 31 12:33:28 PM PDT 24
Peak memory 195368 kb
Host smart-795f73c3-2564-4f46-a30d-087d77b6d078
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758352226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2758352226
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1732368315
Short name T1313
Test name
Test status
Simulation time 32955846 ps
CPU time 0.85 seconds
Started Mar 31 12:33:14 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 199580 kb
Host smart-5f1d16e9-ece0-466d-8606-1740dfdf036f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732368315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1732368315
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.825133003
Short name T1202
Test name
Test status
Simulation time 108878650 ps
CPU time 0.99 seconds
Started Mar 31 12:33:14 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 198732 kb
Host smart-6199ef54-1963-4290-82eb-fea9f17a88bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825133003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.825133003
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.938536544
Short name T1193
Test name
Test status
Simulation time 17472525 ps
CPU time 0.67 seconds
Started Mar 31 12:33:24 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 198108 kb
Host smart-158e59d4-b405-4a4e-8fe3-fc6cf20452a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938536544 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.938536544
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2658960849
Short name T53
Test name
Test status
Simulation time 81617692 ps
CPU time 0.58 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:23 PM PDT 24
Peak memory 195264 kb
Host smart-8c96573e-a368-4c72-902d-e000dc0c1d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658960849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2658960849
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3331450777
Short name T1234
Test name
Test status
Simulation time 49177634 ps
CPU time 0.58 seconds
Started Mar 31 12:33:25 PM PDT 24
Finished Mar 31 12:33:25 PM PDT 24
Peak memory 194172 kb
Host smart-bb10845a-b508-4c27-b546-53a2e44c1231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331450777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3331450777
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2135583145
Short name T1219
Test name
Test status
Simulation time 16720197 ps
CPU time 0.71 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 196900 kb
Host smart-2f432c2c-f7e3-41b1-9fa1-89fe7d150fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135583145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2135583145
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3491903101
Short name T1253
Test name
Test status
Simulation time 102688489 ps
CPU time 1.9 seconds
Started Mar 31 12:33:21 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 199772 kb
Host smart-35f81652-1b4c-42b6-b022-25834eb79186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491903101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3491903101
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.558546727
Short name T1306
Test name
Test status
Simulation time 166372054 ps
CPU time 1.25 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 198912 kb
Host smart-2296ced5-2657-4b65-b485-783cff97421e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558546727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.558546727
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.844761192
Short name T1242
Test name
Test status
Simulation time 227175725 ps
CPU time 0.65 seconds
Started Mar 31 12:33:28 PM PDT 24
Finished Mar 31 12:33:29 PM PDT 24
Peak memory 197260 kb
Host smart-c3ec83d7-a492-4081-9fb3-dcf849013cad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844761192 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.844761192
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2827291358
Short name T1286
Test name
Test status
Simulation time 51832573 ps
CPU time 0.61 seconds
Started Mar 31 12:33:27 PM PDT 24
Finished Mar 31 12:33:28 PM PDT 24
Peak memory 195040 kb
Host smart-eba5dd7d-6773-4947-a188-e2b302583578
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827291358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2827291358
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2071368270
Short name T1295
Test name
Test status
Simulation time 18240646 ps
CPU time 0.56 seconds
Started Mar 31 12:33:26 PM PDT 24
Finished Mar 31 12:33:26 PM PDT 24
Peak memory 194188 kb
Host smart-783a7a56-67da-449a-b204-c1b89910525c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071368270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2071368270
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3483968046
Short name T62
Test name
Test status
Simulation time 55965144 ps
CPU time 0.78 seconds
Started Mar 31 12:33:21 PM PDT 24
Finished Mar 31 12:33:22 PM PDT 24
Peak memory 197484 kb
Host smart-ee4b1e7c-e229-43da-9776-7b026b6554ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483968046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3483968046
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3595583224
Short name T1204
Test name
Test status
Simulation time 59475206 ps
CPU time 0.85 seconds
Started Mar 31 12:33:24 PM PDT 24
Finished Mar 31 12:33:25 PM PDT 24
Peak memory 199076 kb
Host smart-039aa0e1-bc44-42d1-b2a2-2ab66584e962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595583224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3595583224
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3899800621
Short name T1231
Test name
Test status
Simulation time 68974210 ps
CPU time 0.91 seconds
Started Mar 31 12:33:27 PM PDT 24
Finished Mar 31 12:33:29 PM PDT 24
Peak memory 198504 kb
Host smart-373353b8-e576-40e6-9eaa-77a84a9286c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899800621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3899800621
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2141326143
Short name T1289
Test name
Test status
Simulation time 119996064 ps
CPU time 0.9 seconds
Started Mar 31 12:33:22 PM PDT 24
Finished Mar 31 12:33:23 PM PDT 24
Peak memory 199764 kb
Host smart-8834a895-4ef5-40d3-aeb5-aac881bc740f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141326143 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2141326143
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1454207090
Short name T1181
Test name
Test status
Simulation time 158507035 ps
CPU time 0.61 seconds
Started Mar 31 12:33:26 PM PDT 24
Finished Mar 31 12:33:27 PM PDT 24
Peak memory 195228 kb
Host smart-dabd9c92-6b87-49ec-a792-130c6db79260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454207090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1454207090
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.869149690
Short name T1301
Test name
Test status
Simulation time 15448624 ps
CPU time 0.6 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 194308 kb
Host smart-41c4f911-4c3c-459b-8ef5-6da58729cf5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869149690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.869149690
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3965488292
Short name T1244
Test name
Test status
Simulation time 17719147 ps
CPU time 0.59 seconds
Started Mar 31 12:33:27 PM PDT 24
Finished Mar 31 12:33:27 PM PDT 24
Peak memory 195344 kb
Host smart-e33b10da-269e-4031-964b-151fdd2ea6b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965488292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3965488292
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.658352483
Short name T1184
Test name
Test status
Simulation time 105916759 ps
CPU time 2.19 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:25 PM PDT 24
Peak memory 199916 kb
Host smart-7aaad8ef-36f7-429e-81e1-ee441e80498c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658352483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.658352483
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3333873199
Short name T1269
Test name
Test status
Simulation time 66569551 ps
CPU time 0.88 seconds
Started Mar 31 12:33:21 PM PDT 24
Finished Mar 31 12:33:23 PM PDT 24
Peak memory 198668 kb
Host smart-e1e4725d-a4fa-49d5-b691-0c5dd9074566
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333873199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3333873199
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2288618607
Short name T1215
Test name
Test status
Simulation time 21816217 ps
CPU time 0.87 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 199764 kb
Host smart-a700a347-1d8b-42da-8c15-be7691d51719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288618607 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2288618607
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3027755260
Short name T61
Test name
Test status
Simulation time 11711375 ps
CPU time 0.58 seconds
Started Mar 31 12:33:24 PM PDT 24
Finished Mar 31 12:33:25 PM PDT 24
Peak memory 195208 kb
Host smart-16551920-6222-4a41-a01c-3789e7ec966c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027755260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3027755260
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1517458349
Short name T1198
Test name
Test status
Simulation time 43188927 ps
CPU time 0.56 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:24 PM PDT 24
Peak memory 194268 kb
Host smart-6c0678b1-7ba4-4e7f-891d-2c163bcc1073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517458349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1517458349
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.889071132
Short name T1312
Test name
Test status
Simulation time 52484562 ps
CPU time 0.75 seconds
Started Mar 31 12:33:27 PM PDT 24
Finished Mar 31 12:33:28 PM PDT 24
Peak memory 197028 kb
Host smart-ae9b8914-a1cb-4c50-8a17-0da7347092dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889071132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.889071132
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2706345343
Short name T1248
Test name
Test status
Simulation time 164122465 ps
CPU time 2.08 seconds
Started Mar 31 12:33:24 PM PDT 24
Finished Mar 31 12:33:26 PM PDT 24
Peak memory 199808 kb
Host smart-669b1380-b614-4ca0-ab84-e82e7bbad744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706345343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2706345343
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3747279806
Short name T65
Test name
Test status
Simulation time 98980842 ps
CPU time 1.32 seconds
Started Mar 31 12:33:24 PM PDT 24
Finished Mar 31 12:33:25 PM PDT 24
Peak memory 199264 kb
Host smart-4340f6c6-eafd-46b3-a6ff-ecdc927127c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747279806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3747279806
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1801115042
Short name T1262
Test name
Test status
Simulation time 28884063 ps
CPU time 0.79 seconds
Started Mar 31 12:33:27 PM PDT 24
Finished Mar 31 12:33:28 PM PDT 24
Peak memory 198400 kb
Host smart-9e5163c3-ac20-4d4b-a533-294f1d8b1bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801115042 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1801115042
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1106471520
Short name T1267
Test name
Test status
Simulation time 35836900 ps
CPU time 0.62 seconds
Started Mar 31 12:33:25 PM PDT 24
Finished Mar 31 12:33:26 PM PDT 24
Peak memory 195284 kb
Host smart-6c4f762d-db12-49cf-a619-c9764e842836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106471520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1106471520
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2195954538
Short name T1188
Test name
Test status
Simulation time 16764198 ps
CPU time 0.55 seconds
Started Mar 31 12:33:25 PM PDT 24
Finished Mar 31 12:33:26 PM PDT 24
Peak memory 194192 kb
Host smart-75503bf4-9ca1-40de-ab9e-7c7aa03821f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195954538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2195954538
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2053455897
Short name T1212
Test name
Test status
Simulation time 92752171 ps
CPU time 0.75 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:23 PM PDT 24
Peak memory 197012 kb
Host smart-db2e23e5-8119-49d4-950e-a8579b7f7b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053455897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2053455897
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2498678034
Short name T1302
Test name
Test status
Simulation time 133898710 ps
CPU time 2.27 seconds
Started Mar 31 12:33:28 PM PDT 24
Finished Mar 31 12:33:30 PM PDT 24
Peak memory 199948 kb
Host smart-c2755c6a-8d9d-449f-9381-42c07bf85e70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498678034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2498678034
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1549117573
Short name T1293
Test name
Test status
Simulation time 251793074 ps
CPU time 1.29 seconds
Started Mar 31 12:33:28 PM PDT 24
Finished Mar 31 12:33:30 PM PDT 24
Peak memory 199176 kb
Host smart-fcc6c08d-6556-443f-933c-82de6f0621f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549117573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1549117573
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1960038126
Short name T1235
Test name
Test status
Simulation time 22950840 ps
CPU time 0.73 seconds
Started Mar 31 12:33:36 PM PDT 24
Finished Mar 31 12:33:36 PM PDT 24
Peak memory 198020 kb
Host smart-93a1a0a3-ebeb-489e-b564-1ef3340b2390
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960038126 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1960038126
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3089246567
Short name T1309
Test name
Test status
Simulation time 19527508 ps
CPU time 0.59 seconds
Started Mar 31 12:33:30 PM PDT 24
Finished Mar 31 12:33:30 PM PDT 24
Peak memory 195188 kb
Host smart-a3bc4bbe-9c96-4379-91b7-062d8c425db3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089246567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3089246567
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1215684798
Short name T1247
Test name
Test status
Simulation time 38844097 ps
CPU time 0.55 seconds
Started Mar 31 12:33:30 PM PDT 24
Finished Mar 31 12:33:31 PM PDT 24
Peak memory 194244 kb
Host smart-1b38cc92-0921-4d17-aa1c-3fc7478ec34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215684798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1215684798
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1323108403
Short name T60
Test name
Test status
Simulation time 69952574 ps
CPU time 0.65 seconds
Started Mar 31 12:33:34 PM PDT 24
Finished Mar 31 12:33:35 PM PDT 24
Peak memory 195432 kb
Host smart-40ca6fd5-5c86-44a5-bbb7-56e549388da2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323108403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1323108403
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1891137116
Short name T1191
Test name
Test status
Simulation time 66898285 ps
CPU time 1.43 seconds
Started Mar 31 12:33:23 PM PDT 24
Finished Mar 31 12:33:25 PM PDT 24
Peak memory 199808 kb
Host smart-0a292087-3cf9-47a3-890e-96e000b2674e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891137116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1891137116
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2392387240
Short name T1285
Test name
Test status
Simulation time 56301369 ps
CPU time 0.95 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 198808 kb
Host smart-a5321a5c-4a87-4118-ba6f-2f93670f7558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392387240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2392387240
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4020606100
Short name T1241
Test name
Test status
Simulation time 43624445 ps
CPU time 1.13 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 199872 kb
Host smart-15ed4027-98f2-4980-9fff-feec972ee106
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020606100 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4020606100
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1338835913
Short name T1237
Test name
Test status
Simulation time 16093842 ps
CPU time 0.62 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 195224 kb
Host smart-7bcd0bd2-3952-4981-8ecf-de47260a70cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338835913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1338835913
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1929199486
Short name T1190
Test name
Test status
Simulation time 23699038 ps
CPU time 0.6 seconds
Started Mar 31 12:33:32 PM PDT 24
Finished Mar 31 12:33:33 PM PDT 24
Peak memory 194220 kb
Host smart-573c502e-3ee3-4fee-b2f6-983155887e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929199486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1929199486
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3191103201
Short name T1319
Test name
Test status
Simulation time 29924500 ps
CPU time 0.64 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 196460 kb
Host smart-f36bde27-9e04-4ad7-85d5-43ef99b75129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191103201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3191103201
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2036274209
Short name T1195
Test name
Test status
Simulation time 45988114 ps
CPU time 2.56 seconds
Started Mar 31 12:33:32 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 199876 kb
Host smart-e686c395-b1c1-46ba-b51b-99ba4ba7e784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036274209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2036274209
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1780272991
Short name T101
Test name
Test status
Simulation time 334381701 ps
CPU time 1.26 seconds
Started Mar 31 12:33:30 PM PDT 24
Finished Mar 31 12:33:31 PM PDT 24
Peak memory 199196 kb
Host smart-787db121-5a4f-489b-a849-1ac77c542fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780272991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1780272991
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1464208430
Short name T1282
Test name
Test status
Simulation time 170662995 ps
CPU time 0.75 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 199120 kb
Host smart-43df8048-491a-40e1-bdf7-8a806d186754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464208430 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1464208430
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3370024393
Short name T1266
Test name
Test status
Simulation time 53381097 ps
CPU time 0.6 seconds
Started Mar 31 12:33:34 PM PDT 24
Finished Mar 31 12:33:35 PM PDT 24
Peak memory 195288 kb
Host smart-c8804656-d475-40ec-93a0-9bd43b909eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370024393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3370024393
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3490729155
Short name T1299
Test name
Test status
Simulation time 14570812 ps
CPU time 0.56 seconds
Started Mar 31 12:33:36 PM PDT 24
Finished Mar 31 12:33:37 PM PDT 24
Peak memory 194172 kb
Host smart-709abbe3-8259-4cd3-97e4-7dc6ba20c0f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490729155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3490729155
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.507903152
Short name T1311
Test name
Test status
Simulation time 66337012 ps
CPU time 0.72 seconds
Started Mar 31 12:33:33 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 196964 kb
Host smart-6ba2341b-7f78-498f-aaae-08c78d3e13ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507903152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.507903152
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2177682723
Short name T1252
Test name
Test status
Simulation time 459341970 ps
CPU time 0.91 seconds
Started Mar 31 12:33:30 PM PDT 24
Finished Mar 31 12:33:31 PM PDT 24
Peak memory 199700 kb
Host smart-2b9cccff-2cac-45c1-be85-bbb7ec544452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177682723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2177682723
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3041127220
Short name T103
Test name
Test status
Simulation time 336910009 ps
CPU time 1.34 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:33 PM PDT 24
Peak memory 199224 kb
Host smart-fbf3eae5-02a2-4d8e-ad1f-943e08cf40a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041127220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3041127220
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4040882476
Short name T1183
Test name
Test status
Simulation time 84704817 ps
CPU time 0.77 seconds
Started Mar 31 12:33:33 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 198988 kb
Host smart-8edf3042-9182-4ec4-8cc9-e1b41bea7e93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040882476 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4040882476
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3242783944
Short name T1296
Test name
Test status
Simulation time 39324065 ps
CPU time 0.53 seconds
Started Mar 31 12:33:32 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 194260 kb
Host smart-d65e68d4-fc1f-47b0-b24e-acd76eea4522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242783944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3242783944
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2320731472
Short name T1300
Test name
Test status
Simulation time 50760850 ps
CPU time 0.73 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 197516 kb
Host smart-fdba4546-4862-4557-b177-f90aed206f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320731472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2320731472
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2659165934
Short name T1233
Test name
Test status
Simulation time 81518794 ps
CPU time 1.15 seconds
Started Mar 31 12:33:33 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 199916 kb
Host smart-146465ff-b16d-4313-bc27-600de61fc600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659165934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2659165934
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2920911292
Short name T71
Test name
Test status
Simulation time 97256154 ps
CPU time 1.44 seconds
Started Mar 31 12:33:34 PM PDT 24
Finished Mar 31 12:33:35 PM PDT 24
Peak memory 199308 kb
Host smart-c4d26298-2212-4f3c-8071-ddf2f8b9c9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920911292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2920911292
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2512586262
Short name T1238
Test name
Test status
Simulation time 53445862 ps
CPU time 0.77 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:33:01 PM PDT 24
Peak memory 196124 kb
Host smart-a8e4c32b-75dd-497b-b2f7-5ddeb39d7f42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512586262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2512586262
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.504405936
Short name T1203
Test name
Test status
Simulation time 796964188 ps
CPU time 2.19 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 197428 kb
Host smart-b2b3b44e-ac1d-4ca6-8c74-949aab496fdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504405936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.504405936
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.497483033
Short name T52
Test name
Test status
Simulation time 15048669 ps
CPU time 0.57 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:33:01 PM PDT 24
Peak memory 195296 kb
Host smart-89d81668-ccf4-4561-9073-205ceb80b402
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497483033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.497483033
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.647316999
Short name T1272
Test name
Test status
Simulation time 26372440 ps
CPU time 0.77 seconds
Started Mar 31 12:33:11 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 199612 kb
Host smart-9189e70b-63ca-4011-b045-8e5998ef89e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647316999 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.647316999
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1193674747
Short name T1307
Test name
Test status
Simulation time 20059694 ps
CPU time 0.56 seconds
Started Mar 31 12:33:06 PM PDT 24
Finished Mar 31 12:33:07 PM PDT 24
Peak memory 195204 kb
Host smart-6b3f29ec-b2b1-4216-a11a-b55b98fd0d67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193674747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1193674747
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1301168994
Short name T1220
Test name
Test status
Simulation time 44273575 ps
CPU time 0.55 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 194236 kb
Host smart-85162294-1a0f-4235-917f-d12543839f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301168994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1301168994
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2993408477
Short name T1318
Test name
Test status
Simulation time 66033078 ps
CPU time 0.74 seconds
Started Mar 31 12:33:04 PM PDT 24
Finished Mar 31 12:33:05 PM PDT 24
Peak memory 196780 kb
Host smart-c1715f78-1de4-413e-b759-2ef1c08086d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993408477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2993408477
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2443394492
Short name T1258
Test name
Test status
Simulation time 27645127 ps
CPU time 1.27 seconds
Started Mar 31 12:32:58 PM PDT 24
Finished Mar 31 12:32:59 PM PDT 24
Peak memory 199884 kb
Host smart-2705b195-3e74-40b6-baa7-80e20795a3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443394492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2443394492
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2697235451
Short name T1229
Test name
Test status
Simulation time 379091735 ps
CPU time 0.93 seconds
Started Mar 31 12:33:02 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 198692 kb
Host smart-13e19b4a-69f9-4550-a5ad-1a02659e51a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697235451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2697235451
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.4058859737
Short name T1246
Test name
Test status
Simulation time 12625043 ps
CPU time 0.57 seconds
Started Mar 31 12:33:31 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 194144 kb
Host smart-ae72e921-adfd-4a29-9051-63a18079e428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058859737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4058859737
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2930617224
Short name T1240
Test name
Test status
Simulation time 11854225 ps
CPU time 0.54 seconds
Started Mar 31 12:33:33 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 194300 kb
Host smart-6a48c334-da33-4148-a41f-4fefc380cfec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930617224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2930617224
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3578761909
Short name T1249
Test name
Test status
Simulation time 19410825 ps
CPU time 0.58 seconds
Started Mar 31 12:33:33 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 194244 kb
Host smart-ac9b2bf6-9de1-4963-aee8-a378b10a86e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578761909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3578761909
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1032773952
Short name T1259
Test name
Test status
Simulation time 16682496 ps
CPU time 0.55 seconds
Started Mar 31 12:33:32 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 194240 kb
Host smart-b4b0fcc6-4a47-4d8b-9869-3a705acc0d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032773952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1032773952
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.563688091
Short name T1251
Test name
Test status
Simulation time 69838392 ps
CPU time 0.6 seconds
Started Mar 31 12:33:47 PM PDT 24
Finished Mar 31 12:33:48 PM PDT 24
Peak memory 194100 kb
Host smart-6c7bb27a-68d3-4827-824f-7a405cc2a429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563688091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.563688091
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2673526889
Short name T1284
Test name
Test status
Simulation time 24257515 ps
CPU time 0.57 seconds
Started Mar 31 12:33:39 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 194176 kb
Host smart-16d215d1-f194-4018-a7c0-2ed9bd67eced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673526889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2673526889
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.841564339
Short name T1276
Test name
Test status
Simulation time 90991574 ps
CPU time 0.54 seconds
Started Mar 31 12:33:37 PM PDT 24
Finished Mar 31 12:33:38 PM PDT 24
Peak memory 194240 kb
Host smart-1b062430-ba99-4063-a338-e0e17985aa72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841564339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.841564339
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2600891241
Short name T1270
Test name
Test status
Simulation time 16353843 ps
CPU time 0.57 seconds
Started Mar 31 12:33:43 PM PDT 24
Finished Mar 31 12:33:43 PM PDT 24
Peak memory 194168 kb
Host smart-253eb82f-48e7-4d59-90b4-65ef6abbb252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600891241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2600891241
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1456399213
Short name T1239
Test name
Test status
Simulation time 44812431 ps
CPU time 0.54 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194260 kb
Host smart-9899317d-c7cf-42ec-802d-1f1a94926b22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456399213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1456399213
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2260667658
Short name T1182
Test name
Test status
Simulation time 12675503 ps
CPU time 0.61 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 194396 kb
Host smart-b307c852-9190-4669-b4b1-f42609a2df0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260667658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2260667658
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.4252336496
Short name T1236
Test name
Test status
Simulation time 95807786 ps
CPU time 0.67 seconds
Started Mar 31 12:33:10 PM PDT 24
Finished Mar 31 12:33:11 PM PDT 24
Peak memory 194832 kb
Host smart-59b335a1-5946-4fe2-9cfd-0ed480723677
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252336496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.4252336496
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2847798109
Short name T51
Test name
Test status
Simulation time 140023132 ps
CPU time 1.56 seconds
Started Mar 31 12:33:10 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 197008 kb
Host smart-e2432d1c-cef0-4f44-acf6-fc5913943e87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847798109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2847798109
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2904730258
Short name T1214
Test name
Test status
Simulation time 14717285 ps
CPU time 0.58 seconds
Started Mar 31 12:33:09 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 195268 kb
Host smart-a51a9ecd-3c01-446e-9a2c-6f7680de282f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904730258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2904730258
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2176928071
Short name T1217
Test name
Test status
Simulation time 67539291 ps
CPU time 1.13 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 199740 kb
Host smart-12f40bb1-7724-463e-87ba-a50d712238ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176928071 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2176928071
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1127516235
Short name T1283
Test name
Test status
Simulation time 13448820 ps
CPU time 0.59 seconds
Started Mar 31 12:33:09 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 195220 kb
Host smart-b180099e-6254-46da-89ad-e4ce21c09d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127516235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1127516235
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3687136432
Short name T1287
Test name
Test status
Simulation time 27932637 ps
CPU time 0.56 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 194252 kb
Host smart-ec2f2087-53cb-45b9-86c3-f804c6f42b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687136432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3687136432
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.15260250
Short name T1221
Test name
Test status
Simulation time 43984500 ps
CPU time 0.63 seconds
Started Mar 31 12:33:10 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 195584 kb
Host smart-a452f4d0-692c-44d4-8641-1d3429f21373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15260250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_o
utstanding.15260250
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.315719542
Short name T1222
Test name
Test status
Simulation time 212409620 ps
CPU time 1.87 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 199936 kb
Host smart-22a09848-273e-418c-98eb-f8fe47e54ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315719542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.315719542
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.15534186
Short name T68
Test name
Test status
Simulation time 72827297 ps
CPU time 0.9 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 198944 kb
Host smart-41c41d73-84fa-49b1-970f-63876f284dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15534186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.15534186
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1008502552
Short name T1200
Test name
Test status
Simulation time 37744698 ps
CPU time 0.57 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194212 kb
Host smart-cd380403-a7ca-42bb-8c13-90d4c72689db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008502552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1008502552
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3375110950
Short name T1308
Test name
Test status
Simulation time 30656590 ps
CPU time 0.59 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194308 kb
Host smart-640e6b84-37ff-48c8-b6a6-19670bd1519d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375110950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3375110950
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2504433481
Short name T1196
Test name
Test status
Simulation time 59457384 ps
CPU time 0.57 seconds
Started Mar 31 12:33:38 PM PDT 24
Finished Mar 31 12:33:39 PM PDT 24
Peak memory 194208 kb
Host smart-b6246b15-a90b-4fb1-9496-e365dc9588c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504433481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2504433481
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1644171116
Short name T1208
Test name
Test status
Simulation time 14881205 ps
CPU time 0.56 seconds
Started Mar 31 12:33:43 PM PDT 24
Finished Mar 31 12:33:43 PM PDT 24
Peak memory 194144 kb
Host smart-763aad09-c0a1-4c64-b86c-d34dff12ba54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644171116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1644171116
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1773112131
Short name T1187
Test name
Test status
Simulation time 18613287 ps
CPU time 0.59 seconds
Started Mar 31 12:33:38 PM PDT 24
Finished Mar 31 12:33:39 PM PDT 24
Peak memory 194256 kb
Host smart-780765c9-28b7-46c6-9c49-ad93612ec665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773112131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1773112131
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1244857168
Short name T1186
Test name
Test status
Simulation time 24918545 ps
CPU time 0.6 seconds
Started Mar 31 12:33:41 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194184 kb
Host smart-5c03decd-68e7-4d81-af05-d3e15267885a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244857168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1244857168
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2020294098
Short name T1274
Test name
Test status
Simulation time 67025732 ps
CPU time 0.54 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 194284 kb
Host smart-6cfadcf4-a102-4366-a720-a2f13a596408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020294098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2020294098
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1845926406
Short name T1265
Test name
Test status
Simulation time 15624307 ps
CPU time 0.6 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194208 kb
Host smart-68bcf666-32bb-4409-a75e-b7c8c2b272b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845926406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1845926406
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1566693721
Short name T1192
Test name
Test status
Simulation time 11534669 ps
CPU time 0.57 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194240 kb
Host smart-0cdadbe7-3237-4c4f-8c54-0ca02aebf0ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566693721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1566693721
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.633525383
Short name T1297
Test name
Test status
Simulation time 70625493 ps
CPU time 0.61 seconds
Started Mar 31 12:33:37 PM PDT 24
Finished Mar 31 12:33:38 PM PDT 24
Peak memory 194148 kb
Host smart-1aa26813-6f49-4682-9c8c-08ff31c7339a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633525383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.633525383
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.239934453
Short name T1224
Test name
Test status
Simulation time 94645987 ps
CPU time 0.78 seconds
Started Mar 31 12:33:10 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 195944 kb
Host smart-0cc63685-bc52-48f1-8a5e-7eccee201efa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239934453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.239934453
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3337069281
Short name T1199
Test name
Test status
Simulation time 198042981 ps
CPU time 2.4 seconds
Started Mar 31 12:33:11 PM PDT 24
Finished Mar 31 12:33:14 PM PDT 24
Peak memory 197816 kb
Host smart-a7a4b0f7-6b65-42f1-bc8d-45bb747c42db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337069281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3337069281
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2792429853
Short name T1225
Test name
Test status
Simulation time 13876028 ps
CPU time 0.57 seconds
Started Mar 31 12:33:09 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 195216 kb
Host smart-26686522-df41-4ad8-84b0-d5574de48d47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792429853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2792429853
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2259330148
Short name T1207
Test name
Test status
Simulation time 19277237 ps
CPU time 0.79 seconds
Started Mar 31 12:33:11 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 199672 kb
Host smart-7845be01-4dd2-46a5-8e75-fbca5825d432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259330148 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2259330148
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2520795483
Short name T59
Test name
Test status
Simulation time 107263573 ps
CPU time 0.63 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 195300 kb
Host smart-5bf4179d-464b-46e8-8df9-8143c9eb9af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520795483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2520795483
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1204955894
Short name T1298
Test name
Test status
Simulation time 43817086 ps
CPU time 0.55 seconds
Started Mar 31 12:33:10 PM PDT 24
Finished Mar 31 12:33:11 PM PDT 24
Peak memory 194232 kb
Host smart-66393d27-2baa-430e-89bd-7e2851be8859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204955894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1204955894
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.426911880
Short name T1304
Test name
Test status
Simulation time 37669498 ps
CPU time 0.78 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 196508 kb
Host smart-b7c3f12e-de01-47c9-87ed-346b7c6e1236
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426911880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.426911880
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3722114498
Short name T1277
Test name
Test status
Simulation time 182585908 ps
CPU time 1.73 seconds
Started Mar 31 12:33:07 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 199820 kb
Host smart-9800f12b-e06c-4abd-8260-57e6cacebe11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722114498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3722114498
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1198359512
Short name T67
Test name
Test status
Simulation time 68180610 ps
CPU time 1.25 seconds
Started Mar 31 12:33:09 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 199200 kb
Host smart-b16239f0-ee3d-4f38-835f-795e2e880258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198359512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1198359512
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2347027214
Short name T1261
Test name
Test status
Simulation time 14890363 ps
CPU time 0.61 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194240 kb
Host smart-01595011-6248-4faf-9167-9a443e3e29a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347027214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2347027214
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3406618722
Short name T1294
Test name
Test status
Simulation time 13728024 ps
CPU time 0.58 seconds
Started Mar 31 12:33:39 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 194320 kb
Host smart-81821472-d991-40e5-b566-080b85040ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406618722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3406618722
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.830338845
Short name T1232
Test name
Test status
Simulation time 142066054 ps
CPU time 0.55 seconds
Started Mar 31 12:33:39 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 194148 kb
Host smart-1a6d73aa-9fda-431d-91bd-ed994850699c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830338845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.830338845
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3781460730
Short name T1194
Test name
Test status
Simulation time 46611883 ps
CPU time 0.58 seconds
Started Mar 31 12:33:42 PM PDT 24
Finished Mar 31 12:33:42 PM PDT 24
Peak memory 194184 kb
Host smart-e972481b-ac0f-4197-95f0-6ac64f1754f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781460730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3781460730
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2310738186
Short name T1314
Test name
Test status
Simulation time 27157705 ps
CPU time 0.59 seconds
Started Mar 31 12:33:42 PM PDT 24
Finished Mar 31 12:33:43 PM PDT 24
Peak memory 194240 kb
Host smart-89156ba4-cc9a-4457-a490-993f3413f32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310738186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2310738186
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2913875547
Short name T1320
Test name
Test status
Simulation time 17720601 ps
CPU time 0.56 seconds
Started Mar 31 12:33:40 PM PDT 24
Finished Mar 31 12:33:41 PM PDT 24
Peak memory 194280 kb
Host smart-d711e54a-3cdc-4ea9-9290-3c4a5c9fd7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913875547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2913875547
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2931063542
Short name T1256
Test name
Test status
Simulation time 11709875 ps
CPU time 0.56 seconds
Started Mar 31 12:33:37 PM PDT 24
Finished Mar 31 12:33:38 PM PDT 24
Peak memory 194288 kb
Host smart-af98bd1f-ecdf-41be-ae8f-37a97a7f9a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931063542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2931063542
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.496356406
Short name T1210
Test name
Test status
Simulation time 45996878 ps
CPU time 0.55 seconds
Started Mar 31 12:33:39 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 194180 kb
Host smart-e857b702-e3be-433d-8634-9928eb7f3e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496356406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.496356406
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2044379921
Short name T1290
Test name
Test status
Simulation time 32139271 ps
CPU time 0.59 seconds
Started Mar 31 12:33:42 PM PDT 24
Finished Mar 31 12:33:42 PM PDT 24
Peak memory 194156 kb
Host smart-4533dfe1-3e20-422f-93ce-8f49013c2f94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044379921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2044379921
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3170076278
Short name T1268
Test name
Test status
Simulation time 13749306 ps
CPU time 0.59 seconds
Started Mar 31 12:33:43 PM PDT 24
Finished Mar 31 12:33:43 PM PDT 24
Peak memory 194144 kb
Host smart-cc218b0e-8559-4573-b07d-22f78809378a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170076278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3170076278
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1615434429
Short name T1281
Test name
Test status
Simulation time 41104488 ps
CPU time 0.74 seconds
Started Mar 31 12:33:11 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 198372 kb
Host smart-f4c2c66d-8ebe-4179-ab24-0600e2db386f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615434429 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1615434429
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3975136032
Short name T50
Test name
Test status
Simulation time 29727985 ps
CPU time 0.6 seconds
Started Mar 31 12:33:11 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 195256 kb
Host smart-f8651796-741a-4653-935d-077205ed88f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975136032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3975136032
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2007386736
Short name T1189
Test name
Test status
Simulation time 13201905 ps
CPU time 0.6 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 194260 kb
Host smart-c29a1ad3-ce4e-4191-a1d1-5e2d1bcc69af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007386736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2007386736
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1450820213
Short name T1280
Test name
Test status
Simulation time 68789232 ps
CPU time 0.73 seconds
Started Mar 31 12:33:06 PM PDT 24
Finished Mar 31 12:33:08 PM PDT 24
Peak memory 196708 kb
Host smart-a666ed62-6a53-4270-a7f6-e81b67657dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450820213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1450820213
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.995309740
Short name T1263
Test name
Test status
Simulation time 99963977 ps
CPU time 2.13 seconds
Started Mar 31 12:33:12 PM PDT 24
Finished Mar 31 12:33:14 PM PDT 24
Peak memory 199832 kb
Host smart-2d2a9ab8-7dbb-4fa9-8fab-a7635a6bac4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995309740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.995309740
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3385925741
Short name T102
Test name
Test status
Simulation time 141089915 ps
CPU time 1.3 seconds
Started Mar 31 12:33:09 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 199060 kb
Host smart-5f2b36a6-d7b7-4262-b838-bfaa02a0a54c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385925741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3385925741
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.428761200
Short name T1197
Test name
Test status
Simulation time 241892703 ps
CPU time 0.78 seconds
Started Mar 31 12:33:10 PM PDT 24
Finished Mar 31 12:33:11 PM PDT 24
Peak memory 198312 kb
Host smart-eaaa7c40-871d-4499-adc5-1e3e05d0b1a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428761200 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.428761200
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1690867245
Short name T1291
Test name
Test status
Simulation time 40112093 ps
CPU time 0.59 seconds
Started Mar 31 12:33:07 PM PDT 24
Finished Mar 31 12:33:08 PM PDT 24
Peak memory 195288 kb
Host smart-f55dec0f-6423-46f3-9730-757538458259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690867245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1690867245
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3287929532
Short name T1288
Test name
Test status
Simulation time 14761018 ps
CPU time 0.59 seconds
Started Mar 31 12:33:10 PM PDT 24
Finished Mar 31 12:33:11 PM PDT 24
Peak memory 194300 kb
Host smart-436d6c71-6843-46a9-ab68-5809577b5577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287929532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3287929532
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.495513470
Short name T1317
Test name
Test status
Simulation time 59916633 ps
CPU time 0.64 seconds
Started Mar 31 12:33:11 PM PDT 24
Finished Mar 31 12:33:12 PM PDT 24
Peak memory 194712 kb
Host smart-eeb7a70a-d461-41a0-9a91-ac144cca0a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495513470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.495513470
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1509736995
Short name T1227
Test name
Test status
Simulation time 28005767 ps
CPU time 1.27 seconds
Started Mar 31 12:33:08 PM PDT 24
Finished Mar 31 12:33:10 PM PDT 24
Peak memory 199880 kb
Host smart-cea40f74-857c-4a48-9d3c-673a51900e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509736995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1509736995
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1594207340
Short name T1278
Test name
Test status
Simulation time 50497323 ps
CPU time 0.65 seconds
Started Mar 31 12:33:17 PM PDT 24
Finished Mar 31 12:33:18 PM PDT 24
Peak memory 197204 kb
Host smart-e7b55c31-d3be-4800-938c-4d1dd7308ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594207340 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1594207340
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2053710756
Short name T63
Test name
Test status
Simulation time 23982623 ps
CPU time 0.62 seconds
Started Mar 31 12:33:18 PM PDT 24
Finished Mar 31 12:33:19 PM PDT 24
Peak memory 195468 kb
Host smart-6d964cb8-e88b-4874-a7d9-e654f5a6f2c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053710756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2053710756
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.725054738
Short name T1226
Test name
Test status
Simulation time 63170540 ps
CPU time 0.56 seconds
Started Mar 31 12:33:15 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 194208 kb
Host smart-aab3a7ee-12ba-4129-a9cb-8371252aa98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725054738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.725054738
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3439507145
Short name T1228
Test name
Test status
Simulation time 62021345 ps
CPU time 0.64 seconds
Started Mar 31 12:33:18 PM PDT 24
Finished Mar 31 12:33:18 PM PDT 24
Peak memory 195660 kb
Host smart-03dca512-d6e3-41b9-b608-262874c6a33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439507145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3439507145
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.31546756
Short name T1201
Test name
Test status
Simulation time 289851036 ps
CPU time 1.75 seconds
Started Mar 31 12:33:17 PM PDT 24
Finished Mar 31 12:33:19 PM PDT 24
Peak memory 199876 kb
Host smart-5e9314f1-c9c0-4293-99fd-fdc2d53c19c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31546756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.31546756
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4169450895
Short name T1223
Test name
Test status
Simulation time 20191277 ps
CPU time 0.91 seconds
Started Mar 31 12:33:15 PM PDT 24
Finished Mar 31 12:33:17 PM PDT 24
Peak memory 199780 kb
Host smart-4371195d-3b8a-4c8a-b48f-1a8bbcc7024f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169450895 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4169450895
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1544405574
Short name T1218
Test name
Test status
Simulation time 40553601 ps
CPU time 0.6 seconds
Started Mar 31 12:33:16 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 195432 kb
Host smart-aef48b85-9249-40f3-a814-6ebc9828bd94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544405574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1544405574
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.4150177842
Short name T1257
Test name
Test status
Simulation time 22023641 ps
CPU time 0.62 seconds
Started Mar 31 12:33:15 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 194256 kb
Host smart-1988982f-8cc7-4bf4-bfd1-a71d812a531c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150177842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4150177842
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2975401874
Short name T58
Test name
Test status
Simulation time 94467652 ps
CPU time 0.73 seconds
Started Mar 31 12:33:16 PM PDT 24
Finished Mar 31 12:33:17 PM PDT 24
Peak memory 195980 kb
Host smart-b475584b-13a3-4041-9404-1ac0a8b23030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975401874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2975401874
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3136412615
Short name T1292
Test name
Test status
Simulation time 58585762 ps
CPU time 1.46 seconds
Started Mar 31 12:33:17 PM PDT 24
Finished Mar 31 12:33:19 PM PDT 24
Peak memory 199848 kb
Host smart-6107291d-bfc9-4107-9636-7d29074342ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136412615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3136412615
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.174124920
Short name T1250
Test name
Test status
Simulation time 79555269 ps
CPU time 0.99 seconds
Started Mar 31 12:33:15 PM PDT 24
Finished Mar 31 12:33:17 PM PDT 24
Peak memory 198872 kb
Host smart-e4a87e87-1c2e-4f70-aa06-a3fe57694cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174124920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.174124920
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3467328537
Short name T1206
Test name
Test status
Simulation time 14231448 ps
CPU time 0.63 seconds
Started Mar 31 12:33:14 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 197392 kb
Host smart-61e6aa10-a47e-4979-9ce5-61fa547e48d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467328537 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3467328537
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1374250155
Short name T55
Test name
Test status
Simulation time 18174073 ps
CPU time 0.6 seconds
Started Mar 31 12:33:16 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 195288 kb
Host smart-c26867e9-bf28-4cea-9faf-28187ea442b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374250155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1374250155
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3309035356
Short name T1279
Test name
Test status
Simulation time 13390948 ps
CPU time 0.62 seconds
Started Mar 31 12:33:18 PM PDT 24
Finished Mar 31 12:33:19 PM PDT 24
Peak memory 194260 kb
Host smart-95d0a039-81b3-47e2-af0e-721765c204db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309035356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3309035356
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3967306133
Short name T1305
Test name
Test status
Simulation time 67211043 ps
CPU time 0.65 seconds
Started Mar 31 12:33:15 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 195512 kb
Host smart-4b94061c-5c9b-4f9a-9fd2-fc6cc41d7824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967306133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3967306133
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1753438545
Short name T1275
Test name
Test status
Simulation time 150958062 ps
CPU time 1.72 seconds
Started Mar 31 12:33:15 PM PDT 24
Finished Mar 31 12:33:17 PM PDT 24
Peak memory 199872 kb
Host smart-c5e227d4-e088-43e9-84bc-984caaddf11c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753438545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1753438545
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2119728752
Short name T1254
Test name
Test status
Simulation time 65496781 ps
CPU time 1.01 seconds
Started Mar 31 12:33:16 PM PDT 24
Finished Mar 31 12:33:17 PM PDT 24
Peak memory 198976 kb
Host smart-2447b08c-6217-4020-a804-7f9901a1dcd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119728752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2119728752
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2494207127
Short name T556
Test name
Test status
Simulation time 11423261 ps
CPU time 0.56 seconds
Started Mar 31 03:14:21 PM PDT 24
Finished Mar 31 03:14:22 PM PDT 24
Peak memory 194864 kb
Host smart-087cbb18-c375-44a8-aa7e-05193bb9d204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494207127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2494207127
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3650333618
Short name T853
Test name
Test status
Simulation time 109856809626 ps
CPU time 237.53 seconds
Started Mar 31 03:13:59 PM PDT 24
Finished Mar 31 03:17:57 PM PDT 24
Peak memory 200496 kb
Host smart-49b752f7-3de2-4d6c-90fe-bfea4013a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650333618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3650333618
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.4105537289
Short name T74
Test name
Test status
Simulation time 17133722017 ps
CPU time 29.69 seconds
Started Mar 31 03:14:03 PM PDT 24
Finished Mar 31 03:14:33 PM PDT 24
Peak memory 200372 kb
Host smart-83d16b0f-657b-45e1-adab-c0fccca50f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105537289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4105537289
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.1872126181
Short name T305
Test name
Test status
Simulation time 89763040992 ps
CPU time 156.06 seconds
Started Mar 31 03:14:08 PM PDT 24
Finished Mar 31 03:16:45 PM PDT 24
Peak memory 200504 kb
Host smart-034fae0d-057a-44dc-a96f-1706dda62529
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872126181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1872126181
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2157734883
Short name T822
Test name
Test status
Simulation time 163214449528 ps
CPU time 1480.6 seconds
Started Mar 31 03:14:16 PM PDT 24
Finished Mar 31 03:38:57 PM PDT 24
Peak memory 200484 kb
Host smart-61c7d39b-f50f-4590-ad8f-143d69ef37cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157734883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2157734883
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1443780346
Short name T644
Test name
Test status
Simulation time 6368024898 ps
CPU time 8.62 seconds
Started Mar 31 03:14:13 PM PDT 24
Finished Mar 31 03:14:22 PM PDT 24
Peak memory 199996 kb
Host smart-ad58afee-5b23-4144-8a9e-88cbce13f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443780346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1443780346
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.365794545
Short name T485
Test name
Test status
Simulation time 77291219907 ps
CPU time 154.81 seconds
Started Mar 31 03:14:09 PM PDT 24
Finished Mar 31 03:16:44 PM PDT 24
Peak memory 199416 kb
Host smart-1e9050cf-7082-4f6b-bfe3-9573989d2426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365794545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.365794545
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.963983397
Short name T443
Test name
Test status
Simulation time 10626736368 ps
CPU time 543.26 seconds
Started Mar 31 03:14:13 PM PDT 24
Finished Mar 31 03:23:17 PM PDT 24
Peak memory 200400 kb
Host smart-f1d4b352-27ea-4ce6-8bc2-1abf7895fdde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963983397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.963983397
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.936523665
Short name T345
Test name
Test status
Simulation time 3259772359 ps
CPU time 24.36 seconds
Started Mar 31 03:14:03 PM PDT 24
Finished Mar 31 03:14:27 PM PDT 24
Peak memory 198860 kb
Host smart-9028d974-3b75-440e-9513-b95c3a1f5ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936523665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.936523665
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.218485337
Short name T863
Test name
Test status
Simulation time 68990930401 ps
CPU time 48.36 seconds
Started Mar 31 03:14:08 PM PDT 24
Finished Mar 31 03:14:57 PM PDT 24
Peak memory 200416 kb
Host smart-4c03d0fb-f390-4005-b76c-d511438711ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218485337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.218485337
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.703847712
Short name T1142
Test name
Test status
Simulation time 2873034690 ps
CPU time 4.78 seconds
Started Mar 31 03:14:09 PM PDT 24
Finished Mar 31 03:14:14 PM PDT 24
Peak memory 196248 kb
Host smart-569b9315-e427-46db-a6df-1ca895b552ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703847712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.703847712
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.46114102
Short name T500
Test name
Test status
Simulation time 926019138 ps
CPU time 3.95 seconds
Started Mar 31 03:13:59 PM PDT 24
Finished Mar 31 03:14:03 PM PDT 24
Peak memory 200164 kb
Host smart-ad0c2461-839a-4f5f-a207-a4c110a372d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46114102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.46114102
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3083087319
Short name T303
Test name
Test status
Simulation time 392991570033 ps
CPU time 217.19 seconds
Started Mar 31 03:14:15 PM PDT 24
Finished Mar 31 03:17:52 PM PDT 24
Peak memory 200436 kb
Host smart-536afe97-d693-405e-9c18-c36775dbcb20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083087319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3083087319
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1072096117
Short name T1120
Test name
Test status
Simulation time 25196972812 ps
CPU time 220.35 seconds
Started Mar 31 03:14:14 PM PDT 24
Finished Mar 31 03:17:54 PM PDT 24
Peak memory 216980 kb
Host smart-6e1dbf01-2ab2-4789-bd7c-e17b61951474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072096117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1072096117
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1419926478
Short name T16
Test name
Test status
Simulation time 1099135222 ps
CPU time 2.67 seconds
Started Mar 31 03:14:14 PM PDT 24
Finished Mar 31 03:14:17 PM PDT 24
Peak memory 199284 kb
Host smart-cf5424b7-e016-47c2-8568-072014bcab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419926478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1419926478
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.592113779
Short name T269
Test name
Test status
Simulation time 36974346103 ps
CPU time 13.29 seconds
Started Mar 31 03:13:58 PM PDT 24
Finished Mar 31 03:14:12 PM PDT 24
Peak memory 200260 kb
Host smart-146e027e-5b62-4224-9097-ff4626db119e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592113779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.592113779
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.57338613
Short name T438
Test name
Test status
Simulation time 63345654 ps
CPU time 0.56 seconds
Started Mar 31 03:14:42 PM PDT 24
Finished Mar 31 03:14:43 PM PDT 24
Peak memory 195892 kb
Host smart-eb656b7f-b9b7-4d6b-99a6-454a2d0e25a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57338613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.57338613
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1555193658
Short name T776
Test name
Test status
Simulation time 315039906853 ps
CPU time 86.7 seconds
Started Mar 31 03:14:22 PM PDT 24
Finished Mar 31 03:15:48 PM PDT 24
Peak memory 200492 kb
Host smart-bbb9039b-fa56-4709-8b2c-dcff74e1f16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555193658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1555193658
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3683711029
Short name T1091
Test name
Test status
Simulation time 77195586780 ps
CPU time 69.63 seconds
Started Mar 31 03:14:29 PM PDT 24
Finished Mar 31 03:15:39 PM PDT 24
Peak memory 200492 kb
Host smart-df0d3dc5-3884-4421-88a7-9a9376fcb42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683711029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3683711029
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2758341795
Short name T448
Test name
Test status
Simulation time 32180722247 ps
CPU time 53.84 seconds
Started Mar 31 03:14:29 PM PDT 24
Finished Mar 31 03:15:23 PM PDT 24
Peak memory 200488 kb
Host smart-4bcfc988-cca8-4bbb-8689-80bc6fc526aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758341795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2758341795
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3512712728
Short name T1115
Test name
Test status
Simulation time 64311447031 ps
CPU time 57.65 seconds
Started Mar 31 03:14:25 PM PDT 24
Finished Mar 31 03:15:23 PM PDT 24
Peak memory 199548 kb
Host smart-6316f9db-a739-44d4-93ab-73ea91b81b0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512712728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3512712728
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3405846254
Short name T365
Test name
Test status
Simulation time 94413807650 ps
CPU time 1027.03 seconds
Started Mar 31 03:14:44 PM PDT 24
Finished Mar 31 03:31:51 PM PDT 24
Peak memory 200424 kb
Host smart-d59392b2-afe8-41ad-9e65-968915934f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405846254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3405846254
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3576761067
Short name T418
Test name
Test status
Simulation time 10782985114 ps
CPU time 27.66 seconds
Started Mar 31 03:14:35 PM PDT 24
Finished Mar 31 03:15:03 PM PDT 24
Peak memory 200512 kb
Host smart-36ffc819-92f4-4898-9f3a-618013c6b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576761067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3576761067
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3913868019
Short name T1022
Test name
Test status
Simulation time 52047784845 ps
CPU time 67.15 seconds
Started Mar 31 03:14:31 PM PDT 24
Finished Mar 31 03:15:39 PM PDT 24
Peak memory 200716 kb
Host smart-4bd86182-e4b8-4438-a410-444d2f3f04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913868019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3913868019
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2403968118
Short name T370
Test name
Test status
Simulation time 13090621260 ps
CPU time 51.4 seconds
Started Mar 31 03:14:35 PM PDT 24
Finished Mar 31 03:15:27 PM PDT 24
Peak memory 200440 kb
Host smart-1c947983-30a4-480d-9e8d-d0db0d9f18a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403968118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2403968118
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3113901747
Short name T969
Test name
Test status
Simulation time 2776422954 ps
CPU time 5.26 seconds
Started Mar 31 03:14:26 PM PDT 24
Finished Mar 31 03:14:32 PM PDT 24
Peak memory 198904 kb
Host smart-c6010520-77b9-43fe-a3d8-58ca50332a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113901747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3113901747
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.297623906
Short name T1134
Test name
Test status
Simulation time 24178182537 ps
CPU time 41.14 seconds
Started Mar 31 03:14:31 PM PDT 24
Finished Mar 31 03:15:13 PM PDT 24
Peak memory 200444 kb
Host smart-b263e98c-5bbd-4832-9e7b-78352f333b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297623906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.297623906
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.631172408
Short name T1033
Test name
Test status
Simulation time 3283501660 ps
CPU time 2.88 seconds
Started Mar 31 03:14:30 PM PDT 24
Finished Mar 31 03:14:33 PM PDT 24
Peak memory 196768 kb
Host smart-bdb7989d-fce9-47a1-aea2-22d91bf715dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631172408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.631172408
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3865350476
Short name T23
Test name
Test status
Simulation time 402328453 ps
CPU time 0.84 seconds
Started Mar 31 03:14:44 PM PDT 24
Finished Mar 31 03:14:45 PM PDT 24
Peak memory 218976 kb
Host smart-e8c88024-0c4c-4160-8190-3fe94bb66927
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865350476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3865350476
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2674414737
Short name T842
Test name
Test status
Simulation time 116959631 ps
CPU time 0.85 seconds
Started Mar 31 03:14:20 PM PDT 24
Finished Mar 31 03:14:21 PM PDT 24
Peak memory 198592 kb
Host smart-b0fcfbcf-a4cd-4503-9fc9-600d4082a65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674414737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2674414737
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3813534140
Short name T924
Test name
Test status
Simulation time 645626294097 ps
CPU time 259.15 seconds
Started Mar 31 03:14:42 PM PDT 24
Finished Mar 31 03:19:01 PM PDT 24
Peak memory 200740 kb
Host smart-d375dba6-03d2-4fd6-9942-ab7eca12736e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813534140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3813534140
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.163152304
Short name T815
Test name
Test status
Simulation time 98251777508 ps
CPU time 1018.33 seconds
Started Mar 31 03:14:42 PM PDT 24
Finished Mar 31 03:31:41 PM PDT 24
Peak memory 225436 kb
Host smart-c4247a24-e157-410c-a9f0-edf74d287e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163152304 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.163152304
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1949362575
Short name T565
Test name
Test status
Simulation time 12037691965 ps
CPU time 29.33 seconds
Started Mar 31 03:14:37 PM PDT 24
Finished Mar 31 03:15:06 PM PDT 24
Peak memory 200412 kb
Host smart-a3011e33-5833-44c0-9a80-e034e9a1bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949362575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1949362575
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.103053024
Short name T694
Test name
Test status
Simulation time 46469707415 ps
CPU time 52.9 seconds
Started Mar 31 03:14:20 PM PDT 24
Finished Mar 31 03:15:13 PM PDT 24
Peak memory 200496 kb
Host smart-0580a905-85da-47ab-b6c9-06d47dbc083f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103053024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.103053024
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2690632885
Short name T945
Test name
Test status
Simulation time 41068374 ps
CPU time 0.54 seconds
Started Mar 31 03:17:26 PM PDT 24
Finished Mar 31 03:17:27 PM PDT 24
Peak memory 195872 kb
Host smart-24d25d36-402c-4094-bc4c-41a4f4af516f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690632885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2690632885
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2276564245
Short name T658
Test name
Test status
Simulation time 39651376596 ps
CPU time 75.02 seconds
Started Mar 31 03:17:11 PM PDT 24
Finished Mar 31 03:18:26 PM PDT 24
Peak memory 200488 kb
Host smart-74413f1d-3009-4e10-95ff-01902541e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276564245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2276564245
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2803977111
Short name T1127
Test name
Test status
Simulation time 12736931589 ps
CPU time 14.16 seconds
Started Mar 31 03:17:17 PM PDT 24
Finished Mar 31 03:17:31 PM PDT 24
Peak memory 200004 kb
Host smart-592072ac-45bd-45af-aed9-60b151af5482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803977111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2803977111
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.865292507
Short name T199
Test name
Test status
Simulation time 39588309445 ps
CPU time 76.56 seconds
Started Mar 31 03:17:16 PM PDT 24
Finished Mar 31 03:18:32 PM PDT 24
Peak memory 200532 kb
Host smart-e0b4b74f-ebbf-4e4b-9951-d49a7c119875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865292507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.865292507
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.4097479849
Short name T1001
Test name
Test status
Simulation time 1261430264 ps
CPU time 1.71 seconds
Started Mar 31 03:17:21 PM PDT 24
Finished Mar 31 03:17:22 PM PDT 24
Peak memory 196900 kb
Host smart-3ef43dbf-a6ce-4585-8eac-ba1cac5b1876
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097479849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.4097479849
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3159181280
Short name T601
Test name
Test status
Simulation time 196403451855 ps
CPU time 604.02 seconds
Started Mar 31 03:17:21 PM PDT 24
Finished Mar 31 03:27:25 PM PDT 24
Peak memory 200444 kb
Host smart-9bff69ac-63c0-4135-a10f-3370ed67f4fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159181280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3159181280
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3530534163
Short name T1071
Test name
Test status
Simulation time 10121029954 ps
CPU time 21.4 seconds
Started Mar 31 03:17:23 PM PDT 24
Finished Mar 31 03:17:45 PM PDT 24
Peak memory 200408 kb
Host smart-cc49147b-05ee-42d1-b7d8-5d1de056a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530534163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3530534163
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2934267918
Short name T851
Test name
Test status
Simulation time 26274731007 ps
CPU time 20.74 seconds
Started Mar 31 03:17:21 PM PDT 24
Finished Mar 31 03:17:42 PM PDT 24
Peak memory 200720 kb
Host smart-e423efc2-24ba-4f70-aba3-9a0cd3f15c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934267918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2934267918
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3909166971
Short name T956
Test name
Test status
Simulation time 17849405865 ps
CPU time 259.37 seconds
Started Mar 31 03:17:21 PM PDT 24
Finished Mar 31 03:21:41 PM PDT 24
Peak memory 200492 kb
Host smart-f61d4176-0f0a-441b-b566-fc49808f2f1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909166971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3909166971
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4235534028
Short name T318
Test name
Test status
Simulation time 1296660628 ps
CPU time 1.87 seconds
Started Mar 31 03:17:17 PM PDT 24
Finished Mar 31 03:17:20 PM PDT 24
Peak memory 198500 kb
Host smart-3cfaf599-4029-48d8-8a62-8d58a17b23f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235534028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4235534028
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.560941494
Short name T1107
Test name
Test status
Simulation time 127966143417 ps
CPU time 50.92 seconds
Started Mar 31 03:17:23 PM PDT 24
Finished Mar 31 03:18:14 PM PDT 24
Peak memory 200452 kb
Host smart-be92e267-03bd-4e9b-8d88-f777ebd26047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560941494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.560941494
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2802175948
Short name T975
Test name
Test status
Simulation time 3748290456 ps
CPU time 6.99 seconds
Started Mar 31 03:17:22 PM PDT 24
Finished Mar 31 03:17:29 PM PDT 24
Peak memory 196520 kb
Host smart-dbc3bd67-8e81-44ee-b6dd-3164dd46217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802175948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2802175948
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2122124651
Short name T379
Test name
Test status
Simulation time 644280297 ps
CPU time 3.08 seconds
Started Mar 31 03:17:12 PM PDT 24
Finished Mar 31 03:17:15 PM PDT 24
Peak memory 200400 kb
Host smart-34f312d5-bef8-416d-bcde-8ec050590b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122124651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2122124651
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2710123849
Short name T40
Test name
Test status
Simulation time 318770021318 ps
CPU time 799.94 seconds
Started Mar 31 03:17:21 PM PDT 24
Finished Mar 31 03:30:41 PM PDT 24
Peak memory 229780 kb
Host smart-fc0987a9-6429-4d93-a2a4-73a4c972a816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710123849 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2710123849
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1308604531
Short name T995
Test name
Test status
Simulation time 883550010 ps
CPU time 4.05 seconds
Started Mar 31 03:17:22 PM PDT 24
Finished Mar 31 03:17:27 PM PDT 24
Peak memory 199368 kb
Host smart-b46df7fb-0636-4bab-8ecf-f3f5610be979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308604531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1308604531
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2565855674
Short name T1010
Test name
Test status
Simulation time 2033586743 ps
CPU time 4.39 seconds
Started Mar 31 03:17:09 PM PDT 24
Finished Mar 31 03:17:14 PM PDT 24
Peak memory 200252 kb
Host smart-e7037f6a-41ec-4a27-8cfc-ad3d259e38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565855674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2565855674
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1201927441
Short name T503
Test name
Test status
Simulation time 26669759043 ps
CPU time 42.18 seconds
Started Mar 31 03:25:49 PM PDT 24
Finished Mar 31 03:26:31 PM PDT 24
Peak memory 200560 kb
Host smart-20f01dcd-e94e-4de5-8453-258203290b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201927441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1201927441
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3448901303
Short name T722
Test name
Test status
Simulation time 75794014300 ps
CPU time 67.35 seconds
Started Mar 31 03:25:51 PM PDT 24
Finished Mar 31 03:26:59 PM PDT 24
Peak memory 200472 kb
Host smart-1b4fa456-c1f3-49ab-b1cd-2993daa462f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448901303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3448901303
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1371574728
Short name T1150
Test name
Test status
Simulation time 21229409533 ps
CPU time 44.24 seconds
Started Mar 31 03:25:51 PM PDT 24
Finished Mar 31 03:26:35 PM PDT 24
Peak memory 200500 kb
Host smart-7f42ba9d-cf46-4d4b-9f67-1156cc4e40e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371574728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1371574728
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1149052563
Short name T964
Test name
Test status
Simulation time 42624208050 ps
CPU time 14.07 seconds
Started Mar 31 03:25:51 PM PDT 24
Finished Mar 31 03:26:05 PM PDT 24
Peak memory 200152 kb
Host smart-30e1ad42-308c-4a7d-bae9-fefbcf30eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149052563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1149052563
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3762411789
Short name T147
Test name
Test status
Simulation time 69771824152 ps
CPU time 44.48 seconds
Started Mar 31 03:25:53 PM PDT 24
Finished Mar 31 03:26:38 PM PDT 24
Peak memory 200400 kb
Host smart-0560a3e6-d113-43b7-a88c-3418492f2e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762411789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3762411789
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.593941022
Short name T1034
Test name
Test status
Simulation time 53557512510 ps
CPU time 30.87 seconds
Started Mar 31 03:25:52 PM PDT 24
Finished Mar 31 03:26:23 PM PDT 24
Peak memory 200368 kb
Host smart-31892284-c98c-452b-982b-b34412f9f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593941022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.593941022
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3490980108
Short name T980
Test name
Test status
Simulation time 26515928382 ps
CPU time 54.19 seconds
Started Mar 31 03:25:51 PM PDT 24
Finished Mar 31 03:26:45 PM PDT 24
Peak memory 200532 kb
Host smart-73f65205-94cb-4b7f-aec3-93ce23a557bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490980108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3490980108
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1496779525
Short name T1029
Test name
Test status
Simulation time 38764258511 ps
CPU time 17.48 seconds
Started Mar 31 03:25:53 PM PDT 24
Finished Mar 31 03:26:10 PM PDT 24
Peak memory 200492 kb
Host smart-478e869d-0182-4ced-a44b-baef3ebafbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496779525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1496779525
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3166429013
Short name T623
Test name
Test status
Simulation time 35641460 ps
CPU time 0.56 seconds
Started Mar 31 03:17:41 PM PDT 24
Finished Mar 31 03:17:42 PM PDT 24
Peak memory 195900 kb
Host smart-9ab5f1ca-4585-438b-9a72-fab4ff062b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166429013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3166429013
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1837128583
Short name T836
Test name
Test status
Simulation time 26754330891 ps
CPU time 42.39 seconds
Started Mar 31 03:17:26 PM PDT 24
Finished Mar 31 03:18:09 PM PDT 24
Peak memory 200468 kb
Host smart-e69e8746-1f9b-4158-bfea-fbeed1359d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837128583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1837128583
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.399370516
Short name T539
Test name
Test status
Simulation time 28196638261 ps
CPU time 14.44 seconds
Started Mar 31 03:17:27 PM PDT 24
Finished Mar 31 03:17:42 PM PDT 24
Peak memory 200464 kb
Host smart-b005a8a6-f673-436d-b1c9-1f13a8546bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399370516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.399370516
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2349076653
Short name T213
Test name
Test status
Simulation time 38645154062 ps
CPU time 16.4 seconds
Started Mar 31 03:17:27 PM PDT 24
Finished Mar 31 03:17:43 PM PDT 24
Peak memory 200532 kb
Host smart-b54151f1-da5e-463d-aecb-cd46bab2084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349076653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2349076653
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1651562124
Short name T441
Test name
Test status
Simulation time 13061619575 ps
CPU time 6.62 seconds
Started Mar 31 03:17:33 PM PDT 24
Finished Mar 31 03:17:40 PM PDT 24
Peak memory 199796 kb
Host smart-4f8ab798-7fac-4585-874f-0966888f80ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651562124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1651562124
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1678098534
Short name T802
Test name
Test status
Simulation time 135671291342 ps
CPU time 138.25 seconds
Started Mar 31 03:17:42 PM PDT 24
Finished Mar 31 03:20:00 PM PDT 24
Peak memory 200488 kb
Host smart-cd870a5a-ad1a-4660-92e4-ef163dfb28cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678098534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1678098534
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2089891280
Short name T336
Test name
Test status
Simulation time 2637289749 ps
CPU time 6.4 seconds
Started Mar 31 03:17:33 PM PDT 24
Finished Mar 31 03:17:40 PM PDT 24
Peak memory 199432 kb
Host smart-fefd695b-c2c9-4575-a0be-e4680538daf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089891280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2089891280
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2518657307
Short name T487
Test name
Test status
Simulation time 56210538840 ps
CPU time 114.17 seconds
Started Mar 31 03:17:32 PM PDT 24
Finished Mar 31 03:19:26 PM PDT 24
Peak memory 208744 kb
Host smart-1aab798e-ad6f-4c92-b03e-2a4149006dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518657307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2518657307
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.999195882
Short name T1133
Test name
Test status
Simulation time 21924558277 ps
CPU time 108.09 seconds
Started Mar 31 03:17:40 PM PDT 24
Finished Mar 31 03:19:29 PM PDT 24
Peak memory 200508 kb
Host smart-48813496-5cb1-4f22-9854-0303b4fa096b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999195882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.999195882
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3764558951
Short name T1174
Test name
Test status
Simulation time 5623776318 ps
CPU time 2.9 seconds
Started Mar 31 03:17:33 PM PDT 24
Finished Mar 31 03:17:36 PM PDT 24
Peak memory 198696 kb
Host smart-d1e9cb4e-4c16-43ad-8b46-30a19f585831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764558951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3764558951
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2936804305
Short name T275
Test name
Test status
Simulation time 172404717821 ps
CPU time 402.92 seconds
Started Mar 31 03:17:33 PM PDT 24
Finished Mar 31 03:24:17 PM PDT 24
Peak memory 200504 kb
Host smart-2db9ba49-1da5-4838-b058-420104b4d05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936804305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2936804305
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3462244922
Short name T408
Test name
Test status
Simulation time 1585310140 ps
CPU time 1.17 seconds
Started Mar 31 03:17:33 PM PDT 24
Finished Mar 31 03:17:35 PM PDT 24
Peak memory 196168 kb
Host smart-6f365411-75d7-416a-a929-74b74b1391d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462244922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3462244922
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1765924317
Short name T471
Test name
Test status
Simulation time 692395450 ps
CPU time 1.37 seconds
Started Mar 31 03:17:26 PM PDT 24
Finished Mar 31 03:17:28 PM PDT 24
Peak memory 200356 kb
Host smart-6b3b1c99-e4f3-4764-8d02-41ad702a2575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765924317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1765924317
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3725575562
Short name T245
Test name
Test status
Simulation time 166952183147 ps
CPU time 623.67 seconds
Started Mar 31 03:17:38 PM PDT 24
Finished Mar 31 03:28:02 PM PDT 24
Peak memory 208916 kb
Host smart-d879fddc-e046-42cd-8878-2992e9725484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725575562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3725575562
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.264733361
Short name T752
Test name
Test status
Simulation time 27260429602 ps
CPU time 582.31 seconds
Started Mar 31 03:17:38 PM PDT 24
Finished Mar 31 03:27:21 PM PDT 24
Peak memory 216992 kb
Host smart-1054f266-3336-4e53-9be4-dd45365f7ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264733361 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.264733361
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4220836786
Short name T684
Test name
Test status
Simulation time 6468961461 ps
CPU time 18.82 seconds
Started Mar 31 03:17:33 PM PDT 24
Finished Mar 31 03:17:52 PM PDT 24
Peak memory 200360 kb
Host smart-4a4a0d16-8fee-4a5f-98e4-f2dce5323b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220836786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4220836786
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2462360748
Short name T709
Test name
Test status
Simulation time 60300132681 ps
CPU time 50.13 seconds
Started Mar 31 03:17:26 PM PDT 24
Finished Mar 31 03:18:17 PM PDT 24
Peak memory 200468 kb
Host smart-eb4dc14e-7d21-4615-97e3-a043298e77f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462360748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2462360748
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.441920105
Short name T1130
Test name
Test status
Simulation time 106637692696 ps
CPU time 94.68 seconds
Started Mar 31 03:26:01 PM PDT 24
Finished Mar 31 03:27:36 PM PDT 24
Peak memory 200512 kb
Host smart-bc9ff73f-c6bc-4629-a1f5-d1c5cd75f581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441920105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.441920105
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.890045987
Short name T1112
Test name
Test status
Simulation time 12213461262 ps
CPU time 21.25 seconds
Started Mar 31 03:25:58 PM PDT 24
Finished Mar 31 03:26:19 PM PDT 24
Peak memory 200448 kb
Host smart-94b8173b-2adb-442e-b368-38f46e7f21f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890045987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.890045987
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1535468636
Short name T656
Test name
Test status
Simulation time 60100160177 ps
CPU time 33.91 seconds
Started Mar 31 03:25:58 PM PDT 24
Finished Mar 31 03:26:32 PM PDT 24
Peak memory 200528 kb
Host smart-e8d2f87d-e982-4b4f-897f-d3ff95244884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535468636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1535468636
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.335470668
Short name T197
Test name
Test status
Simulation time 84378419051 ps
CPU time 168.76 seconds
Started Mar 31 03:25:58 PM PDT 24
Finished Mar 31 03:28:47 PM PDT 24
Peak memory 200408 kb
Host smart-4848131e-1c2b-48fe-a4fa-bddb64159142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335470668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.335470668
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2722016336
Short name T849
Test name
Test status
Simulation time 20377035103 ps
CPU time 18.08 seconds
Started Mar 31 03:26:05 PM PDT 24
Finished Mar 31 03:26:24 PM PDT 24
Peak memory 200528 kb
Host smart-0b794dc5-47dc-460d-9ae1-9ed516de6cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722016336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2722016336
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3262268477
Short name T942
Test name
Test status
Simulation time 34045629220 ps
CPU time 38.22 seconds
Started Mar 31 03:26:05 PM PDT 24
Finished Mar 31 03:26:44 PM PDT 24
Peak memory 200444 kb
Host smart-4e867eac-8f33-463c-a642-06407b277f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262268477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3262268477
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2508130993
Short name T278
Test name
Test status
Simulation time 46765371665 ps
CPU time 91.18 seconds
Started Mar 31 03:26:04 PM PDT 24
Finished Mar 31 03:27:36 PM PDT 24
Peak memory 200496 kb
Host smart-bad81e80-a166-46c2-9ce4-a62455a5a3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508130993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2508130993
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1846432627
Short name T619
Test name
Test status
Simulation time 158908728314 ps
CPU time 72.85 seconds
Started Mar 31 03:26:04 PM PDT 24
Finished Mar 31 03:27:17 PM PDT 24
Peak memory 200540 kb
Host smart-623ab7dd-fe7f-4a69-b748-f8a1d4f216af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846432627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1846432627
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.322787095
Short name T555
Test name
Test status
Simulation time 14498737 ps
CPU time 0.53 seconds
Started Mar 31 03:17:50 PM PDT 24
Finished Mar 31 03:17:50 PM PDT 24
Peak memory 195320 kb
Host smart-6f7f8f02-0047-449b-af08-abed09bb0f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322787095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.322787095
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2384977815
Short name T890
Test name
Test status
Simulation time 50832327906 ps
CPU time 73.01 seconds
Started Mar 31 03:17:38 PM PDT 24
Finished Mar 31 03:18:52 PM PDT 24
Peak memory 200452 kb
Host smart-7c4cef19-d95c-4506-b35e-079109a6c5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384977815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2384977815
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1460587544
Short name T1175
Test name
Test status
Simulation time 18439456215 ps
CPU time 27.78 seconds
Started Mar 31 03:17:41 PM PDT 24
Finished Mar 31 03:18:09 PM PDT 24
Peak memory 200524 kb
Host smart-5a79bbdf-9b65-4351-bcbc-db518dd95459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460587544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1460587544
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.3255273073
Short name T86
Test name
Test status
Simulation time 37308923589 ps
CPU time 16.25 seconds
Started Mar 31 03:17:44 PM PDT 24
Finished Mar 31 03:18:00 PM PDT 24
Peak memory 200444 kb
Host smart-e9f787bd-a338-4f19-bef6-06d6d99ed944
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255273073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3255273073
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1599138173
Short name T821
Test name
Test status
Simulation time 99516737178 ps
CPU time 256.9 seconds
Started Mar 31 03:17:49 PM PDT 24
Finished Mar 31 03:22:06 PM PDT 24
Peak memory 200444 kb
Host smart-9b20b602-c8de-4f2c-94a9-f9262d1307f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599138173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1599138173
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2663554798
Short name T692
Test name
Test status
Simulation time 3195946280 ps
CPU time 7.94 seconds
Started Mar 31 03:17:51 PM PDT 24
Finished Mar 31 03:17:59 PM PDT 24
Peak memory 199292 kb
Host smart-bca5af95-a010-411a-bedf-0a424692ef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663554798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2663554798
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.4214213562
Short name T937
Test name
Test status
Simulation time 36413635363 ps
CPU time 71.13 seconds
Started Mar 31 03:17:43 PM PDT 24
Finished Mar 31 03:18:55 PM PDT 24
Peak memory 200296 kb
Host smart-9a8ba7c8-9937-43fd-a0b4-1f1e6aa0b7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214213562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.4214213562
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.870261563
Short name T91
Test name
Test status
Simulation time 16751485666 ps
CPU time 179.89 seconds
Started Mar 31 03:17:49 PM PDT 24
Finished Mar 31 03:20:49 PM PDT 24
Peak memory 200436 kb
Host smart-196c0726-9eae-4b7e-9ece-a7137ecd43cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870261563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.870261563
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.421291751
Short name T662
Test name
Test status
Simulation time 6446582525 ps
CPU time 29.28 seconds
Started Mar 31 03:17:44 PM PDT 24
Finished Mar 31 03:18:13 PM PDT 24
Peak memory 199956 kb
Host smart-17d06ca0-aa2a-43ae-9e76-e6582365b964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421291751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.421291751
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.754355542
Short name T14
Test name
Test status
Simulation time 8246549912 ps
CPU time 14.68 seconds
Started Mar 31 03:17:43 PM PDT 24
Finished Mar 31 03:17:58 PM PDT 24
Peak memory 200448 kb
Host smart-8385d2e5-c920-4bce-9b01-85f706ba33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754355542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.754355542
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.814303796
Short name T1002
Test name
Test status
Simulation time 34944641344 ps
CPU time 6.34 seconds
Started Mar 31 03:17:44 PM PDT 24
Finished Mar 31 03:17:50 PM PDT 24
Peak memory 196504 kb
Host smart-25f15c4d-27f1-4f34-9626-8d399496b7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814303796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.814303796
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1799600923
Short name T856
Test name
Test status
Simulation time 922386240 ps
CPU time 1.82 seconds
Started Mar 31 03:17:37 PM PDT 24
Finished Mar 31 03:17:39 PM PDT 24
Peak memory 199928 kb
Host smart-50478f62-939b-47b0-b81d-c6cf6ea21512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799600923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1799600923
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1872231325
Short name T1047
Test name
Test status
Simulation time 423485054908 ps
CPU time 547.94 seconds
Started Mar 31 03:17:50 PM PDT 24
Finished Mar 31 03:26:58 PM PDT 24
Peak memory 209332 kb
Host smart-3a8321fd-57a1-4066-a041-d154e4785ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872231325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1872231325
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2131103573
Short name T423
Test name
Test status
Simulation time 111615612436 ps
CPU time 577.68 seconds
Started Mar 31 03:17:50 PM PDT 24
Finished Mar 31 03:27:28 PM PDT 24
Peak memory 217216 kb
Host smart-a5fd745e-0616-4bae-ac4b-6b8ea06826e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131103573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2131103573
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3370788024
Short name T413
Test name
Test status
Simulation time 6231093562 ps
CPU time 26.73 seconds
Started Mar 31 03:17:44 PM PDT 24
Finished Mar 31 03:18:12 PM PDT 24
Peak memory 199652 kb
Host smart-5122cc90-0d82-4c66-984f-15519bdbc63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370788024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3370788024
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1604756138
Short name T1161
Test name
Test status
Simulation time 31548735410 ps
CPU time 35.46 seconds
Started Mar 31 03:17:39 PM PDT 24
Finished Mar 31 03:18:14 PM PDT 24
Peak memory 200416 kb
Host smart-84f2f8a9-abcc-4be8-adbc-0ed38d933dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604756138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1604756138
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3758994862
Short name T188
Test name
Test status
Simulation time 56185309374 ps
CPU time 32.71 seconds
Started Mar 31 03:26:04 PM PDT 24
Finished Mar 31 03:26:37 PM PDT 24
Peak memory 200460 kb
Host smart-40456065-b90a-44d6-9a97-cd9882e3f61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758994862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3758994862
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1022698410
Short name T800
Test name
Test status
Simulation time 124452047340 ps
CPU time 143.15 seconds
Started Mar 31 03:26:06 PM PDT 24
Finished Mar 31 03:28:29 PM PDT 24
Peak memory 200500 kb
Host smart-774eea55-434d-460b-820c-0b60de40b548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022698410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1022698410
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.4080079491
Short name T151
Test name
Test status
Simulation time 17812853162 ps
CPU time 21.07 seconds
Started Mar 31 03:26:09 PM PDT 24
Finished Mar 31 03:26:31 PM PDT 24
Peak memory 200520 kb
Host smart-81298ac3-9976-4f65-a702-802e1f58dfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080079491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4080079491
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.157492097
Short name T1140
Test name
Test status
Simulation time 86409762383 ps
CPU time 12.66 seconds
Started Mar 31 03:26:09 PM PDT 24
Finished Mar 31 03:26:22 PM PDT 24
Peak memory 200380 kb
Host smart-f1d70d7e-3b3e-414c-b40f-a72524fbee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157492097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.157492097
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2129212150
Short name T140
Test name
Test status
Simulation time 57617189577 ps
CPU time 82.59 seconds
Started Mar 31 03:26:10 PM PDT 24
Finished Mar 31 03:27:33 PM PDT 24
Peak memory 200124 kb
Host smart-4cbaf8b1-593c-4156-be33-de0a5c15606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129212150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2129212150
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3560034631
Short name T764
Test name
Test status
Simulation time 22088541927 ps
CPU time 26.68 seconds
Started Mar 31 03:26:09 PM PDT 24
Finished Mar 31 03:26:36 PM PDT 24
Peak memory 200504 kb
Host smart-a035437d-765f-4f9e-ad24-23c0bf3eda0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560034631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3560034631
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.4226487214
Short name T5
Test name
Test status
Simulation time 130554861915 ps
CPU time 102.22 seconds
Started Mar 31 03:26:10 PM PDT 24
Finished Mar 31 03:27:52 PM PDT 24
Peak memory 200460 kb
Host smart-4ffef173-6adf-4328-8a33-7a1eb3bacff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226487214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.4226487214
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3364176985
Short name T774
Test name
Test status
Simulation time 13594933 ps
CPU time 0.56 seconds
Started Mar 31 03:18:04 PM PDT 24
Finished Mar 31 03:18:05 PM PDT 24
Peak memory 196092 kb
Host smart-0adf1704-0d34-4bc1-9324-9d0c0c548d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364176985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3364176985
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.7055809
Short name T297
Test name
Test status
Simulation time 93300854514 ps
CPU time 299.32 seconds
Started Mar 31 03:17:50 PM PDT 24
Finished Mar 31 03:22:49 PM PDT 24
Peak memory 200408 kb
Host smart-044a6ba4-da74-4129-a761-aeab8b8e9738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7055809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.7055809
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2565672557
Short name T135
Test name
Test status
Simulation time 95201351340 ps
CPU time 18.52 seconds
Started Mar 31 03:17:49 PM PDT 24
Finished Mar 31 03:18:08 PM PDT 24
Peak memory 200472 kb
Host smart-9e81bd56-fd7f-41a3-ae77-72436a119280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565672557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2565672557
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3981438052
Short name T146
Test name
Test status
Simulation time 15238620569 ps
CPU time 29.74 seconds
Started Mar 31 03:18:00 PM PDT 24
Finished Mar 31 03:18:30 PM PDT 24
Peak memory 200516 kb
Host smart-6780b49e-b568-46d5-bce9-d040309c0263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981438052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3981438052
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1583774279
Short name T386
Test name
Test status
Simulation time 42463949106 ps
CPU time 20.64 seconds
Started Mar 31 03:17:59 PM PDT 24
Finished Mar 31 03:18:19 PM PDT 24
Peak memory 200524 kb
Host smart-d357954d-62b9-481f-a72d-d8afc0c30df7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583774279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1583774279
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4037908305
Short name T491
Test name
Test status
Simulation time 76003520401 ps
CPU time 111.27 seconds
Started Mar 31 03:18:07 PM PDT 24
Finished Mar 31 03:19:58 PM PDT 24
Peak memory 200476 kb
Host smart-3594144b-2620-4181-863a-b83fc2da8031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037908305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4037908305
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2871361909
Short name T979
Test name
Test status
Simulation time 4103723573 ps
CPU time 3.91 seconds
Started Mar 31 03:17:58 PM PDT 24
Finished Mar 31 03:18:02 PM PDT 24
Peak memory 196796 kb
Host smart-85871166-ace2-4bfd-a1e6-c4fdea20cc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871361909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2871361909
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.767914767
Short name T988
Test name
Test status
Simulation time 40797929134 ps
CPU time 73.65 seconds
Started Mar 31 03:17:58 PM PDT 24
Finished Mar 31 03:19:12 PM PDT 24
Peak memory 200564 kb
Host smart-e5b7a9ca-ec3b-4db8-b7e6-6b38aac8f16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767914767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.767914767
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.938410339
Short name T257
Test name
Test status
Simulation time 19870228637 ps
CPU time 202.08 seconds
Started Mar 31 03:18:05 PM PDT 24
Finished Mar 31 03:21:27 PM PDT 24
Peak memory 200504 kb
Host smart-3ffae685-99e6-4338-bda0-0a3d25126915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938410339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.938410339
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2167783510
Short name T454
Test name
Test status
Simulation time 7332696272 ps
CPU time 61.53 seconds
Started Mar 31 03:17:59 PM PDT 24
Finished Mar 31 03:19:01 PM PDT 24
Peak memory 199652 kb
Host smart-c66068fc-269e-4f6b-8283-5478db945d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167783510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2167783510
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1773926369
Short name T1009
Test name
Test status
Simulation time 57164737429 ps
CPU time 7.78 seconds
Started Mar 31 03:18:00 PM PDT 24
Finished Mar 31 03:18:08 PM PDT 24
Peak memory 200492 kb
Host smart-450267bb-4ab1-457f-b828-4c72275c4727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773926369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1773926369
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3892959261
Short name T18
Test name
Test status
Simulation time 3655054931 ps
CPU time 6.28 seconds
Started Mar 31 03:17:58 PM PDT 24
Finished Mar 31 03:18:04 PM PDT 24
Peak memory 196500 kb
Host smart-cfade3a2-055f-4a80-92c9-7cd715514626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892959261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3892959261
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1642778235
Short name T292
Test name
Test status
Simulation time 6211122607 ps
CPU time 17.7 seconds
Started Mar 31 03:17:51 PM PDT 24
Finished Mar 31 03:18:09 PM PDT 24
Peak memory 200136 kb
Host smart-69552c5b-2176-41ae-b449-c30d31027ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642778235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1642778235
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3280967500
Short name T713
Test name
Test status
Simulation time 352929548182 ps
CPU time 2330.05 seconds
Started Mar 31 03:18:05 PM PDT 24
Finished Mar 31 03:56:55 PM PDT 24
Peak memory 200460 kb
Host smart-338bc0ef-8861-4839-a958-f236ade40592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280967500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3280967500
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.239668265
Short name T29
Test name
Test status
Simulation time 27586972542 ps
CPU time 163.11 seconds
Started Mar 31 03:18:04 PM PDT 24
Finished Mar 31 03:20:47 PM PDT 24
Peak memory 208780 kb
Host smart-0dbfc484-b853-4c51-9f8c-a5920bf4587e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239668265 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.239668265
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3702879949
Short name T806
Test name
Test status
Simulation time 847846131 ps
CPU time 2.72 seconds
Started Mar 31 03:17:57 PM PDT 24
Finished Mar 31 03:18:00 PM PDT 24
Peak memory 199564 kb
Host smart-28708882-4c54-42ca-ace5-2e8fb318f0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702879949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3702879949
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2500033957
Short name T1078
Test name
Test status
Simulation time 105168344029 ps
CPU time 75.74 seconds
Started Mar 31 03:17:50 PM PDT 24
Finished Mar 31 03:19:05 PM PDT 24
Peak memory 200452 kb
Host smart-2076c6c9-c9dd-4890-89ec-3b40e13cc653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500033957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2500033957
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2068939110
Short name T1103
Test name
Test status
Simulation time 9209671423 ps
CPU time 4.54 seconds
Started Mar 31 03:26:10 PM PDT 24
Finished Mar 31 03:26:14 PM PDT 24
Peak memory 200544 kb
Host smart-0569dde2-cc81-4785-bdf1-0721c5bad279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068939110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2068939110
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4065879209
Short name T534
Test name
Test status
Simulation time 67020060679 ps
CPU time 185.97 seconds
Started Mar 31 03:26:16 PM PDT 24
Finished Mar 31 03:29:22 PM PDT 24
Peak memory 200512 kb
Host smart-f506a67a-61ed-41d1-beb1-ed1fbf0a3d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065879209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4065879209
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2295152590
Short name T955
Test name
Test status
Simulation time 86842281171 ps
CPU time 87.14 seconds
Started Mar 31 03:26:17 PM PDT 24
Finished Mar 31 03:27:45 PM PDT 24
Peak memory 200464 kb
Host smart-12dd0312-e217-4805-8b78-b5c1dffa8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295152590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2295152590
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3611935820
Short name T1036
Test name
Test status
Simulation time 52946033108 ps
CPU time 89.26 seconds
Started Mar 31 03:26:16 PM PDT 24
Finished Mar 31 03:27:46 PM PDT 24
Peak memory 200528 kb
Host smart-c997bd4b-0cd2-46cd-8174-6e82c69e5b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611935820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3611935820
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3916860014
Short name T218
Test name
Test status
Simulation time 406537644258 ps
CPU time 72.35 seconds
Started Mar 31 03:26:16 PM PDT 24
Finished Mar 31 03:27:29 PM PDT 24
Peak memory 200524 kb
Host smart-ace80843-f85e-4164-8ab5-7813be33c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916860014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3916860014
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.414670695
Short name T38
Test name
Test status
Simulation time 22487839778 ps
CPU time 30.21 seconds
Started Mar 31 03:26:23 PM PDT 24
Finished Mar 31 03:26:53 PM PDT 24
Peak memory 200248 kb
Host smart-b803a82f-6d81-47ab-9de7-7844166af98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414670695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.414670695
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1808606845
Short name T916
Test name
Test status
Simulation time 53153985855 ps
CPU time 50.05 seconds
Started Mar 31 03:26:22 PM PDT 24
Finished Mar 31 03:27:12 PM PDT 24
Peak memory 200432 kb
Host smart-33c247ef-c3d8-4b22-9fd9-b3535ec107dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808606845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1808606845
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.803063297
Short name T366
Test name
Test status
Simulation time 27471128273 ps
CPU time 39.19 seconds
Started Mar 31 03:26:22 PM PDT 24
Finished Mar 31 03:27:01 PM PDT 24
Peak memory 200472 kb
Host smart-0c0d4493-5cfb-44a2-a544-94e5392bc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803063297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.803063297
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1450230486
Short name T925
Test name
Test status
Simulation time 47703391 ps
CPU time 0.51 seconds
Started Mar 31 03:18:16 PM PDT 24
Finished Mar 31 03:18:17 PM PDT 24
Peak memory 194872 kb
Host smart-e7811cb7-2f9d-4692-b11f-f0da20cb7cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450230486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1450230486
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1445253391
Short name T547
Test name
Test status
Simulation time 92483256743 ps
CPU time 34.15 seconds
Started Mar 31 03:18:04 PM PDT 24
Finished Mar 31 03:18:38 PM PDT 24
Peak memory 200500 kb
Host smart-b112563f-6803-489d-b56a-d70adb69d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445253391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1445253391
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.588042513
Short name T754
Test name
Test status
Simulation time 304789818371 ps
CPU time 82.89 seconds
Started Mar 31 03:18:06 PM PDT 24
Finished Mar 31 03:19:29 PM PDT 24
Peak memory 200480 kb
Host smart-116dfa71-0f06-44b4-b4a5-120c4e093adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588042513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.588042513
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.580094549
Short name T602
Test name
Test status
Simulation time 122136064195 ps
CPU time 146.49 seconds
Started Mar 31 03:18:10 PM PDT 24
Finished Mar 31 03:20:36 PM PDT 24
Peak memory 200512 kb
Host smart-e042a1c7-33f0-4d34-a75a-49583bbcace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580094549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.580094549
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1130186507
Short name T832
Test name
Test status
Simulation time 8547180695 ps
CPU time 5.52 seconds
Started Mar 31 03:18:14 PM PDT 24
Finished Mar 31 03:18:19 PM PDT 24
Peak memory 199424 kb
Host smart-819ac515-3aea-4df7-9dac-b14efc247156
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130186507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1130186507
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1184197616
Short name T635
Test name
Test status
Simulation time 101648476684 ps
CPU time 566.74 seconds
Started Mar 31 03:18:16 PM PDT 24
Finished Mar 31 03:27:43 PM PDT 24
Peak memory 200532 kb
Host smart-4f263c05-f306-47cd-bf39-49010ab1d50b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184197616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1184197616
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3766372277
Short name T976
Test name
Test status
Simulation time 2529910999 ps
CPU time 2.52 seconds
Started Mar 31 03:18:10 PM PDT 24
Finished Mar 31 03:18:13 PM PDT 24
Peak memory 199544 kb
Host smart-8e8811b7-f8ba-4d16-95a7-4dd2cfeb3e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766372277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3766372277
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.679987933
Short name T470
Test name
Test status
Simulation time 108876981290 ps
CPU time 40.9 seconds
Started Mar 31 03:18:10 PM PDT 24
Finished Mar 31 03:18:51 PM PDT 24
Peak memory 200760 kb
Host smart-89e43f95-7ae3-4ac3-8f78-8087fa63b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679987933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.679987933
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2673412854
Short name T476
Test name
Test status
Simulation time 15062589155 ps
CPU time 382.64 seconds
Started Mar 31 03:18:18 PM PDT 24
Finished Mar 31 03:24:41 PM PDT 24
Peak memory 200448 kb
Host smart-ff1f4b75-7032-4703-9253-c73db43a1e44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673412854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2673412854
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2248168999
Short name T638
Test name
Test status
Simulation time 7240852225 ps
CPU time 31.4 seconds
Started Mar 31 03:18:11 PM PDT 24
Finished Mar 31 03:18:42 PM PDT 24
Peak memory 199996 kb
Host smart-a2ae003f-3da5-4fac-8158-9f6ce3aa6be8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248168999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2248168999
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.968771753
Short name T818
Test name
Test status
Simulation time 91831736866 ps
CPU time 38.91 seconds
Started Mar 31 03:18:09 PM PDT 24
Finished Mar 31 03:18:48 PM PDT 24
Peak memory 200368 kb
Host smart-091ce089-bff3-46e1-8f82-b30b2528d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968771753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.968771753
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1191298888
Short name T543
Test name
Test status
Simulation time 2550749892 ps
CPU time 1.66 seconds
Started Mar 31 03:18:09 PM PDT 24
Finished Mar 31 03:18:11 PM PDT 24
Peak memory 196508 kb
Host smart-e44e86ed-0616-4564-a1f8-c7ac319e2de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191298888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1191298888
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3106778340
Short name T690
Test name
Test status
Simulation time 285277050 ps
CPU time 1.44 seconds
Started Mar 31 03:18:07 PM PDT 24
Finished Mar 31 03:18:08 PM PDT 24
Peak memory 200124 kb
Host smart-13424405-c565-45a8-94a9-4d291706d0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106778340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3106778340
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2397015497
Short name T762
Test name
Test status
Simulation time 141292453485 ps
CPU time 1055.82 seconds
Started Mar 31 03:18:17 PM PDT 24
Finished Mar 31 03:35:54 PM PDT 24
Peak memory 200400 kb
Host smart-9d412419-70c3-40f7-9513-5e3db257e07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397015497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2397015497
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2932606175
Short name T734
Test name
Test status
Simulation time 58546753859 ps
CPU time 1240.02 seconds
Started Mar 31 03:18:17 PM PDT 24
Finished Mar 31 03:38:57 PM PDT 24
Peak memory 217000 kb
Host smart-24d6f82e-59c9-455f-960d-5d489ff7d2e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932606175 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2932606175
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3177349884
Short name T451
Test name
Test status
Simulation time 735421634 ps
CPU time 4.45 seconds
Started Mar 31 03:18:11 PM PDT 24
Finished Mar 31 03:18:16 PM PDT 24
Peak memory 199360 kb
Host smart-59050fc5-1284-4662-b953-f5e51913447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177349884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3177349884
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4220848605
Short name T507
Test name
Test status
Simulation time 97976144444 ps
CPU time 78.44 seconds
Started Mar 31 03:18:06 PM PDT 24
Finished Mar 31 03:19:24 PM PDT 24
Peak memory 200424 kb
Host smart-cf4aa495-e258-4cd7-a319-b9bb9535e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220848605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4220848605
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.4019240803
Short name T521
Test name
Test status
Simulation time 25115439042 ps
CPU time 48.67 seconds
Started Mar 31 03:26:29 PM PDT 24
Finished Mar 31 03:27:17 PM PDT 24
Peak memory 200504 kb
Host smart-565658a3-8b46-4280-b24f-7810f437d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019240803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.4019240803
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.651765940
Short name T219
Test name
Test status
Simulation time 9147183073 ps
CPU time 16.36 seconds
Started Mar 31 03:26:27 PM PDT 24
Finished Mar 31 03:26:44 PM PDT 24
Peak memory 200300 kb
Host smart-a9b3ccdb-0ca3-48b0-99b6-a6cff40052d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651765940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.651765940
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3325693637
Short name T1147
Test name
Test status
Simulation time 103760523511 ps
CPU time 162.57 seconds
Started Mar 31 03:26:28 PM PDT 24
Finished Mar 31 03:29:11 PM PDT 24
Peak memory 200472 kb
Host smart-417176e8-5a9f-47ae-8d70-a1bc694613ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325693637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3325693637
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1869868933
Short name T683
Test name
Test status
Simulation time 204625697635 ps
CPU time 38.85 seconds
Started Mar 31 03:26:28 PM PDT 24
Finished Mar 31 03:27:07 PM PDT 24
Peak memory 200468 kb
Host smart-82514ab3-9077-4bc4-8e06-f9fbbbe73ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869868933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1869868933
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3900030560
Short name T663
Test name
Test status
Simulation time 16301657792 ps
CPU time 23.86 seconds
Started Mar 31 03:26:29 PM PDT 24
Finished Mar 31 03:26:53 PM PDT 24
Peak memory 200436 kb
Host smart-1eb16ec4-b2bf-43ac-afe0-3d1bac79c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900030560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3900030560
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1209724035
Short name T203
Test name
Test status
Simulation time 47674525585 ps
CPU time 6.73 seconds
Started Mar 31 03:26:34 PM PDT 24
Finished Mar 31 03:26:41 PM PDT 24
Peak memory 200104 kb
Host smart-faf604fc-d6fb-4362-acaf-776086eef232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209724035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1209724035
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.913806047
Short name T437
Test name
Test status
Simulation time 70127493584 ps
CPU time 29.07 seconds
Started Mar 31 03:26:36 PM PDT 24
Finished Mar 31 03:27:05 PM PDT 24
Peak memory 200536 kb
Host smart-b4599624-4e0c-48d8-87ca-7efb160feef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913806047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.913806047
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3145282409
Short name T719
Test name
Test status
Simulation time 32186522 ps
CPU time 0.53 seconds
Started Mar 31 03:18:29 PM PDT 24
Finished Mar 31 03:18:30 PM PDT 24
Peak memory 195352 kb
Host smart-ed47cdcb-3468-439b-b09f-114d8f669367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145282409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3145282409
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2289290886
Short name T1070
Test name
Test status
Simulation time 45689701130 ps
CPU time 17.92 seconds
Started Mar 31 03:18:17 PM PDT 24
Finished Mar 31 03:18:35 PM PDT 24
Peak memory 200492 kb
Host smart-f3eb7e42-4bf9-4e10-b2bf-bf58c79b70ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289290886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2289290886
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2043915361
Short name T1155
Test name
Test status
Simulation time 66557830623 ps
CPU time 183.95 seconds
Started Mar 31 03:18:17 PM PDT 24
Finished Mar 31 03:21:21 PM PDT 24
Peak memory 200480 kb
Host smart-08c2d406-0d32-4b3d-9261-d92311a16f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043915361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2043915361
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3716653934
Short name T824
Test name
Test status
Simulation time 24829745417 ps
CPU time 11.08 seconds
Started Mar 31 03:18:20 PM PDT 24
Finished Mar 31 03:18:31 PM PDT 24
Peak memory 200512 kb
Host smart-65ad67d6-1f52-42fe-a811-235ae8c23963
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716653934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3716653934
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1252245643
Short name T881
Test name
Test status
Simulation time 108434454282 ps
CPU time 150.35 seconds
Started Mar 31 03:18:30 PM PDT 24
Finished Mar 31 03:21:02 PM PDT 24
Peak memory 200492 kb
Host smart-fbcb40aa-dbe7-4045-b7c2-f8be3277a9d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252245643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1252245643
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1624987212
Short name T407
Test name
Test status
Simulation time 7929374945 ps
CPU time 18.23 seconds
Started Mar 31 03:18:29 PM PDT 24
Finished Mar 31 03:18:48 PM PDT 24
Peak memory 200140 kb
Host smart-24471cc4-8126-4d81-993f-7283947807d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624987212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1624987212
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1218761948
Short name T634
Test name
Test status
Simulation time 107181791886 ps
CPU time 210.93 seconds
Started Mar 31 03:18:22 PM PDT 24
Finished Mar 31 03:21:53 PM PDT 24
Peak memory 200184 kb
Host smart-58af64b0-3384-4687-a267-3b983ed14956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218761948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1218761948
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1133248357
Short name T1084
Test name
Test status
Simulation time 12065960962 ps
CPU time 136.59 seconds
Started Mar 31 03:18:31 PM PDT 24
Finished Mar 31 03:20:48 PM PDT 24
Peak memory 200500 kb
Host smart-263b261c-5265-465c-aa06-f80e5557925c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1133248357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1133248357
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1732053847
Short name T351
Test name
Test status
Simulation time 3823898146 ps
CPU time 4.36 seconds
Started Mar 31 03:18:17 PM PDT 24
Finished Mar 31 03:18:21 PM PDT 24
Peak memory 198588 kb
Host smart-1196d5c3-3c05-4588-bf2d-394fdfbcf441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732053847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1732053847
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.640462834
Short name T633
Test name
Test status
Simulation time 26446798255 ps
CPU time 22.77 seconds
Started Mar 31 03:18:23 PM PDT 24
Finished Mar 31 03:18:46 PM PDT 24
Peak memory 200504 kb
Host smart-13f8a453-eee3-4d0d-bedd-79d11123f7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640462834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.640462834
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3697082997
Short name T1053
Test name
Test status
Simulation time 3622190246 ps
CPU time 5.69 seconds
Started Mar 31 03:18:23 PM PDT 24
Finished Mar 31 03:18:29 PM PDT 24
Peak memory 196448 kb
Host smart-989ef063-9183-459f-9643-f6ecc240548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697082997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3697082997
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.4023324275
Short name T37
Test name
Test status
Simulation time 677618398 ps
CPU time 1.55 seconds
Started Mar 31 03:18:17 PM PDT 24
Finished Mar 31 03:18:19 PM PDT 24
Peak memory 199152 kb
Host smart-2e57beba-fcb0-450b-81e4-ecde91d9a087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023324275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4023324275
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1712896921
Short name T465
Test name
Test status
Simulation time 113819467550 ps
CPU time 283.72 seconds
Started Mar 31 03:18:28 PM PDT 24
Finished Mar 31 03:23:12 PM PDT 24
Peak memory 216916 kb
Host smart-757ed844-1ca7-46e0-99d7-b819ff575963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712896921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1712896921
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.376438737
Short name T277
Test name
Test status
Simulation time 8507240351 ps
CPU time 6.58 seconds
Started Mar 31 03:18:29 PM PDT 24
Finished Mar 31 03:18:36 PM PDT 24
Peak memory 200492 kb
Host smart-cc3e62a3-434f-4481-86fd-299fb23b8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376438737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.376438737
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.432008638
Short name T759
Test name
Test status
Simulation time 55783623631 ps
CPU time 53.33 seconds
Started Mar 31 03:18:17 PM PDT 24
Finished Mar 31 03:19:10 PM PDT 24
Peak memory 200480 kb
Host smart-bd29614d-7230-45ce-8d78-e9d0da35eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432008638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.432008638
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1134256935
Short name T553
Test name
Test status
Simulation time 53969920890 ps
CPU time 220.5 seconds
Started Mar 31 03:26:35 PM PDT 24
Finished Mar 31 03:30:15 PM PDT 24
Peak memory 200480 kb
Host smart-42d95360-1ca0-4d9b-a4a7-4df6d8d3749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134256935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1134256935
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2945603354
Short name T1064
Test name
Test status
Simulation time 58752954326 ps
CPU time 27.27 seconds
Started Mar 31 03:26:34 PM PDT 24
Finished Mar 31 03:27:02 PM PDT 24
Peak memory 200436 kb
Host smart-264fdd14-bf2f-489a-9737-76dd28aa0a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945603354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2945603354
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1488599217
Short name T1041
Test name
Test status
Simulation time 152600684588 ps
CPU time 167.24 seconds
Started Mar 31 03:26:34 PM PDT 24
Finished Mar 31 03:29:21 PM PDT 24
Peak memory 200504 kb
Host smart-95f64db5-c68b-427a-bbb6-fbab626c691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488599217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1488599217
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.318167220
Short name T1110
Test name
Test status
Simulation time 43414952488 ps
CPU time 12.74 seconds
Started Mar 31 03:26:35 PM PDT 24
Finished Mar 31 03:26:47 PM PDT 24
Peak memory 200448 kb
Host smart-debe39ce-324d-47f0-a220-1017f85e3cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318167220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.318167220
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2347382118
Short name T996
Test name
Test status
Simulation time 189615969433 ps
CPU time 72.64 seconds
Started Mar 31 03:26:33 PM PDT 24
Finished Mar 31 03:27:46 PM PDT 24
Peak memory 200552 kb
Host smart-85776671-966d-4768-a651-1315526664ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347382118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2347382118
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3460324870
Short name T224
Test name
Test status
Simulation time 168145556377 ps
CPU time 56.23 seconds
Started Mar 31 03:26:34 PM PDT 24
Finished Mar 31 03:27:30 PM PDT 24
Peak memory 200464 kb
Host smart-57ddcbe3-a3c3-4cbd-b0e3-999617687400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460324870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3460324870
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1706139424
Short name T793
Test name
Test status
Simulation time 154739376320 ps
CPU time 66.66 seconds
Started Mar 31 03:26:33 PM PDT 24
Finished Mar 31 03:27:40 PM PDT 24
Peak memory 200416 kb
Host smart-b141d638-ddd4-406e-8c40-e855a1e9c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706139424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1706139424
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3097360517
Short name T691
Test name
Test status
Simulation time 29718584741 ps
CPU time 9.86 seconds
Started Mar 31 03:26:35 PM PDT 24
Finished Mar 31 03:26:45 PM PDT 24
Peak memory 200512 kb
Host smart-4474a40d-ad68-4729-af96-442f30e2fa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097360517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3097360517
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2951206609
Short name T1173
Test name
Test status
Simulation time 114251999919 ps
CPU time 177.95 seconds
Started Mar 31 03:26:33 PM PDT 24
Finished Mar 31 03:29:31 PM PDT 24
Peak memory 200468 kb
Host smart-738f57e3-75f9-42f4-b081-10e8d8727c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951206609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2951206609
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.513644667
Short name T187
Test name
Test status
Simulation time 99324996428 ps
CPU time 22.95 seconds
Started Mar 31 03:26:33 PM PDT 24
Finished Mar 31 03:26:57 PM PDT 24
Peak memory 200476 kb
Host smart-19ee5edf-d579-4f7f-9a9a-d4ec896fe058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513644667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.513644667
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4005553231
Short name T339
Test name
Test status
Simulation time 165894558 ps
CPU time 0.55 seconds
Started Mar 31 03:18:46 PM PDT 24
Finished Mar 31 03:18:47 PM PDT 24
Peak memory 195856 kb
Host smart-dd2c39d6-9b1d-425e-aa49-e280121aba4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005553231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4005553231
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.929863209
Short name T119
Test name
Test status
Simulation time 24789967867 ps
CPU time 29.72 seconds
Started Mar 31 03:18:33 PM PDT 24
Finished Mar 31 03:19:03 PM PDT 24
Peak memory 200600 kb
Host smart-4c24891b-ed19-455d-acd8-54de3be6a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929863209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.929863209
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3820280776
Short name T164
Test name
Test status
Simulation time 24533393348 ps
CPU time 19.83 seconds
Started Mar 31 03:18:34 PM PDT 24
Finished Mar 31 03:18:55 PM PDT 24
Peak memory 200328 kb
Host smart-e2580d62-a696-41e1-868b-b48f369c33ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820280776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3820280776
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.2047207183
Short name T990
Test name
Test status
Simulation time 3929204471 ps
CPU time 6.24 seconds
Started Mar 31 03:18:35 PM PDT 24
Finished Mar 31 03:18:41 PM PDT 24
Peak memory 196380 kb
Host smart-5560180d-6d62-44c1-88a9-b7df79ae4aa0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047207183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2047207183
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.4221598357
Short name T533
Test name
Test status
Simulation time 105265893135 ps
CPU time 664.57 seconds
Started Mar 31 03:18:40 PM PDT 24
Finished Mar 31 03:29:45 PM PDT 24
Peak memory 200524 kb
Host smart-f4313720-6c4e-492d-b741-506020c86d31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221598357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4221598357
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3879607939
Short name T1148
Test name
Test status
Simulation time 6375262992 ps
CPU time 9.23 seconds
Started Mar 31 03:18:39 PM PDT 24
Finished Mar 31 03:18:49 PM PDT 24
Peak memory 200352 kb
Host smart-ac0dc544-8ff4-4728-a8a8-dc939614aab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879607939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3879607939
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.507850269
Short name T274
Test name
Test status
Simulation time 109334987928 ps
CPU time 35.55 seconds
Started Mar 31 03:18:34 PM PDT 24
Finished Mar 31 03:19:09 PM PDT 24
Peak memory 200808 kb
Host smart-af4ef68a-b578-47d1-bdd3-17d1e4af56e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507850269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.507850269
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3359344185
Short name T899
Test name
Test status
Simulation time 22593929753 ps
CPU time 54.68 seconds
Started Mar 31 03:18:38 PM PDT 24
Finished Mar 31 03:19:33 PM PDT 24
Peak memory 200496 kb
Host smart-850f8872-3157-438f-9cd6-fd1fe8f8fedf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359344185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3359344185
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1000621605
Short name T1135
Test name
Test status
Simulation time 4703367133 ps
CPU time 19.71 seconds
Started Mar 31 03:18:34 PM PDT 24
Finished Mar 31 03:18:54 PM PDT 24
Peak memory 199368 kb
Host smart-8b0123b8-d428-46ef-ad9a-70e5d01ace99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000621605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1000621605
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3908420450
Short name T613
Test name
Test status
Simulation time 240409717858 ps
CPU time 137.61 seconds
Started Mar 31 03:18:36 PM PDT 24
Finished Mar 31 03:20:54 PM PDT 24
Peak memory 200532 kb
Host smart-a32ecc2a-c68f-4d0f-9418-4ee4f0f57784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908420450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3908420450
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1801109953
Short name T1170
Test name
Test status
Simulation time 2780997831 ps
CPU time 5.42 seconds
Started Mar 31 03:18:34 PM PDT 24
Finished Mar 31 03:18:40 PM PDT 24
Peak memory 196216 kb
Host smart-a199950c-517d-4cb6-acdf-96ddc598a711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801109953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1801109953
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1390992006
Short name T618
Test name
Test status
Simulation time 729838957 ps
CPU time 2.23 seconds
Started Mar 31 03:18:30 PM PDT 24
Finished Mar 31 03:18:34 PM PDT 24
Peak memory 199004 kb
Host smart-4fb9879b-ca90-46b9-a55d-bb662188e19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390992006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1390992006
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.4290686849
Short name T875
Test name
Test status
Simulation time 137553079517 ps
CPU time 481.25 seconds
Started Mar 31 03:18:50 PM PDT 24
Finished Mar 31 03:26:52 PM PDT 24
Peak memory 200504 kb
Host smart-f09e3780-97a9-46d7-b616-aff11a9988fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290686849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4290686849
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.435579559
Short name T153
Test name
Test status
Simulation time 83706235442 ps
CPU time 198.88 seconds
Started Mar 31 03:18:45 PM PDT 24
Finished Mar 31 03:22:04 PM PDT 24
Peak memory 216492 kb
Host smart-a46d9cc7-b3b6-49a8-9ab6-5bcbed9a3650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435579559 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.435579559
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3418434361
Short name T348
Test name
Test status
Simulation time 6731659099 ps
CPU time 16.52 seconds
Started Mar 31 03:18:35 PM PDT 24
Finished Mar 31 03:18:51 PM PDT 24
Peak memory 200440 kb
Host smart-0ccde554-0cf2-4bcf-9a50-cec894bc29a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418434361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3418434361
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1546392932
Short name T95
Test name
Test status
Simulation time 28370546445 ps
CPU time 12.75 seconds
Started Mar 31 03:18:27 PM PDT 24
Finished Mar 31 03:18:40 PM PDT 24
Peak memory 200236 kb
Host smart-fa17334e-b7d8-4131-b0aa-8be89f979c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546392932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1546392932
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1216904106
Short name T130
Test name
Test status
Simulation time 14160769236 ps
CPU time 21.95 seconds
Started Mar 31 03:26:40 PM PDT 24
Finished Mar 31 03:27:02 PM PDT 24
Peak memory 200432 kb
Host smart-3fff9b05-6ca2-4b27-957d-8ecb9fac7548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216904106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1216904106
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2624841176
Short name T650
Test name
Test status
Simulation time 26485012896 ps
CPU time 41.88 seconds
Started Mar 31 03:26:40 PM PDT 24
Finished Mar 31 03:27:22 PM PDT 24
Peak memory 200504 kb
Host smart-3295cbb5-8418-4fa6-852b-88ea33c29bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624841176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2624841176
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.955371754
Short name T770
Test name
Test status
Simulation time 252162649382 ps
CPU time 42.84 seconds
Started Mar 31 03:26:38 PM PDT 24
Finished Mar 31 03:27:21 PM PDT 24
Peak memory 200492 kb
Host smart-345e4c80-fe09-4309-bd05-09f95e90b3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955371754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.955371754
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2250651979
Short name T307
Test name
Test status
Simulation time 6343354108 ps
CPU time 10.38 seconds
Started Mar 31 03:26:39 PM PDT 24
Finished Mar 31 03:26:49 PM PDT 24
Peak memory 200380 kb
Host smart-92b3f626-42db-46cd-b125-08720c4c0be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250651979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2250651979
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2130238410
Short name T152
Test name
Test status
Simulation time 66568589969 ps
CPU time 28.91 seconds
Started Mar 31 03:26:40 PM PDT 24
Finished Mar 31 03:27:09 PM PDT 24
Peak memory 200504 kb
Host smart-dc4f69e8-3c16-4f3e-9552-8a46c6cbbabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130238410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2130238410
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2129715962
Short name T817
Test name
Test status
Simulation time 36304951060 ps
CPU time 59.76 seconds
Started Mar 31 03:26:39 PM PDT 24
Finished Mar 31 03:27:39 PM PDT 24
Peak memory 200492 kb
Host smart-1ed9c1c8-a42d-4c29-90c5-64c7fd677b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129715962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2129715962
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.204052354
Short name T1164
Test name
Test status
Simulation time 108427257834 ps
CPU time 47.86 seconds
Started Mar 31 03:26:45 PM PDT 24
Finished Mar 31 03:27:33 PM PDT 24
Peak memory 200520 kb
Host smart-c99826ac-9724-4b84-95f6-e5a97496fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204052354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.204052354
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3775977078
Short name T404
Test name
Test status
Simulation time 14124483 ps
CPU time 0.57 seconds
Started Mar 31 03:18:55 PM PDT 24
Finished Mar 31 03:18:55 PM PDT 24
Peak memory 195892 kb
Host smart-17b932d3-c3cc-4c4c-9f24-15ffd5631447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775977078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3775977078
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1230932661
Short name T846
Test name
Test status
Simulation time 17013042100 ps
CPU time 26.85 seconds
Started Mar 31 03:18:50 PM PDT 24
Finished Mar 31 03:19:17 PM PDT 24
Peak memory 200440 kb
Host smart-b1c94248-45a3-440e-bb64-2e7aff9d76a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230932661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1230932661
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3225612762
Short name T720
Test name
Test status
Simulation time 15883198930 ps
CPU time 25.69 seconds
Started Mar 31 03:18:47 PM PDT 24
Finished Mar 31 03:19:13 PM PDT 24
Peak memory 200268 kb
Host smart-3c6dd1cc-3f1a-4081-b2e3-eb8388d5fcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225612762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3225612762
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2001915155
Short name T1014
Test name
Test status
Simulation time 16354450102 ps
CPU time 28 seconds
Started Mar 31 03:18:45 PM PDT 24
Finished Mar 31 03:19:13 PM PDT 24
Peak memory 200400 kb
Host smart-48a2c0bd-601a-4872-a50d-45463601ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001915155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2001915155
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2330676736
Short name T636
Test name
Test status
Simulation time 8762506043 ps
CPU time 5.73 seconds
Started Mar 31 03:18:50 PM PDT 24
Finished Mar 31 03:18:56 PM PDT 24
Peak memory 197428 kb
Host smart-ff60bcc3-5982-4514-bcd0-17d54601ecdc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330676736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2330676736
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2071253692
Short name T1063
Test name
Test status
Simulation time 197553714643 ps
CPU time 485.49 seconds
Started Mar 31 03:18:51 PM PDT 24
Finished Mar 31 03:26:57 PM PDT 24
Peak memory 200432 kb
Host smart-52a0e832-15f1-4d8f-a748-866be182bdce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071253692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2071253692
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.374178954
Short name T1108
Test name
Test status
Simulation time 4993312046 ps
CPU time 9.08 seconds
Started Mar 31 03:18:51 PM PDT 24
Finished Mar 31 03:19:00 PM PDT 24
Peak memory 199252 kb
Host smart-0e321b98-4fb7-4c67-be8a-b65be9470475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374178954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.374178954
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.616233069
Short name T993
Test name
Test status
Simulation time 67397203382 ps
CPU time 28.57 seconds
Started Mar 31 03:18:47 PM PDT 24
Finished Mar 31 03:19:16 PM PDT 24
Peak memory 200760 kb
Host smart-754ddd45-e839-4933-9298-16825e000501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616233069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.616233069
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1310231664
Short name T685
Test name
Test status
Simulation time 5524090975 ps
CPU time 315.31 seconds
Started Mar 31 03:18:51 PM PDT 24
Finished Mar 31 03:24:06 PM PDT 24
Peak memory 200436 kb
Host smart-79672594-a68b-49a2-a0a8-bc25ddd142f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310231664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1310231664
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1859433914
Short name T677
Test name
Test status
Simulation time 1899025038 ps
CPU time 4.2 seconds
Started Mar 31 03:18:46 PM PDT 24
Finished Mar 31 03:18:51 PM PDT 24
Peak memory 198480 kb
Host smart-2fee1403-6466-4be9-8d8c-7c8c0eb59d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859433914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1859433914
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3717892331
Short name T453
Test name
Test status
Simulation time 57819400559 ps
CPU time 105.77 seconds
Started Mar 31 03:18:47 PM PDT 24
Finished Mar 31 03:20:32 PM PDT 24
Peak memory 200340 kb
Host smart-17cd34f3-f4d8-4411-9000-137f677a17ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717892331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3717892331
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3502229322
Short name T782
Test name
Test status
Simulation time 611725274 ps
CPU time 1.55 seconds
Started Mar 31 03:18:46 PM PDT 24
Finished Mar 31 03:18:48 PM PDT 24
Peak memory 195832 kb
Host smart-69b33ec5-e711-474b-ad12-ce8fd2abf623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502229322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3502229322
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3962476279
Short name T382
Test name
Test status
Simulation time 500278904 ps
CPU time 2.05 seconds
Started Mar 31 03:18:51 PM PDT 24
Finished Mar 31 03:18:53 PM PDT 24
Peak memory 199044 kb
Host smart-0c461397-4b75-4aaf-98e5-73e2cef6f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962476279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3962476279
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2859371514
Short name T530
Test name
Test status
Simulation time 57272097265 ps
CPU time 102.33 seconds
Started Mar 31 03:18:54 PM PDT 24
Finished Mar 31 03:20:37 PM PDT 24
Peak memory 200528 kb
Host smart-5d968a31-e550-4406-838b-357564660ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859371514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2859371514
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1833005993
Short name T138
Test name
Test status
Simulation time 229674751764 ps
CPU time 701.12 seconds
Started Mar 31 03:18:53 PM PDT 24
Finished Mar 31 03:30:34 PM PDT 24
Peak memory 216988 kb
Host smart-2e77bcba-c6a8-47cf-8333-a1993b394e43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833005993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1833005993
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2246245405
Short name T582
Test name
Test status
Simulation time 680150047 ps
CPU time 2.87 seconds
Started Mar 31 03:18:55 PM PDT 24
Finished Mar 31 03:18:57 PM PDT 24
Peak memory 199432 kb
Host smart-409818df-b5cb-408d-872f-e007556311e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246245405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2246245405
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3972362860
Short name T789
Test name
Test status
Simulation time 77016142891 ps
CPU time 32.98 seconds
Started Mar 31 03:18:50 PM PDT 24
Finished Mar 31 03:19:23 PM PDT 24
Peak memory 200448 kb
Host smart-4b138437-089c-4b67-94b8-e6effad32c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972362860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3972362860
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.762506614
Short name T284
Test name
Test status
Simulation time 28277843301 ps
CPU time 48.01 seconds
Started Mar 31 03:26:42 PM PDT 24
Finished Mar 31 03:27:30 PM PDT 24
Peak memory 200468 kb
Host smart-327da116-9b93-4adb-b34e-22806ca6a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762506614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.762506614
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3071841537
Short name T1077
Test name
Test status
Simulation time 97632615175 ps
CPU time 79.13 seconds
Started Mar 31 03:26:50 PM PDT 24
Finished Mar 31 03:28:10 PM PDT 24
Peak memory 200420 kb
Host smart-647a3203-0de9-43ce-8f8b-71875fe828a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071841537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3071841537
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.971105309
Short name T196
Test name
Test status
Simulation time 10556173818 ps
CPU time 9.63 seconds
Started Mar 31 03:26:50 PM PDT 24
Finished Mar 31 03:27:00 PM PDT 24
Peak memory 200476 kb
Host smart-e14c22a7-fc29-493f-b550-c92222d93f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971105309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.971105309
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.4039677873
Short name T75
Test name
Test status
Simulation time 80189128043 ps
CPU time 14.58 seconds
Started Mar 31 03:26:50 PM PDT 24
Finished Mar 31 03:27:05 PM PDT 24
Peak memory 200456 kb
Host smart-06532f81-3cea-4bc8-9402-54a9a9c9b477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039677873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.4039677873
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.971032476
Short name T145
Test name
Test status
Simulation time 70214547198 ps
CPU time 75.9 seconds
Started Mar 31 03:26:50 PM PDT 24
Finished Mar 31 03:28:06 PM PDT 24
Peak memory 200440 kb
Host smart-c6aaf301-8267-47b8-be01-70a6b9007971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971032476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.971032476
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2560967803
Short name T200
Test name
Test status
Simulation time 58736868597 ps
CPU time 28.52 seconds
Started Mar 31 03:26:49 PM PDT 24
Finished Mar 31 03:27:17 PM PDT 24
Peak memory 200452 kb
Host smart-791764c8-db61-419d-924b-ce74c891a2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560967803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2560967803
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.34668921
Short name T385
Test name
Test status
Simulation time 13571099662 ps
CPU time 17.06 seconds
Started Mar 31 03:26:50 PM PDT 24
Finished Mar 31 03:27:07 PM PDT 24
Peak memory 199612 kb
Host smart-56edb9a6-ac9d-4de4-a1d2-1236eb07278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34668921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.34668921
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2365787414
Short name T137
Test name
Test status
Simulation time 29054991892 ps
CPU time 15.16 seconds
Started Mar 31 03:26:49 PM PDT 24
Finished Mar 31 03:27:04 PM PDT 24
Peak memory 200400 kb
Host smart-78a883e1-a516-47ba-82ac-d3880ff7e76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365787414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2365787414
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3269593000
Short name T647
Test name
Test status
Simulation time 82807524059 ps
CPU time 139.19 seconds
Started Mar 31 03:26:58 PM PDT 24
Finished Mar 31 03:29:17 PM PDT 24
Peak memory 200488 kb
Host smart-98e95cb0-64e9-4974-9629-f7ee09d809c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269593000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3269593000
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1384705684
Short name T346
Test name
Test status
Simulation time 10595529 ps
CPU time 0.54 seconds
Started Mar 31 03:19:12 PM PDT 24
Finished Mar 31 03:19:13 PM PDT 24
Peak memory 194864 kb
Host smart-89fde6ec-9a1f-4663-865c-85944633db32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384705684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1384705684
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1280463123
Short name T1119
Test name
Test status
Simulation time 130312521146 ps
CPU time 223.44 seconds
Started Mar 31 03:19:02 PM PDT 24
Finished Mar 31 03:22:46 PM PDT 24
Peak memory 200488 kb
Host smart-8d4e05f7-952c-4562-9039-285662183e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280463123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1280463123
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2716299592
Short name T779
Test name
Test status
Simulation time 50162164110 ps
CPU time 74.52 seconds
Started Mar 31 03:19:00 PM PDT 24
Finished Mar 31 03:20:15 PM PDT 24
Peak memory 200476 kb
Host smart-17b7002b-268e-4816-8e43-22ff3a8ec5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716299592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2716299592
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.2647015597
Short name T447
Test name
Test status
Simulation time 21880352987 ps
CPU time 9.99 seconds
Started Mar 31 03:18:59 PM PDT 24
Finished Mar 31 03:19:09 PM PDT 24
Peak memory 200188 kb
Host smart-d083a825-32da-4aef-a62b-5b04224fda00
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647015597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2647015597
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_loopback.3012803525
Short name T626
Test name
Test status
Simulation time 2841213801 ps
CPU time 5.33 seconds
Started Mar 31 03:19:05 PM PDT 24
Finished Mar 31 03:19:11 PM PDT 24
Peak memory 196660 kb
Host smart-18334e35-c6ea-442c-ad68-5b712561465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012803525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3012803525
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2384233712
Short name T934
Test name
Test status
Simulation time 123572030753 ps
CPU time 200.45 seconds
Started Mar 31 03:18:58 PM PDT 24
Finished Mar 31 03:22:18 PM PDT 24
Peak memory 200748 kb
Host smart-4aa8f0cd-6afc-4688-8a60-9cfeb42e00fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384233712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2384233712
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1377541687
Short name T1028
Test name
Test status
Simulation time 7038245924 ps
CPU time 300.68 seconds
Started Mar 31 03:19:04 PM PDT 24
Finished Mar 31 03:24:05 PM PDT 24
Peak memory 200396 kb
Host smart-79f7c880-4eb0-48f2-8eb5-175b731a3d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377541687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1377541687
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3159901862
Short name T938
Test name
Test status
Simulation time 5339330257 ps
CPU time 21.85 seconds
Started Mar 31 03:19:02 PM PDT 24
Finished Mar 31 03:19:24 PM PDT 24
Peak memory 199312 kb
Host smart-491915f7-e8a6-4ae4-a214-71f418cedd8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159901862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3159901862
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.784438428
Short name T708
Test name
Test status
Simulation time 31757832889 ps
CPU time 64.41 seconds
Started Mar 31 03:19:03 PM PDT 24
Finished Mar 31 03:20:08 PM PDT 24
Peak memory 200440 kb
Host smart-888b6622-7fea-4154-8bb2-754f7a33e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784438428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.784438428
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.455749442
Short name T267
Test name
Test status
Simulation time 5765236572 ps
CPU time 2.87 seconds
Started Mar 31 03:19:03 PM PDT 24
Finished Mar 31 03:19:07 PM PDT 24
Peak memory 196492 kb
Host smart-d8c55647-bbac-406c-be39-ae15f11c154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455749442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.455749442
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.745963103
Short name T593
Test name
Test status
Simulation time 281553736 ps
CPU time 2.58 seconds
Started Mar 31 03:18:53 PM PDT 24
Finished Mar 31 03:18:55 PM PDT 24
Peak memory 198716 kb
Host smart-2df8b1ca-e7cf-4ac2-ab6e-9e357bed41ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745963103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.745963103
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3912614827
Short name T745
Test name
Test status
Simulation time 251137479338 ps
CPU time 692.41 seconds
Started Mar 31 03:19:03 PM PDT 24
Finished Mar 31 03:30:37 PM PDT 24
Peak memory 216748 kb
Host smart-b91b64c8-9249-440c-85c8-b651c03bf8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912614827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3912614827
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2388983416
Short name T282
Test name
Test status
Simulation time 1783858074 ps
CPU time 1.8 seconds
Started Mar 31 03:19:04 PM PDT 24
Finished Mar 31 03:19:06 PM PDT 24
Peak memory 199468 kb
Host smart-aeaae61d-0a2c-460e-8058-0fd6142cfdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388983416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2388983416
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3133886332
Short name T957
Test name
Test status
Simulation time 197229845475 ps
CPU time 55.18 seconds
Started Mar 31 03:18:52 PM PDT 24
Finished Mar 31 03:19:47 PM PDT 24
Peak memory 200472 kb
Host smart-2c419c0f-271b-4020-a1cc-cf7092bee5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133886332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3133886332
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1375126302
Short name T223
Test name
Test status
Simulation time 95909017037 ps
CPU time 45.45 seconds
Started Mar 31 03:26:54 PM PDT 24
Finished Mar 31 03:27:40 PM PDT 24
Peak memory 200496 kb
Host smart-35e0a63e-1f19-4aac-a0c5-c596bd211b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375126302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1375126302
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2703151302
Short name T208
Test name
Test status
Simulation time 31577574109 ps
CPU time 78.95 seconds
Started Mar 31 03:26:56 PM PDT 24
Finished Mar 31 03:28:15 PM PDT 24
Peak memory 200448 kb
Host smart-5a975ab9-4d0f-4394-8cae-6e69bb7c67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703151302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2703151302
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3601200466
Short name T424
Test name
Test status
Simulation time 162299810543 ps
CPU time 137.69 seconds
Started Mar 31 03:26:55 PM PDT 24
Finished Mar 31 03:29:13 PM PDT 24
Peak memory 200508 kb
Host smart-192b9504-f360-4bb0-b617-a7716300ffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601200466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3601200466
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2718896171
Short name T1057
Test name
Test status
Simulation time 166734254919 ps
CPU time 74.43 seconds
Started Mar 31 03:26:55 PM PDT 24
Finished Mar 31 03:28:10 PM PDT 24
Peak memory 200396 kb
Host smart-7f2c7e87-fedb-49aa-95df-a680705c5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718896171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2718896171
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.4133315144
Short name T474
Test name
Test status
Simulation time 120656879179 ps
CPU time 34.42 seconds
Started Mar 31 03:26:58 PM PDT 24
Finished Mar 31 03:27:32 PM PDT 24
Peak memory 200532 kb
Host smart-fb461b3c-769c-4350-9046-410b0698c63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133315144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4133315144
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2025310086
Short name T766
Test name
Test status
Simulation time 48323359868 ps
CPU time 46.68 seconds
Started Mar 31 03:26:55 PM PDT 24
Finished Mar 31 03:27:41 PM PDT 24
Peak memory 200500 kb
Host smart-f60a0451-85c2-4be0-8670-d75f3200cc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025310086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2025310086
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.640645781
Short name T1122
Test name
Test status
Simulation time 44276081489 ps
CPU time 59.18 seconds
Started Mar 31 03:26:55 PM PDT 24
Finished Mar 31 03:27:55 PM PDT 24
Peak memory 200436 kb
Host smart-e422ce2f-5e01-4d44-9ca2-c0a9c4ee6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640645781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.640645781
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1264935866
Short name T859
Test name
Test status
Simulation time 24679010628 ps
CPU time 20.4 seconds
Started Mar 31 03:27:01 PM PDT 24
Finished Mar 31 03:27:21 PM PDT 24
Peak memory 200404 kb
Host smart-3be28371-71a0-4395-aee0-4061e728badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264935866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1264935866
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4081457553
Short name T198
Test name
Test status
Simulation time 48049334347 ps
CPU time 89.22 seconds
Started Mar 31 03:27:02 PM PDT 24
Finished Mar 31 03:28:32 PM PDT 24
Peak memory 200516 kb
Host smart-d2eac7d0-35eb-4741-bbbc-a958316a83d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081457553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4081457553
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3974117341
Short name T895
Test name
Test status
Simulation time 54079350925 ps
CPU time 90.79 seconds
Started Mar 31 03:27:01 PM PDT 24
Finished Mar 31 03:28:32 PM PDT 24
Peak memory 200368 kb
Host smart-552f90a4-ccc1-4b6e-95ef-16da71c05fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974117341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3974117341
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1800248976
Short name T492
Test name
Test status
Simulation time 70512443 ps
CPU time 0.52 seconds
Started Mar 31 03:19:16 PM PDT 24
Finished Mar 31 03:19:17 PM PDT 24
Peak memory 194900 kb
Host smart-709a8dc2-e970-4966-af98-b799967f1011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800248976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1800248976
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1657103574
Short name T872
Test name
Test status
Simulation time 99444645831 ps
CPU time 37.57 seconds
Started Mar 31 03:19:10 PM PDT 24
Finished Mar 31 03:19:48 PM PDT 24
Peak memory 200456 kb
Host smart-bdfc5875-fafc-4ed8-bca8-16fb7df4de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657103574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1657103574
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.153247981
Short name T858
Test name
Test status
Simulation time 43091334056 ps
CPU time 67.79 seconds
Started Mar 31 03:19:09 PM PDT 24
Finished Mar 31 03:20:17 PM PDT 24
Peak memory 200528 kb
Host smart-b4bc3749-5a15-4dd7-b8bd-726592a510ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153247981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.153247981
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1082880672
Short name T1145
Test name
Test status
Simulation time 141261240730 ps
CPU time 321.14 seconds
Started Mar 31 03:19:10 PM PDT 24
Finished Mar 31 03:24:31 PM PDT 24
Peak memory 200420 kb
Host smart-96cb0b94-7a07-4a73-bcd7-49c9b9c34c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082880672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1082880672
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.650701629
Short name T866
Test name
Test status
Simulation time 54592434571 ps
CPU time 78.43 seconds
Started Mar 31 03:19:13 PM PDT 24
Finished Mar 31 03:20:31 PM PDT 24
Peak memory 200504 kb
Host smart-44f0fad9-e318-4a14-8990-20d1578fec4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650701629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.650701629
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2348009913
Short name T319
Test name
Test status
Simulation time 103477311429 ps
CPU time 96.5 seconds
Started Mar 31 03:19:16 PM PDT 24
Finished Mar 31 03:20:52 PM PDT 24
Peak memory 200504 kb
Host smart-18151511-5b98-4251-8df4-576a76a217f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348009913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2348009913
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2163073520
Short name T1083
Test name
Test status
Simulation time 8974265573 ps
CPU time 6.29 seconds
Started Mar 31 03:19:15 PM PDT 24
Finished Mar 31 03:19:21 PM PDT 24
Peak memory 200372 kb
Host smart-ac4c18f3-b416-42ca-baef-7a3c2cb85136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163073520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2163073520
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2930410451
Short name T36
Test name
Test status
Simulation time 31811468034 ps
CPU time 50.9 seconds
Started Mar 31 03:19:10 PM PDT 24
Finished Mar 31 03:20:01 PM PDT 24
Peak memory 200792 kb
Host smart-068e4376-bfbd-44ef-9f49-f90b575bc502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930410451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2930410451
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1688073245
Short name T1139
Test name
Test status
Simulation time 11606376811 ps
CPU time 52.67 seconds
Started Mar 31 03:19:19 PM PDT 24
Finished Mar 31 03:20:11 PM PDT 24
Peak memory 200488 kb
Host smart-42e16a26-d805-4432-8f1c-6891376ce1fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688073245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1688073245
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1757929855
Short name T429
Test name
Test status
Simulation time 2130556369 ps
CPU time 3.67 seconds
Started Mar 31 03:19:13 PM PDT 24
Finished Mar 31 03:19:17 PM PDT 24
Peak memory 198552 kb
Host smart-fb33207d-4ec2-423a-b61c-18a3195d9358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757929855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1757929855
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3987987642
Short name T795
Test name
Test status
Simulation time 59201926353 ps
CPU time 48.43 seconds
Started Mar 31 03:19:19 PM PDT 24
Finished Mar 31 03:20:07 PM PDT 24
Peak memory 200504 kb
Host smart-c2d84a3b-e4f5-4560-86cb-efab16f3a7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987987642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3987987642
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1385442988
Short name T1066
Test name
Test status
Simulation time 2733052114 ps
CPU time 1.06 seconds
Started Mar 31 03:19:17 PM PDT 24
Finished Mar 31 03:19:18 PM PDT 24
Peak memory 196220 kb
Host smart-02a93a6d-00fc-42e0-ac7f-dc0eb62e3d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385442988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1385442988
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.291255276
Short name T498
Test name
Test status
Simulation time 683073394 ps
CPU time 1.59 seconds
Started Mar 31 03:19:10 PM PDT 24
Finished Mar 31 03:19:12 PM PDT 24
Peak memory 198764 kb
Host smart-cbb08ba2-5369-4b98-bc99-cf9bb7b02240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291255276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.291255276
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1623062815
Short name T657
Test name
Test status
Simulation time 192246835070 ps
CPU time 478.33 seconds
Started Mar 31 03:19:17 PM PDT 24
Finished Mar 31 03:27:15 PM PDT 24
Peak memory 200512 kb
Host smart-930d9de0-5f4a-40eb-bac3-3bd8db1c7d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623062815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1623062815
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3645670029
Short name T1158
Test name
Test status
Simulation time 1096920772 ps
CPU time 1.48 seconds
Started Mar 31 03:19:14 PM PDT 24
Finished Mar 31 03:19:16 PM PDT 24
Peak memory 198848 kb
Host smart-39f5811a-a31b-478d-8030-99c063a7fcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645670029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3645670029
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1311991942
Short name T1156
Test name
Test status
Simulation time 118867478811 ps
CPU time 12.68 seconds
Started Mar 31 03:19:09 PM PDT 24
Finished Mar 31 03:19:22 PM PDT 24
Peak memory 200432 kb
Host smart-f2b13e65-c234-4617-962d-2dceea624e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311991942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1311991942
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3716321352
Short name T1061
Test name
Test status
Simulation time 200890633747 ps
CPU time 83.81 seconds
Started Mar 31 03:27:00 PM PDT 24
Finished Mar 31 03:28:24 PM PDT 24
Peak memory 200400 kb
Host smart-0608b455-8147-4a2b-83a9-a06474c7ffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716321352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3716321352
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1451524186
Short name T981
Test name
Test status
Simulation time 24015465794 ps
CPU time 12.85 seconds
Started Mar 31 03:27:01 PM PDT 24
Finished Mar 31 03:27:14 PM PDT 24
Peak memory 200532 kb
Host smart-a8d429a6-9133-4c8d-87bb-e7fe711a7736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451524186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1451524186
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2455406014
Short name T781
Test name
Test status
Simulation time 44875413417 ps
CPU time 74.52 seconds
Started Mar 31 03:27:00 PM PDT 24
Finished Mar 31 03:28:15 PM PDT 24
Peak memory 200500 kb
Host smart-b5cd5acd-061d-418e-8d24-7300809bcb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455406014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2455406014
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.901842855
Short name T123
Test name
Test status
Simulation time 45449787799 ps
CPU time 17.59 seconds
Started Mar 31 03:27:07 PM PDT 24
Finished Mar 31 03:27:24 PM PDT 24
Peak memory 200440 kb
Host smart-8df7adc0-521d-4384-a48e-22a07166e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901842855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.901842855
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.188223120
Short name T255
Test name
Test status
Simulation time 213487526192 ps
CPU time 101.09 seconds
Started Mar 31 03:27:06 PM PDT 24
Finished Mar 31 03:28:48 PM PDT 24
Peak memory 200460 kb
Host smart-cd1eea75-6361-4118-9b1e-1c1bab729ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188223120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.188223120
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.678947410
Short name T332
Test name
Test status
Simulation time 42502857791 ps
CPU time 14.82 seconds
Started Mar 31 03:27:06 PM PDT 24
Finished Mar 31 03:27:21 PM PDT 24
Peak memory 200428 kb
Host smart-57a3f133-3295-4e79-85af-7a35a98a4c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678947410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.678947410
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2880216824
Short name T391
Test name
Test status
Simulation time 106283237512 ps
CPU time 116.75 seconds
Started Mar 31 03:27:06 PM PDT 24
Finished Mar 31 03:29:03 PM PDT 24
Peak memory 200492 kb
Host smart-de38bc13-045b-47ed-915b-7a4846c1f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880216824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2880216824
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2238359397
Short name T522
Test name
Test status
Simulation time 21488614254 ps
CPU time 50.89 seconds
Started Mar 31 03:27:06 PM PDT 24
Finished Mar 31 03:27:57 PM PDT 24
Peak memory 200448 kb
Host smart-573a9a37-e2f2-4708-9d19-d1e5ddcc4d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238359397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2238359397
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3585970006
Short name T1157
Test name
Test status
Simulation time 75545033609 ps
CPU time 60.81 seconds
Started Mar 31 03:27:06 PM PDT 24
Finished Mar 31 03:28:07 PM PDT 24
Peak memory 200536 kb
Host smart-baf86bf6-de03-48c3-a50e-5aba1d08cf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585970006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3585970006
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4288620318
Short name T1043
Test name
Test status
Simulation time 35403015591 ps
CPU time 15.13 seconds
Started Mar 31 03:27:08 PM PDT 24
Finished Mar 31 03:27:23 PM PDT 24
Peak memory 200516 kb
Host smart-f88865a5-1721-457e-aaef-2f4188883655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288620318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4288620318
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2918045515
Short name T532
Test name
Test status
Simulation time 32099042 ps
CPU time 0.55 seconds
Started Mar 31 03:15:06 PM PDT 24
Finished Mar 31 03:15:07 PM PDT 24
Peak memory 195896 kb
Host smart-1143b56f-e608-4a49-a839-1b1169bc6774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918045515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2918045515
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2486292269
Short name T783
Test name
Test status
Simulation time 118202470882 ps
CPU time 120.53 seconds
Started Mar 31 03:14:46 PM PDT 24
Finished Mar 31 03:16:47 PM PDT 24
Peak memory 200456 kb
Host smart-79286704-c166-4a5a-be56-369268dfc951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486292269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2486292269
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1700736621
Short name T811
Test name
Test status
Simulation time 45573137448 ps
CPU time 81.94 seconds
Started Mar 31 03:14:49 PM PDT 24
Finished Mar 31 03:16:11 PM PDT 24
Peak memory 200444 kb
Host smart-d6f6e175-7df2-4911-8576-96fcce3247d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700736621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1700736621
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.463687846
Short name T1013
Test name
Test status
Simulation time 34895451375 ps
CPU time 61.47 seconds
Started Mar 31 03:14:57 PM PDT 24
Finished Mar 31 03:15:58 PM PDT 24
Peak memory 200440 kb
Host smart-09c2e697-8d24-4941-a67b-6ae214019050
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463687846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.463687846
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3307287550
Short name T265
Test name
Test status
Simulation time 122336444685 ps
CPU time 591.31 seconds
Started Mar 31 03:15:01 PM PDT 24
Finished Mar 31 03:24:53 PM PDT 24
Peak memory 200464 kb
Host smart-7d3c9838-5227-4c22-b187-a25e5e319e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307287550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3307287550
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2912976525
Short name T455
Test name
Test status
Simulation time 6318058652 ps
CPU time 11.89 seconds
Started Mar 31 03:15:01 PM PDT 24
Finished Mar 31 03:15:13 PM PDT 24
Peak memory 196292 kb
Host smart-61dcd902-711b-455f-ae9c-54958011451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912976525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2912976525
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3198162890
Short name T586
Test name
Test status
Simulation time 122883018412 ps
CPU time 140.07 seconds
Started Mar 31 03:14:54 PM PDT 24
Finished Mar 31 03:17:14 PM PDT 24
Peak memory 200140 kb
Host smart-82454a68-22ec-4fb8-a2a1-0582335c1b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198162890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3198162890
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3307749531
Short name T728
Test name
Test status
Simulation time 11050705946 ps
CPU time 505.36 seconds
Started Mar 31 03:14:59 PM PDT 24
Finished Mar 31 03:23:24 PM PDT 24
Peak memory 200440 kb
Host smart-4ce295cd-75f2-46a2-ac63-72eaa8069ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307749531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3307749531
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1762734025
Short name T372
Test name
Test status
Simulation time 3045883687 ps
CPU time 16.21 seconds
Started Mar 31 03:14:48 PM PDT 24
Finished Mar 31 03:15:04 PM PDT 24
Peak memory 198836 kb
Host smart-246bf80b-2ba3-4b99-8b22-f5b3bfc254fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762734025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1762734025
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1476064000
Short name T902
Test name
Test status
Simulation time 50352947167 ps
CPU time 83.56 seconds
Started Mar 31 03:14:55 PM PDT 24
Finished Mar 31 03:16:19 PM PDT 24
Peak memory 200476 kb
Host smart-d153f07a-a930-49b8-831d-bb9c85b3681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476064000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1476064000
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1075162340
Short name T427
Test name
Test status
Simulation time 47163430673 ps
CPU time 75.7 seconds
Started Mar 31 03:14:55 PM PDT 24
Finished Mar 31 03:16:11 PM PDT 24
Peak memory 196200 kb
Host smart-76daaf2a-bd64-472a-8186-e89f629ea336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075162340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1075162340
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1640779448
Short name T72
Test name
Test status
Simulation time 153664606 ps
CPU time 0.85 seconds
Started Mar 31 03:15:06 PM PDT 24
Finished Mar 31 03:15:07 PM PDT 24
Peak memory 218960 kb
Host smart-d2b049c9-0701-4d1b-94f8-aab9a0f80911
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640779448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1640779448
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1749502844
Short name T959
Test name
Test status
Simulation time 893688472 ps
CPU time 2.88 seconds
Started Mar 31 03:14:44 PM PDT 24
Finished Mar 31 03:14:47 PM PDT 24
Peak memory 200216 kb
Host smart-c1888ab9-80ac-4539-9491-16d907af2a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749502844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1749502844
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3308021514
Short name T1100
Test name
Test status
Simulation time 261943440102 ps
CPU time 867.2 seconds
Started Mar 31 03:14:59 PM PDT 24
Finished Mar 31 03:29:26 PM PDT 24
Peak memory 214680 kb
Host smart-c1dca288-8905-4f04-a616-4c1a84063164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308021514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3308021514
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.77497355
Short name T364
Test name
Test status
Simulation time 1506944091 ps
CPU time 1.82 seconds
Started Mar 31 03:14:58 PM PDT 24
Finished Mar 31 03:15:00 PM PDT 24
Peak memory 199000 kb
Host smart-9af7f783-7f53-43fc-8976-abc765dd92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77497355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.77497355
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.912734267
Short name T1162
Test name
Test status
Simulation time 28606637799 ps
CPU time 23.35 seconds
Started Mar 31 03:14:47 PM PDT 24
Finished Mar 31 03:15:11 PM PDT 24
Peak memory 200440 kb
Host smart-64b780a8-dd9b-4cd2-98bd-4adbc0b483d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912734267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.912734267
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2055898976
Short name T578
Test name
Test status
Simulation time 66102039875 ps
CPU time 107.71 seconds
Started Mar 31 03:19:18 PM PDT 24
Finished Mar 31 03:21:06 PM PDT 24
Peak memory 200544 kb
Host smart-46d0619e-5503-4c1d-81cc-14764bbee8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055898976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2055898976
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.395898567
Short name T399
Test name
Test status
Simulation time 128481385791 ps
CPU time 55.14 seconds
Started Mar 31 03:19:23 PM PDT 24
Finished Mar 31 03:20:18 PM PDT 24
Peak memory 200500 kb
Host smart-8864de08-b178-46fc-b465-ef70629b3434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395898567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.395898567
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1103535425
Short name T567
Test name
Test status
Simulation time 117804426034 ps
CPU time 41.3 seconds
Started Mar 31 03:19:25 PM PDT 24
Finished Mar 31 03:20:06 PM PDT 24
Peak memory 200508 kb
Host smart-0559142b-9d30-4a13-a570-19a367f3f624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103535425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1103535425
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.905104537
Short name T513
Test name
Test status
Simulation time 64895600576 ps
CPU time 98.77 seconds
Started Mar 31 03:19:25 PM PDT 24
Finished Mar 31 03:21:04 PM PDT 24
Peak memory 200404 kb
Host smart-9e0c69df-188a-49e0-9562-8915a8d14609
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905104537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.905104537
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2524399931
Short name T1176
Test name
Test status
Simulation time 81293517273 ps
CPU time 291.37 seconds
Started Mar 31 03:19:26 PM PDT 24
Finished Mar 31 03:24:18 PM PDT 24
Peak memory 200504 kb
Host smart-abb51446-65d2-47e5-9261-a5c24f5d8c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524399931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2524399931
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1942119158
Short name T991
Test name
Test status
Simulation time 11261059227 ps
CPU time 20.78 seconds
Started Mar 31 03:19:25 PM PDT 24
Finished Mar 31 03:19:46 PM PDT 24
Peak memory 200484 kb
Host smart-fd099a7f-0819-462e-9781-f7c8143d8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942119158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1942119158
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3991329256
Short name T300
Test name
Test status
Simulation time 28548818541 ps
CPU time 50.61 seconds
Started Mar 31 03:19:25 PM PDT 24
Finished Mar 31 03:20:16 PM PDT 24
Peak memory 199732 kb
Host smart-83cf41bb-fe0b-4067-8341-77b15f1ec738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991329256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3991329256
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.143459596
Short name T1116
Test name
Test status
Simulation time 5945511868 ps
CPU time 354.77 seconds
Started Mar 31 03:19:26 PM PDT 24
Finished Mar 31 03:25:21 PM PDT 24
Peak memory 200544 kb
Host smart-4f4d6333-45f2-4505-89b1-ff166605d0cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143459596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.143459596
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.4022461356
Short name T1129
Test name
Test status
Simulation time 4973642550 ps
CPU time 12.19 seconds
Started Mar 31 03:19:26 PM PDT 24
Finished Mar 31 03:19:39 PM PDT 24
Peak memory 199664 kb
Host smart-ce294b4b-3b5b-44fc-bc8c-86fb19636e87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022461356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.4022461356
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.940773253
Short name T76
Test name
Test status
Simulation time 134576599594 ps
CPU time 257.67 seconds
Started Mar 31 03:19:24 PM PDT 24
Finished Mar 31 03:23:42 PM PDT 24
Peak memory 200508 kb
Host smart-35fe4cb6-15b7-4eec-888f-ee7c8ade0f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940773253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.940773253
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2138123871
Short name T460
Test name
Test status
Simulation time 41617718734 ps
CPU time 28.99 seconds
Started Mar 31 03:19:25 PM PDT 24
Finished Mar 31 03:19:54 PM PDT 24
Peak memory 196224 kb
Host smart-5447507f-8529-46ce-bc35-769f89d230af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138123871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2138123871
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1744075027
Short name T483
Test name
Test status
Simulation time 267522394 ps
CPU time 2 seconds
Started Mar 31 03:19:19 PM PDT 24
Finished Mar 31 03:19:21 PM PDT 24
Peak memory 198696 kb
Host smart-7c224cbc-0ce6-47a6-a489-0fc2ff27e4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744075027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1744075027
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1960755596
Short name T477
Test name
Test status
Simulation time 622564823136 ps
CPU time 149.21 seconds
Started Mar 31 03:19:31 PM PDT 24
Finished Mar 31 03:22:00 PM PDT 24
Peak memory 200512 kb
Host smart-a1405d36-e196-46dd-b468-6cb589942b0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960755596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1960755596
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2181841777
Short name T1080
Test name
Test status
Simulation time 61855871822 ps
CPU time 915.83 seconds
Started Mar 31 03:19:23 PM PDT 24
Finished Mar 31 03:34:39 PM PDT 24
Peak memory 216924 kb
Host smart-9a672f2c-a2df-41ff-b751-50269cc3d9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181841777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2181841777
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3382624517
Short name T767
Test name
Test status
Simulation time 589687756 ps
CPU time 1.13 seconds
Started Mar 31 03:19:23 PM PDT 24
Finished Mar 31 03:19:25 PM PDT 24
Peak memory 197748 kb
Host smart-c73997b7-b5ed-43e3-9397-e89bf66b9023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382624517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3382624517
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2719106904
Short name T785
Test name
Test status
Simulation time 94179383514 ps
CPU time 37.8 seconds
Started Mar 31 03:19:22 PM PDT 24
Finished Mar 31 03:20:00 PM PDT 24
Peak memory 200448 kb
Host smart-cad6650a-ba40-4b1d-9e3d-ddd4f13be26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719106904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2719106904
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1756573861
Short name T195
Test name
Test status
Simulation time 101203239360 ps
CPU time 27.41 seconds
Started Mar 31 03:27:07 PM PDT 24
Finished Mar 31 03:27:34 PM PDT 24
Peak memory 200536 kb
Host smart-a3151384-4128-4255-9f2d-5a91ee1ee115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756573861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1756573861
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3571209695
Short name T947
Test name
Test status
Simulation time 28245138440 ps
CPU time 41.44 seconds
Started Mar 31 03:27:06 PM PDT 24
Finished Mar 31 03:27:48 PM PDT 24
Peak memory 200532 kb
Host smart-021e8f33-e107-4c8a-b33d-2014e2d70011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571209695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3571209695
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4045887392
Short name T787
Test name
Test status
Simulation time 65003876635 ps
CPU time 102.92 seconds
Started Mar 31 03:27:14 PM PDT 24
Finished Mar 31 03:28:57 PM PDT 24
Peak memory 200440 kb
Host smart-112fdc41-25e7-4532-83b9-d9d7671d4ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045887392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4045887392
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2290967274
Short name T444
Test name
Test status
Simulation time 116590979681 ps
CPU time 50.55 seconds
Started Mar 31 03:27:14 PM PDT 24
Finished Mar 31 03:28:05 PM PDT 24
Peak memory 200520 kb
Host smart-b890503d-e7ec-4fe7-b206-d89feb6b318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290967274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2290967274
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1022408185
Short name T541
Test name
Test status
Simulation time 27757737759 ps
CPU time 28.32 seconds
Started Mar 31 03:27:13 PM PDT 24
Finished Mar 31 03:27:41 PM PDT 24
Peak memory 200440 kb
Host smart-b77c0980-eccb-48ed-9db2-fc5bc7da9e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022408185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1022408185
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1625378855
Short name T967
Test name
Test status
Simulation time 123493693546 ps
CPU time 97.88 seconds
Started Mar 31 03:27:14 PM PDT 24
Finished Mar 31 03:28:52 PM PDT 24
Peak memory 200500 kb
Host smart-2893b14e-a5ae-4fcc-870b-f15da7bef8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625378855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1625378855
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2645014126
Short name T504
Test name
Test status
Simulation time 54956088168 ps
CPU time 94.37 seconds
Started Mar 31 03:27:13 PM PDT 24
Finished Mar 31 03:28:47 PM PDT 24
Peak memory 200532 kb
Host smart-e1fec134-dc2f-48ce-8fe6-913e2b5d2c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645014126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2645014126
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1692646007
Short name T687
Test name
Test status
Simulation time 17491858 ps
CPU time 0.53 seconds
Started Mar 31 03:19:38 PM PDT 24
Finished Mar 31 03:19:38 PM PDT 24
Peak memory 195324 kb
Host smart-d797a837-a981-4527-aa2b-bc5f517e6152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692646007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1692646007
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2354213022
Short name T880
Test name
Test status
Simulation time 40304752863 ps
CPU time 60.15 seconds
Started Mar 31 03:19:31 PM PDT 24
Finished Mar 31 03:20:31 PM PDT 24
Peak memory 200532 kb
Host smart-7f0e9df5-dbf6-4075-b709-86e52a5980a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354213022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2354213022
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1753136498
Short name T868
Test name
Test status
Simulation time 68555455259 ps
CPU time 27.21 seconds
Started Mar 31 03:19:31 PM PDT 24
Finished Mar 31 03:19:58 PM PDT 24
Peak memory 200524 kb
Host smart-50d129af-6aed-42c2-b0b9-6b71423f317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753136498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1753136498
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2429631336
Short name T192
Test name
Test status
Simulation time 32981763394 ps
CPU time 57.45 seconds
Started Mar 31 03:19:30 PM PDT 24
Finished Mar 31 03:20:28 PM PDT 24
Peak memory 200416 kb
Host smart-9b6334d3-95f6-45a6-8f4a-8a2b4888b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429631336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2429631336
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2803910610
Short name T648
Test name
Test status
Simulation time 25948771749 ps
CPU time 19.34 seconds
Started Mar 31 03:19:33 PM PDT 24
Finished Mar 31 03:19:52 PM PDT 24
Peak memory 200380 kb
Host smart-109248d8-d90b-41b3-8414-f538edac1a7a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803910610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2803910610
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.646775983
Short name T882
Test name
Test status
Simulation time 52845551520 ps
CPU time 117.16 seconds
Started Mar 31 03:19:36 PM PDT 24
Finished Mar 31 03:21:33 PM PDT 24
Peak memory 200468 kb
Host smart-4d527410-dcdb-47fb-b2ea-df3eeb0f572d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646775983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.646775983
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2455956874
Short name T367
Test name
Test status
Simulation time 2535021211 ps
CPU time 2.3 seconds
Started Mar 31 03:19:38 PM PDT 24
Finished Mar 31 03:19:41 PM PDT 24
Peak memory 199676 kb
Host smart-fff4067a-9ded-4725-9adc-684dfda540b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455956874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2455956874
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3446740919
Short name T566
Test name
Test status
Simulation time 119508882646 ps
CPU time 124.95 seconds
Started Mar 31 03:19:31 PM PDT 24
Finished Mar 31 03:21:36 PM PDT 24
Peak memory 200304 kb
Host smart-11e79963-4347-4ef8-a6b8-c0406b41bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446740919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3446740919
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.4229498710
Short name T401
Test name
Test status
Simulation time 11027552547 ps
CPU time 575.4 seconds
Started Mar 31 03:19:36 PM PDT 24
Finished Mar 31 03:29:11 PM PDT 24
Peak memory 200400 kb
Host smart-1084d46c-2a08-4ae1-b653-ec8d0e7f83fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229498710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4229498710
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1385404473
Short name T744
Test name
Test status
Simulation time 5531875435 ps
CPU time 9.21 seconds
Started Mar 31 03:19:31 PM PDT 24
Finished Mar 31 03:19:40 PM PDT 24
Peak memory 199400 kb
Host smart-f05d27e1-c49d-42cd-9de4-00839359f108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385404473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1385404473
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.938578241
Short name T679
Test name
Test status
Simulation time 45948631755 ps
CPU time 16.3 seconds
Started Mar 31 03:19:37 PM PDT 24
Finished Mar 31 03:19:54 PM PDT 24
Peak memory 200480 kb
Host smart-dfac33f0-584b-465d-8ac9-a0a3b09b4e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938578241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.938578241
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1582053375
Short name T1042
Test name
Test status
Simulation time 4799755237 ps
CPU time 4.8 seconds
Started Mar 31 03:19:32 PM PDT 24
Finished Mar 31 03:19:36 PM PDT 24
Peak memory 196828 kb
Host smart-8892c295-58e6-4a5c-8183-5b49387bbe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582053375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1582053375
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.730128376
Short name T496
Test name
Test status
Simulation time 151218442 ps
CPU time 0.79 seconds
Started Mar 31 03:19:31 PM PDT 24
Finished Mar 31 03:19:32 PM PDT 24
Peak memory 198240 kb
Host smart-94e4a0be-ebfd-499c-a604-62947ac7f465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730128376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.730128376
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3209065802
Short name T563
Test name
Test status
Simulation time 269824754317 ps
CPU time 1403.63 seconds
Started Mar 31 03:19:38 PM PDT 24
Finished Mar 31 03:43:01 PM PDT 24
Peak memory 200468 kb
Host smart-53896fea-b214-40b7-8caf-62017d47709b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209065802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3209065802
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2978931961
Short name T1154
Test name
Test status
Simulation time 52098452506 ps
CPU time 1057.94 seconds
Started Mar 31 03:19:38 PM PDT 24
Finished Mar 31 03:37:16 PM PDT 24
Peak memory 217228 kb
Host smart-47ba0221-b585-4a4a-8407-8f4c82629100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978931961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2978931961
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1565699301
Short name T738
Test name
Test status
Simulation time 856307157 ps
CPU time 3.2 seconds
Started Mar 31 03:19:37 PM PDT 24
Finished Mar 31 03:19:40 PM PDT 24
Peak memory 198744 kb
Host smart-ae8f91f1-2107-4750-b506-271ce283ec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565699301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1565699301
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.4248288781
Short name T406
Test name
Test status
Simulation time 24423798136 ps
CPU time 41.27 seconds
Started Mar 31 03:19:32 PM PDT 24
Finished Mar 31 03:20:13 PM PDT 24
Peak memory 200420 kb
Host smart-1142cf26-6a25-473b-a94d-6716784f4a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248288781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.4248288781
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2795743341
Short name T229
Test name
Test status
Simulation time 82131715731 ps
CPU time 31.01 seconds
Started Mar 31 03:27:15 PM PDT 24
Finished Mar 31 03:27:46 PM PDT 24
Peak memory 200452 kb
Host smart-a1b97c28-7473-4665-86d2-83af876d8f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795743341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2795743341
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1195759217
Short name T1038
Test name
Test status
Simulation time 25473151141 ps
CPU time 43.08 seconds
Started Mar 31 03:27:24 PM PDT 24
Finished Mar 31 03:28:07 PM PDT 24
Peak memory 200552 kb
Host smart-c9fea76d-bc1b-4722-bb6f-abaa498043e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195759217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1195759217
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3905179688
Short name T953
Test name
Test status
Simulation time 67542046393 ps
CPU time 29.08 seconds
Started Mar 31 03:27:20 PM PDT 24
Finished Mar 31 03:27:49 PM PDT 24
Peak memory 200436 kb
Host smart-9e9fdc51-77cc-4c89-b5dc-41871733e9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905179688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3905179688
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3030414586
Short name T216
Test name
Test status
Simulation time 78990415911 ps
CPU time 19.79 seconds
Started Mar 31 03:27:24 PM PDT 24
Finished Mar 31 03:27:44 PM PDT 24
Peak memory 200532 kb
Host smart-fd7289ad-db2f-4af9-84ca-a9c4d3d794aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030414586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3030414586
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2053486436
Short name T378
Test name
Test status
Simulation time 43015546230 ps
CPU time 67.53 seconds
Started Mar 31 03:27:19 PM PDT 24
Finished Mar 31 03:28:27 PM PDT 24
Peak memory 200480 kb
Host smart-1eaf217d-1865-4146-b308-92160e10f18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053486436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2053486436
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1328785210
Short name T173
Test name
Test status
Simulation time 303686724385 ps
CPU time 281.32 seconds
Started Mar 31 03:27:23 PM PDT 24
Finished Mar 31 03:32:05 PM PDT 24
Peak memory 200472 kb
Host smart-9b18aaa8-4281-4a6d-81e1-d260e7e61c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328785210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1328785210
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1684157744
Short name T1030
Test name
Test status
Simulation time 16721880993 ps
CPU time 28.49 seconds
Started Mar 31 03:27:20 PM PDT 24
Finished Mar 31 03:27:49 PM PDT 24
Peak memory 200456 kb
Host smart-bee623a7-910b-4f5e-b068-933f7fe63211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684157744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1684157744
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1159934896
Short name T1160
Test name
Test status
Simulation time 21053116296 ps
CPU time 42.78 seconds
Started Mar 31 03:27:25 PM PDT 24
Finished Mar 31 03:28:08 PM PDT 24
Peak memory 200388 kb
Host smart-513a6133-32f2-40ec-a07c-1b7fb0b19781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159934896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1159934896
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.592555129
Short name T1085
Test name
Test status
Simulation time 31847162416 ps
CPU time 29.45 seconds
Started Mar 31 03:27:26 PM PDT 24
Finished Mar 31 03:27:56 PM PDT 24
Peak memory 200488 kb
Host smart-6166b72b-7436-4405-8e92-24de878a1609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592555129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.592555129
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.301959277
Short name T812
Test name
Test status
Simulation time 42829970 ps
CPU time 0.55 seconds
Started Mar 31 03:19:56 PM PDT 24
Finished Mar 31 03:19:57 PM PDT 24
Peak memory 195900 kb
Host smart-11cb0b66-6d30-4bee-929e-06814a98d41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301959277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.301959277
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.113944005
Short name T259
Test name
Test status
Simulation time 138266444788 ps
CPU time 217.46 seconds
Started Mar 31 03:19:44 PM PDT 24
Finished Mar 31 03:23:21 PM PDT 24
Peak memory 200436 kb
Host smart-7e798b57-a158-460f-a260-0c709391f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113944005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.113944005
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2122882693
Short name T804
Test name
Test status
Simulation time 52685016298 ps
CPU time 81.53 seconds
Started Mar 31 03:19:43 PM PDT 24
Finished Mar 31 03:21:04 PM PDT 24
Peak memory 200500 kb
Host smart-682339a6-479e-4808-980e-f585f5ba194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122882693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2122882693
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2860330996
Short name T1079
Test name
Test status
Simulation time 45732782815 ps
CPU time 20.73 seconds
Started Mar 31 03:19:43 PM PDT 24
Finished Mar 31 03:20:04 PM PDT 24
Peak memory 200516 kb
Host smart-ee8c85d4-618d-466d-a914-cf8c9e40a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860330996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2860330996
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3003903296
Short name T950
Test name
Test status
Simulation time 269231045454 ps
CPU time 105.76 seconds
Started Mar 31 03:19:44 PM PDT 24
Finished Mar 31 03:21:30 PM PDT 24
Peak memory 198560 kb
Host smart-607e892d-c736-464d-9e95-562762fc61f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003903296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3003903296
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1580766665
Short name T579
Test name
Test status
Simulation time 55811856921 ps
CPU time 162.95 seconds
Started Mar 31 03:19:49 PM PDT 24
Finished Mar 31 03:22:32 PM PDT 24
Peak memory 200392 kb
Host smart-2b78520a-85ff-43b1-9db0-9b4c7ad7b5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580766665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1580766665
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1342083165
Short name T564
Test name
Test status
Simulation time 10094247207 ps
CPU time 9.38 seconds
Started Mar 31 03:19:48 PM PDT 24
Finished Mar 31 03:19:57 PM PDT 24
Peak memory 200048 kb
Host smart-15a11019-56a1-4f80-af7b-d5868bc5a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342083165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1342083165
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2326982876
Short name T311
Test name
Test status
Simulation time 25572218481 ps
CPU time 42.94 seconds
Started Mar 31 03:19:50 PM PDT 24
Finished Mar 31 03:20:33 PM PDT 24
Peak memory 199472 kb
Host smart-6be14291-2416-46f2-9113-dfd6e17f24e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326982876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2326982876
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.4123685332
Short name T288
Test name
Test status
Simulation time 6759741730 ps
CPU time 87.04 seconds
Started Mar 31 03:19:49 PM PDT 24
Finished Mar 31 03:21:16 PM PDT 24
Peak memory 200488 kb
Host smart-37105d19-5d97-42f9-890a-008ef5808182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123685332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4123685332
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.185874455
Short name T631
Test name
Test status
Simulation time 1381825905 ps
CPU time 3.09 seconds
Started Mar 31 03:19:43 PM PDT 24
Finished Mar 31 03:19:46 PM PDT 24
Peak memory 198676 kb
Host smart-7424ed73-1956-4244-a553-3d46c475ce03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185874455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.185874455
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.4029670345
Short name T926
Test name
Test status
Simulation time 225472593178 ps
CPU time 87.14 seconds
Started Mar 31 03:19:48 PM PDT 24
Finished Mar 31 03:21:16 PM PDT 24
Peak memory 200432 kb
Host smart-e605126d-db98-4fc6-9507-71f8f428a104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029670345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4029670345
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.706399344
Short name T706
Test name
Test status
Simulation time 47133520783 ps
CPU time 69.16 seconds
Started Mar 31 03:19:49 PM PDT 24
Finished Mar 31 03:20:58 PM PDT 24
Peak memory 196520 kb
Host smart-d6139f4f-22ff-4e1d-867e-627c32decba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706399344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.706399344
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3513630734
Short name T349
Test name
Test status
Simulation time 682226248 ps
CPU time 1.78 seconds
Started Mar 31 03:19:45 PM PDT 24
Finished Mar 31 03:19:47 PM PDT 24
Peak memory 200156 kb
Host smart-bf0aabee-743c-45c7-abb9-d2477be05f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513630734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3513630734
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3738829674
Short name T835
Test name
Test status
Simulation time 120467011670 ps
CPU time 60.38 seconds
Started Mar 31 03:19:57 PM PDT 24
Finished Mar 31 03:20:58 PM PDT 24
Peak memory 200464 kb
Host smart-06b9c611-9526-4db4-9d42-ccf998c58ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738829674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3738829674
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2138764009
Short name T1102
Test name
Test status
Simulation time 205145753613 ps
CPU time 324.94 seconds
Started Mar 31 03:19:49 PM PDT 24
Finished Mar 31 03:25:14 PM PDT 24
Peak memory 217020 kb
Host smart-e14b70e2-60c2-4fea-a311-a90bfe8754c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138764009 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2138764009
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1141266392
Short name T287
Test name
Test status
Simulation time 6972716493 ps
CPU time 16.7 seconds
Started Mar 31 03:19:49 PM PDT 24
Finished Mar 31 03:20:06 PM PDT 24
Peak memory 200440 kb
Host smart-2aacc037-4733-4652-9900-da050913c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141266392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1141266392
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1128280593
Short name T1153
Test name
Test status
Simulation time 17554864260 ps
CPU time 30.85 seconds
Started Mar 31 03:19:43 PM PDT 24
Finished Mar 31 03:20:14 PM PDT 24
Peak memory 200492 kb
Host smart-719b84a2-4666-4a87-9b1f-a23e8a3228b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128280593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1128280593
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3893394224
Short name T191
Test name
Test status
Simulation time 44316148200 ps
CPU time 63.73 seconds
Started Mar 31 03:27:25 PM PDT 24
Finished Mar 31 03:28:29 PM PDT 24
Peak memory 200460 kb
Host smart-f35c1d55-d5c3-4b5d-8f5b-4e5e811f3eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893394224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3893394224
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.4294221104
Short name T731
Test name
Test status
Simulation time 88282201799 ps
CPU time 67.14 seconds
Started Mar 31 03:27:27 PM PDT 24
Finished Mar 31 03:28:35 PM PDT 24
Peak memory 200464 kb
Host smart-62e07202-a939-40a2-9c8a-f168d6c1ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294221104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4294221104
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1342357311
Short name T108
Test name
Test status
Simulation time 38078781131 ps
CPU time 63.59 seconds
Started Mar 31 03:27:27 PM PDT 24
Finished Mar 31 03:28:31 PM PDT 24
Peak memory 200444 kb
Host smart-12b73158-9668-4b41-b9ab-8f31611f4684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342357311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1342357311
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.445987873
Short name T222
Test name
Test status
Simulation time 150458108892 ps
CPU time 125.83 seconds
Started Mar 31 03:27:25 PM PDT 24
Finished Mar 31 03:29:31 PM PDT 24
Peak memory 200404 kb
Host smart-12da1286-3025-4518-ae80-a57152dccadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445987873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.445987873
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1349862796
Short name T301
Test name
Test status
Simulation time 43340895865 ps
CPU time 31.35 seconds
Started Mar 31 03:27:26 PM PDT 24
Finished Mar 31 03:27:57 PM PDT 24
Peak memory 200280 kb
Host smart-1b442acb-1cde-4bf5-9d5a-f2729ca149d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349862796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1349862796
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2471190431
Short name T313
Test name
Test status
Simulation time 129386840690 ps
CPU time 205.13 seconds
Started Mar 31 03:27:30 PM PDT 24
Finished Mar 31 03:30:55 PM PDT 24
Peak memory 200340 kb
Host smart-51bc3bd1-a7c4-4755-82f2-3a9ad29cb48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471190431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2471190431
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3806980967
Short name T742
Test name
Test status
Simulation time 57930200608 ps
CPU time 103.52 seconds
Started Mar 31 03:27:30 PM PDT 24
Finished Mar 31 03:29:14 PM PDT 24
Peak memory 200436 kb
Host smart-2c4bdbd3-101c-49df-89ba-0779c60c10b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806980967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3806980967
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2763973520
Short name T1008
Test name
Test status
Simulation time 73859227100 ps
CPU time 119.02 seconds
Started Mar 31 03:27:31 PM PDT 24
Finished Mar 31 03:29:30 PM PDT 24
Peak memory 200536 kb
Host smart-11e5fcdf-74cf-4efa-a86f-2730c9809ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763973520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2763973520
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2933051385
Short name T537
Test name
Test status
Simulation time 37781942 ps
CPU time 0.59 seconds
Started Mar 31 03:20:07 PM PDT 24
Finished Mar 31 03:20:08 PM PDT 24
Peak memory 195872 kb
Host smart-3992a0ee-5975-41f7-b682-6eef8e65613b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933051385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2933051385
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3030161398
Short name T505
Test name
Test status
Simulation time 84345937065 ps
CPU time 82.47 seconds
Started Mar 31 03:19:59 PM PDT 24
Finished Mar 31 03:21:21 PM PDT 24
Peak memory 200572 kb
Host smart-0a9e5796-b402-4350-82d3-34d808e20da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030161398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3030161398
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.294557106
Short name T77
Test name
Test status
Simulation time 132751386447 ps
CPU time 268.17 seconds
Started Mar 31 03:19:56 PM PDT 24
Finished Mar 31 03:24:25 PM PDT 24
Peak memory 200468 kb
Host smart-de9c0f38-38cf-4559-8c69-5c89ec5d7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294557106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.294557106
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3238581525
Short name T603
Test name
Test status
Simulation time 96258143592 ps
CPU time 38.75 seconds
Started Mar 31 03:19:56 PM PDT 24
Finished Mar 31 03:20:35 PM PDT 24
Peak memory 200476 kb
Host smart-1c0ead3e-e51e-4720-894b-32f72816f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238581525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3238581525
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1134141154
Short name T1179
Test name
Test status
Simulation time 90675482749 ps
CPU time 34.57 seconds
Started Mar 31 03:19:57 PM PDT 24
Finished Mar 31 03:20:31 PM PDT 24
Peak memory 196536 kb
Host smart-a43fc9c0-520d-497c-b6c4-cdbab941a861
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134141154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1134141154
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.4080104852
Short name T695
Test name
Test status
Simulation time 144949878312 ps
CPU time 183.38 seconds
Started Mar 31 03:20:09 PM PDT 24
Finished Mar 31 03:23:12 PM PDT 24
Peak memory 200436 kb
Host smart-4488a1fa-8384-4994-9ef4-6942415fef7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080104852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4080104852
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1085963939
Short name T615
Test name
Test status
Simulation time 5873286385 ps
CPU time 4.54 seconds
Started Mar 31 03:20:09 PM PDT 24
Finished Mar 31 03:20:14 PM PDT 24
Peak memory 200048 kb
Host smart-fb3ac4e4-038b-4327-b189-e3f7da16f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085963939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1085963939
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3969965940
Short name T449
Test name
Test status
Simulation time 203881987993 ps
CPU time 48.86 seconds
Started Mar 31 03:19:57 PM PDT 24
Finished Mar 31 03:20:46 PM PDT 24
Peak memory 200760 kb
Host smart-1c3e2b7a-c468-4c08-9f23-7b3d355eefe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969965940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3969965940
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.271812368
Short name T1096
Test name
Test status
Simulation time 9097365275 ps
CPU time 555.94 seconds
Started Mar 31 03:20:11 PM PDT 24
Finished Mar 31 03:29:27 PM PDT 24
Peak memory 200512 kb
Host smart-aff8eece-0368-43b9-9aa4-2711444b28f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271812368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.271812368
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2936132425
Short name T590
Test name
Test status
Simulation time 5544590455 ps
CPU time 13.41 seconds
Started Mar 31 03:19:58 PM PDT 24
Finished Mar 31 03:20:12 PM PDT 24
Peak memory 199768 kb
Host smart-0d3cdfa6-e154-457a-bb4f-390af18c1617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936132425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2936132425
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3919004407
Short name T171
Test name
Test status
Simulation time 119685408014 ps
CPU time 360.53 seconds
Started Mar 31 03:19:57 PM PDT 24
Finished Mar 31 03:25:58 PM PDT 24
Peak memory 200500 kb
Host smart-d1c3b618-36d7-4724-bdd8-98a81473c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919004407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3919004407
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.200982455
Short name T920
Test name
Test status
Simulation time 63525131487 ps
CPU time 102.92 seconds
Started Mar 31 03:19:57 PM PDT 24
Finished Mar 31 03:21:40 PM PDT 24
Peak memory 196796 kb
Host smart-1889a894-d9ad-49b4-aa16-846554053253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200982455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.200982455
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1026047252
Short name T927
Test name
Test status
Simulation time 479829272 ps
CPU time 0.96 seconds
Started Mar 31 03:19:56 PM PDT 24
Finished Mar 31 03:19:58 PM PDT 24
Peak memory 198788 kb
Host smart-47921c16-447d-4413-8678-7d763acf6f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026047252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1026047252
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.724885115
Short name T628
Test name
Test status
Simulation time 196835258563 ps
CPU time 206.73 seconds
Started Mar 31 03:20:07 PM PDT 24
Finished Mar 31 03:23:34 PM PDT 24
Peak memory 216560 kb
Host smart-8da6591c-c164-4122-84ad-3b313644d2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724885115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.724885115
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4246384615
Short name T1180
Test name
Test status
Simulation time 6658387043 ps
CPU time 25.25 seconds
Started Mar 31 03:20:11 PM PDT 24
Finished Mar 31 03:20:36 PM PDT 24
Peak memory 199780 kb
Host smart-fac279d8-daaf-4252-8825-73b72e24b112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246384615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4246384615
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1234048246
Short name T1159
Test name
Test status
Simulation time 25849852164 ps
CPU time 44.63 seconds
Started Mar 31 03:19:57 PM PDT 24
Finished Mar 31 03:20:42 PM PDT 24
Peak memory 200408 kb
Host smart-609326f3-e634-4e75-9608-c6c4e3d01242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234048246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1234048246
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.740054476
Short name T107
Test name
Test status
Simulation time 18265336570 ps
CPU time 31.89 seconds
Started Mar 31 03:27:30 PM PDT 24
Finished Mar 31 03:28:02 PM PDT 24
Peak memory 200420 kb
Host smart-db0577ee-ed6e-4232-a4c1-cbec597b94cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740054476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.740054476
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1548174825
Short name T673
Test name
Test status
Simulation time 69763108931 ps
CPU time 127.59 seconds
Started Mar 31 03:27:32 PM PDT 24
Finished Mar 31 03:29:39 PM PDT 24
Peak memory 200440 kb
Host smart-571f5ae7-6a33-49f9-9b05-2a166cae99f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548174825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1548174825
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3956873299
Short name T189
Test name
Test status
Simulation time 79816741163 ps
CPU time 35.19 seconds
Started Mar 31 03:27:31 PM PDT 24
Finished Mar 31 03:28:07 PM PDT 24
Peak memory 200496 kb
Host smart-fc675ecc-04eb-477e-907c-42cc6b66255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956873299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3956873299
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1126647397
Short name T93
Test name
Test status
Simulation time 9949394232 ps
CPU time 17.06 seconds
Started Mar 31 03:27:31 PM PDT 24
Finished Mar 31 03:27:48 PM PDT 24
Peak memory 200484 kb
Host smart-6d75f324-3bf4-4845-acfd-3aaa30826c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126647397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1126647397
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1485786128
Short name T758
Test name
Test status
Simulation time 113590861844 ps
CPU time 38.21 seconds
Started Mar 31 03:27:35 PM PDT 24
Finished Mar 31 03:28:13 PM PDT 24
Peak memory 200548 kb
Host smart-0bc8f0e8-90fc-4bb7-b69c-dd2fd5719cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485786128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1485786128
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2049648506
Short name T417
Test name
Test status
Simulation time 16224447796 ps
CPU time 38.05 seconds
Started Mar 31 03:27:37 PM PDT 24
Finished Mar 31 03:28:15 PM PDT 24
Peak memory 200236 kb
Host smart-6ee3e38c-a037-443e-89aa-6b85e43b62ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049648506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2049648506
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1160594040
Short name T261
Test name
Test status
Simulation time 65828460324 ps
CPU time 95.22 seconds
Started Mar 31 03:27:38 PM PDT 24
Finished Mar 31 03:29:13 PM PDT 24
Peak memory 200476 kb
Host smart-1bdadc00-648d-417a-bf73-63a22608dd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160594040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1160594040
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1401556411
Short name T176
Test name
Test status
Simulation time 93547129703 ps
CPU time 172.24 seconds
Started Mar 31 03:27:37 PM PDT 24
Finished Mar 31 03:30:29 PM PDT 24
Peak memory 200424 kb
Host smart-dcb8552a-01e1-4b05-a349-6db861cd7079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401556411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1401556411
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.19499268
Short name T1095
Test name
Test status
Simulation time 172460337824 ps
CPU time 60.77 seconds
Started Mar 31 03:27:36 PM PDT 24
Finished Mar 31 03:28:37 PM PDT 24
Peak memory 200488 kb
Host smart-381d46c7-d0ee-4a69-bb2b-25da87525702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19499268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.19499268
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.229546370
Short name T561
Test name
Test status
Simulation time 13460389 ps
CPU time 0.54 seconds
Started Mar 31 03:20:22 PM PDT 24
Finished Mar 31 03:20:23 PM PDT 24
Peak memory 195868 kb
Host smart-43e07e21-ca88-498b-88f8-8f1819c68ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229546370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.229546370
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2509531608
Short name T576
Test name
Test status
Simulation time 15609669841 ps
CPU time 5.83 seconds
Started Mar 31 03:20:11 PM PDT 24
Finished Mar 31 03:20:17 PM PDT 24
Peak memory 200416 kb
Host smart-5f5ce490-a97a-4ef5-914c-637a81461b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509531608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2509531608
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3342491230
Short name T860
Test name
Test status
Simulation time 69249415055 ps
CPU time 115.14 seconds
Started Mar 31 03:20:09 PM PDT 24
Finished Mar 31 03:22:04 PM PDT 24
Peak memory 200448 kb
Host smart-151ab54e-cf09-4a52-abf0-e3d50caf8c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342491230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3342491230
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1632484337
Short name T599
Test name
Test status
Simulation time 22330311430 ps
CPU time 19.65 seconds
Started Mar 31 03:20:12 PM PDT 24
Finished Mar 31 03:20:32 PM PDT 24
Peak memory 200436 kb
Host smart-3d2c4940-8099-466a-af65-736fb67c994c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632484337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1632484337
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.398915407
Short name T325
Test name
Test status
Simulation time 45978298374 ps
CPU time 53.93 seconds
Started Mar 31 03:20:16 PM PDT 24
Finished Mar 31 03:21:10 PM PDT 24
Peak memory 200544 kb
Host smart-aa59c58d-0ae8-428c-a029-9edb63fd8f43
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398915407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.398915407
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1349168256
Short name T1118
Test name
Test status
Simulation time 84737007100 ps
CPU time 569.65 seconds
Started Mar 31 03:20:15 PM PDT 24
Finished Mar 31 03:29:45 PM PDT 24
Peak memory 200508 kb
Host smart-fd535ab7-71e6-4fc6-83dd-298539db66a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349168256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1349168256
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1519290643
Short name T501
Test name
Test status
Simulation time 2707512572 ps
CPU time 1.19 seconds
Started Mar 31 03:20:15 PM PDT 24
Finished Mar 31 03:20:17 PM PDT 24
Peak memory 199164 kb
Host smart-89ea55f7-f6d5-485f-a450-755f2f8d96f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519290643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1519290643
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2590656687
Short name T620
Test name
Test status
Simulation time 52120088014 ps
CPU time 79.39 seconds
Started Mar 31 03:20:20 PM PDT 24
Finished Mar 31 03:21:40 PM PDT 24
Peak memory 200228 kb
Host smart-2cd7c003-5426-477e-bd65-d64835a03696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590656687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2590656687
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.625236633
Short name T898
Test name
Test status
Simulation time 13129717573 ps
CPU time 133.05 seconds
Started Mar 31 03:20:15 PM PDT 24
Finished Mar 31 03:22:29 PM PDT 24
Peak memory 200492 kb
Host smart-a5b44d4e-663a-4553-8335-e80b6cee0ac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625236633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.625236633
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3134125710
Short name T718
Test name
Test status
Simulation time 3486255819 ps
CPU time 26.19 seconds
Started Mar 31 03:20:09 PM PDT 24
Finished Mar 31 03:20:35 PM PDT 24
Peak memory 199624 kb
Host smart-76b36986-1422-43d0-af51-329a31313577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134125710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3134125710
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1259231563
Short name T480
Test name
Test status
Simulation time 53554645822 ps
CPU time 16.57 seconds
Started Mar 31 03:20:15 PM PDT 24
Finished Mar 31 03:20:32 PM PDT 24
Peak memory 200424 kb
Host smart-cb86f70d-d422-4abe-93d6-70e7fe76163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259231563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1259231563
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2297409493
Short name T799
Test name
Test status
Simulation time 653439760 ps
CPU time 1.52 seconds
Started Mar 31 03:20:16 PM PDT 24
Finished Mar 31 03:20:18 PM PDT 24
Peak memory 196152 kb
Host smart-a16e8ef0-143f-42d0-9d18-2c3a0c64fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297409493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2297409493
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.4186642643
Short name T263
Test name
Test status
Simulation time 6302058592 ps
CPU time 7.2 seconds
Started Mar 31 03:20:07 PM PDT 24
Finished Mar 31 03:20:14 PM PDT 24
Peak memory 200428 kb
Host smart-30d437fb-5e88-40cd-8a3b-12a85312cf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186642643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4186642643
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.4222733401
Short name T796
Test name
Test status
Simulation time 331713992636 ps
CPU time 370.86 seconds
Started Mar 31 03:20:16 PM PDT 24
Finished Mar 31 03:26:27 PM PDT 24
Peak memory 200432 kb
Host smart-55b27092-4ef4-4b36-a13b-09a546c434d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222733401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4222733401
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2773174652
Short name T210
Test name
Test status
Simulation time 118277635462 ps
CPU time 361.11 seconds
Started Mar 31 03:20:16 PM PDT 24
Finished Mar 31 03:26:17 PM PDT 24
Peak memory 216900 kb
Host smart-f01edccc-e6b8-43dd-b0ef-c95f4aa51cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773174652 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2773174652
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2841515777
Short name T750
Test name
Test status
Simulation time 1624580349 ps
CPU time 2.18 seconds
Started Mar 31 03:20:20 PM PDT 24
Finished Mar 31 03:20:22 PM PDT 24
Peak memory 200228 kb
Host smart-129147d7-305c-4f4a-87db-af1cbb08b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841515777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2841515777
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3012382094
Short name T246
Test name
Test status
Simulation time 58287056896 ps
CPU time 53.34 seconds
Started Mar 31 03:20:09 PM PDT 24
Finished Mar 31 03:21:02 PM PDT 24
Peak memory 200524 kb
Host smart-24ebd51e-4e2e-447e-b7ed-dc016ea24d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012382094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3012382094
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1779992128
Short name T1049
Test name
Test status
Simulation time 9227999660 ps
CPU time 17.8 seconds
Started Mar 31 03:27:37 PM PDT 24
Finished Mar 31 03:27:55 PM PDT 24
Peak memory 200500 kb
Host smart-64e7131e-3f53-47ef-8dfe-13648b104183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779992128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1779992128
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4246598239
Short name T552
Test name
Test status
Simulation time 101814894832 ps
CPU time 195.61 seconds
Started Mar 31 03:27:35 PM PDT 24
Finished Mar 31 03:30:52 PM PDT 24
Peak memory 200468 kb
Host smart-31dfcb48-cb12-4bfb-bb52-6844317194c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246598239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4246598239
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3458366506
Short name T524
Test name
Test status
Simulation time 54862460457 ps
CPU time 18.27 seconds
Started Mar 31 03:27:36 PM PDT 24
Finished Mar 31 03:27:54 PM PDT 24
Peak memory 200540 kb
Host smart-d7b4eccd-58a7-4456-ae41-25ad69b5ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458366506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3458366506
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2670347993
Short name T34
Test name
Test status
Simulation time 227573010274 ps
CPU time 59.87 seconds
Started Mar 31 03:27:39 PM PDT 24
Finished Mar 31 03:28:39 PM PDT 24
Peak memory 200404 kb
Host smart-8af77187-37c6-4402-b861-af5841482611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670347993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2670347993
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1834447603
Short name T791
Test name
Test status
Simulation time 24876514914 ps
CPU time 51.16 seconds
Started Mar 31 03:27:42 PM PDT 24
Finished Mar 31 03:28:33 PM PDT 24
Peak memory 200532 kb
Host smart-2ab81c2e-46b6-427c-8ef9-c485a75cc21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834447603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1834447603
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3826174791
Short name T217
Test name
Test status
Simulation time 107976188034 ps
CPU time 92.72 seconds
Started Mar 31 03:27:42 PM PDT 24
Finished Mar 31 03:29:15 PM PDT 24
Peak memory 200524 kb
Host smart-c3dcd548-ad72-4bad-9a06-412357d85fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826174791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3826174791
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.566291905
Short name T204
Test name
Test status
Simulation time 39314511080 ps
CPU time 91.03 seconds
Started Mar 31 03:27:44 PM PDT 24
Finished Mar 31 03:29:15 PM PDT 24
Peak memory 200440 kb
Host smart-f206c08f-91e5-43db-9326-f775d298b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566291905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.566291905
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1069759315
Short name T9
Test name
Test status
Simulation time 99015829479 ps
CPU time 40.92 seconds
Started Mar 31 03:27:40 PM PDT 24
Finished Mar 31 03:28:21 PM PDT 24
Peak memory 200512 kb
Host smart-5e4caaae-04ec-4cb9-bb04-a02ebc3207b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069759315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1069759315
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2549004572
Short name T158
Test name
Test status
Simulation time 66931426854 ps
CPU time 34.06 seconds
Started Mar 31 03:27:41 PM PDT 24
Finished Mar 31 03:28:16 PM PDT 24
Peak memory 200480 kb
Host smart-409d27c8-85bb-4ad6-8bee-6d09eac1ac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549004572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2549004572
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2127500195
Short name T1168
Test name
Test status
Simulation time 42967731431 ps
CPU time 9.83 seconds
Started Mar 31 03:27:41 PM PDT 24
Finished Mar 31 03:27:50 PM PDT 24
Peak memory 200456 kb
Host smart-d7be0e2e-44c7-4ab8-90ec-e692361b6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127500195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2127500195
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4046192418
Short name T1141
Test name
Test status
Simulation time 17244440 ps
CPU time 0.54 seconds
Started Mar 31 03:20:35 PM PDT 24
Finished Mar 31 03:20:35 PM PDT 24
Peak memory 194868 kb
Host smart-dd96e503-8251-4d4a-a49b-247fcddd25bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046192418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4046192418
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2693446361
Short name T243
Test name
Test status
Simulation time 38895915338 ps
CPU time 62.29 seconds
Started Mar 31 03:20:24 PM PDT 24
Finished Mar 31 03:21:27 PM PDT 24
Peak memory 200516 kb
Host smart-6a14e39f-47f5-4610-b774-cf5071b9046c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693446361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2693446361
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.947088839
Short name T143
Test name
Test status
Simulation time 12625532652 ps
CPU time 21.69 seconds
Started Mar 31 03:20:22 PM PDT 24
Finished Mar 31 03:20:44 PM PDT 24
Peak memory 200452 kb
Host smart-75955de9-503c-4ecb-bf9a-2a36724bd71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947088839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.947088839
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.486551850
Short name T908
Test name
Test status
Simulation time 129924813250 ps
CPU time 39.2 seconds
Started Mar 31 03:20:22 PM PDT 24
Finished Mar 31 03:21:01 PM PDT 24
Peak memory 200304 kb
Host smart-3679c7e2-6d7d-4706-b1a8-a09ca269c5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486551850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.486551850
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1651127845
Short name T493
Test name
Test status
Simulation time 302344190466 ps
CPU time 385.85 seconds
Started Mar 31 03:20:23 PM PDT 24
Finished Mar 31 03:26:49 PM PDT 24
Peak memory 200428 kb
Host smart-b772405b-8a60-4716-bd1c-a2fee84a12c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651127845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1651127845
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1580941283
Short name T1005
Test name
Test status
Simulation time 177445991154 ps
CPU time 471.68 seconds
Started Mar 31 03:20:34 PM PDT 24
Finished Mar 31 03:28:26 PM PDT 24
Peak memory 200472 kb
Host smart-2a878103-62bc-4798-8e9b-d1de65418cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580941283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1580941283
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2702673235
Short name T704
Test name
Test status
Simulation time 2995042759 ps
CPU time 7.32 seconds
Started Mar 31 03:20:27 PM PDT 24
Finished Mar 31 03:20:35 PM PDT 24
Peak memory 199024 kb
Host smart-62562628-3eba-41b9-97f3-fafbd0b04e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702673235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2702673235
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3928045285
Short name T330
Test name
Test status
Simulation time 21390681461 ps
CPU time 32.92 seconds
Started Mar 31 03:20:23 PM PDT 24
Finished Mar 31 03:20:57 PM PDT 24
Peak memory 199072 kb
Host smart-ab5bc596-8096-4699-ad81-f376218701ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928045285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3928045285
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.896212893
Short name T377
Test name
Test status
Simulation time 13362858657 ps
CPU time 210.89 seconds
Started Mar 31 03:20:29 PM PDT 24
Finished Mar 31 03:24:00 PM PDT 24
Peak memory 200500 kb
Host smart-b21bf9b2-091d-41b2-9ee2-4834153a0548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896212893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.896212893
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.128570552
Short name T1144
Test name
Test status
Simulation time 5001424344 ps
CPU time 37.59 seconds
Started Mar 31 03:20:22 PM PDT 24
Finished Mar 31 03:21:01 PM PDT 24
Peak memory 198568 kb
Host smart-436ef63b-5597-4a67-ab83-72901d62799a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128570552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.128570552
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1936529857
Short name T1017
Test name
Test status
Simulation time 30093904086 ps
CPU time 30.97 seconds
Started Mar 31 03:20:28 PM PDT 24
Finished Mar 31 03:20:59 PM PDT 24
Peak memory 200444 kb
Host smart-052a36d9-0697-4622-83ab-2cd9d66ea05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936529857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1936529857
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2471902566
Short name T598
Test name
Test status
Simulation time 83700782177 ps
CPU time 114.78 seconds
Started Mar 31 03:20:23 PM PDT 24
Finished Mar 31 03:22:18 PM PDT 24
Peak memory 196464 kb
Host smart-abf0982c-8d70-4369-b0c0-01a411e15825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471902566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2471902566
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.737351825
Short name T765
Test name
Test status
Simulation time 6046430100 ps
CPU time 8.42 seconds
Started Mar 31 03:20:23 PM PDT 24
Finished Mar 31 03:20:31 PM PDT 24
Peak memory 200268 kb
Host smart-bff76583-c4f5-45f0-88fe-e3734c53b859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737351825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.737351825
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3520890631
Short name T570
Test name
Test status
Simulation time 175546165690 ps
CPU time 74.23 seconds
Started Mar 31 03:20:35 PM PDT 24
Finished Mar 31 03:21:50 PM PDT 24
Peak memory 200820 kb
Host smart-97985382-6f1d-4ad2-b748-8a1b1ac79675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520890631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3520890631
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2559211430
Short name T946
Test name
Test status
Simulation time 133417366318 ps
CPU time 286.16 seconds
Started Mar 31 03:20:34 PM PDT 24
Finished Mar 31 03:25:20 PM PDT 24
Peak memory 214740 kb
Host smart-8ccafab0-fab1-47f0-8ee2-4798bc85b35a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559211430 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2559211430
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2550320138
Short name T1151
Test name
Test status
Simulation time 1703878304 ps
CPU time 2.49 seconds
Started Mar 31 03:20:28 PM PDT 24
Finished Mar 31 03:20:31 PM PDT 24
Peak memory 199024 kb
Host smart-ddd14ed4-a81f-443d-a666-20dc0dfb4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550320138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2550320138
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.858523472
Short name T1098
Test name
Test status
Simulation time 46506739065 ps
CPU time 42.16 seconds
Started Mar 31 03:20:22 PM PDT 24
Finished Mar 31 03:21:04 PM PDT 24
Peak memory 200416 kb
Host smart-6379bb8a-ffde-409c-8e99-f8930ceeda1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858523472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.858523472
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2506679999
Short name T244
Test name
Test status
Simulation time 15524908122 ps
CPU time 7.38 seconds
Started Mar 31 03:27:42 PM PDT 24
Finished Mar 31 03:27:51 PM PDT 24
Peak memory 200352 kb
Host smart-8ad3711e-5b77-4cc1-b378-62d6d01941f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506679999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2506679999
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3946365895
Short name T329
Test name
Test status
Simulation time 46340917680 ps
CPU time 121.08 seconds
Started Mar 31 03:27:42 PM PDT 24
Finished Mar 31 03:29:43 PM PDT 24
Peak memory 200496 kb
Host smart-77cc7528-84be-4337-b553-ccfe51164453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946365895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3946365895
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2729462335
Short name T1024
Test name
Test status
Simulation time 50378676702 ps
CPU time 10.41 seconds
Started Mar 31 03:27:41 PM PDT 24
Finished Mar 31 03:27:52 PM PDT 24
Peak memory 200512 kb
Host smart-1be2c9f3-ccce-4923-abe0-d8ee51cbcb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729462335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2729462335
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3906323044
Short name T614
Test name
Test status
Simulation time 16871472893 ps
CPU time 31.2 seconds
Started Mar 31 03:27:42 PM PDT 24
Finished Mar 31 03:28:13 PM PDT 24
Peak memory 200356 kb
Host smart-af9ac718-ac84-4b5d-98d0-37d51663126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906323044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3906323044
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3379033205
Short name T100
Test name
Test status
Simulation time 25971100749 ps
CPU time 49.05 seconds
Started Mar 31 03:27:41 PM PDT 24
Finished Mar 31 03:28:31 PM PDT 24
Peak memory 200504 kb
Host smart-da822e7f-3365-4330-9ce8-6ec7bae5951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379033205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3379033205
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.45071403
Short name T457
Test name
Test status
Simulation time 44426998321 ps
CPU time 110.37 seconds
Started Mar 31 03:27:44 PM PDT 24
Finished Mar 31 03:29:34 PM PDT 24
Peak memory 200416 kb
Host smart-e30ad7e2-6db1-4981-8ec8-0b513e61124a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45071403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.45071403
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.4147442427
Short name T621
Test name
Test status
Simulation time 45700193777 ps
CPU time 80 seconds
Started Mar 31 03:27:42 PM PDT 24
Finished Mar 31 03:29:02 PM PDT 24
Peak memory 200396 kb
Host smart-debb87ca-6e93-46a2-b6fb-ccaa6d07ef56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147442427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.4147442427
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.888774652
Short name T735
Test name
Test status
Simulation time 242716305463 ps
CPU time 156.4 seconds
Started Mar 31 03:27:47 PM PDT 24
Finished Mar 31 03:30:23 PM PDT 24
Peak memory 200452 kb
Host smart-1bc8f6fe-cf88-4f5e-8778-5cec7f30f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888774652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.888774652
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.18887657
Short name T389
Test name
Test status
Simulation time 25735092433 ps
CPU time 10.62 seconds
Started Mar 31 03:27:47 PM PDT 24
Finished Mar 31 03:27:58 PM PDT 24
Peak memory 199832 kb
Host smart-35cec877-d5b4-44cc-92fa-d0ffa49878c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18887657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.18887657
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.589948508
Short name T874
Test name
Test status
Simulation time 15137814 ps
CPU time 0.55 seconds
Started Mar 31 03:20:46 PM PDT 24
Finished Mar 31 03:20:47 PM PDT 24
Peak memory 195868 kb
Host smart-66fea523-a5f4-4535-85a0-3d7ca458f9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589948508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.589948508
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.224749884
Short name T702
Test name
Test status
Simulation time 20442487835 ps
CPU time 33.54 seconds
Started Mar 31 03:20:33 PM PDT 24
Finished Mar 31 03:21:07 PM PDT 24
Peak memory 200428 kb
Host smart-1caac885-881d-4c52-b890-49b28cf8f0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224749884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.224749884
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3180111869
Short name T1020
Test name
Test status
Simulation time 49398522909 ps
CPU time 74.85 seconds
Started Mar 31 03:20:33 PM PDT 24
Finished Mar 31 03:21:48 PM PDT 24
Peak memory 200424 kb
Host smart-5080a1c6-3356-41b0-8326-4c47416afb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180111869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3180111869
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_intr.3764229763
Short name T843
Test name
Test status
Simulation time 13887817830 ps
CPU time 3.35 seconds
Started Mar 31 03:20:36 PM PDT 24
Finished Mar 31 03:20:40 PM PDT 24
Peak memory 197208 kb
Host smart-367cb56a-637c-4909-b97c-c59cb354a50a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764229763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3764229763
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2946596075
Short name T512
Test name
Test status
Simulation time 357275703269 ps
CPU time 266.91 seconds
Started Mar 31 03:20:41 PM PDT 24
Finished Mar 31 03:25:08 PM PDT 24
Peak memory 200536 kb
Host smart-426569d8-1ff7-4ddf-83ab-b38aba70b980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946596075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2946596075
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4204575050
Short name T1054
Test name
Test status
Simulation time 2364338752 ps
CPU time 3.49 seconds
Started Mar 31 03:20:40 PM PDT 24
Finished Mar 31 03:20:44 PM PDT 24
Peak memory 199676 kb
Host smart-a8e5ed2f-243f-44fe-8d39-aa048f9bc4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204575050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4204575050
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.953031133
Short name T710
Test name
Test status
Simulation time 184834044448 ps
CPU time 93.34 seconds
Started Mar 31 03:20:35 PM PDT 24
Finished Mar 31 03:22:08 PM PDT 24
Peak memory 208820 kb
Host smart-139ba645-8079-4c17-a452-69407597d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953031133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.953031133
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1351287301
Short name T655
Test name
Test status
Simulation time 24196152929 ps
CPU time 89.11 seconds
Started Mar 31 03:20:44 PM PDT 24
Finished Mar 31 03:22:13 PM PDT 24
Peak memory 200512 kb
Host smart-3446629b-3ea8-4703-92f0-156d83f229f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351287301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1351287301
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2562919947
Short name T963
Test name
Test status
Simulation time 3267939728 ps
CPU time 6.78 seconds
Started Mar 31 03:20:35 PM PDT 24
Finished Mar 31 03:20:42 PM PDT 24
Peak memory 199576 kb
Host smart-560b6c28-2d50-4358-8236-b6c4fa18de78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562919947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2562919947
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1470373407
Short name T848
Test name
Test status
Simulation time 110043730690 ps
CPU time 47.23 seconds
Started Mar 31 03:20:43 PM PDT 24
Finished Mar 31 03:21:31 PM PDT 24
Peak memory 200532 kb
Host smart-fc532457-dedb-4380-985f-943af601d703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470373407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1470373407
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1933076696
Short name T502
Test name
Test status
Simulation time 4625983242 ps
CPU time 2.88 seconds
Started Mar 31 03:20:41 PM PDT 24
Finished Mar 31 03:20:44 PM PDT 24
Peak memory 196792 kb
Host smart-77c2080f-ad19-4b6c-9bac-1925576330ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933076696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1933076696
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.884330031
Short name T484
Test name
Test status
Simulation time 875663101 ps
CPU time 1.9 seconds
Started Mar 31 03:20:35 PM PDT 24
Finished Mar 31 03:20:37 PM PDT 24
Peak memory 198712 kb
Host smart-b014c11c-4bae-4b32-a6b5-31be80573824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884330031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.884330031
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.101070003
Short name T328
Test name
Test status
Simulation time 144503922743 ps
CPU time 125.07 seconds
Started Mar 31 03:20:47 PM PDT 24
Finished Mar 31 03:22:52 PM PDT 24
Peak memory 200540 kb
Host smart-766ed98f-268d-4e8b-9559-ba923bf0cb3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101070003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.101070003
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.855179958
Short name T316
Test name
Test status
Simulation time 162825226319 ps
CPU time 515.44 seconds
Started Mar 31 03:20:48 PM PDT 24
Finished Mar 31 03:29:23 PM PDT 24
Peak memory 225452 kb
Host smart-1588a6c4-67f2-4ae5-8696-30e0a2c2d342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855179958 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.855179958
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2943750603
Short name T1081
Test name
Test status
Simulation time 965635067 ps
CPU time 2.22 seconds
Started Mar 31 03:20:40 PM PDT 24
Finished Mar 31 03:20:43 PM PDT 24
Peak memory 199108 kb
Host smart-c895bf0b-516f-4f1c-9fb4-d73e8feb5a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943750603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2943750603
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1238900074
Short name T1004
Test name
Test status
Simulation time 151522536033 ps
CPU time 160.69 seconds
Started Mar 31 03:20:34 PM PDT 24
Finished Mar 31 03:23:15 PM PDT 24
Peak memory 200508 kb
Host smart-700c77d3-a073-4cfc-8134-98f18b25d263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238900074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1238900074
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4212931094
Short name T115
Test name
Test status
Simulation time 89314348883 ps
CPU time 122.93 seconds
Started Mar 31 03:27:46 PM PDT 24
Finished Mar 31 03:29:49 PM PDT 24
Peak memory 200432 kb
Host smart-fa99be06-2dcf-404c-8bce-8eb6772e5c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212931094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4212931094
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1871099278
Short name T982
Test name
Test status
Simulation time 23341620894 ps
CPU time 41 seconds
Started Mar 31 03:27:48 PM PDT 24
Finished Mar 31 03:28:29 PM PDT 24
Peak memory 200468 kb
Host smart-9ad8ed28-9f0b-4357-953c-3fecc2a33b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871099278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1871099278
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1150484688
Short name T520
Test name
Test status
Simulation time 30939278513 ps
CPU time 14.3 seconds
Started Mar 31 03:27:54 PM PDT 24
Finished Mar 31 03:28:09 PM PDT 24
Peak memory 200052 kb
Host smart-2b31b857-b766-4b3a-900a-b58a4ef343a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150484688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1150484688
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2811184399
Short name T205
Test name
Test status
Simulation time 19431498073 ps
CPU time 8.5 seconds
Started Mar 31 03:27:53 PM PDT 24
Finished Mar 31 03:28:02 PM PDT 24
Peak memory 200284 kb
Host smart-774b9ccc-48de-478c-9c0a-51ba5cb05c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811184399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2811184399
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2341892029
Short name T403
Test name
Test status
Simulation time 14214387944 ps
CPU time 26.53 seconds
Started Mar 31 03:27:52 PM PDT 24
Finished Mar 31 03:28:19 PM PDT 24
Peak memory 200556 kb
Host smart-a153a556-1080-4cc1-958c-dd4ecfd33a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341892029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2341892029
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.565663535
Short name T174
Test name
Test status
Simulation time 17274807710 ps
CPU time 38.94 seconds
Started Mar 31 03:27:51 PM PDT 24
Finished Mar 31 03:28:30 PM PDT 24
Peak memory 200520 kb
Host smart-56845383-e277-4325-ac32-ad29bcc03e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565663535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.565663535
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4124009686
Short name T227
Test name
Test status
Simulation time 57723194674 ps
CPU time 11.07 seconds
Started Mar 31 03:27:54 PM PDT 24
Finished Mar 31 03:28:06 PM PDT 24
Peak memory 200504 kb
Host smart-e18173f0-128a-4b69-9a89-54795a55de73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124009686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4124009686
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2802967132
Short name T207
Test name
Test status
Simulation time 27244866938 ps
CPU time 25.72 seconds
Started Mar 31 03:27:53 PM PDT 24
Finished Mar 31 03:28:19 PM PDT 24
Peak memory 200504 kb
Host smart-86382cb3-a290-4bd0-94b9-9de65aa4ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802967132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2802967132
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4266468933
Short name T1076
Test name
Test status
Simulation time 18341413859 ps
CPU time 19.92 seconds
Started Mar 31 03:27:52 PM PDT 24
Finished Mar 31 03:28:12 PM PDT 24
Peak memory 200428 kb
Host smart-42f3bd49-5546-4e55-8cf1-3a5e1112b2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266468933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4266468933
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.749489857
Short name T987
Test name
Test status
Simulation time 79231575 ps
CPU time 0.55 seconds
Started Mar 31 03:20:58 PM PDT 24
Finished Mar 31 03:20:59 PM PDT 24
Peak memory 195856 kb
Host smart-3bcba6ab-d89f-46da-a58a-13fc2987abe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749489857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.749489857
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.999802235
Short name T697
Test name
Test status
Simulation time 105363123065 ps
CPU time 50.59 seconds
Started Mar 31 03:20:47 PM PDT 24
Finished Mar 31 03:21:38 PM PDT 24
Peak memory 200416 kb
Host smart-4c8966c2-020a-4e15-99f1-8888b830facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999802235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.999802235
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.399056413
Short name T1131
Test name
Test status
Simulation time 66992586847 ps
CPU time 88.96 seconds
Started Mar 31 03:20:56 PM PDT 24
Finished Mar 31 03:22:25 PM PDT 24
Peak memory 200416 kb
Host smart-300b5012-a2eb-4a5d-8dfb-bd3b83601b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399056413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.399056413
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.1304029800
Short name T81
Test name
Test status
Simulation time 52881252914 ps
CPU time 9.87 seconds
Started Mar 31 03:20:53 PM PDT 24
Finished Mar 31 03:21:03 PM PDT 24
Peak memory 200260 kb
Host smart-f4a559f8-b70c-448b-9b38-e4230f52993f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304029800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1304029800
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1698215099
Short name T772
Test name
Test status
Simulation time 61386841927 ps
CPU time 279.48 seconds
Started Mar 31 03:20:54 PM PDT 24
Finished Mar 31 03:25:34 PM PDT 24
Peak memory 200492 kb
Host smart-b3e79a9e-b35c-434d-888d-0023463b950c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698215099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1698215099
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1195370508
Short name T390
Test name
Test status
Simulation time 8401884748 ps
CPU time 21.01 seconds
Started Mar 31 03:20:54 PM PDT 24
Finished Mar 31 03:21:15 PM PDT 24
Peak memory 200036 kb
Host smart-fe2ab574-1d7d-4e3d-871a-3e2b2bb12f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195370508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1195370508
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.507105252
Short name T518
Test name
Test status
Simulation time 14530221344 ps
CPU time 24.7 seconds
Started Mar 31 03:20:52 PM PDT 24
Finished Mar 31 03:21:16 PM PDT 24
Peak memory 199304 kb
Host smart-fd6de983-44bb-4992-99be-68a13ea19bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507105252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.507105252
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3331835163
Short name T596
Test name
Test status
Simulation time 13318738483 ps
CPU time 765.72 seconds
Started Mar 31 03:20:54 PM PDT 24
Finished Mar 31 03:33:40 PM PDT 24
Peak memory 200508 kb
Host smart-f6a4f0d2-c102-4303-a88b-774ed58e9e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331835163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3331835163
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4111434006
Short name T1152
Test name
Test status
Simulation time 1606625612 ps
CPU time 1.91 seconds
Started Mar 31 03:20:53 PM PDT 24
Finished Mar 31 03:20:55 PM PDT 24
Peak memory 198384 kb
Host smart-d2e3b70b-8511-43f6-a302-e06aff95f94c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111434006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4111434006
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1893064703
Short name T674
Test name
Test status
Simulation time 52796279449 ps
CPU time 28.18 seconds
Started Mar 31 03:20:52 PM PDT 24
Finished Mar 31 03:21:20 PM PDT 24
Peak memory 200536 kb
Host smart-90949f43-d6b1-4cc4-a933-8c509371b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893064703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1893064703
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2700866754
Short name T883
Test name
Test status
Simulation time 4728424585 ps
CPU time 5.17 seconds
Started Mar 31 03:20:51 PM PDT 24
Finished Mar 31 03:20:56 PM PDT 24
Peak memory 196480 kb
Host smart-c75f0811-7896-4805-b65d-fa0a2c4d03ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700866754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2700866754
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2380376439
Short name T1087
Test name
Test status
Simulation time 5763742892 ps
CPU time 17.07 seconds
Started Mar 31 03:20:47 PM PDT 24
Finished Mar 31 03:21:04 PM PDT 24
Peak memory 199664 kb
Host smart-3b2a9453-c93e-4aba-b1e2-5a564dbc0fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380376439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2380376439
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3561611218
Short name T253
Test name
Test status
Simulation time 42114859871 ps
CPU time 235.61 seconds
Started Mar 31 03:21:01 PM PDT 24
Finished Mar 31 03:24:56 PM PDT 24
Peak memory 200464 kb
Host smart-edb36399-2c1e-45c5-be15-24d47427d434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561611218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3561611218
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1902228022
Short name T1035
Test name
Test status
Simulation time 17687030902 ps
CPU time 110.84 seconds
Started Mar 31 03:21:01 PM PDT 24
Finished Mar 31 03:22:51 PM PDT 24
Peak memory 217280 kb
Host smart-875f861b-4db5-4a5c-b2da-4eb33de062fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902228022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1902228022
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3877280976
Short name T907
Test name
Test status
Simulation time 1766280454 ps
CPU time 2.1 seconds
Started Mar 31 03:20:53 PM PDT 24
Finished Mar 31 03:20:55 PM PDT 24
Peak memory 198880 kb
Host smart-6b519877-ce20-4b9b-999a-a002b81e4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877280976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3877280976
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.983487479
Short name T415
Test name
Test status
Simulation time 216967001265 ps
CPU time 25.5 seconds
Started Mar 31 03:20:46 PM PDT 24
Finished Mar 31 03:21:11 PM PDT 24
Peak memory 200480 kb
Host smart-1778388a-c7ed-4cb0-bb60-7253941d7e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983487479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.983487479
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3090616721
Short name T1025
Test name
Test status
Simulation time 100771437383 ps
CPU time 140.05 seconds
Started Mar 31 03:27:51 PM PDT 24
Finished Mar 31 03:30:11 PM PDT 24
Peak memory 200532 kb
Host smart-8e996c31-f9d2-4bac-aaf4-3bc756b4aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090616721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3090616721
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1915282918
Short name T669
Test name
Test status
Simulation time 102750360935 ps
CPU time 46.61 seconds
Started Mar 31 03:28:01 PM PDT 24
Finished Mar 31 03:28:48 PM PDT 24
Peak memory 200496 kb
Host smart-92cd2ef0-ab0c-4f34-aa9c-690a9677c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915282918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1915282918
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2318099749
Short name T572
Test name
Test status
Simulation time 15959375137 ps
CPU time 24.5 seconds
Started Mar 31 03:28:00 PM PDT 24
Finished Mar 31 03:28:24 PM PDT 24
Peak memory 200480 kb
Host smart-822c2218-cd0a-4013-bbc7-df97f2e519d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318099749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2318099749
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.683895186
Short name T682
Test name
Test status
Simulation time 28395083205 ps
CPU time 33.8 seconds
Started Mar 31 03:27:59 PM PDT 24
Finished Mar 31 03:28:33 PM PDT 24
Peak memory 200300 kb
Host smart-8aace12b-db6a-4dc7-b766-307aea953e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683895186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.683895186
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1417321096
Short name T258
Test name
Test status
Simulation time 58238505682 ps
CPU time 96.72 seconds
Started Mar 31 03:28:00 PM PDT 24
Finished Mar 31 03:29:36 PM PDT 24
Peak memory 200532 kb
Host smart-8251ac6a-0ae9-4ce7-ba6b-4cfb17a5ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417321096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1417321096
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3956071299
Short name T678
Test name
Test status
Simulation time 19509616249 ps
CPU time 34.67 seconds
Started Mar 31 03:28:00 PM PDT 24
Finished Mar 31 03:28:35 PM PDT 24
Peak memory 200500 kb
Host smart-810ce7e7-2824-49d1-b3ac-9fb9337c1d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956071299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3956071299
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3884081563
Short name T169
Test name
Test status
Simulation time 112108843142 ps
CPU time 90.86 seconds
Started Mar 31 03:28:01 PM PDT 24
Finished Mar 31 03:29:32 PM PDT 24
Peak memory 200400 kb
Host smart-4ec7e0c9-7f67-4009-a504-abb32f32e72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884081563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3884081563
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2484294186
Short name T616
Test name
Test status
Simulation time 63067048431 ps
CPU time 51.37 seconds
Started Mar 31 03:28:02 PM PDT 24
Finished Mar 31 03:28:53 PM PDT 24
Peak memory 200464 kb
Host smart-bcc7cd47-d5ba-4fcf-ac52-47c5e0976a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484294186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2484294186
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3107772160
Short name T98
Test name
Test status
Simulation time 15387737423 ps
CPU time 39.9 seconds
Started Mar 31 03:28:00 PM PDT 24
Finished Mar 31 03:28:40 PM PDT 24
Peak memory 200520 kb
Host smart-318c7e6d-1012-4643-ad3e-0c7563fabebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107772160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3107772160
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3929813370
Short name T944
Test name
Test status
Simulation time 24276344 ps
CPU time 0.54 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:21:11 PM PDT 24
Peak memory 195884 kb
Host smart-f9f093d4-4d92-4593-9490-8d75b59d7def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929813370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3929813370
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.23404836
Short name T1090
Test name
Test status
Simulation time 112525335423 ps
CPU time 167.96 seconds
Started Mar 31 03:21:05 PM PDT 24
Finished Mar 31 03:23:53 PM PDT 24
Peak memory 200484 kb
Host smart-dab2b2d4-8e0a-41b1-a215-5221836a41ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23404836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.23404836
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.360094751
Short name T1003
Test name
Test status
Simulation time 52436401409 ps
CPU time 74.09 seconds
Started Mar 31 03:21:03 PM PDT 24
Finished Mar 31 03:22:17 PM PDT 24
Peak memory 200412 kb
Host smart-4eb9cd1b-c426-481a-9ed0-6b8e6889f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360094751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.360094751
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.864795464
Short name T548
Test name
Test status
Simulation time 103725005338 ps
CPU time 173.31 seconds
Started Mar 31 03:21:04 PM PDT 24
Finished Mar 31 03:23:57 PM PDT 24
Peak memory 200204 kb
Host smart-910083f7-4b34-4f90-84c4-8004731c5623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864795464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.864795464
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.123240659
Short name T354
Test name
Test status
Simulation time 13044215772 ps
CPU time 6.19 seconds
Started Mar 31 03:21:11 PM PDT 24
Finished Mar 31 03:21:17 PM PDT 24
Peak memory 198396 kb
Host smart-55e9b4a1-c822-415c-8fa9-24246d00a71e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123240659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.123240659
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2837279841
Short name T733
Test name
Test status
Simulation time 86186670784 ps
CPU time 742.11 seconds
Started Mar 31 03:21:11 PM PDT 24
Finished Mar 31 03:33:33 PM PDT 24
Peak memory 200492 kb
Host smart-a29b6861-8d56-4bf0-8095-5595963bbb2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837279841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2837279841
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.706703255
Short name T600
Test name
Test status
Simulation time 823705937 ps
CPU time 1.97 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:21:12 PM PDT 24
Peak memory 195912 kb
Host smart-18d0729b-d661-4381-8fcd-e2b4114d85e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706703255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.706703255
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.173229493
Short name T825
Test name
Test status
Simulation time 114229698414 ps
CPU time 215.61 seconds
Started Mar 31 03:21:11 PM PDT 24
Finished Mar 31 03:24:47 PM PDT 24
Peak memory 208552 kb
Host smart-810a5656-8a69-4e6c-b80b-10da1b2985a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173229493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.173229493
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.27627488
Short name T88
Test name
Test status
Simulation time 3717278791 ps
CPU time 158.68 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:23:48 PM PDT 24
Peak memory 200464 kb
Host smart-264d48a1-e51b-449d-a54c-f6ae31241ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27627488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.27627488
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.7053730
Short name T478
Test name
Test status
Simulation time 6119240109 ps
CPU time 5.91 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:21:15 PM PDT 24
Peak memory 198568 kb
Host smart-09e40a61-8c7b-41d5-82a0-0289f0b11e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7053730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.7053730
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2753909210
Short name T117
Test name
Test status
Simulation time 80827908142 ps
CPU time 75.15 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:22:26 PM PDT 24
Peak memory 200484 kb
Host smart-f4ae2637-0430-4484-ac46-8680df930532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753909210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2753909210
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3284898087
Short name T293
Test name
Test status
Simulation time 4502031788 ps
CPU time 2.46 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:21:13 PM PDT 24
Peak memory 196528 kb
Host smart-af8d926e-c81a-4736-b91b-52c8a539b79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284898087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3284898087
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1432238922
Short name T540
Test name
Test status
Simulation time 446360101 ps
CPU time 1.4 seconds
Started Mar 31 03:21:01 PM PDT 24
Finished Mar 31 03:21:03 PM PDT 24
Peak memory 200384 kb
Host smart-6bd5698b-1376-4ad9-99ce-d329887a2df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432238922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1432238922
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1442788454
Short name T639
Test name
Test status
Simulation time 249183713964 ps
CPU time 151.95 seconds
Started Mar 31 03:21:09 PM PDT 24
Finished Mar 31 03:23:41 PM PDT 24
Peak memory 200528 kb
Host smart-df63664c-145b-469f-ab74-c100a915f330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442788454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1442788454
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1816442049
Short name T402
Test name
Test status
Simulation time 10936887214 ps
CPU time 6.34 seconds
Started Mar 31 03:21:13 PM PDT 24
Finished Mar 31 03:21:19 PM PDT 24
Peak memory 200404 kb
Host smart-65c8a815-191f-4e6b-b598-41fd01c9ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816442049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1816442049
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3989056048
Short name T826
Test name
Test status
Simulation time 81374183767 ps
CPU time 126.52 seconds
Started Mar 31 03:21:01 PM PDT 24
Finished Mar 31 03:23:08 PM PDT 24
Peak memory 200524 kb
Host smart-9154313a-310d-4b49-956d-bb67da41c52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989056048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3989056048
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.580824566
Short name T594
Test name
Test status
Simulation time 8632239069 ps
CPU time 18.02 seconds
Started Mar 31 03:28:01 PM PDT 24
Finished Mar 31 03:28:20 PM PDT 24
Peak memory 200492 kb
Host smart-7ff0eb65-7888-4754-bf95-d89add7a0bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580824566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.580824566
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2749707976
Short name T232
Test name
Test status
Simulation time 58879795268 ps
CPU time 23.28 seconds
Started Mar 31 03:28:00 PM PDT 24
Finished Mar 31 03:28:24 PM PDT 24
Peak memory 200620 kb
Host smart-dd3396e7-a198-438a-b1de-4359accfe4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749707976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2749707976
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1730984166
Short name T870
Test name
Test status
Simulation time 39661862263 ps
CPU time 28.62 seconds
Started Mar 31 03:28:01 PM PDT 24
Finished Mar 31 03:28:30 PM PDT 24
Peak memory 200492 kb
Host smart-827c06dd-41fa-4dfc-a866-fef2efc8d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730984166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1730984166
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.724428315
Short name T177
Test name
Test status
Simulation time 238208009479 ps
CPU time 34.58 seconds
Started Mar 31 03:27:58 PM PDT 24
Finished Mar 31 03:28:33 PM PDT 24
Peak memory 200324 kb
Host smart-931b88b4-fdb4-4ddb-8ff8-01cd75a0fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724428315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.724428315
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2102854421
Short name T241
Test name
Test status
Simulation time 19630315420 ps
CPU time 38.52 seconds
Started Mar 31 03:28:05 PM PDT 24
Finished Mar 31 03:28:44 PM PDT 24
Peak memory 200432 kb
Host smart-3fab4bed-a8e7-4700-abde-2e6dd9384376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102854421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2102854421
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.4011066327
Short name T271
Test name
Test status
Simulation time 106591757241 ps
CPU time 74.27 seconds
Started Mar 31 03:28:04 PM PDT 24
Finished Mar 31 03:29:18 PM PDT 24
Peak memory 200492 kb
Host smart-22019038-d679-48f1-8ba0-fa3e23ce3c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011066327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.4011066327
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2757849210
Short name T183
Test name
Test status
Simulation time 248332271090 ps
CPU time 65.06 seconds
Started Mar 31 03:28:03 PM PDT 24
Finished Mar 31 03:29:09 PM PDT 24
Peak memory 200524 kb
Host smart-00c70a66-6a1e-41a2-8378-244479caffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757849210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2757849210
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1885253454
Short name T608
Test name
Test status
Simulation time 91443024480 ps
CPU time 44.19 seconds
Started Mar 31 03:28:04 PM PDT 24
Finished Mar 31 03:28:48 PM PDT 24
Peak memory 200472 kb
Host smart-be288739-0b07-49cd-8ec0-73494d558ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885253454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1885253454
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4213055521
Short name T971
Test name
Test status
Simulation time 18697839 ps
CPU time 0.53 seconds
Started Mar 31 03:21:23 PM PDT 24
Finished Mar 31 03:21:24 PM PDT 24
Peak memory 194884 kb
Host smart-6e68abeb-92c3-430e-88df-33bc729e067b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213055521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4213055521
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.844490897
Short name T651
Test name
Test status
Simulation time 46892862437 ps
CPU time 21.31 seconds
Started Mar 31 03:21:13 PM PDT 24
Finished Mar 31 03:21:35 PM PDT 24
Peak memory 200500 kb
Host smart-c9f82239-2f83-48fd-8f19-fe495d7dfacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844490897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.844490897
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1554948783
Short name T170
Test name
Test status
Simulation time 49325854727 ps
CPU time 22.65 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:21:32 PM PDT 24
Peak memory 200468 kb
Host smart-82ab8407-43aa-4671-ba5d-3df70147eff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554948783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1554948783
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.77593521
Short name T625
Test name
Test status
Simulation time 74242838553 ps
CPU time 51.4 seconds
Started Mar 31 03:21:10 PM PDT 24
Finished Mar 31 03:22:01 PM PDT 24
Peak memory 200416 kb
Host smart-01465a47-1fce-4dd1-911a-c51794f49355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77593521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.77593521
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1542005607
Short name T525
Test name
Test status
Simulation time 27877785006 ps
CPU time 18.8 seconds
Started Mar 31 03:21:14 PM PDT 24
Finished Mar 31 03:21:33 PM PDT 24
Peak memory 200320 kb
Host smart-ec15a35a-51f6-435b-a94e-93581d4603ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542005607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1542005607
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.696033579
Short name T250
Test name
Test status
Simulation time 57396027461 ps
CPU time 270.67 seconds
Started Mar 31 03:21:20 PM PDT 24
Finished Mar 31 03:25:51 PM PDT 24
Peak memory 200500 kb
Host smart-9bb6826c-4880-4a86-9fda-8dbc56aea59a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696033579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.696033579
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2074678115
Short name T2
Test name
Test status
Simulation time 1579567917 ps
CPU time 4.9 seconds
Started Mar 31 03:21:16 PM PDT 24
Finished Mar 31 03:21:21 PM PDT 24
Peak memory 199208 kb
Host smart-80ce0d97-1fe9-415c-a0b2-3f434df23a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074678115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2074678115
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.685445360
Short name T516
Test name
Test status
Simulation time 20352142514 ps
CPU time 8.35 seconds
Started Mar 31 03:21:15 PM PDT 24
Finished Mar 31 03:21:24 PM PDT 24
Peak memory 200520 kb
Host smart-bf45e6e9-e9ba-45c0-abff-73f15bf6e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685445360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.685445360
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3546048633
Short name T629
Test name
Test status
Simulation time 38349214585 ps
CPU time 548.03 seconds
Started Mar 31 03:21:21 PM PDT 24
Finished Mar 31 03:30:30 PM PDT 24
Peak memory 200456 kb
Host smart-30e6d829-893c-4d06-8bde-16c1a98185c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546048633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3546048633
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3461798081
Short name T877
Test name
Test status
Simulation time 5202666031 ps
CPU time 44.13 seconds
Started Mar 31 03:21:09 PM PDT 24
Finished Mar 31 03:21:53 PM PDT 24
Peak memory 200480 kb
Host smart-b87b4b1d-7747-47c1-bcf3-20542f20cb78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461798081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3461798081
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1353849843
Short name T978
Test name
Test status
Simulation time 111090491013 ps
CPU time 45.67 seconds
Started Mar 31 03:21:16 PM PDT 24
Finished Mar 31 03:22:02 PM PDT 24
Peak memory 200532 kb
Host smart-72491082-3406-424a-8b6e-ef9b6307e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353849843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1353849843
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3176101029
Short name T535
Test name
Test status
Simulation time 2810832418 ps
CPU time 5.47 seconds
Started Mar 31 03:21:15 PM PDT 24
Finished Mar 31 03:21:20 PM PDT 24
Peak memory 196500 kb
Host smart-02f0679c-6d7b-45cb-9251-cae2d705c6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176101029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3176101029
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3117978962
Short name T604
Test name
Test status
Simulation time 100537451 ps
CPU time 0.89 seconds
Started Mar 31 03:21:11 PM PDT 24
Finished Mar 31 03:21:12 PM PDT 24
Peak memory 197380 kb
Host smart-b76e1839-0099-44e3-9859-42cf97761423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117978962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3117978962
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2827091282
Short name T1062
Test name
Test status
Simulation time 149457431617 ps
CPU time 396.06 seconds
Started Mar 31 03:21:23 PM PDT 24
Finished Mar 31 03:27:59 PM PDT 24
Peak memory 200476 kb
Host smart-9cf4ee88-fbb0-4352-b7f7-368dd60f0a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827091282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2827091282
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.76435234
Short name T1092
Test name
Test status
Simulation time 69050313681 ps
CPU time 681.5 seconds
Started Mar 31 03:21:20 PM PDT 24
Finished Mar 31 03:32:42 PM PDT 24
Peak memory 217236 kb
Host smart-05e5fb0d-2da6-495b-935a-5487f35dac25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76435234 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.76435234
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2561547147
Short name T1032
Test name
Test status
Simulation time 12465116065 ps
CPU time 29.12 seconds
Started Mar 31 03:21:16 PM PDT 24
Finished Mar 31 03:21:46 PM PDT 24
Peak memory 199984 kb
Host smart-c6ba5d02-ffa4-41fa-b996-4dff74be11ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561547147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2561547147
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1905145804
Short name T486
Test name
Test status
Simulation time 6965488045 ps
CPU time 12.17 seconds
Started Mar 31 03:21:13 PM PDT 24
Finished Mar 31 03:21:25 PM PDT 24
Peak memory 200476 kb
Host smart-811113fb-fce2-4c37-a82f-e5944204ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905145804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1905145804
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.732149052
Short name T837
Test name
Test status
Simulation time 135728293102 ps
CPU time 193.11 seconds
Started Mar 31 03:28:05 PM PDT 24
Finished Mar 31 03:31:18 PM PDT 24
Peak memory 200464 kb
Host smart-540a2621-6cfd-4ce4-b058-7dfe59de43b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732149052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.732149052
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1518752592
Short name T838
Test name
Test status
Simulation time 121367789339 ps
CPU time 26.13 seconds
Started Mar 31 03:28:03 PM PDT 24
Finished Mar 31 03:28:30 PM PDT 24
Peak memory 200600 kb
Host smart-2046d721-6ed9-4837-9d45-a30037be1815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518752592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1518752592
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1652234367
Short name T536
Test name
Test status
Simulation time 144505456152 ps
CPU time 216.77 seconds
Started Mar 31 03:28:05 PM PDT 24
Finished Mar 31 03:31:42 PM PDT 24
Peak memory 200468 kb
Host smart-5963325b-3228-49da-aa58-a35106e5920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652234367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1652234367
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3917806292
Short name T129
Test name
Test status
Simulation time 74433770701 ps
CPU time 108.76 seconds
Started Mar 31 03:28:02 PM PDT 24
Finished Mar 31 03:29:51 PM PDT 24
Peak memory 200472 kb
Host smart-d1e31e7b-2151-4c14-8aab-5298953b510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917806292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3917806292
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.4012042286
Short name T1050
Test name
Test status
Simulation time 136931858311 ps
CPU time 155.1 seconds
Started Mar 31 03:28:10 PM PDT 24
Finished Mar 31 03:30:45 PM PDT 24
Peak memory 200528 kb
Host smart-c0200246-7079-49b7-845a-a87e15dcfe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012042286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4012042286
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3437518681
Short name T550
Test name
Test status
Simulation time 294214190614 ps
CPU time 23.95 seconds
Started Mar 31 03:28:10 PM PDT 24
Finished Mar 31 03:28:34 PM PDT 24
Peak memory 200504 kb
Host smart-d98e0d7c-c9e0-48e6-9ab4-a48792b5a270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437518681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3437518681
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1398517701
Short name T864
Test name
Test status
Simulation time 30422619906 ps
CPU time 14.32 seconds
Started Mar 31 03:28:09 PM PDT 24
Finished Mar 31 03:28:24 PM PDT 24
Peak memory 200520 kb
Host smart-91b5e793-93a8-44a5-aa60-71e7a2547e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398517701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1398517701
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3226412140
Short name T932
Test name
Test status
Simulation time 50626011334 ps
CPU time 41.33 seconds
Started Mar 31 03:28:09 PM PDT 24
Finished Mar 31 03:28:51 PM PDT 24
Peak memory 200496 kb
Host smart-3d3a1c66-9468-4e3e-b796-2c1ccd718c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226412140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3226412140
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1791973619
Short name T1031
Test name
Test status
Simulation time 20052037163 ps
CPU time 14.13 seconds
Started Mar 31 03:28:10 PM PDT 24
Finished Mar 31 03:28:24 PM PDT 24
Peak memory 200464 kb
Host smart-673b5e64-3dc0-4045-a632-b59a26342a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791973619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1791973619
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.586710105
Short name T20
Test name
Test status
Simulation time 40225978 ps
CPU time 0.55 seconds
Started Mar 31 03:15:37 PM PDT 24
Finished Mar 31 03:15:38 PM PDT 24
Peak memory 195896 kb
Host smart-e3125d07-4bc5-461c-91f5-c14743806eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586710105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.586710105
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1244402552
Short name T900
Test name
Test status
Simulation time 61627507063 ps
CPU time 25.09 seconds
Started Mar 31 03:15:14 PM PDT 24
Finished Mar 31 03:15:39 PM PDT 24
Peak memory 200520 kb
Host smart-949ecc13-2729-4507-89ad-61639c56b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244402552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1244402552
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1801364747
Short name T983
Test name
Test status
Simulation time 45831072624 ps
CPU time 42.67 seconds
Started Mar 31 03:15:12 PM PDT 24
Finished Mar 31 03:15:54 PM PDT 24
Peak memory 200432 kb
Host smart-1464a51c-d450-4ff3-8508-ca1d737f6950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801364747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1801364747
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1949932616
Short name T33
Test name
Test status
Simulation time 74209667266 ps
CPU time 29.52 seconds
Started Mar 31 03:15:13 PM PDT 24
Finished Mar 31 03:15:43 PM PDT 24
Peak memory 200460 kb
Host smart-df4e4878-3694-4537-a65c-81892700dd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949932616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1949932616
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3377611487
Short name T1165
Test name
Test status
Simulation time 30527873360 ps
CPU time 12.15 seconds
Started Mar 31 03:15:18 PM PDT 24
Finished Mar 31 03:15:30 PM PDT 24
Peak memory 199600 kb
Host smart-dbc68eb5-e75a-4d23-9de8-67edab2901fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377611487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3377611487
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3721286786
Short name T642
Test name
Test status
Simulation time 98004881497 ps
CPU time 722.48 seconds
Started Mar 31 03:15:31 PM PDT 24
Finished Mar 31 03:27:33 PM PDT 24
Peak memory 200424 kb
Host smart-3275e62d-7550-43e4-b89e-67b33e92a312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721286786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3721286786
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2893702731
Short name T1094
Test name
Test status
Simulation time 3432634788 ps
CPU time 5.67 seconds
Started Mar 31 03:15:29 PM PDT 24
Finished Mar 31 03:15:35 PM PDT 24
Peak memory 199288 kb
Host smart-2a8e30a4-93ca-4d50-9ad2-ab232dc903a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893702731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2893702731
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.4018581206
Short name T334
Test name
Test status
Simulation time 20606364417 ps
CPU time 11.03 seconds
Started Mar 31 03:15:18 PM PDT 24
Finished Mar 31 03:15:29 PM PDT 24
Peak memory 197380 kb
Host smart-37f8c3bb-a370-4af7-9d31-765498f432e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018581206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4018581206
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1976477103
Short name T545
Test name
Test status
Simulation time 25087882855 ps
CPU time 1131.41 seconds
Started Mar 31 03:15:30 PM PDT 24
Finished Mar 31 03:34:22 PM PDT 24
Peak memory 200428 kb
Host smart-ac1657d4-6676-4350-bb2a-3512ed47bad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976477103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1976477103
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.990929454
Short name T668
Test name
Test status
Simulation time 6117293909 ps
CPU time 13.74 seconds
Started Mar 31 03:15:19 PM PDT 24
Finished Mar 31 03:15:33 PM PDT 24
Peak memory 200368 kb
Host smart-9a8563ab-324f-46ce-bb4b-3483e6d34c99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990929454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.990929454
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2387717332
Short name T961
Test name
Test status
Simulation time 160048997928 ps
CPU time 64.52 seconds
Started Mar 31 03:15:25 PM PDT 24
Finished Mar 31 03:16:29 PM PDT 24
Peak memory 200424 kb
Host smart-d204c33e-9b5f-429a-be1c-69b62ed9730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387717332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2387717332
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1890226687
Short name T808
Test name
Test status
Simulation time 5534432957 ps
CPU time 1.43 seconds
Started Mar 31 03:15:24 PM PDT 24
Finished Mar 31 03:15:26 PM PDT 24
Peak memory 196484 kb
Host smart-21397527-c982-43ae-a5ed-36c23a69d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890226687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1890226687
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1482089163
Short name T22
Test name
Test status
Simulation time 38890455 ps
CPU time 0.77 seconds
Started Mar 31 03:15:38 PM PDT 24
Finished Mar 31 03:15:38 PM PDT 24
Peak memory 218924 kb
Host smart-577b11b2-160c-4b30-b267-77c79095b177
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482089163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1482089163
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3492274743
Short name T660
Test name
Test status
Simulation time 653311886 ps
CPU time 1.38 seconds
Started Mar 31 03:15:08 PM PDT 24
Finished Mar 31 03:15:09 PM PDT 24
Peak memory 199252 kb
Host smart-9254f5c4-a3fd-4462-93d1-d8b991b9aebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492274743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3492274743
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2783578277
Short name T1075
Test name
Test status
Simulation time 414738618719 ps
CPU time 376.36 seconds
Started Mar 31 03:15:35 PM PDT 24
Finished Mar 31 03:21:52 PM PDT 24
Peak memory 200528 kb
Host smart-6a772a7d-f8a8-45a8-82a2-be35163895fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783578277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2783578277
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1350532503
Short name T428
Test name
Test status
Simulation time 63034549437 ps
CPU time 258.39 seconds
Started Mar 31 03:15:30 PM PDT 24
Finished Mar 31 03:19:49 PM PDT 24
Peak memory 216292 kb
Host smart-34c26bdf-7ca2-483e-8f7b-c20120ce9d52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350532503 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1350532503
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4152406594
Short name T966
Test name
Test status
Simulation time 396433740 ps
CPU time 1.69 seconds
Started Mar 31 03:15:25 PM PDT 24
Finished Mar 31 03:15:27 PM PDT 24
Peak memory 199796 kb
Host smart-1abed8c4-9e5d-47e2-b4ba-5cc5ad28b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152406594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4152406594
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1521556523
Short name T905
Test name
Test status
Simulation time 138376001437 ps
CPU time 396.28 seconds
Started Mar 31 03:15:13 PM PDT 24
Finished Mar 31 03:21:49 PM PDT 24
Peak memory 200508 kb
Host smart-c8131aa1-7f6a-449f-87e1-83796bc942d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521556523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1521556523
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1804772349
Short name T381
Test name
Test status
Simulation time 46467331 ps
CPU time 0.57 seconds
Started Mar 31 03:21:32 PM PDT 24
Finished Mar 31 03:21:32 PM PDT 24
Peak memory 195852 kb
Host smart-28108022-0ea0-4dde-87ca-b2bb1f656b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804772349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1804772349
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.433779323
Short name T89
Test name
Test status
Simulation time 173333347866 ps
CPU time 301.33 seconds
Started Mar 31 03:21:20 PM PDT 24
Finished Mar 31 03:26:22 PM PDT 24
Peak memory 200472 kb
Host smart-f6b500a0-3ff3-4191-ac36-523ba17d5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433779323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.433779323
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2546616846
Short name T6
Test name
Test status
Simulation time 136720236048 ps
CPU time 233.88 seconds
Started Mar 31 03:21:26 PM PDT 24
Finished Mar 31 03:25:20 PM PDT 24
Peak memory 200516 kb
Host smart-591691b0-a0c5-4a0a-b0f7-673a0c651353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546616846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2546616846
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1996145453
Short name T142
Test name
Test status
Simulation time 16566273044 ps
CPU time 15.34 seconds
Started Mar 31 03:21:25 PM PDT 24
Finished Mar 31 03:21:41 PM PDT 24
Peak memory 200516 kb
Host smart-2074befd-20f4-494f-8b25-d1c4d9367211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996145453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1996145453
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1677949887
Short name T314
Test name
Test status
Simulation time 12593212327 ps
CPU time 5.93 seconds
Started Mar 31 03:21:27 PM PDT 24
Finished Mar 31 03:21:33 PM PDT 24
Peak memory 197568 kb
Host smart-2e61fc62-2948-4ae2-9618-ccd3ed785b6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677949887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1677949887
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1228761013
Short name T778
Test name
Test status
Simulation time 135473609807 ps
CPU time 1020.87 seconds
Started Mar 31 03:21:27 PM PDT 24
Finished Mar 31 03:38:28 PM PDT 24
Peak memory 200488 kb
Host smart-f8552b1b-510c-4b62-a1c7-f52d4358f0c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228761013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1228761013
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.544871798
Short name T844
Test name
Test status
Simulation time 2114994168 ps
CPU time 7.32 seconds
Started Mar 31 03:21:29 PM PDT 24
Finished Mar 31 03:21:37 PM PDT 24
Peak memory 199068 kb
Host smart-44588902-d765-40bf-8086-35693ae276b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544871798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.544871798
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.30160989
Short name T922
Test name
Test status
Simulation time 20885761058 ps
CPU time 33.56 seconds
Started Mar 31 03:21:27 PM PDT 24
Finished Mar 31 03:22:00 PM PDT 24
Peak memory 199684 kb
Host smart-6f48fec0-6691-42c2-ae82-bdc915af72fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30160989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.30160989
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2611811802
Short name T972
Test name
Test status
Simulation time 14523732716 ps
CPU time 327.7 seconds
Started Mar 31 03:21:26 PM PDT 24
Finished Mar 31 03:26:54 PM PDT 24
Peak memory 200456 kb
Host smart-9de6b271-17ef-468c-a076-2b675e9f26ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611811802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2611811802
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.748261646
Short name T341
Test name
Test status
Simulation time 2849527661 ps
CPU time 5.08 seconds
Started Mar 31 03:21:25 PM PDT 24
Finished Mar 31 03:21:31 PM PDT 24
Peak memory 198548 kb
Host smart-5ec0ce42-1d79-45d1-9ed7-e66cb5e631d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748261646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.748261646
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1608670295
Short name T931
Test name
Test status
Simulation time 25356819200 ps
CPU time 40.46 seconds
Started Mar 31 03:21:27 PM PDT 24
Finished Mar 31 03:22:08 PM PDT 24
Peak memory 200432 kb
Host smart-0018280f-b84d-4942-b2eb-c068844875fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608670295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1608670295
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.496224464
Short name T816
Test name
Test status
Simulation time 1662912754 ps
CPU time 3.45 seconds
Started Mar 31 03:21:25 PM PDT 24
Finished Mar 31 03:21:29 PM PDT 24
Peak memory 195868 kb
Host smart-b5e0f316-8dd6-44dd-b58b-6b93a2d5133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496224464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.496224464
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1635815462
Short name T340
Test name
Test status
Simulation time 5307322834 ps
CPU time 7.93 seconds
Started Mar 31 03:21:20 PM PDT 24
Finished Mar 31 03:21:28 PM PDT 24
Peak memory 200180 kb
Host smart-9a6e6f41-170f-410f-a09d-c7aeb7d95ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635815462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1635815462
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2953363821
Short name T671
Test name
Test status
Simulation time 154086662161 ps
CPU time 63.49 seconds
Started Mar 31 03:21:33 PM PDT 24
Finished Mar 31 03:22:36 PM PDT 24
Peak memory 200492 kb
Host smart-ce7db869-16c1-42e5-911f-902d66c56ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953363821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2953363821
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.883962244
Short name T302
Test name
Test status
Simulation time 28459624423 ps
CPU time 153.35 seconds
Started Mar 31 03:21:33 PM PDT 24
Finished Mar 31 03:24:07 PM PDT 24
Peak memory 208888 kb
Host smart-abbf7b10-40f2-46bd-9ec7-62a11eeaec18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883962244 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.883962244
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2259434321
Short name T968
Test name
Test status
Simulation time 6087143988 ps
CPU time 20.88 seconds
Started Mar 31 03:21:26 PM PDT 24
Finished Mar 31 03:21:48 PM PDT 24
Peak memory 200380 kb
Host smart-809930a0-b026-459e-9a00-e9f6c4123aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259434321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2259434321
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3414733027
Short name T676
Test name
Test status
Simulation time 32157857138 ps
CPU time 12.91 seconds
Started Mar 31 03:21:23 PM PDT 24
Finished Mar 31 03:21:37 PM PDT 24
Peak memory 200276 kb
Host smart-55300ba2-7ebc-4964-b02b-5f3653abdbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414733027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3414733027
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.777351391
Short name T1172
Test name
Test status
Simulation time 104137543 ps
CPU time 0.56 seconds
Started Mar 31 03:21:37 PM PDT 24
Finished Mar 31 03:21:38 PM PDT 24
Peak memory 195832 kb
Host smart-f80889b0-94b8-47bf-9667-875eada59892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777351391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.777351391
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3574716820
Short name T896
Test name
Test status
Simulation time 81302717233 ps
CPU time 28.19 seconds
Started Mar 31 03:21:31 PM PDT 24
Finished Mar 31 03:22:00 PM PDT 24
Peak memory 200536 kb
Host smart-385381ef-61d4-4406-b684-f169a222d74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574716820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3574716820
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3641801592
Short name T306
Test name
Test status
Simulation time 32805758714 ps
CPU time 24.65 seconds
Started Mar 31 03:21:33 PM PDT 24
Finished Mar 31 03:21:57 PM PDT 24
Peak memory 200504 kb
Host smart-4e8d7499-5920-4e8e-bd60-4fc216c135f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641801592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3641801592
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.1965340053
Short name T461
Test name
Test status
Simulation time 28377610182 ps
CPU time 4.34 seconds
Started Mar 31 03:21:33 PM PDT 24
Finished Mar 31 03:21:37 PM PDT 24
Peak memory 198132 kb
Host smart-2350fd36-7a3b-4ea7-822c-4b0ffa1d2168
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965340053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1965340053
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1235947146
Short name T380
Test name
Test status
Simulation time 109282386679 ps
CPU time 802.78 seconds
Started Mar 31 03:21:37 PM PDT 24
Finished Mar 31 03:35:01 PM PDT 24
Peak memory 200460 kb
Host smart-00e28167-7739-4733-ad50-2efc73ba5a09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235947146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1235947146
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2833035511
Short name T954
Test name
Test status
Simulation time 8536939537 ps
CPU time 5.43 seconds
Started Mar 31 03:21:37 PM PDT 24
Finished Mar 31 03:21:42 PM PDT 24
Peak memory 200380 kb
Host smart-e556fa88-4be6-4d3d-9d8d-2b1139ba2cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833035511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2833035511
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3634196184
Short name T1178
Test name
Test status
Simulation time 42295157891 ps
CPU time 18.5 seconds
Started Mar 31 03:21:36 PM PDT 24
Finished Mar 31 03:21:55 PM PDT 24
Peak memory 200832 kb
Host smart-2b0e4c38-fdd5-4e82-b610-21fbb335bd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634196184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3634196184
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.185415319
Short name T392
Test name
Test status
Simulation time 14853900508 ps
CPU time 98 seconds
Started Mar 31 03:21:36 PM PDT 24
Finished Mar 31 03:23:15 PM PDT 24
Peak memory 200528 kb
Host smart-317371c4-39b7-4aef-8d08-e64644eacca8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185415319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.185415319
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2460334966
Short name T1021
Test name
Test status
Simulation time 3936794696 ps
CPU time 32.53 seconds
Started Mar 31 03:21:31 PM PDT 24
Finished Mar 31 03:22:03 PM PDT 24
Peak memory 199092 kb
Host smart-fa362505-e210-49bf-b54e-e9a9514029e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460334966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2460334966
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1147744948
Short name T551
Test name
Test status
Simulation time 26156139800 ps
CPU time 43.75 seconds
Started Mar 31 03:21:39 PM PDT 24
Finished Mar 31 03:22:23 PM PDT 24
Peak memory 200444 kb
Host smart-d771941d-acb2-4c59-98d4-1c76778645af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147744948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1147744948
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1276222748
Short name T509
Test name
Test status
Simulation time 1884131742 ps
CPU time 1.28 seconds
Started Mar 31 03:21:35 PM PDT 24
Finished Mar 31 03:21:36 PM PDT 24
Peak memory 195868 kb
Host smart-f82a8387-7d14-4adb-9926-fa29c00be41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276222748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1276222748
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1227489181
Short name T347
Test name
Test status
Simulation time 5844101727 ps
CPU time 6.1 seconds
Started Mar 31 03:21:32 PM PDT 24
Finished Mar 31 03:21:39 PM PDT 24
Peak memory 200008 kb
Host smart-a09839e2-1b45-442e-9ff0-0b7638ed8845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227489181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1227489181
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3026675634
Short name T262
Test name
Test status
Simulation time 169100987171 ps
CPU time 258.32 seconds
Started Mar 31 03:21:38 PM PDT 24
Finished Mar 31 03:25:56 PM PDT 24
Peak memory 200400 kb
Host smart-de71edee-7bf1-4b2e-9101-fbd3b57765c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026675634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3026675634
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2435541387
Short name T434
Test name
Test status
Simulation time 273390831198 ps
CPU time 970.82 seconds
Started Mar 31 03:21:37 PM PDT 24
Finished Mar 31 03:37:49 PM PDT 24
Peak memory 217272 kb
Host smart-822a8f06-8909-49b4-b09b-ce706d1c195a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435541387 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2435541387
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1930893739
Short name T519
Test name
Test status
Simulation time 750912046 ps
CPU time 2.28 seconds
Started Mar 31 03:21:38 PM PDT 24
Finished Mar 31 03:21:41 PM PDT 24
Peak memory 198844 kb
Host smart-55e11ccb-9b28-4e86-bce6-cea6a6a97a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930893739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1930893739
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3247373688
Short name T357
Test name
Test status
Simulation time 65855778203 ps
CPU time 39.85 seconds
Started Mar 31 03:21:33 PM PDT 24
Finished Mar 31 03:22:13 PM PDT 24
Peak memory 200428 kb
Host smart-305d791e-2d6c-4fc1-84f1-749a01679f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247373688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3247373688
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1516227847
Short name T343
Test name
Test status
Simulation time 52151186 ps
CPU time 0.55 seconds
Started Mar 31 03:21:49 PM PDT 24
Finished Mar 31 03:21:50 PM PDT 24
Peak memory 195900 kb
Host smart-60bb42f8-a3fe-4d87-a4b7-253b5623654a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516227847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1516227847
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3791384484
Short name T1146
Test name
Test status
Simulation time 82672334400 ps
CPU time 133.99 seconds
Started Mar 31 03:21:38 PM PDT 24
Finished Mar 31 03:23:52 PM PDT 24
Peak memory 200432 kb
Host smart-1b188225-4d8f-48e8-95dc-a94d312b1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791384484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3791384484
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3191405363
Short name T469
Test name
Test status
Simulation time 98307298408 ps
CPU time 35.5 seconds
Started Mar 31 03:21:38 PM PDT 24
Finished Mar 31 03:22:14 PM PDT 24
Peak memory 200492 kb
Host smart-80ef0472-f794-4c55-bcae-9f491fc0528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191405363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3191405363
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1154423521
Short name T206
Test name
Test status
Simulation time 75096319681 ps
CPU time 16.91 seconds
Started Mar 31 03:21:37 PM PDT 24
Finished Mar 31 03:21:54 PM PDT 24
Peak memory 200476 kb
Host smart-5d0b2576-d402-4a33-b6e6-6051ab0ac987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154423521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1154423521
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.4023780591
Short name T517
Test name
Test status
Simulation time 64157826458 ps
CPU time 200.55 seconds
Started Mar 31 03:21:45 PM PDT 24
Finished Mar 31 03:25:05 PM PDT 24
Peak memory 200504 kb
Host smart-568f1dd1-6c0e-4cdc-ab91-5f85a5028d08
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023780591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4023780591
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.543479597
Short name T581
Test name
Test status
Simulation time 87892757484 ps
CPU time 626.71 seconds
Started Mar 31 03:21:50 PM PDT 24
Finished Mar 31 03:32:17 PM PDT 24
Peak memory 200508 kb
Host smart-e2ec4bcd-6323-4b77-ba97-34facf152d5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543479597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.543479597
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3004167554
Short name T1128
Test name
Test status
Simulation time 2811195974 ps
CPU time 3.47 seconds
Started Mar 31 03:21:47 PM PDT 24
Finished Mar 31 03:21:51 PM PDT 24
Peak memory 199144 kb
Host smart-86ca1c21-5ddf-4629-8dc1-058b15264b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004167554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3004167554
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3078708300
Short name T308
Test name
Test status
Simulation time 41808129090 ps
CPU time 29.76 seconds
Started Mar 31 03:21:44 PM PDT 24
Finished Mar 31 03:22:14 PM PDT 24
Peak memory 200732 kb
Host smart-f8e031a5-e9fe-4021-839e-705d0ed84ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078708300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3078708300
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2806424743
Short name T94
Test name
Test status
Simulation time 20058849318 ps
CPU time 255.68 seconds
Started Mar 31 03:21:48 PM PDT 24
Finished Mar 31 03:26:04 PM PDT 24
Peak memory 200472 kb
Host smart-a85cd84e-8fda-4d21-abc6-d478a120e74f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806424743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2806424743
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2392302910
Short name T948
Test name
Test status
Simulation time 4771569745 ps
CPU time 11.1 seconds
Started Mar 31 03:21:45 PM PDT 24
Finished Mar 31 03:21:56 PM PDT 24
Peak memory 198752 kb
Host smart-6327ebe4-5710-4fde-ba29-af5fe28e0a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392302910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2392302910
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3833989077
Short name T1058
Test name
Test status
Simulation time 167799579240 ps
CPU time 128.17 seconds
Started Mar 31 03:21:43 PM PDT 24
Finished Mar 31 03:23:51 PM PDT 24
Peak memory 200496 kb
Host smart-b0688c08-8bc8-4d70-b01a-4bfa0d8dbd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833989077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3833989077
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3775105952
Short name T452
Test name
Test status
Simulation time 450487461 ps
CPU time 1.03 seconds
Started Mar 31 03:21:43 PM PDT 24
Finished Mar 31 03:21:44 PM PDT 24
Peak memory 195856 kb
Host smart-7df465a0-da89-44cf-89ee-ec1bbc62134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775105952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3775105952
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3683212438
Short name T753
Test name
Test status
Simulation time 5901460914 ps
CPU time 18.13 seconds
Started Mar 31 03:21:38 PM PDT 24
Finished Mar 31 03:21:57 PM PDT 24
Peak memory 200396 kb
Host smart-504a3fff-f293-47a4-a9ab-7a890c63c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683212438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3683212438
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3713826812
Short name T1105
Test name
Test status
Simulation time 827013793 ps
CPU time 1.42 seconds
Started Mar 31 03:21:50 PM PDT 24
Finished Mar 31 03:21:51 PM PDT 24
Peak memory 199168 kb
Host smart-873b1e9b-33b5-4874-9763-6ff29eb01a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713826812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3713826812
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2731542768
Short name T295
Test name
Test status
Simulation time 82435776181 ps
CPU time 10.21 seconds
Started Mar 31 03:21:38 PM PDT 24
Finished Mar 31 03:21:48 PM PDT 24
Peak memory 200496 kb
Host smart-50f44fd6-56dc-44d0-a6fb-ab37896390e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731542768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2731542768
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3719081659
Short name T435
Test name
Test status
Simulation time 11872758 ps
CPU time 0.58 seconds
Started Mar 31 03:22:02 PM PDT 24
Finished Mar 31 03:22:03 PM PDT 24
Peak memory 195852 kb
Host smart-4b0af594-115e-4bee-8d33-ff728b168bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719081659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3719081659
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.190704001
Short name T405
Test name
Test status
Simulation time 26379330506 ps
CPU time 42.15 seconds
Started Mar 31 03:21:48 PM PDT 24
Finished Mar 31 03:22:30 PM PDT 24
Peak memory 200460 kb
Host smart-e4aa09ef-1def-438b-b194-bc450176e040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190704001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.190704001
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3825197733
Short name T809
Test name
Test status
Simulation time 19404644223 ps
CPU time 29.75 seconds
Started Mar 31 03:21:48 PM PDT 24
Finished Mar 31 03:22:18 PM PDT 24
Peak memory 200468 kb
Host smart-6863f475-1272-4e58-934c-614207500995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825197733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3825197733
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_intr.2515931057
Short name T1132
Test name
Test status
Simulation time 17172470430 ps
CPU time 7.65 seconds
Started Mar 31 03:21:58 PM PDT 24
Finished Mar 31 03:22:06 PM PDT 24
Peak memory 199016 kb
Host smart-6911bbab-167a-4290-b963-79fe895e7ef0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515931057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2515931057
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1551831186
Short name T746
Test name
Test status
Simulation time 210345028081 ps
CPU time 254.52 seconds
Started Mar 31 03:21:55 PM PDT 24
Finished Mar 31 03:26:10 PM PDT 24
Peak memory 200436 kb
Host smart-4862df2d-63ac-4f02-b5cb-9704260ba4c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551831186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1551831186
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1683679245
Short name T985
Test name
Test status
Simulation time 616194137 ps
CPU time 1.48 seconds
Started Mar 31 03:21:56 PM PDT 24
Finished Mar 31 03:21:58 PM PDT 24
Peak memory 195944 kb
Host smart-3e93bee6-7116-404d-92ee-bd0753c95ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683679245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1683679245
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1808895066
Short name T854
Test name
Test status
Simulation time 104078896550 ps
CPU time 86.38 seconds
Started Mar 31 03:21:55 PM PDT 24
Finished Mar 31 03:23:22 PM PDT 24
Peak memory 200820 kb
Host smart-a79d55ee-ca1b-41de-b688-bc3338f0dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808895066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1808895066
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.4271965646
Short name T737
Test name
Test status
Simulation time 7201745647 ps
CPU time 435.65 seconds
Started Mar 31 03:21:56 PM PDT 24
Finished Mar 31 03:29:12 PM PDT 24
Peak memory 200408 kb
Host smart-bd0f28b3-b44b-4fcf-86b9-6c4a01d37b93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271965646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.4271965646
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2722398920
Short name T999
Test name
Test status
Simulation time 5401908360 ps
CPU time 12.84 seconds
Started Mar 31 03:21:57 PM PDT 24
Finished Mar 31 03:22:12 PM PDT 24
Peak memory 198676 kb
Host smart-937ef059-fb14-48ff-b826-5f45cef5db51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722398920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2722398920
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3644896149
Short name T394
Test name
Test status
Simulation time 27804534195 ps
CPU time 18.32 seconds
Started Mar 31 03:21:58 PM PDT 24
Finished Mar 31 03:22:17 PM PDT 24
Peak memory 200504 kb
Host smart-acb6f24e-63bb-4ff2-989b-723cec034492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644896149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3644896149
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.828873511
Short name T497
Test name
Test status
Simulation time 626037447 ps
CPU time 1.51 seconds
Started Mar 31 03:21:55 PM PDT 24
Finished Mar 31 03:21:57 PM PDT 24
Peak memory 195868 kb
Host smart-5493dda9-f88c-4bef-8315-0e316e7a9afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828873511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.828873511
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2213019998
Short name T396
Test name
Test status
Simulation time 652845052 ps
CPU time 2.62 seconds
Started Mar 31 03:21:48 PM PDT 24
Finished Mar 31 03:21:51 PM PDT 24
Peak memory 198956 kb
Host smart-21ef2f0e-7539-4ff5-bc7a-8cbb3f59d6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213019998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2213019998
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.616895862
Short name T397
Test name
Test status
Simulation time 191769099452 ps
CPU time 808.33 seconds
Started Mar 31 03:22:02 PM PDT 24
Finished Mar 31 03:35:31 PM PDT 24
Peak memory 200508 kb
Host smart-eaae9a21-25b5-4188-8534-a12bedcbd148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616895862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.616895862
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.4181673886
Short name T952
Test name
Test status
Simulation time 75468438613 ps
CPU time 881.27 seconds
Started Mar 31 03:21:54 PM PDT 24
Finished Mar 31 03:36:36 PM PDT 24
Peak memory 217272 kb
Host smart-15e94058-23fd-4006-9dbd-6b503c0b908d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181673886 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.4181673886
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1532543959
Short name T680
Test name
Test status
Simulation time 7082837031 ps
CPU time 17.08 seconds
Started Mar 31 03:21:58 PM PDT 24
Finished Mar 31 03:22:16 PM PDT 24
Peak memory 200448 kb
Host smart-bd9a88fa-ee5f-4c34-b81b-53107a42671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532543959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1532543959
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.459224534
Short name T807
Test name
Test status
Simulation time 52497795909 ps
CPU time 125.5 seconds
Started Mar 31 03:21:48 PM PDT 24
Finished Mar 31 03:23:54 PM PDT 24
Peak memory 200532 kb
Host smart-86e90f8d-c5d2-4c5b-aa1f-92ed4c963892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459224534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.459224534
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3721057723
Short name T897
Test name
Test status
Simulation time 21150034 ps
CPU time 0.56 seconds
Started Mar 31 03:22:11 PM PDT 24
Finished Mar 31 03:22:12 PM PDT 24
Peak memory 195904 kb
Host smart-e29a7d06-48d0-4f20-b7a0-195905c0aebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721057723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3721057723
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2839495720
Short name T279
Test name
Test status
Simulation time 126170438900 ps
CPU time 50.1 seconds
Started Mar 31 03:22:03 PM PDT 24
Finished Mar 31 03:22:53 PM PDT 24
Peak memory 200712 kb
Host smart-6d3c97ec-6fbe-41f1-9c5a-e08a9d0319d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839495720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2839495720
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3293276203
Short name T780
Test name
Test status
Simulation time 215774378141 ps
CPU time 84.47 seconds
Started Mar 31 03:22:02 PM PDT 24
Finished Mar 31 03:23:26 PM PDT 24
Peak memory 200660 kb
Host smart-1a2f7c9c-02aa-4522-8643-2af73e3f7d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293276203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3293276203
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.688590453
Short name T823
Test name
Test status
Simulation time 39724692823 ps
CPU time 15.26 seconds
Started Mar 31 03:22:04 PM PDT 24
Finished Mar 31 03:22:19 PM PDT 24
Peak memory 200496 kb
Host smart-f3e242b0-57c2-4085-84df-24b2a730bdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688590453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.688590453
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.704191890
Short name T322
Test name
Test status
Simulation time 33339281360 ps
CPU time 47.79 seconds
Started Mar 31 03:22:07 PM PDT 24
Finished Mar 31 03:22:56 PM PDT 24
Peak memory 200444 kb
Host smart-692af8e7-c97a-4857-bd8e-2a77b0dbb070
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704191890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.704191890
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2680760684
Short name T8
Test name
Test status
Simulation time 178599819271 ps
CPU time 234.26 seconds
Started Mar 31 03:22:07 PM PDT 24
Finished Mar 31 03:26:01 PM PDT 24
Peak memory 200448 kb
Host smart-8b33f97e-b446-49b1-a070-583442de8047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2680760684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2680760684
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3103276927
Short name T1099
Test name
Test status
Simulation time 2425993713 ps
CPU time 2.99 seconds
Started Mar 31 03:22:06 PM PDT 24
Finished Mar 31 03:22:09 PM PDT 24
Peak memory 199256 kb
Host smart-3d3950f8-385b-49c4-9e3c-a578fb1f8c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103276927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3103276927
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.465364246
Short name T473
Test name
Test status
Simulation time 34368822829 ps
CPU time 25.18 seconds
Started Mar 31 03:22:08 PM PDT 24
Finished Mar 31 03:22:33 PM PDT 24
Peak memory 198968 kb
Host smart-d23743be-6cd4-4bc7-96d8-761724138b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465364246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.465364246
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1118751989
Short name T1012
Test name
Test status
Simulation time 17056137969 ps
CPU time 880.73 seconds
Started Mar 31 03:22:07 PM PDT 24
Finished Mar 31 03:36:48 PM PDT 24
Peak memory 200472 kb
Host smart-5a284b17-ecec-4719-86b7-c345c0d043d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118751989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1118751989
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3175990905
Short name T645
Test name
Test status
Simulation time 3372497681 ps
CPU time 2.33 seconds
Started Mar 31 03:22:08 PM PDT 24
Finished Mar 31 03:22:10 PM PDT 24
Peak memory 198660 kb
Host smart-397cd48c-955d-4945-97e3-1fc2949cf1d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175990905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3175990905
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2727591068
Short name T915
Test name
Test status
Simulation time 297507851337 ps
CPU time 221.93 seconds
Started Mar 31 03:22:06 PM PDT 24
Finished Mar 31 03:25:49 PM PDT 24
Peak memory 200484 kb
Host smart-6580e9fc-296f-40c5-a635-bd05e6db27b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727591068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2727591068
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2486786751
Short name T973
Test name
Test status
Simulation time 3351309516 ps
CPU time 3.16 seconds
Started Mar 31 03:22:07 PM PDT 24
Finished Mar 31 03:22:10 PM PDT 24
Peak memory 196956 kb
Host smart-c657ee61-fa91-418b-a6c8-ed54908cef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486786751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2486786751
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.812829306
Short name T362
Test name
Test status
Simulation time 613942339 ps
CPU time 0.98 seconds
Started Mar 31 03:22:01 PM PDT 24
Finished Mar 31 03:22:02 PM PDT 24
Peak memory 198836 kb
Host smart-caa6f9a1-f102-438d-abfa-4bf6d827cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812829306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.812829306
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1280749963
Short name T919
Test name
Test status
Simulation time 553530949088 ps
CPU time 328.46 seconds
Started Mar 31 03:22:08 PM PDT 24
Finished Mar 31 03:27:36 PM PDT 24
Peak memory 209016 kb
Host smart-c04f9e72-58b0-4d4f-a01f-a939fdab9f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280749963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1280749963
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.473363589
Short name T661
Test name
Test status
Simulation time 14413703627 ps
CPU time 257.99 seconds
Started Mar 31 03:22:07 PM PDT 24
Finished Mar 31 03:26:25 PM PDT 24
Peak memory 217232 kb
Host smart-6610a85c-abfd-425d-9b24-893727794875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473363589 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.473363589
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3574039669
Short name T1136
Test name
Test status
Simulation time 6296022863 ps
CPU time 14.95 seconds
Started Mar 31 03:22:07 PM PDT 24
Finished Mar 31 03:22:22 PM PDT 24
Peak memory 200244 kb
Host smart-f88cf725-e46d-4278-a6cb-0bc0b2cb3126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574039669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3574039669
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.4226678884
Short name T508
Test name
Test status
Simulation time 48441894556 ps
CPU time 34.48 seconds
Started Mar 31 03:22:02 PM PDT 24
Finished Mar 31 03:22:36 PM PDT 24
Peak memory 200464 kb
Host smart-986dfa8c-253d-4845-b01b-2df6d7113415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226678884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4226678884
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2499313943
Short name T350
Test name
Test status
Simulation time 19346612 ps
CPU time 0.54 seconds
Started Mar 31 03:22:17 PM PDT 24
Finished Mar 31 03:22:18 PM PDT 24
Peak memory 195864 kb
Host smart-2eb88584-7362-4baf-82fb-34bc7d080059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499313943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2499313943
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1107011471
Short name T703
Test name
Test status
Simulation time 186106953120 ps
CPU time 295.29 seconds
Started Mar 31 03:22:12 PM PDT 24
Finished Mar 31 03:27:08 PM PDT 24
Peak memory 200420 kb
Host smart-6c083fa8-9388-44a8-9992-17602dc0aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107011471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1107011471
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1732844145
Short name T893
Test name
Test status
Simulation time 139006117681 ps
CPU time 19.84 seconds
Started Mar 31 03:22:12 PM PDT 24
Finished Mar 31 03:22:32 PM PDT 24
Peak memory 200476 kb
Host smart-b31f2bf9-58ee-444a-9453-c8956bffc068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732844145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1732844145
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3118597050
Short name T612
Test name
Test status
Simulation time 289253973035 ps
CPU time 122.04 seconds
Started Mar 31 03:22:16 PM PDT 24
Finished Mar 31 03:24:18 PM PDT 24
Peak memory 200436 kb
Host smart-8c116fac-08f8-4c8a-b243-97e45d71abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118597050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3118597050
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1582059428
Short name T725
Test name
Test status
Simulation time 71910375150 ps
CPU time 26.89 seconds
Started Mar 31 03:22:11 PM PDT 24
Finished Mar 31 03:22:38 PM PDT 24
Peak memory 197068 kb
Host smart-62a46eaf-2a5f-4a8d-b420-be4d6feea830
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582059428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1582059428
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.784524871
Short name T528
Test name
Test status
Simulation time 149062102525 ps
CPU time 318.91 seconds
Started Mar 31 03:22:18 PM PDT 24
Finished Mar 31 03:27:37 PM PDT 24
Peak memory 200412 kb
Host smart-3ff5555d-919f-4dea-a43f-ee553d9d9799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784524871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.784524871
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.735260940
Short name T886
Test name
Test status
Simulation time 4681657270 ps
CPU time 4.67 seconds
Started Mar 31 03:22:18 PM PDT 24
Finished Mar 31 03:22:22 PM PDT 24
Peak memory 197900 kb
Host smart-c5a57471-db0a-46b9-b1ca-c3262a49f46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735260940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.735260940
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.346519506
Short name T248
Test name
Test status
Simulation time 140668916678 ps
CPU time 114.87 seconds
Started Mar 31 03:22:11 PM PDT 24
Finished Mar 31 03:24:06 PM PDT 24
Peak memory 200696 kb
Host smart-d32145ba-a8df-452b-b1c4-f93b940d43e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346519506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.346519506
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3076445646
Short name T820
Test name
Test status
Simulation time 16961167060 ps
CPU time 100.68 seconds
Started Mar 31 03:22:18 PM PDT 24
Finished Mar 31 03:23:59 PM PDT 24
Peak memory 200488 kb
Host smart-e0f7df84-8710-440b-9088-488105a7063a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076445646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3076445646
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2772498331
Short name T506
Test name
Test status
Simulation time 4828365966 ps
CPU time 12.24 seconds
Started Mar 31 03:22:12 PM PDT 24
Finished Mar 31 03:22:24 PM PDT 24
Peak memory 199984 kb
Host smart-c37ebe4d-6f41-48e6-8cc3-aebfa8ede8ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772498331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2772498331
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3758080815
Short name T466
Test name
Test status
Simulation time 58703943495 ps
CPU time 22.17 seconds
Started Mar 31 03:22:12 PM PDT 24
Finished Mar 31 03:22:34 PM PDT 24
Peak memory 200280 kb
Host smart-029823b5-5476-4f8a-9125-57e7df9dbc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758080815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3758080815
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1626166877
Short name T342
Test name
Test status
Simulation time 2547407411 ps
CPU time 4.75 seconds
Started Mar 31 03:22:12 PM PDT 24
Finished Mar 31 03:22:17 PM PDT 24
Peak memory 196236 kb
Host smart-63873faf-9b60-4041-85fc-2a1df583f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626166877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1626166877
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3983747385
Short name T538
Test name
Test status
Simulation time 506618403 ps
CPU time 1.07 seconds
Started Mar 31 03:22:11 PM PDT 24
Finished Mar 31 03:22:12 PM PDT 24
Peak memory 199324 kb
Host smart-6690e8b9-e083-4a9f-92dd-f99be6937d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983747385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3983747385
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1036552314
Short name T162
Test name
Test status
Simulation time 315267775921 ps
CPU time 174.09 seconds
Started Mar 31 03:22:19 PM PDT 24
Finished Mar 31 03:25:14 PM PDT 24
Peak memory 200520 kb
Host smart-b96685ca-a315-492b-9a81-8b36b4217adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036552314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1036552314
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.811649160
Short name T814
Test name
Test status
Simulation time 72283663739 ps
CPU time 724.8 seconds
Started Mar 31 03:22:17 PM PDT 24
Finished Mar 31 03:34:23 PM PDT 24
Peak memory 217276 kb
Host smart-d4db6752-4906-4b13-9ada-e8a3096c900c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811649160 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.811649160
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2367522288
Short name T266
Test name
Test status
Simulation time 986243134 ps
CPU time 1.56 seconds
Started Mar 31 03:22:19 PM PDT 24
Finished Mar 31 03:22:21 PM PDT 24
Peak memory 198840 kb
Host smart-4e01258e-9357-47e9-9951-08fc8c56e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367522288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2367522288
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2553099294
Short name T1051
Test name
Test status
Simulation time 24920045303 ps
CPU time 98.99 seconds
Started Mar 31 03:22:11 PM PDT 24
Finished Mar 31 03:23:50 PM PDT 24
Peak memory 200416 kb
Host smart-bab173ca-431b-4694-939e-535b691c08be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553099294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2553099294
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.122915921
Short name T375
Test name
Test status
Simulation time 13943229 ps
CPU time 0.56 seconds
Started Mar 31 03:22:31 PM PDT 24
Finished Mar 31 03:22:31 PM PDT 24
Peak memory 194880 kb
Host smart-8214cec5-b81c-4135-ba73-e09b19a6b44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122915921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.122915921
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.282832679
Short name T840
Test name
Test status
Simulation time 47545413275 ps
CPU time 26.15 seconds
Started Mar 31 03:22:22 PM PDT 24
Finished Mar 31 03:22:48 PM PDT 24
Peak memory 200464 kb
Host smart-fe940ee0-1672-43da-8e65-16005454381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282832679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.282832679
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2321380275
Short name T960
Test name
Test status
Simulation time 29208733604 ps
CPU time 12.91 seconds
Started Mar 31 03:22:22 PM PDT 24
Finished Mar 31 03:22:35 PM PDT 24
Peak memory 200456 kb
Host smart-d12a6c86-c4fe-4fa1-b383-375c5e6b0966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321380275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2321380275
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3669552750
Short name T323
Test name
Test status
Simulation time 29558582261 ps
CPU time 25.6 seconds
Started Mar 31 03:22:22 PM PDT 24
Finished Mar 31 03:22:48 PM PDT 24
Peak memory 200436 kb
Host smart-2eb791f5-1131-4a55-aac4-2124344721e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669552750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3669552750
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2765073807
Short name T463
Test name
Test status
Simulation time 20717857307 ps
CPU time 9.05 seconds
Started Mar 31 03:22:23 PM PDT 24
Finished Mar 31 03:22:32 PM PDT 24
Peak memory 197784 kb
Host smart-506c2101-7146-4a32-bd83-ec1277fa8bc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765073807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2765073807
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1967922116
Short name T254
Test name
Test status
Simulation time 91396479164 ps
CPU time 427.1 seconds
Started Mar 31 03:22:30 PM PDT 24
Finished Mar 31 03:29:38 PM PDT 24
Peak memory 200480 kb
Host smart-454cf4a2-44e3-47b6-b5bf-239b097b3ad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967922116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1967922116
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2319833143
Short name T79
Test name
Test status
Simulation time 4056513980 ps
CPU time 4.29 seconds
Started Mar 31 03:22:27 PM PDT 24
Finished Mar 31 03:22:32 PM PDT 24
Peak memory 196312 kb
Host smart-44be9aa1-6b30-4dfc-a864-e26a52455337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319833143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2319833143
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1724285795
Short name T970
Test name
Test status
Simulation time 26543642596 ps
CPU time 43.28 seconds
Started Mar 31 03:22:22 PM PDT 24
Finished Mar 31 03:23:05 PM PDT 24
Peak memory 199604 kb
Host smart-c0abc5b7-26d8-4844-ab64-73c9498044dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724285795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1724285795
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1835914926
Short name T371
Test name
Test status
Simulation time 16088977419 ps
CPU time 935.64 seconds
Started Mar 31 03:22:28 PM PDT 24
Finished Mar 31 03:38:04 PM PDT 24
Peak memory 200508 kb
Host smart-9ec058e7-d9b7-4e4a-8c87-f6f6b9eab135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835914926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1835914926
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2144760274
Short name T910
Test name
Test status
Simulation time 4593370743 ps
CPU time 35.3 seconds
Started Mar 31 03:22:21 PM PDT 24
Finished Mar 31 03:22:56 PM PDT 24
Peak memory 198380 kb
Host smart-4c22d9d7-23d3-45a7-b5e6-1d2d2743be8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144760274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2144760274
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.4076723444
Short name T712
Test name
Test status
Simulation time 82557385376 ps
CPU time 16.6 seconds
Started Mar 31 03:22:24 PM PDT 24
Finished Mar 31 03:22:40 PM PDT 24
Peak memory 200264 kb
Host smart-c8f96b5e-5eca-4e2f-987d-482e04b1f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076723444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.4076723444
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.387468851
Short name T714
Test name
Test status
Simulation time 2450559706 ps
CPU time 1.68 seconds
Started Mar 31 03:22:23 PM PDT 24
Finished Mar 31 03:22:24 PM PDT 24
Peak memory 196196 kb
Host smart-433092b0-e60b-4bfa-a5fe-8f2febf2b0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387468851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.387468851
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2521907859
Short name T393
Test name
Test status
Simulation time 452064612 ps
CPU time 1.72 seconds
Started Mar 31 03:22:18 PM PDT 24
Finished Mar 31 03:22:20 PM PDT 24
Peak memory 198712 kb
Host smart-8e89f7ed-5c28-49d6-9117-5740d1e6d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521907859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2521907859
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2036310883
Short name T1089
Test name
Test status
Simulation time 587905877708 ps
CPU time 968.16 seconds
Started Mar 31 03:22:29 PM PDT 24
Finished Mar 31 03:38:37 PM PDT 24
Peak memory 225480 kb
Host smart-62ab2bef-ad6c-497f-9f1f-22f639befedc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036310883 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2036310883
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2699120004
Short name T363
Test name
Test status
Simulation time 2308842870 ps
CPU time 2.41 seconds
Started Mar 31 03:22:23 PM PDT 24
Finished Mar 31 03:22:25 PM PDT 24
Peak memory 199264 kb
Host smart-44431ec2-b62c-4d5e-9af1-484877a1e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699120004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2699120004
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1126798939
Short name T544
Test name
Test status
Simulation time 105054900261 ps
CPU time 66.44 seconds
Started Mar 31 03:22:23 PM PDT 24
Finished Mar 31 03:23:29 PM PDT 24
Peak memory 200432 kb
Host smart-a5068230-4b77-4eb6-b8ab-5df010afb571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126798939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1126798939
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.353713059
Short name T790
Test name
Test status
Simulation time 34706475 ps
CPU time 0.51 seconds
Started Mar 31 03:22:38 PM PDT 24
Finished Mar 31 03:22:38 PM PDT 24
Peak memory 194824 kb
Host smart-02c3629a-f869-47ef-9e5e-0a50a055d56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353713059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.353713059
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2406045736
Short name T797
Test name
Test status
Simulation time 39892150621 ps
CPU time 27.4 seconds
Started Mar 31 03:22:30 PM PDT 24
Finished Mar 31 03:22:57 PM PDT 24
Peak memory 200304 kb
Host smart-b3624205-4c3e-4140-a4c2-251d0179c502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406045736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2406045736
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.391276796
Short name T298
Test name
Test status
Simulation time 124774810765 ps
CPU time 442.14 seconds
Started Mar 31 03:22:27 PM PDT 24
Finished Mar 31 03:29:50 PM PDT 24
Peak memory 200460 kb
Host smart-8d5ef723-98ce-468e-9410-5b9c9abbf3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391276796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.391276796
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3156520652
Short name T294
Test name
Test status
Simulation time 147746227060 ps
CPU time 50.51 seconds
Started Mar 31 03:22:33 PM PDT 24
Finished Mar 31 03:23:24 PM PDT 24
Peak memory 200412 kb
Host smart-80ca379f-fdce-444e-9291-e76c8027aaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156520652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3156520652
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.160185800
Short name T865
Test name
Test status
Simulation time 33915706186 ps
CPU time 18.59 seconds
Started Mar 31 03:22:34 PM PDT 24
Finished Mar 31 03:22:52 PM PDT 24
Peak memory 200464 kb
Host smart-348ee92e-fbcf-4d96-9c2f-f8595aeeeb83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160185800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.160185800
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4086372170
Short name T442
Test name
Test status
Simulation time 60682137962 ps
CPU time 115.96 seconds
Started Mar 31 03:22:34 PM PDT 24
Finished Mar 31 03:24:30 PM PDT 24
Peak memory 200496 kb
Host smart-6387c8a2-425b-46d0-9dd5-4c93a02e6155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086372170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4086372170
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1661806679
Short name T721
Test name
Test status
Simulation time 5273253025 ps
CPU time 10.88 seconds
Started Mar 31 03:22:34 PM PDT 24
Finished Mar 31 03:22:45 PM PDT 24
Peak memory 200012 kb
Host smart-c2b12819-5165-44fb-960d-6332dfd25f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661806679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1661806679
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3474488459
Short name T270
Test name
Test status
Simulation time 172277665803 ps
CPU time 97.27 seconds
Started Mar 31 03:22:33 PM PDT 24
Finished Mar 31 03:24:10 PM PDT 24
Peak memory 200756 kb
Host smart-7dd68a21-ecf2-48df-b3ce-3461f6f7e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474488459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3474488459
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.743108041
Short name T1169
Test name
Test status
Simulation time 7515050695 ps
CPU time 416.34 seconds
Started Mar 31 03:22:35 PM PDT 24
Finished Mar 31 03:29:31 PM PDT 24
Peak memory 200508 kb
Host smart-5d9c0739-db79-489b-99b9-e25f366a3660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743108041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.743108041
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2447484538
Short name T39
Test name
Test status
Simulation time 5767814723 ps
CPU time 12.87 seconds
Started Mar 31 03:22:34 PM PDT 24
Finished Mar 31 03:22:47 PM PDT 24
Peak memory 199488 kb
Host smart-93a36e13-7fee-4359-901c-e879bee2dcf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447484538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2447484538
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1297620581
Short name T1055
Test name
Test status
Simulation time 25344964499 ps
CPU time 19.43 seconds
Started Mar 31 03:22:33 PM PDT 24
Finished Mar 31 03:22:52 PM PDT 24
Peak memory 200496 kb
Host smart-093d1082-49d9-49c6-87ca-1503e0f0a987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297620581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1297620581
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1316353272
Short name T727
Test name
Test status
Simulation time 2277480549 ps
CPU time 4.57 seconds
Started Mar 31 03:22:33 PM PDT 24
Finished Mar 31 03:22:37 PM PDT 24
Peak memory 195956 kb
Host smart-76aa1312-0a36-40ce-bdec-58b2d7e2c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316353272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1316353272
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1509593660
Short name T929
Test name
Test status
Simulation time 5686721065 ps
CPU time 7.95 seconds
Started Mar 31 03:22:27 PM PDT 24
Finished Mar 31 03:22:35 PM PDT 24
Peak memory 200208 kb
Host smart-756ee70c-9f51-4498-8b6e-f0c91b280439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509593660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1509593660
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.507340820
Short name T580
Test name
Test status
Simulation time 107863921846 ps
CPU time 54.89 seconds
Started Mar 31 03:22:33 PM PDT 24
Finished Mar 31 03:23:28 PM PDT 24
Peak memory 200760 kb
Host smart-00452b4e-bc11-4be7-a430-0049882c4fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507340820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.507340820
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2084733177
Short name T643
Test name
Test status
Simulation time 18892807224 ps
CPU time 268.53 seconds
Started Mar 31 03:22:33 PM PDT 24
Finished Mar 31 03:27:02 PM PDT 24
Peak memory 216104 kb
Host smart-c36831c7-dbc6-437d-87cc-95a2cc76f6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084733177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2084733177
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1036356417
Short name T741
Test name
Test status
Simulation time 13227923715 ps
CPU time 5.85 seconds
Started Mar 31 03:22:33 PM PDT 24
Finished Mar 31 03:22:39 PM PDT 24
Peak memory 200424 kb
Host smart-d3d593f9-6f30-4dbd-9ceb-c218109441c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036356417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1036356417
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1430394366
Short name T1171
Test name
Test status
Simulation time 26999698305 ps
CPU time 9.72 seconds
Started Mar 31 03:22:28 PM PDT 24
Finished Mar 31 03:22:38 PM PDT 24
Peak memory 200472 kb
Host smart-78d469f9-f679-47b5-bd38-5b55e60c631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430394366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1430394366
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2497214704
Short name T884
Test name
Test status
Simulation time 13664892 ps
CPU time 0.55 seconds
Started Mar 31 03:22:48 PM PDT 24
Finished Mar 31 03:22:49 PM PDT 24
Peak memory 196096 kb
Host smart-be7846f9-9e26-4db8-99eb-377473c831d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497214704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2497214704
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2454291173
Short name T903
Test name
Test status
Simulation time 67404075447 ps
CPU time 29.18 seconds
Started Mar 31 03:22:37 PM PDT 24
Finished Mar 31 03:23:07 PM PDT 24
Peak memory 199756 kb
Host smart-4faa5810-dda4-4bfc-85bd-46ab19b3c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454291173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2454291173
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3707124716
Short name T333
Test name
Test status
Simulation time 152640177964 ps
CPU time 520.44 seconds
Started Mar 31 03:22:38 PM PDT 24
Finished Mar 31 03:31:18 PM PDT 24
Peak memory 200548 kb
Host smart-739cb8a1-3039-4af6-a6d7-131251e14e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707124716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3707124716
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3220654970
Short name T515
Test name
Test status
Simulation time 39366787264 ps
CPU time 17.2 seconds
Started Mar 31 03:22:43 PM PDT 24
Finished Mar 31 03:23:01 PM PDT 24
Peak memory 200464 kb
Host smart-b4380f97-7621-42b0-bda3-f6742bbad74b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220654970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3220654970
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1347551911
Short name T573
Test name
Test status
Simulation time 105117791625 ps
CPU time 90.32 seconds
Started Mar 31 03:22:43 PM PDT 24
Finished Mar 31 03:24:14 PM PDT 24
Peak memory 200476 kb
Host smart-5c69de98-870d-41d2-852a-1b3855f45dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347551911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1347551911
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.279018026
Short name T879
Test name
Test status
Simulation time 9506782964 ps
CPU time 17.08 seconds
Started Mar 31 03:22:45 PM PDT 24
Finished Mar 31 03:23:02 PM PDT 24
Peak memory 199192 kb
Host smart-9ab7e3b5-976d-48a1-ac38-41e0fa94a84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279018026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.279018026
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1410642291
Short name T873
Test name
Test status
Simulation time 185604176038 ps
CPU time 269.99 seconds
Started Mar 31 03:22:43 PM PDT 24
Finished Mar 31 03:27:13 PM PDT 24
Peak memory 208972 kb
Host smart-aa7a7689-f6a8-4cde-921f-a517e0199a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410642291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1410642291
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2763433124
Short name T773
Test name
Test status
Simulation time 5313702951 ps
CPU time 195.67 seconds
Started Mar 31 03:22:44 PM PDT 24
Finished Mar 31 03:26:00 PM PDT 24
Peak memory 200500 kb
Host smart-c05de538-7a25-471e-a1c9-580852022641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763433124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2763433124
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1815641631
Short name T356
Test name
Test status
Simulation time 3788191915 ps
CPU time 34.34 seconds
Started Mar 31 03:22:37 PM PDT 24
Finished Mar 31 03:23:12 PM PDT 24
Peak memory 198580 kb
Host smart-e92ffe1b-492f-4225-86e4-96daa24f04cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815641631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1815641631
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2968578457
Short name T141
Test name
Test status
Simulation time 159528292401 ps
CPU time 98.75 seconds
Started Mar 31 03:22:43 PM PDT 24
Finished Mar 31 03:24:22 PM PDT 24
Peak memory 200532 kb
Host smart-df1908fd-9a41-4616-ab42-d3957f4ea541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968578457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2968578457
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2856914303
Short name T1072
Test name
Test status
Simulation time 3878187516 ps
CPU time 2.26 seconds
Started Mar 31 03:22:45 PM PDT 24
Finished Mar 31 03:22:48 PM PDT 24
Peak memory 197252 kb
Host smart-270f3404-ecd3-4a1f-9458-62d19a2a5cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856914303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2856914303
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.589131431
Short name T654
Test name
Test status
Simulation time 988646650 ps
CPU time 1.37 seconds
Started Mar 31 03:22:40 PM PDT 24
Finished Mar 31 03:22:41 PM PDT 24
Peak memory 198716 kb
Host smart-a19d4a39-4881-49e9-8583-a407c4c2a5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589131431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.589131431
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1630985888
Short name T921
Test name
Test status
Simulation time 32459436903 ps
CPU time 64.31 seconds
Started Mar 31 03:22:50 PM PDT 24
Finished Mar 31 03:23:54 PM PDT 24
Peak memory 200432 kb
Host smart-d52756d2-91fc-403f-a8b8-cadb58be8434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630985888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1630985888
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3889182624
Short name T31
Test name
Test status
Simulation time 100345005060 ps
CPU time 204.6 seconds
Started Mar 31 03:22:49 PM PDT 24
Finished Mar 31 03:26:14 PM PDT 24
Peak memory 216040 kb
Host smart-cdda4767-993a-46c4-b85b-938f39403ed4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889182624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3889182624
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.669601439
Short name T446
Test name
Test status
Simulation time 1516826079 ps
CPU time 1.47 seconds
Started Mar 31 03:22:43 PM PDT 24
Finished Mar 31 03:22:45 PM PDT 24
Peak memory 197492 kb
Host smart-557a16c2-35af-46c7-a9ba-0440f0f0cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669601439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.669601439
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2353363872
Short name T264
Test name
Test status
Simulation time 62710917918 ps
CPU time 154.89 seconds
Started Mar 31 03:22:38 PM PDT 24
Finished Mar 31 03:25:13 PM PDT 24
Peak memory 200448 kb
Host smart-8ec795f7-5b2f-4ea2-bb0a-757b511f9c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353363872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2353363872
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.4119188823
Short name T757
Test name
Test status
Simulation time 39805721 ps
CPU time 0.54 seconds
Started Mar 31 03:22:54 PM PDT 24
Finished Mar 31 03:22:55 PM PDT 24
Peak memory 194880 kb
Host smart-6ff358a0-5d60-41df-b142-cad06dc0fc03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119188823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4119188823
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.566055585
Short name T272
Test name
Test status
Simulation time 70516331508 ps
CPU time 34.21 seconds
Started Mar 31 03:22:48 PM PDT 24
Finished Mar 31 03:23:22 PM PDT 24
Peak memory 200460 kb
Host smart-c5f13d95-6032-4671-b899-769610b32244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566055585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.566055585
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.120199271
Short name T414
Test name
Test status
Simulation time 108011806199 ps
CPU time 45.08 seconds
Started Mar 31 03:22:49 PM PDT 24
Finished Mar 31 03:23:34 PM PDT 24
Peak memory 200252 kb
Host smart-bed70335-50c9-4789-964a-358cd99ab415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120199271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.120199271
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1706062277
Short name T7
Test name
Test status
Simulation time 19150775210 ps
CPU time 28.51 seconds
Started Mar 31 03:22:49 PM PDT 24
Finished Mar 31 03:23:18 PM PDT 24
Peak memory 200412 kb
Host smart-71c3e85f-65d0-431c-84ab-d212cf408a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706062277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1706062277
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.759992307
Short name T436
Test name
Test status
Simulation time 29007460043 ps
CPU time 41.71 seconds
Started Mar 31 03:22:48 PM PDT 24
Finished Mar 31 03:23:30 PM PDT 24
Peak memory 200104 kb
Host smart-e8f99c72-e171-4725-a014-2cccda174d2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759992307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.759992307
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2534748061
Short name T368
Test name
Test status
Simulation time 183292464877 ps
CPU time 399.21 seconds
Started Mar 31 03:22:53 PM PDT 24
Finished Mar 31 03:29:33 PM PDT 24
Peak memory 200472 kb
Host smart-08c256aa-741a-46bf-86fc-9172b8f3f9f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534748061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2534748061
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2640212959
Short name T632
Test name
Test status
Simulation time 4183303191 ps
CPU time 3.53 seconds
Started Mar 31 03:22:53 PM PDT 24
Finished Mar 31 03:22:57 PM PDT 24
Peak memory 199208 kb
Host smart-e3f0d12c-c944-4b28-8463-353573e6fb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640212959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2640212959
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2048155330
Short name T568
Test name
Test status
Simulation time 200000824556 ps
CPU time 146.2 seconds
Started Mar 31 03:22:47 PM PDT 24
Finished Mar 31 03:25:14 PM PDT 24
Peak memory 208964 kb
Host smart-9a8cd769-57b7-448d-a15b-9c14c93bc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048155330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2048155330
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1935513463
Short name T575
Test name
Test status
Simulation time 5322836203 ps
CPU time 73.18 seconds
Started Mar 31 03:22:55 PM PDT 24
Finished Mar 31 03:24:09 PM PDT 24
Peak memory 200392 kb
Host smart-1378d3df-e255-4502-8354-305a6a9bf712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935513463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1935513463
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2332553505
Short name T1137
Test name
Test status
Simulation time 7183341103 ps
CPU time 15.02 seconds
Started Mar 31 03:22:48 PM PDT 24
Finished Mar 31 03:23:03 PM PDT 24
Peak memory 199556 kb
Host smart-892b2463-4fc0-4280-994e-6f02701eb005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332553505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2332553505
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1518016830
Short name T904
Test name
Test status
Simulation time 101030381390 ps
CPU time 198.86 seconds
Started Mar 31 03:22:47 PM PDT 24
Finished Mar 31 03:26:07 PM PDT 24
Peak memory 200492 kb
Host smart-b60df86b-c76e-4e2c-b9cf-e3e4620528db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518016830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1518016830
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2090306851
Short name T640
Test name
Test status
Simulation time 3157881001 ps
CPU time 1.87 seconds
Started Mar 31 03:22:48 PM PDT 24
Finished Mar 31 03:22:50 PM PDT 24
Peak memory 196480 kb
Host smart-1f4c50c0-ccf2-42e7-a34f-3493d0774ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090306851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2090306851
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.136401722
Short name T726
Test name
Test status
Simulation time 5463684035 ps
CPU time 10.35 seconds
Started Mar 31 03:22:49 PM PDT 24
Finished Mar 31 03:23:00 PM PDT 24
Peak memory 200220 kb
Host smart-ed022773-559d-4988-aa20-6f099e1db2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136401722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.136401722
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.834483448
Short name T1073
Test name
Test status
Simulation time 518342074066 ps
CPU time 397.89 seconds
Started Mar 31 03:22:52 PM PDT 24
Finished Mar 31 03:29:31 PM PDT 24
Peak memory 216216 kb
Host smart-5e82dc57-a82b-4ce9-9b65-d8cead5f8ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834483448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.834483448
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2044012749
Short name T1177
Test name
Test status
Simulation time 102631999875 ps
CPU time 662.52 seconds
Started Mar 31 03:22:53 PM PDT 24
Finished Mar 31 03:33:56 PM PDT 24
Peak memory 216940 kb
Host smart-8980406b-98f3-45cd-9a7f-8a8c5868ae77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044012749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2044012749
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.729287848
Short name T775
Test name
Test status
Simulation time 629416163 ps
CPU time 1.04 seconds
Started Mar 31 03:22:47 PM PDT 24
Finished Mar 31 03:22:48 PM PDT 24
Peak memory 198444 kb
Host smart-478432c6-b561-484b-8339-4e371973e45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729287848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.729287848
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.696149077
Short name T747
Test name
Test status
Simulation time 10160134729 ps
CPU time 19.25 seconds
Started Mar 31 03:22:47 PM PDT 24
Finished Mar 31 03:23:07 PM PDT 24
Peak memory 200452 kb
Host smart-aa41dbe7-f587-40ff-a818-0c41d3204a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696149077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.696149077
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1453221116
Short name T939
Test name
Test status
Simulation time 30216366 ps
CPU time 0.56 seconds
Started Mar 31 03:15:50 PM PDT 24
Finished Mar 31 03:15:50 PM PDT 24
Peak memory 195908 kb
Host smart-22a142f9-3a80-4a15-9c53-01aa35dc76e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453221116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1453221116
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2435246520
Short name T611
Test name
Test status
Simulation time 46659987123 ps
CPU time 32.66 seconds
Started Mar 31 03:15:40 PM PDT 24
Finished Mar 31 03:16:12 PM PDT 24
Peak memory 200428 kb
Host smart-d23c5b99-3acc-49e3-bb1a-00e4dd8a6673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435246520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2435246520
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1722450109
Short name T624
Test name
Test status
Simulation time 14473294551 ps
CPU time 27.1 seconds
Started Mar 31 03:15:42 PM PDT 24
Finished Mar 31 03:16:10 PM PDT 24
Peak memory 200432 kb
Host smart-16400581-8604-4ab2-b247-d07c76e454f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722450109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1722450109
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1176066366
Short name T829
Test name
Test status
Simulation time 20042222619 ps
CPU time 43.73 seconds
Started Mar 31 03:15:42 PM PDT 24
Finished Mar 31 03:16:26 PM PDT 24
Peak memory 200456 kb
Host smart-6506e585-aa1a-49b9-ab4a-d997840e508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176066366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1176066366
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.4042873035
Short name T481
Test name
Test status
Simulation time 67018827903 ps
CPU time 125.46 seconds
Started Mar 31 03:15:40 PM PDT 24
Finished Mar 31 03:17:46 PM PDT 24
Peak memory 200292 kb
Host smart-b9763c41-dcb7-489b-8ebb-0fac11f5d851
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042873035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.4042873035
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4208873465
Short name T740
Test name
Test status
Simulation time 361575480686 ps
CPU time 59.25 seconds
Started Mar 31 03:15:49 PM PDT 24
Finished Mar 31 03:16:48 PM PDT 24
Peak memory 200436 kb
Host smart-ac4a7879-2b69-47e1-88db-41e8ba7c5f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208873465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4208873465
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3248603949
Short name T666
Test name
Test status
Simulation time 1347880858 ps
CPU time 1.17 seconds
Started Mar 31 03:15:48 PM PDT 24
Finished Mar 31 03:15:49 PM PDT 24
Peak memory 195912 kb
Host smart-9344bdec-29a2-4876-a2e0-df0f50bbd181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248603949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3248603949
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3698324279
Short name T285
Test name
Test status
Simulation time 42905335287 ps
CPU time 71.68 seconds
Started Mar 31 03:15:40 PM PDT 24
Finished Mar 31 03:16:52 PM PDT 24
Peak memory 199704 kb
Host smart-a573a9f1-0275-4a00-92f3-63eaa4afbbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698324279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3698324279
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.4121655218
Short name T1026
Test name
Test status
Simulation time 26895213969 ps
CPU time 230.09 seconds
Started Mar 31 03:15:50 PM PDT 24
Finished Mar 31 03:19:40 PM PDT 24
Peak memory 200464 kb
Host smart-b52a68bd-8d7a-49ad-883f-89999a08f357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121655218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4121655218
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.886672491
Short name T511
Test name
Test status
Simulation time 3867206476 ps
CPU time 26.59 seconds
Started Mar 31 03:15:41 PM PDT 24
Finished Mar 31 03:16:08 PM PDT 24
Peak memory 199576 kb
Host smart-750d491b-2e27-4405-bc19-92525a86c567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886672491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.886672491
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2270394946
Short name T641
Test name
Test status
Simulation time 75015999546 ps
CPU time 18.13 seconds
Started Mar 31 03:15:49 PM PDT 24
Finished Mar 31 03:16:07 PM PDT 24
Peak memory 200416 kb
Host smart-d9c87792-d0d6-4f20-94eb-37e10a5e6824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270394946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2270394946
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3134444934
Short name T852
Test name
Test status
Simulation time 4556054670 ps
CPU time 4.01 seconds
Started Mar 31 03:15:50 PM PDT 24
Finished Mar 31 03:15:55 PM PDT 24
Peak memory 196772 kb
Host smart-f9866569-126a-4d2b-bfb9-ede72798cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134444934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3134444934
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2749595323
Short name T24
Test name
Test status
Simulation time 59132860 ps
CPU time 0.84 seconds
Started Mar 31 03:15:49 PM PDT 24
Finished Mar 31 03:15:50 PM PDT 24
Peak memory 218944 kb
Host smart-66a2c32d-cf98-4308-9120-1b6b9b0eeb9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749595323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2749595323
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3832476487
Short name T777
Test name
Test status
Simulation time 450218419 ps
CPU time 1.83 seconds
Started Mar 31 03:15:38 PM PDT 24
Finished Mar 31 03:15:40 PM PDT 24
Peak memory 198800 kb
Host smart-236aeb6e-5806-4b06-aaa7-7c6742b42851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832476487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3832476487
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3932517460
Short name T13
Test name
Test status
Simulation time 270587986204 ps
CPU time 1037.26 seconds
Started Mar 31 03:15:51 PM PDT 24
Finished Mar 31 03:33:08 PM PDT 24
Peak memory 200504 kb
Host smart-a8a4e730-0535-411d-9f90-c69ae7a083e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932517460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3932517460
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3720147775
Short name T28
Test name
Test status
Simulation time 13314510164 ps
CPU time 156.14 seconds
Started Mar 31 03:15:49 PM PDT 24
Finished Mar 31 03:18:25 PM PDT 24
Peak memory 216548 kb
Host smart-81ee04e9-9d08-47e0-8011-87e524db97a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720147775 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3720147775
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1387292601
Short name T675
Test name
Test status
Simulation time 1219914816 ps
CPU time 3.65 seconds
Started Mar 31 03:15:49 PM PDT 24
Finished Mar 31 03:15:52 PM PDT 24
Peak memory 200008 kb
Host smart-1793745a-a51a-40b7-8e39-be2bb129a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387292601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1387292601
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1894549468
Short name T869
Test name
Test status
Simulation time 63317984323 ps
CPU time 109.45 seconds
Started Mar 31 03:15:40 PM PDT 24
Finished Mar 31 03:17:30 PM PDT 24
Peak memory 200440 kb
Host smart-f66f8590-27da-4ddb-900d-232c33891823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894549468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1894549468
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3778885725
Short name T355
Test name
Test status
Simulation time 12648192 ps
CPU time 0.56 seconds
Started Mar 31 03:23:04 PM PDT 24
Finished Mar 31 03:23:05 PM PDT 24
Peak memory 195852 kb
Host smart-b4535464-2c26-4ea2-998c-b86b0f973edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778885725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3778885725
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.491903550
Short name T876
Test name
Test status
Simulation time 59159275758 ps
CPU time 26.91 seconds
Started Mar 31 03:22:55 PM PDT 24
Finished Mar 31 03:23:22 PM PDT 24
Peak memory 200412 kb
Host smart-34e0f42d-5dfb-494c-ad65-b8aa65aa42bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491903550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.491903550
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3500889034
Short name T559
Test name
Test status
Simulation time 259340995981 ps
CPU time 325.28 seconds
Started Mar 31 03:22:53 PM PDT 24
Finished Mar 31 03:28:19 PM PDT 24
Peak memory 200476 kb
Host smart-499b45df-d51e-4eec-b3cf-c2b73ee0f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500889034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3500889034
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1605812799
Short name T574
Test name
Test status
Simulation time 73836972148 ps
CPU time 34.95 seconds
Started Mar 31 03:22:53 PM PDT 24
Finished Mar 31 03:23:28 PM PDT 24
Peak memory 200504 kb
Host smart-3e991cf0-24e7-4574-b2c8-121f7bcd9fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605812799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1605812799
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.4023693682
Short name T1086
Test name
Test status
Simulation time 11217266714 ps
CPU time 11.93 seconds
Started Mar 31 03:22:58 PM PDT 24
Finished Mar 31 03:23:11 PM PDT 24
Peak memory 200460 kb
Host smart-a590b09d-c371-48dd-8e04-47bbfc4d0116
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023693682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.4023693682
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2543815714
Short name T943
Test name
Test status
Simulation time 110705035595 ps
CPU time 244.49 seconds
Started Mar 31 03:23:01 PM PDT 24
Finished Mar 31 03:27:05 PM PDT 24
Peak memory 200488 kb
Host smart-1df260b5-d2c8-4348-99a1-bdad2965d7a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543815714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2543815714
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3932321490
Short name T716
Test name
Test status
Simulation time 6420265803 ps
CPU time 12.11 seconds
Started Mar 31 03:23:04 PM PDT 24
Finished Mar 31 03:23:16 PM PDT 24
Peak memory 200520 kb
Host smart-6e866530-d259-46b4-933c-f6ac49413a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932321490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3932321490
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1382249542
Short name T951
Test name
Test status
Simulation time 142982104895 ps
CPU time 64.76 seconds
Started Mar 31 03:22:58 PM PDT 24
Finished Mar 31 03:24:03 PM PDT 24
Peak memory 200772 kb
Host smart-3783208f-ff02-4fa9-b7b6-2ea88134733a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382249542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1382249542
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2264899508
Short name T588
Test name
Test status
Simulation time 12928716840 ps
CPU time 375.69 seconds
Started Mar 31 03:23:00 PM PDT 24
Finished Mar 31 03:29:17 PM PDT 24
Peak memory 200520 kb
Host smart-44ff653c-9ca0-4402-acc1-ca1d8bfdf3b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264899508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2264899508
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3029613786
Short name T751
Test name
Test status
Simulation time 3173959707 ps
CPU time 22.23 seconds
Started Mar 31 03:22:57 PM PDT 24
Finished Mar 31 03:23:19 PM PDT 24
Peak memory 198936 kb
Host smart-7745e3ac-7a35-4109-873c-29f83d0b708e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029613786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3029613786
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.4001265222
Short name T358
Test name
Test status
Simulation time 15684390364 ps
CPU time 8.95 seconds
Started Mar 31 03:22:59 PM PDT 24
Finished Mar 31 03:23:09 PM PDT 24
Peak memory 200244 kb
Host smart-19c5d0c9-a42f-4867-87e5-f272f12d5904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001265222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4001265222
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.475618691
Short name T1044
Test name
Test status
Simulation time 5498828042 ps
CPU time 5.03 seconds
Started Mar 31 03:23:03 PM PDT 24
Finished Mar 31 03:23:08 PM PDT 24
Peak memory 196568 kb
Host smart-91bc7b8f-1bb1-4414-8ddb-7007c38a2e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475618691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.475618691
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2576254559
Short name T906
Test name
Test status
Simulation time 5965541670 ps
CPU time 20.74 seconds
Started Mar 31 03:22:55 PM PDT 24
Finished Mar 31 03:23:16 PM PDT 24
Peak memory 200276 kb
Host smart-5c0b52d8-63b5-41a3-b897-f102aaaac7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576254559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2576254559
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2594157068
Short name T252
Test name
Test status
Simulation time 120530660966 ps
CPU time 501.01 seconds
Started Mar 31 03:23:04 PM PDT 24
Finished Mar 31 03:31:26 PM PDT 24
Peak memory 200424 kb
Host smart-d62681ce-d1fa-49d4-bf7a-46c369fc668d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594157068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2594157068
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4109070696
Short name T867
Test name
Test status
Simulation time 604055916634 ps
CPU time 366.43 seconds
Started Mar 31 03:23:03 PM PDT 24
Finished Mar 31 03:29:10 PM PDT 24
Peak memory 217432 kb
Host smart-fa8b0b7d-4332-4358-8bbf-679417d09a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109070696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4109070696
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3793259240
Short name T1065
Test name
Test status
Simulation time 877091899 ps
CPU time 1.53 seconds
Started Mar 31 03:23:04 PM PDT 24
Finished Mar 31 03:23:05 PM PDT 24
Peak memory 199044 kb
Host smart-0fe5826e-a59e-41ce-80a8-29fad5341341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793259240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3793259240
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3794306272
Short name T273
Test name
Test status
Simulation time 155636583365 ps
CPU time 155.42 seconds
Started Mar 31 03:22:54 PM PDT 24
Finished Mar 31 03:25:30 PM PDT 24
Peak memory 200508 kb
Host smart-06a81f68-1881-4559-a0e1-673b521dc506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794306272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3794306272
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3180991054
Short name T21
Test name
Test status
Simulation time 18032231 ps
CPU time 0.55 seconds
Started Mar 31 03:23:16 PM PDT 24
Finished Mar 31 03:23:17 PM PDT 24
Peak memory 195892 kb
Host smart-2b0f0a11-5b1c-446b-8c55-684d16ddbd49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180991054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3180991054
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2687897298
Short name T78
Test name
Test status
Simulation time 62241764858 ps
CPU time 32.25 seconds
Started Mar 31 03:23:04 PM PDT 24
Finished Mar 31 03:23:37 PM PDT 24
Peak memory 200380 kb
Host smart-41e049e8-931b-4df6-994b-713859428bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687897298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2687897298
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2005243998
Short name T878
Test name
Test status
Simulation time 107080822927 ps
CPU time 69.86 seconds
Started Mar 31 03:23:05 PM PDT 24
Finished Mar 31 03:24:15 PM PDT 24
Peak memory 200496 kb
Host smart-5ea7c330-5138-4c5d-a0d9-4654a449fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005243998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2005243998
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2725803005
Short name T992
Test name
Test status
Simulation time 52766678991 ps
CPU time 22.59 seconds
Started Mar 31 03:23:11 PM PDT 24
Finished Mar 31 03:23:33 PM PDT 24
Peak memory 200548 kb
Host smart-9f544a13-c2ad-4205-8b05-50d4b8c8754f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725803005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2725803005
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3602554309
Short name T1000
Test name
Test status
Simulation time 61661366856 ps
CPU time 373.89 seconds
Started Mar 31 03:23:11 PM PDT 24
Finished Mar 31 03:29:25 PM PDT 24
Peak memory 200520 kb
Host smart-5bbd6159-afd5-4249-b6bb-0236cac0aa70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602554309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3602554309
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1686769884
Short name T911
Test name
Test status
Simulation time 3249686917 ps
CPU time 2.05 seconds
Started Mar 31 03:23:12 PM PDT 24
Finished Mar 31 03:23:14 PM PDT 24
Peak memory 196876 kb
Host smart-252f08ab-daae-40cc-b602-7e64c34fddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686769884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1686769884
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.4101816679
Short name T412
Test name
Test status
Simulation time 105980726336 ps
CPU time 15.28 seconds
Started Mar 31 03:23:10 PM PDT 24
Finished Mar 31 03:23:25 PM PDT 24
Peak memory 200008 kb
Host smart-a6e89e0a-a74e-466e-b368-23565ff2932f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101816679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.4101816679
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.794893597
Short name T688
Test name
Test status
Simulation time 17470347074 ps
CPU time 820.64 seconds
Started Mar 31 03:23:10 PM PDT 24
Finished Mar 31 03:36:51 PM PDT 24
Peak memory 200408 kb
Host smart-74a7b8e9-9926-4d6c-9b07-73a0d92b1f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794893597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.794893597
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1559645913
Short name T479
Test name
Test status
Simulation time 6840174622 ps
CPU time 59.28 seconds
Started Mar 31 03:23:12 PM PDT 24
Finished Mar 31 03:24:11 PM PDT 24
Peak memory 199668 kb
Host smart-10dfdc5e-28d1-43e2-891c-5defe70914f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559645913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1559645913
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2563903576
Short name T958
Test name
Test status
Simulation time 131561788522 ps
CPU time 54.17 seconds
Started Mar 31 03:23:10 PM PDT 24
Finished Mar 31 03:24:05 PM PDT 24
Peak memory 200504 kb
Host smart-6ae8670a-ba34-470b-b183-1dd7801382a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563903576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2563903576
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.868703857
Short name T409
Test name
Test status
Simulation time 702431456 ps
CPU time 1.28 seconds
Started Mar 31 03:23:11 PM PDT 24
Finished Mar 31 03:23:12 PM PDT 24
Peak memory 196164 kb
Host smart-e441be97-42b1-4adf-b81d-57cb016b1a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868703857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.868703857
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.4247522277
Short name T794
Test name
Test status
Simulation time 5721106681 ps
CPU time 20.54 seconds
Started Mar 31 03:23:04 PM PDT 24
Finished Mar 31 03:23:25 PM PDT 24
Peak memory 200328 kb
Host smart-3f957501-816a-4a81-a4c7-9fe88147bd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247522277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4247522277
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2343837323
Short name T606
Test name
Test status
Simulation time 282558088652 ps
CPU time 148.09 seconds
Started Mar 31 03:23:17 PM PDT 24
Finished Mar 31 03:25:46 PM PDT 24
Peak memory 208984 kb
Host smart-59af67bb-7acf-4f4f-917e-627d0b9e5693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343837323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2343837323
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2620775114
Short name T433
Test name
Test status
Simulation time 50012898780 ps
CPU time 968.63 seconds
Started Mar 31 03:23:16 PM PDT 24
Finished Mar 31 03:39:25 PM PDT 24
Peak memory 217192 kb
Host smart-c509994c-5e2d-4b68-8d57-c3051c237c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620775114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2620775114
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2072093930
Short name T1124
Test name
Test status
Simulation time 752018342 ps
CPU time 2.23 seconds
Started Mar 31 03:23:11 PM PDT 24
Finished Mar 31 03:23:13 PM PDT 24
Peak memory 199424 kb
Host smart-5180d53b-8878-4279-95da-db05cb35d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072093930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2072093930
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.606660174
Short name T936
Test name
Test status
Simulation time 12459499150 ps
CPU time 23.87 seconds
Started Mar 31 03:23:07 PM PDT 24
Finished Mar 31 03:23:31 PM PDT 24
Peak memory 200420 kb
Host smart-a2268a6a-0d62-4ded-b01b-95bb7e2f6693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606660174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.606660174
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4180837016
Short name T338
Test name
Test status
Simulation time 58919751 ps
CPU time 0.57 seconds
Started Mar 31 03:23:24 PM PDT 24
Finished Mar 31 03:23:25 PM PDT 24
Peak memory 195896 kb
Host smart-6b9476c1-0cc3-45d4-870e-4485ca06f238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180837016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4180837016
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1028176852
Short name T526
Test name
Test status
Simulation time 124247578440 ps
CPU time 50.75 seconds
Started Mar 31 03:23:16 PM PDT 24
Finished Mar 31 03:24:07 PM PDT 24
Peak memory 200472 kb
Host smart-d18c0f70-af52-4cce-b4ce-84d84826bc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028176852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1028176852
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2320957267
Short name T901
Test name
Test status
Simulation time 62456531704 ps
CPU time 43.39 seconds
Started Mar 31 03:23:16 PM PDT 24
Finished Mar 31 03:24:00 PM PDT 24
Peak memory 200368 kb
Host smart-733d079a-721a-41fa-b3cc-9fbcebd74347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320957267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2320957267
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3237754039
Short name T1059
Test name
Test status
Simulation time 31829277411 ps
CPU time 16.04 seconds
Started Mar 31 03:23:16 PM PDT 24
Finished Mar 31 03:23:32 PM PDT 24
Peak memory 200436 kb
Host smart-7f8ff5c1-e387-401d-833d-51ca57efc481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237754039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3237754039
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.931715181
Short name T321
Test name
Test status
Simulation time 33346865239 ps
CPU time 58.59 seconds
Started Mar 31 03:23:23 PM PDT 24
Finished Mar 31 03:24:22 PM PDT 24
Peak memory 200504 kb
Host smart-72ed8306-47cf-4df6-876b-535ff5afe32f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931715181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.931715181
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4121839745
Short name T337
Test name
Test status
Simulation time 95245858052 ps
CPU time 117.58 seconds
Started Mar 31 03:23:21 PM PDT 24
Finished Mar 31 03:25:18 PM PDT 24
Peak memory 200428 kb
Host smart-5fc7566f-4e9c-48fe-969f-b241ee00fd42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121839745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4121839745
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3250235995
Short name T689
Test name
Test status
Simulation time 384333139 ps
CPU time 0.93 seconds
Started Mar 31 03:23:24 PM PDT 24
Finished Mar 31 03:23:25 PM PDT 24
Peak memory 196192 kb
Host smart-394af76b-dff9-4097-81f2-e28a1bd384aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250235995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3250235995
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3513507885
Short name T887
Test name
Test status
Simulation time 34735940521 ps
CPU time 14.07 seconds
Started Mar 31 03:23:25 PM PDT 24
Finished Mar 31 03:23:39 PM PDT 24
Peak memory 195788 kb
Host smart-01cb200b-61e7-406e-a83e-03e8bdd2ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513507885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3513507885
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3352987419
Short name T1093
Test name
Test status
Simulation time 12698227176 ps
CPU time 614.73 seconds
Started Mar 31 03:23:24 PM PDT 24
Finished Mar 31 03:33:39 PM PDT 24
Peak memory 200484 kb
Host smart-96e2ce35-9e04-4881-b440-86b9d5618c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352987419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3352987419
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2651289481
Short name T649
Test name
Test status
Simulation time 5154259769 ps
CPU time 9.28 seconds
Started Mar 31 03:23:25 PM PDT 24
Finished Mar 31 03:23:35 PM PDT 24
Peak memory 200608 kb
Host smart-8da26829-0e3a-4eaa-a732-481041fd2ad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651289481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2651289481
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1625944714
Short name T1046
Test name
Test status
Simulation time 77694345748 ps
CPU time 138.35 seconds
Started Mar 31 03:23:21 PM PDT 24
Finished Mar 31 03:25:40 PM PDT 24
Peak memory 200432 kb
Host smart-d1c3945c-5bf5-474b-8182-27515ffe9fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625944714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1625944714
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.900852563
Short name T894
Test name
Test status
Simulation time 43592281327 ps
CPU time 71.55 seconds
Started Mar 31 03:23:24 PM PDT 24
Finished Mar 31 03:24:36 PM PDT 24
Peak memory 196500 kb
Host smart-c3320aec-5736-4ef0-a898-0740415f4cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900852563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.900852563
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1903108090
Short name T930
Test name
Test status
Simulation time 714194066 ps
CPU time 2.99 seconds
Started Mar 31 03:23:17 PM PDT 24
Finished Mar 31 03:23:20 PM PDT 24
Peak memory 199932 kb
Host smart-73e0b05e-64ab-47df-b23e-2b0f48400237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903108090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1903108090
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.764445984
Short name T1067
Test name
Test status
Simulation time 6075395903 ps
CPU time 68.15 seconds
Started Mar 31 03:23:25 PM PDT 24
Finished Mar 31 03:24:34 PM PDT 24
Peak memory 217048 kb
Host smart-a9eb8daf-e900-42b5-9bce-eebcdec59ffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764445984 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.764445984
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3925457702
Short name T962
Test name
Test status
Simulation time 1505094896 ps
CPU time 6.46 seconds
Started Mar 31 03:23:22 PM PDT 24
Finished Mar 31 03:23:28 PM PDT 24
Peak memory 200360 kb
Host smart-2332eb5d-7d63-4775-a9ed-a8a60fb9053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925457702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3925457702
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2575793245
Short name T810
Test name
Test status
Simulation time 136156685524 ps
CPU time 72.57 seconds
Started Mar 31 03:23:16 PM PDT 24
Finished Mar 31 03:24:29 PM PDT 24
Peak memory 200464 kb
Host smart-debc8d50-2684-452b-aa2d-97015d6a56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575793245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2575793245
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1829580256
Short name T756
Test name
Test status
Simulation time 14463460 ps
CPU time 0.55 seconds
Started Mar 31 03:23:33 PM PDT 24
Finished Mar 31 03:23:34 PM PDT 24
Peak memory 195900 kb
Host smart-57690967-5bb6-4587-ada6-ef44b4ecb322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829580256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1829580256
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2179694141
Short name T1097
Test name
Test status
Simulation time 110285834432 ps
CPU time 150.72 seconds
Started Mar 31 03:23:28 PM PDT 24
Finished Mar 31 03:25:59 PM PDT 24
Peak memory 200472 kb
Host smart-46548af4-16bc-4fdd-8ee0-50635423ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179694141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2179694141
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.779476293
Short name T514
Test name
Test status
Simulation time 10118878530 ps
CPU time 18.29 seconds
Started Mar 31 03:23:30 PM PDT 24
Finished Mar 31 03:23:49 PM PDT 24
Peak memory 200532 kb
Host smart-f16b7ebb-9a83-41b5-adc7-0139735ea090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779476293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.779476293
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2962517301
Short name T531
Test name
Test status
Simulation time 39617549758 ps
CPU time 68.29 seconds
Started Mar 31 03:23:29 PM PDT 24
Finished Mar 31 03:24:37 PM PDT 24
Peak memory 200432 kb
Host smart-a95f598a-b349-4ad4-b3be-0071143cbe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962517301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2962517301
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3990606970
Short name T87
Test name
Test status
Simulation time 13427223750 ps
CPU time 24.35 seconds
Started Mar 31 03:23:28 PM PDT 24
Finished Mar 31 03:23:53 PM PDT 24
Peak memory 197740 kb
Host smart-7c583e14-5d7a-42cb-839d-bcd6bf00aa0a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990606970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3990606970
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1486320204
Short name T489
Test name
Test status
Simulation time 164700484711 ps
CPU time 1097.82 seconds
Started Mar 31 03:23:35 PM PDT 24
Finished Mar 31 03:41:53 PM PDT 24
Peak memory 200480 kb
Host smart-054dc1d9-6ac8-4363-b564-f47173fe592e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486320204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1486320204
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1088106041
Short name T696
Test name
Test status
Simulation time 12438710806 ps
CPU time 26.38 seconds
Started Mar 31 03:23:35 PM PDT 24
Finished Mar 31 03:24:02 PM PDT 24
Peak memory 200456 kb
Host smart-b83b9055-4cb0-4c14-a5de-42dda2c5f9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088106041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1088106041
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1126090211
Short name T440
Test name
Test status
Simulation time 62661171133 ps
CPU time 77.74 seconds
Started Mar 31 03:23:29 PM PDT 24
Finished Mar 31 03:24:46 PM PDT 24
Peak memory 199628 kb
Host smart-dd114d35-dba1-4a3e-aed0-2093f9a1f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126090211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1126090211
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1807265996
Short name T917
Test name
Test status
Simulation time 12802411214 ps
CPU time 167.4 seconds
Started Mar 31 03:23:33 PM PDT 24
Finished Mar 31 03:26:21 PM PDT 24
Peak memory 200500 kb
Host smart-af277aa2-6c6a-45e3-adfb-db913e8a847c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807265996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1807265996
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2781574346
Short name T90
Test name
Test status
Simulation time 5864372552 ps
CPU time 24.25 seconds
Started Mar 31 03:23:28 PM PDT 24
Finished Mar 31 03:23:53 PM PDT 24
Peak memory 200320 kb
Host smart-f6426ea9-6ab6-4478-b625-b80ebe6ad045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781574346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2781574346
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1436876583
Short name T467
Test name
Test status
Simulation time 380674035904 ps
CPU time 70.52 seconds
Started Mar 31 03:23:30 PM PDT 24
Finished Mar 31 03:24:41 PM PDT 24
Peak memory 200488 kb
Host smart-d0b1f1b3-51af-4e85-bb95-82e1a4335bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436876583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1436876583
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4223991391
Short name T1007
Test name
Test status
Simulation time 597950764 ps
CPU time 0.87 seconds
Started Mar 31 03:23:28 PM PDT 24
Finished Mar 31 03:23:29 PM PDT 24
Peak memory 196132 kb
Host smart-10de5bd2-299b-4522-87a0-8400081ef3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223991391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4223991391
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1760048503
Short name T1106
Test name
Test status
Simulation time 6255831444 ps
CPU time 14.42 seconds
Started Mar 31 03:23:29 PM PDT 24
Finished Mar 31 03:23:44 PM PDT 24
Peak memory 200184 kb
Host smart-2b4f6299-9c5d-4c7b-b92c-ad7a09994e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760048503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1760048503
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1036465831
Short name T121
Test name
Test status
Simulation time 201259615288 ps
CPU time 622.09 seconds
Started Mar 31 03:23:32 PM PDT 24
Finished Mar 31 03:33:55 PM PDT 24
Peak memory 200480 kb
Host smart-970b29aa-9324-4144-b0f0-7171f3d83501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036465831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1036465831
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1866637943
Short name T1040
Test name
Test status
Simulation time 177413372303 ps
CPU time 516.5 seconds
Started Mar 31 03:23:37 PM PDT 24
Finished Mar 31 03:32:14 PM PDT 24
Peak memory 217048 kb
Host smart-5d9fe978-8358-4a60-b4f0-a8c9fcf579d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866637943 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1866637943
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1339010398
Short name T798
Test name
Test status
Simulation time 1464598083 ps
CPU time 3.38 seconds
Started Mar 31 03:23:28 PM PDT 24
Finished Mar 31 03:23:32 PM PDT 24
Peak memory 200000 kb
Host smart-39614387-5b7c-4245-a91f-3301f069c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339010398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1339010398
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2696403443
Short name T32
Test name
Test status
Simulation time 68335708652 ps
CPU time 100.09 seconds
Started Mar 31 03:23:27 PM PDT 24
Finished Mar 31 03:25:07 PM PDT 24
Peak memory 200488 kb
Host smart-edf47b26-c3fc-41a7-998d-0bfcc043c53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696403443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2696403443
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3039860691
Short name T748
Test name
Test status
Simulation time 32165668 ps
CPU time 0.52 seconds
Started Mar 31 03:23:48 PM PDT 24
Finished Mar 31 03:23:49 PM PDT 24
Peak memory 195884 kb
Host smart-203e5dd0-4319-4540-b361-147b99b4ea92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039860691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3039860691
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3577341332
Short name T597
Test name
Test status
Simulation time 153462657459 ps
CPU time 62.89 seconds
Started Mar 31 03:23:43 PM PDT 24
Finished Mar 31 03:24:46 PM PDT 24
Peak memory 200468 kb
Host smart-c1d25671-23d1-4414-ae67-f3199594bbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577341332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3577341332
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4224337120
Short name T1011
Test name
Test status
Simulation time 37319131933 ps
CPU time 29.93 seconds
Started Mar 31 03:23:42 PM PDT 24
Finished Mar 31 03:24:12 PM PDT 24
Peak memory 200412 kb
Host smart-7792b7dc-70d1-4a70-ab21-770341cbc5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224337120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4224337120
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1259472743
Short name T584
Test name
Test status
Simulation time 66780480282 ps
CPU time 26.17 seconds
Started Mar 31 03:23:48 PM PDT 24
Finished Mar 31 03:24:15 PM PDT 24
Peak memory 200616 kb
Host smart-20731aa0-d099-4f5a-bbbb-35486ec5f040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259472743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1259472743
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1525805646
Short name T445
Test name
Test status
Simulation time 45765684173 ps
CPU time 8.73 seconds
Started Mar 31 03:23:42 PM PDT 24
Finished Mar 31 03:23:51 PM PDT 24
Peak memory 200448 kb
Host smart-1acb010c-aa1a-49c8-a6aa-dba78cb3f9c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525805646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1525805646
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2593935449
Short name T670
Test name
Test status
Simulation time 89029016614 ps
CPU time 469.31 seconds
Started Mar 31 03:23:46 PM PDT 24
Finished Mar 31 03:31:35 PM PDT 24
Peak memory 200504 kb
Host smart-62849e7c-74a7-43c9-b9b0-9392f13c9ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593935449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2593935449
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.398118486
Short name T977
Test name
Test status
Simulation time 2121573108 ps
CPU time 4.3 seconds
Started Mar 31 03:23:47 PM PDT 24
Finished Mar 31 03:23:51 PM PDT 24
Peak memory 198940 kb
Host smart-13dd9cf9-3de1-4dfd-89d1-a81984628fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398118486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.398118486
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2991698328
Short name T1167
Test name
Test status
Simulation time 60608080343 ps
CPU time 61.09 seconds
Started Mar 31 03:23:41 PM PDT 24
Finished Mar 31 03:24:42 PM PDT 24
Peak memory 200792 kb
Host smart-b2cf9ef8-b319-41f5-94d5-dc23074ef77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991698328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2991698328
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3080718896
Short name T595
Test name
Test status
Simulation time 4598054475 ps
CPU time 183.45 seconds
Started Mar 31 03:23:53 PM PDT 24
Finished Mar 31 03:26:56 PM PDT 24
Peak memory 200536 kb
Host smart-6f6a305b-7b37-4de6-8a8b-d5fbc142ceab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080718896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3080718896
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2878979722
Short name T788
Test name
Test status
Simulation time 6382938918 ps
CPU time 25.35 seconds
Started Mar 31 03:23:43 PM PDT 24
Finished Mar 31 03:24:09 PM PDT 24
Peak memory 199780 kb
Host smart-11d82e50-ed0f-4266-af40-24b5048f7e57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878979722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2878979722
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2584902347
Short name T933
Test name
Test status
Simulation time 269337058662 ps
CPU time 115.6 seconds
Started Mar 31 03:23:41 PM PDT 24
Finished Mar 31 03:25:36 PM PDT 24
Peak memory 200500 kb
Host smart-dd9e08fa-3904-48f8-b844-1512fc9faf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584902347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2584902347
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4227513804
Short name T369
Test name
Test status
Simulation time 3649994072 ps
CPU time 4.93 seconds
Started Mar 31 03:23:48 PM PDT 24
Finished Mar 31 03:23:53 PM PDT 24
Peak memory 196624 kb
Host smart-3ebebe6c-4cb9-4698-b542-04fe7cdf7404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227513804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4227513804
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.4119382111
Short name T830
Test name
Test status
Simulation time 263374189 ps
CPU time 1.88 seconds
Started Mar 31 03:23:35 PM PDT 24
Finished Mar 31 03:23:37 PM PDT 24
Peak memory 199180 kb
Host smart-68870bb9-2427-406c-a7cc-0da48ac3f19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119382111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4119382111
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2618340619
Short name T421
Test name
Test status
Simulation time 12961034717 ps
CPU time 26.25 seconds
Started Mar 31 03:23:46 PM PDT 24
Finished Mar 31 03:24:13 PM PDT 24
Peak memory 200452 kb
Host smart-8a54fa37-46e2-48a6-8699-9e56fbc1cc0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618340619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2618340619
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.4115486671
Short name T383
Test name
Test status
Simulation time 329286946794 ps
CPU time 747.23 seconds
Started Mar 31 03:23:49 PM PDT 24
Finished Mar 31 03:36:16 PM PDT 24
Peak memory 216404 kb
Host smart-b969204a-1435-4c02-a9cf-f18a40c86ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115486671 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.4115486671
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2354675738
Short name T416
Test name
Test status
Simulation time 6701640150 ps
CPU time 11.96 seconds
Started Mar 31 03:23:49 PM PDT 24
Finished Mar 31 03:24:01 PM PDT 24
Peak memory 200432 kb
Host smart-72930e62-c17c-4a93-9057-fd85f1c98286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354675738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2354675738
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2185027554
Short name T892
Test name
Test status
Simulation time 93339517021 ps
CPU time 297.59 seconds
Started Mar 31 03:23:49 PM PDT 24
Finished Mar 31 03:28:46 PM PDT 24
Peak memory 200584 kb
Host smart-779ddf43-8ce0-4c12-8a6e-49183d0c79b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185027554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2185027554
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2482963111
Short name T554
Test name
Test status
Simulation time 10526809 ps
CPU time 0.55 seconds
Started Mar 31 03:23:59 PM PDT 24
Finished Mar 31 03:24:00 PM PDT 24
Peak memory 195968 kb
Host smart-767dd718-c724-4263-a353-da80bcbc3a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482963111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2482963111
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3543251892
Short name T97
Test name
Test status
Simulation time 90478331403 ps
CPU time 145.61 seconds
Started Mar 31 03:23:48 PM PDT 24
Finished Mar 31 03:26:14 PM PDT 24
Peak memory 200496 kb
Host smart-88e0a425-7ce5-4592-aba0-cdbdaea56a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543251892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3543251892
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.627777904
Short name T1113
Test name
Test status
Simulation time 113304656601 ps
CPU time 46.78 seconds
Started Mar 31 03:23:47 PM PDT 24
Finished Mar 31 03:24:34 PM PDT 24
Peak memory 200520 kb
Host smart-50fb1250-66e9-4e52-a5a7-17d019d1f4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627777904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.627777904
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2078603559
Short name T729
Test name
Test status
Simulation time 33499251294 ps
CPU time 46.43 seconds
Started Mar 31 03:23:47 PM PDT 24
Finished Mar 31 03:24:34 PM PDT 24
Peak memory 200472 kb
Host smart-5e6d0b5b-3e92-447d-aa60-70fed0edaa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078603559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2078603559
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3582083770
Short name T11
Test name
Test status
Simulation time 48006002566 ps
CPU time 91.7 seconds
Started Mar 31 03:23:47 PM PDT 24
Finished Mar 31 03:25:19 PM PDT 24
Peak memory 200492 kb
Host smart-7d129abf-09a7-4e21-b7d0-199dd7c94eab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582083770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3582083770
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4293132148
Short name T495
Test name
Test status
Simulation time 34109064551 ps
CPU time 217.55 seconds
Started Mar 31 03:23:53 PM PDT 24
Finished Mar 31 03:27:31 PM PDT 24
Peak memory 200496 kb
Host smart-9f9f2c34-f5cc-4b00-9b85-554d7dcae27e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293132148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4293132148
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.35064462
Short name T1121
Test name
Test status
Simulation time 2856982933 ps
CPU time 2.32 seconds
Started Mar 31 03:23:54 PM PDT 24
Finished Mar 31 03:23:56 PM PDT 24
Peak memory 199180 kb
Host smart-43f23a79-6c3e-4872-ae5e-ed0f51949a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35064462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.35064462
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.160860871
Short name T583
Test name
Test status
Simulation time 46295774550 ps
CPU time 61.31 seconds
Started Mar 31 03:23:52 PM PDT 24
Finished Mar 31 03:24:53 PM PDT 24
Peak memory 200736 kb
Host smart-204849fd-06f5-4cdb-8a0c-c4674311f221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160860871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.160860871
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.963363265
Short name T458
Test name
Test status
Simulation time 16118686563 ps
CPU time 203.52 seconds
Started Mar 31 03:23:53 PM PDT 24
Finished Mar 31 03:27:17 PM PDT 24
Peak memory 200496 kb
Host smart-f803d12e-c09f-4ee2-bdd5-64c349da0dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963363265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.963363265
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.346475484
Short name T352
Test name
Test status
Simulation time 7016722751 ps
CPU time 67.69 seconds
Started Mar 31 03:23:47 PM PDT 24
Finished Mar 31 03:24:55 PM PDT 24
Peak memory 198936 kb
Host smart-3a1cbf0c-6378-43d1-bea0-aa10a2edb690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346475484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.346475484
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2319354488
Short name T398
Test name
Test status
Simulation time 20881536355 ps
CPU time 30.9 seconds
Started Mar 31 03:23:52 PM PDT 24
Finished Mar 31 03:24:23 PM PDT 24
Peak memory 200448 kb
Host smart-b82fe039-23db-4484-a25c-e06389a62a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319354488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2319354488
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2424106431
Short name T609
Test name
Test status
Simulation time 48498425503 ps
CPU time 36.89 seconds
Started Mar 31 03:23:52 PM PDT 24
Finished Mar 31 03:24:29 PM PDT 24
Peak memory 196200 kb
Host smart-5e2ef155-4209-4fca-aa2b-a997ec130069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424106431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2424106431
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2090571978
Short name T1074
Test name
Test status
Simulation time 5455218675 ps
CPU time 12.43 seconds
Started Mar 31 03:23:46 PM PDT 24
Finished Mar 31 03:23:58 PM PDT 24
Peak memory 199672 kb
Host smart-46c52129-5613-4298-a75e-a0a4834ab499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090571978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2090571978
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.303071627
Short name T841
Test name
Test status
Simulation time 173182894182 ps
CPU time 284.31 seconds
Started Mar 31 03:23:53 PM PDT 24
Finished Mar 31 03:28:37 PM PDT 24
Peak memory 200468 kb
Host smart-cb751eba-4d75-4ef0-8e74-82b32aa88bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303071627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.303071627
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.604877473
Short name T861
Test name
Test status
Simulation time 489602840 ps
CPU time 1.54 seconds
Started Mar 31 03:23:53 PM PDT 24
Finished Mar 31 03:23:55 PM PDT 24
Peak memory 200212 kb
Host smart-b59d1d72-00a8-4a71-aaee-1910e2fa803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604877473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.604877473
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3249989100
Short name T450
Test name
Test status
Simulation time 76909750881 ps
CPU time 46.56 seconds
Started Mar 31 03:23:53 PM PDT 24
Finished Mar 31 03:24:39 PM PDT 24
Peak memory 200556 kb
Host smart-2abfa6bb-2835-47d3-8595-97f6ad4f181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249989100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3249989100
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.501372807
Short name T527
Test name
Test status
Simulation time 41801961 ps
CPU time 0.57 seconds
Started Mar 31 03:24:03 PM PDT 24
Finished Mar 31 03:24:04 PM PDT 24
Peak memory 195908 kb
Host smart-7125b7c8-206d-4166-a952-88ae8a5db462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501372807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.501372807
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1902858256
Short name T1088
Test name
Test status
Simulation time 20768178569 ps
CPU time 35.56 seconds
Started Mar 31 03:23:59 PM PDT 24
Finished Mar 31 03:24:35 PM PDT 24
Peak memory 200388 kb
Host smart-d7282a7a-e292-457b-b0f5-478045573c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902858256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1902858256
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2895574203
Short name T1006
Test name
Test status
Simulation time 31679240713 ps
CPU time 52.06 seconds
Started Mar 31 03:23:58 PM PDT 24
Finished Mar 31 03:24:50 PM PDT 24
Peak memory 200520 kb
Host smart-b5cabe42-cfd8-4fb2-bc66-9d5bd6724cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895574203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2895574203
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3008892470
Short name T157
Test name
Test status
Simulation time 16022787918 ps
CPU time 18.98 seconds
Started Mar 31 03:23:58 PM PDT 24
Finished Mar 31 03:24:17 PM PDT 24
Peak memory 199896 kb
Host smart-1c10b31f-a55c-4d5d-b13d-2bb1a7e5b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008892470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3008892470
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3232511154
Short name T589
Test name
Test status
Simulation time 186319496483 ps
CPU time 288.63 seconds
Started Mar 31 03:23:59 PM PDT 24
Finished Mar 31 03:28:48 PM PDT 24
Peak memory 197748 kb
Host smart-3a60ed0e-2259-400b-a78d-092f4651ef74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232511154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3232511154
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2348192773
Short name T249
Test name
Test status
Simulation time 130587303412 ps
CPU time 768.28 seconds
Started Mar 31 03:24:04 PM PDT 24
Finished Mar 31 03:36:52 PM PDT 24
Peak memory 200468 kb
Host smart-76123ea4-035b-4c2d-9e6d-d5d7baf211a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348192773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2348192773
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2780992448
Short name T587
Test name
Test status
Simulation time 5306799958 ps
CPU time 3.05 seconds
Started Mar 31 03:24:03 PM PDT 24
Finished Mar 31 03:24:06 PM PDT 24
Peak memory 199388 kb
Host smart-d12d8f71-21ee-47a4-bffd-a0886ec83288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780992448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2780992448
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.135851688
Short name T1138
Test name
Test status
Simulation time 123781879565 ps
CPU time 45.71 seconds
Started Mar 31 03:23:57 PM PDT 24
Finished Mar 31 03:24:43 PM PDT 24
Peak memory 200680 kb
Host smart-e31a3115-8c03-4319-bbb9-b83185bf173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135851688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.135851688
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1319630947
Short name T359
Test name
Test status
Simulation time 21639192623 ps
CPU time 540.41 seconds
Started Mar 31 03:24:06 PM PDT 24
Finished Mar 31 03:33:06 PM PDT 24
Peak memory 200480 kb
Host smart-48b13909-8e64-460b-ac87-81fd475d87be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319630947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1319630947
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2409176640
Short name T353
Test name
Test status
Simulation time 6613383854 ps
CPU time 34.3 seconds
Started Mar 31 03:23:58 PM PDT 24
Finished Mar 31 03:24:32 PM PDT 24
Peak memory 199900 kb
Host smart-2c68ff3a-8581-4a29-9340-935b43d6f39d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409176640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2409176640
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4283811048
Short name T769
Test name
Test status
Simulation time 46060484975 ps
CPU time 89.72 seconds
Started Mar 31 03:23:59 PM PDT 24
Finished Mar 31 03:25:29 PM PDT 24
Peak memory 200484 kb
Host smart-303d3230-5f8f-4d0e-84c6-210f1538eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283811048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4283811048
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.895651426
Short name T464
Test name
Test status
Simulation time 68765275133 ps
CPU time 22.89 seconds
Started Mar 31 03:23:58 PM PDT 24
Finished Mar 31 03:24:21 PM PDT 24
Peak memory 196480 kb
Host smart-95f20784-0f2a-41a8-a270-76bc829d6c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895651426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.895651426
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4147396083
Short name T717
Test name
Test status
Simulation time 658238783 ps
CPU time 1.84 seconds
Started Mar 31 03:23:59 PM PDT 24
Finished Mar 31 03:24:01 PM PDT 24
Peak memory 198816 kb
Host smart-ff19de63-1ca2-4b9e-88ee-8f4ee872f6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147396083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4147396083
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3142486958
Short name T64
Test name
Test status
Simulation time 145521119361 ps
CPU time 549.13 seconds
Started Mar 31 03:24:04 PM PDT 24
Finished Mar 31 03:33:13 PM PDT 24
Peak memory 208944 kb
Host smart-ab1d9c9a-56d4-44a6-abef-f171eb7d9d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142486958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3142486958
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2738412125
Short name T1111
Test name
Test status
Simulation time 76162904174 ps
CPU time 394.58 seconds
Started Mar 31 03:24:06 PM PDT 24
Finished Mar 31 03:30:41 PM PDT 24
Peak memory 211676 kb
Host smart-6c6f97a4-7b46-4194-a038-c427418a8b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738412125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2738412125
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3219307540
Short name T289
Test name
Test status
Simulation time 7474262457 ps
CPU time 8.77 seconds
Started Mar 31 03:24:03 PM PDT 24
Finished Mar 31 03:24:12 PM PDT 24
Peak memory 200044 kb
Host smart-cf99e16b-e36b-42a9-8a05-9ca97dcd64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219307540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3219307540
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3553638517
Short name T571
Test name
Test status
Simulation time 110252887409 ps
CPU time 145.04 seconds
Started Mar 31 03:23:58 PM PDT 24
Finished Mar 31 03:26:23 PM PDT 24
Peak memory 200564 kb
Host smart-3a268f73-ff0e-48fc-b6d8-be5e6e2a0f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553638517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3553638517
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1238170232
Short name T997
Test name
Test status
Simulation time 14736208 ps
CPU time 0.53 seconds
Started Mar 31 03:24:16 PM PDT 24
Finished Mar 31 03:24:17 PM PDT 24
Peak memory 195872 kb
Host smart-c3b9f4c1-a814-4ea2-a359-c4349be6789e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238170232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1238170232
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.436634069
Short name T1023
Test name
Test status
Simulation time 117288465418 ps
CPU time 106.47 seconds
Started Mar 31 03:24:04 PM PDT 24
Finished Mar 31 03:25:51 PM PDT 24
Peak memory 200516 kb
Host smart-54174de0-6ffe-4dd5-b870-7060f7907737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436634069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.436634069
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3700354609
Short name T857
Test name
Test status
Simulation time 91308377481 ps
CPU time 77.34 seconds
Started Mar 31 03:24:05 PM PDT 24
Finished Mar 31 03:25:22 PM PDT 24
Peak memory 200476 kb
Host smart-32a6a154-e65a-446f-af47-a320cc49c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700354609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3700354609
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2070789763
Short name T891
Test name
Test status
Simulation time 9532851002 ps
CPU time 13.53 seconds
Started Mar 31 03:24:12 PM PDT 24
Finished Mar 31 03:24:26 PM PDT 24
Peak memory 200508 kb
Host smart-1e414716-ec0a-4530-a630-4d620545eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070789763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2070789763
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1502068214
Short name T490
Test name
Test status
Simulation time 15982521156 ps
CPU time 8.65 seconds
Started Mar 31 03:24:10 PM PDT 24
Finished Mar 31 03:24:19 PM PDT 24
Peak memory 198208 kb
Host smart-6dbbbc8d-5b96-4dab-8059-d2b436cf699e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502068214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1502068214
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2517674137
Short name T459
Test name
Test status
Simulation time 93664898747 ps
CPU time 295.05 seconds
Started Mar 31 03:24:15 PM PDT 24
Finished Mar 31 03:29:10 PM PDT 24
Peak memory 200472 kb
Host smart-2d462706-cb90-4a99-ab83-bb7234f3d13a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517674137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2517674137
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2034454186
Short name T335
Test name
Test status
Simulation time 5254539622 ps
CPU time 12.88 seconds
Started Mar 31 03:24:11 PM PDT 24
Finished Mar 31 03:24:24 PM PDT 24
Peak memory 200448 kb
Host smart-20e0d176-8c97-4827-b0b7-e3c8690953aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034454186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2034454186
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3853412824
Short name T304
Test name
Test status
Simulation time 87980429095 ps
CPU time 63.04 seconds
Started Mar 31 03:24:11 PM PDT 24
Finished Mar 31 03:25:14 PM PDT 24
Peak memory 200680 kb
Host smart-000f8427-03f9-4167-80a3-bf35e445afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853412824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3853412824
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3513268894
Short name T914
Test name
Test status
Simulation time 5904366341 ps
CPU time 167.84 seconds
Started Mar 31 03:24:15 PM PDT 24
Finished Mar 31 03:27:05 PM PDT 24
Peak memory 200244 kb
Host smart-d248b33f-08d5-4f50-968c-a31a8008d87e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513268894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3513268894
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1228798868
Short name T715
Test name
Test status
Simulation time 3396640481 ps
CPU time 14.21 seconds
Started Mar 31 03:24:11 PM PDT 24
Finished Mar 31 03:24:25 PM PDT 24
Peak memory 198572 kb
Host smart-b0974120-6785-402c-a1a4-f7b185f340e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228798868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1228798868
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.677419524
Short name T617
Test name
Test status
Simulation time 124861037460 ps
CPU time 48.95 seconds
Started Mar 31 03:24:10 PM PDT 24
Finished Mar 31 03:24:59 PM PDT 24
Peak memory 200452 kb
Host smart-0ae73ce0-6759-43f4-9270-1628cfffc030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677419524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.677419524
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.958777350
Short name T739
Test name
Test status
Simulation time 4255501952 ps
CPU time 3.61 seconds
Started Mar 31 03:24:15 PM PDT 24
Finished Mar 31 03:24:20 PM PDT 24
Peak memory 196272 kb
Host smart-0b9547f8-8aed-444f-8120-c08166d21d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958777350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.958777350
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1005732147
Short name T431
Test name
Test status
Simulation time 704622475 ps
CPU time 1.88 seconds
Started Mar 31 03:24:03 PM PDT 24
Finished Mar 31 03:24:05 PM PDT 24
Peak memory 198816 kb
Host smart-59957476-bfeb-44db-87a4-2353517b07de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005732147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1005732147
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3123736891
Short name T701
Test name
Test status
Simulation time 16844160420 ps
CPU time 36.51 seconds
Started Mar 31 03:24:17 PM PDT 24
Finished Mar 31 03:24:54 PM PDT 24
Peak memory 200460 kb
Host smart-d2d1079e-d50d-4d72-8153-3075bb12449c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123736891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3123736891
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.870891610
Short name T54
Test name
Test status
Simulation time 70247946080 ps
CPU time 511.45 seconds
Started Mar 31 03:24:16 PM PDT 24
Finished Mar 31 03:32:48 PM PDT 24
Peak memory 216996 kb
Host smart-f6dd780b-33bb-4c6a-999c-ef61b600667f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870891610 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.870891610
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.737049454
Short name T411
Test name
Test status
Simulation time 437651167 ps
CPU time 1.53 seconds
Started Mar 31 03:24:13 PM PDT 24
Finished Mar 31 03:24:14 PM PDT 24
Peak memory 197620 kb
Host smart-cea1c16f-464b-4ad2-b1c2-b7e3a031fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737049454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.737049454
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.318721690
Short name T928
Test name
Test status
Simulation time 38297754951 ps
CPU time 69.16 seconds
Started Mar 31 03:24:05 PM PDT 24
Finished Mar 31 03:25:14 PM PDT 24
Peak memory 200420 kb
Host smart-9bfd2d76-cedd-4f5c-b833-b81dc9249865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318721690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.318721690
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1978400907
Short name T1125
Test name
Test status
Simulation time 14610897 ps
CPU time 0.56 seconds
Started Mar 31 03:24:26 PM PDT 24
Finished Mar 31 03:24:27 PM PDT 24
Peak memory 195872 kb
Host smart-c902c221-dec3-408d-84c6-d1657bf4c54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978400907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1978400907
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2300475886
Short name T693
Test name
Test status
Simulation time 61434850485 ps
CPU time 20.09 seconds
Started Mar 31 03:24:17 PM PDT 24
Finished Mar 31 03:24:38 PM PDT 24
Peak memory 200348 kb
Host smart-2eeba01f-c592-4297-8f46-8b8c76f80a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300475886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2300475886
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1625630176
Short name T149
Test name
Test status
Simulation time 43582973309 ps
CPU time 75.41 seconds
Started Mar 31 03:24:23 PM PDT 24
Finished Mar 31 03:25:39 PM PDT 24
Peak memory 200500 kb
Host smart-ff4f7412-896f-41de-8044-df8e9d3e8750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625630176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1625630176
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3149106376
Short name T833
Test name
Test status
Simulation time 99994165283 ps
CPU time 11.22 seconds
Started Mar 31 03:24:21 PM PDT 24
Finished Mar 31 03:24:33 PM PDT 24
Peak memory 200252 kb
Host smart-f8960327-ee43-466d-abbb-487b25016eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149106376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3149106376
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.427991593
Short name T659
Test name
Test status
Simulation time 248501999965 ps
CPU time 389.18 seconds
Started Mar 31 03:24:22 PM PDT 24
Finished Mar 31 03:30:52 PM PDT 24
Peak memory 199044 kb
Host smart-c2d6ff0f-54f2-4fa5-aba9-a418311b8f27
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427991593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.427991593
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3769046953
Short name T965
Test name
Test status
Simulation time 143583035809 ps
CPU time 541.29 seconds
Started Mar 31 03:24:27 PM PDT 24
Finished Mar 31 03:33:29 PM PDT 24
Peak memory 200488 kb
Host smart-7e9d637b-2a42-4184-b7fa-3697924f2bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769046953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3769046953
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1548916827
Short name T850
Test name
Test status
Simulation time 7108216317 ps
CPU time 5.6 seconds
Started Mar 31 03:24:29 PM PDT 24
Finished Mar 31 03:24:35 PM PDT 24
Peak memory 199712 kb
Host smart-7702bc6d-ef63-486e-b607-d40391912b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548916827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1548916827
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.399502143
Short name T986
Test name
Test status
Simulation time 24819648319 ps
CPU time 124.36 seconds
Started Mar 31 03:24:29 PM PDT 24
Finished Mar 31 03:26:33 PM PDT 24
Peak memory 199088 kb
Host smart-3b2e2b20-3667-451f-acc2-60d0da159ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399502143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.399502143
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4262340021
Short name T622
Test name
Test status
Simulation time 12827640529 ps
CPU time 175.37 seconds
Started Mar 31 03:24:27 PM PDT 24
Finished Mar 31 03:27:23 PM PDT 24
Peak memory 200488 kb
Host smart-533252c8-a660-470a-9e7f-451cf8d66322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262340021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4262340021
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.209492761
Short name T888
Test name
Test status
Simulation time 6480420297 ps
CPU time 14.17 seconds
Started Mar 31 03:24:23 PM PDT 24
Finished Mar 31 03:24:38 PM PDT 24
Peak memory 198496 kb
Host smart-a77fd64a-f7f6-4b61-8217-789b6e76b2f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209492761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.209492761
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.308695020
Short name T700
Test name
Test status
Simulation time 52235923419 ps
CPU time 41.55 seconds
Started Mar 31 03:24:28 PM PDT 24
Finished Mar 31 03:25:10 PM PDT 24
Peak memory 200432 kb
Host smart-47d58a28-4ca9-4e52-a236-01444bb499ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308695020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.308695020
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2498658925
Short name T698
Test name
Test status
Simulation time 40922335751 ps
CPU time 4.81 seconds
Started Mar 31 03:24:28 PM PDT 24
Finished Mar 31 03:24:34 PM PDT 24
Peak memory 196512 kb
Host smart-c9654561-05c6-4245-b87a-6412a3d75416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498658925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2498658925
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1561790706
Short name T681
Test name
Test status
Simulation time 10570966063 ps
CPU time 52.84 seconds
Started Mar 31 03:24:19 PM PDT 24
Finished Mar 31 03:25:12 PM PDT 24
Peak memory 200416 kb
Host smart-87db5948-e61a-47f5-ad32-e7753d9abe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561790706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1561790706
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1524909780
Short name T15
Test name
Test status
Simulation time 131811971501 ps
CPU time 520.58 seconds
Started Mar 31 03:24:29 PM PDT 24
Finished Mar 31 03:33:11 PM PDT 24
Peak memory 208972 kb
Host smart-c9bdc25c-a321-458b-87aa-8709f445706b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524909780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1524909780
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1857498640
Short name T732
Test name
Test status
Simulation time 162382687863 ps
CPU time 483.85 seconds
Started Mar 31 03:24:29 PM PDT 24
Finished Mar 31 03:32:33 PM PDT 24
Peak memory 216980 kb
Host smart-a49aae03-6f91-41de-8bdb-010a68819f23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857498640 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1857498640
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.54405529
Short name T425
Test name
Test status
Simulation time 1454757103 ps
CPU time 4.71 seconds
Started Mar 31 03:24:28 PM PDT 24
Finished Mar 31 03:24:33 PM PDT 24
Peak memory 199436 kb
Host smart-40e569f8-3f4a-46a4-b08d-5437740d8b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54405529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.54405529
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1577060723
Short name T482
Test name
Test status
Simulation time 12526496842 ps
CPU time 10.59 seconds
Started Mar 31 03:24:16 PM PDT 24
Finished Mar 31 03:24:27 PM PDT 24
Peak memory 200248 kb
Host smart-36196893-a71e-45b1-a50d-1498f05ae654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577060723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1577060723
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2496258942
Short name T743
Test name
Test status
Simulation time 10351606 ps
CPU time 0.52 seconds
Started Mar 31 03:24:38 PM PDT 24
Finished Mar 31 03:24:39 PM PDT 24
Peak memory 194860 kb
Host smart-6a140860-c627-487d-b3a8-d2536bcc861f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496258942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2496258942
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3059917395
Short name T281
Test name
Test status
Simulation time 210206882914 ps
CPU time 315.03 seconds
Started Mar 31 03:24:28 PM PDT 24
Finished Mar 31 03:29:44 PM PDT 24
Peak memory 200472 kb
Host smart-35df1a8d-64c5-454d-9aff-dbb5e817ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059917395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3059917395
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3913575890
Short name T792
Test name
Test status
Simulation time 39624636528 ps
CPU time 14.93 seconds
Started Mar 31 03:24:26 PM PDT 24
Finished Mar 31 03:24:42 PM PDT 24
Peak memory 200412 kb
Host smart-586ec932-9afd-4144-b6db-b0dee1d065ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913575890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3913575890
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3662970481
Short name T376
Test name
Test status
Simulation time 98396605819 ps
CPU time 67.89 seconds
Started Mar 31 03:24:27 PM PDT 24
Finished Mar 31 03:25:35 PM PDT 24
Peak memory 200412 kb
Host smart-a99e4f89-3463-4f94-8916-29ce60d57cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662970481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3662970481
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.4272841927
Short name T918
Test name
Test status
Simulation time 52955786313 ps
CPU time 26.51 seconds
Started Mar 31 03:24:33 PM PDT 24
Finished Mar 31 03:24:59 PM PDT 24
Peak memory 200444 kb
Host smart-82d9cfca-7f10-4d2d-9861-836d75afe647
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272841927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4272841927
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3296119883
Short name T1019
Test name
Test status
Simulation time 62698159982 ps
CPU time 380.06 seconds
Started Mar 31 03:24:32 PM PDT 24
Finished Mar 31 03:30:52 PM PDT 24
Peak memory 200560 kb
Host smart-3f3709cd-b80e-4bb8-bf8d-9ef82e67b471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296119883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3296119883
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.261076383
Short name T488
Test name
Test status
Simulation time 12631654268 ps
CPU time 14.18 seconds
Started Mar 31 03:24:34 PM PDT 24
Finished Mar 31 03:24:48 PM PDT 24
Peak memory 200524 kb
Host smart-cbeded87-1f3a-413e-8ec3-5437d89a4760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261076383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.261076383
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.37323624
Short name T827
Test name
Test status
Simulation time 539121013120 ps
CPU time 92.58 seconds
Started Mar 31 03:24:34 PM PDT 24
Finished Mar 31 03:26:06 PM PDT 24
Peak memory 208780 kb
Host smart-723de8f7-a9de-4634-8921-0db056f50ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37323624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.37323624
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.107537363
Short name T1056
Test name
Test status
Simulation time 12172143241 ps
CPU time 719.98 seconds
Started Mar 31 03:24:34 PM PDT 24
Finished Mar 31 03:36:34 PM PDT 24
Peak memory 200508 kb
Host smart-fab5c3ed-89db-4a27-b944-c5f5101651b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107537363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.107537363
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.5161704
Short name T664
Test name
Test status
Simulation time 5254488487 ps
CPU time 45.81 seconds
Started Mar 31 03:24:32 PM PDT 24
Finished Mar 31 03:25:18 PM PDT 24
Peak memory 199696 kb
Host smart-c8d92f98-75b7-4d17-838b-09e8dc839b65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5161704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.5161704
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2079219699
Short name T154
Test name
Test status
Simulation time 116610498825 ps
CPU time 238.57 seconds
Started Mar 31 03:24:33 PM PDT 24
Finished Mar 31 03:28:32 PM PDT 24
Peak memory 200532 kb
Host smart-87bbe70a-78e8-48fd-a2f7-e5a1aed071fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079219699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2079219699
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1255557174
Short name T10
Test name
Test status
Simulation time 3723371065 ps
CPU time 6.61 seconds
Started Mar 31 03:24:33 PM PDT 24
Finished Mar 31 03:24:40 PM PDT 24
Peak memory 196480 kb
Host smart-3a05d50b-48f6-44d1-a5c3-3f3a58254474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255557174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1255557174
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1372192235
Short name T4
Test name
Test status
Simulation time 319064456 ps
CPU time 1.02 seconds
Started Mar 31 03:24:26 PM PDT 24
Finished Mar 31 03:24:28 PM PDT 24
Peak memory 198908 kb
Host smart-7390598d-670f-47ad-a85f-7cf6c305569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372192235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1372192235
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2473106372
Short name T150
Test name
Test status
Simulation time 362333081440 ps
CPU time 121.39 seconds
Started Mar 31 03:24:38 PM PDT 24
Finished Mar 31 03:26:40 PM PDT 24
Peak memory 200512 kb
Host smart-82b6a3f0-c501-4cdf-80e3-57edf89f2d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473106372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2473106372
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1876384612
Short name T85
Test name
Test status
Simulation time 100537298273 ps
CPU time 457.33 seconds
Started Mar 31 03:24:40 PM PDT 24
Finished Mar 31 03:32:18 PM PDT 24
Peak memory 217060 kb
Host smart-b205a3d8-da99-4e62-9c3b-a491f1a31948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876384612 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1876384612
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1263958194
Short name T998
Test name
Test status
Simulation time 6528922731 ps
CPU time 9.02 seconds
Started Mar 31 03:24:33 PM PDT 24
Finished Mar 31 03:24:42 PM PDT 24
Peak memory 200456 kb
Host smart-beb7aab6-dc49-402c-aa9e-8a4672bab744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263958194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1263958194
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2056527461
Short name T299
Test name
Test status
Simulation time 99328591913 ps
CPU time 61.37 seconds
Started Mar 31 03:24:27 PM PDT 24
Finished Mar 31 03:25:29 PM PDT 24
Peak memory 200464 kb
Host smart-4d5ed135-0ce8-4460-aecb-0d94ed0b4a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056527461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2056527461
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3819487598
Short name T847
Test name
Test status
Simulation time 31200828 ps
CPU time 0.6 seconds
Started Mar 31 03:16:14 PM PDT 24
Finished Mar 31 03:16:14 PM PDT 24
Peak memory 194836 kb
Host smart-241b5922-3bb8-47d7-9867-2aa3f906c1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819487598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3819487598
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2725830087
Short name T475
Test name
Test status
Simulation time 217767827358 ps
CPU time 518.02 seconds
Started Mar 31 03:15:56 PM PDT 24
Finished Mar 31 03:24:34 PM PDT 24
Peak memory 200540 kb
Host smart-d83c0781-1e29-46c0-ae52-21f9260beeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725830087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2725830087
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2646586365
Short name T831
Test name
Test status
Simulation time 152617809394 ps
CPU time 52.61 seconds
Started Mar 31 03:15:56 PM PDT 24
Finished Mar 31 03:16:49 PM PDT 24
Peak memory 200468 kb
Host smart-24216dcd-e23f-4695-822c-cd64a0bdabc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646586365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2646586365
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.3893928134
Short name T1060
Test name
Test status
Simulation time 15680054925 ps
CPU time 6.99 seconds
Started Mar 31 03:16:02 PM PDT 24
Finished Mar 31 03:16:09 PM PDT 24
Peak memory 200468 kb
Host smart-ffb75964-64f8-444e-a879-4d9127dd0eca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893928134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3893928134
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.265806204
Short name T247
Test name
Test status
Simulation time 85732584894 ps
CPU time 129.44 seconds
Started Mar 31 03:16:10 PM PDT 24
Finished Mar 31 03:18:19 PM PDT 24
Peak memory 200480 kb
Host smart-fe1727ad-0258-4657-9494-43afd1e01266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265806204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.265806204
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2782209019
Short name T724
Test name
Test status
Simulation time 74713232 ps
CPU time 0.61 seconds
Started Mar 31 03:16:09 PM PDT 24
Finished Mar 31 03:16:10 PM PDT 24
Peak memory 196260 kb
Host smart-e7cb546b-e15e-4958-b5bf-95fe4f9173e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782209019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2782209019
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2408553031
Short name T913
Test name
Test status
Simulation time 216839673691 ps
CPU time 60.31 seconds
Started Mar 31 03:16:05 PM PDT 24
Finished Mar 31 03:17:05 PM PDT 24
Peak memory 208996 kb
Host smart-656bae65-0be0-486d-8237-a0b3119cff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408553031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2408553031
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3716137186
Short name T384
Test name
Test status
Simulation time 9419820923 ps
CPU time 464.31 seconds
Started Mar 31 03:16:07 PM PDT 24
Finished Mar 31 03:23:52 PM PDT 24
Peak memory 200432 kb
Host smart-61ba8abe-b06a-4ef4-8047-c1760cb67b27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716137186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3716137186
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.494133459
Short name T420
Test name
Test status
Simulation time 6159434773 ps
CPU time 18.42 seconds
Started Mar 31 03:16:03 PM PDT 24
Finished Mar 31 03:16:22 PM PDT 24
Peak memory 199252 kb
Host smart-a3f1c2af-2714-499e-86d8-f159508f6b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494133459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.494133459
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.635529500
Short name T128
Test name
Test status
Simulation time 58976211299 ps
CPU time 29.7 seconds
Started Mar 31 03:16:02 PM PDT 24
Finished Mar 31 03:16:32 PM PDT 24
Peak memory 200524 kb
Host smart-95d2352c-3708-4566-ba0a-509ad3d98d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635529500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.635529500
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3501208376
Short name T360
Test name
Test status
Simulation time 34051529717 ps
CPU time 13.7 seconds
Started Mar 31 03:16:03 PM PDT 24
Finished Mar 31 03:16:17 PM PDT 24
Peak memory 196468 kb
Host smart-e5bc285e-4bec-4eb9-960f-12cd7d22b805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501208376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3501208376
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1532226242
Short name T309
Test name
Test status
Simulation time 5522838442 ps
CPU time 6.9 seconds
Started Mar 31 03:15:50 PM PDT 24
Finished Mar 31 03:15:57 PM PDT 24
Peak memory 200360 kb
Host smart-43ecefd3-dee6-4aba-817b-14bed9297f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532226242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1532226242
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2185933281
Short name T707
Test name
Test status
Simulation time 38170613648 ps
CPU time 42 seconds
Started Mar 31 03:16:14 PM PDT 24
Finished Mar 31 03:16:56 PM PDT 24
Peak memory 200396 kb
Host smart-436eae32-0360-48e7-8fd4-177c6f705d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185933281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2185933281
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.198686255
Short name T557
Test name
Test status
Simulation time 24512056542 ps
CPU time 674.34 seconds
Started Mar 31 03:16:07 PM PDT 24
Finished Mar 31 03:27:22 PM PDT 24
Peak memory 208676 kb
Host smart-1f9e794a-5411-43da-bacc-aa36fd5ae1bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198686255 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.198686255
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1589171628
Short name T610
Test name
Test status
Simulation time 7935301458 ps
CPU time 12.66 seconds
Started Mar 31 03:16:01 PM PDT 24
Finished Mar 31 03:16:14 PM PDT 24
Peak memory 200252 kb
Host smart-2cae9cef-94ac-4ed7-b4bd-90cbebc1ef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589171628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1589171628
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3677642211
Short name T723
Test name
Test status
Simulation time 82576681936 ps
CPU time 30.3 seconds
Started Mar 31 03:15:56 PM PDT 24
Finished Mar 31 03:16:26 PM PDT 24
Peak memory 200444 kb
Host smart-8f297f36-38f8-4b09-8508-467b74a48687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677642211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3677642211
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1126261111
Short name T327
Test name
Test status
Simulation time 18550573358 ps
CPU time 110.84 seconds
Started Mar 31 03:24:39 PM PDT 24
Finished Mar 31 03:26:31 PM PDT 24
Peak memory 200500 kb
Host smart-11b2a4f6-89ef-45f4-9709-4a5c7df590ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126261111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1126261111
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2491962789
Short name T912
Test name
Test status
Simulation time 238844207707 ps
CPU time 1374.54 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:47:41 PM PDT 24
Peak memory 226412 kb
Host smart-2255426e-e79b-42e5-97dc-4838feb0847f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491962789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2491962789
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.256023370
Short name T310
Test name
Test status
Simulation time 58701116778 ps
CPU time 85.85 seconds
Started Mar 31 03:24:38 PM PDT 24
Finished Mar 31 03:26:04 PM PDT 24
Peak memory 200432 kb
Host smart-5738877b-5fa8-4a7a-a6c0-9d5762dbbe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256023370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.256023370
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.4093982412
Short name T494
Test name
Test status
Simulation time 47090071041 ps
CPU time 499.91 seconds
Started Mar 31 03:24:38 PM PDT 24
Finished Mar 31 03:32:59 PM PDT 24
Peak memory 216996 kb
Host smart-d8d199de-5919-4495-9395-aa5e073681c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093982412 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4093982412
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3426325336
Short name T1048
Test name
Test status
Simulation time 42328357760 ps
CPU time 77.14 seconds
Started Mar 31 03:24:40 PM PDT 24
Finished Mar 31 03:25:57 PM PDT 24
Peak memory 200488 kb
Host smart-f0ca0bf8-1955-42aa-91c7-eea03c784f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426325336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3426325336
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.151517560
Short name T84
Test name
Test status
Simulation time 35699846686 ps
CPU time 337.61 seconds
Started Mar 31 03:24:38 PM PDT 24
Finished Mar 31 03:30:15 PM PDT 24
Peak memory 209828 kb
Host smart-451e03b2-e47d-4587-92b8-2381a4cbb6a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151517560 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.151517560
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3892079779
Short name T159
Test name
Test status
Simulation time 236139079009 ps
CPU time 112.42 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:26:38 PM PDT 24
Peak memory 200472 kb
Host smart-c4e90537-3761-4485-946b-611d622d2f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892079779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3892079779
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.630415702
Short name T160
Test name
Test status
Simulation time 134632341420 ps
CPU time 1088.56 seconds
Started Mar 31 03:24:43 PM PDT 24
Finished Mar 31 03:42:52 PM PDT 24
Peak memory 233652 kb
Host smart-1708db17-b6ce-4136-b5f2-c0fcbe2a5f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630415702 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.630415702
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1028193341
Short name T786
Test name
Test status
Simulation time 202203110319 ps
CPU time 41.36 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:25:28 PM PDT 24
Peak memory 200404 kb
Host smart-9071e8c8-fc54-4387-ac06-3e65126c7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028193341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1028193341
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3781833987
Short name T1123
Test name
Test status
Simulation time 25309627293 ps
CPU time 236.83 seconds
Started Mar 31 03:24:45 PM PDT 24
Finished Mar 31 03:28:42 PM PDT 24
Peak memory 217220 kb
Host smart-57d51c74-6ad5-4df8-a2d0-a5c22b6c8c41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781833987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3781833987
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1365803503
Short name T1149
Test name
Test status
Simulation time 69075166249 ps
CPU time 114.47 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:26:41 PM PDT 24
Peak memory 200456 kb
Host smart-428ce867-de8b-452a-a455-89c046847052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365803503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1365803503
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3844457101
Short name T819
Test name
Test status
Simulation time 88907245468 ps
CPU time 136.53 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:27:03 PM PDT 24
Peak memory 200320 kb
Host smart-18c7b780-4355-4177-83a3-f1f8e6615f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844457101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3844457101
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3289782871
Short name T179
Test name
Test status
Simulation time 40754316263 ps
CPU time 18.43 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:25:05 PM PDT 24
Peak memory 200368 kb
Host smart-6b056a42-738b-4ebb-9031-5a4805d82eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289782871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3289782871
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2184377897
Short name T529
Test name
Test status
Simulation time 22692065186 ps
CPU time 267.99 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:29:14 PM PDT 24
Peak memory 217204 kb
Host smart-78200d6a-55da-4778-b0e2-53208edeeecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184377897 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2184377897
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3824955788
Short name T805
Test name
Test status
Simulation time 95567582276 ps
CPU time 74.82 seconds
Started Mar 31 03:24:46 PM PDT 24
Finished Mar 31 03:26:01 PM PDT 24
Peak memory 200436 kb
Host smart-1acf4ddf-8271-48e8-923f-f9307247c736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824955788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3824955788
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.402767598
Short name T105
Test name
Test status
Simulation time 27124260483 ps
CPU time 169.92 seconds
Started Mar 31 03:24:53 PM PDT 24
Finished Mar 31 03:27:44 PM PDT 24
Peak memory 210588 kb
Host smart-141dff6f-e444-437e-922a-c4152e330f67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402767598 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.402767598
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3567546391
Short name T1
Test name
Test status
Simulation time 52502352346 ps
CPU time 20.57 seconds
Started Mar 31 03:24:53 PM PDT 24
Finished Mar 31 03:25:14 PM PDT 24
Peak memory 200492 kb
Host smart-30a22c1a-6e4e-4f5f-9dbe-ddb9878f3213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567546391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3567546391
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3482248712
Short name T653
Test name
Test status
Simulation time 12231052 ps
CPU time 0.54 seconds
Started Mar 31 03:16:29 PM PDT 24
Finished Mar 31 03:16:29 PM PDT 24
Peak memory 195840 kb
Host smart-22ddadd1-e151-4d9d-b1f1-b7a1e93280a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482248712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3482248712
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.979498904
Short name T165
Test name
Test status
Simulation time 236994210228 ps
CPU time 196.33 seconds
Started Mar 31 03:16:18 PM PDT 24
Finished Mar 31 03:19:34 PM PDT 24
Peak memory 200524 kb
Host smart-c53d17b8-c88b-4a07-8506-ed201e9fb287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979498904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.979498904
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3920406071
Short name T560
Test name
Test status
Simulation time 109568357169 ps
CPU time 193.91 seconds
Started Mar 31 03:16:15 PM PDT 24
Finished Mar 31 03:19:29 PM PDT 24
Peak memory 200420 kb
Host smart-a92ec80e-596c-457c-b8c2-e79dd90773bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920406071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3920406071
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.967256165
Short name T361
Test name
Test status
Simulation time 70202976934 ps
CPU time 29.21 seconds
Started Mar 31 03:16:13 PM PDT 24
Finished Mar 31 03:16:42 PM PDT 24
Peak memory 200528 kb
Host smart-0b338665-f427-4598-a068-103fa922b099
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967256165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.967256165
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3584207616
Short name T1117
Test name
Test status
Simulation time 105543587272 ps
CPU time 655.98 seconds
Started Mar 31 03:16:28 PM PDT 24
Finished Mar 31 03:27:24 PM PDT 24
Peak memory 200476 kb
Host smart-a9b3af04-54ff-4cd0-a617-c4dd8b321983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584207616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3584207616
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3092135027
Short name T549
Test name
Test status
Simulation time 11638776758 ps
CPU time 5.49 seconds
Started Mar 31 03:16:20 PM PDT 24
Finished Mar 31 03:16:26 PM PDT 24
Peak memory 200492 kb
Host smart-fa04426e-7110-4bb7-ad5c-7b7a3e7c2208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092135027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3092135027
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2128595175
Short name T387
Test name
Test status
Simulation time 25038406301 ps
CPU time 21.67 seconds
Started Mar 31 03:16:17 PM PDT 24
Finished Mar 31 03:16:39 PM PDT 24
Peak memory 199332 kb
Host smart-c1ea6faf-b55a-479c-b26c-c0bf609fb30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128595175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2128595175
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.620677362
Short name T296
Test name
Test status
Simulation time 26778502651 ps
CPU time 264.81 seconds
Started Mar 31 03:16:24 PM PDT 24
Finished Mar 31 03:20:49 PM PDT 24
Peak memory 200524 kb
Host smart-5d888456-ac6e-4a4a-847c-c64ae01a288f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620677362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.620677362
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1780928961
Short name T558
Test name
Test status
Simulation time 1168333043 ps
CPU time 2.41 seconds
Started Mar 31 03:16:13 PM PDT 24
Finished Mar 31 03:16:16 PM PDT 24
Peak memory 197428 kb
Host smart-0d25e99f-4d82-4e1c-8290-fbc3092f9134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780928961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1780928961
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3743594742
Short name T1037
Test name
Test status
Simulation time 50915163556 ps
CPU time 20.83 seconds
Started Mar 31 03:16:15 PM PDT 24
Finished Mar 31 03:16:36 PM PDT 24
Peak memory 196236 kb
Host smart-46774be2-570a-40ec-88e0-f80c9647d006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743594742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3743594742
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.805921113
Short name T1082
Test name
Test status
Simulation time 688822560 ps
CPU time 1.7 seconds
Started Mar 31 03:16:16 PM PDT 24
Finished Mar 31 03:16:18 PM PDT 24
Peak memory 199264 kb
Host smart-d63e525a-5103-40a8-997c-08ecdcc97a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805921113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.805921113
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2068562083
Short name T510
Test name
Test status
Simulation time 18513364751 ps
CPU time 202.17 seconds
Started Mar 31 03:16:24 PM PDT 24
Finished Mar 31 03:19:47 PM PDT 24
Peak memory 216076 kb
Host smart-05f2d8e0-58b8-4450-b781-f9272919c1cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068562083 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2068562083
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.150824930
Short name T1109
Test name
Test status
Simulation time 881998454 ps
CPU time 3.15 seconds
Started Mar 31 03:16:17 PM PDT 24
Finished Mar 31 03:16:20 PM PDT 24
Peak memory 198900 kb
Host smart-32489e85-ffdb-4457-84ad-e746aed6fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150824930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.150824930
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.284674712
Short name T862
Test name
Test status
Simulation time 121444406139 ps
CPU time 113.62 seconds
Started Mar 31 03:16:14 PM PDT 24
Finished Mar 31 03:18:07 PM PDT 24
Peak memory 200468 kb
Host smart-07d00efd-e641-4eba-adbe-911f79f26411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284674712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.284674712
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1875454247
Short name T607
Test name
Test status
Simulation time 17043120622 ps
CPU time 13.43 seconds
Started Mar 31 03:24:52 PM PDT 24
Finished Mar 31 03:25:06 PM PDT 24
Peak memory 200496 kb
Host smart-5de94c7a-abc5-40c8-91c6-3ce185307aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875454247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1875454247
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.293877805
Short name T331
Test name
Test status
Simulation time 1174130499004 ps
CPU time 839.76 seconds
Started Mar 31 03:24:53 PM PDT 24
Finished Mar 31 03:38:54 PM PDT 24
Peak memory 225372 kb
Host smart-fac874dc-c060-4f77-8660-5893ed3253eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293877805 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.293877805
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4151779075
Short name T686
Test name
Test status
Simulation time 6365643737 ps
CPU time 6.47 seconds
Started Mar 31 03:24:51 PM PDT 24
Finished Mar 31 03:24:57 PM PDT 24
Peak memory 200520 kb
Host smart-9730c97d-10aa-4722-ba0c-b561d12918b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151779075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4151779075
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3942021011
Short name T699
Test name
Test status
Simulation time 38952945447 ps
CPU time 278.02 seconds
Started Mar 31 03:24:50 PM PDT 24
Finished Mar 31 03:29:28 PM PDT 24
Peak memory 214056 kb
Host smart-50e57e24-c71f-4f40-81e7-40437e10e7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942021011 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3942021011
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.292163749
Short name T585
Test name
Test status
Simulation time 94585358999 ps
CPU time 70.35 seconds
Started Mar 31 03:24:51 PM PDT 24
Finished Mar 31 03:26:01 PM PDT 24
Peak memory 200476 kb
Host smart-f2558eb4-b346-4249-b914-6f1e38da63b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292163749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.292163749
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1089309265
Short name T761
Test name
Test status
Simulation time 94478536497 ps
CPU time 399.52 seconds
Started Mar 31 03:24:50 PM PDT 24
Finished Mar 31 03:31:30 PM PDT 24
Peak memory 225484 kb
Host smart-f298db85-85d5-4935-a24d-85bd40b827e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089309265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1089309265
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1258151346
Short name T630
Test name
Test status
Simulation time 133075726626 ps
CPU time 234.16 seconds
Started Mar 31 03:24:55 PM PDT 24
Finished Mar 31 03:28:50 PM PDT 24
Peak memory 216888 kb
Host smart-5f788d09-9c09-4267-badf-aebdb2ee4fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258151346 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1258151346
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3085086408
Short name T175
Test name
Test status
Simulation time 18037031147 ps
CPU time 30.18 seconds
Started Mar 31 03:24:56 PM PDT 24
Finished Mar 31 03:25:26 PM PDT 24
Peak memory 200512 kb
Host smart-3ea57583-1648-40e0-ae97-0d3af94798c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085086408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3085086408
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3778569233
Short name T705
Test name
Test status
Simulation time 74178034997 ps
CPU time 963.83 seconds
Started Mar 31 03:24:55 PM PDT 24
Finished Mar 31 03:40:59 PM PDT 24
Peak memory 216688 kb
Host smart-0ddc8b08-d535-4605-bbf0-b079a4c83c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778569233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3778569233
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.837113945
Short name T439
Test name
Test status
Simulation time 251771200150 ps
CPU time 29.43 seconds
Started Mar 31 03:24:57 PM PDT 24
Finished Mar 31 03:25:27 PM PDT 24
Peak memory 200416 kb
Host smart-92522b3f-453c-44ff-a747-a2ea57a4a10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837113945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.837113945
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.647933173
Short name T426
Test name
Test status
Simulation time 43052827234 ps
CPU time 447.43 seconds
Started Mar 31 03:24:56 PM PDT 24
Finished Mar 31 03:32:23 PM PDT 24
Peak memory 210540 kb
Host smart-2b9ae0af-4ff5-4f83-af03-e60055467aae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647933173 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.647933173
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1817583153
Short name T542
Test name
Test status
Simulation time 20804959871 ps
CPU time 54.92 seconds
Started Mar 31 03:24:58 PM PDT 24
Finished Mar 31 03:25:53 PM PDT 24
Peak memory 200460 kb
Host smart-a353026e-856b-4a66-88fd-973abd690317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817583153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1817583153
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3057310464
Short name T315
Test name
Test status
Simulation time 34347739754 ps
CPU time 630.06 seconds
Started Mar 31 03:24:54 PM PDT 24
Finished Mar 31 03:35:24 PM PDT 24
Peak memory 208676 kb
Host smart-93229a0a-0f4a-46ca-91a1-c4cc95b03705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057310464 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3057310464
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1238599325
Short name T1143
Test name
Test status
Simulation time 154808901183 ps
CPU time 67.91 seconds
Started Mar 31 03:24:57 PM PDT 24
Finished Mar 31 03:26:05 PM PDT 24
Peak memory 200412 kb
Host smart-505608ed-d455-4838-bed7-a1adc3b21724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238599325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1238599325
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.4011250800
Short name T41
Test name
Test status
Simulation time 237964975597 ps
CPU time 746.46 seconds
Started Mar 31 03:24:58 PM PDT 24
Finished Mar 31 03:37:24 PM PDT 24
Peak memory 228380 kb
Host smart-a774ecd2-e0cd-4735-a5d4-9bc5997040c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011250800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.4011250800
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.4163126096
Short name T546
Test name
Test status
Simulation time 29447073945 ps
CPU time 49.93 seconds
Started Mar 31 03:25:04 PM PDT 24
Finished Mar 31 03:25:54 PM PDT 24
Peak memory 200428 kb
Host smart-884bae6a-3445-4cee-b022-037448e59dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163126096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4163126096
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2675357592
Short name T1015
Test name
Test status
Simulation time 185733300997 ps
CPU time 137.68 seconds
Started Mar 31 03:25:03 PM PDT 24
Finished Mar 31 03:27:21 PM PDT 24
Peak memory 200548 kb
Host smart-b43d06f8-cdf5-452e-b98c-d365b98fdaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675357592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2675357592
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.515022444
Short name T889
Test name
Test status
Simulation time 26417287105 ps
CPU time 311.46 seconds
Started Mar 31 03:25:03 PM PDT 24
Finished Mar 31 03:30:14 PM PDT 24
Peak memory 217236 kb
Host smart-c1937b2e-c008-4d69-bf5c-3f55987698b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515022444 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.515022444
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.505281580
Short name T577
Test name
Test status
Simulation time 19698577 ps
CPU time 0.53 seconds
Started Mar 31 03:16:41 PM PDT 24
Finished Mar 31 03:16:41 PM PDT 24
Peak memory 195864 kb
Host smart-e42073f5-a3b1-4013-bf91-3c9af24f362e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505281580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.505281580
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.849253695
Short name T1101
Test name
Test status
Simulation time 25936261663 ps
CPU time 21.01 seconds
Started Mar 31 03:16:29 PM PDT 24
Finished Mar 31 03:16:50 PM PDT 24
Peak memory 200412 kb
Host smart-613d3e2b-2c0d-4fa5-9ddc-e05630ad84df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849253695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.849253695
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3903480308
Short name T667
Test name
Test status
Simulation time 23859731260 ps
CPU time 43.09 seconds
Started Mar 31 03:16:24 PM PDT 24
Finished Mar 31 03:17:07 PM PDT 24
Peak memory 200392 kb
Host smart-68f0162c-ebb1-449a-95a8-b0a93db21c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903480308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3903480308
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1211396966
Short name T1166
Test name
Test status
Simulation time 16807234436 ps
CPU time 32.19 seconds
Started Mar 31 03:16:30 PM PDT 24
Finished Mar 31 03:17:02 PM PDT 24
Peak memory 200488 kb
Host smart-e32fd00a-520e-4eab-b5c2-df42982b8d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211396966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1211396966
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1576922770
Short name T562
Test name
Test status
Simulation time 9437932249 ps
CPU time 14.8 seconds
Started Mar 31 03:16:31 PM PDT 24
Finished Mar 31 03:16:46 PM PDT 24
Peak memory 199320 kb
Host smart-7dcaa834-adbc-4e6a-8839-9c771b35f5c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576922770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1576922770
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2785663882
Short name T373
Test name
Test status
Simulation time 137607198642 ps
CPU time 155.73 seconds
Started Mar 31 03:16:41 PM PDT 24
Finished Mar 31 03:19:16 PM PDT 24
Peak memory 200500 kb
Host smart-519f331d-decf-4694-82a0-3c1e96656d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785663882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2785663882
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.43372571
Short name T468
Test name
Test status
Simulation time 8247977718 ps
CPU time 15.04 seconds
Started Mar 31 03:16:36 PM PDT 24
Finished Mar 31 03:16:51 PM PDT 24
Peak memory 200388 kb
Host smart-5d2f150c-36ad-468f-816b-c0293370e278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43372571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.43372571
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.379006869
Short name T627
Test name
Test status
Simulation time 115473255149 ps
CPU time 133.37 seconds
Started Mar 31 03:16:29 PM PDT 24
Finished Mar 31 03:18:42 PM PDT 24
Peak memory 200684 kb
Host smart-f1bb30d5-50c1-4ab2-b130-a4cee37c082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379006869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.379006869
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.924329166
Short name T256
Test name
Test status
Simulation time 27851206043 ps
CPU time 661 seconds
Started Mar 31 03:16:36 PM PDT 24
Finished Mar 31 03:27:38 PM PDT 24
Peak memory 200520 kb
Host smart-8e860747-8d7e-4d77-bf5d-eb9aab31783d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924329166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.924329166
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.367901579
Short name T909
Test name
Test status
Simulation time 2039109722 ps
CPU time 2.57 seconds
Started Mar 31 03:16:30 PM PDT 24
Finished Mar 31 03:16:32 PM PDT 24
Peak memory 198852 kb
Host smart-ca0b5e36-2bea-4ab8-9392-8d8394224444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367901579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.367901579
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2140225576
Short name T472
Test name
Test status
Simulation time 286323480479 ps
CPU time 25.92 seconds
Started Mar 31 03:16:32 PM PDT 24
Finished Mar 31 03:16:58 PM PDT 24
Peak memory 200392 kb
Host smart-943bcfed-7b0e-48f9-b76d-5b3bc6dd00c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140225576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2140225576
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3382396921
Short name T276
Test name
Test status
Simulation time 4966335350 ps
CPU time 4.44 seconds
Started Mar 31 03:16:32 PM PDT 24
Finished Mar 31 03:16:36 PM PDT 24
Peak memory 196520 kb
Host smart-7576a4e5-ba9f-42f2-9e73-4c6931edbdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382396921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3382396921
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2081741877
Short name T286
Test name
Test status
Simulation time 887624848 ps
CPU time 3.96 seconds
Started Mar 31 03:16:24 PM PDT 24
Finished Mar 31 03:16:28 PM PDT 24
Peak memory 199200 kb
Host smart-8c226634-150d-4475-ba26-b2be8310bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081741877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2081741877
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3699853192
Short name T400
Test name
Test status
Simulation time 202110601512 ps
CPU time 247.65 seconds
Started Mar 31 03:16:42 PM PDT 24
Finished Mar 31 03:20:50 PM PDT 24
Peak memory 200492 kb
Host smart-92660a6a-5ac6-4ef0-843c-40aa951fe7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699853192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3699853192
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.250984871
Short name T1126
Test name
Test status
Simulation time 28127073952 ps
CPU time 330.81 seconds
Started Mar 31 03:16:42 PM PDT 24
Finished Mar 31 03:22:13 PM PDT 24
Peak memory 208740 kb
Host smart-520a5a47-73c1-4fb2-83b2-a20375b1e809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250984871 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.250984871
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3511109474
Short name T523
Test name
Test status
Simulation time 1140300960 ps
CPU time 4.16 seconds
Started Mar 31 03:16:30 PM PDT 24
Finished Mar 31 03:16:34 PM PDT 24
Peak memory 199792 kb
Host smart-3ed7dbbb-84db-4619-82e2-47f790a95111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511109474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3511109474
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3775781563
Short name T109
Test name
Test status
Simulation time 26547294988 ps
CPU time 56.97 seconds
Started Mar 31 03:16:25 PM PDT 24
Finished Mar 31 03:17:22 PM PDT 24
Peak memory 200400 kb
Host smart-fe2f3151-05cd-433b-96f8-e90991b5942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775781563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3775781563
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.334328238
Short name T1114
Test name
Test status
Simulation time 53709820938 ps
CPU time 24.14 seconds
Started Mar 31 03:25:03 PM PDT 24
Finished Mar 31 03:25:27 PM PDT 24
Peak memory 200408 kb
Host smart-e32ab695-4918-46ca-aced-64e13c8ab90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334328238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.334328238
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.109964212
Short name T211
Test name
Test status
Simulation time 503569678160 ps
CPU time 328.11 seconds
Started Mar 31 03:25:03 PM PDT 24
Finished Mar 31 03:30:31 PM PDT 24
Peak memory 217100 kb
Host smart-7b1b437f-1dfd-4c65-b004-fce58a462d55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109964212 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.109964212
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1512801988
Short name T180
Test name
Test status
Simulation time 38351620056 ps
CPU time 39.18 seconds
Started Mar 31 03:25:01 PM PDT 24
Finished Mar 31 03:25:41 PM PDT 24
Peak memory 200376 kb
Host smart-6b01cc86-c268-4353-b97c-dc2498cc85ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512801988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1512801988
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3939940771
Short name T83
Test name
Test status
Simulation time 80755057376 ps
CPU time 422.6 seconds
Started Mar 31 03:25:01 PM PDT 24
Finished Mar 31 03:32:05 PM PDT 24
Peak memory 211048 kb
Host smart-123f38f3-dc1f-4aad-9cc4-29ede09f2a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939940771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3939940771
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.4033854135
Short name T181
Test name
Test status
Simulation time 89607381985 ps
CPU time 122.57 seconds
Started Mar 31 03:25:03 PM PDT 24
Finished Mar 31 03:27:06 PM PDT 24
Peak memory 200428 kb
Host smart-8b7f110b-dac3-4ff2-a744-9e06653621a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033854135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4033854135
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2510447741
Short name T45
Test name
Test status
Simulation time 314956312231 ps
CPU time 911.57 seconds
Started Mar 31 03:25:00 PM PDT 24
Finished Mar 31 03:40:12 PM PDT 24
Peak memory 226232 kb
Host smart-2a06b982-af55-4b2c-ae0c-3503f4841b52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510447741 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2510447741
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.4100140153
Short name T803
Test name
Test status
Simulation time 217149887246 ps
CPU time 578.3 seconds
Started Mar 31 03:25:08 PM PDT 24
Finished Mar 31 03:34:46 PM PDT 24
Peak memory 217320 kb
Host smart-b2b27c99-f213-45f9-bfa0-8c0c7081b766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100140153 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.4100140153
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1560231399
Short name T114
Test name
Test status
Simulation time 135203183671 ps
CPU time 357.03 seconds
Started Mar 31 03:25:09 PM PDT 24
Finished Mar 31 03:31:06 PM PDT 24
Peak memory 200488 kb
Host smart-b98641a5-5005-485a-bfcc-01942c2bb2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560231399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1560231399
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2925061146
Short name T828
Test name
Test status
Simulation time 13637922211 ps
CPU time 21.85 seconds
Started Mar 31 03:25:08 PM PDT 24
Finished Mar 31 03:25:30 PM PDT 24
Peak memory 200372 kb
Host smart-6fdcedfa-6e88-4756-9d30-dbb2da70badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925061146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2925061146
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3814585114
Short name T27
Test name
Test status
Simulation time 61714477538 ps
CPU time 722.06 seconds
Started Mar 31 03:25:09 PM PDT 24
Finished Mar 31 03:37:11 PM PDT 24
Peak memory 225408 kb
Host smart-4dcf0054-2b4d-4447-bed9-4a783110d157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814585114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3814585114
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.979706845
Short name T834
Test name
Test status
Simulation time 27409677943 ps
CPU time 24.41 seconds
Started Mar 31 03:25:09 PM PDT 24
Finished Mar 31 03:25:33 PM PDT 24
Peak memory 200492 kb
Host smart-c1356381-fa7b-4223-8587-f9c74f0249a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979706845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.979706845
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1465550819
Short name T1027
Test name
Test status
Simulation time 127473599787 ps
CPU time 55.82 seconds
Started Mar 31 03:25:09 PM PDT 24
Finished Mar 31 03:26:05 PM PDT 24
Peak memory 200492 kb
Host smart-c719ce37-202e-4b65-8b17-890fb365f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465550819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1465550819
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3048609077
Short name T47
Test name
Test status
Simulation time 141393829107 ps
CPU time 231.29 seconds
Started Mar 31 03:25:06 PM PDT 24
Finished Mar 31 03:28:58 PM PDT 24
Peak memory 216896 kb
Host smart-a2b83d46-eb20-4a89-9ba2-cf2846720d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048609077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3048609077
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.4277955541
Short name T324
Test name
Test status
Simulation time 99520365270 ps
CPU time 117.05 seconds
Started Mar 31 03:25:10 PM PDT 24
Finished Mar 31 03:27:07 PM PDT 24
Peak memory 200324 kb
Host smart-3a8c0b57-48d0-43e3-90c2-8585076b1a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277955541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.4277955541
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4270817218
Short name T44
Test name
Test status
Simulation time 66110379662 ps
CPU time 339.25 seconds
Started Mar 31 03:25:09 PM PDT 24
Finished Mar 31 03:30:49 PM PDT 24
Peak memory 217200 kb
Host smart-e57354f8-192e-429b-9444-e45f3380057e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270817218 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4270817218
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.584756815
Short name T220
Test name
Test status
Simulation time 51183339392 ps
CPU time 44.72 seconds
Started Mar 31 03:25:09 PM PDT 24
Finished Mar 31 03:25:54 PM PDT 24
Peak memory 200504 kb
Host smart-02b6597a-0360-4e1f-90bc-9f18be976bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584756815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.584756815
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.656611331
Short name T940
Test name
Test status
Simulation time 62539678253 ps
CPU time 711.95 seconds
Started Mar 31 03:25:08 PM PDT 24
Finished Mar 31 03:37:00 PM PDT 24
Peak memory 216280 kb
Host smart-e3e763da-370c-4b60-9710-de2fff26c4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656611331 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.656611331
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.989094524
Short name T569
Test name
Test status
Simulation time 25154495 ps
CPU time 0.55 seconds
Started Mar 31 03:16:56 PM PDT 24
Finished Mar 31 03:16:56 PM PDT 24
Peak memory 195824 kb
Host smart-5093bf05-c674-4d3b-a612-9e648e21cabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989094524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.989094524
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2985264794
Short name T388
Test name
Test status
Simulation time 58835609204 ps
CPU time 42.62 seconds
Started Mar 31 03:16:47 PM PDT 24
Finished Mar 31 03:17:30 PM PDT 24
Peak memory 200492 kb
Host smart-14865495-6dfa-49fd-8607-50103d61a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985264794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2985264794
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1589571757
Short name T1018
Test name
Test status
Simulation time 27002167204 ps
CPU time 9.81 seconds
Started Mar 31 03:16:46 PM PDT 24
Finished Mar 31 03:16:56 PM PDT 24
Peak memory 200328 kb
Host smart-b147fbb3-8f76-4145-bc5a-22450731c9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589571757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1589571757
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3299344940
Short name T646
Test name
Test status
Simulation time 124340099737 ps
CPU time 213.72 seconds
Started Mar 31 03:16:47 PM PDT 24
Finished Mar 31 03:20:21 PM PDT 24
Peak memory 200524 kb
Host smart-fa2797fc-644c-4ae5-9fca-d924306b7833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299344940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3299344940
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3941292515
Short name T410
Test name
Test status
Simulation time 70209732737 ps
CPU time 26.79 seconds
Started Mar 31 03:16:46 PM PDT 24
Finished Mar 31 03:17:13 PM PDT 24
Peak memory 200392 kb
Host smart-adabf8c0-bff8-427d-8a36-24ff6cc7a3a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941292515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3941292515
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3033670774
Short name T711
Test name
Test status
Simulation time 128864699572 ps
CPU time 852.91 seconds
Started Mar 31 03:16:51 PM PDT 24
Finished Mar 31 03:31:04 PM PDT 24
Peak memory 200492 kb
Host smart-3bce4c09-d7d0-48a4-8aa1-7726114d1dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033670774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3033670774
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.826669497
Short name T941
Test name
Test status
Simulation time 3420105256 ps
CPU time 1.5 seconds
Started Mar 31 03:16:52 PM PDT 24
Finished Mar 31 03:16:54 PM PDT 24
Peak memory 199576 kb
Host smart-78e49f6d-751e-4523-b472-afbd59836fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826669497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.826669497
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3928101526
Short name T994
Test name
Test status
Simulation time 54076531456 ps
CPU time 24.7 seconds
Started Mar 31 03:16:45 PM PDT 24
Finished Mar 31 03:17:10 PM PDT 24
Peak memory 199476 kb
Host smart-d1a60777-6af5-4873-ad9f-31a4a93507e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928101526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3928101526
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2618896063
Short name T736
Test name
Test status
Simulation time 9089747855 ps
CPU time 169.93 seconds
Started Mar 31 03:16:52 PM PDT 24
Finished Mar 31 03:19:42 PM PDT 24
Peak memory 200444 kb
Host smart-2187e3c4-9704-4f42-af0c-7513feb37446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618896063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2618896063
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1306530703
Short name T855
Test name
Test status
Simulation time 6126491715 ps
CPU time 54.78 seconds
Started Mar 31 03:16:46 PM PDT 24
Finished Mar 31 03:17:41 PM PDT 24
Peak memory 198676 kb
Host smart-04b007f5-a703-41ae-b06d-8e8b763d9ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306530703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1306530703
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2434494413
Short name T251
Test name
Test status
Simulation time 15104874277 ps
CPU time 22.93 seconds
Started Mar 31 03:16:46 PM PDT 24
Finished Mar 31 03:17:09 PM PDT 24
Peak memory 200424 kb
Host smart-01d9db5f-1609-42e9-bdff-1ee063332bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434494413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2434494413
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2545346962
Short name T760
Test name
Test status
Simulation time 39477618309 ps
CPU time 14.42 seconds
Started Mar 31 03:16:48 PM PDT 24
Finished Mar 31 03:17:03 PM PDT 24
Peak memory 196720 kb
Host smart-98e1bdfc-c271-4435-90cd-e4ed37124629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545346962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2545346962
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1195426988
Short name T771
Test name
Test status
Simulation time 6071878083 ps
CPU time 19.27 seconds
Started Mar 31 03:16:47 PM PDT 24
Finished Mar 31 03:17:06 PM PDT 24
Peak memory 200480 kb
Host smart-85f92cd2-5819-46ee-bb58-3319c8d86e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195426988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1195426988
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.62188267
Short name T395
Test name
Test status
Simulation time 182932288723 ps
CPU time 869.57 seconds
Started Mar 31 03:16:56 PM PDT 24
Finished Mar 31 03:31:26 PM PDT 24
Peak memory 200500 kb
Host smart-83a5bb83-88c4-431e-8c38-4d80d9d988e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62188267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.62188267
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.641644818
Short name T1039
Test name
Test status
Simulation time 32676558159 ps
CPU time 599.83 seconds
Started Mar 31 03:16:51 PM PDT 24
Finished Mar 31 03:26:51 PM PDT 24
Peak memory 217176 kb
Host smart-e60fb07b-0ec1-4137-a2c2-b8bb0bdc8c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641644818 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.641644818
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3615778394
Short name T291
Test name
Test status
Simulation time 6957310457 ps
CPU time 10.98 seconds
Started Mar 31 03:16:53 PM PDT 24
Finished Mar 31 03:17:04 PM PDT 24
Peak memory 199812 kb
Host smart-93fc4ead-2700-4dc5-991a-768e8d6e1974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615778394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3615778394
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1535787838
Short name T935
Test name
Test status
Simulation time 103380310858 ps
CPU time 80.69 seconds
Started Mar 31 03:16:48 PM PDT 24
Finished Mar 31 03:18:09 PM PDT 24
Peak memory 200676 kb
Host smart-ae4e6476-74ad-4134-9d48-48e0181ff589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535787838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1535787838
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2542839082
Short name T801
Test name
Test status
Simulation time 115971515891 ps
CPU time 48.99 seconds
Started Mar 31 03:25:15 PM PDT 24
Finished Mar 31 03:26:04 PM PDT 24
Peak memory 200432 kb
Host smart-5b79742b-b8ab-42bb-93cf-7bc5fecd6ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542839082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2542839082
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3799216957
Short name T46
Test name
Test status
Simulation time 52082138524 ps
CPU time 657.49 seconds
Started Mar 31 03:25:15 PM PDT 24
Finished Mar 31 03:36:13 PM PDT 24
Peak memory 225460 kb
Host smart-88b05de8-82c2-4de7-89c2-fc8f66cff71f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799216957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3799216957
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3389425574
Short name T749
Test name
Test status
Simulation time 208152508528 ps
CPU time 93.34 seconds
Started Mar 31 03:25:15 PM PDT 24
Finished Mar 31 03:26:49 PM PDT 24
Peak memory 200524 kb
Host smart-97914d87-d231-4040-a5b4-3c458f7dcf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389425574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3389425574
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3863837776
Short name T763
Test name
Test status
Simulation time 95165205488 ps
CPU time 1136.53 seconds
Started Mar 31 03:25:16 PM PDT 24
Finished Mar 31 03:44:13 PM PDT 24
Peak memory 225440 kb
Host smart-8c17d08b-0cc6-4a77-a89b-542271ac12b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863837776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3863837776
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1900243696
Short name T237
Test name
Test status
Simulation time 25272452704 ps
CPU time 76.1 seconds
Started Mar 31 03:25:15 PM PDT 24
Finished Mar 31 03:26:31 PM PDT 24
Peak memory 200484 kb
Host smart-827d4ffb-9ca3-4a66-9ec6-9f885b442a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900243696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1900243696
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3284508554
Short name T42
Test name
Test status
Simulation time 303028934091 ps
CPU time 978.9 seconds
Started Mar 31 03:25:16 PM PDT 24
Finished Mar 31 03:41:35 PM PDT 24
Peak memory 227360 kb
Host smart-f549ebc6-b3a7-475c-bd5c-dce42144564c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284508554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3284508554
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2626411963
Short name T374
Test name
Test status
Simulation time 102221491875 ps
CPU time 127.38 seconds
Started Mar 31 03:25:15 PM PDT 24
Finished Mar 31 03:27:22 PM PDT 24
Peak memory 200464 kb
Host smart-d6b64c98-f1cc-492e-bb1b-3c214257fe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626411963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2626411963
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3636867770
Short name T923
Test name
Test status
Simulation time 23649094115 ps
CPU time 215.43 seconds
Started Mar 31 03:25:15 PM PDT 24
Finished Mar 31 03:28:51 PM PDT 24
Peak memory 216252 kb
Host smart-01672dc4-82ec-4ce0-9bc8-6061819a50df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636867770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3636867770
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3464101896
Short name T236
Test name
Test status
Simulation time 81994463415 ps
CPU time 17.17 seconds
Started Mar 31 03:25:16 PM PDT 24
Finished Mar 31 03:25:33 PM PDT 24
Peak memory 200488 kb
Host smart-01f1e891-d002-43af-a02e-f29947bd36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464101896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3464101896
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2166700130
Short name T592
Test name
Test status
Simulation time 36895730354 ps
CPU time 158.55 seconds
Started Mar 31 03:25:15 PM PDT 24
Finished Mar 31 03:27:54 PM PDT 24
Peak memory 208744 kb
Host smart-1b90d506-0f4f-47f2-bb77-c5f1625bc9ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166700130 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2166700130
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2492505938
Short name T839
Test name
Test status
Simulation time 72653092093 ps
CPU time 121.97 seconds
Started Mar 31 03:25:22 PM PDT 24
Finished Mar 31 03:27:24 PM PDT 24
Peak memory 200420 kb
Host smart-5ae00b64-ee85-4ccc-b96d-79c8443010fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492505938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2492505938
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2471655073
Short name T665
Test name
Test status
Simulation time 150022230653 ps
CPU time 211.13 seconds
Started Mar 31 03:25:22 PM PDT 24
Finished Mar 31 03:28:54 PM PDT 24
Peak memory 208900 kb
Host smart-7f4d1c23-7c2d-4581-b1ad-4d4786f4afff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471655073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2471655073
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2451969916
Short name T320
Test name
Test status
Simulation time 27933018817 ps
CPU time 26.63 seconds
Started Mar 31 03:25:22 PM PDT 24
Finished Mar 31 03:25:49 PM PDT 24
Peak memory 200512 kb
Host smart-607b9b49-c273-4488-8657-e5951995307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451969916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2451969916
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2619260993
Short name T456
Test name
Test status
Simulation time 146154555831 ps
CPU time 1021.45 seconds
Started Mar 31 03:25:21 PM PDT 24
Finished Mar 31 03:42:23 PM PDT 24
Peak memory 225416 kb
Host smart-c050b78d-139b-439b-918b-5023368b901d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619260993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2619260993
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3753874347
Short name T949
Test name
Test status
Simulation time 114373312186 ps
CPU time 195.35 seconds
Started Mar 31 03:25:21 PM PDT 24
Finished Mar 31 03:28:37 PM PDT 24
Peak memory 200532 kb
Host smart-113bdfb3-4238-4fcc-8df0-e721c7d336bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753874347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3753874347
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3656963668
Short name T591
Test name
Test status
Simulation time 122224588793 ps
CPU time 1124.12 seconds
Started Mar 31 03:25:22 PM PDT 24
Finished Mar 31 03:44:06 PM PDT 24
Peak memory 225452 kb
Host smart-1335a164-7207-48f8-aa50-acead55275fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656963668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3656963668
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1192596524
Short name T132
Test name
Test status
Simulation time 108015125538 ps
CPU time 74.47 seconds
Started Mar 31 03:25:21 PM PDT 24
Finished Mar 31 03:26:36 PM PDT 24
Peak memory 200400 kb
Host smart-f5cae02a-0ca0-4a6a-b50b-5781206a0bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192596524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1192596524
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2091874276
Short name T312
Test name
Test status
Simulation time 59711952256 ps
CPU time 649.59 seconds
Started Mar 31 03:25:22 PM PDT 24
Finished Mar 31 03:36:12 PM PDT 24
Peak memory 225408 kb
Host smart-1bd3e6d3-f831-41d8-a2bc-79544543d1f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091874276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2091874276
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3243134712
Short name T178
Test name
Test status
Simulation time 71868481306 ps
CPU time 106.81 seconds
Started Mar 31 03:25:22 PM PDT 24
Finished Mar 31 03:27:09 PM PDT 24
Peak memory 200484 kb
Host smart-e18dcb6b-8191-4f02-8673-5f281192cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243134712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3243134712
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2528040733
Short name T730
Test name
Test status
Simulation time 91855184753 ps
CPU time 253.91 seconds
Started Mar 31 03:25:28 PM PDT 24
Finished Mar 31 03:29:42 PM PDT 24
Peak memory 217104 kb
Host smart-013de71c-9bf3-4eb9-ada8-55332bf8d8f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528040733 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2528040733
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4160379290
Short name T344
Test name
Test status
Simulation time 29892470 ps
CPU time 0.63 seconds
Started Mar 31 03:17:11 PM PDT 24
Finished Mar 31 03:17:12 PM PDT 24
Peak memory 195856 kb
Host smart-08d5ca46-fdc9-48af-956c-6dbb4cb8a782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160379290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4160379290
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1262648366
Short name T430
Test name
Test status
Simulation time 93454544067 ps
CPU time 142.43 seconds
Started Mar 31 03:16:57 PM PDT 24
Finished Mar 31 03:19:20 PM PDT 24
Peak memory 200488 kb
Host smart-7edf7724-4fca-4230-99dc-3633567f5b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262648366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1262648366
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3694057820
Short name T283
Test name
Test status
Simulation time 25907710550 ps
CPU time 36.02 seconds
Started Mar 31 03:17:03 PM PDT 24
Finished Mar 31 03:17:39 PM PDT 24
Peak memory 200456 kb
Host smart-99fa97bf-b4e2-4655-a81d-da4f98edf25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694057820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3694057820
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2651280346
Short name T1045
Test name
Test status
Simulation time 20560705159 ps
CPU time 31.03 seconds
Started Mar 31 03:17:05 PM PDT 24
Finished Mar 31 03:17:36 PM PDT 24
Peak memory 200452 kb
Host smart-8d6c7b02-ce0a-4701-affc-859aba270330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651280346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2651280346
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.922177650
Short name T1068
Test name
Test status
Simulation time 39142919101 ps
CPU time 22.21 seconds
Started Mar 31 03:17:04 PM PDT 24
Finished Mar 31 03:17:26 PM PDT 24
Peak memory 200496 kb
Host smart-96aa33fb-1513-4ad1-8bb9-35736c7a9738
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922177650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.922177650
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4082330765
Short name T974
Test name
Test status
Simulation time 80871178604 ps
CPU time 655.63 seconds
Started Mar 31 03:17:10 PM PDT 24
Finished Mar 31 03:28:06 PM PDT 24
Peak memory 200500 kb
Host smart-a2b9b3fe-4b48-4222-9ddf-a1abf8e1cbf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082330765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4082330765
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.514431406
Short name T419
Test name
Test status
Simulation time 3382650597 ps
CPU time 4.08 seconds
Started Mar 31 03:17:09 PM PDT 24
Finished Mar 31 03:17:14 PM PDT 24
Peak memory 199612 kb
Host smart-7fedb2e2-2169-4bc3-9418-9aea44cb2b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514431406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.514431406
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3475855967
Short name T290
Test name
Test status
Simulation time 13656002328 ps
CPU time 22.12 seconds
Started Mar 31 03:17:06 PM PDT 24
Finished Mar 31 03:17:28 PM PDT 24
Peak memory 200780 kb
Host smart-2d665257-227c-4db3-a171-288d9a0eb390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475855967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3475855967
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1761404636
Short name T326
Test name
Test status
Simulation time 7842136195 ps
CPU time 96.01 seconds
Started Mar 31 03:17:10 PM PDT 24
Finished Mar 31 03:18:46 PM PDT 24
Peak memory 200496 kb
Host smart-4c37770d-575e-4db7-910f-a42cc1a14350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761404636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1761404636
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2678424081
Short name T80
Test name
Test status
Simulation time 2760292739 ps
CPU time 16.79 seconds
Started Mar 31 03:17:03 PM PDT 24
Finished Mar 31 03:17:20 PM PDT 24
Peak memory 198608 kb
Host smart-aa7996f0-1c1c-41be-8566-0983c754cbd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678424081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2678424081
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.197966977
Short name T1163
Test name
Test status
Simulation time 89873461710 ps
CPU time 76.84 seconds
Started Mar 31 03:17:05 PM PDT 24
Finished Mar 31 03:18:22 PM PDT 24
Peak memory 200456 kb
Host smart-86d8f242-64b9-4895-a8c2-0a679651437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197966977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.197966977
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3265319267
Short name T499
Test name
Test status
Simulation time 4236301718 ps
CPU time 2.44 seconds
Started Mar 31 03:17:05 PM PDT 24
Finished Mar 31 03:17:07 PM PDT 24
Peak memory 196508 kb
Host smart-c70b04fe-ef54-4e7c-95be-726fa28d8609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265319267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3265319267
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1771853990
Short name T652
Test name
Test status
Simulation time 483892005 ps
CPU time 1.64 seconds
Started Mar 31 03:16:59 PM PDT 24
Finished Mar 31 03:17:01 PM PDT 24
Peak memory 199316 kb
Host smart-849917f1-042b-47ba-9a7f-6d276e559f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771853990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1771853990
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.625683113
Short name T637
Test name
Test status
Simulation time 255679860638 ps
CPU time 305.11 seconds
Started Mar 31 03:17:10 PM PDT 24
Finished Mar 31 03:22:16 PM PDT 24
Peak memory 200416 kb
Host smart-77dce23d-fa1c-4d98-aefd-ad6ce2b6f2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625683113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.625683113
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2021941943
Short name T432
Test name
Test status
Simulation time 40453324283 ps
CPU time 247.17 seconds
Started Mar 31 03:17:10 PM PDT 24
Finished Mar 31 03:21:18 PM PDT 24
Peak memory 216960 kb
Host smart-4dea1b84-694a-4cd7-a9ad-92d8ae540dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021941943 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2021941943
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2287865341
Short name T672
Test name
Test status
Simulation time 7650327637 ps
CPU time 11.37 seconds
Started Mar 31 03:17:05 PM PDT 24
Finished Mar 31 03:17:17 PM PDT 24
Peak memory 200492 kb
Host smart-1a455fd8-ea5d-4052-b307-f7c87ee5582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287865341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2287865341
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3257550194
Short name T260
Test name
Test status
Simulation time 66444828668 ps
CPU time 42.18 seconds
Started Mar 31 03:16:57 PM PDT 24
Finished Mar 31 03:17:40 PM PDT 24
Peak memory 200472 kb
Host smart-ddc22866-809b-4d24-a3d8-9fca6ac8adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257550194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3257550194
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.865571851
Short name T125
Test name
Test status
Simulation time 103348556517 ps
CPU time 131.05 seconds
Started Mar 31 03:25:28 PM PDT 24
Finished Mar 31 03:27:39 PM PDT 24
Peak memory 200472 kb
Host smart-212875b0-b1b9-4ce7-a046-101d62d8506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865571851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.865571851
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1082122127
Short name T768
Test name
Test status
Simulation time 223915673130 ps
CPU time 407.62 seconds
Started Mar 31 03:25:27 PM PDT 24
Finished Mar 31 03:32:15 PM PDT 24
Peak memory 211392 kb
Host smart-93c16f4b-9054-431f-acf6-063907a121d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082122127 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1082122127
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.983855396
Short name T133
Test name
Test status
Simulation time 57348465100 ps
CPU time 18.76 seconds
Started Mar 31 03:25:27 PM PDT 24
Finished Mar 31 03:25:46 PM PDT 24
Peak memory 200492 kb
Host smart-a455f8bf-ab6e-4ae0-9d88-a756b3b33b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983855396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.983855396
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.379012914
Short name T813
Test name
Test status
Simulation time 16128475811 ps
CPU time 164.39 seconds
Started Mar 31 03:25:28 PM PDT 24
Finished Mar 31 03:28:13 PM PDT 24
Peak memory 216968 kb
Host smart-a9b02d87-af36-44df-b82c-732b7f6a1565
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379012914 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.379012914
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.717974181
Short name T190
Test name
Test status
Simulation time 29857583585 ps
CPU time 23.12 seconds
Started Mar 31 03:25:34 PM PDT 24
Finished Mar 31 03:25:57 PM PDT 24
Peak memory 200524 kb
Host smart-7692b909-505c-4e16-a819-2727b48c4af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717974181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.717974181
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2348718377
Short name T317
Test name
Test status
Simulation time 169541595993 ps
CPU time 1223.25 seconds
Started Mar 31 03:25:35 PM PDT 24
Finished Mar 31 03:45:59 PM PDT 24
Peak memory 225164 kb
Host smart-1c20ce53-9768-4c8a-95a2-df79a41aea95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348718377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2348718377
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1785921620
Short name T755
Test name
Test status
Simulation time 19535707052 ps
CPU time 15.32 seconds
Started Mar 31 03:25:35 PM PDT 24
Finished Mar 31 03:25:51 PM PDT 24
Peak memory 200272 kb
Host smart-1b344b53-b078-4a73-bc75-3b27387d48ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785921620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1785921620
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.880392114
Short name T1052
Test name
Test status
Simulation time 83282464998 ps
CPU time 1256.35 seconds
Started Mar 31 03:25:33 PM PDT 24
Finished Mar 31 03:46:29 PM PDT 24
Peak memory 225416 kb
Host smart-c40bbfd2-23bd-45ab-b383-0849741e3bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880392114 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.880392114
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.101046356
Short name T605
Test name
Test status
Simulation time 146060074384 ps
CPU time 26.35 seconds
Started Mar 31 03:25:34 PM PDT 24
Finished Mar 31 03:26:00 PM PDT 24
Peak memory 200500 kb
Host smart-0f50cc0e-97b6-45f9-bcfb-f5aa395bb072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101046356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.101046356
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1770785157
Short name T422
Test name
Test status
Simulation time 4658995983 ps
CPU time 50.51 seconds
Started Mar 31 03:25:34 PM PDT 24
Finished Mar 31 03:26:24 PM PDT 24
Peak memory 208772 kb
Host smart-fc0acd22-a5ec-4b54-8a81-cb898403e9f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770785157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1770785157
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1661921386
Short name T984
Test name
Test status
Simulation time 88888266314 ps
CPU time 503.09 seconds
Started Mar 31 03:25:39 PM PDT 24
Finished Mar 31 03:34:02 PM PDT 24
Peak memory 200508 kb
Host smart-f797f17e-21d6-4019-9355-d72747d61298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661921386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1661921386
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3394820085
Short name T885
Test name
Test status
Simulation time 54355049928 ps
CPU time 353.13 seconds
Started Mar 31 03:25:39 PM PDT 24
Finished Mar 31 03:31:32 PM PDT 24
Peak memory 210004 kb
Host smart-3139b6a9-d641-4b92-bdc6-c440ed57dbac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394820085 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3394820085
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3081761087
Short name T1069
Test name
Test status
Simulation time 96931879952 ps
CPU time 74.7 seconds
Started Mar 31 03:25:40 PM PDT 24
Finished Mar 31 03:26:55 PM PDT 24
Peak memory 200496 kb
Host smart-fe7ec403-bb24-4e84-9827-19212cbe4ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081761087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3081761087
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3975428550
Short name T989
Test name
Test status
Simulation time 23347364125 ps
CPU time 136.5 seconds
Started Mar 31 03:25:40 PM PDT 24
Finished Mar 31 03:27:56 PM PDT 24
Peak memory 208748 kb
Host smart-014b612b-4d18-4625-a5d2-a108ac3411df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975428550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3975428550
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.114553035
Short name T871
Test name
Test status
Simulation time 142977750575 ps
CPU time 269.69 seconds
Started Mar 31 03:25:46 PM PDT 24
Finished Mar 31 03:30:16 PM PDT 24
Peak memory 200488 kb
Host smart-57c0fc22-7e0d-4e33-9035-9436bf29256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114553035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.114553035
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3274570577
Short name T784
Test name
Test status
Simulation time 349054001028 ps
CPU time 753.03 seconds
Started Mar 31 03:25:47 PM PDT 24
Finished Mar 31 03:38:20 PM PDT 24
Peak memory 217240 kb
Host smart-db80d001-a678-4501-af08-4612327db0a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274570577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3274570577
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3198574106
Short name T268
Test name
Test status
Simulation time 96174923279 ps
CPU time 70.96 seconds
Started Mar 31 03:25:47 PM PDT 24
Finished Mar 31 03:26:58 PM PDT 24
Peak memory 200524 kb
Host smart-d43f4fc0-5c06-4cb6-8879-f0344d629b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198574106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3198574106
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1824720621
Short name T1104
Test name
Test status
Simulation time 69876429681 ps
CPU time 357.97 seconds
Started Mar 31 03:25:48 PM PDT 24
Finished Mar 31 03:31:46 PM PDT 24
Peak memory 217280 kb
Host smart-a4aab9b4-d76b-4dd6-8b2b-468ae70c6669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824720621 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1824720621
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1706434954
Short name T124
Test name
Test status
Simulation time 88427439350 ps
CPU time 137.25 seconds
Started Mar 31 03:25:45 PM PDT 24
Finished Mar 31 03:28:03 PM PDT 24
Peak memory 200412 kb
Host smart-8f20f892-dbfe-4fba-8dde-8451eca9b33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706434954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1706434954
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1721671411
Short name T462
Test name
Test status
Simulation time 266037226368 ps
CPU time 296.21 seconds
Started Mar 31 03:25:46 PM PDT 24
Finished Mar 31 03:30:42 PM PDT 24
Peak memory 216892 kb
Host smart-3dfdd5a4-2be8-4ae5-8e9e-3035467f7ec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721671411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1721671411
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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