Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71390352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27772391

1

T1

53

T2

144

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89512086	1			T1	5760		T2	352		T3	1
values[0x0]	4557742	1			T1	26		T2	69		T3	2
values[0x1]	5092915	1			T1	36		T2	72		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49493346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49669397

1

T1

1936

T2

219

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	370494	1			T1	27		T4	85		T5	137
valid_sources[0x01]	391526	1			T1	21		T2	4		T4	90
valid_sources[0x02]	374732	1			T1	28		T2	1		T4	90
valid_sources[0x03]	384771	1			T1	21		T2	2		T4	97
valid_sources[0x04]	360844	1			T1	28		T2	1		T4	71
valid_sources[0x05]	406188	1			T1	31		T4	96		T5	131
valid_sources[0x06]	375289	1			T1	29		T2	2		T4	92
valid_sources[0x07]	371584	1			T1	18		T2	2		T4	105
valid_sources[0x08]	390348	1			T1	20		T4	92		T5	157
valid_sources[0x09]	376863	1			T1	13		T2	1		T4	85
valid_sources[0x0a]	370093	1			T1	11		T4	99		T5	112
valid_sources[0x0b]	379646	1			T1	14		T2	2		T4	89
valid_sources[0x0c]	373473	1			T1	23		T2	1		T4	102
valid_sources[0x0d]	377505	1			T1	12		T2	3		T4	93
valid_sources[0x0e]	362719	1			T1	25		T2	2		T4	88
valid_sources[0x0f]	514671	1			T1	11		T2	1		T4	65
valid_sources[0x10]	369103	1			T1	8		T2	3		T4	95
valid_sources[0x11]	384380	1			T1	37		T2	1		T4	68
valid_sources[0x12]	371257	1			T1	11		T2	5		T4	76
valid_sources[0x13]	384792	1			T1	17		T4	100		T5	126
valid_sources[0x14]	407433	1			T1	10		T2	3		T4	106
valid_sources[0x15]	397236	1			T1	30		T2	3		T4	89
valid_sources[0x16]	411858	1			T1	29		T2	2		T4	97
valid_sources[0x17]	371230	1			T1	22		T2	1		T4	92
valid_sources[0x18]	379329	1			T1	34		T4	96		T5	118
valid_sources[0x19]	364336	1			T1	3		T2	4		T4	94
valid_sources[0x1a]	377572	1			T1	26		T2	1		T4	74
valid_sources[0x1b]	379747	1			T1	45		T2	3		T4	101
valid_sources[0x1c]	386573	1			T1	9		T4	85		T5	129
valid_sources[0x1d]	384255	1			T1	22		T2	1		T4	89
valid_sources[0x1e]	372696	1			T1	35		T2	1		T4	84
valid_sources[0x1f]	378211	1			T1	22		T2	5		T4	97
valid_sources[0x20]	390328	1			T1	15		T2	2		T4	84
valid_sources[0x21]	409826	1			T1	11		T2	3		T4	89
valid_sources[0x22]	471795	1			T1	24		T2	3		T4	90
valid_sources[0x23]	377396	1			T1	9		T2	1		T4	86
valid_sources[0x24]	379442	1			T1	19		T2	1		T4	87
valid_sources[0x25]	379168	1			T1	16		T2	2		T4	112
valid_sources[0x26]	375899	1			T1	47		T4	89		T5	118
valid_sources[0x27]	373267	1			T1	9		T2	4		T4	78
valid_sources[0x28]	387105	1			T1	15		T2	5		T4	105
valid_sources[0x29]	364555	1			T1	26		T2	2		T4	100
valid_sources[0x2a]	365135	1			T1	35		T2	1		T4	89
valid_sources[0x2b]	386492	1			T1	17		T2	1		T4	88
valid_sources[0x2c]	602540	1			T1	31		T2	3		T4	87
valid_sources[0x2d]	390009	1			T1	9		T2	1		T4	95
valid_sources[0x2e]	394690	1			T1	22		T2	1		T4	84
valid_sources[0x2f]	370790	1			T1	26		T2	2		T4	93
valid_sources[0x30]	404353	1			T1	15		T2	1		T4	85
valid_sources[0x31]	372949	1			T1	34		T2	1		T4	89
valid_sources[0x32]	377761	1			T1	13		T4	68		T5	132
valid_sources[0x33]	348734	1			T1	13		T4	95		T5	139
valid_sources[0x34]	390570	1			T1	42		T3	3		T4	78
valid_sources[0x35]	474001	1			T1	11		T2	1		T4	89
valid_sources[0x36]	383651	1			T1	37		T2	2		T4	101
valid_sources[0x37]	384922	1			T1	40		T2	5		T4	82
valid_sources[0x38]	368988	1			T1	35		T4	119		T5	152
valid_sources[0x39]	387175	1			T1	22		T2	3		T4	89
valid_sources[0x3a]	376746	1			T1	40		T2	1		T4	105
valid_sources[0x3b]	377521	1			T1	26		T2	1		T4	102
valid_sources[0x3c]	381539	1			T1	46		T2	2		T4	94
valid_sources[0x3d]	351825	1			T1	32		T2	2		T4	81
valid_sources[0x3e]	382823	1			T1	36		T2	5		T4	99
valid_sources[0x3f]	379685	1			T1	22		T2	2		T4	74
valid_sources[0x40]	371484	1			T1	5		T2	4		T4	90
valid_sources[0x41]	370630	1			T1	12		T2	2		T4	112
valid_sources[0x42]	383076	1			T1	13		T2	3		T4	88
valid_sources[0x43]	401205	1			T1	19		T2	2		T4	102
valid_sources[0x44]	389382	1			T1	11		T2	1		T4	82
valid_sources[0x45]	360923	1			T1	30		T2	2		T4	92
valid_sources[0x46]	420957	1			T1	24		T2	2		T4	92
valid_sources[0x47]	382367	1			T1	35		T2	4		T4	88
valid_sources[0x48]	365609	1			T1	21		T2	2		T4	97
valid_sources[0x49]	370735	1			T1	31		T2	1		T4	100
valid_sources[0x4a]	474804	1			T1	26		T2	2		T4	92
valid_sources[0x4b]	629347	1			T1	21		T2	2		T4	83
valid_sources[0x4c]	382307	1			T1	14		T2	1		T4	104
valid_sources[0x4d]	380404	1			T1	24		T2	2		T4	88
valid_sources[0x4e]	354311	1			T1	20		T2	3		T4	107
valid_sources[0x4f]	382076	1			T1	47		T2	2		T4	86
valid_sources[0x50]	418021	1			T1	3		T2	2		T4	87
valid_sources[0x51]	355723	1			T1	6		T2	3		T4	90
valid_sources[0x52]	378336	1			T1	25		T2	2		T4	94
valid_sources[0x53]	381247	1			T1	38		T2	2		T4	119
valid_sources[0x54]	370236	1			T1	44		T2	2		T4	66
valid_sources[0x55]	380548	1			T1	27		T4	76		T5	138
valid_sources[0x56]	380880	1			T1	18		T2	2		T4	82
valid_sources[0x57]	431933	1			T1	21		T2	2		T4	89
valid_sources[0x58]	369323	1			T1	23		T2	2		T4	86
valid_sources[0x59]	422756	1			T1	21		T4	86		T5	129
valid_sources[0x5a]	358755	1			T1	30		T2	4		T4	91
valid_sources[0x5b]	397208	1			T1	22		T2	3		T4	105
valid_sources[0x5c]	434500	1			T1	14		T2	2		T4	91
valid_sources[0x5d]	378937	1			T1	19		T2	3		T4	108
valid_sources[0x5e]	369180	1			T1	34		T2	2		T4	75
valid_sources[0x5f]	382416	1			T1	54		T2	1		T4	103
valid_sources[0x60]	369640	1			T1	9		T2	3		T4	88
valid_sources[0x61]	380138	1			T1	5		T2	2		T4	81
valid_sources[0x62]	370457	1			T1	21		T2	1		T4	85
valid_sources[0x63]	369500	1			T1	29		T2	4		T4	90
valid_sources[0x64]	359443	1			T1	46		T2	2		T4	78
valid_sources[0x65]	374272	1			T1	13		T2	3		T4	84
valid_sources[0x66]	371983	1			T1	18		T2	2		T4	87
valid_sources[0x67]	399309	1			T1	15		T2	3		T4	89
valid_sources[0x68]	361416	1			T1	15		T2	3		T4	80
valid_sources[0x69]	374447	1			T1	37		T2	2		T4	88
valid_sources[0x6a]	370254	1			T1	17		T4	92		T5	127
valid_sources[0x6b]	387782	1			T1	17		T2	5		T4	95
valid_sources[0x6c]	381385	1			T1	21		T2	5		T4	75
valid_sources[0x6d]	373978	1			T1	27		T2	1		T4	106
valid_sources[0x6e]	408063	1			T1	21		T2	2		T4	89
valid_sources[0x6f]	360978	1			T1	21		T2	1		T3	5
valid_sources[0x70]	452266	1			T1	31		T2	2		T4	102
valid_sources[0x71]	386997	1			T1	27		T2	3		T4	106
valid_sources[0x72]	364876	1			T1	43		T2	2		T4	78
valid_sources[0x73]	365519	1			T1	8		T2	4		T4	87
valid_sources[0x74]	369250	1			T1	21		T4	111		T5	123
valid_sources[0x75]	366748	1			T1	21		T2	1		T4	88
valid_sources[0x76]	390515	1			T1	33		T2	5		T4	90
valid_sources[0x77]	364107	1			T1	16		T2	1		T4	95
valid_sources[0x78]	387446	1			T1	11		T2	5		T4	90
valid_sources[0x79]	365249	1			T1	20		T2	4		T4	108
valid_sources[0x7a]	376888	1			T1	33		T2	1		T4	94
valid_sources[0x7b]	382457	1			T1	37		T2	1		T4	95
valid_sources[0x7c]	403363	1			T1	22		T2	1		T4	79
valid_sources[0x7d]	379758	1			T1	23		T2	3		T4	63
valid_sources[0x7e]	394862	1			T1	3		T4	88		T5	131
valid_sources[0x7f]	389297	1			T1	19		T2	2		T4	87
valid_sources[0x80]	362761	1			T1	40		T2	1		T4	104

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19240355

1

T1

8

T2

102

T5

108

values[0x0]

all_enables

biggest_size

4293934

1

T1

18

T2

24

T3

1

values[0x1]

all_enables

biggest_size

4238102

1

T1

27

T2

18

T3

3