Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14261758	0	0
ctrl_rd_A	2147483647	183051	0	0
intr_enable_rd_A	2147483647	162233	0	0
ovrd_rd_A	2147483647	180480	0	0
timeout_ctrl_rd_A	2147483647	178964	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14261758	0	0
T16	0	60365	0	0
T17	188501	42793	0	0
T18	729262	0	0	0
T19	972679	384957	0	0
T21	0	33229	0	0
T24	0	58244	0	0
T30	0	137504	0	0
T31	0	12552	0	0
T32	0	129509	0	0
T33	0	139758	0	0
T34	0	103943	0	0
T35	420134	0	0	0
T36	942507	0	0	0
T37	726857	0	0	0
T38	138521	0	0	0
T39	324296	0	0	0
T40	320065	0	0	0
T41	108002	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	183051	0	0
T16	0	2759	0	0
T17	188501	4671	0	0
T18	729262	0	0	0
T19	972679	0	0	0
T35	420134	0	0	0
T36	942507	0	0	0
T37	726857	0	0	0
T38	138521	0	0	0
T39	324296	0	0	0
T40	320065	0	0	0
T41	108002	0	0	0
T57	0	12591	0	0
T58	0	2431	0	0
T113	0	3647	0	0
T114	0	5657	0	0
T115	0	8714	0	0
T116	0	3028	0	0
T117	0	10555	0	0
T118	0	2551	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	162233	0	0
T16	0	2399	0	0
T17	188501	4270	0	0
T18	729262	0	0	0
T19	972679	0	0	0
T35	420134	0	0	0
T36	942507	0	0	0
T37	726857	0	0	0
T38	138521	0	0	0
T39	324296	0	0	0
T40	320065	0	0	0
T41	108002	0	0	0
T57	0	11265	0	0
T58	0	2324	0	0
T113	0	3365	0	0
T114	0	4820	0	0
T115	0	7558	0	0
T116	0	2585	0	0
T117	0	9163	0	0
T119	0	23	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	180480	0	0
T16	0	2758	0	0
T17	188501	4642	0	0
T18	729262	0	0	0
T19	972679	0	0	0
T35	420134	0	0	0
T36	942507	0	0	0
T37	726857	0	0	0
T38	138521	0	0	0
T39	324296	0	0	0
T40	320065	0	0	0
T41	108002	0	0	0
T57	0	12504	0	0
T58	0	2778	0	0
T113	0	3690	0	0
T114	0	5502	0	0
T115	0	8737	0	0
T116	0	2900	0	0
T117	0	10398	0	0
T118	0	2506	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	178964	0	0
T16	0	2562	0	0
T17	188501	4685	0	0
T18	729262	0	0	0
T19	972679	0	0	0
T35	420134	0	0	0
T36	942507	0	0	0
T37	726857	0	0	0
T38	138521	0	0	0
T39	324296	0	0	0
T40	320065	0	0	0
T41	108002	0	0	0
T57	0	12323	0	0
T58	0	2384	0	0
T113	0	3753	0	0
T114	0	5499	0	0
T115	0	8859	0	0
T116	0	3038	0	0
T117	0	10941	0	0
T118	0	2446	0	0