Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	80165992	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29751808

1

T1

134

T2

209

T3

77982

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	99474393	1			T1	1903		T2	7414		T3	82326
values[0x0]	4931460	1			T1	43		T2	96		T3	22731
values[0x1]	5511947	1			T1	33		T2	106		T3	25662

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55409264	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

54508536

1

T1

735

T2

2607

T3

94159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	434996	1			T1	6		T2	16		T3	305
valid_sources[0x01]	397206	1			T1	25		T2	43		T3	151
valid_sources[0x02]	489442	1			T1	10		T2	38		T3	326
valid_sources[0x03]	496960	1			T1	3		T2	32		T3	291
valid_sources[0x04]	581527	1			T1	9		T2	28		T3	141
valid_sources[0x05]	415474	1			T1	2		T2	24		T3	152
valid_sources[0x06]	538930	1			T1	2		T2	22		T3	392
valid_sources[0x07]	403590	1			T1	16		T2	26		T3	546
valid_sources[0x08]	484904	1			T1	1		T2	22		T3	176
valid_sources[0x09]	448203	1			T2	27		T3	602		T4	17
valid_sources[0x0a]	418345	1			T1	31		T2	27		T3	103
valid_sources[0x0b]	428426	1			T1	6		T2	20		T3	424
valid_sources[0x0c]	488281	1			T1	10		T2	34		T3	589
valid_sources[0x0d]	411458	1			T1	13		T2	20		T3	160
valid_sources[0x0e]	404674	1			T1	3		T2	23		T3	259
valid_sources[0x0f]	420657	1			T1	7		T2	28		T3	77
valid_sources[0x10]	422907	1			T1	3		T2	47		T3	349
valid_sources[0x11]	420477	1			T1	15		T2	24		T3	3507
valid_sources[0x12]	472408	1			T1	13		T2	26		T3	199
valid_sources[0x13]	420573	1			T1	3		T2	23		T3	668
valid_sources[0x14]	401178	1			T1	4		T2	32		T3	489
valid_sources[0x15]	409329	1			T1	9		T2	17		T3	212
valid_sources[0x16]	404665	1			T1	4		T2	25		T3	417
valid_sources[0x17]	430126	1			T1	6		T2	29		T3	31
valid_sources[0x18]	428984	1			T1	4		T2	12		T3	274
valid_sources[0x19]	468481	1			T1	10		T2	22		T3	273
valid_sources[0x1a]	405672	1			T1	6		T2	27		T3	153
valid_sources[0x1b]	411699	1			T1	13		T2	43		T3	269
valid_sources[0x1c]	430514	1			T1	2		T2	20		T3	99
valid_sources[0x1d]	409607	1			T1	5		T2	23		T3	435
valid_sources[0x1e]	413637	1			T2	24		T3	169		T4	31
valid_sources[0x1f]	420496	1			T1	16		T2	20		T3	537
valid_sources[0x20]	392610	1			T1	6		T2	29		T3	149
valid_sources[0x21]	400723	1			T2	27		T3	482		T4	23
valid_sources[0x22]	420043	1			T1	1		T2	29		T3	920
valid_sources[0x23]	433636	1			T1	5		T2	25		T3	324
valid_sources[0x24]	439783	1			T1	1		T2	25		T3	3228
valid_sources[0x25]	393634	1			T1	5		T2	42		T3	179
valid_sources[0x26]	428849	1			T1	6		T2	28		T3	2570
valid_sources[0x27]	408302	1			T1	17		T2	30		T3	268
valid_sources[0x28]	393463	1			T1	7		T2	37		T3	197
valid_sources[0x29]	402594	1			T2	29		T3	387		T4	15
valid_sources[0x2a]	427044	1			T1	10		T2	22		T3	695
valid_sources[0x2b]	410481	1			T1	2		T2	22		T3	1226
valid_sources[0x2c]	408798	1			T1	29		T2	25		T3	159
valid_sources[0x2d]	429043	1			T2	28		T3	215		T4	28
valid_sources[0x2e]	410062	1			T1	5		T2	34		T3	293
valid_sources[0x2f]	402905	1			T1	11		T2	20		T3	218
valid_sources[0x30]	1235628	1			T2	24		T3	226		T4	29
valid_sources[0x31]	421741	1			T1	8		T2	16		T3	523
valid_sources[0x32]	406501	1			T1	2		T2	35		T3	230
valid_sources[0x33]	421793	1			T1	2		T2	28		T3	613
valid_sources[0x34]	407726	1			T1	6		T2	24		T3	556
valid_sources[0x35]	412897	1			T1	4		T2	29		T3	108
valid_sources[0x36]	475739	1			T1	26		T2	26		T3	772
valid_sources[0x37]	428112	1			T1	13		T2	19		T3	225
valid_sources[0x38]	415661	1			T1	6		T2	35		T3	243
valid_sources[0x39]	418849	1			T2	33		T3	223		T4	13
valid_sources[0x3a]	500532	1			T1	2		T2	35		T3	131
valid_sources[0x3b]	455274	1			T1	5		T2	31		T3	432
valid_sources[0x3c]	403964	1			T1	10		T2	30		T3	498
valid_sources[0x3d]	397793	1			T1	12		T2	22		T3	148
valid_sources[0x3e]	467675	1			T1	5		T2	54		T3	372
valid_sources[0x3f]	404629	1			T1	14		T2	44		T3	293
valid_sources[0x40]	503478	1			T1	15		T2	24		T3	327
valid_sources[0x41]	416501	1			T2	27		T3	347		T4	20
valid_sources[0x42]	409565	1			T1	5		T2	22		T3	723
valid_sources[0x43]	467159	1			T1	12		T2	26		T3	221
valid_sources[0x44]	438568	1			T1	8		T2	41		T3	40
valid_sources[0x45]	431782	1			T1	3		T2	24		T3	5076
valid_sources[0x46]	445120	1			T1	9		T2	26		T3	323
valid_sources[0x47]	412276	1			T1	7		T2	28		T3	176
valid_sources[0x48]	430576	1			T2	36		T3	278		T4	19
valid_sources[0x49]	392527	1			T1	11		T2	34		T3	91
valid_sources[0x4a]	465979	1			T1	9		T2	22		T3	256
valid_sources[0x4b]	407539	1			T1	8		T2	41		T3	118
valid_sources[0x4c]	416187	1			T1	7		T2	34		T3	1676
valid_sources[0x4d]	403982	1			T1	6		T2	29		T3	103
valid_sources[0x4e]	410107	1			T1	2		T2	28		T3	252
valid_sources[0x4f]	403259	1			T1	6		T2	25		T3	1016
valid_sources[0x50]	413580	1			T1	2		T2	29		T3	414
valid_sources[0x51]	402860	1			T1	1		T2	30		T3	339
valid_sources[0x52]	422060	1			T1	10		T2	26		T3	109
valid_sources[0x53]	392866	1			T1	8		T2	37		T3	70
valid_sources[0x54]	443998	1			T1	8		T2	26		T3	363
valid_sources[0x55]	388825	1			T1	14		T2	21		T3	641
valid_sources[0x56]	411415	1			T1	8		T2	36		T3	539
valid_sources[0x57]	410947	1			T1	20		T2	32		T3	3200
valid_sources[0x58]	472141	1			T1	6		T2	40		T3	378
valid_sources[0x59]	405900	1			T1	6		T2	34		T3	301
valid_sources[0x5a]	410489	1			T1	4		T2	54		T3	34
valid_sources[0x5b]	414564	1			T1	3		T2	37		T3	439
valid_sources[0x5c]	408703	1			T1	1		T2	32		T3	120
valid_sources[0x5d]	417112	1			T1	14		T2	30		T3	53
valid_sources[0x5e]	410471	1			T1	12		T2	24		T3	595
valid_sources[0x5f]	415430	1			T1	8		T2	23		T3	396
valid_sources[0x60]	433445	1			T1	3		T2	32		T3	3503
valid_sources[0x61]	444238	1			T1	4		T2	24		T3	1010
valid_sources[0x62]	392729	1			T1	14		T2	20		T3	23
valid_sources[0x63]	413896	1			T1	14		T2	26		T3	760
valid_sources[0x64]	395117	1			T2	50		T3	265		T4	24
valid_sources[0x65]	408605	1			T1	10		T2	39		T3	340
valid_sources[0x66]	413028	1			T1	10		T2	50		T3	204
valid_sources[0x67]	407127	1			T1	14		T2	37		T3	1250
valid_sources[0x68]	525433	1			T1	2		T2	42		T3	1394
valid_sources[0x69]	444851	1			T1	6		T2	35		T3	50
valid_sources[0x6a]	418498	1			T1	10		T2	25		T3	179
valid_sources[0x6b]	514937	1			T1	6		T2	31		T3	238
valid_sources[0x6c]	422274	1			T1	6		T2	37		T3	490
valid_sources[0x6d]	440158	1			T1	19		T2	33		T3	222
valid_sources[0x6e]	435628	1			T1	9		T2	25		T3	660
valid_sources[0x6f]	480663	1			T1	7		T2	41		T3	1164
valid_sources[0x70]	436686	1			T1	8		T2	26		T3	766
valid_sources[0x71]	415210	1			T1	10		T2	25		T3	259
valid_sources[0x72]	400524	1			T1	4		T2	17		T3	1254
valid_sources[0x73]	406547	1			T1	10		T2	40		T3	680
valid_sources[0x74]	416900	1			T1	18		T2	32		T3	12
valid_sources[0x75]	426231	1			T1	20		T2	27		T3	25
valid_sources[0x76]	432207	1			T1	4		T2	25		T3	493
valid_sources[0x77]	395969	1			T1	5		T2	33		T3	935
valid_sources[0x78]	457337	1			T1	10		T2	26		T3	651
valid_sources[0x79]	427697	1			T1	11		T2	25		T3	961
valid_sources[0x7a]	431063	1			T1	4		T2	27		T3	399
valid_sources[0x7b]	412728	1			T1	3		T2	21		T3	75
valid_sources[0x7c]	421411	1			T1	13		T2	28		T3	250
valid_sources[0x7d]	422485	1			T1	8		T2	39		T3	309
valid_sources[0x7e]	426612	1			T1	12		T2	32		T3	393
valid_sources[0x7f]	428594	1			T1	11		T2	52		T3	46
valid_sources[0x80]	422042	1			T1	6		T2	35		T3	285

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20483700

1

T1

102

T2

126

T3

33088

values[0x0]

all_enables

biggest_size

4663610

1

T1

21

T2

47

T3

22440

values[0x1]

all_enables

biggest_size

4604498

1

T1

11

T2

36

T3

22454