Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15522125	0	0
ctrl_rd_A	2147483647	172061	0	0
intr_enable_rd_A	2147483647	151892	0	0
ovrd_rd_A	2147483647	169217	0	0
timeout_ctrl_rd_A	2147483647	171667	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15522125	0	0
T3	189223	77527	0	0
T4	257456	0	0	0
T5	137688	0	0	0
T6	54863	0	0	0
T7	101075	0	0	0
T8	160433	0	0	0
T9	100287	0	0	0
T10	636136	0	0	0
T11	56380	0	0	0
T12	296892	0	0	0
T16	0	114927	0	0
T19	0	140446	0	0
T25	0	6195	0	0
T32	0	454627	0	0
T33	0	212106	0	0
T34	0	378591	0	0
T35	0	168623	0	0
T36	0	112313	0	0
T37	0	256561	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	172061	0	0
T16	504511	12355	0	0
T19	366747	0	0	0
T24	186697	0	0	0
T25	463420	633	0	0
T26	853	0	0	0
T40	203596	0	0	0
T41	568298	0	0	0
T51	0	6086	0	0
T92	0	4088	0	0
T93	0	7241	0	0
T94	0	13870	0	0
T95	0	7341	0	0
T96	0	13334	0	0
T97	0	9887	0	0
T98	0	21636	0	0
T99	933934	0	0	0
T100	112222	0	0	0
T101	407783	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	151892	0	0
T16	504511	10850	0	0
T19	366747	0	0	0
T24	186697	0	0	0
T25	463420	593	0	0
T26	853	0	0	0
T40	203596	0	0	0
T41	568298	0	0	0
T92	0	3682	0	0
T93	0	6645	0	0
T94	0	12015	0	0
T95	0	7050	0	0
T96	0	12267	0	0
T97	0	8753	0	0
T98	0	19091	0	0
T99	933934	0	0	0
T100	112222	0	0	0
T101	407783	0	0	0
T102	0	3	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	169217	0	0
T16	504511	12841	0	0
T19	366747	0	0	0
T24	186697	0	0	0
T25	463420	680	0	0
T26	853	0	0	0
T40	203596	0	0	0
T41	568298	0	0	0
T51	0	5766	0	0
T92	0	4183	0	0
T93	0	7392	0	0
T94	0	13614	0	0
T95	0	7286	0	0
T96	0	13859	0	0
T97	0	9539	0	0
T98	0	21437	0	0
T99	933934	0	0	0
T100	112222	0	0	0
T101	407783	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	171667	0	0
T16	504511	12306	0	0
T19	366747	0	0	0
T24	186697	0	0	0
T25	463420	831	0	0
T26	853	0	0	0
T40	203596	0	0	0
T41	568298	0	0	0
T51	0	6036	0	0
T92	0	4108	0	0
T93	0	7316	0	0
T94	0	14116	0	0
T95	0	7802	0	0
T96	0	14068	0	0
T97	0	9804	0	0
T98	0	21988	0	0
T99	933934	0	0	0
T100	112222	0	0	0
T101	407783	0	0	0