Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14167645	0	0
ctrl_rd_A	2147483647	248432	0	0
intr_enable_rd_A	2147483647	219618	0	0
ovrd_rd_A	2147483647	246232	0	0
timeout_ctrl_rd_A	2147483647	247468	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14167645	0	0
T14	0	222334	0	0
T17	667956	0	0	0
T18	88913	0	0	0
T19	0	318671	0	0
T20	532727	104125	0	0
T21	201907	0	0	0
T22	164122	0	0	0
T24	0	170858	0	0
T33	938431	0	0	0
T34	0	99275	0	0
T35	0	131705	0	0
T36	0	27106	0	0
T37	0	236515	0	0
T38	0	72015	0	0
T39	0	39454	0	0
T40	23237	0	0	0
T41	161620	0	0	0
T42	374639	0	0	0
T43	178791	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	248432	0	0
T14	922291	10803	0	0
T15	922719	0	0	0
T19	117288	0	0	0
T29	1450	0	0	0
T35	0	14860	0	0
T36	0	1217	0	0
T39	0	4488	0	0
T44	305889	0	0	0
T107	0	3721	0	0
T108	0	2108	0	0
T109	0	7299	0	0
T110	0	2045	0	0
T111	0	6884	0	0
T112	0	5536	0	0
T113	505646	0	0	0
T114	129280	0	0	0
T115	199432	0	0	0
T116	594072	0	0	0
T117	118263	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	219618	0	0
T14	922291	9565	0	0
T15	922719	0	0	0
T16	100692	41	0	0
T19	117288	0	0	0
T29	1450	0	0	0
T35	0	13063	0	0
T36	0	1100	0	0
T39	0	4062	0	0
T44	305889	0	0	0
T107	0	3487	0	0
T108	0	1890	0	0
T109	0	6129	0	0
T113	505646	0	0	0
T114	129280	0	0	0
T115	199432	0	0	0
T116	594072	0	0	0
T118	0	5	0	0
T119	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	246232	0	0
T14	922291	10872	0	0
T15	922719	0	0	0
T19	117288	0	0	0
T29	1450	0	0	0
T35	0	14676	0	0
T36	0	1147	0	0
T39	0	4382	0	0
T44	305889	0	0	0
T107	0	3430	0	0
T108	0	2141	0	0
T109	0	6959	0	0
T110	0	1907	0	0
T111	0	6525	0	0
T112	0	5608	0	0
T113	505646	0	0	0
T114	129280	0	0	0
T115	199432	0	0	0
T116	594072	0	0	0
T117	118263	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	247468	0	0
T14	922291	11000	0	0
T15	922719	0	0	0
T19	117288	0	0	0
T29	1450	0	0	0
T35	0	14281	0	0
T36	0	1065	0	0
T39	0	4453	0	0
T44	305889	0	0	0
T107	0	3693	0	0
T108	0	2180	0	0
T109	0	6784	0	0
T110	0	1975	0	0
T111	0	6755	0	0
T112	0	5468	0	0
T113	505646	0	0	0
T114	129280	0	0	0
T115	199432	0	0	0
T116	594072	0	0	0
T117	118263	0	0	0