Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	75351981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28105007

1

T1

90

T2

373

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93439368	1			T1	6477		T2	18048		T3	1
values[0x0]	4732506	1			T1	51		T2	129		T3	5
values[0x1]	5285114	1			T1	50		T2	147		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52050572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51406416

1

T1

2231

T2

6218

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	379326	1			T1	28		T4	1		T5	36
valid_sources[0x01]	373855	1			T1	27		T4	1		T5	38
valid_sources[0x02]	450890	1			T1	29		T4	5		T5	37
valid_sources[0x03]	498853	1			T1	31		T4	5		T5	53
valid_sources[0x04]	410536	1			T1	22		T4	1		T5	55
valid_sources[0x05]	383377	1			T1	19		T4	1		T5	33
valid_sources[0x06]	381087	1			T1	25		T2	1		T4	4
valid_sources[0x07]	387832	1			T1	32		T4	1		T5	47
valid_sources[0x08]	410656	1			T1	29		T4	1		T5	53
valid_sources[0x09]	403411	1			T1	26		T5	58		T6	7
valid_sources[0x0a]	395616	1			T1	27		T4	4		T5	56
valid_sources[0x0b]	373887	1			T1	20		T4	4		T5	43
valid_sources[0x0c]	369531	1			T1	30		T4	4		T5	48
valid_sources[0x0d]	392892	1			T1	29		T4	1		T5	57
valid_sources[0x0e]	388846	1			T1	24		T4	4		T5	24
valid_sources[0x0f]	366018	1			T1	23		T4	1		T5	59
valid_sources[0x10]	381419	1			T1	26		T4	3		T5	61
valid_sources[0x11]	440954	1			T1	34		T4	5		T5	24
valid_sources[0x12]	384470	1			T1	13		T4	2		T5	60
valid_sources[0x13]	385722	1			T1	28		T3	2		T4	2
valid_sources[0x14]	416638	1			T1	23		T4	7		T5	62
valid_sources[0x15]	384354	1			T1	39		T4	3		T5	62
valid_sources[0x16]	357050	1			T1	31		T4	3		T5	52
valid_sources[0x17]	406563	1			T1	19		T4	3		T5	29
valid_sources[0x18]	378948	1			T1	29		T4	6		T5	55
valid_sources[0x19]	420391	1			T1	28		T4	2		T5	53
valid_sources[0x1a]	444209	1			T1	27		T4	3		T5	37
valid_sources[0x1b]	408671	1			T1	23		T4	1		T5	21
valid_sources[0x1c]	389650	1			T1	21		T3	1		T4	3
valid_sources[0x1d]	388480	1			T1	21		T4	2		T5	52
valid_sources[0x1e]	390327	1			T1	25		T4	5		T5	50
valid_sources[0x1f]	424974	1			T1	24		T5	69		T6	22
valid_sources[0x20]	394860	1			T1	24		T5	28		T6	5
valid_sources[0x21]	379638	1			T1	18		T4	4		T5	38
valid_sources[0x22]	377153	1			T1	26		T4	4		T5	51
valid_sources[0x23]	512955	1			T1	18		T4	3		T5	73
valid_sources[0x24]	439015	1			T1	21		T4	2		T5	59
valid_sources[0x25]	375077	1			T1	14		T4	5		T5	33
valid_sources[0x26]	400822	1			T1	17		T4	2		T5	41
valid_sources[0x27]	381568	1			T1	26		T4	4		T5	47
valid_sources[0x28]	380559	1			T1	26		T4	3		T5	54
valid_sources[0x29]	373963	1			T1	36		T4	5		T5	43
valid_sources[0x2a]	385537	1			T1	26		T4	4		T5	40
valid_sources[0x2b]	388160	1			T1	18		T4	1		T5	49
valid_sources[0x2c]	413022	1			T1	9		T4	6		T5	46
valid_sources[0x2d]	497765	1			T1	26		T4	2		T5	46
valid_sources[0x2e]	373805	1			T1	23		T4	4		T5	51
valid_sources[0x2f]	394079	1			T1	29		T4	5		T5	44
valid_sources[0x30]	409410	1			T1	28		T4	1		T5	53
valid_sources[0x31]	400185	1			T1	28		T4	6		T5	58
valid_sources[0x32]	384982	1			T1	28		T4	3		T5	43
valid_sources[0x33]	373960	1			T1	33		T4	2		T5	21
valid_sources[0x34]	383290	1			T1	31		T4	2		T5	51
valid_sources[0x35]	376073	1			T1	29		T4	3		T5	32
valid_sources[0x36]	362421	1			T1	40		T4	3		T5	52
valid_sources[0x37]	467405	1			T1	27		T4	5		T5	67
valid_sources[0x38]	409084	1			T1	21		T4	2		T5	32
valid_sources[0x39]	373258	1			T1	30		T4	2		T5	35
valid_sources[0x3a]	401415	1			T1	37		T2	1889		T4	2
valid_sources[0x3b]	367066	1			T1	20		T4	2		T5	38
valid_sources[0x3c]	388145	1			T1	19		T4	3		T5	38
valid_sources[0x3d]	382689	1			T1	26		T4	4		T5	54
valid_sources[0x3e]	381262	1			T1	33		T4	2		T5	42
valid_sources[0x3f]	411831	1			T1	25		T4	2		T5	45
valid_sources[0x40]	370848	1			T1	21		T4	1		T5	42
valid_sources[0x41]	395566	1			T1	27		T4	6		T5	62
valid_sources[0x42]	374252	1			T1	18		T4	1		T5	54
valid_sources[0x43]	401468	1			T1	23		T4	2		T5	66
valid_sources[0x44]	461602	1			T1	21		T4	2		T5	32
valid_sources[0x45]	388871	1			T1	33		T4	5		T5	59
valid_sources[0x46]	417926	1			T1	31		T4	3		T5	62
valid_sources[0x47]	459817	1			T1	20		T4	4		T5	40
valid_sources[0x48]	429893	1			T1	29		T2	453		T4	2
valid_sources[0x49]	350050	1			T1	15		T4	8		T5	47
valid_sources[0x4a]	398617	1			T1	28		T2	3368		T4	6
valid_sources[0x4b]	371004	1			T1	27		T4	4		T5	46
valid_sources[0x4c]	354220	1			T1	32		T4	4		T5	53
valid_sources[0x4d]	364176	1			T1	20		T4	2		T5	53
valid_sources[0x4e]	381270	1			T1	20		T4	3		T5	57
valid_sources[0x4f]	396851	1			T1	23		T4	6		T5	63
valid_sources[0x50]	359998	1			T1	28		T4	3		T5	54
valid_sources[0x51]	405445	1			T1	27		T4	1		T5	48
valid_sources[0x52]	427199	1			T1	26		T4	5		T5	63
valid_sources[0x53]	395378	1			T1	22		T4	1		T5	56
valid_sources[0x54]	365458	1			T1	22		T4	3		T5	46
valid_sources[0x55]	474594	1			T1	27		T4	5		T5	62
valid_sources[0x56]	376614	1			T1	31		T4	4		T5	54
valid_sources[0x57]	405932	1			T1	32		T3	1		T4	2
valid_sources[0x58]	381811	1			T1	25		T4	3		T5	40
valid_sources[0x59]	399634	1			T1	33		T3	1		T4	1
valid_sources[0x5a]	415258	1			T1	27		T4	2		T5	51
valid_sources[0x5b]	374995	1			T1	28		T4	2		T5	36
valid_sources[0x5c]	394236	1			T1	25		T4	5		T5	55
valid_sources[0x5d]	379331	1			T1	25		T4	4		T5	50
valid_sources[0x5e]	428020	1			T1	28		T4	1		T5	37
valid_sources[0x5f]	456184	1			T1	20		T4	4		T5	49
valid_sources[0x60]	376986	1			T1	22		T4	2		T5	34
valid_sources[0x61]	366146	1			T1	34		T4	5		T5	39
valid_sources[0x62]	408827	1			T1	26		T4	4		T5	30
valid_sources[0x63]	376152	1			T1	25		T4	3		T5	55
valid_sources[0x64]	375404	1			T1	27		T4	5		T5	58
valid_sources[0x65]	420407	1			T1	27		T4	3		T5	33
valid_sources[0x66]	487495	1			T1	27		T4	1		T5	55
valid_sources[0x67]	424684	1			T1	27		T4	6		T5	47
valid_sources[0x68]	389900	1			T1	20		T4	5		T5	33
valid_sources[0x69]	454895	1			T1	22		T4	2		T5	37
valid_sources[0x6a]	415221	1			T1	25		T4	3		T5	69
valid_sources[0x6b]	371097	1			T1	34		T4	3		T5	50
valid_sources[0x6c]	453750	1			T1	29		T4	2		T5	73
valid_sources[0x6d]	407129	1			T1	24		T4	7		T5	61
valid_sources[0x6e]	381156	1			T1	29		T4	3		T5	62
valid_sources[0x6f]	434800	1			T1	30		T4	4		T5	40
valid_sources[0x70]	421386	1			T1	28		T4	3		T5	57
valid_sources[0x71]	486700	1			T1	27		T4	2		T5	29
valid_sources[0x72]	403506	1			T1	16		T4	2		T5	43
valid_sources[0x73]	410731	1			T1	25		T4	2		T5	52
valid_sources[0x74]	413585	1			T1	27		T4	2		T5	46
valid_sources[0x75]	396820	1			T1	32		T4	5		T5	35
valid_sources[0x76]	469182	1			T1	32		T4	5		T5	56
valid_sources[0x77]	401403	1			T1	28		T4	5		T5	49
valid_sources[0x78]	397380	1			T1	33		T4	3		T5	48
valid_sources[0x79]	916559	1			T1	30		T4	5		T5	55
valid_sources[0x7a]	396107	1			T1	19		T4	3		T5	45
valid_sources[0x7b]	371139	1			T1	21		T4	8		T5	39
valid_sources[0x7c]	422666	1			T1	31		T4	3		T5	48
valid_sources[0x7d]	408052	1			T1	19		T5	50		T6	5
valid_sources[0x7e]	371620	1			T1	23		T4	2		T5	64
valid_sources[0x7f]	361945	1			T1	19		T4	9		T5	40
valid_sources[0x80]	397449	1			T1	19		T4	5		T5	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19258009

1

T1

66

T2

277

T4

83

values[0x0]

all_enables

biggest_size

4451990

1

T1

16

T2

51

T3

2

values[0x1]

all_enables

biggest_size

4395008

1

T1

8

T2

45

T4

31