Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14654533	0	0
ctrl_rd_A	2147483647	251311	0	0
intr_enable_rd_A	2147483647	221920	0	0
ovrd_rd_A	2147483647	251566	0	0
timeout_ctrl_rd_A	2147483647	251044	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14654533	0	0
T13	0	158075	0	0
T15	179546	75403	0	0
T18	249651	100896	0	0
T19	27508	0	0	0
T22	142754	54265	0	0
T23	828267	0	0	0
T24	604072	234441	0	0
T34	0	60285	0	0
T35	0	123941	0	0
T36	0	93064	0	0
T37	0	140192	0	0
T38	0	203200	0	0
T39	216330	0	0	0
T40	16767	0	0	0
T41	324885	0	0	0
T42	249804	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251311	0	0
T14	545877	0	0	0
T20	206648	0	0	0
T27	1073	0	0	0
T34	199314	3448	0	0
T35	0	14167	0	0
T37	0	15275	0	0
T55	0	11194	0	0
T68	0	24118	0	0
T113	0	4047	0	0
T114	0	6988	0	0
T115	0	9785	0	0
T116	0	3062	0	0
T117	0	5205	0	0
T118	228735	0	0	0
T119	253504	0	0	0
T120	141120	0	0	0
T121	2099	0	0	0
T122	319612	0	0	0
T123	19093	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	221920	0	0
T14	545877	0	0	0
T20	206648	0	0	0
T27	1073	0	0	0
T34	199314	2937	0	0
T35	0	12312	0	0
T37	0	12742	0	0
T55	0	9571	0	0
T68	0	21100	0	0
T113	0	3336	0	0
T114	0	6212	0	0
T115	0	9021	0	0
T116	0	2635	0	0
T118	228735	0	0	0
T119	253504	0	0	0
T120	141120	0	0	0
T121	2099	0	0	0
T122	319612	0	0	0
T123	19093	0	0	0
T124	0	25	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251566	0	0
T14	545877	0	0	0
T20	206648	0	0	0
T27	1073	0	0	0
T34	199314	3551	0	0
T35	0	14294	0	0
T37	0	14534	0	0
T55	0	10968	0	0
T68	0	23951	0	0
T113	0	3836	0	0
T114	0	6983	0	0
T115	0	10429	0	0
T116	0	2767	0	0
T117	0	5412	0	0
T118	228735	0	0	0
T119	253504	0	0	0
T120	141120	0	0	0
T121	2099	0	0	0
T122	319612	0	0	0
T123	19093	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251044	0	0
T14	545877	0	0	0
T20	206648	0	0	0
T27	1073	0	0	0
T34	199314	3235	0	0
T35	0	14510	0	0
T37	0	14604	0	0
T55	0	10978	0	0
T68	0	23397	0	0
T113	0	4123	0	0
T114	0	7188	0	0
T115	0	9909	0	0
T116	0	3070	0	0
T117	0	5464	0	0
T118	228735	0	0	0
T119	253504	0	0	0
T120	141120	0	0	0
T121	2099	0	0	0
T122	319612	0	0	0
T123	19093	0	0	0