Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14899424	0	0
ctrl_rd_A	2147483647	226612	0	0
intr_enable_rd_A	2147483647	200933	0	0
ovrd_rd_A	2147483647	225329	0	0
timeout_ctrl_rd_A	2147483647	226364	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14899424	0	0
T5	230652	72406	0	0
T6	511522	0	0	0
T7	30989	0	0	0
T8	891990	0	0	0
T9	200216	0	0	0
T10	118904	0	0	0
T11	530029	200329	0	0
T13	136223	37584	0	0
T16	0	190327	0	0
T18	0	28343	0	0
T26	0	256916	0	0
T27	0	65913	0	0
T28	0	160663	0	0
T29	0	294899	0	0
T30	0	54072	0	0
T31	44731	0	0	0
T32	166945	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	226612	0	0
T5	230652	3832	0	0
T6	511522	0	0	0
T7	30989	0	0	0
T8	891990	0	0	0
T9	200216	0	0	0
T10	118904	0	0	0
T11	530029	0	0	0
T13	136223	0	0	0
T31	44731	0	0	0
T32	166945	0	0	0
T40	0	9968	0	0
T42	0	4141	0	0
T97	0	5903	0	0
T98	0	6607	0	0
T99	0	12087	0	0
T100	0	5059	0	0
T101	0	10841	0	0
T102	0	4581	0	0
T103	0	9677	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	200933	0	0
T5	230652	3435	0	0
T6	511522	0	0	0
T7	30989	0	0	0
T8	891990	0	0	0
T9	200216	0	0	0
T10	118904	0	0	0
T11	530029	0	0	0
T13	136223	0	0	0
T31	44731	0	0	0
T32	166945	0	0	0
T40	0	8872	0	0
T42	0	3656	0	0
T97	0	5251	0	0
T98	0	5751	0	0
T99	0	10314	0	0
T100	0	4199	0	0
T101	0	9585	0	0
T102	0	4120	0	0
T103	0	8382	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225329	0	0
T5	230652	4074	0	0
T6	511522	0	0	0
T7	30989	0	0	0
T8	891990	0	0	0
T9	200216	0	0	0
T10	118904	0	0	0
T11	530029	0	0	0
T13	136223	0	0	0
T31	44731	0	0	0
T32	166945	0	0	0
T40	0	10202	0	0
T42	0	3828	0	0
T97	0	5979	0	0
T98	0	6328	0	0
T99	0	11482	0	0
T100	0	5012	0	0
T101	0	10476	0	0
T102	0	4594	0	0
T103	0	9585	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	226364	0	0
T5	230652	3987	0	0
T6	511522	0	0	0
T7	30989	0	0	0
T8	891990	0	0	0
T9	200216	0	0	0
T10	118904	0	0	0
T11	530029	0	0	0
T13	136223	0	0	0
T31	44731	0	0	0
T32	166945	0	0	0
T40	0	10024	0	0
T42	0	3817	0	0
T97	0	6039	0	0
T98	0	6643	0	0
T99	0	11164	0	0
T100	0	5084	0	0
T101	0	11188	0	0
T102	0	4286	0	0
T103	0	9967	0	0