Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78401211	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29456736

1

T1

12

T2

70

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	97590170	1			T1	939		T2	2905		T3	232202
values[0x0]	4854013	1			T1	5		T2	40		T3	53
values[0x1]	5413764	1			T1	8		T2	31		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54220357	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53637590

1

T1

350

T2

1036

T3

77279

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	402967	1			T2	17		T3	825		T4	33
valid_sources[0x01]	380548	1			T2	16		T3	823		T4	26
valid_sources[0x02]	448346	1			T2	5		T3	878		T4	22
valid_sources[0x03]	386913	1			T2	7		T3	935		T4	24
valid_sources[0x04]	426283	1			T2	19		T3	870		T4	20
valid_sources[0x05]	393449	1			T2	11		T3	895		T4	25
valid_sources[0x06]	495641	1			T2	16		T3	916		T4	27
valid_sources[0x07]	400275	1			T2	13		T3	879		T4	27
valid_sources[0x08]	442095	1			T2	52		T3	886		T4	34
valid_sources[0x09]	404613	1			T2	17		T3	856		T4	33
valid_sources[0x0a]	476839	1			T2	17		T3	1067		T4	28
valid_sources[0x0b]	393449	1			T3	956		T4	32		T6	826
valid_sources[0x0c]	393216	1			T2	76		T3	916		T4	20
valid_sources[0x0d]	427372	1			T2	2		T3	856		T4	34
valid_sources[0x0e]	397424	1			T2	1		T3	865		T4	27
valid_sources[0x0f]	429620	1			T2	11		T3	835		T4	32
valid_sources[0x10]	438336	1			T3	930		T4	29		T6	836
valid_sources[0x11]	401469	1			T2	18		T3	866		T4	28
valid_sources[0x12]	475598	1			T2	10		T3	998		T4	31
valid_sources[0x13]	429326	1			T2	13		T3	971		T4	29
valid_sources[0x14]	414863	1			T2	38		T3	961		T4	27
valid_sources[0x15]	395172	1			T2	4		T3	878		T4	36
valid_sources[0x16]	393956	1			T3	845		T4	24		T6	859
valid_sources[0x17]	403567	1			T2	3		T3	916		T4	23
valid_sources[0x18]	454821	1			T2	8		T3	1002		T4	39
valid_sources[0x19]	390157	1			T2	15		T3	905		T4	22
valid_sources[0x1a]	453974	1			T2	1		T3	867		T4	29
valid_sources[0x1b]	414630	1			T2	1		T3	845		T4	25
valid_sources[0x1c]	415749	1			T3	929		T4	33		T6	966
valid_sources[0x1d]	439435	1			T3	989		T4	24		T6	994
valid_sources[0x1e]	473923	1			T3	834		T4	29		T6	811
valid_sources[0x1f]	444378	1			T2	14		T3	883		T4	29
valid_sources[0x20]	401035	1			T2	3		T3	919		T4	25
valid_sources[0x21]	399153	1			T2	6		T3	956		T4	25
valid_sources[0x22]	489096	1			T2	8		T3	992		T4	33
valid_sources[0x23]	382476	1			T2	3		T3	888		T4	25
valid_sources[0x24]	422089	1			T3	913		T4	24		T6	786
valid_sources[0x25]	442088	1			T3	816		T4	28		T6	796
valid_sources[0x26]	389223	1			T2	8		T3	965		T4	22
valid_sources[0x27]	530579	1			T2	2		T3	837		T4	28
valid_sources[0x28]	391865	1			T2	19		T3	1024		T4	23
valid_sources[0x29]	440527	1			T2	21		T3	1017		T4	33
valid_sources[0x2a]	432288	1			T3	848		T4	25		T6	903
valid_sources[0x2b]	397674	1			T2	9		T3	875		T4	25
valid_sources[0x2c]	393515	1			T2	16		T3	934		T4	20
valid_sources[0x2d]	399135	1			T2	16		T3	905		T4	31
valid_sources[0x2e]	428051	1			T1	224		T2	7		T3	1015
valid_sources[0x2f]	437860	1			T2	2		T3	934		T4	24
valid_sources[0x30]	419794	1			T2	9		T3	978		T4	33
valid_sources[0x31]	396049	1			T3	875		T4	44		T6	1013
valid_sources[0x32]	437261	1			T2	8		T3	903		T4	28
valid_sources[0x33]	493985	1			T3	837		T4	25		T6	795
valid_sources[0x34]	401177	1			T2	10		T3	764		T4	16
valid_sources[0x35]	378570	1			T2	6		T3	943		T4	38
valid_sources[0x36]	415781	1			T2	11		T3	891		T4	24
valid_sources[0x37]	401176	1			T2	29		T3	832		T4	31
valid_sources[0x38]	413366	1			T2	14		T3	805		T4	35
valid_sources[0x39]	414210	1			T2	11		T3	993		T4	29
valid_sources[0x3a]	400522	1			T3	942		T4	28		T6	872
valid_sources[0x3b]	530268	1			T2	3		T3	792		T4	27
valid_sources[0x3c]	484028	1			T2	25		T3	866		T4	26
valid_sources[0x3d]	400584	1			T2	20		T3	1021		T4	22
valid_sources[0x3e]	406821	1			T2	2		T3	827		T4	19
valid_sources[0x3f]	406204	1			T2	10		T3	871		T4	26
valid_sources[0x40]	388040	1			T2	7		T3	994		T4	36
valid_sources[0x41]	412808	1			T2	13		T3	938		T4	26
valid_sources[0x42]	415711	1			T2	10		T3	840		T4	30
valid_sources[0x43]	400141	1			T2	6		T3	777		T4	19
valid_sources[0x44]	531522	1			T2	20		T3	930		T4	26
valid_sources[0x45]	419178	1			T2	28		T3	841		T4	25
valid_sources[0x46]	433532	1			T2	5		T3	877		T4	41
valid_sources[0x47]	398937	1			T3	880		T4	25		T6	997
valid_sources[0x48]	409317	1			T2	31		T3	829		T4	45
valid_sources[0x49]	555915	1			T2	6		T3	920		T4	25
valid_sources[0x4a]	423379	1			T2	13		T3	932		T4	17
valid_sources[0x4b]	388539	1			T2	10		T3	902		T4	39
valid_sources[0x4c]	486303	1			T2	10		T3	1041		T4	27
valid_sources[0x4d]	406171	1			T2	3		T3	918		T4	38
valid_sources[0x4e]	417168	1			T3	931		T4	21		T6	780
valid_sources[0x4f]	393568	1			T3	897		T4	40		T6	922
valid_sources[0x50]	409586	1			T3	807		T4	17		T6	949
valid_sources[0x51]	425265	1			T2	31		T3	826		T4	27
valid_sources[0x52]	395688	1			T2	6		T3	936		T4	24
valid_sources[0x53]	438213	1			T2	13		T3	875		T4	19
valid_sources[0x54]	445049	1			T2	8		T3	892		T4	38
valid_sources[0x55]	411111	1			T2	6		T3	933		T4	28
valid_sources[0x56]	492701	1			T2	1		T3	841		T4	28
valid_sources[0x57]	453511	1			T2	24		T3	932		T4	25
valid_sources[0x58]	400404	1			T1	66		T2	3		T3	909
valid_sources[0x59]	462303	1			T2	1		T3	888		T4	30
valid_sources[0x5a]	407042	1			T2	18		T3	949		T4	29
valid_sources[0x5b]	430529	1			T2	6		T3	1001		T4	27
valid_sources[0x5c]	373312	1			T2	38		T3	901		T4	25
valid_sources[0x5d]	406712	1			T3	798		T4	23		T6	851
valid_sources[0x5e]	389740	1			T2	6		T3	828		T4	25
valid_sources[0x5f]	407238	1			T2	24		T3	901		T4	20
valid_sources[0x60]	534229	1			T2	34		T3	978		T4	28
valid_sources[0x61]	405305	1			T2	15		T3	837		T4	20
valid_sources[0x62]	374915	1			T2	2		T3	790		T4	39
valid_sources[0x63]	432803	1			T2	2		T3	806		T4	29
valid_sources[0x64]	395651	1			T2	3		T3	836		T4	21
valid_sources[0x65]	408795	1			T2	2		T3	973		T4	33
valid_sources[0x66]	393179	1			T2	39		T3	959		T4	31
valid_sources[0x67]	393164	1			T3	954		T4	20		T6	701
valid_sources[0x68]	397316	1			T2	3		T3	899		T4	30
valid_sources[0x69]	488883	1			T2	12		T3	870		T4	32
valid_sources[0x6a]	390605	1			T3	892		T4	28		T6	883
valid_sources[0x6b]	453396	1			T2	15		T3	931		T4	41
valid_sources[0x6c]	386822	1			T2	7		T3	867		T4	28
valid_sources[0x6d]	422414	1			T2	17		T3	973		T4	29
valid_sources[0x6e]	383920	1			T2	42		T3	874		T4	25
valid_sources[0x6f]	397464	1			T2	17		T3	916		T4	25
valid_sources[0x70]	503381	1			T3	861		T4	37		T5	7
valid_sources[0x71]	419078	1			T2	14		T3	882		T4	22
valid_sources[0x72]	421489	1			T3	923		T4	31		T6	818
valid_sources[0x73]	416697	1			T1	100		T2	7		T3	858
valid_sources[0x74]	390435	1			T2	46		T3	927		T4	16
valid_sources[0x75]	380343	1			T2	15		T3	931		T4	22
valid_sources[0x76]	424280	1			T2	11		T3	960		T4	25
valid_sources[0x77]	431245	1			T2	12		T3	934		T4	20
valid_sources[0x78]	413672	1			T2	6		T3	899		T4	14
valid_sources[0x79]	445236	1			T2	22		T3	804		T4	26
valid_sources[0x7a]	410545	1			T2	11		T3	962		T4	16
valid_sources[0x7b]	432748	1			T2	2		T3	874		T4	29
valid_sources[0x7c]	412006	1			T2	3		T3	899		T4	33
valid_sources[0x7d]	455431	1			T2	9		T3	949		T4	22
valid_sources[0x7e]	447510	1			T2	13		T3	1007		T4	40
valid_sources[0x7f]	369906	1			T2	15		T3	964		T4	25
valid_sources[0x80]	373322	1			T2	7		T3	772		T4	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20348826

1

T1

8

T2

45

T3

19

values[0x0]

all_enables

biggest_size

4584363

1

T1

2

T2

12

T3

26

values[0x1]

all_enables

biggest_size

4523547

1

T1

2

T2

13

T3

11