Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15027860	0	0
ctrl_rd_A	2147483647	317304	0	0
intr_enable_rd_A	2147483647	286567	0	0
ovrd_rd_A	2147483647	317721	0	0
timeout_ctrl_rd_A	2147483647	319323	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15027860	0	0
T12	107381	0	0	0
T13	166650	34915	0	0
T14	473013	189377	0	0
T20	13533	0	0	0
T22	0	200752	0	0
T24	247876	0	0	0
T26	948	0	0	0
T32	0	89323	0	0
T33	0	119460	0	0
T34	0	154377	0	0
T35	0	24031	0	0
T36	0	92236	0	0
T37	0	65907	0	0
T38	0	203084	0	0
T39	131481	0	0	0
T40	129672	0	0	0
T41	22568	0	0	0
T42	734425	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	317304	0	0
T12	107381	0	0	0
T13	166650	4262	0	0
T14	473013	0	0	0
T20	13533	0	0	0
T24	247876	0	0	0
T26	948	0	0	0
T32	0	8923	0	0
T34	0	17567	0	0
T35	0	2572	0	0
T36	0	6078	0	0
T39	131481	0	0	0
T40	129672	0	0	0
T41	22568	0	0	0
T42	734425	0	0	0
T106	0	3181	0	0
T107	0	1618	0	0
T108	0	4746	0	0
T109	0	3074	0	0
T110	0	4477	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	286567	0	0
T12	107381	0	0	0
T13	166650	3474	0	0
T14	473013	0	0	0
T20	13533	0	0	0
T24	247876	0	0	0
T26	948	0	0	0
T32	0	8770	0	0
T34	0	16176	0	0
T35	0	2323	0	0
T36	0	5917	0	0
T39	131481	0	0	0
T40	129672	0	0	0
T41	22568	0	0	0
T42	734425	0	0	0
T106	0	2814	0	0
T107	0	1550	0	0
T108	0	4307	0	0
T109	0	2655	0	0
T110	0	3966	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	317721	0	0
T12	107381	0	0	0
T13	166650	3572	0	0
T14	473013	0	0	0
T20	13533	0	0	0
T24	247876	0	0	0
T26	948	0	0	0
T32	0	9775	0	0
T34	0	18318	0	0
T35	0	2534	0	0
T36	0	6218	0	0
T39	131481	0	0	0
T40	129672	0	0	0
T41	22568	0	0	0
T42	734425	0	0	0
T106	0	3458	0	0
T107	0	1641	0	0
T108	0	4932	0	0
T109	0	3038	0	0
T110	0	4817	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	319323	0	0
T12	107381	0	0	0
T13	166650	3494	0	0
T14	473013	0	0	0
T20	13533	0	0	0
T24	247876	0	0	0
T26	948	0	0	0
T32	0	9763	0	0
T34	0	17942	0	0
T35	0	2584	0	0
T36	0	6270	0	0
T39	131481	0	0	0
T40	129672	0	0	0
T41	22568	0	0	0
T42	734425	0	0	0
T106	0	3192	0	0
T107	0	1669	0	0
T108	0	4813	0	0
T109	0	2931	0	0
T110	0	4816	0	0