Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13989622	0	0
ctrl_rd_A	2147483647	269152	0	0
intr_enable_rd_A	2147483647	239205	0	0
ovrd_rd_A	2147483647	268886	0	0
timeout_ctrl_rd_A	2147483647	270785	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13989622	0	0
T14	389508	121080	0	0
T15	0	283056	0	0
T20	0	208482	0	0
T22	188808	0	0	0
T29	0	258970	0	0
T30	0	148574	0	0
T31	0	47618	0	0
T32	0	193933	0	0
T33	0	154531	0	0
T34	0	163373	0	0
T35	0	589741	0	0
T36	671064	0	0	0
T37	161180	0	0	0
T38	9145	0	0	0
T39	539384	0	0	0
T40	130577	0	0	0
T41	380868	0	0	0
T42	15783	0	0	0
T43	492759	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	269152	0	0
T14	389508	6184	0	0
T22	188808	0	0	0
T34	0	18472	0	0
T36	671064	0	0	0
T37	161180	0	0	0
T38	9145	0	0	0
T39	539384	0	0	0
T40	130577	0	0	0
T41	380868	0	0	0
T42	15783	0	0	0
T43	492759	0	0	0
T55	0	16227	0	0
T112	0	9364	0	0
T113	0	15026	0	0
T114	0	2223	0	0
T115	0	16160	0	0
T116	0	5048	0	0
T117	0	7150	0	0
T118	0	1725	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	239205	0	0
T14	389508	5778	0	0
T19	0	11	0	0
T22	188808	0	0	0
T34	0	16491	0	0
T36	671064	0	0	0
T37	161180	0	0	0
T38	9145	0	0	0
T39	539384	0	0	0
T40	130577	0	0	0
T41	380868	0	0	0
T42	15783	0	0	0
T43	492759	0	0	0
T55	0	14213	0	0
T112	0	8471	0	0
T113	0	13288	0	0
T114	0	1868	0	0
T115	0	13646	0	0
T116	0	4294	0	0
T117	0	6429	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	268886	0	0
T14	389508	6312	0	0
T22	188808	0	0	0
T34	0	17833	0	0
T36	671064	0	0	0
T37	161180	0	0	0
T38	9145	0	0	0
T39	539384	0	0	0
T40	130577	0	0	0
T41	380868	0	0	0
T42	15783	0	0	0
T43	492759	0	0	0
T55	0	16686	0	0
T112	0	9518	0	0
T113	0	14730	0	0
T114	0	2528	0	0
T115	0	15846	0	0
T116	0	5069	0	0
T117	0	7480	0	0
T118	0	1792	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	270785	0	0
T14	389508	6401	0	0
T22	188808	0	0	0
T34	0	18495	0	0
T36	671064	0	0	0
T37	161180	0	0	0
T38	9145	0	0	0
T39	539384	0	0	0
T40	130577	0	0	0
T41	380868	0	0	0
T42	15783	0	0	0
T43	492759	0	0	0
T55	0	16947	0	0
T112	0	9303	0	0
T113	0	15071	0	0
T114	0	2386	0	0
T115	0	15829	0	0
T116	0	5154	0	0
T117	0	7201	0	0
T118	0	1881	0	0