Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.61


Total test records in report: 1317
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1261 /workspace/coverage/cover_reg_top/8.uart_csr_rw.465435503 Apr 23 02:45:45 PM PDT 24 Apr 23 02:45:46 PM PDT 24 18396298 ps
T101 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2891322940 Apr 23 02:45:50 PM PDT 24 Apr 23 02:45:52 PM PDT 24 95372423 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4217443962 Apr 23 02:45:41 PM PDT 24 Apr 23 02:45:42 PM PDT 24 107870713 ps
T1263 /workspace/coverage/cover_reg_top/4.uart_intr_test.460272707 Apr 23 02:45:37 PM PDT 24 Apr 23 02:45:38 PM PDT 24 38104131 ps
T1264 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1452282770 Apr 23 02:45:29 PM PDT 24 Apr 23 02:45:31 PM PDT 24 267059041 ps
T81 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3458597268 Apr 23 02:45:48 PM PDT 24 Apr 23 02:45:49 PM PDT 24 17049391 ps
T1265 /workspace/coverage/cover_reg_top/27.uart_intr_test.523751166 Apr 23 02:46:07 PM PDT 24 Apr 23 02:46:08 PM PDT 24 11040553 ps
T1266 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2554003384 Apr 23 02:45:52 PM PDT 24 Apr 23 02:45:53 PM PDT 24 84947721 ps
T1267 /workspace/coverage/cover_reg_top/10.uart_intr_test.2445127470 Apr 23 02:45:48 PM PDT 24 Apr 23 02:45:49 PM PDT 24 17659661 ps
T1268 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3756560388 Apr 23 02:45:50 PM PDT 24 Apr 23 02:45:52 PM PDT 24 709688105 ps
T1269 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4196697578 Apr 23 02:45:56 PM PDT 24 Apr 23 02:45:57 PM PDT 24 20792293 ps
T1270 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1423999839 Apr 23 02:45:40 PM PDT 24 Apr 23 02:45:41 PM PDT 24 60546959 ps
T1271 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1322501099 Apr 23 02:45:56 PM PDT 24 Apr 23 02:45:57 PM PDT 24 107371759 ps
T1272 /workspace/coverage/cover_reg_top/47.uart_intr_test.2264868483 Apr 23 02:46:10 PM PDT 24 Apr 23 02:46:11 PM PDT 24 14885296 ps
T1273 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1457540717 Apr 23 02:45:55 PM PDT 24 Apr 23 02:45:56 PM PDT 24 12084844 ps
T1274 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4071052264 Apr 23 02:45:35 PM PDT 24 Apr 23 02:45:36 PM PDT 24 138615222 ps
T1275 /workspace/coverage/cover_reg_top/28.uart_intr_test.3371487837 Apr 23 02:46:06 PM PDT 24 Apr 23 02:46:07 PM PDT 24 100712971 ps
T1276 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.559462914 Apr 23 02:45:56 PM PDT 24 Apr 23 02:45:57 PM PDT 24 17404905 ps
T65 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2706084006 Apr 23 02:45:33 PM PDT 24 Apr 23 02:45:34 PM PDT 24 31281246 ps
T1277 /workspace/coverage/cover_reg_top/45.uart_intr_test.3269641914 Apr 23 02:46:08 PM PDT 24 Apr 23 02:46:09 PM PDT 24 26794932 ps
T66 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4126781288 Apr 23 02:45:34 PM PDT 24 Apr 23 02:45:35 PM PDT 24 16007976 ps
T1278 /workspace/coverage/cover_reg_top/13.uart_intr_test.3039338348 Apr 23 02:45:52 PM PDT 24 Apr 23 02:45:53 PM PDT 24 11273372 ps
T1279 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2198764224 Apr 23 02:45:49 PM PDT 24 Apr 23 02:45:50 PM PDT 24 132958307 ps
T67 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.997316660 Apr 23 02:45:35 PM PDT 24 Apr 23 02:45:38 PM PDT 24 1129066949 ps
T1280 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2921624746 Apr 23 02:46:01 PM PDT 24 Apr 23 02:46:02 PM PDT 24 48899903 ps
T96 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1816099904 Apr 23 02:45:31 PM PDT 24 Apr 23 02:45:33 PM PDT 24 156677113 ps
T1281 /workspace/coverage/cover_reg_top/19.uart_tl_errors.457649662 Apr 23 02:46:02 PM PDT 24 Apr 23 02:46:05 PM PDT 24 177910051 ps
T1282 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1700604306 Apr 23 02:45:36 PM PDT 24 Apr 23 02:45:37 PM PDT 24 105976752 ps
T1283 /workspace/coverage/cover_reg_top/43.uart_intr_test.2060094700 Apr 23 02:46:09 PM PDT 24 Apr 23 02:46:11 PM PDT 24 69885157 ps
T1284 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2899256506 Apr 23 02:45:56 PM PDT 24 Apr 23 02:45:57 PM PDT 24 51311130 ps
T1285 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.606534306 Apr 23 02:45:47 PM PDT 24 Apr 23 02:45:48 PM PDT 24 24490551 ps
T1286 /workspace/coverage/cover_reg_top/20.uart_intr_test.1366674786 Apr 23 02:46:02 PM PDT 24 Apr 23 02:46:03 PM PDT 24 12347024 ps
T1287 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1158508557 Apr 23 02:45:30 PM PDT 24 Apr 23 02:45:31 PM PDT 24 122188522 ps
T1288 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4234417233 Apr 23 02:45:52 PM PDT 24 Apr 23 02:45:54 PM PDT 24 695853224 ps
T1289 /workspace/coverage/cover_reg_top/2.uart_intr_test.3987650595 Apr 23 02:45:34 PM PDT 24 Apr 23 02:45:35 PM PDT 24 32795892 ps
T1290 /workspace/coverage/cover_reg_top/23.uart_intr_test.1910132826 Apr 23 02:46:05 PM PDT 24 Apr 23 02:46:06 PM PDT 24 21349908 ps
T1291 /workspace/coverage/cover_reg_top/3.uart_intr_test.3132978342 Apr 23 02:45:41 PM PDT 24 Apr 23 02:45:42 PM PDT 24 15684779 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1216166971 Apr 23 02:45:45 PM PDT 24 Apr 23 02:45:47 PM PDT 24 24208090 ps
T68 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1238991617 Apr 23 02:45:55 PM PDT 24 Apr 23 02:45:56 PM PDT 24 34174596 ps
T1293 /workspace/coverage/cover_reg_top/44.uart_intr_test.435423320 Apr 23 02:46:08 PM PDT 24 Apr 23 02:46:10 PM PDT 24 15794905 ps
T1294 /workspace/coverage/cover_reg_top/49.uart_intr_test.2292033896 Apr 23 02:46:09 PM PDT 24 Apr 23 02:46:11 PM PDT 24 15764098 ps
T1295 /workspace/coverage/cover_reg_top/14.uart_tl_errors.725954193 Apr 23 02:45:56 PM PDT 24 Apr 23 02:45:58 PM PDT 24 198302403 ps
T1296 /workspace/coverage/cover_reg_top/7.uart_intr_test.3470172181 Apr 23 02:45:42 PM PDT 24 Apr 23 02:45:43 PM PDT 24 14784098 ps
T102 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2903465635 Apr 23 02:45:53 PM PDT 24 Apr 23 02:45:55 PM PDT 24 187783402 ps
T1297 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3205361488 Apr 23 02:45:48 PM PDT 24 Apr 23 02:45:49 PM PDT 24 89056144 ps
T1298 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1057997567 Apr 23 02:45:46 PM PDT 24 Apr 23 02:45:48 PM PDT 24 317818437 ps
T1299 /workspace/coverage/cover_reg_top/42.uart_intr_test.1646364873 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:13 PM PDT 24 49932041 ps
T1300 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2230231778 Apr 23 02:45:39 PM PDT 24 Apr 23 02:45:40 PM PDT 24 20025284 ps
T1301 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2655835365 Apr 23 02:45:53 PM PDT 24 Apr 23 02:45:55 PM PDT 24 51917066 ps
T1302 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3341930706 Apr 23 02:45:29 PM PDT 24 Apr 23 02:45:30 PM PDT 24 28160521 ps
T1303 /workspace/coverage/cover_reg_top/41.uart_intr_test.2163672786 Apr 23 02:46:08 PM PDT 24 Apr 23 02:46:09 PM PDT 24 70397736 ps
T1304 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1422377948 Apr 23 02:45:58 PM PDT 24 Apr 23 02:46:01 PM PDT 24 498745914 ps
T1305 /workspace/coverage/cover_reg_top/16.uart_intr_test.3128932341 Apr 23 02:45:56 PM PDT 24 Apr 23 02:45:57 PM PDT 24 39486456 ps
T1306 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3297233315 Apr 23 02:45:49 PM PDT 24 Apr 23 02:45:51 PM PDT 24 42687924 ps
T1307 /workspace/coverage/cover_reg_top/15.uart_tl_errors.247021669 Apr 23 02:45:59 PM PDT 24 Apr 23 02:46:01 PM PDT 24 157300454 ps
T1308 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3366925349 Apr 23 02:45:38 PM PDT 24 Apr 23 02:45:39 PM PDT 24 48686879 ps
T1309 /workspace/coverage/cover_reg_top/21.uart_intr_test.3769847823 Apr 23 02:46:04 PM PDT 24 Apr 23 02:46:05 PM PDT 24 28845697 ps
T1310 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1646470330 Apr 23 02:46:03 PM PDT 24 Apr 23 02:46:04 PM PDT 24 95489288 ps
T69 /workspace/coverage/cover_reg_top/18.uart_csr_rw.64992277 Apr 23 02:46:00 PM PDT 24 Apr 23 02:46:01 PM PDT 24 41648428 ps
T1311 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4081389702 Apr 23 02:45:44 PM PDT 24 Apr 23 02:45:46 PM PDT 24 84177391 ps
T70 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1841114527 Apr 23 02:45:40 PM PDT 24 Apr 23 02:45:41 PM PDT 24 14219751 ps
T1312 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.949674695 Apr 23 02:46:04 PM PDT 24 Apr 23 02:46:06 PM PDT 24 19500474 ps
T1313 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.198158357 Apr 23 02:45:29 PM PDT 24 Apr 23 02:45:30 PM PDT 24 97901461 ps
T1314 /workspace/coverage/cover_reg_top/6.uart_intr_test.2329991175 Apr 23 02:45:38 PM PDT 24 Apr 23 02:45:39 PM PDT 24 16488123 ps
T1315 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4290549602 Apr 23 02:45:37 PM PDT 24 Apr 23 02:45:39 PM PDT 24 271215878 ps
T1316 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2760348076 Apr 23 02:45:43 PM PDT 24 Apr 23 02:45:44 PM PDT 24 18442864 ps
T1317 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3475845885 Apr 23 02:45:36 PM PDT 24 Apr 23 02:45:37 PM PDT 24 90996713 ps

Test location /workspace/coverage/default/44.uart_stress_all.2607372146
Short name T4
Test name
Test status
Simulation time 720105776974 ps
CPU time 292.94 seconds
Started Apr 23 02:02:37 PM PDT 24
Finished Apr 23 02:07:30 PM PDT 24
Peak memory 216448 kb
Host smart-815a7d59-cf95-41d8-9532-48bd020516b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607372146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2607372146
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3072164841
Short name T14
Test name
Test status
Simulation time 79490897791 ps
CPU time 394.46 seconds
Started Apr 23 02:03:34 PM PDT 24
Finished Apr 23 02:10:09 PM PDT 24
Peak memory 217220 kb
Host smart-31b21aeb-c2e5-42d9-8e10-9bb5cdd52273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072164841 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3072164841
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.714357422
Short name T15
Test name
Test status
Simulation time 138237370102 ps
CPU time 1041.15 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 02:15:57 PM PDT 24
Peak memory 217124 kb
Host smart-81515077-430e-4513-95a9-688847f9701f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714357422 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.714357422
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3398543714
Short name T267
Test name
Test status
Simulation time 108144525433 ps
CPU time 431.77 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 02:05:38 PM PDT 24
Peak memory 200744 kb
Host smart-1f7b3eea-d42c-4f19-bd5a-f246f520f80a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398543714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3398543714
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1469338553
Short name T20
Test name
Test status
Simulation time 150565816767 ps
CPU time 1071.92 seconds
Started Apr 23 02:03:20 PM PDT 24
Finished Apr 23 02:21:13 PM PDT 24
Peak memory 226784 kb
Host smart-118109f4-ea20-447a-9a36-a2f9ee89b17c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469338553 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1469338553
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.1606821975
Short name T159
Test name
Test status
Simulation time 660279457874 ps
CPU time 395 seconds
Started Apr 23 02:02:46 PM PDT 24
Finished Apr 23 02:09:22 PM PDT 24
Peak memory 200780 kb
Host smart-bd274095-f84c-42c2-932b-33346df4d178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606821975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1606821975
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.718926005
Short name T30
Test name
Test status
Simulation time 378298041769 ps
CPU time 586.32 seconds
Started Apr 23 01:59:36 PM PDT 24
Finished Apr 23 02:09:22 PM PDT 24
Peak memory 217388 kb
Host smart-7979402e-1e35-4054-b792-9e0e40b74323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718926005 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.718926005
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3619356974
Short name T23
Test name
Test status
Simulation time 33951560 ps
CPU time 0.76 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 01:58:26 PM PDT 24
Peak memory 218868 kb
Host smart-586641fd-b05f-4683-b72f-ab80e6a3f838
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619356974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3619356974
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3511935105
Short name T126
Test name
Test status
Simulation time 509348478425 ps
CPU time 716.83 seconds
Started Apr 23 02:01:39 PM PDT 24
Finished Apr 23 02:13:37 PM PDT 24
Peak memory 225824 kb
Host smart-fe7fb3eb-43ae-4a25-87cb-b174533b2dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511935105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3511935105
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3187466675
Short name T12
Test name
Test status
Simulation time 191436552602 ps
CPU time 81.61 seconds
Started Apr 23 02:01:07 PM PDT 24
Finished Apr 23 02:02:29 PM PDT 24
Peak memory 200736 kb
Host smart-f6e1bbfe-bccb-4b8a-ab09-b2d587ab5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187466675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3187466675
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3005060317
Short name T140
Test name
Test status
Simulation time 189407793669 ps
CPU time 156.77 seconds
Started Apr 23 02:05:45 PM PDT 24
Finished Apr 23 02:08:22 PM PDT 24
Peak memory 200860 kb
Host smart-d757e5bd-ee45-4393-ae28-4dc84bbb28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005060317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3005060317
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.1597058355
Short name T147
Test name
Test status
Simulation time 309329487235 ps
CPU time 128.15 seconds
Started Apr 23 01:58:24 PM PDT 24
Finished Apr 23 02:00:33 PM PDT 24
Peak memory 200916 kb
Host smart-957fa981-4293-443c-8be0-fe8af3e7ddb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597058355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1597058355
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1674958548
Short name T54
Test name
Test status
Simulation time 68759509869 ps
CPU time 239.53 seconds
Started Apr 23 02:03:38 PM PDT 24
Finished Apr 23 02:07:38 PM PDT 24
Peak memory 216664 kb
Host smart-49caceaf-45b7-4aa3-8075-e3631e6aeb3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674958548 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1674958548
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.1288037610
Short name T138
Test name
Test status
Simulation time 126724968994 ps
CPU time 188.27 seconds
Started Apr 23 02:02:15 PM PDT 24
Finished Apr 23 02:05:24 PM PDT 24
Peak memory 200728 kb
Host smart-ef17e0e3-c2e9-4c97-bcdb-dd4847ae8b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288037610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1288037610
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2267497913
Short name T142
Test name
Test status
Simulation time 104469471216 ps
CPU time 580.21 seconds
Started Apr 23 01:58:15 PM PDT 24
Finished Apr 23 02:07:56 PM PDT 24
Peak memory 200700 kb
Host smart-87766a9d-e219-4895-a682-752ae771b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267497913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2267497913
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.84503220
Short name T130
Test name
Test status
Simulation time 532478983900 ps
CPU time 114.05 seconds
Started Apr 23 01:59:54 PM PDT 24
Finished Apr 23 02:01:48 PM PDT 24
Peak memory 200896 kb
Host smart-2d07e3c1-ff57-46fe-8a56-891672a139c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84503220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.84503220
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_noise_filter.794471333
Short name T8
Test name
Test status
Simulation time 90602274680 ps
CPU time 53.5 seconds
Started Apr 23 01:59:18 PM PDT 24
Finished Apr 23 02:00:12 PM PDT 24
Peak memory 200572 kb
Host smart-b57f88a2-ea04-4e18-9701-7f710a5ea5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794471333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.794471333
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2949112689
Short name T29
Test name
Test status
Simulation time 144321905603 ps
CPU time 1377.3 seconds
Started Apr 23 02:00:10 PM PDT 24
Finished Apr 23 02:23:08 PM PDT 24
Peak memory 225736 kb
Host smart-93ce900d-f324-4da4-bf42-7a97bf37d0f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949112689 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2949112689
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2429929644
Short name T98
Test name
Test status
Simulation time 195500101 ps
CPU time 0.98 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 199304 kb
Host smart-7040f243-4124-4a9e-86bc-08ef4991c96a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429929644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2429929644
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.840189470
Short name T356
Test name
Test status
Simulation time 14579541 ps
CPU time 0.57 seconds
Started Apr 23 01:58:11 PM PDT 24
Finished Apr 23 01:58:12 PM PDT 24
Peak memory 196144 kb
Host smart-4ae483f0-62ed-4dc2-8fba-bb3d301cf731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840189470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.840189470
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2951774514
Short name T164
Test name
Test status
Simulation time 54825239119 ps
CPU time 45.92 seconds
Started Apr 23 02:06:30 PM PDT 24
Finished Apr 23 02:07:16 PM PDT 24
Peak memory 200908 kb
Host smart-c2fdfaeb-c544-4898-8a01-2466393ec63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951774514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2951774514
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2706084006
Short name T65
Test name
Test status
Simulation time 31281246 ps
CPU time 0.82 seconds
Started Apr 23 02:45:33 PM PDT 24
Finished Apr 23 02:45:34 PM PDT 24
Peak memory 196444 kb
Host smart-9fe76b95-d3c1-459f-a1a5-e19f62a7934b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706084006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2706084006
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2232673840
Short name T35
Test name
Test status
Simulation time 146894269283 ps
CPU time 2185.47 seconds
Started Apr 23 02:04:00 PM PDT 24
Finished Apr 23 02:40:26 PM PDT 24
Peak memory 225480 kb
Host smart-a41f2f57-57e8-4c0c-99ba-43a4bfb89741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232673840 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2232673840
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.2368355451
Short name T320
Test name
Test status
Simulation time 366668018314 ps
CPU time 912.7 seconds
Started Apr 23 02:02:20 PM PDT 24
Finished Apr 23 02:17:33 PM PDT 24
Peak memory 209288 kb
Host smart-6d0685a5-176e-40c6-9e38-db513e07e56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368355451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2368355451
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1947363460
Short name T315
Test name
Test status
Simulation time 106701915072 ps
CPU time 172.42 seconds
Started Apr 23 01:58:40 PM PDT 24
Finished Apr 23 02:01:33 PM PDT 24
Peak memory 200752 kb
Host smart-59540d95-7036-4cd8-a4c6-bec68b573ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947363460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1947363460
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3274171199
Short name T87
Test name
Test status
Simulation time 45664655 ps
CPU time 0.68 seconds
Started Apr 23 02:45:33 PM PDT 24
Finished Apr 23 02:45:34 PM PDT 24
Peak memory 194744 kb
Host smart-77cd540a-9698-44e5-94ad-1ddda868180e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274171199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3274171199
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2903465635
Short name T102
Test name
Test status
Simulation time 187783402 ps
CPU time 1.36 seconds
Started Apr 23 02:45:53 PM PDT 24
Finished Apr 23 02:45:55 PM PDT 24
Peak memory 199368 kb
Host smart-ce02b387-19d2-4274-b3c1-937a3f4ae627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903465635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2903465635
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.745594615
Short name T191
Test name
Test status
Simulation time 278354531875 ps
CPU time 125.87 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 02:00:42 PM PDT 24
Peak memory 200860 kb
Host smart-a3f08cf6-492f-4af1-abbd-0bd603fd513a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745594615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.745594615
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2907617136
Short name T157
Test name
Test status
Simulation time 16869138369 ps
CPU time 29.81 seconds
Started Apr 23 02:04:32 PM PDT 24
Finished Apr 23 02:05:02 PM PDT 24
Peak memory 200780 kb
Host smart-b14868ea-6513-46be-86e1-128db7617aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907617136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2907617136
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3696630252
Short name T165
Test name
Test status
Simulation time 93481328295 ps
CPU time 71.12 seconds
Started Apr 23 02:06:02 PM PDT 24
Finished Apr 23 02:07:13 PM PDT 24
Peak memory 200844 kb
Host smart-328172b3-0eef-4e54-8ac1-047698fcb390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696630252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3696630252
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1623609843
Short name T128
Test name
Test status
Simulation time 232528434117 ps
CPU time 1220.97 seconds
Started Apr 23 02:03:53 PM PDT 24
Finished Apr 23 02:24:14 PM PDT 24
Peak memory 230952 kb
Host smart-dd063a52-d381-4c39-ae16-ef2d10d1a363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623609843 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1623609843
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3757922421
Short name T273
Test name
Test status
Simulation time 188970398856 ps
CPU time 173.05 seconds
Started Apr 23 01:58:52 PM PDT 24
Finished Apr 23 02:01:46 PM PDT 24
Peak memory 209236 kb
Host smart-250ca296-1516-4858-8123-98fed8c3eb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757922421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3757922421
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2020605716
Short name T50
Test name
Test status
Simulation time 23872728010 ps
CPU time 39.29 seconds
Started Apr 23 02:05:12 PM PDT 24
Finished Apr 23 02:05:52 PM PDT 24
Peak memory 200880 kb
Host smart-0bd4ecfd-e697-4fb5-8c3d-644840a1d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020605716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2020605716
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2406927456
Short name T168
Test name
Test status
Simulation time 40152560776 ps
CPU time 36.26 seconds
Started Apr 23 02:05:36 PM PDT 24
Finished Apr 23 02:06:12 PM PDT 24
Peak memory 200888 kb
Host smart-085e8bd0-65ea-4615-8f10-6b78d21d463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406927456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2406927456
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2406415603
Short name T149
Test name
Test status
Simulation time 187100484354 ps
CPU time 63.56 seconds
Started Apr 23 02:01:23 PM PDT 24
Finished Apr 23 02:02:27 PM PDT 24
Peak memory 200664 kb
Host smart-f23a4864-5c05-43e4-9aac-ceee2ab9f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406415603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2406415603
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1845533204
Short name T154
Test name
Test status
Simulation time 160634560943 ps
CPU time 23.37 seconds
Started Apr 23 02:03:27 PM PDT 24
Finished Apr 23 02:03:51 PM PDT 24
Peak memory 200784 kb
Host smart-4fe6f2d1-5fcd-4461-bcc1-0bb25e9f130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845533204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1845533204
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.977539101
Short name T131
Test name
Test status
Simulation time 39289278881 ps
CPU time 17.78 seconds
Started Apr 23 02:01:52 PM PDT 24
Finished Apr 23 02:02:10 PM PDT 24
Peak memory 200848 kb
Host smart-35a04d5a-48df-4c73-a7a6-69ac24943418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977539101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.977539101
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1465351410
Short name T176
Test name
Test status
Simulation time 43136211343 ps
CPU time 39.67 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 01:59:09 PM PDT 24
Peak memory 200872 kb
Host smart-ba5c93e8-dff9-4379-8983-0dd2246f0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465351410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1465351410
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1816099904
Short name T96
Test name
Test status
Simulation time 156677113 ps
CPU time 1.28 seconds
Started Apr 23 02:45:31 PM PDT 24
Finished Apr 23 02:45:33 PM PDT 24
Peak memory 199348 kb
Host smart-3c2f5730-c159-47d5-9a81-1520b00215d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816099904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1816099904
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1070310189
Short name T230
Test name
Test status
Simulation time 41274609261 ps
CPU time 62.32 seconds
Started Apr 23 02:04:59 PM PDT 24
Finished Apr 23 02:06:02 PM PDT 24
Peak memory 200808 kb
Host smart-29ab402b-f71f-480b-9f22-09a1b648cefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070310189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1070310189
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4243660920
Short name T197
Test name
Test status
Simulation time 246929323433 ps
CPU time 55.08 seconds
Started Apr 23 02:06:37 PM PDT 24
Finished Apr 23 02:07:33 PM PDT 24
Peak memory 200884 kb
Host smart-001c3b17-09fe-4e65-b2a2-4457ad66e903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243660920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4243660920
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_perf.3454429602
Short name T297
Test name
Test status
Simulation time 26461124292 ps
CPU time 1141.05 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 02:17:32 PM PDT 24
Peak memory 200904 kb
Host smart-93fde629-7599-4546-98fe-86bb58533a5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454429602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3454429602
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1031574949
Short name T233
Test name
Test status
Simulation time 74606236375 ps
CPU time 119.62 seconds
Started Apr 23 02:05:24 PM PDT 24
Finished Apr 23 02:07:24 PM PDT 24
Peak memory 200844 kb
Host smart-df33d0cd-67a8-4038-b82e-d017f73266bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031574949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1031574949
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1945790042
Short name T278
Test name
Test status
Simulation time 70850689378 ps
CPU time 113.78 seconds
Started Apr 23 02:05:27 PM PDT 24
Finished Apr 23 02:07:21 PM PDT 24
Peak memory 200804 kb
Host smart-7bf269c7-1ade-4aa0-bfb4-daa286c965ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945790042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1945790042
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1469608874
Short name T170
Test name
Test status
Simulation time 30759539341 ps
CPU time 15.81 seconds
Started Apr 23 02:06:20 PM PDT 24
Finished Apr 23 02:06:37 PM PDT 24
Peak memory 200872 kb
Host smart-e3dbbd57-597b-4dbe-b94a-15f28269968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469608874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1469608874
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2104155842
Short name T175
Test name
Test status
Simulation time 49782193861 ps
CPU time 54.49 seconds
Started Apr 23 02:05:15 PM PDT 24
Finished Apr 23 02:06:10 PM PDT 24
Peak memory 200872 kb
Host smart-cf8f1749-b299-4581-bc62-12c9118d0964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104155842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2104155842
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.4039209392
Short name T258
Test name
Test status
Simulation time 212768398705 ps
CPU time 80.06 seconds
Started Apr 23 02:05:47 PM PDT 24
Finished Apr 23 02:07:07 PM PDT 24
Peak memory 200860 kb
Host smart-ab81d73c-a888-4485-af84-f46c29a7d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039209392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4039209392
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3608415964
Short name T188
Test name
Test status
Simulation time 150768081321 ps
CPU time 181.09 seconds
Started Apr 23 02:05:48 PM PDT 24
Finished Apr 23 02:08:50 PM PDT 24
Peak memory 200880 kb
Host smart-aa41531b-6838-4d92-8823-4dfaaf56a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608415964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3608415964
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1057023664
Short name T665
Test name
Test status
Simulation time 102897608400 ps
CPU time 202.18 seconds
Started Apr 23 02:03:25 PM PDT 24
Finished Apr 23 02:06:48 PM PDT 24
Peak memory 200792 kb
Host smart-dcae0f63-a634-4938-b6c4-0f29232cb8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057023664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1057023664
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1371724817
Short name T55
Test name
Test status
Simulation time 64767189643 ps
CPU time 618.1 seconds
Started Apr 23 01:58:45 PM PDT 24
Finished Apr 23 02:09:04 PM PDT 24
Peak memory 223688 kb
Host smart-f7757bb1-85c3-49cd-931e-55b83b9b5d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371724817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1371724817
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1674196409
Short name T161
Test name
Test status
Simulation time 35413976520 ps
CPU time 21.36 seconds
Started Apr 23 02:04:46 PM PDT 24
Finished Apr 23 02:05:08 PM PDT 24
Peak memory 200896 kb
Host smart-7828fd71-96bc-4dde-a225-7715f1dd17d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674196409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1674196409
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.2419867621
Short name T225
Test name
Test status
Simulation time 83721980778 ps
CPU time 121.96 seconds
Started Apr 23 01:59:01 PM PDT 24
Finished Apr 23 02:01:04 PM PDT 24
Peak memory 200780 kb
Host smart-c16bf5c3-f02a-42f2-bd47-e4ad03137cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419867621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2419867621
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2867401931
Short name T156
Test name
Test status
Simulation time 168285158088 ps
CPU time 130.05 seconds
Started Apr 23 02:05:13 PM PDT 24
Finished Apr 23 02:07:24 PM PDT 24
Peak memory 200864 kb
Host smart-b1f8f632-6fe3-4ee1-8e9b-7367c60edf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867401931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2867401931
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2502343012
Short name T246
Test name
Test status
Simulation time 28464114724 ps
CPU time 50.44 seconds
Started Apr 23 02:05:24 PM PDT 24
Finished Apr 23 02:06:15 PM PDT 24
Peak memory 200892 kb
Host smart-30c706e2-b1fc-4c56-be40-6b1220caf9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502343012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2502343012
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2375502744
Short name T143
Test name
Test status
Simulation time 239994605051 ps
CPU time 23.46 seconds
Started Apr 23 02:06:02 PM PDT 24
Finished Apr 23 02:06:26 PM PDT 24
Peak memory 200912 kb
Host smart-582b8a23-426f-4d2a-8464-588afde7a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375502744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2375502744
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1711330231
Short name T171
Test name
Test status
Simulation time 24313728835 ps
CPU time 13.87 seconds
Started Apr 23 01:58:34 PM PDT 24
Finished Apr 23 01:58:49 PM PDT 24
Peak memory 200800 kb
Host smart-5a4742cc-8fcc-4088-b859-0e0cbec289d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711330231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1711330231
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2299131308
Short name T235
Test name
Test status
Simulation time 47210319510 ps
CPU time 38.69 seconds
Started Apr 23 02:04:07 PM PDT 24
Finished Apr 23 02:04:48 PM PDT 24
Peak memory 200808 kb
Host smart-33b55747-976c-4c74-98e2-87ebfe456c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299131308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2299131308
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.2984777413
Short name T210
Test name
Test status
Simulation time 243529356020 ps
CPU time 369.34 seconds
Started Apr 23 01:58:13 PM PDT 24
Finished Apr 23 02:04:23 PM PDT 24
Peak memory 201144 kb
Host smart-401c4e1a-6b79-4143-b288-71d313424877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984777413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2984777413
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3427399258
Short name T337
Test name
Test status
Simulation time 23488589580 ps
CPU time 41.88 seconds
Started Apr 23 01:58:11 PM PDT 24
Finished Apr 23 01:58:53 PM PDT 24
Peak memory 200752 kb
Host smart-89a7cb93-3de5-4177-9c85-976fd1323180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427399258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3427399258
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3066097820
Short name T78
Test name
Test status
Simulation time 110483335661 ps
CPU time 15.56 seconds
Started Apr 23 02:04:18 PM PDT 24
Finished Apr 23 02:04:34 PM PDT 24
Peak memory 200400 kb
Host smart-efff84c2-b6bd-4251-ad88-d07956984ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066097820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3066097820
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4133490039
Short name T1070
Test name
Test status
Simulation time 274744373707 ps
CPU time 99.84 seconds
Started Apr 23 02:04:30 PM PDT 24
Finished Apr 23 02:06:10 PM PDT 24
Peak memory 200788 kb
Host smart-fb1808fa-30bd-42f8-a32a-92b51850a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133490039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4133490039
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3082106606
Short name T152
Test name
Test status
Simulation time 16328497163 ps
CPU time 27.7 seconds
Started Apr 23 02:04:36 PM PDT 24
Finished Apr 23 02:05:04 PM PDT 24
Peak memory 200804 kb
Host smart-ad5a4b7c-bcde-4ce0-8d5f-859c6a0a9920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082106606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3082106606
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1327460226
Short name T205
Test name
Test status
Simulation time 111407444265 ps
CPU time 235.06 seconds
Started Apr 23 02:04:44 PM PDT 24
Finished Apr 23 02:08:39 PM PDT 24
Peak memory 200720 kb
Host smart-44c81c14-79d9-4610-b1d7-69bdf6c29ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327460226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1327460226
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1117713534
Short name T215
Test name
Test status
Simulation time 76142813703 ps
CPU time 64.16 seconds
Started Apr 23 02:04:48 PM PDT 24
Finished Apr 23 02:05:52 PM PDT 24
Peak memory 200848 kb
Host smart-7fb9a429-6f73-4f72-b592-a5eeee36d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117713534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1117713534
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3954124966
Short name T229
Test name
Test status
Simulation time 73507455419 ps
CPU time 199.87 seconds
Started Apr 23 01:59:00 PM PDT 24
Finished Apr 23 02:02:20 PM PDT 24
Peak memory 200924 kb
Host smart-daf753fd-d75d-4131-8df1-c0cb86e17868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954124966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3954124966
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.107855253
Short name T148
Test name
Test status
Simulation time 45251849540 ps
CPU time 20.16 seconds
Started Apr 23 02:05:15 PM PDT 24
Finished Apr 23 02:05:36 PM PDT 24
Peak memory 200808 kb
Host smart-e2bcb0f2-da43-4d33-be1d-31ab25647bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107855253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.107855253
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3249260599
Short name T241
Test name
Test status
Simulation time 23758310913 ps
CPU time 47.28 seconds
Started Apr 23 02:05:17 PM PDT 24
Finished Apr 23 02:06:05 PM PDT 24
Peak memory 200808 kb
Host smart-0061eac8-e3f6-47a7-abb0-c68acf343866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249260599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3249260599
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2808336587
Short name T158
Test name
Test status
Simulation time 90468641835 ps
CPU time 29.31 seconds
Started Apr 23 02:05:43 PM PDT 24
Finished Apr 23 02:06:13 PM PDT 24
Peak memory 200812 kb
Host smart-dd44da2e-c1b9-4d71-a3a6-ccaf24c71d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808336587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2808336587
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.732887947
Short name T182
Test name
Test status
Simulation time 126447428652 ps
CPU time 228.7 seconds
Started Apr 23 02:06:35 PM PDT 24
Finished Apr 23 02:10:25 PM PDT 24
Peak memory 200844 kb
Host smart-6991223e-9c59-456a-9a3e-86949df4c586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732887947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.732887947
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.691630805
Short name T248
Test name
Test status
Simulation time 97856221375 ps
CPU time 133.88 seconds
Started Apr 23 02:06:44 PM PDT 24
Finished Apr 23 02:08:59 PM PDT 24
Peak memory 200864 kb
Host smart-ca0d7302-dbbb-4363-9030-c459c601ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691630805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.691630805
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1733975796
Short name T187
Test name
Test status
Simulation time 98228287440 ps
CPU time 65.72 seconds
Started Apr 23 02:00:34 PM PDT 24
Finished Apr 23 02:01:40 PM PDT 24
Peak memory 200884 kb
Host smart-cea33cb2-e97a-494d-b795-cfeac891debf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733975796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1733975796
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all.3002121411
Short name T259
Test name
Test status
Simulation time 217202560730 ps
CPU time 471.03 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 02:06:20 PM PDT 24
Peak memory 200852 kb
Host smart-7703d792-875c-4ca8-8ce7-2942edfc559b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002121411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3002121411
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2895334232
Short name T240
Test name
Test status
Simulation time 32609727881 ps
CPU time 69.05 seconds
Started Apr 23 02:03:26 PM PDT 24
Finished Apr 23 02:04:35 PM PDT 24
Peak memory 200808 kb
Host smart-344338f6-a561-4660-9a57-66c5e99f0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895334232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2895334232
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1441333242
Short name T252
Test name
Test status
Simulation time 184814129715 ps
CPU time 87.98 seconds
Started Apr 23 02:03:42 PM PDT 24
Finished Apr 23 02:05:11 PM PDT 24
Peak memory 200832 kb
Host smart-b3f9b494-de2e-40bd-a2f1-8481957d8d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441333242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1441333242
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2478238967
Short name T254
Test name
Test status
Simulation time 92247727005 ps
CPU time 46.86 seconds
Started Apr 23 02:03:57 PM PDT 24
Finished Apr 23 02:04:45 PM PDT 24
Peak memory 200748 kb
Host smart-d9d33c21-8a87-4220-b9ce-95b4fa3d4f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478238967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2478238967
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1876439142
Short name T1229
Test name
Test status
Simulation time 65241498 ps
CPU time 0.64 seconds
Started Apr 23 02:45:31 PM PDT 24
Finished Apr 23 02:45:32 PM PDT 24
Peak memory 194888 kb
Host smart-17675f4a-8e4f-402d-8b3a-94d9c6a0de7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876439142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1876439142
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1046141745
Short name T1245
Test name
Test status
Simulation time 177388990 ps
CPU time 2.45 seconds
Started Apr 23 02:45:33 PM PDT 24
Finished Apr 23 02:45:36 PM PDT 24
Peak memory 197772 kb
Host smart-75d00854-1eac-40eb-880c-d7d950bfe23d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046141745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1046141745
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1158508557
Short name T1287
Test name
Test status
Simulation time 122188522 ps
CPU time 0.57 seconds
Started Apr 23 02:45:30 PM PDT 24
Finished Apr 23 02:45:31 PM PDT 24
Peak memory 195468 kb
Host smart-83866c42-0434-4c49-b97c-41ce87938aec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158508557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1158508557
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.608467826
Short name T1233
Test name
Test status
Simulation time 24377695 ps
CPU time 1.24 seconds
Started Apr 23 02:45:30 PM PDT 24
Finished Apr 23 02:45:31 PM PDT 24
Peak memory 200100 kb
Host smart-07f82e70-d3bc-43c1-a5aa-f0776d084410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608467826 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.608467826
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3341930706
Short name T1302
Test name
Test status
Simulation time 28160521 ps
CPU time 0.6 seconds
Started Apr 23 02:45:29 PM PDT 24
Finished Apr 23 02:45:30 PM PDT 24
Peak memory 195480 kb
Host smart-c4a2403e-4ee7-4fa9-8711-e9092c0fb8a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341930706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3341930706
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.927386576
Short name T1246
Test name
Test status
Simulation time 132956356 ps
CPU time 0.57 seconds
Started Apr 23 02:45:29 PM PDT 24
Finished Apr 23 02:45:30 PM PDT 24
Peak memory 194456 kb
Host smart-8ecd6192-ed30-49c0-baf1-37219d8f4141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927386576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.927386576
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.198158357
Short name T1313
Test name
Test status
Simulation time 97901461 ps
CPU time 0.76 seconds
Started Apr 23 02:45:29 PM PDT 24
Finished Apr 23 02:45:30 PM PDT 24
Peak memory 197288 kb
Host smart-101b910d-0076-4928-9ec3-9af6c87ae757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198158357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.198158357
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2067244161
Short name T1210
Test name
Test status
Simulation time 129232168 ps
CPU time 2.33 seconds
Started Apr 23 02:45:31 PM PDT 24
Finished Apr 23 02:45:33 PM PDT 24
Peak memory 200108 kb
Host smart-ee8cdcd3-0886-4b95-824a-74efe1866fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067244161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2067244161
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.729147655
Short name T1200
Test name
Test status
Simulation time 19157244 ps
CPU time 0.8 seconds
Started Apr 23 02:45:29 PM PDT 24
Finished Apr 23 02:45:30 PM PDT 24
Peak memory 196620 kb
Host smart-b34b2d9e-e5ab-45e8-84ee-f5438eab1c5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729147655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.729147655
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2488981054
Short name T1197
Test name
Test status
Simulation time 137243199 ps
CPU time 2.22 seconds
Started Apr 23 02:45:31 PM PDT 24
Finished Apr 23 02:45:33 PM PDT 24
Peak memory 197756 kb
Host smart-5e4cefd5-110c-4b7d-9712-8358e70e2fd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488981054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2488981054
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1046819136
Short name T1187
Test name
Test status
Simulation time 65503209 ps
CPU time 0.59 seconds
Started Apr 23 02:45:31 PM PDT 24
Finished Apr 23 02:45:32 PM PDT 24
Peak memory 195448 kb
Host smart-368be0c5-0bb9-4cd7-8de5-e47f4e646ae3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046819136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1046819136
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1700604306
Short name T1282
Test name
Test status
Simulation time 105976752 ps
CPU time 0.78 seconds
Started Apr 23 02:45:36 PM PDT 24
Finished Apr 23 02:45:37 PM PDT 24
Peak memory 198448 kb
Host smart-2c02e54d-9e4e-4e82-9b10-7bde46673ea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700604306 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1700604306
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3925779161
Short name T1248
Test name
Test status
Simulation time 26530564 ps
CPU time 0.61 seconds
Started Apr 23 02:45:30 PM PDT 24
Finished Apr 23 02:45:31 PM PDT 24
Peak memory 195400 kb
Host smart-174fe50a-5fb4-49f1-b2f3-7f8c9bbc2676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925779161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3925779161
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2241629681
Short name T1227
Test name
Test status
Simulation time 38734825 ps
CPU time 0.55 seconds
Started Apr 23 02:45:33 PM PDT 24
Finished Apr 23 02:45:34 PM PDT 24
Peak memory 194432 kb
Host smart-b2ab1dd2-f569-48a4-924d-a4aab81815f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241629681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2241629681
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1452282770
Short name T1264
Test name
Test status
Simulation time 267059041 ps
CPU time 1.39 seconds
Started Apr 23 02:45:29 PM PDT 24
Finished Apr 23 02:45:31 PM PDT 24
Peak memory 200052 kb
Host smart-a4d2234d-76ac-491d-afd4-f1e82de16561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452282770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1452282770
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3895216071
Short name T100
Test name
Test status
Simulation time 107436852 ps
CPU time 1.24 seconds
Started Apr 23 02:45:28 PM PDT 24
Finished Apr 23 02:45:30 PM PDT 24
Peak memory 199424 kb
Host smart-1e6b20a0-0ec8-4466-ba3e-34b77e15808f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895216071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3895216071
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3914016361
Short name T1247
Test name
Test status
Simulation time 25721911 ps
CPU time 1.09 seconds
Started Apr 23 02:45:48 PM PDT 24
Finished Apr 23 02:45:49 PM PDT 24
Peak memory 200156 kb
Host smart-c9d870fc-8d4e-48a8-85ff-fb55477e4e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914016361 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3914016361
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3458597268
Short name T81
Test name
Test status
Simulation time 17049391 ps
CPU time 0.59 seconds
Started Apr 23 02:45:48 PM PDT 24
Finished Apr 23 02:45:49 PM PDT 24
Peak memory 195516 kb
Host smart-112f7095-35fe-4aa5-8c6a-f6b8bda1680c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458597268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3458597268
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2445127470
Short name T1267
Test name
Test status
Simulation time 17659661 ps
CPU time 0.58 seconds
Started Apr 23 02:45:48 PM PDT 24
Finished Apr 23 02:45:49 PM PDT 24
Peak memory 194432 kb
Host smart-a588ff57-0955-453b-8c62-d3a630d499aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445127470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2445127470
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2198764224
Short name T1279
Test name
Test status
Simulation time 132958307 ps
CPU time 0.67 seconds
Started Apr 23 02:45:49 PM PDT 24
Finished Apr 23 02:45:50 PM PDT 24
Peak memory 195700 kb
Host smart-85312d82-f126-4d0a-b25f-11a80a43f8f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198764224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2198764224
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3297233315
Short name T1306
Test name
Test status
Simulation time 42687924 ps
CPU time 1.08 seconds
Started Apr 23 02:45:49 PM PDT 24
Finished Apr 23 02:45:51 PM PDT 24
Peak memory 199832 kb
Host smart-b30fcbd3-4c04-40ea-8803-ce26443b1c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297233315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3297233315
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2891322940
Short name T101
Test name
Test status
Simulation time 95372423 ps
CPU time 0.98 seconds
Started Apr 23 02:45:50 PM PDT 24
Finished Apr 23 02:45:52 PM PDT 24
Peak memory 198932 kb
Host smart-f5f4031c-2289-40ce-a236-12908935b8ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891322940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2891322940
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3901578239
Short name T1258
Test name
Test status
Simulation time 43750659 ps
CPU time 0.77 seconds
Started Apr 23 02:45:49 PM PDT 24
Finished Apr 23 02:45:50 PM PDT 24
Peak memory 198412 kb
Host smart-52889ffd-fc2b-45f0-9589-ccd3d8eaae06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901578239 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3901578239
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3390055221
Short name T82
Test name
Test status
Simulation time 13657349 ps
CPU time 0.57 seconds
Started Apr 23 02:45:49 PM PDT 24
Finished Apr 23 02:45:50 PM PDT 24
Peak memory 195500 kb
Host smart-21afcd60-5d66-463f-97c8-31c178a1202b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390055221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3390055221
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3954191406
Short name T1208
Test name
Test status
Simulation time 12647099 ps
CPU time 0.57 seconds
Started Apr 23 02:45:49 PM PDT 24
Finished Apr 23 02:45:50 PM PDT 24
Peak memory 194356 kb
Host smart-99b0f5bf-fb67-4cb1-96de-9b470990306a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954191406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3954191406
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.596291115
Short name T1234
Test name
Test status
Simulation time 29565211 ps
CPU time 0.61 seconds
Started Apr 23 02:45:49 PM PDT 24
Finished Apr 23 02:45:50 PM PDT 24
Peak memory 195576 kb
Host smart-e01608b3-1e73-486e-9732-0fcad4777ad6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596291115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.596291115
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3046186913
Short name T1188
Test name
Test status
Simulation time 243354941 ps
CPU time 1.53 seconds
Started Apr 23 02:45:50 PM PDT 24
Finished Apr 23 02:45:53 PM PDT 24
Peak memory 200112 kb
Host smart-66234ea7-1833-4d23-80dd-8aa13c21c6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046186913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3046186913
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4234417233
Short name T1288
Test name
Test status
Simulation time 695853224 ps
CPU time 1.29 seconds
Started Apr 23 02:45:52 PM PDT 24
Finished Apr 23 02:45:54 PM PDT 24
Peak memory 199452 kb
Host smart-8627482a-6b88-4266-96f8-4020b57677bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234417233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4234417233
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2970816202
Short name T1226
Test name
Test status
Simulation time 22096851 ps
CPU time 0.64 seconds
Started Apr 23 02:45:50 PM PDT 24
Finished Apr 23 02:45:51 PM PDT 24
Peak memory 197760 kb
Host smart-50240b64-1b6b-4e34-ad60-d8df7d2b4a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970816202 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2970816202
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2899256506
Short name T1284
Test name
Test status
Simulation time 51311130 ps
CPU time 0.61 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 195404 kb
Host smart-5aa99a04-05b9-4c66-bf2d-e522432a6888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899256506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2899256506
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1773297496
Short name T1198
Test name
Test status
Simulation time 19510832 ps
CPU time 0.57 seconds
Started Apr 23 02:45:51 PM PDT 24
Finished Apr 23 02:45:52 PM PDT 24
Peak memory 194448 kb
Host smart-078b1ad7-52a3-4b9b-a12e-b8ff55b8da9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773297496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1773297496
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2554003384
Short name T1266
Test name
Test status
Simulation time 84947721 ps
CPU time 0.72 seconds
Started Apr 23 02:45:52 PM PDT 24
Finished Apr 23 02:45:53 PM PDT 24
Peak memory 197520 kb
Host smart-db7f3a14-6a24-40d4-a3af-87d9653b1707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554003384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2554003384
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3756560388
Short name T1268
Test name
Test status
Simulation time 709688105 ps
CPU time 2.05 seconds
Started Apr 23 02:45:50 PM PDT 24
Finished Apr 23 02:45:52 PM PDT 24
Peak memory 200128 kb
Host smart-3342c7d9-86a4-45ba-95da-d41b43c56fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756560388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3756560388
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2655835365
Short name T1301
Test name
Test status
Simulation time 51917066 ps
CPU time 0.97 seconds
Started Apr 23 02:45:53 PM PDT 24
Finished Apr 23 02:45:55 PM PDT 24
Peak memory 199212 kb
Host smart-8bac1a88-b0a5-40b6-9d8c-f494a77421b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655835365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2655835365
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2152730080
Short name T1191
Test name
Test status
Simulation time 100490760 ps
CPU time 1.07 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 200060 kb
Host smart-93ec31b7-56a2-4564-997b-2df7d4d7df44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152730080 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2152730080
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1964020306
Short name T1214
Test name
Test status
Simulation time 40485395 ps
CPU time 0.6 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 195484 kb
Host smart-dc40746b-4a0a-4f84-9690-544cf278aba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964020306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1964020306
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3039338348
Short name T1278
Test name
Test status
Simulation time 11273372 ps
CPU time 0.59 seconds
Started Apr 23 02:45:52 PM PDT 24
Finished Apr 23 02:45:53 PM PDT 24
Peak memory 194424 kb
Host smart-71f81388-13c9-447f-a861-a3ea5fb5a025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039338348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3039338348
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2352245997
Short name T90
Test name
Test status
Simulation time 29091267 ps
CPU time 0.78 seconds
Started Apr 23 02:45:53 PM PDT 24
Finished Apr 23 02:45:54 PM PDT 24
Peak memory 196104 kb
Host smart-bb7b6d19-4600-4c71-966f-4d2970d691db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352245997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2352245997
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1939713396
Short name T1242
Test name
Test status
Simulation time 39633406 ps
CPU time 1.99 seconds
Started Apr 23 02:45:52 PM PDT 24
Finished Apr 23 02:45:54 PM PDT 24
Peak memory 200136 kb
Host smart-8ef1e367-0b64-4bda-b97e-e76b0234f9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939713396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1939713396
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.559462914
Short name T1276
Test name
Test status
Simulation time 17404905 ps
CPU time 0.68 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 197916 kb
Host smart-b1417811-8156-4373-8227-d468b1405913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559462914 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.559462914
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1457540717
Short name T1273
Test name
Test status
Simulation time 12084844 ps
CPU time 0.58 seconds
Started Apr 23 02:45:55 PM PDT 24
Finished Apr 23 02:45:56 PM PDT 24
Peak memory 195472 kb
Host smart-7dfef417-f1e0-4c09-a4be-86c8c674d962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457540717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1457540717
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2065182742
Short name T1195
Test name
Test status
Simulation time 14647342 ps
CPU time 0.58 seconds
Started Apr 23 02:45:51 PM PDT 24
Finished Apr 23 02:45:52 PM PDT 24
Peak memory 194396 kb
Host smart-959e1b3c-b97f-4ea1-b7ee-1c54903f0055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065182742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2065182742
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1980141097
Short name T83
Test name
Test status
Simulation time 21269763 ps
CPU time 0.64 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 195572 kb
Host smart-11fa8857-2bde-4811-8fe1-344d914ce5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980141097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1980141097
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.725954193
Short name T1295
Test name
Test status
Simulation time 198302403 ps
CPU time 2.03 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 200148 kb
Host smart-ddf787f3-7634-42f9-89d1-c4a9428e61fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725954193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.725954193
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4088068054
Short name T95
Test name
Test status
Simulation time 204472695 ps
CPU time 0.99 seconds
Started Apr 23 02:45:51 PM PDT 24
Finished Apr 23 02:45:53 PM PDT 24
Peak memory 198804 kb
Host smart-9759a535-ed26-4f5f-b445-2d07ecdf1f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088068054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4088068054
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4196697578
Short name T1269
Test name
Test status
Simulation time 20792293 ps
CPU time 0.68 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 197856 kb
Host smart-d6547269-adab-4deb-9c8b-e6b310697fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196697578 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4196697578
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1929773296
Short name T1251
Test name
Test status
Simulation time 41565428 ps
CPU time 0.56 seconds
Started Apr 23 02:45:57 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 195444 kb
Host smart-1348b514-141c-4b67-b402-522f72c7fcd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929773296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1929773296
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2738115092
Short name T1249
Test name
Test status
Simulation time 14486720 ps
CPU time 0.57 seconds
Started Apr 23 02:45:57 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 194376 kb
Host smart-534ac29a-b489-4085-b976-6fa0425e2fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738115092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2738115092
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1322501099
Short name T1271
Test name
Test status
Simulation time 107371759 ps
CPU time 0.72 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 197076 kb
Host smart-93adcfee-7f14-440f-8c38-0a9bb9b64bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322501099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1322501099
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.247021669
Short name T1307
Test name
Test status
Simulation time 157300454 ps
CPU time 1.66 seconds
Started Apr 23 02:45:59 PM PDT 24
Finished Apr 23 02:46:01 PM PDT 24
Peak memory 200148 kb
Host smart-641646f7-12b8-42f8-8bd9-14369491af86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247021669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.247021669
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.104156159
Short name T1190
Test name
Test status
Simulation time 64194369 ps
CPU time 0.71 seconds
Started Apr 23 02:45:59 PM PDT 24
Finished Apr 23 02:46:00 PM PDT 24
Peak memory 198440 kb
Host smart-4052d04c-901d-4b23-89c5-3f11e47ba149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104156159 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.104156159
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1238991617
Short name T68
Test name
Test status
Simulation time 34174596 ps
CPU time 0.61 seconds
Started Apr 23 02:45:55 PM PDT 24
Finished Apr 23 02:45:56 PM PDT 24
Peak memory 195612 kb
Host smart-d08fee2e-f423-4aff-b619-900d19e4a59e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238991617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1238991617
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3128932341
Short name T1305
Test name
Test status
Simulation time 39486456 ps
CPU time 0.56 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 194364 kb
Host smart-0534bd73-0b1e-44e9-8106-d9af16ea55b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128932341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3128932341
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2557295803
Short name T85
Test name
Test status
Simulation time 24495572 ps
CPU time 0.72 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:57 PM PDT 24
Peak memory 196936 kb
Host smart-80025c29-761b-4755-8e34-b2ee459507ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557295803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2557295803
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.292968168
Short name T1204
Test name
Test status
Simulation time 46697971 ps
CPU time 1.17 seconds
Started Apr 23 02:45:57 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 199856 kb
Host smart-2a7bf6f4-5eb3-411b-806c-9bba1c528214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292968168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.292968168
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1347359236
Short name T105
Test name
Test status
Simulation time 90123844 ps
CPU time 0.91 seconds
Started Apr 23 02:45:57 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 198680 kb
Host smart-13c95cac-b9d1-451b-b3ee-8a70568ad43b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347359236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1347359236
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3681084752
Short name T1217
Test name
Test status
Simulation time 112789749 ps
CPU time 1.31 seconds
Started Apr 23 02:45:58 PM PDT 24
Finished Apr 23 02:45:59 PM PDT 24
Peak memory 200104 kb
Host smart-808d021c-6479-4bc4-afa9-d8bce03c218a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681084752 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3681084752
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2898272019
Short name T1241
Test name
Test status
Simulation time 41465240 ps
CPU time 0.59 seconds
Started Apr 23 02:45:56 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 195536 kb
Host smart-fb33fe38-75ed-424e-b6e4-23e18858ead0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898272019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2898272019
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.32283677
Short name T1219
Test name
Test status
Simulation time 42286402 ps
CPU time 0.55 seconds
Started Apr 23 02:45:57 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 194304 kb
Host smart-508a62da-2eac-42ca-996b-10cbdd629201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.32283677
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.452096581
Short name T91
Test name
Test status
Simulation time 83069810 ps
CPU time 0.66 seconds
Started Apr 23 02:45:59 PM PDT 24
Finished Apr 23 02:46:00 PM PDT 24
Peak memory 195812 kb
Host smart-0da9da68-f5f7-4ae6-a3aa-6ccf92b0e332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452096581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.452096581
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4087782147
Short name T1199
Test name
Test status
Simulation time 109472600 ps
CPU time 2.38 seconds
Started Apr 23 02:45:59 PM PDT 24
Finished Apr 23 02:46:01 PM PDT 24
Peak memory 200096 kb
Host smart-43e9df15-054f-47c2-b8d6-975c1c029d03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087782147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4087782147
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.541956905
Short name T99
Test name
Test status
Simulation time 175627648 ps
CPU time 0.9 seconds
Started Apr 23 02:45:58 PM PDT 24
Finished Apr 23 02:46:00 PM PDT 24
Peak memory 198800 kb
Host smart-773bae55-99c7-462d-98b6-35de4a855682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541956905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.541956905
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4252220343
Short name T1203
Test name
Test status
Simulation time 22875348 ps
CPU time 0.71 seconds
Started Apr 23 02:46:04 PM PDT 24
Finished Apr 23 02:46:05 PM PDT 24
Peak memory 198004 kb
Host smart-c51f2cee-f892-41f8-9670-7f94ae7f78f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252220343 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4252220343
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.64992277
Short name T69
Test name
Test status
Simulation time 41648428 ps
CPU time 0.58 seconds
Started Apr 23 02:46:00 PM PDT 24
Finished Apr 23 02:46:01 PM PDT 24
Peak memory 195480 kb
Host smart-e234e52b-680a-4457-9970-d6609b1e450d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64992277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.64992277
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.759489653
Short name T1218
Test name
Test status
Simulation time 111656239 ps
CPU time 0.59 seconds
Started Apr 23 02:46:01 PM PDT 24
Finished Apr 23 02:46:03 PM PDT 24
Peak memory 194348 kb
Host smart-b33a08f0-8a0d-4ca2-91dc-fce819d87af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759489653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.759489653
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2412796385
Short name T1236
Test name
Test status
Simulation time 24066562 ps
CPU time 0.63 seconds
Started Apr 23 02:46:01 PM PDT 24
Finished Apr 23 02:46:03 PM PDT 24
Peak memory 195652 kb
Host smart-1ea7cd9b-eec6-4c3b-892a-aa5fffd36682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412796385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2412796385
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1422377948
Short name T1304
Test name
Test status
Simulation time 498745914 ps
CPU time 2.75 seconds
Started Apr 23 02:45:58 PM PDT 24
Finished Apr 23 02:46:01 PM PDT 24
Peak memory 200064 kb
Host smart-3a15ed76-1ad2-4aca-af5b-05be90d9079b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422377948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1422377948
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2120611852
Short name T123
Test name
Test status
Simulation time 84196434 ps
CPU time 1.34 seconds
Started Apr 23 02:45:59 PM PDT 24
Finished Apr 23 02:46:01 PM PDT 24
Peak memory 199280 kb
Host smart-31abde44-c326-43e2-a697-d51b97b03566
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120611852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2120611852
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.949674695
Short name T1312
Test name
Test status
Simulation time 19500474 ps
CPU time 0.68 seconds
Started Apr 23 02:46:04 PM PDT 24
Finished Apr 23 02:46:06 PM PDT 24
Peak memory 198248 kb
Host smart-22c8f812-3fbf-4cd2-809a-15ce58a5603a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949674695 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.949674695
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2921624746
Short name T1280
Test name
Test status
Simulation time 48899903 ps
CPU time 0.65 seconds
Started Apr 23 02:46:01 PM PDT 24
Finished Apr 23 02:46:02 PM PDT 24
Peak memory 195520 kb
Host smart-1e1f94cd-bdb5-455e-90fb-08eb86e051fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921624746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2921624746
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3087823463
Short name T1213
Test name
Test status
Simulation time 24396003 ps
CPU time 0.55 seconds
Started Apr 23 02:46:02 PM PDT 24
Finished Apr 23 02:46:03 PM PDT 24
Peak memory 194412 kb
Host smart-0cd11787-9951-4f45-89cc-855028c50ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087823463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3087823463
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.414863936
Short name T1224
Test name
Test status
Simulation time 29739848 ps
CPU time 0.67 seconds
Started Apr 23 02:46:02 PM PDT 24
Finished Apr 23 02:46:03 PM PDT 24
Peak memory 195616 kb
Host smart-2c259194-48ba-48b2-9d52-1c6575461b81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414863936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.414863936
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.457649662
Short name T1281
Test name
Test status
Simulation time 177910051 ps
CPU time 1.86 seconds
Started Apr 23 02:46:02 PM PDT 24
Finished Apr 23 02:46:05 PM PDT 24
Peak memory 200100 kb
Host smart-876733eb-fbce-4003-9f8f-9d8bb896a562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457649662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.457649662
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1646470330
Short name T1310
Test name
Test status
Simulation time 95489288 ps
CPU time 0.95 seconds
Started Apr 23 02:46:03 PM PDT 24
Finished Apr 23 02:46:04 PM PDT 24
Peak memory 199132 kb
Host smart-143837c1-c121-49bd-b90c-5e7769937520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646470330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1646470330
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2895166820
Short name T63
Test name
Test status
Simulation time 35869211 ps
CPU time 1.51 seconds
Started Apr 23 02:45:33 PM PDT 24
Finished Apr 23 02:45:35 PM PDT 24
Peak memory 197840 kb
Host smart-df3e0614-93a2-4591-bf70-98dbcbc4576c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895166820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2895166820
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4126781288
Short name T66
Test name
Test status
Simulation time 16007976 ps
CPU time 0.65 seconds
Started Apr 23 02:45:34 PM PDT 24
Finished Apr 23 02:45:35 PM PDT 24
Peak memory 195484 kb
Host smart-1b2c4a11-04c0-441e-9ebd-e459dae91da8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126781288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4126781288
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4217443962
Short name T1262
Test name
Test status
Simulation time 107870713 ps
CPU time 0.85 seconds
Started Apr 23 02:45:41 PM PDT 24
Finished Apr 23 02:45:42 PM PDT 24
Peak memory 199824 kb
Host smart-23846c6d-5197-466d-a848-f259a80726e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217443962 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4217443962
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1543921391
Short name T1220
Test name
Test status
Simulation time 15544403 ps
CPU time 0.59 seconds
Started Apr 23 02:45:33 PM PDT 24
Finished Apr 23 02:45:34 PM PDT 24
Peak memory 195472 kb
Host smart-4bdfc515-e5fa-4aa3-8063-30bc74901dd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543921391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1543921391
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3987650595
Short name T1289
Test name
Test status
Simulation time 32795892 ps
CPU time 0.57 seconds
Started Apr 23 02:45:34 PM PDT 24
Finished Apr 23 02:45:35 PM PDT 24
Peak memory 194456 kb
Host smart-01b14c7c-66aa-4256-9c1e-a03752593ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987650595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3987650595
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1897966220
Short name T89
Test name
Test status
Simulation time 22674595 ps
CPU time 0.69 seconds
Started Apr 23 02:45:34 PM PDT 24
Finished Apr 23 02:45:35 PM PDT 24
Peak memory 195988 kb
Host smart-1f90193f-5ada-4d07-bfcd-5e8385ece851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897966220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1897966220
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2031715621
Short name T1222
Test name
Test status
Simulation time 401909445 ps
CPU time 1.73 seconds
Started Apr 23 02:45:34 PM PDT 24
Finished Apr 23 02:45:36 PM PDT 24
Peak memory 200084 kb
Host smart-e11995cc-f895-4982-b733-039ff6fbef02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031715621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2031715621
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.667116535
Short name T104
Test name
Test status
Simulation time 83299232 ps
CPU time 1.3 seconds
Started Apr 23 02:45:33 PM PDT 24
Finished Apr 23 02:45:35 PM PDT 24
Peak memory 199284 kb
Host smart-49561087-4b4c-41af-b763-dd9b6ec94564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667116535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.667116535
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1366674786
Short name T1286
Test name
Test status
Simulation time 12347024 ps
CPU time 0.55 seconds
Started Apr 23 02:46:02 PM PDT 24
Finished Apr 23 02:46:03 PM PDT 24
Peak memory 194396 kb
Host smart-1f249127-0ff4-42b7-af62-d88a7323b7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366674786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1366674786
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3769847823
Short name T1309
Test name
Test status
Simulation time 28845697 ps
CPU time 0.59 seconds
Started Apr 23 02:46:04 PM PDT 24
Finished Apr 23 02:46:05 PM PDT 24
Peak memory 194404 kb
Host smart-b79a713b-8016-458a-92da-087eabf40d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769847823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3769847823
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2889700812
Short name T1216
Test name
Test status
Simulation time 81950762 ps
CPU time 0.59 seconds
Started Apr 23 02:46:06 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194468 kb
Host smart-2147acf7-9720-4326-bf50-0e8c409077d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889700812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2889700812
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1910132826
Short name T1290
Test name
Test status
Simulation time 21349908 ps
CPU time 0.6 seconds
Started Apr 23 02:46:05 PM PDT 24
Finished Apr 23 02:46:06 PM PDT 24
Peak memory 194460 kb
Host smart-68932cf5-90d3-4f35-953e-334b9c3d6052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910132826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1910132826
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1171909824
Short name T1221
Test name
Test status
Simulation time 28811178 ps
CPU time 0.59 seconds
Started Apr 23 02:46:05 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194396 kb
Host smart-7156108f-36d8-4e43-b63e-4042cb708ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171909824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1171909824
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3455257408
Short name T1260
Test name
Test status
Simulation time 12244151 ps
CPU time 0.6 seconds
Started Apr 23 02:46:07 PM PDT 24
Finished Apr 23 02:46:08 PM PDT 24
Peak memory 194352 kb
Host smart-b45a5a8b-f396-4d68-8a30-e4961c800964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455257408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3455257408
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3149534396
Short name T1244
Test name
Test status
Simulation time 11476875 ps
CPU time 0.56 seconds
Started Apr 23 02:46:05 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194444 kb
Host smart-85a73424-8fee-4c95-9ed9-1e5901cdd01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149534396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3149534396
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.523751166
Short name T1265
Test name
Test status
Simulation time 11040553 ps
CPU time 0.56 seconds
Started Apr 23 02:46:07 PM PDT 24
Finished Apr 23 02:46:08 PM PDT 24
Peak memory 194404 kb
Host smart-e8dfdb78-ebbb-4c5a-8963-219c4b0cd437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523751166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.523751166
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3371487837
Short name T1275
Test name
Test status
Simulation time 100712971 ps
CPU time 0.56 seconds
Started Apr 23 02:46:06 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194404 kb
Host smart-ec372aee-293a-4ad2-b81c-3467ff98bed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371487837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3371487837
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2063750737
Short name T1209
Test name
Test status
Simulation time 171323522 ps
CPU time 0.56 seconds
Started Apr 23 02:46:06 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194400 kb
Host smart-273a0e3a-398d-4122-89ae-539c0dcb5f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063750737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2063750737
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3553948169
Short name T1223
Test name
Test status
Simulation time 258597485 ps
CPU time 0.79 seconds
Started Apr 23 02:45:34 PM PDT 24
Finished Apr 23 02:45:36 PM PDT 24
Peak memory 196344 kb
Host smart-1967a9e0-2aa4-4c7f-bf43-c46f35778a96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553948169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3553948169
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4290549602
Short name T1315
Test name
Test status
Simulation time 271215878 ps
CPU time 1.59 seconds
Started Apr 23 02:45:37 PM PDT 24
Finished Apr 23 02:45:39 PM PDT 24
Peak memory 198060 kb
Host smart-007508e0-7f60-47b6-8aef-5372757af40e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290549602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4290549602
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1783457677
Short name T1250
Test name
Test status
Simulation time 49902083 ps
CPU time 0.58 seconds
Started Apr 23 02:45:37 PM PDT 24
Finished Apr 23 02:45:38 PM PDT 24
Peak memory 195436 kb
Host smart-58db6186-9aa8-4762-9600-c53b1d6cf97e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783457677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1783457677
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3698981065
Short name T1211
Test name
Test status
Simulation time 82694521 ps
CPU time 0.75 seconds
Started Apr 23 02:45:37 PM PDT 24
Finished Apr 23 02:45:39 PM PDT 24
Peak memory 197876 kb
Host smart-1b209692-de11-48fe-87a7-95f2333f9a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698981065 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3698981065
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4070468787
Short name T1231
Test name
Test status
Simulation time 36877123 ps
CPU time 0.63 seconds
Started Apr 23 02:45:38 PM PDT 24
Finished Apr 23 02:45:39 PM PDT 24
Peak memory 195440 kb
Host smart-6fc27d11-dba7-4cb6-a42b-b9eb5df077ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070468787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4070468787
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3132978342
Short name T1291
Test name
Test status
Simulation time 15684779 ps
CPU time 0.58 seconds
Started Apr 23 02:45:41 PM PDT 24
Finished Apr 23 02:45:42 PM PDT 24
Peak memory 194456 kb
Host smart-e542260b-6d43-4e1b-92b3-c05ae55246b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132978342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3132978342
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.183766510
Short name T86
Test name
Test status
Simulation time 44552194 ps
CPU time 0.66 seconds
Started Apr 23 02:45:36 PM PDT 24
Finished Apr 23 02:45:37 PM PDT 24
Peak memory 195880 kb
Host smart-5d405c97-bab3-4e12-b6fb-1ccbaf5e100c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183766510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.183766510
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2061378870
Short name T1189
Test name
Test status
Simulation time 65224953 ps
CPU time 1.78 seconds
Started Apr 23 02:45:36 PM PDT 24
Finished Apr 23 02:45:38 PM PDT 24
Peak memory 200148 kb
Host smart-a204c317-5b36-4f00-b35a-9b2da47a7f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061378870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2061378870
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2135994708
Short name T93
Test name
Test status
Simulation time 175426963 ps
CPU time 1 seconds
Started Apr 23 02:45:37 PM PDT 24
Finished Apr 23 02:45:38 PM PDT 24
Peak memory 198868 kb
Host smart-da0e339d-7dff-4d90-84b1-1d69a00850a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135994708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2135994708
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.361355657
Short name T1215
Test name
Test status
Simulation time 13940630 ps
CPU time 0.54 seconds
Started Apr 23 02:46:09 PM PDT 24
Finished Apr 23 02:46:10 PM PDT 24
Peak memory 194456 kb
Host smart-6ca7d6fe-a181-4961-a487-3b41081bf37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361355657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.361355657
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2089414137
Short name T1205
Test name
Test status
Simulation time 57449874 ps
CPU time 0.58 seconds
Started Apr 23 02:46:04 PM PDT 24
Finished Apr 23 02:46:05 PM PDT 24
Peak memory 194356 kb
Host smart-b0fcb466-7da6-49cf-a911-770c94bb56e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089414137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2089414137
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4122734774
Short name T1225
Test name
Test status
Simulation time 17268409 ps
CPU time 0.57 seconds
Started Apr 23 02:46:05 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194372 kb
Host smart-52418a0a-c70b-4536-b02a-22a5c7313ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122734774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4122734774
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.816580303
Short name T1238
Test name
Test status
Simulation time 37579020 ps
CPU time 0.57 seconds
Started Apr 23 02:46:05 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194460 kb
Host smart-6dfd332f-ec5d-4f1f-9103-87db68926b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816580303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.816580303
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3890784364
Short name T1235
Test name
Test status
Simulation time 55084158 ps
CPU time 0.55 seconds
Started Apr 23 02:46:06 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194452 kb
Host smart-4934d832-4e57-48af-b286-0581ab4e9045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890784364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3890784364
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3263889745
Short name T1192
Test name
Test status
Simulation time 18448779 ps
CPU time 0.61 seconds
Started Apr 23 02:46:06 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194428 kb
Host smart-35706123-325d-4a03-815a-2782198b7766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263889745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3263889745
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1490211230
Short name T1230
Test name
Test status
Simulation time 14407960 ps
CPU time 0.59 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:10 PM PDT 24
Peak memory 194448 kb
Host smart-3feb88f4-a6dc-4b3a-916d-a0c8602fa35e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490211230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1490211230
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2139276312
Short name T1254
Test name
Test status
Simulation time 13751006 ps
CPU time 0.57 seconds
Started Apr 23 02:46:06 PM PDT 24
Finished Apr 23 02:46:07 PM PDT 24
Peak memory 194436 kb
Host smart-8768d507-743b-4522-a512-61b10f53f219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139276312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2139276312
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3959096863
Short name T1240
Test name
Test status
Simulation time 35603374 ps
CPU time 0.64 seconds
Started Apr 23 02:46:09 PM PDT 24
Finished Apr 23 02:46:10 PM PDT 24
Peak memory 194380 kb
Host smart-6d0a7a64-4a72-4d04-aa8e-954238d0d3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959096863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3959096863
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2722725166
Short name T1253
Test name
Test status
Simulation time 36043024 ps
CPU time 0.58 seconds
Started Apr 23 02:46:11 PM PDT 24
Finished Apr 23 02:46:12 PM PDT 24
Peak memory 194424 kb
Host smart-c51023ac-8036-4739-98a2-3588d1d60371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722725166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2722725166
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1841114527
Short name T70
Test name
Test status
Simulation time 14219751 ps
CPU time 0.67 seconds
Started Apr 23 02:45:40 PM PDT 24
Finished Apr 23 02:45:41 PM PDT 24
Peak memory 195480 kb
Host smart-7b0c724e-90fb-4dd7-a845-eb7fb86fcea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841114527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1841114527
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.997316660
Short name T67
Test name
Test status
Simulation time 1129066949 ps
CPU time 2.51 seconds
Started Apr 23 02:45:35 PM PDT 24
Finished Apr 23 02:45:38 PM PDT 24
Peak memory 198284 kb
Host smart-45e3d27a-e205-48b9-9da7-3387f464a85a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997316660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.997316660
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3401142747
Short name T1194
Test name
Test status
Simulation time 45722844 ps
CPU time 0.6 seconds
Started Apr 23 02:45:37 PM PDT 24
Finished Apr 23 02:45:38 PM PDT 24
Peak memory 195476 kb
Host smart-489cd428-e2ca-4608-a2dd-9419d41f2d8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401142747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3401142747
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2230231778
Short name T1300
Test name
Test status
Simulation time 20025284 ps
CPU time 0.65 seconds
Started Apr 23 02:45:39 PM PDT 24
Finished Apr 23 02:45:40 PM PDT 24
Peak memory 197944 kb
Host smart-653069d6-3257-4dbe-acce-b38c9b59b8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230231778 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2230231778
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3475845885
Short name T1317
Test name
Test status
Simulation time 90996713 ps
CPU time 0.58 seconds
Started Apr 23 02:45:36 PM PDT 24
Finished Apr 23 02:45:37 PM PDT 24
Peak memory 195508 kb
Host smart-f4b2f40e-c0ec-4237-8967-28d4ef80dc1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475845885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3475845885
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.460272707
Short name T1263
Test name
Test status
Simulation time 38104131 ps
CPU time 0.56 seconds
Started Apr 23 02:45:37 PM PDT 24
Finished Apr 23 02:45:38 PM PDT 24
Peak memory 194420 kb
Host smart-d8e444d1-920d-4c66-a542-7b65bbb42b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460272707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.460272707
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.399508909
Short name T84
Test name
Test status
Simulation time 17627385 ps
CPU time 0.63 seconds
Started Apr 23 02:45:41 PM PDT 24
Finished Apr 23 02:45:42 PM PDT 24
Peak memory 195536 kb
Host smart-6311534a-88c3-4967-949f-a6999603faa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399508909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.399508909
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1315456494
Short name T1207
Test name
Test status
Simulation time 81885277 ps
CPU time 1.67 seconds
Started Apr 23 02:45:38 PM PDT 24
Finished Apr 23 02:45:40 PM PDT 24
Peak memory 200180 kb
Host smart-6ec51f21-9e2d-4df9-95e0-4eccc9200544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315456494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1315456494
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4071052264
Short name T1274
Test name
Test status
Simulation time 138615222 ps
CPU time 0.93 seconds
Started Apr 23 02:45:35 PM PDT 24
Finished Apr 23 02:45:36 PM PDT 24
Peak memory 199044 kb
Host smart-6a5678b5-3542-42a7-8f2c-6e8eca84913c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071052264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4071052264
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2386343151
Short name T1196
Test name
Test status
Simulation time 19964490 ps
CPU time 0.56 seconds
Started Apr 23 02:46:13 PM PDT 24
Finished Apr 23 02:46:14 PM PDT 24
Peak memory 194396 kb
Host smart-07867f91-23da-42a4-9ed8-b444a4417b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386343151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2386343151
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2163672786
Short name T1303
Test name
Test status
Simulation time 70397736 ps
CPU time 0.58 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:09 PM PDT 24
Peak memory 194380 kb
Host smart-88fc999e-ac83-4899-9278-009cdf53b9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163672786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2163672786
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1646364873
Short name T1299
Test name
Test status
Simulation time 49932041 ps
CPU time 0.59 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:13 PM PDT 24
Peak memory 194464 kb
Host smart-c62d5288-af3d-4acb-968f-76451fd53eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646364873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1646364873
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2060094700
Short name T1283
Test name
Test status
Simulation time 69885157 ps
CPU time 0.57 seconds
Started Apr 23 02:46:09 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 194420 kb
Host smart-d4e3713d-5331-40e7-b6da-2df81379e61e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060094700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2060094700
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.435423320
Short name T1293
Test name
Test status
Simulation time 15794905 ps
CPU time 0.56 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:10 PM PDT 24
Peak memory 194400 kb
Host smart-f71705ec-2d8a-4fa5-b19e-04bc92f18fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435423320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.435423320
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3269641914
Short name T1277
Test name
Test status
Simulation time 26794932 ps
CPU time 0.59 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:09 PM PDT 24
Peak memory 194416 kb
Host smart-431324aa-35ec-4bf0-8d8b-3303848dffbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269641914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3269641914
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2395566986
Short name T1237
Test name
Test status
Simulation time 13508712 ps
CPU time 0.58 seconds
Started Apr 23 02:46:10 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 194360 kb
Host smart-35476478-5e49-42b3-be3d-ad001d0a6c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395566986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2395566986
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2264868483
Short name T1272
Test name
Test status
Simulation time 14885296 ps
CPU time 0.62 seconds
Started Apr 23 02:46:10 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 194428 kb
Host smart-aceb8534-10c5-4a4b-9847-c6aea42430a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264868483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2264868483
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2689535552
Short name T1212
Test name
Test status
Simulation time 17798680 ps
CPU time 0.58 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:10 PM PDT 24
Peak memory 194352 kb
Host smart-d473bd45-022b-4707-9e4b-4832ad7ef5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689535552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2689535552
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2292033896
Short name T1294
Test name
Test status
Simulation time 15764098 ps
CPU time 0.54 seconds
Started Apr 23 02:46:09 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 194368 kb
Host smart-c29acc0a-0920-432a-94a3-03c26f14aa32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292033896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2292033896
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3797094583
Short name T1252
Test name
Test status
Simulation time 30571832 ps
CPU time 1.48 seconds
Started Apr 23 02:45:38 PM PDT 24
Finished Apr 23 02:45:40 PM PDT 24
Peak memory 200072 kb
Host smart-8b2d04c0-be92-403e-a50c-6d2da9cbd51a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797094583 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3797094583
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3366925349
Short name T1308
Test name
Test status
Simulation time 48686879 ps
CPU time 0.61 seconds
Started Apr 23 02:45:38 PM PDT 24
Finished Apr 23 02:45:39 PM PDT 24
Peak memory 195476 kb
Host smart-07a0b78f-d1e4-4104-b26a-84dc893f6f52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366925349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3366925349
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2026371533
Short name T1193
Test name
Test status
Simulation time 18317426 ps
CPU time 0.57 seconds
Started Apr 23 02:45:39 PM PDT 24
Finished Apr 23 02:45:40 PM PDT 24
Peak memory 194444 kb
Host smart-60f02b6b-d8f5-4260-90af-6db95e582b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026371533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2026371533
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1423999839
Short name T1270
Test name
Test status
Simulation time 60546959 ps
CPU time 0.63 seconds
Started Apr 23 02:45:40 PM PDT 24
Finished Apr 23 02:45:41 PM PDT 24
Peak memory 195768 kb
Host smart-c053c3cf-46c6-4686-8868-889951ba9950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423999839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1423999839
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4014786408
Short name T1239
Test name
Test status
Simulation time 99684493 ps
CPU time 1.96 seconds
Started Apr 23 02:45:42 PM PDT 24
Finished Apr 23 02:45:45 PM PDT 24
Peak memory 200088 kb
Host smart-476fa34e-fbc9-4ca7-a9b9-b66d829d5ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014786408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4014786408
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2581196438
Short name T94
Test name
Test status
Simulation time 132642467 ps
CPU time 0.92 seconds
Started Apr 23 02:45:38 PM PDT 24
Finished Apr 23 02:45:39 PM PDT 24
Peak memory 198980 kb
Host smart-93b287d6-51ca-448e-9dc7-cf4f7713852a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581196438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2581196438
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1228753120
Short name T1202
Test name
Test status
Simulation time 33005545 ps
CPU time 0.82 seconds
Started Apr 23 02:45:42 PM PDT 24
Finished Apr 23 02:45:43 PM PDT 24
Peak memory 199844 kb
Host smart-79fded7b-318b-4403-9a55-dc2a0fc6f830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228753120 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1228753120
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.651476960
Short name T64
Test name
Test status
Simulation time 18903552 ps
CPU time 0.65 seconds
Started Apr 23 02:45:39 PM PDT 24
Finished Apr 23 02:45:40 PM PDT 24
Peak memory 195436 kb
Host smart-36a4a5b3-7d8d-4ee4-a341-3986203d62f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651476960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.651476960
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2329991175
Short name T1314
Test name
Test status
Simulation time 16488123 ps
CPU time 0.59 seconds
Started Apr 23 02:45:38 PM PDT 24
Finished Apr 23 02:45:39 PM PDT 24
Peak memory 194408 kb
Host smart-15dec0ea-bed4-449c-9d55-01376583a1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329991175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2329991175
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2988943690
Short name T1256
Test name
Test status
Simulation time 52457229 ps
CPU time 0.66 seconds
Started Apr 23 02:45:41 PM PDT 24
Finished Apr 23 02:45:43 PM PDT 24
Peak memory 195956 kb
Host smart-e967096a-aa61-4d73-9810-aaa58794b8ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988943690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2988943690
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2220578629
Short name T1255
Test name
Test status
Simulation time 20239660 ps
CPU time 1.19 seconds
Started Apr 23 02:45:37 PM PDT 24
Finished Apr 23 02:45:39 PM PDT 24
Peak memory 200160 kb
Host smart-612eff97-950a-4fbe-bb16-995c46d05e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220578629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2220578629
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2498390790
Short name T124
Test name
Test status
Simulation time 98833023 ps
CPU time 0.94 seconds
Started Apr 23 02:45:42 PM PDT 24
Finished Apr 23 02:45:43 PM PDT 24
Peak memory 198788 kb
Host smart-e8bb91e7-5ac2-43e1-8593-2276aff1787d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498390790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2498390790
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3935784681
Short name T1228
Test name
Test status
Simulation time 19220813 ps
CPU time 0.93 seconds
Started Apr 23 02:45:43 PM PDT 24
Finished Apr 23 02:45:44 PM PDT 24
Peak memory 199848 kb
Host smart-08bee6eb-2c2f-498e-94df-94c49c44175a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935784681 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3935784681
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2760348076
Short name T1316
Test name
Test status
Simulation time 18442864 ps
CPU time 0.63 seconds
Started Apr 23 02:45:43 PM PDT 24
Finished Apr 23 02:45:44 PM PDT 24
Peak memory 195728 kb
Host smart-688a67c9-7c09-4644-af96-9ebcf5ec5986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760348076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2760348076
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3470172181
Short name T1296
Test name
Test status
Simulation time 14784098 ps
CPU time 0.57 seconds
Started Apr 23 02:45:42 PM PDT 24
Finished Apr 23 02:45:43 PM PDT 24
Peak memory 194388 kb
Host smart-5717835c-b7f3-4517-bc49-5cbc45908164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470172181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3470172181
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2151040164
Short name T1243
Test name
Test status
Simulation time 66319893 ps
CPU time 0.63 seconds
Started Apr 23 02:45:41 PM PDT 24
Finished Apr 23 02:45:42 PM PDT 24
Peak memory 195828 kb
Host smart-7d48854c-2be4-49b9-b93d-3c50a51d22f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151040164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2151040164
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.791910661
Short name T1201
Test name
Test status
Simulation time 261684261 ps
CPU time 1.6 seconds
Started Apr 23 02:45:43 PM PDT 24
Finished Apr 23 02:45:45 PM PDT 24
Peak memory 200100 kb
Host smart-dcff88be-4c70-4109-afb2-d83552048feb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791910661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.791910661
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1281646013
Short name T97
Test name
Test status
Simulation time 170680250 ps
CPU time 0.92 seconds
Started Apr 23 02:45:41 PM PDT 24
Finished Apr 23 02:45:43 PM PDT 24
Peak memory 198964 kb
Host smart-f6fdbb0c-b8d3-42b4-9cb4-6ccfdb5c8757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281646013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1281646013
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1216166971
Short name T1292
Test name
Test status
Simulation time 24208090 ps
CPU time 0.76 seconds
Started Apr 23 02:45:45 PM PDT 24
Finished Apr 23 02:45:47 PM PDT 24
Peak memory 198796 kb
Host smart-b1145b57-0fdc-49c6-b665-6fa1dfdad907
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216166971 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1216166971
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.465435503
Short name T1261
Test name
Test status
Simulation time 18396298 ps
CPU time 0.6 seconds
Started Apr 23 02:45:45 PM PDT 24
Finished Apr 23 02:45:46 PM PDT 24
Peak memory 195508 kb
Host smart-3de3a7cb-b3d7-4cc7-aece-02d47ce769f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465435503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.465435503
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2289611995
Short name T1232
Test name
Test status
Simulation time 18647260 ps
CPU time 0.56 seconds
Started Apr 23 02:45:47 PM PDT 24
Finished Apr 23 02:45:48 PM PDT 24
Peak memory 194396 kb
Host smart-7d083322-8586-47a8-8467-833ce3bb285a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289611995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2289611995
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1774497831
Short name T88
Test name
Test status
Simulation time 50681551 ps
CPU time 0.69 seconds
Started Apr 23 02:45:46 PM PDT 24
Finished Apr 23 02:45:47 PM PDT 24
Peak memory 195568 kb
Host smart-495f7410-5b0b-4eb9-8012-1962eddaf7eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774497831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1774497831
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1057997567
Short name T1298
Test name
Test status
Simulation time 317818437 ps
CPU time 1.82 seconds
Started Apr 23 02:45:46 PM PDT 24
Finished Apr 23 02:45:48 PM PDT 24
Peak memory 200064 kb
Host smart-36e2cbd0-0a67-4200-aae6-ca189bdc6a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057997567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1057997567
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4081389702
Short name T1311
Test name
Test status
Simulation time 84177391 ps
CPU time 1.37 seconds
Started Apr 23 02:45:44 PM PDT 24
Finished Apr 23 02:45:46 PM PDT 24
Peak memory 199704 kb
Host smart-5ac6fa3f-5419-49b6-a3b2-a88e83ea07cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081389702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4081389702
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.606534306
Short name T1285
Test name
Test status
Simulation time 24490551 ps
CPU time 0.79 seconds
Started Apr 23 02:45:47 PM PDT 24
Finished Apr 23 02:45:48 PM PDT 24
Peak memory 199872 kb
Host smart-d0688864-592b-4b46-949f-ecc436878484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606534306 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.606534306
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3205361488
Short name T1297
Test name
Test status
Simulation time 89056144 ps
CPU time 0.57 seconds
Started Apr 23 02:45:48 PM PDT 24
Finished Apr 23 02:45:49 PM PDT 24
Peak memory 195464 kb
Host smart-a2af8fce-1508-465b-a71b-00c63b03340d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205361488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3205361488
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1333215340
Short name T1257
Test name
Test status
Simulation time 12074829 ps
CPU time 0.57 seconds
Started Apr 23 02:45:46 PM PDT 24
Finished Apr 23 02:45:47 PM PDT 24
Peak memory 194396 kb
Host smart-23ae0d8f-005a-4579-a585-53f09d726f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333215340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1333215340
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2860640728
Short name T1259
Test name
Test status
Simulation time 126208097 ps
CPU time 0.77 seconds
Started Apr 23 02:45:50 PM PDT 24
Finished Apr 23 02:45:52 PM PDT 24
Peak memory 197008 kb
Host smart-1fbf126b-d7a3-4dc0-90a7-5bc1cad21f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860640728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2860640728
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1953108616
Short name T1206
Test name
Test status
Simulation time 94511852 ps
CPU time 1.38 seconds
Started Apr 23 02:45:44 PM PDT 24
Finished Apr 23 02:45:46 PM PDT 24
Peak memory 200100 kb
Host smart-c02a235a-61c0-44cf-999a-3e75f6497d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953108616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1953108616
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1414205535
Short name T103
Test name
Test status
Simulation time 228907339 ps
CPU time 1.31 seconds
Started Apr 23 02:45:45 PM PDT 24
Finished Apr 23 02:45:47 PM PDT 24
Peak memory 199520 kb
Host smart-e3514c91-3beb-4a98-b86a-66df694a904c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414205535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1414205535
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.58190806
Short name T601
Test name
Test status
Simulation time 190985911788 ps
CPU time 192.85 seconds
Started Apr 23 01:58:09 PM PDT 24
Finished Apr 23 02:01:22 PM PDT 24
Peak memory 200872 kb
Host smart-6253d5e1-4ec3-403e-aa2e-18a56b835b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58190806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.58190806
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.958960779
Short name T916
Test name
Test status
Simulation time 29603466942 ps
CPU time 26.39 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 01:58:37 PM PDT 24
Peak memory 200796 kb
Host smart-4fd48e65-8cbf-42f3-98c2-a93818f68108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958960779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.958960779
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2374757165
Short name T1000
Test name
Test status
Simulation time 74050106954 ps
CPU time 135.01 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 02:00:25 PM PDT 24
Peak memory 200760 kb
Host smart-bde57272-d135-4a27-a785-f255f43ac3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374757165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2374757165
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1998320057
Short name T523
Test name
Test status
Simulation time 20170873144 ps
CPU time 49.71 seconds
Started Apr 23 01:58:12 PM PDT 24
Finished Apr 23 01:59:03 PM PDT 24
Peak memory 200788 kb
Host smart-3d09108e-a6df-4a6f-a1d9-ecdbc40872e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998320057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1998320057
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.152211652
Short name T547
Test name
Test status
Simulation time 46207946080 ps
CPU time 211.85 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 02:01:43 PM PDT 24
Peak memory 200768 kb
Host smart-015f9f96-ab62-4847-adf1-634c01d33cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152211652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.152211652
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.89975691
Short name T767
Test name
Test status
Simulation time 1598484243 ps
CPU time 3.96 seconds
Started Apr 23 01:58:09 PM PDT 24
Finished Apr 23 01:58:13 PM PDT 24
Peak memory 198300 kb
Host smart-80552fff-3b9c-41ad-8d78-d454de239e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89975691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.89975691
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2274702483
Short name T1019
Test name
Test status
Simulation time 119674572079 ps
CPU time 57.25 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 01:59:08 PM PDT 24
Peak memory 199524 kb
Host smart-87a9fb18-4d33-407f-9629-ccf5fedc003e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274702483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2274702483
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3009106222
Short name T831
Test name
Test status
Simulation time 17936742347 ps
CPU time 156.26 seconds
Started Apr 23 01:58:09 PM PDT 24
Finished Apr 23 02:00:46 PM PDT 24
Peak memory 200864 kb
Host smart-f22e6e8a-6bd9-45b9-9811-e4db641d4d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009106222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3009106222
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3527152451
Short name T424
Test name
Test status
Simulation time 5618790416 ps
CPU time 47.12 seconds
Started Apr 23 01:58:07 PM PDT 24
Finished Apr 23 01:58:54 PM PDT 24
Peak memory 198716 kb
Host smart-247417ab-b937-469b-8307-80e719504869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527152451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3527152451
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2732898431
Short name T73
Test name
Test status
Simulation time 7598065004 ps
CPU time 11.47 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 01:58:23 PM PDT 24
Peak memory 200588 kb
Host smart-f7bbce9f-75b3-4c6c-b470-5650916803ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732898431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2732898431
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1295257256
Short name T906
Test name
Test status
Simulation time 3896382775 ps
CPU time 2.29 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 01:58:13 PM PDT 24
Peak memory 196936 kb
Host smart-e361b191-a148-4b5b-8887-c30159efa3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295257256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1295257256
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3521116488
Short name T107
Test name
Test status
Simulation time 114775010 ps
CPU time 0.77 seconds
Started Apr 23 01:58:12 PM PDT 24
Finished Apr 23 01:58:13 PM PDT 24
Peak memory 218864 kb
Host smart-d83e369d-7cc5-4eba-9899-12692e3b29a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521116488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3521116488
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.30949210
Short name T1018
Test name
Test status
Simulation time 434225259 ps
CPU time 1.31 seconds
Started Apr 23 01:58:08 PM PDT 24
Finished Apr 23 01:58:10 PM PDT 24
Peak memory 199600 kb
Host smart-45bd3f00-2a89-40cd-9a90-c151e8fe9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30949210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.30949210
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.644306946
Short name T1185
Test name
Test status
Simulation time 50979851902 ps
CPU time 743.98 seconds
Started Apr 23 01:58:09 PM PDT 24
Finished Apr 23 02:10:33 PM PDT 24
Peak memory 200768 kb
Host smart-424e7f6d-c659-4d39-949e-d61882fb09e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644306946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.644306946
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2297042202
Short name T1061
Test name
Test status
Simulation time 61411834738 ps
CPU time 890.16 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 02:13:00 PM PDT 24
Peak memory 217356 kb
Host smart-1542a3e3-4e9a-48d0-af8e-21e1fe11540b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297042202 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2297042202
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3005094982
Short name T622
Test name
Test status
Simulation time 3741543637 ps
CPU time 2.22 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 01:58:13 PM PDT 24
Peak memory 200856 kb
Host smart-57a2abeb-4d3e-4997-92ec-b530506aac41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005094982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3005094982
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.287464550
Short name T482
Test name
Test status
Simulation time 29204900231 ps
CPU time 18.53 seconds
Started Apr 23 01:58:12 PM PDT 24
Finished Apr 23 01:58:31 PM PDT 24
Peak memory 200828 kb
Host smart-47535124-a8e4-4016-8610-b0c12e72bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287464550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.287464550
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3123583973
Short name T1137
Test name
Test status
Simulation time 42991850 ps
CPU time 0.56 seconds
Started Apr 23 01:58:13 PM PDT 24
Finished Apr 23 01:58:14 PM PDT 24
Peak memory 196132 kb
Host smart-1a59f465-17c2-451a-92b0-77e523327f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123583973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3123583973
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2924328348
Short name T621
Test name
Test status
Simulation time 39494440502 ps
CPU time 67.33 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 01:59:18 PM PDT 24
Peak memory 200876 kb
Host smart-99a0d1f7-09d0-46c4-b714-bd190471a4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924328348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2924328348
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2499387275
Short name T72
Test name
Test status
Simulation time 122147251193 ps
CPU time 178.73 seconds
Started Apr 23 01:58:10 PM PDT 24
Finished Apr 23 02:01:10 PM PDT 24
Peak memory 200752 kb
Host smart-456ded93-502c-4c90-b842-268e0b74ec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499387275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2499387275
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3369072223
Short name T249
Test name
Test status
Simulation time 236959430907 ps
CPU time 104.55 seconds
Started Apr 23 01:58:19 PM PDT 24
Finished Apr 23 02:00:04 PM PDT 24
Peak memory 200812 kb
Host smart-90e6ab27-0268-4bf8-90ba-e64075ac9fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369072223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3369072223
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.83952991
Short name T409
Test name
Test status
Simulation time 30864712387 ps
CPU time 14.15 seconds
Started Apr 23 01:58:12 PM PDT 24
Finished Apr 23 01:58:26 PM PDT 24
Peak memory 199720 kb
Host smart-7608347e-7c3f-4f19-a120-65780bdd40b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83952991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.83952991
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2651163016
Short name T660
Test name
Test status
Simulation time 96416571674 ps
CPU time 838.46 seconds
Started Apr 23 01:58:14 PM PDT 24
Finished Apr 23 02:12:13 PM PDT 24
Peak memory 200856 kb
Host smart-31af1f8e-949b-41c5-b06d-096bb005ac94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651163016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2651163016
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2844284404
Short name T456
Test name
Test status
Simulation time 1012469035 ps
CPU time 2.29 seconds
Started Apr 23 01:58:13 PM PDT 24
Finished Apr 23 01:58:16 PM PDT 24
Peak memory 196576 kb
Host smart-21f6d027-c4f4-4357-bec8-a79f54e53df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844284404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2844284404
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2972029589
Short name T422
Test name
Test status
Simulation time 420706820834 ps
CPU time 40.66 seconds
Started Apr 23 01:58:13 PM PDT 24
Finished Apr 23 01:58:54 PM PDT 24
Peak memory 200932 kb
Host smart-5fab493d-7cc6-46e1-a86a-7efbccbbafcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972029589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2972029589
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2536553447
Short name T1067
Test name
Test status
Simulation time 11585967508 ps
CPU time 144.08 seconds
Started Apr 23 01:58:14 PM PDT 24
Finished Apr 23 02:00:39 PM PDT 24
Peak memory 200892 kb
Host smart-2dd65538-585d-4ac2-8d6c-c34c9c24f5b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536553447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2536553447
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1933020056
Short name T452
Test name
Test status
Simulation time 3491382681 ps
CPU time 6.26 seconds
Started Apr 23 01:58:13 PM PDT 24
Finished Apr 23 01:58:20 PM PDT 24
Peak memory 198860 kb
Host smart-656f1454-4ed0-418f-88d2-0fea7cc21252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933020056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1933020056
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3696013873
Short name T443
Test name
Test status
Simulation time 122818438964 ps
CPU time 150.33 seconds
Started Apr 23 01:58:14 PM PDT 24
Finished Apr 23 02:00:45 PM PDT 24
Peak memory 200780 kb
Host smart-edd130e1-f087-467b-92fa-a5f002427b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696013873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3696013873
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3355387513
Short name T1021
Test name
Test status
Simulation time 658277509 ps
CPU time 1.14 seconds
Started Apr 23 01:58:19 PM PDT 24
Finished Apr 23 01:58:21 PM PDT 24
Peak memory 196228 kb
Host smart-45681356-c344-4161-bf92-d8313ad3aadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355387513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3355387513
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.746683887
Short name T27
Test name
Test status
Simulation time 38010559 ps
CPU time 0.78 seconds
Started Apr 23 01:58:12 PM PDT 24
Finished Apr 23 01:58:13 PM PDT 24
Peak memory 218720 kb
Host smart-76baff03-ac10-440a-8df2-e153e7d8ea02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746683887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.746683887
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3524206164
Short name T963
Test name
Test status
Simulation time 459798525 ps
CPU time 1.22 seconds
Started Apr 23 01:58:09 PM PDT 24
Finished Apr 23 01:58:10 PM PDT 24
Peak memory 199164 kb
Host smart-ba3bccf1-8508-4f03-b58b-1fbb113b0457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524206164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3524206164
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.523859271
Short name T112
Test name
Test status
Simulation time 36912046341 ps
CPU time 327.78 seconds
Started Apr 23 01:58:19 PM PDT 24
Finished Apr 23 02:03:48 PM PDT 24
Peak memory 217072 kb
Host smart-3d8dbf37-853e-4f41-bf1f-9f09fd407fc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523859271 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.523859271
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1526495392
Short name T416
Test name
Test status
Simulation time 13046477496 ps
CPU time 13.34 seconds
Started Apr 23 01:58:15 PM PDT 24
Finished Apr 23 01:58:29 PM PDT 24
Peak memory 200704 kb
Host smart-47a9a35c-76e9-43a7-80b5-664d4f82eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526495392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1526495392
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_alert_test.3493207815
Short name T348
Test name
Test status
Simulation time 115926087 ps
CPU time 0.54 seconds
Started Apr 23 01:58:38 PM PDT 24
Finished Apr 23 01:58:39 PM PDT 24
Peak memory 196132 kb
Host smart-13fb54ae-77f8-4d6e-aed6-f2df17ad7f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493207815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3493207815
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.251067901
Short name T812
Test name
Test status
Simulation time 49946620972 ps
CPU time 19.67 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:58:56 PM PDT 24
Peak memory 200668 kb
Host smart-8eda1dfe-db03-4c9a-9327-ca156247de2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251067901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.251067901
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2404558134
Short name T1017
Test name
Test status
Simulation time 42041087935 ps
CPU time 66.29 seconds
Started Apr 23 01:58:45 PM PDT 24
Finished Apr 23 01:59:52 PM PDT 24
Peak memory 200500 kb
Host smart-a1ee74af-87fe-42ed-a5b0-5e6ef5d2d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404558134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2404558134
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.3765065804
Short name T120
Test name
Test status
Simulation time 73426808430 ps
CPU time 91.73 seconds
Started Apr 23 01:58:46 PM PDT 24
Finished Apr 23 02:00:18 PM PDT 24
Peak memory 200664 kb
Host smart-7b99a794-3644-4090-9740-055a55ad96ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765065804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3765065804
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2478919270
Short name T974
Test name
Test status
Simulation time 37038203100 ps
CPU time 72.37 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:59:49 PM PDT 24
Peak memory 200860 kb
Host smart-f8c8b8ab-3564-4165-a7e7-1487f0d76cb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478919270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2478919270
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2214451885
Short name T705
Test name
Test status
Simulation time 4004049314 ps
CPU time 2.43 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:58:39 PM PDT 24
Peak memory 199584 kb
Host smart-f0c2b910-2a2c-4126-ae59-a6d43b441575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214451885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2214451885
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1875554245
Short name T359
Test name
Test status
Simulation time 1997731621 ps
CPU time 3.42 seconds
Started Apr 23 01:58:46 PM PDT 24
Finished Apr 23 01:58:50 PM PDT 24
Peak memory 195344 kb
Host smart-6b0e16ad-0bff-4d7d-9d44-07f98e9fedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875554245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1875554245
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.155977174
Short name T1057
Test name
Test status
Simulation time 16677299802 ps
CPU time 179.03 seconds
Started Apr 23 01:58:34 PM PDT 24
Finished Apr 23 02:01:33 PM PDT 24
Peak memory 200772 kb
Host smart-a6441527-ae34-417b-b33c-45c79cd4c6e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155977174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.155977174
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3512495130
Short name T657
Test name
Test status
Simulation time 4580047721 ps
CPU time 16.35 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:58:53 PM PDT 24
Peak memory 199876 kb
Host smart-4fddb195-3416-4452-b944-d702e0a4dee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512495130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3512495130
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3162187264
Short name T451
Test name
Test status
Simulation time 123722507060 ps
CPU time 38.74 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 01:59:14 PM PDT 24
Peak memory 200772 kb
Host smart-bc2930f4-a988-46b9-b776-b8b84a46939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162187264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3162187264
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.220575294
Short name T1170
Test name
Test status
Simulation time 4579471820 ps
CPU time 2.3 seconds
Started Apr 23 01:58:37 PM PDT 24
Finished Apr 23 01:58:40 PM PDT 24
Peak memory 197148 kb
Host smart-d6144738-dc37-4092-8538-8ddec9ad22e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220575294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.220575294
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3742204074
Short name T389
Test name
Test status
Simulation time 658820348 ps
CPU time 1.69 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:58:39 PM PDT 24
Peak memory 200212 kb
Host smart-5fb3b0eb-c932-4e98-b92f-fe372fa3f6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742204074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3742204074
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.563501061
Short name T806
Test name
Test status
Simulation time 265565676876 ps
CPU time 2486.34 seconds
Started Apr 23 01:58:46 PM PDT 24
Finished Apr 23 02:40:13 PM PDT 24
Peak memory 200804 kb
Host smart-30616ba2-5c00-4079-b368-09f02f23f8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563501061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.563501061
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2070011519
Short name T912
Test name
Test status
Simulation time 83996703787 ps
CPU time 737.77 seconds
Started Apr 23 01:58:45 PM PDT 24
Finished Apr 23 02:11:03 PM PDT 24
Peak memory 217188 kb
Host smart-3abdc820-277b-4d69-a7f4-563e14d534e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070011519 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2070011519
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3362972569
Short name T475
Test name
Test status
Simulation time 1438263726 ps
CPU time 2.5 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:58:42 PM PDT 24
Peak memory 199676 kb
Host smart-a460ba50-e4dd-4f37-be07-b9a8625c3b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362972569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3362972569
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3623858717
Short name T467
Test name
Test status
Simulation time 86076697727 ps
CPU time 19.85 seconds
Started Apr 23 01:58:46 PM PDT 24
Finished Apr 23 01:59:06 PM PDT 24
Peak memory 200768 kb
Host smart-50764a64-b532-4c89-b67f-8cc157ab2b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623858717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3623858717
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3758966832
Short name T897
Test name
Test status
Simulation time 15903638100 ps
CPU time 25.52 seconds
Started Apr 23 02:04:18 PM PDT 24
Finished Apr 23 02:04:44 PM PDT 24
Peak memory 200752 kb
Host smart-3f77a116-bf26-41c4-a8df-5cbf29f309c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758966832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3758966832
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.202731624
Short name T261
Test name
Test status
Simulation time 104270855989 ps
CPU time 46.3 seconds
Started Apr 23 02:04:19 PM PDT 24
Finished Apr 23 02:05:06 PM PDT 24
Peak memory 200856 kb
Host smart-f2a84177-eb01-4ce8-af94-2e07a1681149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202731624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.202731624
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1620398973
Short name T195
Test name
Test status
Simulation time 18223314895 ps
CPU time 28.12 seconds
Started Apr 23 02:04:19 PM PDT 24
Finished Apr 23 02:04:48 PM PDT 24
Peak memory 200852 kb
Host smart-b9714345-a54b-4b57-a4af-5ae48c796960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620398973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1620398973
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1857625016
Short name T944
Test name
Test status
Simulation time 41136184670 ps
CPU time 20.02 seconds
Started Apr 23 02:04:19 PM PDT 24
Finished Apr 23 02:04:40 PM PDT 24
Peak memory 200808 kb
Host smart-d8daa1d5-d66b-4bb2-b761-4f6b435b4b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857625016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1857625016
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.537242421
Short name T290
Test name
Test status
Simulation time 56795968797 ps
CPU time 54.68 seconds
Started Apr 23 02:04:19 PM PDT 24
Finished Apr 23 02:05:15 PM PDT 24
Peak memory 200860 kb
Host smart-030d620c-4852-4df8-88a2-50499e4957ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537242421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.537242421
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1727896148
Short name T404
Test name
Test status
Simulation time 15056698963 ps
CPU time 11.8 seconds
Started Apr 23 02:04:21 PM PDT 24
Finished Apr 23 02:04:33 PM PDT 24
Peak memory 200808 kb
Host smart-d1d1c6e8-168b-4908-99db-cee528b2bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727896148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1727896148
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.777634274
Short name T505
Test name
Test status
Simulation time 68790844721 ps
CPU time 108.79 seconds
Started Apr 23 02:04:22 PM PDT 24
Finished Apr 23 02:06:11 PM PDT 24
Peak memory 200796 kb
Host smart-dee5c7db-61dd-4a4b-8225-ee80aa7cdc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777634274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.777634274
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.822852723
Short name T48
Test name
Test status
Simulation time 48523642999 ps
CPU time 8.4 seconds
Started Apr 23 02:04:21 PM PDT 24
Finished Apr 23 02:04:30 PM PDT 24
Peak memory 200660 kb
Host smart-375ae799-a173-4a29-8801-578931e0b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822852723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.822852723
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3444269613
Short name T209
Test name
Test status
Simulation time 24809369275 ps
CPU time 51.51 seconds
Started Apr 23 02:04:23 PM PDT 24
Finished Apr 23 02:05:15 PM PDT 24
Peak memory 200908 kb
Host smart-3e4bfa80-9ff2-458f-a988-9b8b18b666eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444269613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3444269613
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3114421229
Short name T1145
Test name
Test status
Simulation time 49291751 ps
CPU time 0.53 seconds
Started Apr 23 01:58:40 PM PDT 24
Finished Apr 23 01:58:41 PM PDT 24
Peak memory 195576 kb
Host smart-7b935d7b-2610-44af-b205-00ae0c93e0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114421229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3114421229
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2161151191
Short name T285
Test name
Test status
Simulation time 200767681892 ps
CPU time 103.16 seconds
Started Apr 23 01:58:40 PM PDT 24
Finished Apr 23 02:00:24 PM PDT 24
Peak memory 200824 kb
Host smart-57448be4-45d3-40ee-b860-1028986c3fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161151191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2161151191
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2987777570
Short name T591
Test name
Test status
Simulation time 46572521846 ps
CPU time 16.52 seconds
Started Apr 23 01:58:37 PM PDT 24
Finished Apr 23 01:58:54 PM PDT 24
Peak memory 200736 kb
Host smart-f281ae1e-e6f2-4b27-bc82-5ae645d0b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987777570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2987777570
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2168309633
Short name T662
Test name
Test status
Simulation time 36630231278 ps
CPU time 33.55 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 01:59:16 PM PDT 24
Peak memory 200908 kb
Host smart-f24feb03-fb87-4642-918a-cf036fc7c312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168309633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2168309633
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.799361095
Short name T945
Test name
Test status
Simulation time 3262263317 ps
CPU time 14.51 seconds
Started Apr 23 01:58:41 PM PDT 24
Finished Apr 23 01:58:56 PM PDT 24
Peak memory 200672 kb
Host smart-437d214a-db64-4546-a17e-4a4293f21af4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799361095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.799361095
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.532857742
Short name T403
Test name
Test status
Simulation time 62618068836 ps
CPU time 235.31 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 02:02:38 PM PDT 24
Peak memory 200704 kb
Host smart-dc75cc68-2438-40f9-9f3a-ec99c29d47e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532857742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.532857742
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1222044396
Short name T1031
Test name
Test status
Simulation time 2278796901 ps
CPU time 4.8 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:58:45 PM PDT 24
Peak memory 199276 kb
Host smart-5da4d8d6-62f8-4627-8c3b-9248d95963f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222044396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1222044396
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1545429846
Short name T695
Test name
Test status
Simulation time 543804623029 ps
CPU time 53.23 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 01:59:37 PM PDT 24
Peak memory 201036 kb
Host smart-c27e95d8-22a2-43d2-8022-290dc7fa3305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545429846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1545429846
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1038649471
Short name T677
Test name
Test status
Simulation time 11198552558 ps
CPU time 119.13 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 02:00:42 PM PDT 24
Peak memory 200804 kb
Host smart-3f001618-c0b3-46df-ad70-f01ebb54c439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038649471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1038649471
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1577535535
Short name T441
Test name
Test status
Simulation time 1651607376 ps
CPU time 1.17 seconds
Started Apr 23 01:58:41 PM PDT 24
Finished Apr 23 01:58:43 PM PDT 24
Peak memory 198628 kb
Host smart-076357b4-ecac-4870-b89f-6c488aeb95ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577535535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1577535535
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1918624959
Short name T141
Test name
Test status
Simulation time 164405625866 ps
CPU time 31.87 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:59:11 PM PDT 24
Peak memory 200772 kb
Host smart-31d6e9fe-8292-447b-a1b1-564423bde600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918624959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1918624959
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.618384816
Short name T980
Test name
Test status
Simulation time 3821646566 ps
CPU time 2.16 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:58:42 PM PDT 24
Peak memory 196720 kb
Host smart-3d2c053a-2570-47d9-859e-3362b5ebdcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618384816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.618384816
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3147205578
Short name T866
Test name
Test status
Simulation time 702515964 ps
CPU time 1.48 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 01:58:44 PM PDT 24
Peak memory 199448 kb
Host smart-77189663-0b66-4464-8590-2f392919372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147205578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3147205578
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2141713758
Short name T752
Test name
Test status
Simulation time 113885288636 ps
CPU time 212.4 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 02:02:12 PM PDT 24
Peak memory 209196 kb
Host smart-5f17ef4a-5f85-4ac2-b1c6-a830cc341dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141713758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2141713758
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3454786729
Short name T582
Test name
Test status
Simulation time 34221629346 ps
CPU time 116.6 seconds
Started Apr 23 01:58:37 PM PDT 24
Finished Apr 23 02:00:34 PM PDT 24
Peak memory 217548 kb
Host smart-07708da3-9611-47a9-889e-cfc988ed97db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454786729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3454786729
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3160415275
Short name T882
Test name
Test status
Simulation time 905390513 ps
CPU time 1.41 seconds
Started Apr 23 01:58:41 PM PDT 24
Finished Apr 23 01:58:42 PM PDT 24
Peak memory 199068 kb
Host smart-605f4342-5531-4ccc-bf08-479e716958fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160415275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3160415275
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3523567657
Short name T922
Test name
Test status
Simulation time 58077922635 ps
CPU time 146.14 seconds
Started Apr 23 02:04:20 PM PDT 24
Finished Apr 23 02:06:47 PM PDT 24
Peak memory 200844 kb
Host smart-4ca38948-6059-4b83-be2e-b7233538b788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523567657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3523567657
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2397646625
Short name T1179
Test name
Test status
Simulation time 15317974736 ps
CPU time 14.31 seconds
Started Apr 23 02:04:22 PM PDT 24
Finished Apr 23 02:04:37 PM PDT 24
Peak memory 200872 kb
Host smart-f3af1310-a574-4fce-bce7-a378a98f85b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397646625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2397646625
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3974758547
Short name T381
Test name
Test status
Simulation time 115351519483 ps
CPU time 63.76 seconds
Started Apr 23 02:04:21 PM PDT 24
Finished Apr 23 02:05:26 PM PDT 24
Peak memory 200904 kb
Host smart-adf79c45-26c4-4bbd-9bea-ab0734fba3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974758547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3974758547
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2196648374
Short name T740
Test name
Test status
Simulation time 134312784307 ps
CPU time 150.89 seconds
Started Apr 23 02:04:24 PM PDT 24
Finished Apr 23 02:06:56 PM PDT 24
Peak memory 200808 kb
Host smart-3a3fd51d-a979-4182-a426-c8bbfdf665dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196648374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2196648374
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1142384147
Short name T232
Test name
Test status
Simulation time 43447191865 ps
CPU time 75 seconds
Started Apr 23 02:04:29 PM PDT 24
Finished Apr 23 02:05:44 PM PDT 24
Peak memory 200772 kb
Host smart-852622d9-305b-4b17-ba82-f603c3c3c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142384147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1142384147
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.545363505
Short name T1035
Test name
Test status
Simulation time 16320712924 ps
CPU time 24.8 seconds
Started Apr 23 02:04:24 PM PDT 24
Finished Apr 23 02:04:49 PM PDT 24
Peak memory 200560 kb
Host smart-caa5ccf1-e12e-4caa-811c-5ea20e5ba3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545363505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.545363505
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4217569505
Short name T236
Test name
Test status
Simulation time 83500826354 ps
CPU time 55.47 seconds
Started Apr 23 02:04:26 PM PDT 24
Finished Apr 23 02:05:22 PM PDT 24
Peak memory 200812 kb
Host smart-5f136d73-a537-4e96-92ec-25600a45bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217569505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4217569505
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3210925874
Short name T810
Test name
Test status
Simulation time 24676719192 ps
CPU time 26.21 seconds
Started Apr 23 02:04:31 PM PDT 24
Finished Apr 23 02:04:57 PM PDT 24
Peak memory 200832 kb
Host smart-cef3f012-5fce-498c-8f02-96929d7dda42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210925874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3210925874
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1733338418
Short name T859
Test name
Test status
Simulation time 23601428754 ps
CPU time 11.59 seconds
Started Apr 23 02:04:31 PM PDT 24
Finished Apr 23 02:04:43 PM PDT 24
Peak memory 200868 kb
Host smart-d43702c3-5d85-426f-8fbf-55c484b82d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733338418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1733338418
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2225088565
Short name T737
Test name
Test status
Simulation time 12607309 ps
CPU time 0.57 seconds
Started Apr 23 01:58:43 PM PDT 24
Finished Apr 23 01:58:44 PM PDT 24
Peak memory 195680 kb
Host smart-77221c65-32ba-4bf2-a5b8-c5eff4343284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225088565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2225088565
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3618445439
Short name T817
Test name
Test status
Simulation time 29801264815 ps
CPU time 10.34 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 01:58:53 PM PDT 24
Peak memory 200640 kb
Host smart-7815af93-79f9-4a57-af7b-fcd70d17e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618445439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3618445439
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3020966311
Short name T508
Test name
Test status
Simulation time 30655505021 ps
CPU time 25.21 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:59:04 PM PDT 24
Peak memory 200628 kb
Host smart-16aec512-965d-46e0-b518-95a87ae43d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020966311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3020966311
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.701598886
Short name T545
Test name
Test status
Simulation time 203425271881 ps
CPU time 336.14 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 02:04:16 PM PDT 24
Peak memory 200800 kb
Host smart-763aa91e-bb4c-498f-9438-f6b2efffeb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701598886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.701598886
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4256678678
Short name T792
Test name
Test status
Simulation time 67686736544 ps
CPU time 32.68 seconds
Started Apr 23 01:58:40 PM PDT 24
Finished Apr 23 01:59:13 PM PDT 24
Peak memory 200804 kb
Host smart-a69fcb36-8d74-4eae-acbe-615770a851ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256678678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4256678678
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2821894898
Short name T594
Test name
Test status
Simulation time 243919136993 ps
CPU time 377.78 seconds
Started Apr 23 01:58:41 PM PDT 24
Finished Apr 23 02:04:59 PM PDT 24
Peak memory 200812 kb
Host smart-a6d4779e-a199-4f2b-8564-ce7512c7bc92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821894898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2821894898
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.610403720
Short name T750
Test name
Test status
Simulation time 5238954001 ps
CPU time 5.18 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 01:58:47 PM PDT 24
Peak memory 200356 kb
Host smart-93cfe3ef-4201-4750-a1fe-5cca4a45c7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610403720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.610403720
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3385699981
Short name T745
Test name
Test status
Simulation time 140177372099 ps
CPU time 64.56 seconds
Started Apr 23 01:58:45 PM PDT 24
Finished Apr 23 01:59:50 PM PDT 24
Peak memory 200392 kb
Host smart-7e2cbab2-7368-44f5-9acf-42ea65ece24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385699981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3385699981
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.109159536
Short name T469
Test name
Test status
Simulation time 19351845026 ps
CPU time 266.01 seconds
Started Apr 23 01:58:43 PM PDT 24
Finished Apr 23 02:03:10 PM PDT 24
Peak memory 200872 kb
Host smart-ccd437cf-9821-43aa-8895-f94701ee7670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109159536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.109159536
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4181945917
Short name T378
Test name
Test status
Simulation time 6689772023 ps
CPU time 16.26 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:58:56 PM PDT 24
Peak memory 199200 kb
Host smart-085ca247-3c37-4c92-8d3b-46e438b48dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181945917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4181945917
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2564772277
Short name T408
Test name
Test status
Simulation time 136712062910 ps
CPU time 74.41 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 01:59:59 PM PDT 24
Peak memory 200860 kb
Host smart-008ef66d-2c9b-4078-b558-5e8b7380f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564772277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2564772277
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4027239472
Short name T1093
Test name
Test status
Simulation time 4133974595 ps
CPU time 1.02 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 01:58:46 PM PDT 24
Peak memory 196836 kb
Host smart-9bb9ab07-33ba-4b92-8518-5bc095548b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027239472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4027239472
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.4089359279
Short name T447
Test name
Test status
Simulation time 6070675239 ps
CPU time 8.06 seconds
Started Apr 23 01:58:41 PM PDT 24
Finished Apr 23 01:58:49 PM PDT 24
Peak memory 199952 kb
Host smart-7be9f3fc-bca4-4b6d-a562-f5195cfc3292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089359279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4089359279
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.820280357
Short name T1161
Test name
Test status
Simulation time 126011905545 ps
CPU time 437.45 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 02:06:02 PM PDT 24
Peak memory 200728 kb
Host smart-423ae7b6-91e9-4515-ab09-e92bada52cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820280357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.820280357
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2247762785
Short name T778
Test name
Test status
Simulation time 491338063 ps
CPU time 1.37 seconds
Started Apr 23 01:58:43 PM PDT 24
Finished Apr 23 01:58:45 PM PDT 24
Peak memory 199304 kb
Host smart-2a813b79-b502-4fb4-8808-4c32cca4fa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247762785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2247762785
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3443368896
Short name T729
Test name
Test status
Simulation time 138438152711 ps
CPU time 81.56 seconds
Started Apr 23 01:58:37 PM PDT 24
Finished Apr 23 01:59:59 PM PDT 24
Peak memory 200924 kb
Host smart-2699949f-6a23-4129-a4a8-62f9ad70caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443368896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3443368896
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1377053471
Short name T486
Test name
Test status
Simulation time 65585224318 ps
CPU time 62.38 seconds
Started Apr 23 02:04:31 PM PDT 24
Finished Apr 23 02:05:34 PM PDT 24
Peak memory 200880 kb
Host smart-449628ee-c9c8-4411-b185-8c5376ae3fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377053471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1377053471
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2745201983
Short name T654
Test name
Test status
Simulation time 104658352948 ps
CPU time 53.49 seconds
Started Apr 23 02:04:30 PM PDT 24
Finished Apr 23 02:05:24 PM PDT 24
Peak memory 200768 kb
Host smart-c4d3c35d-bbdb-40df-a0e6-4c3958aedad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745201983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2745201983
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1772553926
Short name T192
Test name
Test status
Simulation time 70554271868 ps
CPU time 33.72 seconds
Started Apr 23 02:04:32 PM PDT 24
Finished Apr 23 02:05:06 PM PDT 24
Peak memory 200812 kb
Host smart-31305be6-948a-481a-9281-805f6d796e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772553926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1772553926
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1048918039
Short name T162
Test name
Test status
Simulation time 43002814975 ps
CPU time 45.43 seconds
Started Apr 23 02:04:32 PM PDT 24
Finished Apr 23 02:05:18 PM PDT 24
Peak memory 200892 kb
Host smart-c2f315b4-7efd-4120-9b16-ee8ceadc1149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048918039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1048918039
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.4151569031
Short name T305
Test name
Test status
Simulation time 23997418146 ps
CPU time 11.33 seconds
Started Apr 23 02:04:35 PM PDT 24
Finished Apr 23 02:04:46 PM PDT 24
Peak memory 200888 kb
Host smart-8632046b-2c25-411f-9bcf-ea269777fa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151569031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4151569031
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2294128803
Short name T686
Test name
Test status
Simulation time 18031098912 ps
CPU time 36.44 seconds
Started Apr 23 02:04:36 PM PDT 24
Finished Apr 23 02:05:13 PM PDT 24
Peak memory 200712 kb
Host smart-ffe35f1c-f36d-4465-ac24-a0fd7a4e86ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294128803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2294128803
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.4113786748
Short name T207
Test name
Test status
Simulation time 12046029982 ps
CPU time 13.19 seconds
Started Apr 23 02:04:38 PM PDT 24
Finished Apr 23 02:04:52 PM PDT 24
Peak memory 200756 kb
Host smart-40ac0693-1baf-4460-919b-fbc00ee10d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113786748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.4113786748
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.118589837
Short name T1046
Test name
Test status
Simulation time 42196499055 ps
CPU time 41.2 seconds
Started Apr 23 02:04:39 PM PDT 24
Finished Apr 23 02:05:21 PM PDT 24
Peak memory 200744 kb
Host smart-265af6d2-c71f-4e51-95e5-e208744ef793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118589837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.118589837
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.252206881
Short name T501
Test name
Test status
Simulation time 24014132 ps
CPU time 0.56 seconds
Started Apr 23 01:58:47 PM PDT 24
Finished Apr 23 01:58:48 PM PDT 24
Peak memory 196136 kb
Host smart-73a245e3-e33d-4858-a001-f665447361b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252206881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.252206881
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.321772431
Short name T51
Test name
Test status
Simulation time 20656827430 ps
CPU time 37.21 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 01:59:19 PM PDT 24
Peak memory 200788 kb
Host smart-755d3e81-c41c-4f95-bede-3d5d4b1b5b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321772431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.321772431
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2896064457
Short name T1109
Test name
Test status
Simulation time 122939814736 ps
CPU time 204.83 seconds
Started Apr 23 01:58:40 PM PDT 24
Finished Apr 23 02:02:06 PM PDT 24
Peak memory 200860 kb
Host smart-5732ae3c-4296-4d6b-b690-03926013a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896064457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2896064457
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3418945620
Short name T255
Test name
Test status
Simulation time 99561528944 ps
CPU time 45.62 seconds
Started Apr 23 01:58:48 PM PDT 24
Finished Apr 23 01:59:34 PM PDT 24
Peak memory 200848 kb
Host smart-e22ad447-2f4a-4188-afed-03f4f2bc9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418945620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3418945620
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3268347771
Short name T996
Test name
Test status
Simulation time 223435953993 ps
CPU time 82.36 seconds
Started Apr 23 01:58:46 PM PDT 24
Finished Apr 23 02:00:09 PM PDT 24
Peak memory 200772 kb
Host smart-3dd92d58-1643-43b6-9440-88ca2e32f462
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268347771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3268347771
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2048960201
Short name T891
Test name
Test status
Simulation time 47296435118 ps
CPU time 244.33 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 02:02:49 PM PDT 24
Peak memory 200908 kb
Host smart-15a7111f-1e41-4b64-925a-cb7d2e453f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048960201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2048960201
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1455988396
Short name T401
Test name
Test status
Simulation time 10215049441 ps
CPU time 5.62 seconds
Started Apr 23 01:58:45 PM PDT 24
Finished Apr 23 01:58:51 PM PDT 24
Peak memory 199524 kb
Host smart-100ae243-920e-4b58-a543-145a69b4eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455988396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1455988396
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.369418700
Short name T342
Test name
Test status
Simulation time 38796002896 ps
CPU time 14.93 seconds
Started Apr 23 01:58:46 PM PDT 24
Finished Apr 23 01:59:02 PM PDT 24
Peak memory 198220 kb
Host smart-6fcf86e0-072c-4e6a-8472-ecb831b9ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369418700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.369418700
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1396432231
Short name T682
Test name
Test status
Simulation time 17455682496 ps
CPU time 228.63 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 02:02:33 PM PDT 24
Peak memory 200824 kb
Host smart-d535da48-c545-4c77-af99-4ac6da8f94b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396432231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1396432231
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1148685184
Short name T573
Test name
Test status
Simulation time 2018913026 ps
CPU time 9.99 seconds
Started Apr 23 01:58:47 PM PDT 24
Finished Apr 23 01:58:57 PM PDT 24
Peak memory 199328 kb
Host smart-4110bad0-7e74-4baa-98b5-9e3c5636420e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148685184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1148685184
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2442529151
Short name T578
Test name
Test status
Simulation time 131594690740 ps
CPU time 296.48 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 02:03:41 PM PDT 24
Peak memory 200844 kb
Host smart-fb0026a2-b91b-4bbd-9cf0-31d25c2aa79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442529151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2442529151
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3478031511
Short name T372
Test name
Test status
Simulation time 6688564714 ps
CPU time 5.96 seconds
Started Apr 23 01:58:45 PM PDT 24
Finished Apr 23 01:58:52 PM PDT 24
Peak memory 196844 kb
Host smart-fe2e133d-c9c5-4396-b9a3-fa68cf7b049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478031511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3478031511
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.89165442
Short name T311
Test name
Test status
Simulation time 6241619134 ps
CPU time 13.83 seconds
Started Apr 23 01:58:41 PM PDT 24
Finished Apr 23 01:58:55 PM PDT 24
Peak memory 200664 kb
Host smart-4586dace-9fbf-433d-abd4-42a48baa6319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89165442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.89165442
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1828483700
Short name T1123
Test name
Test status
Simulation time 1143827249902 ps
CPU time 401.86 seconds
Started Apr 23 01:58:44 PM PDT 24
Finished Apr 23 02:05:27 PM PDT 24
Peak memory 209196 kb
Host smart-48fc5813-69ec-4807-843b-b6710a563236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828483700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1828483700
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.114572743
Short name T60
Test name
Test status
Simulation time 43638491429 ps
CPU time 543.39 seconds
Started Apr 23 01:58:43 PM PDT 24
Finished Apr 23 02:07:47 PM PDT 24
Peak memory 225660 kb
Host smart-f47be59a-e1d9-42d2-97f2-1abde193d192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114572743 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.114572743
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1208791586
Short name T369
Test name
Test status
Simulation time 535767020 ps
CPU time 1.54 seconds
Started Apr 23 01:58:48 PM PDT 24
Finished Apr 23 01:58:50 PM PDT 24
Peak memory 199304 kb
Host smart-f7779580-8bde-4a46-af65-c3d1f5e5db81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208791586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1208791586
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.69053433
Short name T554
Test name
Test status
Simulation time 89575035404 ps
CPU time 192.26 seconds
Started Apr 23 01:58:42 PM PDT 24
Finished Apr 23 02:01:55 PM PDT 24
Peak memory 200816 kb
Host smart-5c20c5f4-9c08-46b0-8115-b4de65c9b9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69053433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.69053433
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2386893249
Short name T251
Test name
Test status
Simulation time 151525775686 ps
CPU time 62.18 seconds
Started Apr 23 02:04:39 PM PDT 24
Finished Apr 23 02:05:41 PM PDT 24
Peak memory 200792 kb
Host smart-8306628f-8ad4-42d8-b5d9-9532b427ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386893249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2386893249
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3578154721
Short name T1008
Test name
Test status
Simulation time 45602679389 ps
CPU time 12.44 seconds
Started Apr 23 02:04:40 PM PDT 24
Finished Apr 23 02:04:52 PM PDT 24
Peak memory 200836 kb
Host smart-2799c54d-b14a-4c9e-a5a3-839c225d2522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578154721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3578154721
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3278831466
Short name T184
Test name
Test status
Simulation time 52415049234 ps
CPU time 96.82 seconds
Started Apr 23 02:04:45 PM PDT 24
Finished Apr 23 02:06:22 PM PDT 24
Peak memory 200944 kb
Host smart-ab6bbe98-8206-46c8-b1a6-3ff2c83b4c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278831466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3278831466
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3966450072
Short name T907
Test name
Test status
Simulation time 59724436002 ps
CPU time 83.47 seconds
Started Apr 23 02:04:47 PM PDT 24
Finished Apr 23 02:06:11 PM PDT 24
Peak memory 200868 kb
Host smart-bc5b674b-1ac9-44ba-ad09-0d33f4bc96b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966450072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3966450072
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2098956354
Short name T1176
Test name
Test status
Simulation time 16645130298 ps
CPU time 38.54 seconds
Started Apr 23 02:04:47 PM PDT 24
Finished Apr 23 02:05:26 PM PDT 24
Peak memory 200832 kb
Host smart-4d6035e1-2511-443f-be07-a0329b5f939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098956354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2098956354
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1337999123
Short name T720
Test name
Test status
Simulation time 245959794006 ps
CPU time 165.31 seconds
Started Apr 23 02:04:49 PM PDT 24
Finished Apr 23 02:07:35 PM PDT 24
Peak memory 200792 kb
Host smart-9bc0a5db-c0d2-428e-98b8-801400b4c0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337999123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1337999123
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1278119180
Short name T470
Test name
Test status
Simulation time 83883280825 ps
CPU time 158.76 seconds
Started Apr 23 02:04:47 PM PDT 24
Finished Apr 23 02:07:26 PM PDT 24
Peak memory 200848 kb
Host smart-c140dd45-a039-4b1d-8e95-486c7146a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278119180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1278119180
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4255431750
Short name T287
Test name
Test status
Simulation time 136898772118 ps
CPU time 251.83 seconds
Started Apr 23 02:04:47 PM PDT 24
Finished Apr 23 02:08:59 PM PDT 24
Peak memory 200708 kb
Host smart-86409854-5a98-4a83-97ff-568f0de2928f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255431750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4255431750
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2301360912
Short name T1053
Test name
Test status
Simulation time 29046065 ps
CPU time 0.53 seconds
Started Apr 23 01:58:54 PM PDT 24
Finished Apr 23 01:58:55 PM PDT 24
Peak memory 196272 kb
Host smart-32fa00ad-bb1e-42d8-b597-8b66a2b78253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301360912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2301360912
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1978674855
Short name T860
Test name
Test status
Simulation time 31004773485 ps
CPU time 13.77 seconds
Started Apr 23 01:58:49 PM PDT 24
Finished Apr 23 01:59:03 PM PDT 24
Peak memory 200788 kb
Host smart-16f66520-b05e-43e8-8b10-509728faae13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978674855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1978674855
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3883333865
Short name T1120
Test name
Test status
Simulation time 65664136886 ps
CPU time 41.76 seconds
Started Apr 23 01:58:47 PM PDT 24
Finished Apr 23 01:59:29 PM PDT 24
Peak memory 200708 kb
Host smart-08ae5f08-f96e-447a-9ce5-a063ecea2e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883333865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3883333865
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3630346638
Short name T213
Test name
Test status
Simulation time 23541689285 ps
CPU time 50.01 seconds
Started Apr 23 01:58:50 PM PDT 24
Finished Apr 23 01:59:40 PM PDT 24
Peak memory 200872 kb
Host smart-0a48253c-69d9-462a-a683-29157cd4e44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630346638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3630346638
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3634830019
Short name T11
Test name
Test status
Simulation time 44024740721 ps
CPU time 22.78 seconds
Started Apr 23 01:58:51 PM PDT 24
Finished Apr 23 01:59:15 PM PDT 24
Peak memory 200796 kb
Host smart-7108659c-f609-4869-8e26-9b9d758a0459
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634830019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3634830019
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3261414031
Short name T730
Test name
Test status
Simulation time 303334886172 ps
CPU time 130.15 seconds
Started Apr 23 01:58:54 PM PDT 24
Finished Apr 23 02:01:05 PM PDT 24
Peak memory 200892 kb
Host smart-6ee4c80e-7e9c-4959-bbf6-e9bc9c5ba7bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261414031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3261414031
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3323774172
Short name T40
Test name
Test status
Simulation time 1360250453 ps
CPU time 2.7 seconds
Started Apr 23 01:58:51 PM PDT 24
Finished Apr 23 01:58:54 PM PDT 24
Peak memory 198448 kb
Host smart-b5a74c92-fdc1-4ffe-9a83-d4c212e9c285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323774172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3323774172
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.1320500626
Short name T306
Test name
Test status
Simulation time 14592443229 ps
CPU time 35.05 seconds
Started Apr 23 01:58:53 PM PDT 24
Finished Apr 23 01:59:29 PM PDT 24
Peak memory 200844 kb
Host smart-f2ef8983-5395-4585-8d81-69570a02c17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320500626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1320500626
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3919765432
Short name T357
Test name
Test status
Simulation time 1820071011 ps
CPU time 2.09 seconds
Started Apr 23 01:58:50 PM PDT 24
Finished Apr 23 01:58:52 PM PDT 24
Peak memory 198840 kb
Host smart-fbd66a52-570f-4114-95bd-6d28f0c3aeee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919765432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3919765432
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1666504551
Short name T776
Test name
Test status
Simulation time 100942064610 ps
CPU time 141.84 seconds
Started Apr 23 01:58:52 PM PDT 24
Finished Apr 23 02:01:15 PM PDT 24
Peak memory 200616 kb
Host smart-7c73ce28-9104-4969-8b2d-3e7dbd0844ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666504551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1666504551
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3850973370
Short name T347
Test name
Test status
Simulation time 3940504882 ps
CPU time 7.14 seconds
Started Apr 23 01:58:49 PM PDT 24
Finished Apr 23 01:58:57 PM PDT 24
Peak memory 197224 kb
Host smart-e602f2ab-f9ed-4503-a091-a54f48243163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850973370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3850973370
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.255951340
Short name T655
Test name
Test status
Simulation time 6267309235 ps
CPU time 15.27 seconds
Started Apr 23 01:58:48 PM PDT 24
Finished Apr 23 01:59:04 PM PDT 24
Peak memory 200684 kb
Host smart-72aa9c4f-ec30-4278-8890-79386225657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255951340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.255951340
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2859374174
Short name T153
Test name
Test status
Simulation time 154199957879 ps
CPU time 70.68 seconds
Started Apr 23 01:58:53 PM PDT 24
Finished Apr 23 02:00:04 PM PDT 24
Peak memory 200800 kb
Host smart-9c2a50c8-cceb-4778-aa75-6cba8165ee20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859374174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2859374174
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1545983860
Short name T702
Test name
Test status
Simulation time 201971596597 ps
CPU time 565.82 seconds
Started Apr 23 01:58:54 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 229624 kb
Host smart-fc403527-0b5e-4bc0-81c7-5f5b64440932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545983860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1545983860
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.427632062
Short name T930
Test name
Test status
Simulation time 978382140 ps
CPU time 1.48 seconds
Started Apr 23 01:58:53 PM PDT 24
Finished Apr 23 01:58:55 PM PDT 24
Peak memory 199116 kb
Host smart-d5e279d8-b5b1-4403-aa74-4073e0ed9725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427632062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.427632062
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.53529816
Short name T777
Test name
Test status
Simulation time 44561416772 ps
CPU time 15.27 seconds
Started Apr 23 01:58:48 PM PDT 24
Finished Apr 23 01:59:04 PM PDT 24
Peak memory 198740 kb
Host smart-ef3c5aae-8e55-4b2f-89e6-8b41001d338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53529816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.53529816
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1039658801
Short name T664
Test name
Test status
Simulation time 47881761411 ps
CPU time 35.39 seconds
Started Apr 23 02:04:49 PM PDT 24
Finished Apr 23 02:05:25 PM PDT 24
Peak memory 200908 kb
Host smart-05b77137-e582-406e-b2fc-7d31097ce93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039658801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1039658801
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3241146364
Short name T646
Test name
Test status
Simulation time 184504183089 ps
CPU time 133.54 seconds
Started Apr 23 02:04:50 PM PDT 24
Finished Apr 23 02:07:04 PM PDT 24
Peak memory 200940 kb
Host smart-789d7afc-fb25-43ce-964c-f6ceb651a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241146364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3241146364
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3028314771
Short name T690
Test name
Test status
Simulation time 29707012790 ps
CPU time 26.44 seconds
Started Apr 23 02:04:50 PM PDT 24
Finished Apr 23 02:05:17 PM PDT 24
Peak memory 200712 kb
Host smart-0726b642-e892-409e-8bf4-38e569b59f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028314771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3028314771
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2245483620
Short name T663
Test name
Test status
Simulation time 49597507541 ps
CPU time 18.94 seconds
Started Apr 23 02:04:51 PM PDT 24
Finished Apr 23 02:05:10 PM PDT 24
Peak memory 200840 kb
Host smart-b9d02315-d98f-453f-b8a2-1fa8afa2d0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245483620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2245483620
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2057464440
Short name T1119
Test name
Test status
Simulation time 36912748495 ps
CPU time 16.51 seconds
Started Apr 23 02:04:51 PM PDT 24
Finished Apr 23 02:05:08 PM PDT 24
Peak memory 200868 kb
Host smart-79a34cde-f15d-430d-b2fe-8bff57f1de44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057464440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2057464440
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1835750442
Short name T933
Test name
Test status
Simulation time 275796467562 ps
CPU time 53.32 seconds
Started Apr 23 02:04:50 PM PDT 24
Finished Apr 23 02:05:44 PM PDT 24
Peak memory 200892 kb
Host smart-70ec0586-0316-42f3-b383-075841019373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835750442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1835750442
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1011014010
Short name T949
Test name
Test status
Simulation time 34985324455 ps
CPU time 65.44 seconds
Started Apr 23 02:04:56 PM PDT 24
Finished Apr 23 02:06:01 PM PDT 24
Peak memory 200880 kb
Host smart-76379281-e511-4728-977c-e06a77afeb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011014010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1011014010
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2327184045
Short name T398
Test name
Test status
Simulation time 274071940970 ps
CPU time 71.06 seconds
Started Apr 23 02:04:53 PM PDT 24
Finished Apr 23 02:06:04 PM PDT 24
Peak memory 200724 kb
Host smart-a099c79c-0396-48af-8671-8378302dc0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327184045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2327184045
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1934367709
Short name T936
Test name
Test status
Simulation time 145565972299 ps
CPU time 222.75 seconds
Started Apr 23 02:04:53 PM PDT 24
Finished Apr 23 02:08:36 PM PDT 24
Peak memory 200840 kb
Host smart-01c9e05d-c76d-4bf6-a82e-5da02e763c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934367709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1934367709
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2352838675
Short name T380
Test name
Test status
Simulation time 11844318 ps
CPU time 0.56 seconds
Started Apr 23 01:59:01 PM PDT 24
Finished Apr 23 01:59:01 PM PDT 24
Peak memory 196232 kb
Host smart-f538a327-d87c-42d8-9455-a7310a6f9128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352838675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2352838675
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3146588755
Short name T757
Test name
Test status
Simulation time 62064919952 ps
CPU time 31.43 seconds
Started Apr 23 01:58:56 PM PDT 24
Finished Apr 23 01:59:28 PM PDT 24
Peak memory 200880 kb
Host smart-da1777ec-1c57-4a7e-a265-4885c8789a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146588755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3146588755
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2911907917
Short name T888
Test name
Test status
Simulation time 77837908011 ps
CPU time 75.87 seconds
Started Apr 23 01:58:57 PM PDT 24
Finished Apr 23 02:00:14 PM PDT 24
Peak memory 200760 kb
Host smart-441a5571-c114-4748-a6b1-ebdbe9d06a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911907917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2911907917
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.226778050
Short name T481
Test name
Test status
Simulation time 4412337396 ps
CPU time 8.16 seconds
Started Apr 23 01:58:58 PM PDT 24
Finished Apr 23 01:59:06 PM PDT 24
Peak memory 197288 kb
Host smart-c2c96581-dc0e-4129-9adb-f6964bea3f48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226778050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.226778050
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.267637301
Short name T638
Test name
Test status
Simulation time 60974029128 ps
CPU time 324.95 seconds
Started Apr 23 01:58:59 PM PDT 24
Finished Apr 23 02:04:25 PM PDT 24
Peak memory 200836 kb
Host smart-ef2c7ef1-2425-4716-90f0-805b7bbb8aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267637301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.267637301
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.34260372
Short name T1079
Test name
Test status
Simulation time 9808511144 ps
CPU time 9.96 seconds
Started Apr 23 01:59:00 PM PDT 24
Finished Apr 23 01:59:10 PM PDT 24
Peak memory 199152 kb
Host smart-e5d84050-2862-4e7b-a868-60780bc11f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34260372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.34260372
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1267153183
Short name T286
Test name
Test status
Simulation time 18136609347 ps
CPU time 31.85 seconds
Started Apr 23 01:58:59 PM PDT 24
Finished Apr 23 01:59:31 PM PDT 24
Peak memory 199488 kb
Host smart-b9dc2fe3-6ed8-4893-8db4-3f56c2f51d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267153183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1267153183
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3674507211
Short name T900
Test name
Test status
Simulation time 11594930280 ps
CPU time 138.97 seconds
Started Apr 23 01:58:59 PM PDT 24
Finished Apr 23 02:01:19 PM PDT 24
Peak memory 200868 kb
Host smart-4e75f497-9e74-436e-9df7-2c8b18621ade
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674507211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3674507211
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3184350648
Short name T709
Test name
Test status
Simulation time 5994273137 ps
CPU time 24.23 seconds
Started Apr 23 01:58:58 PM PDT 24
Finished Apr 23 01:59:23 PM PDT 24
Peak memory 198996 kb
Host smart-b042eca7-a67f-47fc-b615-b1007dd5df67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184350648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3184350648
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2612592534
Short name T411
Test name
Test status
Simulation time 225158842362 ps
CPU time 141.42 seconds
Started Apr 23 01:59:00 PM PDT 24
Finished Apr 23 02:01:22 PM PDT 24
Peak memory 200828 kb
Host smart-429aea91-e159-4707-9bed-2294ef1f0fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612592534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2612592534
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3702674207
Short name T588
Test name
Test status
Simulation time 3339635007 ps
CPU time 2.31 seconds
Started Apr 23 01:58:59 PM PDT 24
Finished Apr 23 01:59:02 PM PDT 24
Peak memory 197120 kb
Host smart-5c26a36e-84b7-4196-aefc-ae612c1007cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702674207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3702674207
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3264587485
Short name T1071
Test name
Test status
Simulation time 5450807553 ps
CPU time 23.69 seconds
Started Apr 23 01:58:51 PM PDT 24
Finished Apr 23 01:59:16 PM PDT 24
Peak memory 200724 kb
Host smart-9ef822fa-4c84-4f15-9138-a701f160948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264587485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3264587485
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.214300837
Short name T34
Test name
Test status
Simulation time 69189301927 ps
CPU time 630.9 seconds
Started Apr 23 01:59:03 PM PDT 24
Finished Apr 23 02:09:35 PM PDT 24
Peak memory 225712 kb
Host smart-32c1bcca-1b3e-4b29-a4b6-29d87c60ea33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214300837 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.214300837
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3744428267
Short name T360
Test name
Test status
Simulation time 1242697596 ps
CPU time 2.34 seconds
Started Apr 23 01:59:00 PM PDT 24
Finished Apr 23 01:59:02 PM PDT 24
Peak memory 199616 kb
Host smart-25d79a9e-3609-43c2-8035-ab212a1e3bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744428267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3744428267
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.4224585940
Short name T268
Test name
Test status
Simulation time 85254889227 ps
CPU time 144.33 seconds
Started Apr 23 01:58:58 PM PDT 24
Finished Apr 23 02:01:23 PM PDT 24
Peak memory 200864 kb
Host smart-8b17e03a-2685-416c-a284-3eb4cc668c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224585940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4224585940
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2801212543
Short name T536
Test name
Test status
Simulation time 84008179069 ps
CPU time 149.83 seconds
Started Apr 23 02:04:55 PM PDT 24
Finished Apr 23 02:07:25 PM PDT 24
Peak memory 200924 kb
Host smart-947cef9d-6c3c-4cd4-8e41-7d7b38e09057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801212543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2801212543
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1297370184
Short name T238
Test name
Test status
Simulation time 168186681084 ps
CPU time 306.98 seconds
Started Apr 23 02:04:53 PM PDT 24
Finished Apr 23 02:10:00 PM PDT 24
Peak memory 200856 kb
Host smart-930df2e9-d124-4083-9f2e-aada659d6011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297370184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1297370184
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2956342024
Short name T485
Test name
Test status
Simulation time 15321717727 ps
CPU time 24.19 seconds
Started Apr 23 02:04:53 PM PDT 24
Finished Apr 23 02:05:18 PM PDT 24
Peak memory 200772 kb
Host smart-a74e0051-17cd-4572-9697-a24304e422e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956342024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2956342024
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2534461185
Short name T250
Test name
Test status
Simulation time 201640879233 ps
CPU time 182.83 seconds
Started Apr 23 02:04:56 PM PDT 24
Finished Apr 23 02:08:00 PM PDT 24
Peak memory 200952 kb
Host smart-bad002dd-f40d-4113-b02e-69347fa5f643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534461185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2534461185
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3151154305
Short name T684
Test name
Test status
Simulation time 14098522929 ps
CPU time 33.45 seconds
Started Apr 23 02:04:55 PM PDT 24
Finished Apr 23 02:05:29 PM PDT 24
Peak memory 200824 kb
Host smart-608804f0-bbdd-41b3-bf74-2c5b3d430e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151154305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3151154305
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.173480315
Short name T121
Test name
Test status
Simulation time 24746557904 ps
CPU time 21.53 seconds
Started Apr 23 02:04:57 PM PDT 24
Finished Apr 23 02:05:19 PM PDT 24
Peak memory 200892 kb
Host smart-6ce2fdbf-0ed9-4e07-8360-c725cfd7f526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173480315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.173480315
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3869207775
Short name T881
Test name
Test status
Simulation time 35643379913 ps
CPU time 55.7 seconds
Started Apr 23 02:04:58 PM PDT 24
Finished Apr 23 02:05:54 PM PDT 24
Peak memory 200832 kb
Host smart-0a69128b-a13e-4bc0-9ae3-a40801cdea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869207775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3869207775
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1674804821
Short name T76
Test name
Test status
Simulation time 68657466592 ps
CPU time 29.92 seconds
Started Apr 23 02:04:59 PM PDT 24
Finished Apr 23 02:05:29 PM PDT 24
Peak memory 200872 kb
Host smart-b872804d-53ab-4dee-a4c9-2ac5243e61b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674804821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1674804821
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3048139734
Short name T1013
Test name
Test status
Simulation time 40462536999 ps
CPU time 83.78 seconds
Started Apr 23 02:04:59 PM PDT 24
Finished Apr 23 02:06:23 PM PDT 24
Peak memory 200808 kb
Host smart-a74abfa1-a028-4667-84ad-2235b94169fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048139734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3048139734
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3634957384
Short name T413
Test name
Test status
Simulation time 132507489 ps
CPU time 0.54 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 01:59:11 PM PDT 24
Peak memory 195660 kb
Host smart-7f5cb687-cd9a-4c03-93ec-1745e0ebdeaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634957384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3634957384
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2159095164
Short name T1075
Test name
Test status
Simulation time 69659045090 ps
CPU time 34.74 seconds
Started Apr 23 01:59:03 PM PDT 24
Finished Apr 23 01:59:38 PM PDT 24
Peak memory 200772 kb
Host smart-a83f6f4f-9ef0-4b47-9853-b40f7e6e99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159095164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2159095164
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.252618032
Short name T589
Test name
Test status
Simulation time 23531334095 ps
CPU time 19.92 seconds
Started Apr 23 01:59:06 PM PDT 24
Finished Apr 23 01:59:26 PM PDT 24
Peak memory 199648 kb
Host smart-372b64f9-6896-4a1c-a090-85d8613a2392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252618032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.252618032
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.195869594
Short name T354
Test name
Test status
Simulation time 133636650657 ps
CPU time 292.75 seconds
Started Apr 23 01:59:06 PM PDT 24
Finished Apr 23 02:03:59 PM PDT 24
Peak memory 200848 kb
Host smart-8afdddb8-1325-4b0b-bbb8-c4d25f95cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195869594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.195869594
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2980626778
Short name T17
Test name
Test status
Simulation time 27377434899 ps
CPU time 13.42 seconds
Started Apr 23 01:59:05 PM PDT 24
Finished Apr 23 01:59:19 PM PDT 24
Peak memory 200760 kb
Host smart-3ce2a333-f108-4143-a294-e9784c1f29fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980626778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2980626778
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.4162843376
Short name T606
Test name
Test status
Simulation time 161725379157 ps
CPU time 296.93 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 02:04:07 PM PDT 24
Peak memory 200860 kb
Host smart-ffe87bd6-3ebc-4779-bbdc-119491811f94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162843376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4162843376
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1498611342
Short name T1102
Test name
Test status
Simulation time 3732067189 ps
CPU time 7.57 seconds
Started Apr 23 01:59:07 PM PDT 24
Finished Apr 23 01:59:15 PM PDT 24
Peak memory 199760 kb
Host smart-61221821-3a8e-4b16-b025-c09c8f41c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498611342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1498611342
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2777940717
Short name T521
Test name
Test status
Simulation time 150981455649 ps
CPU time 31.58 seconds
Started Apr 23 01:59:04 PM PDT 24
Finished Apr 23 01:59:36 PM PDT 24
Peak memory 200952 kb
Host smart-bdb59fb8-00b3-449f-8da2-9d61ad32270d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777940717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2777940717
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.137091770
Short name T1039
Test name
Test status
Simulation time 5159908283 ps
CPU time 294.79 seconds
Started Apr 23 01:59:05 PM PDT 24
Finished Apr 23 02:04:00 PM PDT 24
Peak memory 200796 kb
Host smart-ef894a64-954d-4053-99eb-dc57006cb618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137091770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.137091770
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.250483563
Short name T892
Test name
Test status
Simulation time 6679827740 ps
CPU time 16.4 seconds
Started Apr 23 01:59:05 PM PDT 24
Finished Apr 23 01:59:21 PM PDT 24
Peak memory 198932 kb
Host smart-77f4196e-9f47-4493-9053-cde7d9dadbbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250483563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.250483563
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2537253401
Short name T911
Test name
Test status
Simulation time 165383222428 ps
CPU time 380.97 seconds
Started Apr 23 01:59:07 PM PDT 24
Finished Apr 23 02:05:29 PM PDT 24
Peak memory 200760 kb
Host smart-17f82846-6eb2-4815-96bd-0ec5696a0a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537253401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2537253401
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1646354255
Short name T448
Test name
Test status
Simulation time 3393483069 ps
CPU time 5.42 seconds
Started Apr 23 01:59:04 PM PDT 24
Finished Apr 23 01:59:10 PM PDT 24
Peak memory 196836 kb
Host smart-93e590b8-8f4f-4053-96cd-86630d563ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646354255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1646354255
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.164953285
Short name T1173
Test name
Test status
Simulation time 257132247 ps
CPU time 1.16 seconds
Started Apr 23 01:59:02 PM PDT 24
Finished Apr 23 01:59:03 PM PDT 24
Peak memory 199316 kb
Host smart-05e50571-e466-4161-b533-6f0614a0c038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164953285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.164953285
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3054957695
Short name T395
Test name
Test status
Simulation time 215151405580 ps
CPU time 1042.51 seconds
Started Apr 23 01:59:11 PM PDT 24
Finished Apr 23 02:16:34 PM PDT 24
Peak memory 217328 kb
Host smart-08a1e638-a917-4d2f-8f96-aa9c40f86b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054957695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3054957695
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.297286138
Short name T410
Test name
Test status
Simulation time 162720234329 ps
CPU time 1311.29 seconds
Started Apr 23 01:59:08 PM PDT 24
Finished Apr 23 02:21:01 PM PDT 24
Peak memory 216520 kb
Host smart-ff822859-9ec6-4690-a9d4-e76a7230fd90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297286138 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.297286138
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3310399162
Short name T499
Test name
Test status
Simulation time 3935005675 ps
CPU time 1.46 seconds
Started Apr 23 01:59:06 PM PDT 24
Finished Apr 23 01:59:08 PM PDT 24
Peak memory 199660 kb
Host smart-6745db08-4cfd-4294-ba40-2075c15faca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310399162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3310399162
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3317723398
Short name T887
Test name
Test status
Simulation time 127511368742 ps
CPU time 464.46 seconds
Started Apr 23 01:59:01 PM PDT 24
Finished Apr 23 02:06:45 PM PDT 24
Peak memory 200888 kb
Host smart-0b94d662-4842-40ce-9d33-119f49f5b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317723398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3317723398
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.595931453
Short name T304
Test name
Test status
Simulation time 48080681423 ps
CPU time 21.85 seconds
Started Apr 23 02:05:03 PM PDT 24
Finished Apr 23 02:05:25 PM PDT 24
Peak memory 200700 kb
Host smart-7ba06512-cc5a-4047-a41b-2c4ede16fa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595931453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.595931453
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3121679793
Short name T679
Test name
Test status
Simulation time 20622373555 ps
CPU time 38.02 seconds
Started Apr 23 02:05:04 PM PDT 24
Finished Apr 23 02:05:42 PM PDT 24
Peak memory 200880 kb
Host smart-b1ac29e7-8ec8-42b5-b597-c3c5b7564e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121679793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3121679793
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2270422312
Short name T1076
Test name
Test status
Simulation time 44689653740 ps
CPU time 18.99 seconds
Started Apr 23 02:05:03 PM PDT 24
Finished Apr 23 02:05:22 PM PDT 24
Peak memory 200888 kb
Host smart-afedbde9-8a2b-4694-9e7c-72d019393777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270422312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2270422312
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2311019233
Short name T1005
Test name
Test status
Simulation time 25116612328 ps
CPU time 10.97 seconds
Started Apr 23 02:05:04 PM PDT 24
Finished Apr 23 02:05:16 PM PDT 24
Peak memory 199832 kb
Host smart-3cb81076-ddf1-44a6-9afa-c7074de522cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311019233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2311019233
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2952738698
Short name T903
Test name
Test status
Simulation time 12733768685 ps
CPU time 25.05 seconds
Started Apr 23 02:05:03 PM PDT 24
Finished Apr 23 02:05:28 PM PDT 24
Peak memory 200752 kb
Host smart-88490eef-8551-401d-8de7-7aa2a9afeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952738698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2952738698
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3306875195
Short name T177
Test name
Test status
Simulation time 187680578381 ps
CPU time 113.01 seconds
Started Apr 23 02:05:05 PM PDT 24
Finished Apr 23 02:06:59 PM PDT 24
Peak memory 200956 kb
Host smart-8b55e6a6-383d-4ad3-91d4-b5b1a9695e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306875195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3306875195
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.571044682
Short name T75
Test name
Test status
Simulation time 132294230712 ps
CPU time 117.93 seconds
Started Apr 23 02:05:06 PM PDT 24
Finished Apr 23 02:07:04 PM PDT 24
Peak memory 200720 kb
Host smart-a02a1a1f-de9a-4d70-804d-35e01d1d49bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571044682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.571044682
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2818236545
Short name T908
Test name
Test status
Simulation time 156089792446 ps
CPU time 67.03 seconds
Started Apr 23 02:05:05 PM PDT 24
Finished Apr 23 02:06:13 PM PDT 24
Peak memory 200792 kb
Host smart-0e7aae28-10f0-44f2-8a03-cdba3823c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818236545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2818236545
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1869370003
Short name T185
Test name
Test status
Simulation time 45679360757 ps
CPU time 37.7 seconds
Started Apr 23 02:05:06 PM PDT 24
Finished Apr 23 02:05:44 PM PDT 24
Peak memory 200784 kb
Host smart-8b7e053a-9803-4788-851b-07d834a5d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869370003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1869370003
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2216824340
Short name T439
Test name
Test status
Simulation time 33070420949 ps
CPU time 15.01 seconds
Started Apr 23 02:05:06 PM PDT 24
Finished Apr 23 02:05:22 PM PDT 24
Peak memory 200852 kb
Host smart-311ebf5c-63bc-4052-8dbd-4c9974649a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216824340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2216824340
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.708614844
Short name T610
Test name
Test status
Simulation time 20055849 ps
CPU time 0.55 seconds
Started Apr 23 01:59:12 PM PDT 24
Finished Apr 23 01:59:12 PM PDT 24
Peak memory 196120 kb
Host smart-2bf924d1-240e-4ec8-b7b6-3ad55680ca7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708614844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.708614844
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2117818788
Short name T180
Test name
Test status
Simulation time 169682778179 ps
CPU time 72.68 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 02:00:23 PM PDT 24
Peak memory 200880 kb
Host smart-32ee4b46-7574-4bc7-9416-4674e12e4fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117818788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2117818788
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.360010205
Short name T886
Test name
Test status
Simulation time 24525575517 ps
CPU time 14.34 seconds
Started Apr 23 01:59:09 PM PDT 24
Finished Apr 23 01:59:23 PM PDT 24
Peak memory 200676 kb
Host smart-35e4c79e-041b-467b-b63a-3a34d436e27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360010205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.360010205
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2146836161
Short name T770
Test name
Test status
Simulation time 54391133242 ps
CPU time 22.08 seconds
Started Apr 23 01:59:09 PM PDT 24
Finished Apr 23 01:59:32 PM PDT 24
Peak memory 200008 kb
Host smart-8e327373-cbb3-4bc0-be4e-35288baa42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146836161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2146836161
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.106436704
Short name T1124
Test name
Test status
Simulation time 11977513286 ps
CPU time 5.59 seconds
Started Apr 23 01:59:09 PM PDT 24
Finished Apr 23 01:59:15 PM PDT 24
Peak memory 199380 kb
Host smart-2de9ef2c-1aeb-4c0e-afe2-c181abb7148d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106436704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.106436704
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.444968109
Short name T1088
Test name
Test status
Simulation time 119560602771 ps
CPU time 247.02 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 02:03:17 PM PDT 24
Peak memory 200812 kb
Host smart-edcfad7e-f5ee-4d89-a93b-13e11b7d8744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444968109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.444968109
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.963376164
Short name T532
Test name
Test status
Simulation time 14790754638 ps
CPU time 24.21 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 01:59:35 PM PDT 24
Peak memory 198704 kb
Host smart-cf93f053-75c5-4fed-af30-cc59140a2a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963376164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.963376164
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.285217460
Short name T1043
Test name
Test status
Simulation time 91641723921 ps
CPU time 170.93 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 02:02:01 PM PDT 24
Peak memory 200624 kb
Host smart-164e0e6a-c06e-4236-b384-5282b0d0acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285217460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.285217460
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.19951548
Short name T734
Test name
Test status
Simulation time 6101050829 ps
CPU time 307.93 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 02:04:18 PM PDT 24
Peak memory 200804 kb
Host smart-f5c4494a-3ac3-4a9b-87b2-ba3538476fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19951548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.19951548
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.280167933
Short name T463
Test name
Test status
Simulation time 4410353436 ps
CPU time 18.8 seconds
Started Apr 23 01:59:11 PM PDT 24
Finished Apr 23 01:59:31 PM PDT 24
Peak memory 200204 kb
Host smart-ab4df11b-32ee-45de-a8ad-9995a40347ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280167933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.280167933
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2204264172
Short name T624
Test name
Test status
Simulation time 43776065097 ps
CPU time 53.51 seconds
Started Apr 23 01:59:12 PM PDT 24
Finished Apr 23 02:00:06 PM PDT 24
Peak memory 200804 kb
Host smart-ba185f34-86e3-4997-968f-dca4d837573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204264172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2204264172
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.736996932
Short name T506
Test name
Test status
Simulation time 4551027059 ps
CPU time 2.65 seconds
Started Apr 23 01:59:12 PM PDT 24
Finished Apr 23 01:59:15 PM PDT 24
Peak memory 196948 kb
Host smart-0078f217-0e1f-460b-a3e1-6b50bc4919dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736996932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.736996932
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3402377429
Short name T432
Test name
Test status
Simulation time 558728914 ps
CPU time 1.54 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 01:59:12 PM PDT 24
Peak memory 199188 kb
Host smart-9574696d-757c-4967-b1d7-c875a657432a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402377429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3402377429
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3015830986
Short name T768
Test name
Test status
Simulation time 347169199181 ps
CPU time 181.92 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 02:02:13 PM PDT 24
Peak memory 217004 kb
Host smart-bcb97583-9669-4c13-99f4-c7c8ae5ce7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015830986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3015830986
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.4125893895
Short name T718
Test name
Test status
Simulation time 168840978388 ps
CPU time 274.39 seconds
Started Apr 23 01:59:12 PM PDT 24
Finished Apr 23 02:03:47 PM PDT 24
Peak memory 217428 kb
Host smart-a2201333-bab1-4548-95d2-55b72b5e95f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125893895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.4125893895
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2795794060
Short name T978
Test name
Test status
Simulation time 722911307 ps
CPU time 3.18 seconds
Started Apr 23 01:59:10 PM PDT 24
Finished Apr 23 01:59:13 PM PDT 24
Peak memory 200532 kb
Host smart-ee10c02e-e49f-420c-9ff9-95a537f65575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795794060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2795794060
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3649464989
Short name T500
Test name
Test status
Simulation time 43138537864 ps
CPU time 70.71 seconds
Started Apr 23 01:59:09 PM PDT 24
Finished Apr 23 02:00:20 PM PDT 24
Peak memory 200724 kb
Host smart-f9aa436b-79bb-4b94-a943-375ab8f694d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649464989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3649464989
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3027407069
Short name T993
Test name
Test status
Simulation time 72568922970 ps
CPU time 51.06 seconds
Started Apr 23 02:05:08 PM PDT 24
Finished Apr 23 02:06:00 PM PDT 24
Peak memory 200912 kb
Host smart-bc8153cf-843e-462b-9703-72a1db34ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027407069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3027407069
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3957192530
Short name T746
Test name
Test status
Simulation time 109477355891 ps
CPU time 36.84 seconds
Started Apr 23 02:05:09 PM PDT 24
Finished Apr 23 02:05:46 PM PDT 24
Peak memory 200660 kb
Host smart-c937f0dc-7ae2-4673-89e3-3064a3f12b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957192530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3957192530
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3862648814
Short name T1160
Test name
Test status
Simulation time 142933046026 ps
CPU time 185.65 seconds
Started Apr 23 02:05:13 PM PDT 24
Finished Apr 23 02:08:19 PM PDT 24
Peak memory 200936 kb
Host smart-ffb8ad0a-1ff0-442f-9628-e112f0c71c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862648814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3862648814
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2694327636
Short name T336
Test name
Test status
Simulation time 19041969707 ps
CPU time 15.97 seconds
Started Apr 23 02:05:12 PM PDT 24
Finished Apr 23 02:05:28 PM PDT 24
Peak memory 200908 kb
Host smart-baac3e46-fe87-4bb6-bd83-9d108153580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694327636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2694327636
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2054890191
Short name T415
Test name
Test status
Simulation time 21827911594 ps
CPU time 22.88 seconds
Started Apr 23 02:05:14 PM PDT 24
Finished Apr 23 02:05:37 PM PDT 24
Peak memory 200820 kb
Host smart-950b8a46-a7ac-458b-88a5-0547ae76e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054890191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2054890191
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.177506176
Short name T202
Test name
Test status
Simulation time 77265500212 ps
CPU time 19.18 seconds
Started Apr 23 02:05:15 PM PDT 24
Finished Apr 23 02:05:35 PM PDT 24
Peak memory 200772 kb
Host smart-cd482fa9-ae4c-4124-884f-1ed70a8bd4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177506176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.177506176
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.4244580929
Short name T257
Test name
Test status
Simulation time 37876299312 ps
CPU time 26.68 seconds
Started Apr 23 02:05:14 PM PDT 24
Finished Apr 23 02:05:41 PM PDT 24
Peak memory 200568 kb
Host smart-e5930789-4f35-418d-bef1-eb334579d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244580929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.4244580929
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2719852297
Short name T825
Test name
Test status
Simulation time 65209227879 ps
CPU time 52.82 seconds
Started Apr 23 02:05:16 PM PDT 24
Finished Apr 23 02:06:09 PM PDT 24
Peak memory 200836 kb
Host smart-4d379864-1b42-4d2b-aabd-cad076f7656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719852297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2719852297
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.436848871
Short name T842
Test name
Test status
Simulation time 47185490 ps
CPU time 0.55 seconds
Started Apr 23 01:59:16 PM PDT 24
Finished Apr 23 01:59:17 PM PDT 24
Peak memory 196124 kb
Host smart-db156a03-481c-463a-89bb-beef9857fe36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436848871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.436848871
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2024053622
Short name T1003
Test name
Test status
Simulation time 229969205939 ps
CPU time 159.65 seconds
Started Apr 23 01:59:11 PM PDT 24
Finished Apr 23 02:01:51 PM PDT 24
Peak memory 200856 kb
Host smart-edc3679b-9254-4114-a7e4-64b51364d604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024053622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2024053622
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2981069173
Short name T144
Test name
Test status
Simulation time 26753223177 ps
CPU time 13.88 seconds
Started Apr 23 01:59:11 PM PDT 24
Finished Apr 23 01:59:26 PM PDT 24
Peak memory 200500 kb
Host smart-f83bf974-24dc-423a-89a5-98733db5e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981069173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2981069173
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3565134427
Short name T6
Test name
Test status
Simulation time 24748850549 ps
CPU time 21.13 seconds
Started Apr 23 01:59:12 PM PDT 24
Finished Apr 23 01:59:33 PM PDT 24
Peak memory 200844 kb
Host smart-4883cdcc-cf7a-47ba-8b42-ce5df54bdfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565134427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3565134427
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2035546076
Short name T291
Test name
Test status
Simulation time 468179805052 ps
CPU time 374.28 seconds
Started Apr 23 01:59:14 PM PDT 24
Finished Apr 23 02:05:28 PM PDT 24
Peak memory 200216 kb
Host smart-a9feecf4-61ca-40cc-ae44-1918faa30bc3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035546076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2035546076
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2278281174
Short name T854
Test name
Test status
Simulation time 87686915418 ps
CPU time 454.33 seconds
Started Apr 23 01:59:15 PM PDT 24
Finished Apr 23 02:06:50 PM PDT 24
Peak memory 200900 kb
Host smart-99090441-e864-4d51-88a6-e3c4d4610e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278281174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2278281174
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2506140237
Short name T534
Test name
Test status
Simulation time 9193688481 ps
CPU time 14.31 seconds
Started Apr 23 01:59:13 PM PDT 24
Finished Apr 23 01:59:28 PM PDT 24
Peak memory 200800 kb
Host smart-0e0cfffb-2806-4bbf-886e-59c4c1630d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506140237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2506140237
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3017171037
Short name T293
Test name
Test status
Simulation time 64828837943 ps
CPU time 38.94 seconds
Started Apr 23 01:59:13 PM PDT 24
Finished Apr 23 01:59:52 PM PDT 24
Peak memory 199924 kb
Host smart-c89d7def-ada6-4613-ac33-c602510010d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017171037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3017171037
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2340610832
Short name T537
Test name
Test status
Simulation time 13595647426 ps
CPU time 623.86 seconds
Started Apr 23 01:59:15 PM PDT 24
Finished Apr 23 02:09:40 PM PDT 24
Peak memory 200848 kb
Host smart-f4cdfa45-8ead-4fca-8e7f-f06a47c557d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340610832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2340610832
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2351595764
Short name T419
Test name
Test status
Simulation time 5387936496 ps
CPU time 12.74 seconds
Started Apr 23 01:59:15 PM PDT 24
Finished Apr 23 01:59:28 PM PDT 24
Peak memory 200048 kb
Host smart-2ee17577-50d6-4906-aa5a-edde445c9699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351595764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2351595764
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2217821779
Short name T1011
Test name
Test status
Simulation time 13172090421 ps
CPU time 12.17 seconds
Started Apr 23 01:59:14 PM PDT 24
Finished Apr 23 01:59:27 PM PDT 24
Peak memory 200832 kb
Host smart-02c1a65f-d335-4848-b72e-4b62bd40c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217821779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2217821779
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.547904846
Short name T809
Test name
Test status
Simulation time 1858933097 ps
CPU time 1.44 seconds
Started Apr 23 01:59:14 PM PDT 24
Finished Apr 23 01:59:15 PM PDT 24
Peak memory 196228 kb
Host smart-09a02872-fd45-4c31-adcb-e93d85c26044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547904846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.547904846
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2038656728
Short name T853
Test name
Test status
Simulation time 5474715453 ps
CPU time 16.22 seconds
Started Apr 23 01:59:11 PM PDT 24
Finished Apr 23 01:59:27 PM PDT 24
Peak memory 200640 kb
Host smart-b69901ee-668f-439b-b65f-7ff880f7be20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038656728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2038656728
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2341933080
Short name T895
Test name
Test status
Simulation time 90143880839 ps
CPU time 44 seconds
Started Apr 23 01:59:15 PM PDT 24
Finished Apr 23 02:00:00 PM PDT 24
Peak memory 200780 kb
Host smart-af10598b-ba3c-4311-8070-2846a06df9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341933080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2341933080
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3219070599
Short name T884
Test name
Test status
Simulation time 22891206407 ps
CPU time 361.12 seconds
Started Apr 23 01:59:16 PM PDT 24
Finished Apr 23 02:05:18 PM PDT 24
Peak memory 211696 kb
Host smart-13e0e2af-1b2a-45f2-8596-e2b9c099ae24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219070599 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3219070599
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3756553452
Short name T849
Test name
Test status
Simulation time 707899780 ps
CPU time 1.6 seconds
Started Apr 23 01:59:15 PM PDT 24
Finished Apr 23 01:59:17 PM PDT 24
Peak memory 199492 kb
Host smart-a2eddd8c-41c6-4be9-b27b-14eb52b5eba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756553452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3756553452
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4289051040
Short name T307
Test name
Test status
Simulation time 90439566695 ps
CPU time 13.15 seconds
Started Apr 23 01:59:09 PM PDT 24
Finished Apr 23 01:59:23 PM PDT 24
Peak memory 200812 kb
Host smart-79433ad0-7088-43ad-99a5-a0097537d81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289051040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4289051040
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3322533726
Short name T715
Test name
Test status
Simulation time 186346761212 ps
CPU time 413.02 seconds
Started Apr 23 02:05:16 PM PDT 24
Finished Apr 23 02:12:10 PM PDT 24
Peak memory 200808 kb
Host smart-7bbf8180-713d-4ace-82e6-326adcb7406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322533726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3322533726
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1414004074
Short name T798
Test name
Test status
Simulation time 166253596446 ps
CPU time 223.27 seconds
Started Apr 23 02:05:18 PM PDT 24
Finished Apr 23 02:09:02 PM PDT 24
Peak memory 200768 kb
Host smart-5710dd7f-7139-4e62-a939-b75ef305396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414004074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1414004074
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.4088632583
Short name T218
Test name
Test status
Simulation time 122086487869 ps
CPU time 72.29 seconds
Started Apr 23 02:05:19 PM PDT 24
Finished Apr 23 02:06:32 PM PDT 24
Peak memory 200836 kb
Host smart-d24f8576-8eb0-4832-8956-5653a18d2a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088632583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4088632583
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1929250765
Short name T785
Test name
Test status
Simulation time 38931423887 ps
CPU time 83.83 seconds
Started Apr 23 02:05:17 PM PDT 24
Finished Apr 23 02:06:42 PM PDT 24
Peak memory 200748 kb
Host smart-213b169d-18b6-44c2-a8f0-3f9a891af008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929250765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1929250765
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1852309271
Short name T1033
Test name
Test status
Simulation time 247697014838 ps
CPU time 97.16 seconds
Started Apr 23 02:05:20 PM PDT 24
Finished Apr 23 02:06:57 PM PDT 24
Peak memory 200864 kb
Host smart-97dd906f-1414-4b60-8a2a-f39546f3f631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852309271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1852309271
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1126677702
Short name T242
Test name
Test status
Simulation time 300630892096 ps
CPU time 141.51 seconds
Started Apr 23 02:05:22 PM PDT 24
Finished Apr 23 02:07:44 PM PDT 24
Peak memory 200864 kb
Host smart-1855d17e-d350-49b3-b4c8-eb5e657d6c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126677702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1126677702
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3240051334
Short name T808
Test name
Test status
Simulation time 96765443710 ps
CPU time 37.61 seconds
Started Apr 23 02:05:21 PM PDT 24
Finished Apr 23 02:05:59 PM PDT 24
Peak memory 200776 kb
Host smart-def10247-90b5-4621-916d-29f21e4b0c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240051334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3240051334
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.742223140
Short name T765
Test name
Test status
Simulation time 27793092 ps
CPU time 0.56 seconds
Started Apr 23 01:59:26 PM PDT 24
Finished Apr 23 01:59:27 PM PDT 24
Peak memory 195176 kb
Host smart-62d5415f-b346-46fd-94e0-dc70f9b843d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742223140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.742223140
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1284894980
Short name T813
Test name
Test status
Simulation time 24396610016 ps
CPU time 52.21 seconds
Started Apr 23 01:59:21 PM PDT 24
Finished Apr 23 02:00:14 PM PDT 24
Peak memory 200820 kb
Host smart-0453a2e8-63ba-4163-93d7-92151e805828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284894980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1284894980
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2886121639
Short name T719
Test name
Test status
Simulation time 9040594555 ps
CPU time 15.47 seconds
Started Apr 23 01:59:19 PM PDT 24
Finished Apr 23 01:59:35 PM PDT 24
Peak memory 200332 kb
Host smart-bc930549-0e1d-4caf-bba2-b69df1b62749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886121639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2886121639
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.992905177
Short name T1122
Test name
Test status
Simulation time 32059851093 ps
CPU time 27.82 seconds
Started Apr 23 01:59:20 PM PDT 24
Finished Apr 23 01:59:48 PM PDT 24
Peak memory 200860 kb
Host smart-0868b034-9c36-4b14-81f1-f395c0f8c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992905177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.992905177
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3744005058
Short name T586
Test name
Test status
Simulation time 26054328551 ps
CPU time 45.94 seconds
Started Apr 23 01:59:19 PM PDT 24
Finished Apr 23 02:00:05 PM PDT 24
Peak memory 200720 kb
Host smart-e797b882-493e-41d1-91d7-7c09341a23b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744005058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3744005058
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.685910642
Short name T714
Test name
Test status
Simulation time 153600952246 ps
CPU time 35.89 seconds
Started Apr 23 01:59:25 PM PDT 24
Finished Apr 23 02:00:01 PM PDT 24
Peak memory 200804 kb
Host smart-aeb2260a-5f97-410f-a4d2-39f0c5890b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685910642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.685910642
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3051337523
Short name T526
Test name
Test status
Simulation time 8920840180 ps
CPU time 9.77 seconds
Started Apr 23 01:59:22 PM PDT 24
Finished Apr 23 01:59:32 PM PDT 24
Peak memory 199900 kb
Host smart-1ba2207d-c776-424a-ad92-dab904e39450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051337523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3051337523
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3673061050
Short name T1037
Test name
Test status
Simulation time 13754918130 ps
CPU time 96.83 seconds
Started Apr 23 01:59:22 PM PDT 24
Finished Apr 23 02:01:00 PM PDT 24
Peak memory 200768 kb
Host smart-802e5fc1-7a63-498f-a53b-5beff7f9b17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673061050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3673061050
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.4098721475
Short name T479
Test name
Test status
Simulation time 2463680818 ps
CPU time 5.42 seconds
Started Apr 23 01:59:21 PM PDT 24
Finished Apr 23 01:59:26 PM PDT 24
Peak memory 198872 kb
Host smart-2f5c74b6-3106-44aa-ae2c-862d67bb475a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098721475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4098721475
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.124276228
Short name T1117
Test name
Test status
Simulation time 138307719285 ps
CPU time 63.36 seconds
Started Apr 23 01:59:20 PM PDT 24
Finished Apr 23 02:00:24 PM PDT 24
Peak memory 200820 kb
Host smart-434acd53-732f-496b-8466-f8d364e8bf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124276228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.124276228
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1718722270
Short name T388
Test name
Test status
Simulation time 2338788422 ps
CPU time 4.19 seconds
Started Apr 23 01:59:20 PM PDT 24
Finished Apr 23 01:59:24 PM PDT 24
Peak memory 196440 kb
Host smart-e7256592-07a3-419e-9800-4474ae5782c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718722270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1718722270
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.959042221
Short name T418
Test name
Test status
Simulation time 314864845 ps
CPU time 0.95 seconds
Started Apr 23 01:59:15 PM PDT 24
Finished Apr 23 01:59:16 PM PDT 24
Peak memory 199284 kb
Host smart-01655b3b-5056-41c7-8668-759723983b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959042221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.959042221
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2139616952
Short name T181
Test name
Test status
Simulation time 48270346177 ps
CPU time 1911.16 seconds
Started Apr 23 01:59:26 PM PDT 24
Finished Apr 23 02:31:18 PM PDT 24
Peak memory 200892 kb
Host smart-9db7529d-233b-49c8-aef8-75d576ed8ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139616952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2139616952
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.732358347
Short name T614
Test name
Test status
Simulation time 78308337111 ps
CPU time 205.07 seconds
Started Apr 23 01:59:23 PM PDT 24
Finished Apr 23 02:02:49 PM PDT 24
Peak memory 214052 kb
Host smart-a2e638c1-a80e-433d-9af9-5e00cfba3ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732358347 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.732358347
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3830127750
Short name T340
Test name
Test status
Simulation time 656910981 ps
CPU time 2.61 seconds
Started Apr 23 01:59:20 PM PDT 24
Finished Apr 23 01:59:23 PM PDT 24
Peak memory 200620 kb
Host smart-d2645fe6-2697-4997-b5e2-9c474d3997d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830127750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3830127750
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2370253155
Short name T801
Test name
Test status
Simulation time 10022417953 ps
CPU time 17.58 seconds
Started Apr 23 01:59:19 PM PDT 24
Finished Apr 23 01:59:37 PM PDT 24
Peak memory 200780 kb
Host smart-4e9e1f48-74ae-45d4-9bc5-2bef99dad76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370253155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2370253155
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.157273143
Short name T1165
Test name
Test status
Simulation time 75872601261 ps
CPU time 154.09 seconds
Started Apr 23 02:05:21 PM PDT 24
Finished Apr 23 02:07:56 PM PDT 24
Peak memory 200796 kb
Host smart-41e6bbc6-46c3-4861-9423-0b0065b1e578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157273143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.157273143
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2551720045
Short name T803
Test name
Test status
Simulation time 83442580382 ps
CPU time 111.87 seconds
Started Apr 23 02:05:25 PM PDT 24
Finished Apr 23 02:07:17 PM PDT 24
Peak memory 200848 kb
Host smart-c270765b-c152-4c17-beea-d98e8c0887e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551720045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2551720045
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2525562015
Short name T917
Test name
Test status
Simulation time 103983463395 ps
CPU time 96.43 seconds
Started Apr 23 02:05:23 PM PDT 24
Finished Apr 23 02:07:00 PM PDT 24
Peak memory 200808 kb
Host smart-e5f927d6-7068-4e2e-8359-d0013aeb3d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525562015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2525562015
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2044108986
Short name T420
Test name
Test status
Simulation time 16028492412 ps
CPU time 15.35 seconds
Started Apr 23 02:05:24 PM PDT 24
Finished Apr 23 02:05:40 PM PDT 24
Peak memory 200796 kb
Host smart-775567c9-c278-4bb6-a020-fb3774d9614b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044108986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2044108986
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.248714504
Short name T673
Test name
Test status
Simulation time 19454775707 ps
CPU time 22.64 seconds
Started Apr 23 02:05:26 PM PDT 24
Finished Apr 23 02:05:49 PM PDT 24
Peak memory 200824 kb
Host smart-755d9ae8-a51a-4a98-b169-a1730b614170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248714504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.248714504
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4126941537
Short name T1055
Test name
Test status
Simulation time 28285613877 ps
CPU time 14.36 seconds
Started Apr 23 02:05:30 PM PDT 24
Finished Apr 23 02:05:45 PM PDT 24
Peak memory 200796 kb
Host smart-a94bed09-5431-4501-a178-95f915928075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126941537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4126941537
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2526439498
Short name T243
Test name
Test status
Simulation time 19965770571 ps
CPU time 32.31 seconds
Started Apr 23 02:05:30 PM PDT 24
Finished Apr 23 02:06:03 PM PDT 24
Peak memory 200832 kb
Host smart-4d7c8c83-b5dc-417b-aeae-f281519dbdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526439498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2526439498
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.4256218397
Short name T386
Test name
Test status
Simulation time 22789484 ps
CPU time 0.61 seconds
Started Apr 23 01:58:21 PM PDT 24
Finished Apr 23 01:58:22 PM PDT 24
Peak memory 196220 kb
Host smart-e7680c67-5eaf-42ea-b8ee-1f363ebe110f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256218397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.4256218397
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.780301171
Short name T438
Test name
Test status
Simulation time 85813234378 ps
CPU time 39.02 seconds
Started Apr 23 01:58:17 PM PDT 24
Finished Apr 23 01:58:57 PM PDT 24
Peak memory 200824 kb
Host smart-67ac06d9-6915-44e2-8d04-3cf760206ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780301171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.780301171
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.4142187436
Short name T528
Test name
Test status
Simulation time 73663351070 ps
CPU time 128.46 seconds
Started Apr 23 01:58:16 PM PDT 24
Finished Apr 23 02:00:25 PM PDT 24
Peak memory 200776 kb
Host smart-31bd326a-157a-470d-bd3d-c3fc2ab9c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142187436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.4142187436
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.20767061
Short name T204
Test name
Test status
Simulation time 124555688954 ps
CPU time 40.65 seconds
Started Apr 23 01:58:17 PM PDT 24
Finished Apr 23 01:58:58 PM PDT 24
Peak memory 200848 kb
Host smart-26294ff0-6c26-4bff-8bb7-991d6bdbf066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20767061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.20767061
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3039958135
Short name T627
Test name
Test status
Simulation time 373244696137 ps
CPU time 162.49 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 02:01:01 PM PDT 24
Peak memory 198736 kb
Host smart-0f163602-6e4d-42b6-9173-0cdcf5cc70eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039958135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3039958135
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1579289884
Short name T350
Test name
Test status
Simulation time 139717941329 ps
CPU time 1143.95 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 02:17:23 PM PDT 24
Peak memory 200808 kb
Host smart-88648862-0a96-4b74-bc07-a9d81ad4a2df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579289884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1579289884
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3154567274
Short name T10
Test name
Test status
Simulation time 5558430084 ps
CPU time 10.37 seconds
Started Apr 23 01:58:17 PM PDT 24
Finished Apr 23 01:58:27 PM PDT 24
Peak memory 199696 kb
Host smart-cfb722ea-4926-42a1-902f-21d6f0c0d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154567274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3154567274
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2606844115
Short name T1152
Test name
Test status
Simulation time 96966064653 ps
CPU time 164.07 seconds
Started Apr 23 01:58:16 PM PDT 24
Finished Apr 23 02:01:01 PM PDT 24
Peak memory 200504 kb
Host smart-12bc9c8e-164a-4eaf-9c97-9f6fa47c8d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606844115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2606844115
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3313037293
Short name T619
Test name
Test status
Simulation time 19411817131 ps
CPU time 889.58 seconds
Started Apr 23 01:58:19 PM PDT 24
Finished Apr 23 02:13:09 PM PDT 24
Peak memory 200940 kb
Host smart-1a76908c-9482-4d4e-ac4e-0483df6fecb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313037293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3313037293
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2013946813
Short name T1049
Test name
Test status
Simulation time 1815697449 ps
CPU time 2.74 seconds
Started Apr 23 01:58:15 PM PDT 24
Finished Apr 23 01:58:18 PM PDT 24
Peak memory 199376 kb
Host smart-bf6978ce-65c5-4dbd-be32-ff9f3ca4d0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013946813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2013946813
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.773457947
Short name T700
Test name
Test status
Simulation time 2809162316 ps
CPU time 1.73 seconds
Started Apr 23 01:58:16 PM PDT 24
Finished Apr 23 01:58:18 PM PDT 24
Peak memory 196592 kb
Host smart-28c2f240-382e-4737-8e54-d3f196722843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773457947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.773457947
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3506843085
Short name T28
Test name
Test status
Simulation time 67912448 ps
CPU time 0.83 seconds
Started Apr 23 01:58:20 PM PDT 24
Finished Apr 23 01:58:22 PM PDT 24
Peak memory 219060 kb
Host smart-4d13e992-ac52-46ab-a7a4-11ab718e92a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506843085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3506843085
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.689253067
Short name T484
Test name
Test status
Simulation time 6173583390 ps
CPU time 8.18 seconds
Started Apr 23 01:58:14 PM PDT 24
Finished Apr 23 01:58:23 PM PDT 24
Peak memory 200092 kb
Host smart-3a3068f0-15d3-4e92-913e-cf063f1e5d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689253067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.689253067
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2056331967
Short name T946
Test name
Test status
Simulation time 100060692174 ps
CPU time 43.24 seconds
Started Apr 23 01:58:16 PM PDT 24
Finished Apr 23 01:59:00 PM PDT 24
Peak memory 200764 kb
Host smart-6993883f-17b6-4071-a3f6-be65d25d4306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056331967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2056331967
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.4068737813
Short name T62
Test name
Test status
Simulation time 500451598030 ps
CPU time 1303.57 seconds
Started Apr 23 01:58:17 PM PDT 24
Finished Apr 23 02:20:01 PM PDT 24
Peak memory 217292 kb
Host smart-acb3a838-cd00-465f-927a-81aa1a94aa0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068737813 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.4068737813
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.788257612
Short name T302
Test name
Test status
Simulation time 6490857193 ps
CPU time 30.12 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 01:58:49 PM PDT 24
Peak memory 200728 kb
Host smart-30737169-cff6-4113-afb1-55d0c14969fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788257612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.788257612
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1970635148
Short name T836
Test name
Test status
Simulation time 12729562064 ps
CPU time 19.06 seconds
Started Apr 23 01:58:16 PM PDT 24
Finished Apr 23 01:58:35 PM PDT 24
Peak memory 200796 kb
Host smart-7e460406-28ee-4800-823b-4e560e03e204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970635148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1970635148
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.439221624
Short name T1178
Test name
Test status
Simulation time 18366575 ps
CPU time 0.53 seconds
Started Apr 23 01:59:28 PM PDT 24
Finished Apr 23 01:59:29 PM PDT 24
Peak memory 196192 kb
Host smart-7de1cedf-dd62-43b5-856a-e52a73a5933b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439221624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.439221624
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3621252975
Short name T132
Test name
Test status
Simulation time 16734741701 ps
CPU time 12.3 seconds
Started Apr 23 01:59:27 PM PDT 24
Finished Apr 23 01:59:40 PM PDT 24
Peak memory 200808 kb
Host smart-bc66d2ee-5a1a-486f-af72-27f8323a3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621252975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3621252975
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1812973256
Short name T670
Test name
Test status
Simulation time 17284193473 ps
CPU time 29.42 seconds
Started Apr 23 01:59:29 PM PDT 24
Finished Apr 23 01:59:59 PM PDT 24
Peak memory 200716 kb
Host smart-335c82d7-56e4-4f4a-b953-d2e6407306c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812973256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1812973256
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.633518045
Short name T266
Test name
Test status
Simulation time 22648425839 ps
CPU time 8.11 seconds
Started Apr 23 01:59:26 PM PDT 24
Finished Apr 23 01:59:34 PM PDT 24
Peak memory 200808 kb
Host smart-3470e4bd-5b9f-4d2b-8201-76edc003ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633518045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.633518045
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.356825414
Short name T74
Test name
Test status
Simulation time 17515576007 ps
CPU time 31.39 seconds
Started Apr 23 01:59:29 PM PDT 24
Finished Apr 23 02:00:01 PM PDT 24
Peak memory 198580 kb
Host smart-cc69d1b4-de22-4656-a41f-4d7e08a1bef2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356825414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.356825414
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1668382757
Short name T303
Test name
Test status
Simulation time 182164121052 ps
CPU time 377.35 seconds
Started Apr 23 01:59:24 PM PDT 24
Finished Apr 23 02:05:42 PM PDT 24
Peak memory 200816 kb
Host smart-ca7581a0-4721-48f9-ad18-27f2ea30ed78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668382757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1668382757
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1544398125
Short name T691
Test name
Test status
Simulation time 3734183327 ps
CPU time 3.76 seconds
Started Apr 23 01:59:26 PM PDT 24
Finished Apr 23 01:59:30 PM PDT 24
Peak memory 199920 kb
Host smart-8a468e05-bd09-494e-bfd2-152f6258d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544398125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1544398125
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.265052317
Short name T1121
Test name
Test status
Simulation time 157690769118 ps
CPU time 60.36 seconds
Started Apr 23 01:59:26 PM PDT 24
Finished Apr 23 02:00:27 PM PDT 24
Peak memory 200540 kb
Host smart-e514a7f9-9fa9-4460-86f2-aed42e9a7031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265052317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.265052317
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.44666936
Short name T498
Test name
Test status
Simulation time 15137478044 ps
CPU time 816.42 seconds
Started Apr 23 01:59:28 PM PDT 24
Finished Apr 23 02:13:05 PM PDT 24
Peak memory 200832 kb
Host smart-fa193bc5-c411-4c21-939f-6fa71ec84fa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44666936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.44666936
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1379389262
Short name T938
Test name
Test status
Simulation time 3980125794 ps
CPU time 30.56 seconds
Started Apr 23 01:59:25 PM PDT 24
Finished Apr 23 01:59:56 PM PDT 24
Peak memory 199080 kb
Host smart-fb3812f7-80ce-4753-b002-6d2aa22986e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379389262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1379389262
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.4052441012
Short name T979
Test name
Test status
Simulation time 146282309382 ps
CPU time 60.5 seconds
Started Apr 23 01:59:28 PM PDT 24
Finished Apr 23 02:00:29 PM PDT 24
Peak memory 200828 kb
Host smart-db06d559-1ccf-41d6-a0c2-3e9ca8f24f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052441012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4052441012
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2980225713
Short name T515
Test name
Test status
Simulation time 5017280268 ps
CPU time 1.47 seconds
Started Apr 23 01:59:25 PM PDT 24
Finished Apr 23 01:59:27 PM PDT 24
Peak memory 196780 kb
Host smart-d7d15b78-4bcf-447a-b3da-1197599026f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980225713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2980225713
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1234637808
Short name T507
Test name
Test status
Simulation time 268226010 ps
CPU time 1.25 seconds
Started Apr 23 01:59:26 PM PDT 24
Finished Apr 23 01:59:28 PM PDT 24
Peak memory 199348 kb
Host smart-4921ca9e-60fc-4c30-8c87-4b3a9f1e21ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234637808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1234637808
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1199633027
Short name T755
Test name
Test status
Simulation time 139985688730 ps
CPU time 765.21 seconds
Started Apr 23 01:59:29 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 201128 kb
Host smart-b9121e48-2c93-4ac6-af04-f0907d8c1fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199633027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1199633027
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2356617837
Short name T1087
Test name
Test status
Simulation time 16036270855 ps
CPU time 137.98 seconds
Started Apr 23 01:59:30 PM PDT 24
Finished Apr 23 02:01:48 PM PDT 24
Peak memory 216164 kb
Host smart-697e6eb0-b6c5-4262-a1b9-346cdc58a697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356617837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2356617837
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.4017979956
Short name T1171
Test name
Test status
Simulation time 505169593 ps
CPU time 2.42 seconds
Started Apr 23 01:59:29 PM PDT 24
Finished Apr 23 01:59:32 PM PDT 24
Peak memory 199276 kb
Host smart-5232b59e-fce4-4518-9e54-5f911d9fb0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017979956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4017979956
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.425853880
Short name T275
Test name
Test status
Simulation time 98233451178 ps
CPU time 58.31 seconds
Started Apr 23 01:59:28 PM PDT 24
Finished Apr 23 02:00:27 PM PDT 24
Peak memory 200900 kb
Host smart-92f18cb9-6c26-4415-b9f5-57f8a5dda286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425853880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.425853880
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3163348686
Short name T925
Test name
Test status
Simulation time 133561846737 ps
CPU time 49.44 seconds
Started Apr 23 02:05:30 PM PDT 24
Finished Apr 23 02:06:20 PM PDT 24
Peak memory 200832 kb
Host smart-56b5d728-b79f-4bf9-b4e8-8390de2cfe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163348686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3163348686
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.568246402
Short name T1103
Test name
Test status
Simulation time 46333599282 ps
CPU time 42.52 seconds
Started Apr 23 02:05:31 PM PDT 24
Finished Apr 23 02:06:13 PM PDT 24
Peak memory 200788 kb
Host smart-dac5a21c-a0bd-4c7e-aace-6078f3ea7e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568246402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.568246402
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2884993400
Short name T971
Test name
Test status
Simulation time 11243829012 ps
CPU time 22.03 seconds
Started Apr 23 02:05:33 PM PDT 24
Finished Apr 23 02:05:56 PM PDT 24
Peak memory 200840 kb
Host smart-a8d4f135-0fb9-42d3-a9b1-d811db2ac8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884993400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2884993400
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.466683591
Short name T667
Test name
Test status
Simulation time 91087728367 ps
CPU time 45.61 seconds
Started Apr 23 02:05:34 PM PDT 24
Finished Apr 23 02:06:20 PM PDT 24
Peak memory 200824 kb
Host smart-9005ef69-b48b-4963-8ad6-f892571c4193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466683591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.466683591
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1796358127
Short name T725
Test name
Test status
Simulation time 17754477154 ps
CPU time 26.27 seconds
Started Apr 23 02:05:37 PM PDT 24
Finished Apr 23 02:06:03 PM PDT 24
Peak memory 200880 kb
Host smart-07d57834-6d39-49ec-af98-86ea439fca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796358127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1796358127
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1329811811
Short name T294
Test name
Test status
Simulation time 93649431719 ps
CPU time 233.49 seconds
Started Apr 23 02:05:35 PM PDT 24
Finished Apr 23 02:09:29 PM PDT 24
Peak memory 200868 kb
Host smart-cad1f229-b941-4c87-9493-e131e82d74f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329811811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1329811811
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3506740765
Short name T223
Test name
Test status
Simulation time 42043741216 ps
CPU time 72.77 seconds
Started Apr 23 02:05:36 PM PDT 24
Finished Apr 23 02:06:49 PM PDT 24
Peak memory 200812 kb
Host smart-2e777781-cd17-4095-83f8-719ff439921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506740765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3506740765
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1876346232
Short name T914
Test name
Test status
Simulation time 128512915925 ps
CPU time 211.95 seconds
Started Apr 23 02:05:43 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 200816 kb
Host smart-c69d02c5-1163-4337-af5d-38d808bcc7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876346232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1876346232
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2696781467
Short name T968
Test name
Test status
Simulation time 24849075519 ps
CPU time 44.91 seconds
Started Apr 23 02:05:39 PM PDT 24
Finished Apr 23 02:06:25 PM PDT 24
Peak memory 200740 kb
Host smart-1198fb99-cdaf-43e3-bd18-929fe3e143e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696781467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2696781467
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3576010544
Short name T561
Test name
Test status
Simulation time 166656202 ps
CPU time 0.56 seconds
Started Apr 23 01:59:36 PM PDT 24
Finished Apr 23 01:59:37 PM PDT 24
Peak memory 196232 kb
Host smart-c71ad392-40fe-4b1a-ac40-160da2747e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576010544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3576010544
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2700984592
Short name T848
Test name
Test status
Simulation time 84308561127 ps
CPU time 129.99 seconds
Started Apr 23 01:59:29 PM PDT 24
Finished Apr 23 02:01:39 PM PDT 24
Peak memory 200812 kb
Host smart-506a8243-0d46-49c1-94a1-4f3eefa39fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700984592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2700984592
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2592973917
Short name T800
Test name
Test status
Simulation time 142889321630 ps
CPU time 241.39 seconds
Started Apr 23 01:59:28 PM PDT 24
Finished Apr 23 02:03:30 PM PDT 24
Peak memory 200928 kb
Host smart-74e2fcbf-632e-4b70-9c95-25e65c5110e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592973917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2592973917
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2093339397
Short name T284
Test name
Test status
Simulation time 91642549427 ps
CPU time 20.08 seconds
Started Apr 23 01:59:28 PM PDT 24
Finished Apr 23 01:59:48 PM PDT 24
Peak memory 200832 kb
Host smart-78726dfe-4109-46db-b2d8-e66abc68b149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093339397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2093339397
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1404510253
Short name T816
Test name
Test status
Simulation time 58544801521 ps
CPU time 27.77 seconds
Started Apr 23 01:59:31 PM PDT 24
Finished Apr 23 02:00:00 PM PDT 24
Peak memory 200828 kb
Host smart-7fea6487-456f-4a43-af1b-b22434570b79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404510253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1404510253
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3500315414
Short name T516
Test name
Test status
Simulation time 199698547344 ps
CPU time 151.55 seconds
Started Apr 23 01:59:34 PM PDT 24
Finished Apr 23 02:02:06 PM PDT 24
Peak memory 200716 kb
Host smart-6d9719de-0ddf-465f-81c7-df0e1e9a7f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500315414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3500315414
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2657208150
Short name T374
Test name
Test status
Simulation time 10359436779 ps
CPU time 10.94 seconds
Started Apr 23 01:59:31 PM PDT 24
Finished Apr 23 01:59:42 PM PDT 24
Peak memory 200588 kb
Host smart-41c2c9ed-f51d-4be4-885d-33b38972d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657208150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2657208150
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1617921027
Short name T863
Test name
Test status
Simulation time 57185956638 ps
CPU time 38.77 seconds
Started Apr 23 01:59:31 PM PDT 24
Finished Apr 23 02:00:11 PM PDT 24
Peak memory 200460 kb
Host smart-2d250bfc-76db-4a20-ad98-2010ba1c680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617921027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1617921027
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1829201726
Short name T1104
Test name
Test status
Simulation time 6829039420 ps
CPU time 64.08 seconds
Started Apr 23 01:59:36 PM PDT 24
Finished Apr 23 02:00:41 PM PDT 24
Peak memory 200848 kb
Host smart-9884de92-f550-420e-a82d-bb0f01745915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829201726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1829201726
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3705753275
Short name T385
Test name
Test status
Simulation time 5101567603 ps
CPU time 46.02 seconds
Started Apr 23 01:59:31 PM PDT 24
Finished Apr 23 02:00:18 PM PDT 24
Peak memory 198788 kb
Host smart-d3f64987-c730-4170-975c-e379e50b1fe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705753275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3705753275
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.255192246
Short name T133
Test name
Test status
Simulation time 50575208557 ps
CPU time 91.74 seconds
Started Apr 23 01:59:31 PM PDT 24
Finished Apr 23 02:01:03 PM PDT 24
Peak memory 200780 kb
Host smart-f3a01953-cb26-496a-9bc5-8ff37ba37084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255192246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.255192246
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2883152169
Short name T1081
Test name
Test status
Simulation time 1358414179 ps
CPU time 2.81 seconds
Started Apr 23 01:59:32 PM PDT 24
Finished Apr 23 01:59:35 PM PDT 24
Peak memory 196268 kb
Host smart-eeb94951-45be-4e55-8892-5a96f07bc912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883152169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2883152169
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1386293692
Short name T625
Test name
Test status
Simulation time 5688639266 ps
CPU time 10.88 seconds
Started Apr 23 01:59:27 PM PDT 24
Finished Apr 23 01:59:39 PM PDT 24
Peak memory 199992 kb
Host smart-8eef0f36-909f-48d2-b4fa-9be03bfc042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386293692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1386293692
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.599608669
Short name T658
Test name
Test status
Simulation time 271243289497 ps
CPU time 451.14 seconds
Started Apr 23 01:59:36 PM PDT 24
Finished Apr 23 02:07:07 PM PDT 24
Peak memory 200788 kb
Host smart-a7bb2bcf-a12b-439e-b7ff-8a4a39f0ca64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599608669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.599608669
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1198209356
Short name T483
Test name
Test status
Simulation time 4309901241 ps
CPU time 1.72 seconds
Started Apr 23 01:59:32 PM PDT 24
Finished Apr 23 01:59:34 PM PDT 24
Peak memory 199688 kb
Host smart-aecb1654-49b8-46dd-abeb-7ce4bde0b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198209356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1198209356
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2047437472
Short name T277
Test name
Test status
Simulation time 49603266819 ps
CPU time 88.03 seconds
Started Apr 23 01:59:29 PM PDT 24
Finished Apr 23 02:00:58 PM PDT 24
Peak memory 200824 kb
Host smart-4e7fa925-2a70-4d22-a649-a0c384e68020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047437472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2047437472
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3661062238
Short name T1084
Test name
Test status
Simulation time 121417742642 ps
CPU time 49.58 seconds
Started Apr 23 02:05:38 PM PDT 24
Finished Apr 23 02:06:28 PM PDT 24
Peak memory 200580 kb
Host smart-b4142eaa-6159-4ebe-8d3a-454d36fbd1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661062238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3661062238
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.150242260
Short name T867
Test name
Test status
Simulation time 19270374418 ps
CPU time 30.34 seconds
Started Apr 23 02:05:42 PM PDT 24
Finished Apr 23 02:06:13 PM PDT 24
Peak memory 200616 kb
Host smart-15c39a15-c73a-4c56-8832-b917ca0d657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150242260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.150242260
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1015692213
Short name T36
Test name
Test status
Simulation time 67784237422 ps
CPU time 146.61 seconds
Started Apr 23 02:05:42 PM PDT 24
Finished Apr 23 02:08:09 PM PDT 24
Peak memory 200856 kb
Host smart-68041f77-9fa6-44c8-8f5f-e1eb8809d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015692213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1015692213
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1829804270
Short name T964
Test name
Test status
Simulation time 38074034336 ps
CPU time 38.77 seconds
Started Apr 23 02:05:43 PM PDT 24
Finished Apr 23 02:06:22 PM PDT 24
Peak memory 200844 kb
Host smart-fa9c025b-e427-4d2b-a31d-aac56403dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829804270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1829804270
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2156848618
Short name T1131
Test name
Test status
Simulation time 69915070552 ps
CPU time 61.67 seconds
Started Apr 23 02:05:42 PM PDT 24
Finished Apr 23 02:06:44 PM PDT 24
Peak memory 200848 kb
Host smart-800f0cc0-a283-4d90-b3e1-0f312ff9cddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156848618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2156848618
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1628515857
Short name T569
Test name
Test status
Simulation time 113971794645 ps
CPU time 50.32 seconds
Started Apr 23 02:05:44 PM PDT 24
Finished Apr 23 02:06:34 PM PDT 24
Peak memory 200728 kb
Host smart-8966a8dd-16c2-4fe1-ae79-175f52ed2d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628515857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1628515857
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2041079369
Short name T747
Test name
Test status
Simulation time 15963373139 ps
CPU time 48.72 seconds
Started Apr 23 02:05:45 PM PDT 24
Finished Apr 23 02:06:34 PM PDT 24
Peak memory 200904 kb
Host smart-b5f23ed0-b80e-4e6a-943d-22968465fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041079369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2041079369
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1816260993
Short name T349
Test name
Test status
Simulation time 56337073 ps
CPU time 0.58 seconds
Started Apr 23 01:59:42 PM PDT 24
Finished Apr 23 01:59:43 PM PDT 24
Peak memory 196196 kb
Host smart-be96d0d2-6f85-47d3-95e4-d53b24ff0333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816260993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1816260993
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1044249474
Short name T135
Test name
Test status
Simulation time 149841368964 ps
CPU time 168.53 seconds
Started Apr 23 01:59:37 PM PDT 24
Finished Apr 23 02:02:26 PM PDT 24
Peak memory 200760 kb
Host smart-fce9bebd-a838-4db1-be82-2bee71b795f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044249474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1044249474
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.234097778
Short name T991
Test name
Test status
Simulation time 217854910268 ps
CPU time 28.67 seconds
Started Apr 23 01:59:37 PM PDT 24
Finished Apr 23 02:00:06 PM PDT 24
Peak memory 200756 kb
Host smart-954b5517-8798-4fa6-9ee5-73180aa93f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234097778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.234097778
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1681610767
Short name T998
Test name
Test status
Simulation time 83146561358 ps
CPU time 332.31 seconds
Started Apr 23 01:59:38 PM PDT 24
Finished Apr 23 02:05:10 PM PDT 24
Peak memory 200796 kb
Host smart-97b341ac-0c84-49f4-95ab-5b8f4ceac96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681610767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1681610767
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.219338679
Short name T924
Test name
Test status
Simulation time 67004216007 ps
CPU time 99.49 seconds
Started Apr 23 01:59:40 PM PDT 24
Finished Apr 23 02:01:20 PM PDT 24
Peak memory 200820 kb
Host smart-03f974d9-0f17-4bf7-999a-0f31924ba744
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219338679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.219338679
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1670672894
Short name T875
Test name
Test status
Simulation time 95785481832 ps
CPU time 911.8 seconds
Started Apr 23 01:59:40 PM PDT 24
Finished Apr 23 02:14:53 PM PDT 24
Peak memory 200844 kb
Host smart-6cc411cd-ede5-42aa-8331-be67f5e1b652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670672894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1670672894
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.4245454292
Short name T371
Test name
Test status
Simulation time 7245117969 ps
CPU time 12.6 seconds
Started Apr 23 01:59:43 PM PDT 24
Finished Apr 23 01:59:56 PM PDT 24
Peak memory 199248 kb
Host smart-973ba4e6-52ea-422b-8d7d-7a97d04c3a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245454292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.4245454292
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.4485816
Short name T1042
Test name
Test status
Simulation time 17926239010 ps
CPU time 17.44 seconds
Started Apr 23 01:59:38 PM PDT 24
Finished Apr 23 01:59:56 PM PDT 24
Peak memory 196884 kb
Host smart-65a87a9e-9798-4a80-be81-c7327dc5a80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4485816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.4485816
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1801980139
Short name T1108
Test name
Test status
Simulation time 14108001342 ps
CPU time 795.75 seconds
Started Apr 23 01:59:40 PM PDT 24
Finished Apr 23 02:12:56 PM PDT 24
Peak memory 200808 kb
Host smart-065ae3c0-a1a7-490d-a425-0a95ff454654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801980139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1801980139
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1474834680
Short name T834
Test name
Test status
Simulation time 3774184221 ps
CPU time 32.82 seconds
Started Apr 23 01:59:37 PM PDT 24
Finished Apr 23 02:00:10 PM PDT 24
Peak memory 198944 kb
Host smart-4ca2e192-15db-4e3a-82fa-cfa63216f77f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474834680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1474834680
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3701075573
Short name T762
Test name
Test status
Simulation time 293714041833 ps
CPU time 118.47 seconds
Started Apr 23 01:59:42 PM PDT 24
Finished Apr 23 02:01:40 PM PDT 24
Peak memory 200832 kb
Host smart-cfd777e1-f378-4865-b76d-fffb78a9b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701075573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3701075573
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1097950372
Short name T1068
Test name
Test status
Simulation time 41735371114 ps
CPU time 69.24 seconds
Started Apr 23 01:59:36 PM PDT 24
Finished Apr 23 02:00:46 PM PDT 24
Peak memory 196700 kb
Host smart-ed136c11-4259-4a6e-a2d6-54cff5f6fbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097950372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1097950372
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.693792471
Short name T553
Test name
Test status
Simulation time 627293554 ps
CPU time 2.38 seconds
Started Apr 23 01:59:36 PM PDT 24
Finished Apr 23 01:59:39 PM PDT 24
Peak memory 200296 kb
Host smart-76f74cdd-d353-408b-8eca-0a760fe4f852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693792471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.693792471
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.89035985
Short name T1092
Test name
Test status
Simulation time 134489397407 ps
CPU time 300.52 seconds
Started Apr 23 01:59:42 PM PDT 24
Finished Apr 23 02:04:43 PM PDT 24
Peak memory 200768 kb
Host smart-c47cc308-28e7-4608-94a3-ffc563638e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89035985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.89035985
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1609459394
Short name T316
Test name
Test status
Simulation time 45522153450 ps
CPU time 218.68 seconds
Started Apr 23 01:59:41 PM PDT 24
Finished Apr 23 02:03:20 PM PDT 24
Peak memory 216376 kb
Host smart-fe092e78-d337-4021-a703-4805beb9c813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609459394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1609459394
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3180761309
Short name T576
Test name
Test status
Simulation time 489076330 ps
CPU time 1.45 seconds
Started Apr 23 01:59:42 PM PDT 24
Finished Apr 23 01:59:44 PM PDT 24
Peak memory 198604 kb
Host smart-ac6d0640-2abf-4950-bfeb-02b148f8c887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180761309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3180761309
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1079122277
Short name T513
Test name
Test status
Simulation time 33655406295 ps
CPU time 16.66 seconds
Started Apr 23 01:59:36 PM PDT 24
Finished Apr 23 01:59:54 PM PDT 24
Peak memory 200748 kb
Host smart-7b7dce95-1483-4eb1-a084-fbbe616a4c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079122277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1079122277
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2814747495
Short name T1047
Test name
Test status
Simulation time 74676575717 ps
CPU time 115.17 seconds
Started Apr 23 02:05:47 PM PDT 24
Finished Apr 23 02:07:43 PM PDT 24
Peak memory 200752 kb
Host smart-379dba54-e412-4c23-b25a-61297f80abd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814747495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2814747495
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1246300436
Short name T994
Test name
Test status
Simulation time 33227637043 ps
CPU time 16.46 seconds
Started Apr 23 02:05:47 PM PDT 24
Finished Apr 23 02:06:04 PM PDT 24
Peak memory 200812 kb
Host smart-377779ad-b420-4fdc-8cbc-93b674ead5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246300436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1246300436
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3447399277
Short name T579
Test name
Test status
Simulation time 41418782822 ps
CPU time 14.88 seconds
Started Apr 23 02:05:48 PM PDT 24
Finished Apr 23 02:06:03 PM PDT 24
Peak memory 200448 kb
Host smart-9930f49a-684a-4a71-9a8c-7ba853e4dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447399277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3447399277
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1718901213
Short name T186
Test name
Test status
Simulation time 86879094446 ps
CPU time 23 seconds
Started Apr 23 02:05:49 PM PDT 24
Finished Apr 23 02:06:12 PM PDT 24
Peak memory 200808 kb
Host smart-317454ee-8eef-4a50-b744-263a226965e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718901213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1718901213
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.590002319
Short name T461
Test name
Test status
Simulation time 126502633413 ps
CPU time 604.76 seconds
Started Apr 23 02:05:52 PM PDT 24
Finished Apr 23 02:15:57 PM PDT 24
Peak memory 200724 kb
Host smart-23697a33-5cbb-4812-9396-70c221376e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590002319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.590002319
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2764405653
Short name T929
Test name
Test status
Simulation time 193719668473 ps
CPU time 44.31 seconds
Started Apr 23 02:05:56 PM PDT 24
Finished Apr 23 02:06:41 PM PDT 24
Peak memory 200868 kb
Host smart-a6298c80-d13c-4af0-9c25-e462bacae7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764405653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2764405653
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1176373478
Short name T604
Test name
Test status
Simulation time 10535217809 ps
CPU time 23.03 seconds
Started Apr 23 02:05:52 PM PDT 24
Finished Apr 23 02:06:16 PM PDT 24
Peak memory 200712 kb
Host smart-6555689d-ede9-4299-8b74-31be40e5893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176373478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1176373478
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3647074452
Short name T1059
Test name
Test status
Simulation time 23708379106 ps
CPU time 42.64 seconds
Started Apr 23 02:05:52 PM PDT 24
Finished Apr 23 02:06:35 PM PDT 24
Peak memory 200740 kb
Host smart-6a133793-8bf9-4abc-bb12-d26c22b38bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647074452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3647074452
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1297087410
Short name T1142
Test name
Test status
Simulation time 153359867147 ps
CPU time 112.04 seconds
Started Apr 23 02:05:50 PM PDT 24
Finished Apr 23 02:07:43 PM PDT 24
Peak memory 200812 kb
Host smart-1f5fa8ed-bae6-40c1-a3ec-bf4f02c25f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297087410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1297087410
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3350944241
Short name T797
Test name
Test status
Simulation time 46336959 ps
CPU time 0.55 seconds
Started Apr 23 01:59:49 PM PDT 24
Finished Apr 23 01:59:50 PM PDT 24
Peak memory 195608 kb
Host smart-35098e52-33ea-4791-93b7-7f783f1d180b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350944241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3350944241
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2522017365
Short name T1127
Test name
Test status
Simulation time 135833629740 ps
CPU time 192.96 seconds
Started Apr 23 01:59:44 PM PDT 24
Finished Apr 23 02:02:57 PM PDT 24
Peak memory 200896 kb
Host smart-dac98f4c-3c7a-4bd1-a351-83fa8ca0715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522017365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2522017365
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4170454818
Short name T318
Test name
Test status
Simulation time 71112103073 ps
CPU time 122.68 seconds
Started Apr 23 01:59:42 PM PDT 24
Finished Apr 23 02:01:45 PM PDT 24
Peak memory 200740 kb
Host smart-ceacb4ab-ce80-4c19-8271-ad630c1fcd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170454818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4170454818
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1048053148
Short name T680
Test name
Test status
Simulation time 39879502342 ps
CPU time 45.82 seconds
Started Apr 23 01:59:43 PM PDT 24
Finished Apr 23 02:00:29 PM PDT 24
Peak memory 200872 kb
Host smart-ad972992-fd38-45df-a17f-fe6c4e5cd68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048053148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1048053148
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.321787108
Short name T706
Test name
Test status
Simulation time 35336176873 ps
CPU time 17.41 seconds
Started Apr 23 01:59:43 PM PDT 24
Finished Apr 23 02:00:00 PM PDT 24
Peak memory 199996 kb
Host smart-b99133d0-6aa3-4d03-81d2-2e74fcc12f22
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321787108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.321787108
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.776921939
Short name T649
Test name
Test status
Simulation time 139940336204 ps
CPU time 175.4 seconds
Started Apr 23 01:59:46 PM PDT 24
Finished Apr 23 02:02:41 PM PDT 24
Peak memory 200844 kb
Host smart-e8389a88-1ebb-4cd7-b0bc-61259a1618c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776921939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.776921939
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3694278773
Short name T552
Test name
Test status
Simulation time 9323063951 ps
CPU time 4.12 seconds
Started Apr 23 01:59:46 PM PDT 24
Finished Apr 23 01:59:50 PM PDT 24
Peak memory 199412 kb
Host smart-b72d18a2-40aa-42d9-943e-c9b4d64e66ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694278773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3694278773
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.435776194
Short name T21
Test name
Test status
Simulation time 64929431417 ps
CPU time 56.96 seconds
Started Apr 23 01:59:43 PM PDT 24
Finished Apr 23 02:00:40 PM PDT 24
Peak memory 201096 kb
Host smart-ed387179-081f-4960-a6fc-e8ebe3301477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435776194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.435776194
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1948388263
Short name T1044
Test name
Test status
Simulation time 10317523789 ps
CPU time 79.14 seconds
Started Apr 23 01:59:45 PM PDT 24
Finished Apr 23 02:01:05 PM PDT 24
Peak memory 200868 kb
Host smart-aea04162-273a-4557-94e0-bc81c5189349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948388263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1948388263
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4226718023
Short name T1144
Test name
Test status
Simulation time 5135844814 ps
CPU time 42.55 seconds
Started Apr 23 01:59:45 PM PDT 24
Finished Apr 23 02:00:28 PM PDT 24
Peak memory 199136 kb
Host smart-36e0d125-f8ea-4fde-ac66-dcb999ea0aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226718023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4226718023
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2780860539
Short name T942
Test name
Test status
Simulation time 175228281436 ps
CPU time 52.04 seconds
Started Apr 23 01:59:44 PM PDT 24
Finished Apr 23 02:00:36 PM PDT 24
Peak memory 200880 kb
Host smart-2fb1e750-a1c1-45d6-b065-45f8e7f3bf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780860539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2780860539
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.4226802122
Short name T471
Test name
Test status
Simulation time 36064135858 ps
CPU time 11.65 seconds
Started Apr 23 01:59:42 PM PDT 24
Finished Apr 23 01:59:54 PM PDT 24
Peak memory 196512 kb
Host smart-6196fc50-3c85-4445-b96a-758502821bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226802122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.4226802122
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.337662621
Short name T802
Test name
Test status
Simulation time 416098015 ps
CPU time 1.58 seconds
Started Apr 23 01:59:40 PM PDT 24
Finished Apr 23 01:59:42 PM PDT 24
Peak memory 199760 kb
Host smart-94a3e263-68c6-454e-bdbc-16d411e19a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337662621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.337662621
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2442137657
Short name T190
Test name
Test status
Simulation time 159320127512 ps
CPU time 225.48 seconds
Started Apr 23 01:59:45 PM PDT 24
Finished Apr 23 02:03:31 PM PDT 24
Peak memory 200804 kb
Host smart-ee32abe7-7fc4-487d-9310-34e71c61e0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442137657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2442137657
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.27052334
Short name T531
Test name
Test status
Simulation time 61001965006 ps
CPU time 620.4 seconds
Started Apr 23 01:59:48 PM PDT 24
Finished Apr 23 02:10:08 PM PDT 24
Peak memory 217448 kb
Host smart-0bcf7f3c-cf0f-423e-a43e-0281024ef9d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27052334 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.27052334
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.620317881
Short name T376
Test name
Test status
Simulation time 2721581150 ps
CPU time 2.57 seconds
Started Apr 23 01:59:45 PM PDT 24
Finished Apr 23 01:59:48 PM PDT 24
Peak memory 200780 kb
Host smart-0db9bca3-bc4b-452f-be7f-4f6620f7f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620317881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.620317881
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3217817045
Short name T760
Test name
Test status
Simulation time 80794205284 ps
CPU time 66.82 seconds
Started Apr 23 01:59:41 PM PDT 24
Finished Apr 23 02:00:48 PM PDT 24
Peak memory 200776 kb
Host smart-c3973965-791d-4cf0-97cb-c9cbdaeecb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217817045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3217817045
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1365826218
Short name T299
Test name
Test status
Simulation time 81895481563 ps
CPU time 148.57 seconds
Started Apr 23 02:05:51 PM PDT 24
Finished Apr 23 02:08:20 PM PDT 24
Peak memory 200848 kb
Host smart-5e990999-c47f-434d-933c-f36f7ab24e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365826218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1365826218
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3049463170
Short name T200
Test name
Test status
Simulation time 30289293349 ps
CPU time 40.53 seconds
Started Apr 23 02:05:55 PM PDT 24
Finished Apr 23 02:06:36 PM PDT 24
Peak memory 200776 kb
Host smart-04af7530-4a03-431c-9df9-c79c94d79d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049463170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3049463170
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.250776311
Short name T199
Test name
Test status
Simulation time 44952121328 ps
CPU time 81.67 seconds
Started Apr 23 02:06:00 PM PDT 24
Finished Apr 23 02:07:22 PM PDT 24
Peak memory 200908 kb
Host smart-3dbe2399-f55e-4392-8d80-b37629edb855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250776311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.250776311
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3697432560
Short name T253
Test name
Test status
Simulation time 168066308534 ps
CPU time 141.76 seconds
Started Apr 23 02:05:55 PM PDT 24
Finished Apr 23 02:08:17 PM PDT 24
Peak memory 200808 kb
Host smart-adbeef08-4746-45bf-9b01-d3a8eed3ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697432560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3697432560
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3813190258
Short name T599
Test name
Test status
Simulation time 146324501070 ps
CPU time 205.88 seconds
Started Apr 23 02:05:56 PM PDT 24
Finished Apr 23 02:09:22 PM PDT 24
Peak memory 200904 kb
Host smart-5b0f3e71-f5dc-4874-a64b-eb680f4d2164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813190258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3813190258
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1881533086
Short name T950
Test name
Test status
Simulation time 12451624420 ps
CPU time 11.13 seconds
Started Apr 23 02:06:02 PM PDT 24
Finished Apr 23 02:06:13 PM PDT 24
Peak memory 200852 kb
Host smart-4720e787-da7f-4e1f-b034-4363200e88e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881533086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1881533086
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.8838932
Short name T53
Test name
Test status
Simulation time 20125183725 ps
CPU time 19.1 seconds
Started Apr 23 02:05:57 PM PDT 24
Finished Apr 23 02:06:16 PM PDT 24
Peak memory 200828 kb
Host smart-81b76c6a-410b-4d10-affc-5ff3229c8e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8838932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.8838932
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3173892309
Short name T2
Test name
Test status
Simulation time 35436845449 ps
CPU time 67.24 seconds
Started Apr 23 02:05:56 PM PDT 24
Finished Apr 23 02:07:04 PM PDT 24
Peak memory 200916 kb
Host smart-1fdf3c69-9612-49ce-8436-90475ba1c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173892309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3173892309
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2729650625
Short name T9
Test name
Test status
Simulation time 58499317434 ps
CPU time 48.59 seconds
Started Apr 23 02:05:57 PM PDT 24
Finished Apr 23 02:06:46 PM PDT 24
Peak memory 200864 kb
Host smart-8b9565d3-6ed4-427c-a039-cd7764cfe130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729650625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2729650625
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3956173870
Short name T1175
Test name
Test status
Simulation time 44591751 ps
CPU time 0.54 seconds
Started Apr 23 01:59:56 PM PDT 24
Finished Apr 23 01:59:57 PM PDT 24
Peak memory 196172 kb
Host smart-3d0938c0-48de-4569-9655-75c6a7c26f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956173870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3956173870
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1695577115
Short name T648
Test name
Test status
Simulation time 135234882090 ps
CPU time 239.29 seconds
Started Apr 23 01:59:46 PM PDT 24
Finished Apr 23 02:03:46 PM PDT 24
Peak memory 200860 kb
Host smart-6feee4c7-1083-47f5-b18b-e45887ba38df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695577115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1695577115
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3939338965
Short name T689
Test name
Test status
Simulation time 29353270293 ps
CPU time 54.16 seconds
Started Apr 23 01:59:49 PM PDT 24
Finished Apr 23 02:00:43 PM PDT 24
Peak memory 200864 kb
Host smart-1c1c40c3-0d39-4106-976f-3051ebe7a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939338965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3939338965
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1082755651
Short name T405
Test name
Test status
Simulation time 105170115801 ps
CPU time 299.33 seconds
Started Apr 23 01:59:50 PM PDT 24
Finished Apr 23 02:04:50 PM PDT 24
Peak memory 200808 kb
Host smart-800f8e11-dd52-4d2a-9ce8-ff3c67ad9dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082755651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1082755651
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3946120600
Short name T331
Test name
Test status
Simulation time 350202538 ps
CPU time 1.07 seconds
Started Apr 23 01:59:50 PM PDT 24
Finished Apr 23 01:59:51 PM PDT 24
Peak memory 196376 kb
Host smart-250e859a-9943-4002-acfd-348b2ec466bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946120600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3946120600
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2385958165
Short name T435
Test name
Test status
Simulation time 96957405139 ps
CPU time 572.75 seconds
Started Apr 23 01:59:51 PM PDT 24
Finished Apr 23 02:09:24 PM PDT 24
Peak memory 200884 kb
Host smart-b91167af-4b3d-4efd-b62e-5f672b6f2c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385958165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2385958165
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3944661114
Short name T1074
Test name
Test status
Simulation time 4449748370 ps
CPU time 9.7 seconds
Started Apr 23 01:59:56 PM PDT 24
Finished Apr 23 02:00:07 PM PDT 24
Peak memory 199620 kb
Host smart-e8dddca3-47d9-4a92-9922-3a3135509f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944661114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3944661114
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3966664317
Short name T1094
Test name
Test status
Simulation time 22931151472 ps
CPU time 43.15 seconds
Started Apr 23 01:59:48 PM PDT 24
Finished Apr 23 02:00:31 PM PDT 24
Peak memory 200156 kb
Host smart-cb4a740d-14d9-435f-b4f3-78ab05cb1b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966664317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3966664317
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.236943071
Short name T781
Test name
Test status
Simulation time 20926235832 ps
CPU time 217.17 seconds
Started Apr 23 01:59:56 PM PDT 24
Finished Apr 23 02:03:34 PM PDT 24
Peak memory 200860 kb
Host smart-289f38cb-9afa-4b4f-897a-8ff72533af36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236943071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.236943071
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.222119343
Short name T343
Test name
Test status
Simulation time 5220493426 ps
CPU time 11.76 seconds
Started Apr 23 01:59:50 PM PDT 24
Finished Apr 23 02:00:02 PM PDT 24
Peak memory 199864 kb
Host smart-586f16fd-f29c-4fd3-be81-adb6ba429257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222119343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.222119343
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1275505368
Short name T1001
Test name
Test status
Simulation time 700054521 ps
CPU time 1.09 seconds
Started Apr 23 01:59:49 PM PDT 24
Finished Apr 23 01:59:50 PM PDT 24
Peak memory 196516 kb
Host smart-147e14cd-899a-4410-b0c7-49337fe76023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275505368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1275505368
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3964052447
Short name T492
Test name
Test status
Simulation time 510433163 ps
CPU time 1.88 seconds
Started Apr 23 01:59:49 PM PDT 24
Finished Apr 23 01:59:51 PM PDT 24
Peak memory 200648 kb
Host smart-0aabe6e1-535a-4710-a323-e4f0be4d8469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964052447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3964052447
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2611567954
Short name T1180
Test name
Test status
Simulation time 9431912562 ps
CPU time 17.66 seconds
Started Apr 23 01:59:55 PM PDT 24
Finished Apr 23 02:00:13 PM PDT 24
Peak memory 200768 kb
Host smart-3f8ec176-28dd-4a67-aa72-b3e90def10c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611567954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2611567954
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1801118145
Short name T932
Test name
Test status
Simulation time 41767036075 ps
CPU time 119.73 seconds
Started Apr 23 01:59:56 PM PDT 24
Finished Apr 23 02:01:56 PM PDT 24
Peak memory 209424 kb
Host smart-847703ab-6bbb-4149-89cd-23eb79fb49bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801118145 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1801118145
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3515758540
Short name T364
Test name
Test status
Simulation time 587187440 ps
CPU time 2.08 seconds
Started Apr 23 01:59:51 PM PDT 24
Finished Apr 23 01:59:54 PM PDT 24
Peak memory 199304 kb
Host smart-0dd2b41d-9491-47e4-9cd2-40b762bfcdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515758540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3515758540
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.227323048
Short name T580
Test name
Test status
Simulation time 107541044640 ps
CPU time 25.44 seconds
Started Apr 23 01:59:47 PM PDT 24
Finished Apr 23 02:00:12 PM PDT 24
Peak memory 200940 kb
Host smart-7b43632c-747c-41a5-8177-84ddb94ef17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227323048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.227323048
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1152176486
Short name T493
Test name
Test status
Simulation time 127443096024 ps
CPU time 54.15 seconds
Started Apr 23 02:06:01 PM PDT 24
Finished Apr 23 02:06:55 PM PDT 24
Peak memory 200888 kb
Host smart-faa3f42e-3502-4952-944d-713f7cbfa648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152176486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1152176486
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3352573079
Short name T201
Test name
Test status
Simulation time 27276139566 ps
CPU time 45.98 seconds
Started Apr 23 02:06:00 PM PDT 24
Finished Apr 23 02:06:46 PM PDT 24
Peak memory 200804 kb
Host smart-01dc6898-0993-4832-81df-2f715b7b9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352573079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3352573079
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2432951736
Short name T334
Test name
Test status
Simulation time 17273588040 ps
CPU time 25.54 seconds
Started Apr 23 02:06:02 PM PDT 24
Finished Apr 23 02:06:28 PM PDT 24
Peak memory 200912 kb
Host smart-342c7b38-7837-4ac2-a802-5f7d9e752292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432951736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2432951736
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2548545971
Short name T71
Test name
Test status
Simulation time 16814466105 ps
CPU time 10.02 seconds
Started Apr 23 02:06:06 PM PDT 24
Finished Apr 23 02:06:16 PM PDT 24
Peak memory 200824 kb
Host smart-c2549c3c-f60c-487d-9d4b-461306f0af0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548545971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2548545971
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2351107102
Short name T1157
Test name
Test status
Simulation time 44117344048 ps
CPU time 34.44 seconds
Started Apr 23 02:06:01 PM PDT 24
Finished Apr 23 02:06:36 PM PDT 24
Peak memory 200836 kb
Host smart-119352e6-258e-4d73-8aaa-252801c1aa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351107102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2351107102
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1444529750
Short name T1006
Test name
Test status
Simulation time 59804924039 ps
CPU time 71.21 seconds
Started Apr 23 02:06:01 PM PDT 24
Finished Apr 23 02:07:13 PM PDT 24
Peak memory 200872 kb
Host smart-6b7551f4-b2bf-4edc-ac79-e7df94526182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444529750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1444529750
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3605592268
Short name T333
Test name
Test status
Simulation time 72503524167 ps
CPU time 27.86 seconds
Started Apr 23 02:06:01 PM PDT 24
Finished Apr 23 02:06:29 PM PDT 24
Peak memory 200856 kb
Host smart-01a79afb-807d-48d2-a27d-b9d990ad7b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605592268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3605592268
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2525351315
Short name T858
Test name
Test status
Simulation time 138991065882 ps
CPU time 57.93 seconds
Started Apr 23 02:06:03 PM PDT 24
Finished Apr 23 02:07:01 PM PDT 24
Peak memory 200772 kb
Host smart-f89e428e-7bae-49c1-8ed1-4bc0ed247de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525351315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2525351315
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1355138245
Short name T707
Test name
Test status
Simulation time 62937796019 ps
CPU time 91.77 seconds
Started Apr 23 02:06:04 PM PDT 24
Finished Apr 23 02:07:36 PM PDT 24
Peak memory 200876 kb
Host smart-e5d7adb8-446e-4076-8050-c65b3651089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355138245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1355138245
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.977386940
Short name T683
Test name
Test status
Simulation time 13559944 ps
CPU time 0.61 seconds
Started Apr 23 02:00:02 PM PDT 24
Finished Apr 23 02:00:03 PM PDT 24
Peak memory 196116 kb
Host smart-57782e53-a3e0-4752-93cb-def705104bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977386940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.977386940
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3651573895
Short name T845
Test name
Test status
Simulation time 43947929707 ps
CPU time 82.72 seconds
Started Apr 23 01:59:59 PM PDT 24
Finished Apr 23 02:01:23 PM PDT 24
Peak memory 200776 kb
Host smart-74547ba5-9e71-47a8-bf94-bf77732c001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651573895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3651573895
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.4190614011
Short name T634
Test name
Test status
Simulation time 33087773947 ps
CPU time 56.02 seconds
Started Apr 23 01:59:58 PM PDT 24
Finished Apr 23 02:00:54 PM PDT 24
Peak memory 200708 kb
Host smart-374a3cff-aeb8-4a92-8e57-fc988097ca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190614011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.4190614011
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3492400229
Short name T237
Test name
Test status
Simulation time 20748885501 ps
CPU time 19.4 seconds
Started Apr 23 02:00:01 PM PDT 24
Finished Apr 23 02:00:20 PM PDT 24
Peak memory 200836 kb
Host smart-805ef0b7-0290-4737-8f29-87d3cf7eb2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492400229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3492400229
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2773948389
Short name T728
Test name
Test status
Simulation time 465987896501 ps
CPU time 738.27 seconds
Started Apr 23 02:00:00 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 200744 kb
Host smart-24765898-0e4b-4a14-b6de-f9c553c98fb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773948389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2773948389
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2806110302
Short name T899
Test name
Test status
Simulation time 74091529301 ps
CPU time 159.12 seconds
Started Apr 23 01:59:58 PM PDT 24
Finished Apr 23 02:02:37 PM PDT 24
Peak memory 200836 kb
Host smart-4ed2d376-5d35-4ce4-a391-d01d26a6f4d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806110302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2806110302
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.500598040
Short name T927
Test name
Test status
Simulation time 3796955870 ps
CPU time 7.77 seconds
Started Apr 23 02:00:00 PM PDT 24
Finished Apr 23 02:00:08 PM PDT 24
Peak memory 200732 kb
Host smart-d7562444-6179-4384-bfb3-7fcaa0ecda7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500598040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.500598040
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2160316766
Short name T511
Test name
Test status
Simulation time 75163530940 ps
CPU time 34.23 seconds
Started Apr 23 02:00:02 PM PDT 24
Finished Apr 23 02:00:37 PM PDT 24
Peak memory 200940 kb
Host smart-cfa7c93f-e898-4de2-9313-2c0612745b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160316766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2160316766
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.441996913
Short name T751
Test name
Test status
Simulation time 13781881989 ps
CPU time 244.08 seconds
Started Apr 23 01:59:58 PM PDT 24
Finished Apr 23 02:04:03 PM PDT 24
Peak memory 200840 kb
Host smart-1d46e27a-8237-422d-8785-1f3c110992df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441996913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.441996913
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2011866284
Short name T1186
Test name
Test status
Simulation time 4990772544 ps
CPU time 10.69 seconds
Started Apr 23 01:59:57 PM PDT 24
Finished Apr 23 02:00:08 PM PDT 24
Peak memory 199660 kb
Host smart-f46a0cbc-054a-4e72-a8a0-953612f84a01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011866284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2011866284
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.31589301
Short name T1148
Test name
Test status
Simulation time 21252540390 ps
CPU time 17.57 seconds
Started Apr 23 01:59:57 PM PDT 24
Finished Apr 23 02:00:15 PM PDT 24
Peak memory 200888 kb
Host smart-af76f0d5-ceca-4936-b2c1-3d8336be5e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31589301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.31589301
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.385026972
Short name T314
Test name
Test status
Simulation time 72635252675 ps
CPU time 25.79 seconds
Started Apr 23 01:59:58 PM PDT 24
Finished Apr 23 02:00:25 PM PDT 24
Peak memory 197124 kb
Host smart-0327c699-e454-4447-a76e-a394828670bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385026972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.385026972
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1169585579
Short name T391
Test name
Test status
Simulation time 6273942993 ps
CPU time 7.29 seconds
Started Apr 23 01:59:57 PM PDT 24
Finished Apr 23 02:00:05 PM PDT 24
Peak memory 200840 kb
Host smart-d3a32b70-e4a5-4f98-8507-a9fdadb4a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169585579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1169585579
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.483981368
Short name T1038
Test name
Test status
Simulation time 30286995647 ps
CPU time 56.27 seconds
Started Apr 23 02:00:03 PM PDT 24
Finished Apr 23 02:01:00 PM PDT 24
Peak memory 200996 kb
Host smart-6a036c88-0f9a-4a33-bdd5-8acddf0218dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483981368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.483981368
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1364749363
Short name T597
Test name
Test status
Simulation time 977960009243 ps
CPU time 988.25 seconds
Started Apr 23 01:59:58 PM PDT 24
Finished Apr 23 02:16:27 PM PDT 24
Peak memory 225736 kb
Host smart-6cc8628a-0f7d-44d3-918d-2a66f3e73077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364749363 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1364749363
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2005135358
Short name T716
Test name
Test status
Simulation time 2250507938 ps
CPU time 1.75 seconds
Started Apr 23 02:00:00 PM PDT 24
Finished Apr 23 02:00:02 PM PDT 24
Peak memory 199364 kb
Host smart-33917d60-4d2a-4016-b3d6-dfd348544c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005135358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2005135358
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3964075007
Short name T581
Test name
Test status
Simulation time 9438294991 ps
CPU time 16.01 seconds
Started Apr 23 01:59:57 PM PDT 24
Finished Apr 23 02:00:14 PM PDT 24
Peak memory 200816 kb
Host smart-dea1bc76-8c7a-4b13-8871-3e7b07c04319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964075007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3964075007
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1167901347
Short name T1156
Test name
Test status
Simulation time 40103291436 ps
CPU time 29.9 seconds
Started Apr 23 02:06:08 PM PDT 24
Finished Apr 23 02:06:39 PM PDT 24
Peak memory 200844 kb
Host smart-6b6f255b-b556-49fa-840b-aaf387a67bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167901347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1167901347
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.446156819
Short name T1024
Test name
Test status
Simulation time 22047854596 ps
CPU time 40.68 seconds
Started Apr 23 02:06:07 PM PDT 24
Finished Apr 23 02:06:48 PM PDT 24
Peak memory 200840 kb
Host smart-f323bf4c-a7f3-4459-a727-b65cd5123325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446156819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.446156819
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2848771897
Short name T970
Test name
Test status
Simulation time 17962586472 ps
CPU time 41.7 seconds
Started Apr 23 02:06:11 PM PDT 24
Finished Apr 23 02:06:53 PM PDT 24
Peak memory 200828 kb
Host smart-004b792e-cf7f-4067-8ab4-0d5fbe2a7af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848771897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2848771897
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4058615040
Short name T7
Test name
Test status
Simulation time 13074362619 ps
CPU time 21.81 seconds
Started Apr 23 02:06:10 PM PDT 24
Finished Apr 23 02:06:32 PM PDT 24
Peak memory 200808 kb
Host smart-907aa3b6-9ade-480f-b5f7-ee798a41a266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058615040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4058615040
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.786615865
Short name T928
Test name
Test status
Simulation time 102954182223 ps
CPU time 421.48 seconds
Started Apr 23 02:06:10 PM PDT 24
Finished Apr 23 02:13:12 PM PDT 24
Peak memory 200712 kb
Host smart-cf0c32b7-85e7-48df-b149-a6982d889226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786615865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.786615865
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2749595475
Short name T694
Test name
Test status
Simulation time 19143883424 ps
CPU time 17.29 seconds
Started Apr 23 02:06:13 PM PDT 24
Finished Apr 23 02:06:31 PM PDT 24
Peak memory 200876 kb
Host smart-6193d13f-8939-4530-9cfd-18cee085df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749595475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2749595475
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.55169444
Short name T975
Test name
Test status
Simulation time 53282240758 ps
CPU time 95.53 seconds
Started Apr 23 02:06:14 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 200848 kb
Host smart-c23b1f77-b0b4-4028-abd0-70733b155777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55169444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.55169444
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.439287330
Short name T37
Test name
Test status
Simulation time 167901643632 ps
CPU time 346.39 seconds
Started Apr 23 02:06:14 PM PDT 24
Finished Apr 23 02:12:01 PM PDT 24
Peak memory 200860 kb
Host smart-33863ce6-6d61-4027-8a63-39fdc764620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439287330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.439287330
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3727945978
Short name T901
Test name
Test status
Simulation time 65881354375 ps
CPU time 40.28 seconds
Started Apr 23 02:06:13 PM PDT 24
Finished Apr 23 02:06:54 PM PDT 24
Peak memory 200780 kb
Host smart-c0a18e6f-04e7-4c16-8bc4-7a2b6026d8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727945978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3727945978
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.688486668
Short name T1009
Test name
Test status
Simulation time 32130607084 ps
CPU time 36.24 seconds
Started Apr 23 02:06:15 PM PDT 24
Finished Apr 23 02:06:52 PM PDT 24
Peak memory 200828 kb
Host smart-ce5e543f-475a-4973-be09-8c8f426315ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688486668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.688486668
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1917594028
Short name T969
Test name
Test status
Simulation time 57427031 ps
CPU time 0.59 seconds
Started Apr 23 02:00:06 PM PDT 24
Finished Apr 23 02:00:07 PM PDT 24
Peak memory 196152 kb
Host smart-b8e6477a-d255-409b-978a-c272e0421c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917594028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1917594028
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3396806271
Short name T805
Test name
Test status
Simulation time 37409964672 ps
CPU time 15.79 seconds
Started Apr 23 02:00:02 PM PDT 24
Finished Apr 23 02:00:18 PM PDT 24
Peak memory 200848 kb
Host smart-1c93eb94-4587-449a-ab9b-bba286a61b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396806271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3396806271
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4007722471
Short name T313
Test name
Test status
Simulation time 142559505319 ps
CPU time 547.15 seconds
Started Apr 23 02:00:00 PM PDT 24
Finished Apr 23 02:09:07 PM PDT 24
Peak memory 200924 kb
Host smart-db6dea68-4740-46d1-a1ad-cca773ed4da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007722471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4007722471
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.4046056351
Short name T52
Test name
Test status
Simulation time 21686805565 ps
CPU time 38.26 seconds
Started Apr 23 02:00:03 PM PDT 24
Finished Apr 23 02:00:42 PM PDT 24
Peak memory 200900 kb
Host smart-f3e1a79d-db8b-4e6e-9fb5-08151a6b4f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046056351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4046056351
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1930410157
Short name T1016
Test name
Test status
Simulation time 47241268773 ps
CPU time 78.98 seconds
Started Apr 23 02:00:03 PM PDT 24
Finished Apr 23 02:01:23 PM PDT 24
Peak memory 200792 kb
Host smart-d4c2f269-e302-4004-a91e-95bfcd2bdeae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930410157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1930410157
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1317280687
Short name T952
Test name
Test status
Simulation time 168781726423 ps
CPU time 1473.2 seconds
Started Apr 23 02:00:04 PM PDT 24
Finished Apr 23 02:24:38 PM PDT 24
Peak memory 200744 kb
Host smart-7d386ab4-faa5-4755-ab68-1084657bac82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317280687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1317280687
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2390457123
Short name T583
Test name
Test status
Simulation time 12264422497 ps
CPU time 13.71 seconds
Started Apr 23 02:00:06 PM PDT 24
Finished Apr 23 02:00:20 PM PDT 24
Peak memory 200504 kb
Host smart-bce1127a-1236-461b-b8b9-30b5dab3100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390457123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2390457123
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1571568485
Short name T761
Test name
Test status
Simulation time 217313588446 ps
CPU time 87.73 seconds
Started Apr 23 01:59:59 PM PDT 24
Finished Apr 23 02:01:27 PM PDT 24
Peak memory 209232 kb
Host smart-faf34171-916e-4cf8-823e-806a22d5b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571568485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1571568485
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2448063084
Short name T876
Test name
Test status
Simulation time 5707602430 ps
CPU time 147.24 seconds
Started Apr 23 02:00:04 PM PDT 24
Finished Apr 23 02:02:31 PM PDT 24
Peak memory 200876 kb
Host smart-7cfbdcd1-ecf8-4245-a456-cccc2994b37c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448063084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2448063084
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.940906829
Short name T735
Test name
Test status
Simulation time 1615684760 ps
CPU time 2.66 seconds
Started Apr 23 02:00:02 PM PDT 24
Finished Apr 23 02:00:06 PM PDT 24
Peak memory 198568 kb
Host smart-a643c75f-b653-4acc-bffb-1f5a3f6574c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940906829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.940906829
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.74955055
Short name T295
Test name
Test status
Simulation time 133149070313 ps
CPU time 194.57 seconds
Started Apr 23 02:00:02 PM PDT 24
Finished Apr 23 02:03:17 PM PDT 24
Peak memory 200112 kb
Host smart-78540684-0ad3-4606-8562-bf507ad69a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74955055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.74955055
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.227452527
Short name T865
Test name
Test status
Simulation time 29319424033 ps
CPU time 4.74 seconds
Started Apr 23 02:00:00 PM PDT 24
Finished Apr 23 02:00:05 PM PDT 24
Peak memory 196936 kb
Host smart-01e31e79-dc29-4b01-b961-1196a63a36f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227452527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.227452527
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3829202639
Short name T478
Test name
Test status
Simulation time 957291528 ps
CPU time 1.98 seconds
Started Apr 23 02:00:02 PM PDT 24
Finished Apr 23 02:00:04 PM PDT 24
Peak memory 199296 kb
Host smart-6b5b1288-7354-410d-b817-ef4ff4935cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829202639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3829202639
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2986862368
Short name T983
Test name
Test status
Simulation time 120850139112 ps
CPU time 109.38 seconds
Started Apr 23 02:00:04 PM PDT 24
Finished Apr 23 02:01:54 PM PDT 24
Peak memory 200744 kb
Host smart-dc326146-3d79-4e53-8738-419caf97a8de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986862368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2986862368
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3878891840
Short name T984
Test name
Test status
Simulation time 1127931083 ps
CPU time 3.83 seconds
Started Apr 23 02:00:04 PM PDT 24
Finished Apr 23 02:00:09 PM PDT 24
Peak memory 200396 kb
Host smart-6c7809bb-5efe-4aa8-8856-e3c02f3d6408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878891840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3878891840
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1843886457
Short name T406
Test name
Test status
Simulation time 42330666608 ps
CPU time 34.75 seconds
Started Apr 23 01:59:58 PM PDT 24
Finished Apr 23 02:00:33 PM PDT 24
Peak memory 200832 kb
Host smart-823560ea-aeec-49d9-bbcc-192dce3f9250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843886457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1843886457
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2235935947
Short name T920
Test name
Test status
Simulation time 66137361675 ps
CPU time 100.84 seconds
Started Apr 23 02:06:17 PM PDT 24
Finished Apr 23 02:07:58 PM PDT 24
Peak memory 200848 kb
Host smart-72477d92-970d-4979-afbf-b109ba20cc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235935947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2235935947
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1635751930
Short name T510
Test name
Test status
Simulation time 207939572664 ps
CPU time 348.63 seconds
Started Apr 23 02:06:15 PM PDT 24
Finished Apr 23 02:12:05 PM PDT 24
Peak memory 200912 kb
Host smart-ffb15c65-8e32-41f2-96c5-b060e13c1d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635751930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1635751930
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2886835526
Short name T217
Test name
Test status
Simulation time 69641782519 ps
CPU time 40.99 seconds
Started Apr 23 02:06:16 PM PDT 24
Finished Apr 23 02:06:57 PM PDT 24
Peak memory 200832 kb
Host smart-c8564f1a-ffed-4b9e-af4d-13742e57bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886835526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2886835526
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3264449944
Short name T744
Test name
Test status
Simulation time 24717716348 ps
CPU time 20.2 seconds
Started Apr 23 02:06:15 PM PDT 24
Finished Apr 23 02:06:36 PM PDT 24
Peak memory 198400 kb
Host smart-72d7b274-9aa5-4044-8145-0c34550e7aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264449944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3264449944
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3259955980
Short name T1069
Test name
Test status
Simulation time 34523705600 ps
CPU time 27.83 seconds
Started Apr 23 02:06:19 PM PDT 24
Finished Apr 23 02:06:48 PM PDT 24
Peak memory 200860 kb
Host smart-c49555e8-1462-49d8-86a4-69f48ae29480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259955980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3259955980
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1363232024
Short name T256
Test name
Test status
Simulation time 61951539789 ps
CPU time 10.25 seconds
Started Apr 23 02:06:19 PM PDT 24
Finished Apr 23 02:06:30 PM PDT 24
Peak memory 200884 kb
Host smart-6abf3927-6b86-4aaa-af33-e31c0797ac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363232024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1363232024
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2591805925
Short name T1026
Test name
Test status
Simulation time 64015400645 ps
CPU time 45.59 seconds
Started Apr 23 02:06:20 PM PDT 24
Finished Apr 23 02:07:06 PM PDT 24
Peak memory 200864 kb
Host smart-954c3dd5-a896-40c6-9dce-6cd3e7e637cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591805925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2591805925
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3690818465
Short name T512
Test name
Test status
Simulation time 23447086272 ps
CPU time 37.38 seconds
Started Apr 23 02:06:21 PM PDT 24
Finished Apr 23 02:06:59 PM PDT 24
Peak memory 200744 kb
Host smart-a35c6b2e-ffd6-4708-a1c4-4736ded275fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690818465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3690818465
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2592909151
Short name T227
Test name
Test status
Simulation time 69423751240 ps
CPU time 33.78 seconds
Started Apr 23 02:06:21 PM PDT 24
Finished Apr 23 02:06:55 PM PDT 24
Peak memory 200792 kb
Host smart-8610ca00-b857-4d97-b591-7f7a3365d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592909151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2592909151
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2927506971
Short name T490
Test name
Test status
Simulation time 22088469 ps
CPU time 0.52 seconds
Started Apr 23 02:00:09 PM PDT 24
Finished Apr 23 02:00:10 PM PDT 24
Peak memory 195128 kb
Host smart-0b77ed9d-cbf4-4776-922a-b8e7827eda7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927506971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2927506971
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.938613214
Short name T966
Test name
Test status
Simulation time 44272706298 ps
CPU time 75.29 seconds
Started Apr 23 02:00:04 PM PDT 24
Finished Apr 23 02:01:20 PM PDT 24
Peak memory 200912 kb
Host smart-2a6a7daa-1def-4133-8329-a0eccbfb7b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938613214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.938613214
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3602953980
Short name T172
Test name
Test status
Simulation time 197770795053 ps
CPU time 28.56 seconds
Started Apr 23 02:00:04 PM PDT 24
Finished Apr 23 02:00:33 PM PDT 24
Peak memory 200824 kb
Host smart-69007cff-db62-4f13-8d84-741ec3c68cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602953980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3602953980
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2494615729
Short name T613
Test name
Test status
Simulation time 8001637099 ps
CPU time 4.39 seconds
Started Apr 23 02:00:07 PM PDT 24
Finished Apr 23 02:00:12 PM PDT 24
Peak memory 200784 kb
Host smart-f0ff414c-8900-405d-ad0a-3668d6f8dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494615729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2494615729
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1644951554
Short name T454
Test name
Test status
Simulation time 39688207288 ps
CPU time 33.21 seconds
Started Apr 23 02:00:07 PM PDT 24
Finished Apr 23 02:00:41 PM PDT 24
Peak memory 200524 kb
Host smart-aa01152c-7f62-4f97-8288-5ecd76c8f999
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644951554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1644951554
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2943971499
Short name T570
Test name
Test status
Simulation time 114549675071 ps
CPU time 523.91 seconds
Started Apr 23 02:00:09 PM PDT 24
Finished Apr 23 02:08:54 PM PDT 24
Peak memory 200888 kb
Host smart-37777687-9b88-4904-8e95-58bcffca39b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943971499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2943971499
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1933282672
Short name T341
Test name
Test status
Simulation time 1117802971 ps
CPU time 2.69 seconds
Started Apr 23 02:00:10 PM PDT 24
Finished Apr 23 02:00:13 PM PDT 24
Peak memory 198064 kb
Host smart-b63dc2b2-7cc6-462d-bc14-b41665ba5d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933282672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1933282672
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.926098300
Short name T92
Test name
Test status
Simulation time 333729417154 ps
CPU time 97.21 seconds
Started Apr 23 02:00:08 PM PDT 24
Finished Apr 23 02:01:45 PM PDT 24
Peak memory 209200 kb
Host smart-18192296-95a3-42a5-a0e8-c9690f295dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926098300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.926098300
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1193717242
Short name T363
Test name
Test status
Simulation time 12701150925 ps
CPU time 675.95 seconds
Started Apr 23 02:00:10 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 200908 kb
Host smart-2dd60756-b5df-49ea-ab25-1f73bedf3025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193717242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1193717242
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1525304570
Short name T1063
Test name
Test status
Simulation time 1814341811 ps
CPU time 2.73 seconds
Started Apr 23 02:00:08 PM PDT 24
Finished Apr 23 02:00:11 PM PDT 24
Peak memory 198928 kb
Host smart-0bd2c779-1d7d-4afe-958e-83f49e126238
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525304570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1525304570
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1592756193
Short name T13
Test name
Test status
Simulation time 70427427666 ps
CPU time 30.82 seconds
Started Apr 23 02:00:07 PM PDT 24
Finished Apr 23 02:00:39 PM PDT 24
Peak memory 200756 kb
Host smart-a8661874-ade5-4de1-8cee-d39935df58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592756193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1592756193
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3935563012
Short name T639
Test name
Test status
Simulation time 3414761750 ps
CPU time 2 seconds
Started Apr 23 02:00:06 PM PDT 24
Finished Apr 23 02:00:09 PM PDT 24
Peak memory 196892 kb
Host smart-6932ad50-796c-4739-87c7-17b498bbc641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935563012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3935563012
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1459366582
Short name T496
Test name
Test status
Simulation time 254065428 ps
CPU time 1.7 seconds
Started Apr 23 02:00:06 PM PDT 24
Finished Apr 23 02:00:08 PM PDT 24
Peak memory 199784 kb
Host smart-1f9a8175-a03f-4f71-b7ce-93bd9cebe9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459366582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1459366582
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.473024061
Short name T1143
Test name
Test status
Simulation time 358495125713 ps
CPU time 244.78 seconds
Started Apr 23 02:00:11 PM PDT 24
Finished Apr 23 02:04:16 PM PDT 24
Peak memory 216504 kb
Host smart-10ef8c71-1592-4731-89b0-d8b8735eca21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473024061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.473024061
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1654223608
Short name T1077
Test name
Test status
Simulation time 5951169580 ps
CPU time 20.44 seconds
Started Apr 23 02:00:08 PM PDT 24
Finished Apr 23 02:00:29 PM PDT 24
Peak memory 200504 kb
Host smart-344cbcb7-5324-4fe5-9cb8-248cb877fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654223608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1654223608
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1546853188
Short name T270
Test name
Test status
Simulation time 120355263897 ps
CPU time 59.62 seconds
Started Apr 23 02:00:04 PM PDT 24
Finished Apr 23 02:01:05 PM PDT 24
Peak memory 200700 kb
Host smart-0745aea5-5459-4e1e-858d-449a6ab3691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546853188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1546853188
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1194358578
Short name T189
Test name
Test status
Simulation time 146712055898 ps
CPU time 115.88 seconds
Started Apr 23 02:06:21 PM PDT 24
Finished Apr 23 02:08:17 PM PDT 24
Peak memory 200852 kb
Host smart-e5b98f55-7cc0-4f68-bcce-d4c3989e48e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194358578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1194358578
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1866293778
Short name T332
Test name
Test status
Simulation time 68163142242 ps
CPU time 232.7 seconds
Started Apr 23 02:06:22 PM PDT 24
Finished Apr 23 02:10:15 PM PDT 24
Peak memory 200832 kb
Host smart-65c4f3e0-2390-4f2f-a0e2-3d35e227cb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866293778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1866293778
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1246993510
Short name T228
Test name
Test status
Simulation time 42907477774 ps
CPU time 17.65 seconds
Started Apr 23 02:06:20 PM PDT 24
Finished Apr 23 02:06:38 PM PDT 24
Peak memory 199344 kb
Host smart-5e513213-e7e4-4a88-9418-14e3e650daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246993510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1246993510
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3028451434
Short name T211
Test name
Test status
Simulation time 7627055541 ps
CPU time 13.4 seconds
Started Apr 23 02:06:27 PM PDT 24
Finished Apr 23 02:06:41 PM PDT 24
Peak memory 200788 kb
Host smart-b31f3a42-93a0-423e-9aa0-1cb5eac90b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028451434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3028451434
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2665006163
Short name T221
Test name
Test status
Simulation time 23261956552 ps
CPU time 19.56 seconds
Started Apr 23 02:06:26 PM PDT 24
Finished Apr 23 02:06:46 PM PDT 24
Peak memory 200904 kb
Host smart-7fad0fee-7131-42ec-b980-0bf3f103c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665006163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2665006163
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3928003573
Short name T206
Test name
Test status
Simulation time 26376731478 ps
CPU time 43.36 seconds
Started Apr 23 02:06:24 PM PDT 24
Finished Apr 23 02:07:08 PM PDT 24
Peak memory 200852 kb
Host smart-c2bfa957-e65a-4f2a-b755-80bb26e884cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928003573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3928003573
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3302596558
Short name T659
Test name
Test status
Simulation time 159690925153 ps
CPU time 157.04 seconds
Started Apr 23 02:06:31 PM PDT 24
Finished Apr 23 02:09:08 PM PDT 24
Peak memory 200856 kb
Host smart-b85c6af5-e4bb-41aa-9609-e383b0548ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302596558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3302596558
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3853755015
Short name T847
Test name
Test status
Simulation time 248486994251 ps
CPU time 27.51 seconds
Started Apr 23 02:06:32 PM PDT 24
Finished Apr 23 02:07:00 PM PDT 24
Peak memory 200792 kb
Host smart-1f7e1a5e-425d-4037-8cca-8e2cd7f4d2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853755015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3853755015
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3798161077
Short name T1020
Test name
Test status
Simulation time 18675387448 ps
CPU time 26.6 seconds
Started Apr 23 02:06:32 PM PDT 24
Finished Apr 23 02:06:59 PM PDT 24
Peak memory 200680 kb
Host smart-2010f8fd-0141-4cd0-977f-f9ea9f317b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798161077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3798161077
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.929316110
Short name T565
Test name
Test status
Simulation time 23049016 ps
CPU time 0.53 seconds
Started Apr 23 02:00:21 PM PDT 24
Finished Apr 23 02:00:22 PM PDT 24
Peak memory 195108 kb
Host smart-7e7bd58c-b141-45c4-8281-fe014135b078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929316110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.929316110
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3530588872
Short name T155
Test name
Test status
Simulation time 101484893649 ps
CPU time 37.13 seconds
Started Apr 23 02:00:12 PM PDT 24
Finished Apr 23 02:00:50 PM PDT 24
Peak memory 200904 kb
Host smart-61cd04ec-2fcc-454a-a2e0-4d2cd05ae244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530588872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3530588872
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.144513188
Short name T179
Test name
Test status
Simulation time 41136434275 ps
CPU time 47.28 seconds
Started Apr 23 02:00:13 PM PDT 24
Finished Apr 23 02:01:01 PM PDT 24
Peak memory 200888 kb
Host smart-3cbaf938-9447-4c00-bb89-585f363f6a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144513188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.144513188
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2539732026
Short name T150
Test name
Test status
Simulation time 114367669529 ps
CPU time 95.35 seconds
Started Apr 23 02:00:15 PM PDT 24
Finished Apr 23 02:01:51 PM PDT 24
Peak memory 200864 kb
Host smart-ca1ea4c7-9ed9-4136-b431-84568666c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539732026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2539732026
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.900660611
Short name T754
Test name
Test status
Simulation time 258364296518 ps
CPU time 419.49 seconds
Started Apr 23 02:00:21 PM PDT 24
Finished Apr 23 02:07:21 PM PDT 24
Peak memory 199784 kb
Host smart-21bd0137-c19c-4bbe-9f4c-ac83bf52ad25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900660611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.900660611
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1515246049
Short name T814
Test name
Test status
Simulation time 109666670428 ps
CPU time 334.02 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:06:18 PM PDT 24
Peak memory 200860 kb
Host smart-93f7eed5-064c-4313-876c-4a92a4c5b5b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515246049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1515246049
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2066565452
Short name T509
Test name
Test status
Simulation time 12763677491 ps
CPU time 7.03 seconds
Started Apr 23 02:00:19 PM PDT 24
Finished Apr 23 02:00:27 PM PDT 24
Peak memory 196728 kb
Host smart-30b60772-ad69-407c-b735-bc66136671a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066565452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2066565452
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2805008335
Short name T605
Test name
Test status
Simulation time 69393483495 ps
CPU time 130.51 seconds
Started Apr 23 02:00:20 PM PDT 24
Finished Apr 23 02:02:31 PM PDT 24
Peak memory 201116 kb
Host smart-71f83039-ab10-4b66-a3c1-786c98b884b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805008335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2805008335
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2968077984
Short name T931
Test name
Test status
Simulation time 9824572408 ps
CPU time 571.38 seconds
Started Apr 23 02:00:22 PM PDT 24
Finished Apr 23 02:09:54 PM PDT 24
Peak memory 200856 kb
Host smart-62d304a4-84fb-4087-b7ae-5017d9c80c4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968077984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2968077984
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2736815648
Short name T1029
Test name
Test status
Simulation time 5368248742 ps
CPU time 47.51 seconds
Started Apr 23 02:00:15 PM PDT 24
Finished Apr 23 02:01:03 PM PDT 24
Peak memory 198896 kb
Host smart-04cad491-f5e2-4d04-a353-c304fbd99936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736815648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2736815648
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.722317382
Short name T319
Test name
Test status
Simulation time 97173480358 ps
CPU time 485.65 seconds
Started Apr 23 02:00:18 PM PDT 24
Finished Apr 23 02:08:24 PM PDT 24
Peak memory 200708 kb
Host smart-2b585db0-36bd-463b-9ef4-c7c84870ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722317382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.722317382
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2812557577
Short name T22
Test name
Test status
Simulation time 1946439184 ps
CPU time 3.69 seconds
Started Apr 23 02:00:20 PM PDT 24
Finished Apr 23 02:00:24 PM PDT 24
Peak memory 196480 kb
Host smart-d2afa122-9baa-4f78-8ca3-1e2474442626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812557577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2812557577
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3534978047
Short name T1028
Test name
Test status
Simulation time 5337121008 ps
CPU time 16.49 seconds
Started Apr 23 02:00:13 PM PDT 24
Finished Apr 23 02:00:30 PM PDT 24
Peak memory 199944 kb
Host smart-a3d7e2f6-db2f-4077-a9bb-d53865289988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534978047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3534978047
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2668006729
Short name T1133
Test name
Test status
Simulation time 168984092773 ps
CPU time 777.12 seconds
Started Apr 23 02:00:21 PM PDT 24
Finished Apr 23 02:13:19 PM PDT 24
Peak memory 200816 kb
Host smart-ba9bf3be-ccd7-4159-80ae-b8d657c93180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668006729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2668006729
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1582009912
Short name T775
Test name
Test status
Simulation time 412463184595 ps
CPU time 1040.78 seconds
Started Apr 23 02:00:42 PM PDT 24
Finished Apr 23 02:18:03 PM PDT 24
Peak memory 233828 kb
Host smart-926305ab-a6e3-4259-8c0a-8fddd378e639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582009912 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1582009912
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.342406659
Short name T487
Test name
Test status
Simulation time 2487606884 ps
CPU time 2.38 seconds
Started Apr 23 02:00:20 PM PDT 24
Finished Apr 23 02:00:23 PM PDT 24
Peak memory 199684 kb
Host smart-193bc2ab-52f4-40f3-8676-f283fbfc993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342406659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.342406659
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3252480470
Short name T898
Test name
Test status
Simulation time 131332922145 ps
CPU time 52.74 seconds
Started Apr 23 02:00:13 PM PDT 24
Finished Apr 23 02:01:07 PM PDT 24
Peak memory 200792 kb
Host smart-96b29615-26c1-42b0-b248-8bc60ec96aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252480470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3252480470
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3376522318
Short name T753
Test name
Test status
Simulation time 19409816797 ps
CPU time 15.85 seconds
Started Apr 23 02:06:30 PM PDT 24
Finished Apr 23 02:06:46 PM PDT 24
Peak memory 200896 kb
Host smart-2b2449bd-1947-43d8-91f2-a14b49f213fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376522318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3376522318
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4166078975
Short name T1168
Test name
Test status
Simulation time 68521340738 ps
CPU time 265.35 seconds
Started Apr 23 02:06:32 PM PDT 24
Finished Apr 23 02:10:58 PM PDT 24
Peak memory 200856 kb
Host smart-5a5c898f-36d5-4420-b0da-ca8fc611e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166078975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4166078975
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.905152074
Short name T864
Test name
Test status
Simulation time 141258545625 ps
CPU time 198.05 seconds
Started Apr 23 02:06:36 PM PDT 24
Finished Apr 23 02:09:55 PM PDT 24
Peak memory 200908 kb
Host smart-dde2a5a4-1194-4121-8402-f6bfbf8d310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905152074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.905152074
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.438248764
Short name T1114
Test name
Test status
Simulation time 147837748312 ps
CPU time 229.81 seconds
Started Apr 23 02:06:34 PM PDT 24
Finished Apr 23 02:10:25 PM PDT 24
Peak memory 200836 kb
Host smart-2ee1b67f-f1c6-4bc1-930c-5c9199671604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438248764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.438248764
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1587772006
Short name T247
Test name
Test status
Simulation time 17797482311 ps
CPU time 12.71 seconds
Started Apr 23 02:06:41 PM PDT 24
Finished Apr 23 02:06:54 PM PDT 24
Peak memory 200876 kb
Host smart-03cb5a2b-2673-4bf2-b2f4-284403189a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587772006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1587772006
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1018206060
Short name T231
Test name
Test status
Simulation time 416501656162 ps
CPU time 41.84 seconds
Started Apr 23 02:06:35 PM PDT 24
Finished Apr 23 02:07:18 PM PDT 24
Peak memory 200748 kb
Host smart-70f981ec-8125-4087-b089-92c4928b8ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018206060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1018206060
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3884353108
Short name T1111
Test name
Test status
Simulation time 20912628616 ps
CPU time 32.75 seconds
Started Apr 23 02:06:34 PM PDT 24
Finished Apr 23 02:07:08 PM PDT 24
Peak memory 200752 kb
Host smart-f8612a8b-878e-4377-b158-56cacc89ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884353108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3884353108
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3114749726
Short name T264
Test name
Test status
Simulation time 128000832292 ps
CPU time 212.1 seconds
Started Apr 23 02:06:33 PM PDT 24
Finished Apr 23 02:10:06 PM PDT 24
Peak memory 200876 kb
Host smart-7174ace1-03f0-46a9-98bd-43ddd0c9c29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114749726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3114749726
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3757715661
Short name T212
Test name
Test status
Simulation time 91938898220 ps
CPU time 80.69 seconds
Started Apr 23 02:06:32 PM PDT 24
Finished Apr 23 02:07:53 PM PDT 24
Peak memory 200800 kb
Host smart-4c9fc5ab-0382-490e-b7d1-2e57c95ab1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757715661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3757715661
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.127435335
Short name T630
Test name
Test status
Simulation time 17745915141 ps
CPU time 31.37 seconds
Started Apr 23 02:06:35 PM PDT 24
Finished Apr 23 02:07:07 PM PDT 24
Peak memory 200808 kb
Host smart-13660af0-a1b1-421f-a76b-ce3890e99489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127435335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.127435335
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1034995729
Short name T794
Test name
Test status
Simulation time 102507803 ps
CPU time 0.55 seconds
Started Apr 23 02:00:45 PM PDT 24
Finished Apr 23 02:00:46 PM PDT 24
Peak memory 195576 kb
Host smart-33e240b4-6956-4192-aa14-ebc1df12f7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034995729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1034995729
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.831211281
Short name T44
Test name
Test status
Simulation time 132826818014 ps
CPU time 135.77 seconds
Started Apr 23 02:00:26 PM PDT 24
Finished Apr 23 02:02:42 PM PDT 24
Peak memory 200576 kb
Host smart-ff9e65e4-74af-46d1-8008-cf73b6806d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831211281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.831211281
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.4193446038
Short name T1147
Test name
Test status
Simulation time 221283605893 ps
CPU time 26.4 seconds
Started Apr 23 02:00:45 PM PDT 24
Finished Apr 23 02:01:12 PM PDT 24
Peak memory 200528 kb
Host smart-39a7ac4d-12ab-4e91-8f3a-fef4b1fc1c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193446038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4193446038
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1824861113
Short name T844
Test name
Test status
Simulation time 232312967079 ps
CPU time 233.41 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:04:37 PM PDT 24
Peak memory 200912 kb
Host smart-de5bca70-b516-4e8a-a6f3-0090d20c6851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824861113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1824861113
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2807228590
Short name T828
Test name
Test status
Simulation time 35621501285 ps
CPU time 15.79 seconds
Started Apr 23 02:00:25 PM PDT 24
Finished Apr 23 02:00:41 PM PDT 24
Peak memory 200740 kb
Host smart-284209b4-511a-4bec-952c-238574aa3332
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807228590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2807228590
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2248915240
Short name T529
Test name
Test status
Simulation time 152712172564 ps
CPU time 1709.1 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:29:14 PM PDT 24
Peak memory 200760 kb
Host smart-63ad005d-497b-40e9-b694-e716f74b9bea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248915240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2248915240
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1555713417
Short name T444
Test name
Test status
Simulation time 11496302695 ps
CPU time 24.67 seconds
Started Apr 23 02:00:32 PM PDT 24
Finished Apr 23 02:00:57 PM PDT 24
Peak memory 200804 kb
Host smart-de8d8f04-b9d1-47a9-8ac6-e96c7e00199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555713417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1555713417
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.879046640
Short name T840
Test name
Test status
Simulation time 56789169214 ps
CPU time 36.74 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:01:21 PM PDT 24
Peak memory 198560 kb
Host smart-8213c24d-2715-4c23-9135-faff08e914ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879046640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.879046640
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2296979938
Short name T495
Test name
Test status
Simulation time 28940268765 ps
CPU time 337.77 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:06:22 PM PDT 24
Peak memory 200804 kb
Host smart-33e05d49-d416-4123-915b-72fdbd87ea10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296979938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2296979938
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3425418664
Short name T749
Test name
Test status
Simulation time 3265420692 ps
CPU time 7.91 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:00:51 PM PDT 24
Peak memory 199280 kb
Host smart-f0b6b3b1-904a-4cfd-bb79-c8e438f6bcd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425418664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3425418664
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3374218397
Short name T1164
Test name
Test status
Simulation time 12187769632 ps
CPU time 12.14 seconds
Started Apr 23 02:00:30 PM PDT 24
Finished Apr 23 02:00:42 PM PDT 24
Peak memory 200792 kb
Host smart-a923e832-26c2-4996-9925-9bcd02f145f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374218397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3374218397
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.849910123
Short name T941
Test name
Test status
Simulation time 1955747003 ps
CPU time 2.09 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:00:45 PM PDT 24
Peak memory 196552 kb
Host smart-df00fdc0-bd3e-4356-828a-de3f5df4ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849910123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.849910123
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3372385427
Short name T857
Test name
Test status
Simulation time 458884814 ps
CPU time 1.98 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:00:46 PM PDT 24
Peak memory 199472 kb
Host smart-e8d709fd-96d5-4b57-a150-6414d3dceab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372385427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3372385427
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.4092009378
Short name T1105
Test name
Test status
Simulation time 125768067457 ps
CPU time 186.84 seconds
Started Apr 23 02:00:32 PM PDT 24
Finished Apr 23 02:03:39 PM PDT 24
Peak memory 200804 kb
Host smart-f46ec069-052a-4313-95a4-33806f999043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092009378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.4092009378
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1644792645
Short name T1062
Test name
Test status
Simulation time 30165028127 ps
CPU time 167.5 seconds
Started Apr 23 02:00:34 PM PDT 24
Finished Apr 23 02:03:22 PM PDT 24
Peak memory 216776 kb
Host smart-aa711c35-279f-45b9-b205-f50300f7f53f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644792645 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1644792645
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1644722034
Short name T1136
Test name
Test status
Simulation time 1506428874 ps
CPU time 1.81 seconds
Started Apr 23 02:00:30 PM PDT 24
Finished Apr 23 02:00:32 PM PDT 24
Peak memory 199172 kb
Host smart-8ec9e47a-278f-4dff-b66a-bdddf174d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644722034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1644722034
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.645951126
Short name T889
Test name
Test status
Simulation time 12074300067 ps
CPU time 9.52 seconds
Started Apr 23 02:00:22 PM PDT 24
Finished Apr 23 02:00:32 PM PDT 24
Peak memory 200156 kb
Host smart-8c4c97fa-876c-41a2-8587-f86029c3513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645951126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.645951126
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1313076906
Short name T1025
Test name
Test status
Simulation time 142359497603 ps
CPU time 71.09 seconds
Started Apr 23 02:06:38 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 200916 kb
Host smart-7e591edd-d1b8-4422-8336-b2f2b00be2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313076906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1313076906
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3774520396
Short name T1027
Test name
Test status
Simulation time 20867566549 ps
CPU time 21.66 seconds
Started Apr 23 02:06:38 PM PDT 24
Finished Apr 23 02:07:00 PM PDT 24
Peak memory 200828 kb
Host smart-12edf5f0-3933-418e-9012-acc0a72f6782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774520396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3774520396
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3122878209
Short name T219
Test name
Test status
Simulation time 15425065678 ps
CPU time 26.43 seconds
Started Apr 23 02:06:41 PM PDT 24
Finished Apr 23 02:07:08 PM PDT 24
Peak memory 200628 kb
Host smart-413f5ec7-f283-4559-9814-884eedd3f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122878209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3122878209
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2109178431
Short name T321
Test name
Test status
Simulation time 28356598814 ps
CPU time 69.13 seconds
Started Apr 23 02:06:41 PM PDT 24
Finished Apr 23 02:07:50 PM PDT 24
Peak memory 200836 kb
Host smart-b8f8f8db-d764-4f20-a768-99983871fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109178431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2109178431
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3181360010
Short name T530
Test name
Test status
Simulation time 39518802863 ps
CPU time 62.06 seconds
Started Apr 23 02:06:40 PM PDT 24
Finished Apr 23 02:07:42 PM PDT 24
Peak memory 200852 kb
Host smart-4e4d67af-a7e7-4042-a474-e073a561f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181360010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3181360010
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.999238603
Short name T163
Test name
Test status
Simulation time 105270506281 ps
CPU time 18.79 seconds
Started Apr 23 02:06:39 PM PDT 24
Finished Apr 23 02:06:59 PM PDT 24
Peak memory 200912 kb
Host smart-fc756e5a-6dcc-4177-9691-59f4201c511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999238603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.999238603
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2157154805
Short name T226
Test name
Test status
Simulation time 102057776041 ps
CPU time 308.72 seconds
Started Apr 23 02:06:44 PM PDT 24
Finished Apr 23 02:11:53 PM PDT 24
Peak memory 200840 kb
Host smart-c98130f6-26e7-4725-8576-7c2fa53d9235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157154805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2157154805
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1970524538
Short name T370
Test name
Test status
Simulation time 12849868 ps
CPU time 0.56 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:58:29 PM PDT 24
Peak memory 196116 kb
Host smart-b47faa3e-a787-40a2-8230-6648ddb4e9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970524538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1970524538
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1323116456
Short name T961
Test name
Test status
Simulation time 86896104020 ps
CPU time 12.79 seconds
Started Apr 23 01:58:19 PM PDT 24
Finished Apr 23 01:58:33 PM PDT 24
Peak memory 200788 kb
Host smart-5b4acef6-62d0-4640-9c4f-e28aa268cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323116456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1323116456
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3003110775
Short name T902
Test name
Test status
Simulation time 120287390804 ps
CPU time 50.14 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 01:59:08 PM PDT 24
Peak memory 200772 kb
Host smart-0bf2f82a-8dd9-47d4-a49c-67d0a2f9ec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003110775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3003110775
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2031928264
Short name T244
Test name
Test status
Simulation time 140178110652 ps
CPU time 79.67 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 01:59:38 PM PDT 24
Peak memory 200808 kb
Host smart-d91a01c9-3f56-4eee-a7ff-8527ade93b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031928264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2031928264
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1285551569
Short name T327
Test name
Test status
Simulation time 5758584036 ps
CPU time 9.55 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 01:58:28 PM PDT 24
Peak memory 197508 kb
Host smart-31ab3649-1757-4b5c-96d8-7a7c963f0b1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285551569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1285551569
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.425587813
Short name T1163
Test name
Test status
Simulation time 173346355766 ps
CPU time 125.53 seconds
Started Apr 23 01:58:21 PM PDT 24
Finished Apr 23 02:00:27 PM PDT 24
Peak memory 200768 kb
Host smart-3fb2106a-5ef5-4556-920f-5fdeee0eb87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425587813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.425587813
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1465947405
Short name T954
Test name
Test status
Simulation time 1778959816 ps
CPU time 1.32 seconds
Started Apr 23 01:58:21 PM PDT 24
Finished Apr 23 01:58:23 PM PDT 24
Peak memory 197984 kb
Host smart-3cb28a01-484a-47a1-be99-beb2e2b27f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465947405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1465947405
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.588359563
Short name T652
Test name
Test status
Simulation time 11629240066 ps
CPU time 16.9 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 01:58:36 PM PDT 24
Peak memory 198992 kb
Host smart-a94b9fd9-b864-4e6a-9176-9aa432b6c69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588359563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.588359563
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3237597339
Short name T1051
Test name
Test status
Simulation time 14622070220 ps
CPU time 776.75 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 200844 kb
Host smart-5266affd-1dd0-41aa-b048-e1d1d2452615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237597339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3237597339
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3745087884
Short name T344
Test name
Test status
Simulation time 4222531518 ps
CPU time 20.63 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 01:58:39 PM PDT 24
Peak memory 198960 kb
Host smart-d59d847d-ef80-46f7-8d12-4397795bd08d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745087884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3745087884
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2312001513
Short name T1128
Test name
Test status
Simulation time 66233004207 ps
CPU time 46.53 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 01:59:05 PM PDT 24
Peak memory 200800 kb
Host smart-c8a2c09e-5eeb-4dfc-8503-93493a16b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312001513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2312001513
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3887865521
Short name T839
Test name
Test status
Simulation time 3058362722 ps
CPU time 1.8 seconds
Started Apr 23 01:58:20 PM PDT 24
Finished Apr 23 01:58:23 PM PDT 24
Peak memory 196740 kb
Host smart-098a8c49-9e52-42ef-8bab-70f58e88bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887865521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3887865521
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2220324778
Short name T108
Test name
Test status
Simulation time 38309270 ps
CPU time 0.77 seconds
Started Apr 23 01:58:19 PM PDT 24
Finished Apr 23 01:58:20 PM PDT 24
Peak memory 218652 kb
Host smart-6892c655-ff51-4527-a03b-fb81e4480ec2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220324778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2220324778
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4278980693
Short name T759
Test name
Test status
Simulation time 446540408 ps
CPU time 2.42 seconds
Started Apr 23 01:58:17 PM PDT 24
Finished Apr 23 01:58:20 PM PDT 24
Peak memory 200644 kb
Host smart-29da6bb8-0452-4cf7-b3b8-102ab53337b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278980693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4278980693
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2861534492
Short name T122
Test name
Test status
Simulation time 691580702467 ps
CPU time 229.44 seconds
Started Apr 23 01:58:20 PM PDT 24
Finished Apr 23 02:02:10 PM PDT 24
Peak memory 209244 kb
Host smart-9ca338eb-1091-49b2-b9cc-1fa128aa9ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861534492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2861534492
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.803599727
Short name T617
Test name
Test status
Simulation time 48705151737 ps
CPU time 1299.4 seconds
Started Apr 23 01:58:18 PM PDT 24
Finished Apr 23 02:19:58 PM PDT 24
Peak memory 217196 kb
Host smart-e57d11bf-662b-4c20-bf40-2b04940a96ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803599727 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.803599727
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2060316083
Short name T544
Test name
Test status
Simulation time 862466792 ps
CPU time 3.56 seconds
Started Apr 23 01:58:20 PM PDT 24
Finished Apr 23 01:58:24 PM PDT 24
Peak memory 200732 kb
Host smart-c7aa0831-edd5-4bdd-b9f4-67316a4f7f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060316083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2060316083
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.283200557
Short name T355
Test name
Test status
Simulation time 43861223023 ps
CPU time 73.45 seconds
Started Apr 23 01:58:19 PM PDT 24
Finished Apr 23 01:59:33 PM PDT 24
Peak memory 200788 kb
Host smart-736c790c-0d77-4a80-bd22-077bb1b9992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283200557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.283200557
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2918088048
Short name T26
Test name
Test status
Simulation time 37968406 ps
CPU time 0.55 seconds
Started Apr 23 02:00:42 PM PDT 24
Finished Apr 23 02:00:43 PM PDT 24
Peak memory 195608 kb
Host smart-090d7fab-124c-446a-a841-a83fd722073d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918088048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2918088048
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3372386065
Short name T674
Test name
Test status
Simulation time 77208242879 ps
CPU time 33.42 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:01:18 PM PDT 24
Peak memory 200888 kb
Host smart-93e47d6f-6184-4428-a045-09af51e179bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372386065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3372386065
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3739687368
Short name T909
Test name
Test status
Simulation time 26272085043 ps
CPU time 22.65 seconds
Started Apr 23 02:00:33 PM PDT 24
Finished Apr 23 02:00:57 PM PDT 24
Peak memory 200768 kb
Host smart-7e991275-15e9-4a4a-90de-17577033559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739687368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3739687368
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.2120601643
Short name T939
Test name
Test status
Simulation time 41233477877 ps
CPU time 36.56 seconds
Started Apr 23 02:00:35 PM PDT 24
Finished Apr 23 02:01:12 PM PDT 24
Peak memory 200844 kb
Host smart-2a0ef23f-341d-4194-a680-20708315ce6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120601643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2120601643
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.196196568
Short name T396
Test name
Test status
Simulation time 166739072259 ps
CPU time 895 seconds
Started Apr 23 02:00:40 PM PDT 24
Finished Apr 23 02:15:36 PM PDT 24
Peak memory 200748 kb
Host smart-c2575830-ec22-47b3-bc2d-5d5a2b25eeda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196196568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.196196568
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.4145182068
Short name T843
Test name
Test status
Simulation time 7463307979 ps
CPU time 7.16 seconds
Started Apr 23 02:00:41 PM PDT 24
Finished Apr 23 02:00:48 PM PDT 24
Peak memory 200748 kb
Host smart-c787af4e-607e-4a33-bc5c-7549a206dd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145182068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4145182068
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1673600342
Short name T711
Test name
Test status
Simulation time 197698678472 ps
CPU time 35.62 seconds
Started Apr 23 02:00:35 PM PDT 24
Finished Apr 23 02:01:11 PM PDT 24
Peak memory 200424 kb
Host smart-fbecce9f-cb1d-4088-b3f4-1bb8f3ba09ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673600342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1673600342
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1166662306
Short name T1066
Test name
Test status
Simulation time 13030935580 ps
CPU time 185.15 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:03:49 PM PDT 24
Peak memory 200888 kb
Host smart-004f20bc-861f-4e96-ab85-d3c636fb91a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166662306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1166662306
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2740076340
Short name T557
Test name
Test status
Simulation time 1717327747 ps
CPU time 1.98 seconds
Started Apr 23 02:00:34 PM PDT 24
Finished Apr 23 02:00:37 PM PDT 24
Peak memory 198668 kb
Host smart-ba2f288a-cccd-43f4-80ca-e8a98f81db9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740076340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2740076340
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2682920902
Short name T280
Test name
Test status
Simulation time 93386156795 ps
CPU time 210.23 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:04:14 PM PDT 24
Peak memory 200728 kb
Host smart-8f6125ca-4300-4539-96a5-b2d9a9f3e4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682920902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2682920902
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.600283339
Short name T566
Test name
Test status
Simulation time 37958499848 ps
CPU time 29.45 seconds
Started Apr 23 02:00:33 PM PDT 24
Finished Apr 23 02:01:03 PM PDT 24
Peak memory 196952 kb
Host smart-9c5434b2-efc5-4462-9674-faa97cf69860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600283339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.600283339
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3747232927
Short name T365
Test name
Test status
Simulation time 513438893 ps
CPU time 1.62 seconds
Started Apr 23 02:00:31 PM PDT 24
Finished Apr 23 02:00:33 PM PDT 24
Peak memory 199808 kb
Host smart-27acc876-781d-4b4e-a3b2-f08499a9f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747232927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3747232927
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1126223097
Short name T1150
Test name
Test status
Simulation time 1347097269723 ps
CPU time 437.2 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:08:01 PM PDT 24
Peak memory 209292 kb
Host smart-73294550-3d88-4f24-9637-1d0af9dd0fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126223097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1126223097
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3512224344
Short name T609
Test name
Test status
Simulation time 151905056531 ps
CPU time 490.82 seconds
Started Apr 23 02:00:38 PM PDT 24
Finished Apr 23 02:08:49 PM PDT 24
Peak memory 217292 kb
Host smart-9cbe9b0b-3789-4290-92b4-830d96485c62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512224344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3512224344
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1469864175
Short name T1177
Test name
Test status
Simulation time 720525476 ps
CPU time 3.14 seconds
Started Apr 23 02:00:39 PM PDT 24
Finished Apr 23 02:00:42 PM PDT 24
Peak memory 199704 kb
Host smart-5a015d8f-ea9e-46a1-8b31-c6068bd43e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469864175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1469864175
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2514603935
Short name T366
Test name
Test status
Simulation time 51645709070 ps
CPU time 7.6 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:00:51 PM PDT 24
Peak memory 200816 kb
Host smart-d882f1b7-339a-4cfc-9b96-5188a28946ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514603935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2514603935
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1621553955
Short name T393
Test name
Test status
Simulation time 11641134 ps
CPU time 0.54 seconds
Started Apr 23 02:00:46 PM PDT 24
Finished Apr 23 02:00:47 PM PDT 24
Peak memory 196204 kb
Host smart-23b644ba-ff84-44f3-9ae3-a967a8c6cf98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621553955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1621553955
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.388753559
Short name T712
Test name
Test status
Simulation time 67916347699 ps
CPU time 108.74 seconds
Started Apr 23 02:00:42 PM PDT 24
Finished Apr 23 02:02:31 PM PDT 24
Peak memory 200848 kb
Host smart-95ee0c02-e8db-4766-8c2d-a5380bed1f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388753559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.388753559
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.4116478935
Short name T1065
Test name
Test status
Simulation time 68553244786 ps
CPU time 115.25 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:02:40 PM PDT 24
Peak memory 200732 kb
Host smart-3da4a355-671f-4848-a692-e2fcd6902b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116478935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4116478935
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1528851012
Short name T972
Test name
Test status
Simulation time 124986408914 ps
CPU time 56.86 seconds
Started Apr 23 02:00:47 PM PDT 24
Finished Apr 23 02:01:45 PM PDT 24
Peak memory 200736 kb
Host smart-1cc12075-48d6-45cc-9ff1-e3a9b95bb561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528851012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1528851012
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3881320248
Short name T1162
Test name
Test status
Simulation time 28344809838 ps
CPU time 55.25 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:01:40 PM PDT 24
Peak memory 200868 kb
Host smart-1c72774e-7c36-47a1-8410-f7b699414289
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881320248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3881320248
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.955609789
Short name T1083
Test name
Test status
Simulation time 80448481181 ps
CPU time 414.11 seconds
Started Apr 23 02:00:47 PM PDT 24
Finished Apr 23 02:07:41 PM PDT 24
Peak memory 200820 kb
Host smart-1881d357-13ed-4038-b9ec-7a7d51fb1934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955609789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.955609789
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.496204623
Short name T457
Test name
Test status
Simulation time 2459706136 ps
CPU time 0.91 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:00:44 PM PDT 24
Peak memory 196544 kb
Host smart-45588e29-b8f3-4757-91c5-f0202429500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496204623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.496204623
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3064939807
Short name T871
Test name
Test status
Simulation time 57038857099 ps
CPU time 87.08 seconds
Started Apr 23 02:00:45 PM PDT 24
Finished Apr 23 02:02:12 PM PDT 24
Peak memory 200080 kb
Host smart-5d39a0de-2d23-4fa2-8e52-b08eb7351ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064939807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3064939807
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3106987502
Short name T1091
Test name
Test status
Simulation time 12512174539 ps
CPU time 751.57 seconds
Started Apr 23 02:00:47 PM PDT 24
Finished Apr 23 02:13:19 PM PDT 24
Peak memory 200824 kb
Host smart-2229f856-91a4-4758-8fe5-a37002263206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106987502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3106987502
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2023453928
Short name T1159
Test name
Test status
Simulation time 7384876790 ps
CPU time 15.97 seconds
Started Apr 23 02:00:43 PM PDT 24
Finished Apr 23 02:00:59 PM PDT 24
Peak memory 198912 kb
Host smart-61b37ebd-92cd-4725-829a-25c8be587856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023453928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2023453928
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2547896317
Short name T784
Test name
Test status
Simulation time 36902498660 ps
CPU time 69.08 seconds
Started Apr 23 02:00:46 PM PDT 24
Finished Apr 23 02:01:55 PM PDT 24
Peak memory 200772 kb
Host smart-4a5979d5-50fb-433f-93e9-7b42dfac8323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547896317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2547896317
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3315821261
Short name T394
Test name
Test status
Simulation time 54189667596 ps
CPU time 43.19 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:01:28 PM PDT 24
Peak memory 196528 kb
Host smart-c85142d9-9711-4096-aaaa-1c79ecee9ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315821261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3315821261
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2779109069
Short name T1058
Test name
Test status
Simulation time 6285233758 ps
CPU time 5 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:00:49 PM PDT 24
Peak memory 200496 kb
Host smart-61517d16-e5ff-41fb-8bf8-89e859088600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779109069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2779109069
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3374855025
Short name T732
Test name
Test status
Simulation time 144490813649 ps
CPU time 56.09 seconds
Started Apr 23 02:00:47 PM PDT 24
Finished Apr 23 02:01:43 PM PDT 24
Peak memory 200804 kb
Host smart-5f4750c3-9c99-4545-809b-a7193600b8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374855025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3374855025
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3924662216
Short name T959
Test name
Test status
Simulation time 11601511074 ps
CPU time 234.35 seconds
Started Apr 23 02:00:46 PM PDT 24
Finished Apr 23 02:04:41 PM PDT 24
Peak memory 209108 kb
Host smart-787506a7-8d14-49a6-a170-f52bde5df335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924662216 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3924662216
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1522892430
Short name T1130
Test name
Test status
Simulation time 1215034601 ps
CPU time 2.37 seconds
Started Apr 23 02:00:41 PM PDT 24
Finished Apr 23 02:00:44 PM PDT 24
Peak memory 200640 kb
Host smart-0880d951-d4f4-404e-aeb3-d5ece3c0fe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522892430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1522892430
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.771137986
Short name T326
Test name
Test status
Simulation time 25770394775 ps
CPU time 9.96 seconds
Started Apr 23 02:00:44 PM PDT 24
Finished Apr 23 02:00:55 PM PDT 24
Peak memory 198768 kb
Host smart-6db471eb-a15e-4441-b767-332309d19d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771137986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.771137986
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1092685720
Short name T789
Test name
Test status
Simulation time 12232850 ps
CPU time 0.62 seconds
Started Apr 23 02:00:55 PM PDT 24
Finished Apr 23 02:00:56 PM PDT 24
Peak memory 195696 kb
Host smart-27276b88-a9ea-4730-9524-13967cea9deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092685720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1092685720
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1718400187
Short name T795
Test name
Test status
Simulation time 179986046515 ps
CPU time 300.06 seconds
Started Apr 23 02:00:49 PM PDT 24
Finished Apr 23 02:05:49 PM PDT 24
Peak memory 200836 kb
Host smart-15fdc475-2b5c-480d-815f-3dcebf5d8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718400187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1718400187
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2881524864
Short name T1125
Test name
Test status
Simulation time 62448224550 ps
CPU time 95.72 seconds
Started Apr 23 02:00:46 PM PDT 24
Finished Apr 23 02:02:22 PM PDT 24
Peak memory 200732 kb
Host smart-392bcce7-499e-478b-aed7-4aa5548a725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881524864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2881524864
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.4140830041
Short name T216
Test name
Test status
Simulation time 160509503457 ps
CPU time 119.65 seconds
Started Apr 23 02:00:52 PM PDT 24
Finished Apr 23 02:02:52 PM PDT 24
Peak memory 200896 kb
Host smart-41edf011-24e5-4a6c-b04b-8c2e7e8bdaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140830041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.4140830041
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.711322021
Short name T883
Test name
Test status
Simulation time 180016219375 ps
CPU time 67.5 seconds
Started Apr 23 02:00:50 PM PDT 24
Finished Apr 23 02:01:58 PM PDT 24
Peak memory 200812 kb
Host smart-361033c6-254d-4303-af29-2e076b54b875
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711322021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.711322021
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1223702763
Short name T799
Test name
Test status
Simulation time 178644942929 ps
CPU time 246.9 seconds
Started Apr 23 02:00:52 PM PDT 24
Finished Apr 23 02:04:59 PM PDT 24
Peak memory 200808 kb
Host smart-12f0ff4e-dcb4-4510-9e1f-74ac7dbc529f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223702763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1223702763
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2325063243
Short name T833
Test name
Test status
Simulation time 8549850246 ps
CPU time 19.88 seconds
Started Apr 23 02:00:53 PM PDT 24
Finished Apr 23 02:01:13 PM PDT 24
Peak memory 199024 kb
Host smart-36cbff23-9148-446f-986f-005fb73b0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325063243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2325063243
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3547488859
Short name T701
Test name
Test status
Simulation time 24003117077 ps
CPU time 20.83 seconds
Started Apr 23 02:00:50 PM PDT 24
Finished Apr 23 02:01:11 PM PDT 24
Peak memory 200976 kb
Host smart-d831c831-c330-48a5-b6d3-b47b1ce17674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547488859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3547488859
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2924187394
Short name T997
Test name
Test status
Simulation time 20083786586 ps
CPU time 242.73 seconds
Started Apr 23 02:00:54 PM PDT 24
Finished Apr 23 02:04:57 PM PDT 24
Peak memory 200904 kb
Host smart-a295cf35-898d-403b-b1a2-f9eab0d7cdac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924187394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2924187394
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3516631044
Short name T397
Test name
Test status
Simulation time 6752619799 ps
CPU time 30.94 seconds
Started Apr 23 02:00:52 PM PDT 24
Finished Apr 23 02:01:23 PM PDT 24
Peak memory 198976 kb
Host smart-ea0b9c80-9c16-4014-a849-8189fa938239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516631044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3516631044
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.672486012
Short name T872
Test name
Test status
Simulation time 184899056542 ps
CPU time 54.53 seconds
Started Apr 23 02:00:54 PM PDT 24
Finished Apr 23 02:01:49 PM PDT 24
Peak memory 200712 kb
Host smart-52cb8017-42b8-49fd-ba6a-2052ef0fb7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672486012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.672486012
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2969560807
Short name T1153
Test name
Test status
Simulation time 5785093319 ps
CPU time 1.17 seconds
Started Apr 23 02:00:50 PM PDT 24
Finished Apr 23 02:00:52 PM PDT 24
Peak memory 196872 kb
Host smart-c3f3bb7d-9fc8-4dc6-9f77-1593082fea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969560807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2969560807
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3302389430
Short name T877
Test name
Test status
Simulation time 261889602 ps
CPU time 1.53 seconds
Started Apr 23 02:00:46 PM PDT 24
Finished Apr 23 02:00:48 PM PDT 24
Peak memory 199172 kb
Host smart-cf895b9c-5879-4e5c-8b1d-8f5da556fd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302389430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3302389430
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1069323837
Short name T434
Test name
Test status
Simulation time 251104610080 ps
CPU time 482.45 seconds
Started Apr 23 02:00:54 PM PDT 24
Finished Apr 23 02:08:57 PM PDT 24
Peak memory 209184 kb
Host smart-fa716512-5829-423f-847b-379f48058e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069323837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1069323837
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1189293393
Short name T61
Test name
Test status
Simulation time 271516703300 ps
CPU time 820.86 seconds
Started Apr 23 02:00:55 PM PDT 24
Finished Apr 23 02:14:36 PM PDT 24
Peak memory 217384 kb
Host smart-9e154965-c530-419b-ba21-8d2ac91550bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189293393 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1189293393
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4217912142
Short name T671
Test name
Test status
Simulation time 1145228255 ps
CPU time 2.69 seconds
Started Apr 23 02:00:53 PM PDT 24
Finished Apr 23 02:00:56 PM PDT 24
Peak memory 199644 kb
Host smart-1dc95fc7-680a-4e09-ad36-d98b867908a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217912142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4217912142
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.4097270859
Short name T1034
Test name
Test status
Simulation time 143908369491 ps
CPU time 54.46 seconds
Started Apr 23 02:00:48 PM PDT 24
Finished Apr 23 02:01:42 PM PDT 24
Peak memory 200780 kb
Host smart-67a839d1-bdda-409c-95d9-153ce9fc8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097270859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4097270859
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1049151601
Short name T841
Test name
Test status
Simulation time 33843683 ps
CPU time 0.54 seconds
Started Apr 23 02:01:04 PM PDT 24
Finished Apr 23 02:01:05 PM PDT 24
Peak memory 196192 kb
Host smart-a0fb0f1a-5b37-41bc-a971-570256a6e499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049151601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1049151601
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2719098360
Short name T146
Test name
Test status
Simulation time 58374159165 ps
CPU time 25.58 seconds
Started Apr 23 02:00:56 PM PDT 24
Finished Apr 23 02:01:22 PM PDT 24
Peak memory 200832 kb
Host smart-31674024-885f-4438-8940-61345db59a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719098360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2719098360
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2068789693
Short name T129
Test name
Test status
Simulation time 103199945876 ps
CPU time 78.6 seconds
Started Apr 23 02:00:56 PM PDT 24
Finished Apr 23 02:02:15 PM PDT 24
Peak memory 200808 kb
Host smart-e38835d9-c0c2-4a9e-82d1-c8b285e97edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068789693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2068789693
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2775024582
Short name T109
Test name
Test status
Simulation time 114145504338 ps
CPU time 198.42 seconds
Started Apr 23 02:01:00 PM PDT 24
Finished Apr 23 02:04:19 PM PDT 24
Peak memory 200936 kb
Host smart-3a05bc92-c9fa-4ea3-bd56-7c85defac9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775024582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2775024582
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.283760210
Short name T1002
Test name
Test status
Simulation time 42069216421 ps
CPU time 13.06 seconds
Started Apr 23 02:01:00 PM PDT 24
Finished Apr 23 02:01:13 PM PDT 24
Peak memory 200712 kb
Host smart-205cf90c-0baa-4448-80aa-8ed4444f40ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283760210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.283760210
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2634767957
Short name T412
Test name
Test status
Simulation time 143617789161 ps
CPU time 191.43 seconds
Started Apr 23 02:01:02 PM PDT 24
Finished Apr 23 02:04:14 PM PDT 24
Peak memory 200912 kb
Host smart-37245e4b-e1e8-457a-984e-520c8d242f42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634767957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2634767957
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3265600938
Short name T890
Test name
Test status
Simulation time 8277632695 ps
CPU time 15.59 seconds
Started Apr 23 02:01:01 PM PDT 24
Finished Apr 23 02:01:17 PM PDT 24
Peak memory 200244 kb
Host smart-8fe2257b-73b5-4713-b46c-72cc0b03ef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265600938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3265600938
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.382896566
Short name T830
Test name
Test status
Simulation time 143192616916 ps
CPU time 17.48 seconds
Started Apr 23 02:01:01 PM PDT 24
Finished Apr 23 02:01:19 PM PDT 24
Peak memory 199324 kb
Host smart-b86bef41-f5d5-4e1b-8bfc-be08b40ea544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382896566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.382896566
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2113657695
Short name T1097
Test name
Test status
Simulation time 12778541234 ps
CPU time 157.95 seconds
Started Apr 23 02:01:05 PM PDT 24
Finished Apr 23 02:03:43 PM PDT 24
Peak memory 200968 kb
Host smart-bdb4221d-791e-49f8-a957-a9259f637098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113657695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2113657695
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1013503211
Short name T915
Test name
Test status
Simulation time 5681377273 ps
CPU time 48.03 seconds
Started Apr 23 02:00:57 PM PDT 24
Finished Apr 23 02:01:45 PM PDT 24
Peak memory 199992 kb
Host smart-a55b0f50-6843-46a0-ad5d-099656c734e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013503211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1013503211
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1102971286
Short name T1096
Test name
Test status
Simulation time 29759028194 ps
CPU time 34.63 seconds
Started Apr 23 02:01:00 PM PDT 24
Finished Apr 23 02:01:35 PM PDT 24
Peak memory 200704 kb
Host smart-cf701176-8a72-48f0-9378-62f898391e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102971286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1102971286
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1105238357
Short name T43
Test name
Test status
Simulation time 41063151635 ps
CPU time 9.63 seconds
Started Apr 23 02:01:01 PM PDT 24
Finished Apr 23 02:01:11 PM PDT 24
Peak memory 196636 kb
Host smart-825bd546-0dd0-480f-a88b-3cf94147ed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105238357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1105238357
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2138660657
Short name T868
Test name
Test status
Simulation time 890629440 ps
CPU time 3.79 seconds
Started Apr 23 02:00:59 PM PDT 24
Finished Apr 23 02:01:03 PM PDT 24
Peak memory 199148 kb
Host smart-5b2aaa11-8949-47cb-a69b-084e272f73f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138660657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2138660657
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3921259888
Short name T973
Test name
Test status
Simulation time 186830770153 ps
CPU time 279.42 seconds
Started Apr 23 02:01:06 PM PDT 24
Finished Apr 23 02:05:45 PM PDT 24
Peak memory 200836 kb
Host smart-8751d4ba-5447-42ca-9434-c4ab934e00a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921259888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3921259888
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.403487447
Short name T32
Test name
Test status
Simulation time 74506654763 ps
CPU time 886.84 seconds
Started Apr 23 02:01:02 PM PDT 24
Finished Apr 23 02:15:49 PM PDT 24
Peak memory 213704 kb
Host smart-759e6f3a-5fb9-4fd4-87df-8ec3e413eb70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403487447 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.403487447
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1209745971
Short name T459
Test name
Test status
Simulation time 6612361273 ps
CPU time 9.03 seconds
Started Apr 23 02:00:58 PM PDT 24
Finished Apr 23 02:01:08 PM PDT 24
Peak memory 200632 kb
Host smart-32a45238-4085-4b9a-9804-b689ddc8d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209745971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1209745971
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1529517243
Short name T276
Test name
Test status
Simulation time 72654043314 ps
CPU time 30.04 seconds
Started Apr 23 02:00:55 PM PDT 24
Finished Apr 23 02:01:25 PM PDT 24
Peak memory 200732 kb
Host smart-b707dc0c-0913-478c-80b4-c344f6e86528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529517243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1529517243
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2298500164
Short name T361
Test name
Test status
Simulation time 48594825 ps
CPU time 0.59 seconds
Started Apr 23 02:01:21 PM PDT 24
Finished Apr 23 02:01:22 PM PDT 24
Peak memory 195576 kb
Host smart-eae63b3f-899f-4294-9642-140548a354d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298500164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2298500164
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.803007929
Short name T46
Test name
Test status
Simulation time 26901194688 ps
CPU time 31.66 seconds
Started Apr 23 02:01:07 PM PDT 24
Finished Apr 23 02:01:39 PM PDT 24
Peak memory 200748 kb
Host smart-e5fd651d-38c4-4252-8353-af4ce48dfbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803007929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.803007929
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.529151792
Short name T79
Test name
Test status
Simulation time 16935104828 ps
CPU time 27.2 seconds
Started Apr 23 02:01:05 PM PDT 24
Finished Apr 23 02:01:33 PM PDT 24
Peak memory 200700 kb
Host smart-7d5e672d-ba54-4436-921c-c8e6100d5206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529151792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.529151792
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3149548227
Short name T564
Test name
Test status
Simulation time 12571277803 ps
CPU time 5.44 seconds
Started Apr 23 02:01:03 PM PDT 24
Finished Apr 23 02:01:09 PM PDT 24
Peak memory 197600 kb
Host smart-7ce3ecff-cddb-40af-9ff6-cfa281599399
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149548227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3149548227
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2954815343
Short name T856
Test name
Test status
Simulation time 112065179463 ps
CPU time 183.71 seconds
Started Apr 23 02:01:10 PM PDT 24
Finished Apr 23 02:04:14 PM PDT 24
Peak memory 200880 kb
Host smart-43e0b9a5-a324-4843-8175-d71edde7357a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954815343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2954815343
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3834208328
Short name T571
Test name
Test status
Simulation time 1229678631 ps
CPU time 0.95 seconds
Started Apr 23 02:01:10 PM PDT 24
Finished Apr 23 02:01:12 PM PDT 24
Peak memory 196236 kb
Host smart-17228d31-580c-438a-997d-39b2d32bd895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834208328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3834208328
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1404058022
Short name T989
Test name
Test status
Simulation time 97012215605 ps
CPU time 175.96 seconds
Started Apr 23 02:01:10 PM PDT 24
Finished Apr 23 02:04:06 PM PDT 24
Peak memory 209188 kb
Host smart-9adbe401-139d-40f2-847a-d40f27c9c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404058022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1404058022
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.137368416
Short name T375
Test name
Test status
Simulation time 24569021191 ps
CPU time 1268.98 seconds
Started Apr 23 02:01:13 PM PDT 24
Finished Apr 23 02:22:22 PM PDT 24
Peak memory 200880 kb
Host smart-45369cd6-ebbe-4e64-99eb-535ca30e1283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137368416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.137368416
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3258806689
Short name T1181
Test name
Test status
Simulation time 3598057217 ps
CPU time 32.06 seconds
Started Apr 23 02:01:08 PM PDT 24
Finished Apr 23 02:01:40 PM PDT 24
Peak memory 199204 kb
Host smart-815a01ef-34df-4a2a-bdb2-5ca19745798d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258806689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3258806689
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1835391955
Short name T791
Test name
Test status
Simulation time 20342445006 ps
CPU time 34.42 seconds
Started Apr 23 02:01:10 PM PDT 24
Finished Apr 23 02:01:45 PM PDT 24
Peak memory 200840 kb
Host smart-bc90fc0b-c01a-41c4-8cd9-be7f3625f3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835391955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1835391955
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3001627082
Short name T1101
Test name
Test status
Simulation time 6477715673 ps
CPU time 9.66 seconds
Started Apr 23 02:01:10 PM PDT 24
Finished Apr 23 02:01:20 PM PDT 24
Peak memory 196788 kb
Host smart-8f1a1798-5085-48b3-a907-b8e75082c6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001627082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3001627082
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.173403455
Short name T879
Test name
Test status
Simulation time 476485234 ps
CPU time 1.48 seconds
Started Apr 23 02:01:07 PM PDT 24
Finished Apr 23 02:01:09 PM PDT 24
Peak memory 199636 kb
Host smart-fde9ec27-1db3-4bb4-924d-55aca05375dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173403455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.173403455
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1029211523
Short name T491
Test name
Test status
Simulation time 213565230595 ps
CPU time 336.18 seconds
Started Apr 23 02:01:24 PM PDT 24
Finished Apr 23 02:07:00 PM PDT 24
Peak memory 200784 kb
Host smart-eddea194-f2ea-4cf6-a3e1-cab5ee5cb76e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029211523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1029211523
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2188491432
Short name T626
Test name
Test status
Simulation time 82820235339 ps
CPU time 320.51 seconds
Started Apr 23 02:01:10 PM PDT 24
Finished Apr 23 02:06:31 PM PDT 24
Peak memory 217292 kb
Host smart-b7259583-11ce-48d9-a870-837c0b0e061b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188491432 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2188491432
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2396796023
Short name T855
Test name
Test status
Simulation time 1199098712 ps
CPU time 2.03 seconds
Started Apr 23 02:01:11 PM PDT 24
Finished Apr 23 02:01:14 PM PDT 24
Peak memory 198628 kb
Host smart-829cc5d0-4429-4553-b9c0-515e575764a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396796023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2396796023
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2609218880
Short name T635
Test name
Test status
Simulation time 98644082244 ps
CPU time 13.65 seconds
Started Apr 23 02:01:06 PM PDT 24
Finished Apr 23 02:01:20 PM PDT 24
Peak memory 200756 kb
Host smart-5bc8bcf8-5eb9-4f69-952a-e99b8693ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609218880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2609218880
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4061478126
Short name T687
Test name
Test status
Simulation time 49447942 ps
CPU time 0.54 seconds
Started Apr 23 02:01:19 PM PDT 24
Finished Apr 23 02:01:20 PM PDT 24
Peak memory 196188 kb
Host smart-6198be42-0af7-46e9-9604-4bad6f234a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061478126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4061478126
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.321127327
Short name T169
Test name
Test status
Simulation time 127876575847 ps
CPU time 109.93 seconds
Started Apr 23 02:01:15 PM PDT 24
Finished Apr 23 02:03:05 PM PDT 24
Peak memory 200832 kb
Host smart-803bfd77-363b-4173-9b50-e5ebcf57b781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321127327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.321127327
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1603705926
Short name T773
Test name
Test status
Simulation time 94915067690 ps
CPU time 85.32 seconds
Started Apr 23 02:01:21 PM PDT 24
Finished Apr 23 02:02:47 PM PDT 24
Peak memory 200740 kb
Host smart-d65e6549-75f1-4738-94db-644dd7c76031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603705926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1603705926
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1195218921
Short name T196
Test name
Test status
Simulation time 124432698859 ps
CPU time 220.19 seconds
Started Apr 23 02:01:24 PM PDT 24
Finished Apr 23 02:05:05 PM PDT 24
Peak memory 200728 kb
Host smart-c9117134-a697-4364-927f-702e3c574052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195218921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1195218921
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3830744658
Short name T477
Test name
Test status
Simulation time 33851572556 ps
CPU time 56.02 seconds
Started Apr 23 02:01:23 PM PDT 24
Finished Apr 23 02:02:19 PM PDT 24
Peak memory 200568 kb
Host smart-c8fc9e95-be8b-4e5f-8942-1cf3b83dcd6a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830744658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3830744658
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4023666500
Short name T731
Test name
Test status
Simulation time 155792383562 ps
CPU time 661.87 seconds
Started Apr 23 02:01:23 PM PDT 24
Finished Apr 23 02:12:26 PM PDT 24
Peak memory 200856 kb
Host smart-9b7c765b-f382-45d3-b389-a3bcbbc82167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023666500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4023666500
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3248969644
Short name T368
Test name
Test status
Simulation time 865315038 ps
CPU time 1.86 seconds
Started Apr 23 02:01:23 PM PDT 24
Finished Apr 23 02:01:25 PM PDT 24
Peak memory 196260 kb
Host smart-84409fb7-e483-49f8-9938-34a8c22e5d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248969644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3248969644
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1750082775
Short name T910
Test name
Test status
Simulation time 101940428237 ps
CPU time 54.99 seconds
Started Apr 23 02:01:20 PM PDT 24
Finished Apr 23 02:02:16 PM PDT 24
Peak memory 200228 kb
Host smart-08571ff4-2c54-4d9f-b1bb-ac412d33a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750082775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1750082775
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.926021043
Short name T1052
Test name
Test status
Simulation time 11272025462 ps
CPU time 120.97 seconds
Started Apr 23 02:01:23 PM PDT 24
Finished Apr 23 02:03:24 PM PDT 24
Peak memory 200804 kb
Host smart-46be9331-f5f8-4251-8cc5-d2e4235f69fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926021043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.926021043
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3194893240
Short name T400
Test name
Test status
Simulation time 5181926803 ps
CPU time 36.16 seconds
Started Apr 23 02:01:22 PM PDT 24
Finished Apr 23 02:01:58 PM PDT 24
Peak memory 198984 kb
Host smart-a89ce452-1982-49bb-862f-d3a959c08727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194893240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3194893240
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1642765061
Short name T421
Test name
Test status
Simulation time 145437928809 ps
CPU time 150.09 seconds
Started Apr 23 02:01:21 PM PDT 24
Finished Apr 23 02:03:52 PM PDT 24
Peak memory 200820 kb
Host smart-a951aa10-f2f9-48c0-af2e-34b8544cdd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642765061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1642765061
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2921562463
Short name T282
Test name
Test status
Simulation time 45307904862 ps
CPU time 66.05 seconds
Started Apr 23 02:01:21 PM PDT 24
Finished Apr 23 02:02:27 PM PDT 24
Peak memory 196704 kb
Host smart-6138c53c-e85c-41bb-87a8-6f1ced22b636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921562463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2921562463
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4101111624
Short name T623
Test name
Test status
Simulation time 5683651993 ps
CPU time 8.95 seconds
Started Apr 23 02:01:19 PM PDT 24
Finished Apr 23 02:01:28 PM PDT 24
Peak memory 200652 kb
Host smart-bcd9dc03-594f-4d7f-9228-bb871b30a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101111624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4101111624
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.290982037
Short name T541
Test name
Test status
Simulation time 198680204181 ps
CPU time 676.59 seconds
Started Apr 23 02:01:26 PM PDT 24
Finished Apr 23 02:12:43 PM PDT 24
Peak memory 200856 kb
Host smart-d586cf96-e6a3-414f-8ab1-161593d1a50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290982037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.290982037
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2624490903
Short name T713
Test name
Test status
Simulation time 82748954806 ps
CPU time 1166.28 seconds
Started Apr 23 02:01:24 PM PDT 24
Finished Apr 23 02:20:51 PM PDT 24
Peak memory 217940 kb
Host smart-68bf2d7a-48e1-4c28-b758-f333550468dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624490903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2624490903
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4010853345
Short name T697
Test name
Test status
Simulation time 6761370004 ps
CPU time 15.74 seconds
Started Apr 23 02:01:23 PM PDT 24
Finished Apr 23 02:01:39 PM PDT 24
Peak memory 200168 kb
Host smart-af04b1c2-4a95-44c9-a9b7-2fdcc5f31e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010853345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4010853345
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1708884851
Short name T790
Test name
Test status
Simulation time 78810136731 ps
CPU time 111.62 seconds
Started Apr 23 02:01:19 PM PDT 24
Finished Apr 23 02:03:11 PM PDT 24
Peak memory 200788 kb
Host smart-8ba61956-6733-4b58-af1d-b8cb43ca8fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708884851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1708884851
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.561196298
Short name T25
Test name
Test status
Simulation time 11275462 ps
CPU time 0.55 seconds
Started Apr 23 02:01:29 PM PDT 24
Finished Apr 23 02:01:30 PM PDT 24
Peak memory 195680 kb
Host smart-847ed080-2bc9-40c5-a179-007b09c55e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561196298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.561196298
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2485400202
Short name T110
Test name
Test status
Simulation time 93697548770 ps
CPU time 39.17 seconds
Started Apr 23 02:01:21 PM PDT 24
Finished Apr 23 02:02:01 PM PDT 24
Peak memory 200784 kb
Host smart-fe9ce0a7-fefe-4a73-9f4b-d7aee5517bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485400202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2485400202
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4221939062
Short name T111
Test name
Test status
Simulation time 165671983639 ps
CPU time 263.55 seconds
Started Apr 23 02:01:22 PM PDT 24
Finished Apr 23 02:05:47 PM PDT 24
Peak memory 200848 kb
Host smart-7b6fffeb-2e0f-4b6a-baf9-162d2b201322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221939062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4221939062
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2152148505
Short name T527
Test name
Test status
Simulation time 11184501041 ps
CPU time 20.22 seconds
Started Apr 23 02:01:22 PM PDT 24
Finished Apr 23 02:01:43 PM PDT 24
Peak memory 197356 kb
Host smart-d39e832e-64f8-4a23-8839-2a8d383cfdc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152148505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2152148505
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2283928318
Short name T870
Test name
Test status
Simulation time 119336111815 ps
CPU time 1094.98 seconds
Started Apr 23 02:01:29 PM PDT 24
Finished Apr 23 02:19:44 PM PDT 24
Peak memory 200812 kb
Host smart-a8e67545-d54a-4c95-aa2f-c9af08fbe5a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283928318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2283928318
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1816350007
Short name T460
Test name
Test status
Simulation time 2132538340 ps
CPU time 2.37 seconds
Started Apr 23 02:01:25 PM PDT 24
Finished Apr 23 02:01:28 PM PDT 24
Peak memory 199516 kb
Host smart-eafe5b89-c55e-4011-b75d-355e9ac70ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816350007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1816350007
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2988591818
Short name T298
Test name
Test status
Simulation time 32640306848 ps
CPU time 35.48 seconds
Started Apr 23 02:01:26 PM PDT 24
Finished Apr 23 02:02:02 PM PDT 24
Peak memory 200936 kb
Host smart-cf34c5a7-4705-4c8d-ac3f-c4470ae50037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988591818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2988591818
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3227757832
Short name T466
Test name
Test status
Simulation time 13230827340 ps
CPU time 604.88 seconds
Started Apr 23 02:01:26 PM PDT 24
Finished Apr 23 02:11:31 PM PDT 24
Peak memory 200768 kb
Host smart-372e606c-3b83-448f-bc5b-aefbe8f0fbf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227757832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3227757832
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3285020762
Short name T472
Test name
Test status
Simulation time 2628504502 ps
CPU time 16.08 seconds
Started Apr 23 02:01:23 PM PDT 24
Finished Apr 23 02:01:39 PM PDT 24
Peak memory 199184 kb
Host smart-8c9b786a-9341-44ff-9c64-314291dcf950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285020762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3285020762
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.584548005
Short name T756
Test name
Test status
Simulation time 116246955162 ps
CPU time 45.36 seconds
Started Apr 23 02:01:27 PM PDT 24
Finished Apr 23 02:02:13 PM PDT 24
Peak memory 200792 kb
Host smart-dc77cd52-8799-4721-ab81-fd791ede0bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584548005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.584548005
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3284976506
Short name T522
Test name
Test status
Simulation time 46192429523 ps
CPU time 14.93 seconds
Started Apr 23 02:01:24 PM PDT 24
Finished Apr 23 02:01:40 PM PDT 24
Peak memory 196588 kb
Host smart-d214f8f7-16df-4647-aa24-dc63da2ca1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284976506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3284976506
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1818736891
Short name T423
Test name
Test status
Simulation time 572333858 ps
CPU time 1.4 seconds
Started Apr 23 02:01:20 PM PDT 24
Finished Apr 23 02:01:22 PM PDT 24
Peak memory 200364 kb
Host smart-60a9b1f3-8315-475a-b236-c8b2c3126f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818736891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1818736891
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4286392625
Short name T1118
Test name
Test status
Simulation time 125960884900 ps
CPU time 108.03 seconds
Started Apr 23 02:01:29 PM PDT 24
Finished Apr 23 02:03:18 PM PDT 24
Peak memory 200892 kb
Host smart-e64a1ab6-d857-41ed-9c9f-b5731fd1dc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286392625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4286392625
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3845888885
Short name T1099
Test name
Test status
Simulation time 193632449915 ps
CPU time 563.33 seconds
Started Apr 23 02:01:28 PM PDT 24
Finished Apr 23 02:10:51 PM PDT 24
Peak memory 229520 kb
Host smart-4ab54728-b360-4a15-bbb4-a090cc819e22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845888885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3845888885
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2659682805
Short name T642
Test name
Test status
Simulation time 900298802 ps
CPU time 3 seconds
Started Apr 23 02:01:26 PM PDT 24
Finished Apr 23 02:01:29 PM PDT 24
Peak memory 200632 kb
Host smart-8769441f-3e63-4ac5-853d-d874f356099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659682805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2659682805
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.979144852
Short name T271
Test name
Test status
Simulation time 16878952233 ps
CPU time 24.6 seconds
Started Apr 23 02:01:22 PM PDT 24
Finished Apr 23 02:01:47 PM PDT 24
Peak memory 200700 kb
Host smart-0b122681-06c6-41ff-a8a9-51903650582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979144852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.979144852
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1443268679
Short name T1040
Test name
Test status
Simulation time 21807277 ps
CPU time 0.54 seconds
Started Apr 23 02:01:36 PM PDT 24
Finished Apr 23 02:01:37 PM PDT 24
Peak memory 196124 kb
Host smart-e3bacbf5-6d02-43e7-998a-ed3efa504b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443268679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1443268679
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3662818915
Short name T647
Test name
Test status
Simulation time 34989504988 ps
CPU time 15.85 seconds
Started Apr 23 02:01:28 PM PDT 24
Finished Apr 23 02:01:44 PM PDT 24
Peak memory 200788 kb
Host smart-1d7727dc-ec37-4736-a13d-19e5b37208db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662818915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3662818915
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2880089992
Short name T45
Test name
Test status
Simulation time 7531516779 ps
CPU time 10.44 seconds
Started Apr 23 02:01:31 PM PDT 24
Finished Apr 23 02:01:42 PM PDT 24
Peak memory 200160 kb
Host smart-24a67a2f-271e-405c-9ce2-5575fea14d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880089992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2880089992
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2911066351
Short name T672
Test name
Test status
Simulation time 50127359485 ps
CPU time 23.22 seconds
Started Apr 23 02:01:32 PM PDT 24
Finished Apr 23 02:01:55 PM PDT 24
Peak memory 200748 kb
Host smart-dd6c3c90-e40b-413b-b890-091448e31dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911066351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2911066351
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2590089768
Short name T514
Test name
Test status
Simulation time 2536515963 ps
CPU time 12.24 seconds
Started Apr 23 02:01:35 PM PDT 24
Finished Apr 23 02:01:47 PM PDT 24
Peak memory 200272 kb
Host smart-12049c4d-ff1d-472c-8351-5aae9c60d840
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590089768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2590089768
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2081504397
Short name T263
Test name
Test status
Simulation time 60930529606 ps
CPU time 185.26 seconds
Started Apr 23 02:01:36 PM PDT 24
Finished Apr 23 02:04:42 PM PDT 24
Peak memory 200932 kb
Host smart-cdb39e1b-4af1-439e-a4fa-32b39a10bdb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081504397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2081504397
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3851737957
Short name T548
Test name
Test status
Simulation time 6562294653 ps
CPU time 4.56 seconds
Started Apr 23 02:01:36 PM PDT 24
Finished Apr 23 02:01:41 PM PDT 24
Peak memory 200680 kb
Host smart-5f67d8a4-8eeb-40de-a33f-efc08a2b8883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851737957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3851737957
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2692799061
Short name T450
Test name
Test status
Simulation time 8953977724 ps
CPU time 15.67 seconds
Started Apr 23 02:01:32 PM PDT 24
Finished Apr 23 02:01:48 PM PDT 24
Peak memory 201032 kb
Host smart-595507ac-841a-4f9d-a866-54b87a753c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692799061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2692799061
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.368179593
Short name T312
Test name
Test status
Simulation time 1679391924 ps
CPU time 82.14 seconds
Started Apr 23 02:01:38 PM PDT 24
Finished Apr 23 02:03:01 PM PDT 24
Peak memory 200668 kb
Host smart-f43dc4fa-eed3-4ecd-a6b9-dcc3dc4618ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368179593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.368179593
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3070518120
Short name T1010
Test name
Test status
Simulation time 2768618350 ps
CPU time 7 seconds
Started Apr 23 02:01:34 PM PDT 24
Finished Apr 23 02:01:42 PM PDT 24
Peak memory 200068 kb
Host smart-834a82a6-11f0-42e4-83e0-02aa5d3d29a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070518120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3070518120
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1760746519
Short name T151
Test name
Test status
Simulation time 37457013306 ps
CPU time 19.69 seconds
Started Apr 23 02:01:37 PM PDT 24
Finished Apr 23 02:01:57 PM PDT 24
Peak memory 200824 kb
Host smart-1331101a-6985-4dcc-b36f-dbd14fe4d1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760746519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1760746519
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2420590338
Short name T1116
Test name
Test status
Simulation time 4010907056 ps
CPU time 2.22 seconds
Started Apr 23 02:01:31 PM PDT 24
Finished Apr 23 02:01:34 PM PDT 24
Peak memory 197228 kb
Host smart-5fb7d226-8285-489b-adbe-19eb5e2981fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420590338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2420590338
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.216531474
Short name T727
Test name
Test status
Simulation time 1081185977 ps
CPU time 1.01 seconds
Started Apr 23 02:01:29 PM PDT 24
Finished Apr 23 02:01:30 PM PDT 24
Peak memory 199108 kb
Host smart-2579330f-e037-4cfd-9523-2bee6a4074f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216531474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.216531474
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.251496575
Short name T832
Test name
Test status
Simulation time 505446261505 ps
CPU time 229.92 seconds
Started Apr 23 02:01:39 PM PDT 24
Finished Apr 23 02:05:30 PM PDT 24
Peak memory 200840 kb
Host smart-be9e8d78-f2af-4683-b37e-52781499f836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251496575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.251496575
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4290856764
Short name T1004
Test name
Test status
Simulation time 1124785190 ps
CPU time 2.67 seconds
Started Apr 23 02:01:39 PM PDT 24
Finished Apr 23 02:01:42 PM PDT 24
Peak memory 199548 kb
Host smart-9c9ae371-1799-4ad1-bbdd-bbb17402326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290856764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4290856764
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.251112695
Short name T669
Test name
Test status
Simulation time 8282970603 ps
CPU time 6.97 seconds
Started Apr 23 02:01:27 PM PDT 24
Finished Apr 23 02:01:34 PM PDT 24
Peak memory 198064 kb
Host smart-9539c0da-d8fb-4103-bab7-03660bf2ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251112695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.251112695
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3199761922
Short name T402
Test name
Test status
Simulation time 22052099 ps
CPU time 0.55 seconds
Started Apr 23 02:01:43 PM PDT 24
Finished Apr 23 02:01:44 PM PDT 24
Peak memory 196216 kb
Host smart-ea0f2246-9c47-4c82-9df8-beac41735285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199761922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3199761922
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.435003568
Short name T145
Test name
Test status
Simulation time 98824944067 ps
CPU time 46.92 seconds
Started Apr 23 02:01:40 PM PDT 24
Finished Apr 23 02:02:27 PM PDT 24
Peak memory 200780 kb
Host smart-ca765035-0bba-442e-b88c-32954269f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435003568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.435003568
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1200463516
Short name T49
Test name
Test status
Simulation time 39060770726 ps
CPU time 16.29 seconds
Started Apr 23 02:01:42 PM PDT 24
Finished Apr 23 02:01:59 PM PDT 24
Peak memory 200864 kb
Host smart-4fc1e729-6306-4639-953d-ab72b27f634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200463516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1200463516
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3147153324
Short name T763
Test name
Test status
Simulation time 24438821577 ps
CPU time 40.96 seconds
Started Apr 23 02:01:40 PM PDT 24
Finished Apr 23 02:02:22 PM PDT 24
Peak memory 200768 kb
Host smart-ac76c5b6-b9fb-4de9-8e11-93176f036ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147153324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3147153324
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2054749096
Short name T1073
Test name
Test status
Simulation time 23885704231 ps
CPU time 9.12 seconds
Started Apr 23 02:01:45 PM PDT 24
Finished Apr 23 02:01:54 PM PDT 24
Peak memory 199620 kb
Host smart-b7f50066-69b7-425e-a0ed-32165c7cbe59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054749096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2054749096
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3023450508
Short name T823
Test name
Test status
Simulation time 76322070959 ps
CPU time 706.25 seconds
Started Apr 23 02:01:45 PM PDT 24
Finished Apr 23 02:13:31 PM PDT 24
Peak memory 200960 kb
Host smart-1eba836e-1a52-4833-ba71-6317acc6151e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023450508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3023450508
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2681347197
Short name T5
Test name
Test status
Simulation time 4104024700 ps
CPU time 7.23 seconds
Started Apr 23 02:01:48 PM PDT 24
Finished Apr 23 02:01:55 PM PDT 24
Peak memory 199584 kb
Host smart-dba0a41b-3e02-44d7-9e6c-c0c7d37c4442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681347197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2681347197
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2163767285
Short name T468
Test name
Test status
Simulation time 45554219386 ps
CPU time 71.49 seconds
Started Apr 23 02:01:45 PM PDT 24
Finished Apr 23 02:02:57 PM PDT 24
Peak memory 198016 kb
Host smart-ffdcfc9b-113d-4b3b-a49d-8048c651901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163767285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2163767285
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4227355165
Short name T77
Test name
Test status
Simulation time 12014002107 ps
CPU time 163.42 seconds
Started Apr 23 02:01:49 PM PDT 24
Finished Apr 23 02:04:33 PM PDT 24
Peak memory 200100 kb
Host smart-dd757fc1-c634-4d34-89d5-c4f64aa6126b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227355165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4227355165
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2185163104
Short name T608
Test name
Test status
Simulation time 2112585458 ps
CPU time 6.79 seconds
Started Apr 23 02:01:42 PM PDT 24
Finished Apr 23 02:01:49 PM PDT 24
Peak memory 199436 kb
Host smart-abb25349-0cce-4748-b686-5007ea34a869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185163104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2185163104
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4033025611
Short name T1115
Test name
Test status
Simulation time 18967447318 ps
CPU time 33.18 seconds
Started Apr 23 02:01:45 PM PDT 24
Finished Apr 23 02:02:19 PM PDT 24
Peak memory 200692 kb
Host smart-e7af448b-60f9-4006-a359-d2aae23033f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033025611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4033025611
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2296594959
Short name T953
Test name
Test status
Simulation time 4133239817 ps
CPU time 1.47 seconds
Started Apr 23 02:01:46 PM PDT 24
Finished Apr 23 02:01:47 PM PDT 24
Peak memory 196884 kb
Host smart-43eed603-38e8-4305-99e4-0873c8759ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296594959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2296594959
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1421717524
Short name T641
Test name
Test status
Simulation time 428789782 ps
CPU time 2.04 seconds
Started Apr 23 02:01:37 PM PDT 24
Finished Apr 23 02:01:40 PM PDT 24
Peak memory 199104 kb
Host smart-cf18fdd4-9340-46f9-ba3b-cce2cf04f8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421717524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1421717524
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3222487456
Short name T1078
Test name
Test status
Simulation time 231018443029 ps
CPU time 1084.22 seconds
Started Apr 23 02:01:44 PM PDT 24
Finished Apr 23 02:19:48 PM PDT 24
Peak memory 200772 kb
Host smart-b6d292a5-1c66-4397-bf75-a9f00da768ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222487456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3222487456
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3450360962
Short name T58
Test name
Test status
Simulation time 66404264065 ps
CPU time 268.11 seconds
Started Apr 23 02:01:49 PM PDT 24
Finished Apr 23 02:06:18 PM PDT 24
Peak memory 215884 kb
Host smart-233e454b-62f0-4cbc-b58b-7ad1c52b498b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450360962 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3450360962
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2777564079
Short name T1151
Test name
Test status
Simulation time 1121321218 ps
CPU time 3.56 seconds
Started Apr 23 02:01:44 PM PDT 24
Finished Apr 23 02:01:48 PM PDT 24
Peak memory 200740 kb
Host smart-6310dbc5-fe72-4fe5-bbc5-b44bb66efb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777564079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2777564079
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3237172462
Short name T593
Test name
Test status
Simulation time 55304535261 ps
CPU time 103.13 seconds
Started Apr 23 02:01:45 PM PDT 24
Finished Apr 23 02:03:29 PM PDT 24
Peak memory 200816 kb
Host smart-77e26229-8147-470f-a52e-8edcad2dfdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237172462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3237172462
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3641386939
Short name T346
Test name
Test status
Simulation time 28564125 ps
CPU time 0.54 seconds
Started Apr 23 02:01:55 PM PDT 24
Finished Apr 23 02:01:56 PM PDT 24
Peak memory 195104 kb
Host smart-83bcca3e-6efc-4944-a3fb-b5b688cd8a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641386939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3641386939
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2654423933
Short name T462
Test name
Test status
Simulation time 51322715050 ps
CPU time 33.56 seconds
Started Apr 23 02:01:47 PM PDT 24
Finished Apr 23 02:02:20 PM PDT 24
Peak memory 200660 kb
Host smart-a2a2731e-c214-487c-9264-36b49209dff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654423933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2654423933
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.4219450360
Short name T999
Test name
Test status
Simulation time 62186588885 ps
CPU time 30.14 seconds
Started Apr 23 02:01:52 PM PDT 24
Finished Apr 23 02:02:23 PM PDT 24
Peak memory 200824 kb
Host smart-79fb9d70-d2cf-405a-8e45-fe936900c14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219450360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4219450360
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.370484596
Short name T951
Test name
Test status
Simulation time 204932782156 ps
CPU time 90.12 seconds
Started Apr 23 02:01:51 PM PDT 24
Finished Apr 23 02:03:22 PM PDT 24
Peak memory 200768 kb
Host smart-f09b3914-ff51-4c88-8edb-6bfd9916a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370484596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.370484596
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.609196946
Short name T322
Test name
Test status
Simulation time 47022716849 ps
CPU time 34.78 seconds
Started Apr 23 02:01:52 PM PDT 24
Finished Apr 23 02:02:27 PM PDT 24
Peak memory 200780 kb
Host smart-ca906729-c546-4844-a267-3f438e67bf01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609196946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.609196946
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1739958405
Short name T323
Test name
Test status
Simulation time 72909213006 ps
CPU time 626.12 seconds
Started Apr 23 02:01:55 PM PDT 24
Finished Apr 23 02:12:22 PM PDT 24
Peak memory 200800 kb
Host smart-90674f83-5f1f-47b9-a5ce-fcd68b9fa858
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739958405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1739958405
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1742781725
Short name T940
Test name
Test status
Simulation time 1389846672 ps
CPU time 2.57 seconds
Started Apr 23 02:01:53 PM PDT 24
Finished Apr 23 02:01:56 PM PDT 24
Peak memory 199464 kb
Host smart-3f1e14ac-2f30-4e0a-bfd8-1232450a6643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742781725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1742781725
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.873739838
Short name T788
Test name
Test status
Simulation time 34987984247 ps
CPU time 15.1 seconds
Started Apr 23 02:01:52 PM PDT 24
Finished Apr 23 02:02:07 PM PDT 24
Peak memory 195424 kb
Host smart-12eaab30-00cd-4a16-92bb-144fc85e6e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873739838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.873739838
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2382024910
Short name T41
Test name
Test status
Simulation time 15234797765 ps
CPU time 167.77 seconds
Started Apr 23 02:01:55 PM PDT 24
Finished Apr 23 02:04:43 PM PDT 24
Peak memory 200796 kb
Host smart-a2c152a2-9454-4e6a-99eb-b063641f2156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382024910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2382024910
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.173126058
Short name T430
Test name
Test status
Simulation time 4345390908 ps
CPU time 2.74 seconds
Started Apr 23 02:01:52 PM PDT 24
Finished Apr 23 02:01:55 PM PDT 24
Peak memory 198988 kb
Host smart-55cabc86-ab63-4564-9b6f-24eaa0ec430f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173126058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.173126058
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.325841092
Short name T1106
Test name
Test status
Simulation time 35782426556 ps
CPU time 60.77 seconds
Started Apr 23 02:01:52 PM PDT 24
Finished Apr 23 02:02:54 PM PDT 24
Peak memory 197216 kb
Host smart-5f53b66f-d3c8-40a8-b4b8-3ebdafe90f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325841092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.325841092
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.4113353278
Short name T38
Test name
Test status
Simulation time 1016204609 ps
CPU time 1.89 seconds
Started Apr 23 02:01:49 PM PDT 24
Finished Apr 23 02:01:52 PM PDT 24
Peak memory 199636 kb
Host smart-9123267e-6fb0-4b11-818d-ca80f7a754af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113353278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4113353278
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2352975071
Short name T982
Test name
Test status
Simulation time 301921831966 ps
CPU time 486.91 seconds
Started Apr 23 02:01:57 PM PDT 24
Finished Apr 23 02:10:04 PM PDT 24
Peak memory 200820 kb
Host smart-9b748e2d-947a-4659-a6be-62463aa203ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352975071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2352975071
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1962647729
Short name T117
Test name
Test status
Simulation time 28876465295 ps
CPU time 255.03 seconds
Started Apr 23 02:01:54 PM PDT 24
Finished Apr 23 02:06:09 PM PDT 24
Peak memory 216456 kb
Host smart-2185f744-a2d5-4068-a3b5-345b71044134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962647729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1962647729
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1049223405
Short name T904
Test name
Test status
Simulation time 977074061 ps
CPU time 3.27 seconds
Started Apr 23 02:01:51 PM PDT 24
Finished Apr 23 02:01:55 PM PDT 24
Peak memory 200588 kb
Host smart-5673b4ee-501f-4c7f-8656-b3961c735a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049223405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1049223405
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1394300036
Short name T637
Test name
Test status
Simulation time 47477994097 ps
CPU time 76.32 seconds
Started Apr 23 02:01:48 PM PDT 24
Finished Apr 23 02:03:05 PM PDT 24
Peak memory 200696 kb
Host smart-f5d893ff-0b52-4c4e-9228-983fcc0ce7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394300036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1394300036
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.147720461
Short name T474
Test name
Test status
Simulation time 19301185 ps
CPU time 0.53 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:58:29 PM PDT 24
Peak memory 196096 kb
Host smart-12d898fb-6e46-479b-b04a-4517b179150a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147720461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.147720461
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3188469482
Short name T1060
Test name
Test status
Simulation time 21426841444 ps
CPU time 37.82 seconds
Started Apr 23 01:58:20 PM PDT 24
Finished Apr 23 01:58:59 PM PDT 24
Peak memory 200860 kb
Host smart-2f89b391-fa8e-428a-a80a-85631d2c5019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188469482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3188469482
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2764305502
Short name T636
Test name
Test status
Simulation time 163722043960 ps
CPU time 62.76 seconds
Started Apr 23 01:58:22 PM PDT 24
Finished Apr 23 01:59:25 PM PDT 24
Peak memory 200772 kb
Host smart-fe706e53-69c9-4f56-bdfb-cf9b44677d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764305502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2764305502
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3566336067
Short name T1098
Test name
Test status
Simulation time 15353454200 ps
CPU time 31.59 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:59:00 PM PDT 24
Peak memory 200804 kb
Host smart-8efa6f07-0c50-4380-a58d-52c5044ee3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566336067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3566336067
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.671194289
Short name T520
Test name
Test status
Simulation time 260463561696 ps
CPU time 120 seconds
Started Apr 23 01:58:21 PM PDT 24
Finished Apr 23 02:00:22 PM PDT 24
Peak memory 200688 kb
Host smart-3943eac0-f697-4545-95a1-0dfbb134a6ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671194289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.671194289
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_loopback.3657367655
Short name T804
Test name
Test status
Simulation time 2682531372 ps
CPU time 5.94 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:58:35 PM PDT 24
Peak memory 200780 kb
Host smart-b98735d7-5ea9-4095-9003-3552692b3f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657367655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3657367655
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1767586115
Short name T743
Test name
Test status
Simulation time 37233148931 ps
CPU time 35.82 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 01:59:01 PM PDT 24
Peak memory 201088 kb
Host smart-f030adcd-b030-4bee-870f-5a513c27cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767586115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1767586115
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2741202266
Short name T283
Test name
Test status
Simulation time 23325318671 ps
CPU time 872.49 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 02:13:02 PM PDT 24
Peak memory 200816 kb
Host smart-81bdb840-19e6-40b6-823c-7e2625b688fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741202266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2741202266
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1539401557
Short name T464
Test name
Test status
Simulation time 6007515516 ps
CPU time 47.84 seconds
Started Apr 23 01:58:21 PM PDT 24
Finished Apr 23 01:59:10 PM PDT 24
Peak memory 200060 kb
Host smart-4279dda2-cf58-481b-b048-c878640491d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539401557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1539401557
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1285466696
Short name T678
Test name
Test status
Simulation time 36987380842 ps
CPU time 55.06 seconds
Started Apr 23 01:58:22 PM PDT 24
Finished Apr 23 01:59:17 PM PDT 24
Peak memory 197224 kb
Host smart-736231c7-f9e2-460a-ab93-f7c4fe45d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285466696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1285466696
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_smoke.1930073071
Short name T632
Test name
Test status
Simulation time 492367996 ps
CPU time 2.45 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 01:58:28 PM PDT 24
Peak memory 200644 kb
Host smart-a22ed801-97bf-47f7-a4b6-809ed8ad9a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930073071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1930073071
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1222112399
Short name T1056
Test name
Test status
Simulation time 44271613235 ps
CPU time 487.63 seconds
Started Apr 23 01:58:21 PM PDT 24
Finished Apr 23 02:06:29 PM PDT 24
Peak memory 217536 kb
Host smart-f35d730f-d20b-40a4-a488-f184a142db1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222112399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1222112399
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.464076102
Short name T741
Test name
Test status
Simulation time 8059268918 ps
CPU time 11.47 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 01:58:41 PM PDT 24
Peak memory 200308 kb
Host smart-91fc88b0-5490-4011-aecf-aacf81258021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464076102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.464076102
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.908932371
Short name T616
Test name
Test status
Simulation time 198979074248 ps
CPU time 42.63 seconds
Started Apr 23 01:58:21 PM PDT 24
Finished Apr 23 01:59:04 PM PDT 24
Peak memory 200872 kb
Host smart-cac42c34-f8e0-4feb-8642-6e5826db8a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908932371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.908932371
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3749920589
Short name T345
Test name
Test status
Simulation time 34841075 ps
CPU time 0.54 seconds
Started Apr 23 02:02:06 PM PDT 24
Finished Apr 23 02:02:07 PM PDT 24
Peak memory 195152 kb
Host smart-71d8a126-e7f6-4f72-9644-ba06eeceaae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749920589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3749920589
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.688214498
Short name T676
Test name
Test status
Simulation time 52125543389 ps
CPU time 103.54 seconds
Started Apr 23 02:01:53 PM PDT 24
Finished Apr 23 02:03:37 PM PDT 24
Peak memory 200836 kb
Host smart-c1dba68b-84e2-4293-b38c-4f021f280ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688214498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.688214498
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1963692276
Short name T820
Test name
Test status
Simulation time 60832647145 ps
CPU time 53.07 seconds
Started Apr 23 02:01:53 PM PDT 24
Finished Apr 23 02:02:47 PM PDT 24
Peak memory 200808 kb
Host smart-512daf7b-9656-4e59-a563-22f72d1d260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963692276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1963692276
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2014452952
Short name T985
Test name
Test status
Simulation time 147034572589 ps
CPU time 25.58 seconds
Started Apr 23 02:01:57 PM PDT 24
Finished Apr 23 02:02:23 PM PDT 24
Peak memory 200940 kb
Host smart-0a4ef189-bcd9-4300-b109-d12d438b1808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014452952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2014452952
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1530939897
Short name T913
Test name
Test status
Simulation time 17981238217 ps
CPU time 39.09 seconds
Started Apr 23 02:01:57 PM PDT 24
Finished Apr 23 02:02:36 PM PDT 24
Peak memory 200756 kb
Host smart-c0167ad0-ea20-41c1-b1c7-7919377685d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530939897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1530939897
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2321759869
Short name T1085
Test name
Test status
Simulation time 161951692955 ps
CPU time 846.95 seconds
Started Apr 23 02:02:04 PM PDT 24
Finished Apr 23 02:16:12 PM PDT 24
Peak memory 200868 kb
Host smart-0450dc1c-3a87-4717-8213-4e1fe856841b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321759869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2321759869
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.26567979
Short name T1138
Test name
Test status
Simulation time 5644849401 ps
CPU time 7.16 seconds
Started Apr 23 02:02:00 PM PDT 24
Finished Apr 23 02:02:08 PM PDT 24
Peak memory 200088 kb
Host smart-6323fc8f-f018-47f2-8590-6c06929b8355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26567979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.26567979
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1334275039
Short name T390
Test name
Test status
Simulation time 17594509930 ps
CPU time 26.33 seconds
Started Apr 23 02:01:57 PM PDT 24
Finished Apr 23 02:02:24 PM PDT 24
Peak memory 199884 kb
Host smart-81d20adb-2ad0-4255-ac40-225d34f8088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334275039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1334275039
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1065276271
Short name T643
Test name
Test status
Simulation time 12799558315 ps
CPU time 623.15 seconds
Started Apr 23 02:02:00 PM PDT 24
Finished Apr 23 02:12:24 PM PDT 24
Peak memory 200824 kb
Host smart-44f27b53-b0b9-4ece-b303-323f5e56276c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065276271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1065276271
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1172663355
Short name T824
Test name
Test status
Simulation time 3609619300 ps
CPU time 8.61 seconds
Started Apr 23 02:01:56 PM PDT 24
Finished Apr 23 02:02:05 PM PDT 24
Peak memory 200076 kb
Host smart-f0ff5f63-30e0-4e29-aeb4-3d82982fc7a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172663355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1172663355
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3709725962
Short name T703
Test name
Test status
Simulation time 139937786566 ps
CPU time 64.85 seconds
Started Apr 23 02:02:00 PM PDT 24
Finished Apr 23 02:03:06 PM PDT 24
Peak memory 200672 kb
Host smart-a324e8c3-8f5d-4d10-a94f-41a0bad925de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709725962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3709725962
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.835070360
Short name T590
Test name
Test status
Simulation time 1869784240 ps
CPU time 3.37 seconds
Started Apr 23 02:02:01 PM PDT 24
Finished Apr 23 02:02:04 PM PDT 24
Peak memory 196196 kb
Host smart-97c9f80f-cf5e-4410-8ca5-cc6672b947f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835070360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.835070360
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.683984667
Short name T1072
Test name
Test status
Simulation time 741618093 ps
CPU time 2.02 seconds
Started Apr 23 02:01:54 PM PDT 24
Finished Apr 23 02:01:56 PM PDT 24
Peak memory 199236 kb
Host smart-d54f582d-8d94-4829-9958-c4f58bb86a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683984667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.683984667
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2868209008
Short name T309
Test name
Test status
Simulation time 242090022666 ps
CPU time 398.17 seconds
Started Apr 23 02:02:05 PM PDT 24
Finished Apr 23 02:08:44 PM PDT 24
Peak memory 209104 kb
Host smart-cdf568bf-d774-4cdb-a309-b0c24915e7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868209008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2868209008
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2616529930
Short name T819
Test name
Test status
Simulation time 109490649927 ps
CPU time 609 seconds
Started Apr 23 02:02:05 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 209536 kb
Host smart-dac74712-e547-416d-94a8-2068a7d88ec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616529930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2616529930
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3145802452
Short name T502
Test name
Test status
Simulation time 2635949441 ps
CPU time 1.96 seconds
Started Apr 23 02:02:04 PM PDT 24
Finished Apr 23 02:02:06 PM PDT 24
Peak memory 199664 kb
Host smart-d7cd5657-226f-4612-b199-a44793f5c8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145802452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3145802452
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2973852952
Short name T300
Test name
Test status
Simulation time 63565158104 ps
CPU time 104.85 seconds
Started Apr 23 02:01:54 PM PDT 24
Finished Apr 23 02:03:40 PM PDT 24
Peak memory 200796 kb
Host smart-73216241-486d-49d0-944e-ddf8d55efebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973852952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2973852952
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1227844189
Short name T555
Test name
Test status
Simulation time 41003294 ps
CPU time 0.55 seconds
Started Apr 23 02:02:13 PM PDT 24
Finished Apr 23 02:02:14 PM PDT 24
Peak memory 196240 kb
Host smart-d2f9b610-e4b6-4206-9964-ed3db41fbb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227844189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1227844189
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1793083586
Short name T538
Test name
Test status
Simulation time 53728266686 ps
CPU time 91.87 seconds
Started Apr 23 02:02:07 PM PDT 24
Finished Apr 23 02:03:39 PM PDT 24
Peak memory 200728 kb
Host smart-edd1b44e-a4c5-482c-ba80-3be7c69ea0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793083586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1793083586
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.390097941
Short name T976
Test name
Test status
Simulation time 24741062172 ps
CPU time 52.46 seconds
Started Apr 23 02:02:06 PM PDT 24
Finished Apr 23 02:02:59 PM PDT 24
Peak memory 200512 kb
Host smart-5c6a80ea-8c42-495e-b34b-623f1c825577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390097941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.390097941
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2477151010
Short name T1030
Test name
Test status
Simulation time 121251595562 ps
CPU time 45.64 seconds
Started Apr 23 02:02:07 PM PDT 24
Finished Apr 23 02:02:53 PM PDT 24
Peak memory 200840 kb
Host smart-eacbe0f6-c3f6-4402-b97e-551840543823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477151010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2477151010
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.773942874
Short name T465
Test name
Test status
Simulation time 8371787599 ps
CPU time 15.45 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:02:30 PM PDT 24
Peak memory 197480 kb
Host smart-8119e595-1f7d-4790-af12-547967fb2d28
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773942874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.773942874
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.659655884
Short name T675
Test name
Test status
Simulation time 65968262781 ps
CPU time 257.82 seconds
Started Apr 23 02:02:11 PM PDT 24
Finished Apr 23 02:06:29 PM PDT 24
Peak memory 200828 kb
Host smart-8dee13f9-1273-4643-9040-7dbdf8c4b663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659655884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.659655884
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1106908342
Short name T476
Test name
Test status
Simulation time 7058311401 ps
CPU time 25.83 seconds
Started Apr 23 02:02:13 PM PDT 24
Finished Apr 23 02:02:40 PM PDT 24
Peak memory 200864 kb
Host smart-38752b25-437a-4f23-a17a-6c4a3e42896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106908342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1106908342
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.682066139
Short name T644
Test name
Test status
Simulation time 180693512632 ps
CPU time 74.61 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:03:29 PM PDT 24
Peak memory 217368 kb
Host smart-933f0c85-809e-4edd-957a-1ae1d37421e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682066139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.682066139
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1388849051
Short name T1140
Test name
Test status
Simulation time 9678528315 ps
CPU time 99.07 seconds
Started Apr 23 02:02:16 PM PDT 24
Finished Apr 23 02:03:56 PM PDT 24
Peak memory 200768 kb
Host smart-092d6123-5385-43a0-8818-3bf28d7482a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388849051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1388849051
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.122169717
Short name T106
Test name
Test status
Simulation time 2111393824 ps
CPU time 7.79 seconds
Started Apr 23 02:02:10 PM PDT 24
Finished Apr 23 02:02:18 PM PDT 24
Peak memory 198688 kb
Host smart-12683bd4-be6f-41ec-af5c-c774f47bd0cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122169717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.122169717
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3661294339
Short name T772
Test name
Test status
Simulation time 70888032798 ps
CPU time 137.58 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:04:33 PM PDT 24
Peak memory 200844 kb
Host smart-10de9a9f-ac0b-4e1f-80b9-2c4ca02fb6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661294339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3661294339
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.809469138
Short name T595
Test name
Test status
Simulation time 3514654948 ps
CPU time 1.25 seconds
Started Apr 23 02:02:11 PM PDT 24
Finished Apr 23 02:02:12 PM PDT 24
Peak memory 197140 kb
Host smart-ece4f0fc-dbba-4920-ad2d-fe992d993569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809469138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.809469138
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3842841168
Short name T656
Test name
Test status
Simulation time 11143089005 ps
CPU time 7.91 seconds
Started Apr 23 02:02:04 PM PDT 24
Finished Apr 23 02:02:12 PM PDT 24
Peak memory 200720 kb
Host smart-2367d699-935f-41e9-a941-d37ccfc9b06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842841168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3842841168
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3454473179
Short name T330
Test name
Test status
Simulation time 19397748484 ps
CPU time 232.73 seconds
Started Apr 23 02:02:11 PM PDT 24
Finished Apr 23 02:06:04 PM PDT 24
Peak memory 209100 kb
Host smart-8a17a2eb-9a10-417b-a3a7-d8db84289112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454473179 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3454473179
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2574957083
Short name T742
Test name
Test status
Simulation time 1450355551 ps
CPU time 3.04 seconds
Started Apr 23 02:02:11 PM PDT 24
Finished Apr 23 02:02:15 PM PDT 24
Peak memory 200484 kb
Host smart-32aa51f2-cede-4142-817b-44d90125e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574957083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2574957083
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2725090371
Short name T480
Test name
Test status
Simulation time 65640239628 ps
CPU time 203.2 seconds
Started Apr 23 02:02:05 PM PDT 24
Finished Apr 23 02:05:29 PM PDT 24
Peak memory 200788 kb
Host smart-952d2f0f-8881-4823-9f11-d863a6860858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725090371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2725090371
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3903927794
Short name T1015
Test name
Test status
Simulation time 14850627 ps
CPU time 0.55 seconds
Started Apr 23 02:02:20 PM PDT 24
Finished Apr 23 02:02:21 PM PDT 24
Peak memory 195156 kb
Host smart-090d8873-4508-4486-b0fe-12d6e41a483e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903927794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3903927794
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2182348429
Short name T178
Test name
Test status
Simulation time 177222335097 ps
CPU time 39.14 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:02:54 PM PDT 24
Peak memory 200888 kb
Host smart-51ca61b1-43fa-4167-b9b8-bf81279903ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182348429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2182348429
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1728151706
Short name T503
Test name
Test status
Simulation time 40116954712 ps
CPU time 31.28 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:02:46 PM PDT 24
Peak memory 198952 kb
Host smart-45e26030-7d5d-4b03-a321-8f5ce09986e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728151706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1728151706
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.790115156
Short name T1095
Test name
Test status
Simulation time 162836513182 ps
CPU time 78.72 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:03:33 PM PDT 24
Peak memory 200772 kb
Host smart-b548e65d-ffa7-49d3-a94a-3a6a4e674b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790115156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.790115156
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2871276585
Short name T328
Test name
Test status
Simulation time 6842535287 ps
CPU time 3.22 seconds
Started Apr 23 02:02:15 PM PDT 24
Finished Apr 23 02:02:19 PM PDT 24
Peak memory 197492 kb
Host smart-96063199-cd4b-4671-ad3f-6d602965d81a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871276585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2871276585
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4200282780
Short name T926
Test name
Test status
Simulation time 40050938030 ps
CPU time 71.9 seconds
Started Apr 23 02:02:18 PM PDT 24
Finished Apr 23 02:03:30 PM PDT 24
Peak memory 200824 kb
Host smart-7ddac94b-ac85-4820-930c-bf56b927118f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200282780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4200282780
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.4293510746
Short name T937
Test name
Test status
Simulation time 4533212244 ps
CPU time 3.29 seconds
Started Apr 23 02:02:17 PM PDT 24
Finished Apr 23 02:02:20 PM PDT 24
Peak memory 200688 kb
Host smart-329b7364-f246-4d1d-9d00-57f2e9186aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293510746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4293510746
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2898393098
Short name T827
Test name
Test status
Simulation time 15037885312 ps
CPU time 8.95 seconds
Started Apr 23 02:02:19 PM PDT 24
Finished Apr 23 02:02:28 PM PDT 24
Peak memory 200996 kb
Host smart-eea72240-6f26-43ea-8bf3-918849ba2e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898393098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2898393098
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3789093290
Short name T1146
Test name
Test status
Simulation time 26716711848 ps
CPU time 401.37 seconds
Started Apr 23 02:02:17 PM PDT 24
Finished Apr 23 02:08:59 PM PDT 24
Peak memory 200840 kb
Host smart-ba48cbf8-2f77-4764-aaf4-98013ecbbc73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789093290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3789093290
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3613474492
Short name T367
Test name
Test status
Simulation time 3985257513 ps
CPU time 33.71 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:02:48 PM PDT 24
Peak memory 199104 kb
Host smart-7764ba78-e489-4fbf-8269-833470123afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613474492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3613474492
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.100839675
Short name T414
Test name
Test status
Simulation time 238681658758 ps
CPU time 77.07 seconds
Started Apr 23 02:02:16 PM PDT 24
Finished Apr 23 02:03:33 PM PDT 24
Peak memory 200768 kb
Host smart-f58ce3bf-d110-4a5b-9256-9119a3edde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100839675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.100839675
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3551969105
Short name T1107
Test name
Test status
Simulation time 3537000150 ps
CPU time 5.99 seconds
Started Apr 23 02:02:16 PM PDT 24
Finished Apr 23 02:02:23 PM PDT 24
Peak memory 197120 kb
Host smart-829787e2-3f8b-4e6d-87cd-42a4b64fc887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551969105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3551969105
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.533874316
Short name T774
Test name
Test status
Simulation time 883914128 ps
CPU time 3.49 seconds
Started Apr 23 02:02:14 PM PDT 24
Finished Apr 23 02:02:18 PM PDT 24
Peak memory 199020 kb
Host smart-0af09dec-13d4-47e0-80dd-9295c985a6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533874316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.533874316
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3541286201
Short name T335
Test name
Test status
Simulation time 272146929354 ps
CPU time 1556.09 seconds
Started Apr 23 02:02:20 PM PDT 24
Finished Apr 23 02:28:16 PM PDT 24
Peak memory 217272 kb
Host smart-9ae41b03-1d78-4e7a-b982-390922919c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541286201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3541286201
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2840812257
Short name T837
Test name
Test status
Simulation time 1206972715 ps
CPU time 2.3 seconds
Started Apr 23 02:02:16 PM PDT 24
Finished Apr 23 02:02:19 PM PDT 24
Peak memory 198960 kb
Host smart-20aec8fd-34a8-45a5-82ab-c972e8f6d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840812257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2840812257
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.26075850
Short name T1022
Test name
Test status
Simulation time 9222282732 ps
CPU time 15.77 seconds
Started Apr 23 02:02:13 PM PDT 24
Finished Apr 23 02:02:29 PM PDT 24
Peak memory 198420 kb
Host smart-f4101edc-6792-4b78-bdd5-994f166f2076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26075850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.26075850
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.139903550
Short name T353
Test name
Test status
Simulation time 37611934 ps
CPU time 0.54 seconds
Started Apr 23 02:02:28 PM PDT 24
Finished Apr 23 02:02:29 PM PDT 24
Peak memory 195076 kb
Host smart-79dbc8cf-faa3-4415-a95e-800b7a650fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139903550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.139903550
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2397028936
Short name T525
Test name
Test status
Simulation time 43148580658 ps
CPU time 19.86 seconds
Started Apr 23 02:02:22 PM PDT 24
Finished Apr 23 02:02:42 PM PDT 24
Peak memory 200776 kb
Host smart-5e85a038-4d54-4d04-bcf1-e3d07e72a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397028936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2397028936
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3043324927
Short name T449
Test name
Test status
Simulation time 105080614416 ps
CPU time 52.29 seconds
Started Apr 23 02:02:20 PM PDT 24
Finished Apr 23 02:03:12 PM PDT 24
Peak memory 200840 kb
Host smart-452a63c8-48e2-4be7-a8e7-137907ba9284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043324927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3043324927
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3854385490
Short name T542
Test name
Test status
Simulation time 25435530380 ps
CPU time 11.84 seconds
Started Apr 23 02:02:22 PM PDT 24
Finished Apr 23 02:02:35 PM PDT 24
Peak memory 200468 kb
Host smart-226c75da-a63d-4f44-b1c2-9c4472116cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854385490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3854385490
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2407251926
Short name T325
Test name
Test status
Simulation time 114644261009 ps
CPU time 29.53 seconds
Started Apr 23 02:02:24 PM PDT 24
Finished Apr 23 02:02:54 PM PDT 24
Peak memory 196864 kb
Host smart-320714f1-b578-4f45-ab81-e1f3e35c2e5d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407251926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2407251926
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.724552748
Short name T453
Test name
Test status
Simulation time 96096988363 ps
CPU time 554.3 seconds
Started Apr 23 02:02:28 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 200848 kb
Host smart-5f97ad7c-22fa-420b-accf-ba59e99cf9b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724552748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.724552748
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3718044869
Short name T42
Test name
Test status
Simulation time 328833504 ps
CPU time 0.8 seconds
Started Apr 23 02:02:26 PM PDT 24
Finished Apr 23 02:02:27 PM PDT 24
Peak memory 196428 kb
Host smart-b6462684-2767-45d0-a6cb-e538e7a7e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718044869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3718044869
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.757571524
Short name T352
Test name
Test status
Simulation time 10386400024 ps
CPU time 19.52 seconds
Started Apr 23 02:02:23 PM PDT 24
Finished Apr 23 02:02:43 PM PDT 24
Peak memory 199432 kb
Host smart-216dcb4f-1ed0-4700-8aeb-531409057a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757571524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.757571524
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.162383609
Short name T786
Test name
Test status
Simulation time 26078389241 ps
CPU time 1306.1 seconds
Started Apr 23 02:02:26 PM PDT 24
Finished Apr 23 02:24:13 PM PDT 24
Peak memory 200856 kb
Host smart-8bef9d87-9931-4c36-ad0f-afa8440e6f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162383609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.162383609
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4069376161
Short name T429
Test name
Test status
Simulation time 2322200863 ps
CPU time 4.2 seconds
Started Apr 23 02:02:19 PM PDT 24
Finished Apr 23 02:02:24 PM PDT 24
Peak memory 198784 kb
Host smart-7601de2a-2c7a-4efa-9ff8-75bb5cdcd500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069376161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4069376161
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3527312327
Short name T119
Test name
Test status
Simulation time 15702149727 ps
CPU time 25.43 seconds
Started Apr 23 02:02:25 PM PDT 24
Finished Apr 23 02:02:51 PM PDT 24
Peak memory 200804 kb
Host smart-ed548e68-3868-4575-983e-1255cdbc5bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527312327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3527312327
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1340597368
Short name T560
Test name
Test status
Simulation time 3662701463 ps
CPU time 6.43 seconds
Started Apr 23 02:02:23 PM PDT 24
Finished Apr 23 02:02:30 PM PDT 24
Peak memory 196876 kb
Host smart-81bcbcfe-7335-40f0-9529-8d7fc5bd3121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340597368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1340597368
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.62844090
Short name T517
Test name
Test status
Simulation time 89549630 ps
CPU time 0.9 seconds
Started Apr 23 02:02:20 PM PDT 24
Finished Apr 23 02:02:21 PM PDT 24
Peak memory 198020 kb
Host smart-e13fa720-71e5-47da-933e-d5847bd986a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62844090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.62844090
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1659497378
Short name T563
Test name
Test status
Simulation time 41402905756 ps
CPU time 81.28 seconds
Started Apr 23 02:02:28 PM PDT 24
Finished Apr 23 02:03:50 PM PDT 24
Peak memory 200788 kb
Host smart-9a58b487-ab65-471d-86e3-b533267b7a1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659497378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1659497378
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2429418053
Short name T113
Test name
Test status
Simulation time 54469731162 ps
CPU time 570.14 seconds
Started Apr 23 02:02:31 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 225724 kb
Host smart-d214ca37-a0b1-4b59-87fa-e978de277c55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429418053 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2429418053
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3602707400
Short name T358
Test name
Test status
Simulation time 1310649826 ps
CPU time 1.79 seconds
Started Apr 23 02:02:27 PM PDT 24
Finished Apr 23 02:02:29 PM PDT 24
Peak memory 200688 kb
Host smart-f3ba158f-f015-44fe-aa9f-55f2e1fd5c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602707400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3602707400
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.4204751046
Short name T661
Test name
Test status
Simulation time 17458753347 ps
CPU time 16.26 seconds
Started Apr 23 02:02:21 PM PDT 24
Finished Apr 23 02:02:38 PM PDT 24
Peak memory 200764 kb
Host smart-9265cc8c-806a-4bb3-9f9b-da814444f312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204751046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.4204751046
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2339472666
Short name T733
Test name
Test status
Simulation time 49237458 ps
CPU time 0.52 seconds
Started Apr 23 02:02:36 PM PDT 24
Finished Apr 23 02:02:36 PM PDT 24
Peak memory 195096 kb
Host smart-cca9c7e1-9977-42ca-9d8c-d0aaf36a3cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339472666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2339472666
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3312165386
Short name T1166
Test name
Test status
Simulation time 116753631394 ps
CPU time 13.48 seconds
Started Apr 23 02:02:26 PM PDT 24
Finished Apr 23 02:02:40 PM PDT 24
Peak memory 200912 kb
Host smart-56427e13-befc-42c3-aabb-ea2a433fbdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312165386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3312165386
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4237898494
Short name T1149
Test name
Test status
Simulation time 187201890510 ps
CPU time 90.11 seconds
Started Apr 23 02:02:28 PM PDT 24
Finished Apr 23 02:03:59 PM PDT 24
Peak memory 200760 kb
Host smart-92039cfe-df56-4ccb-9284-b641d3418f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237898494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4237898494
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.4031457721
Short name T338
Test name
Test status
Simulation time 108502454437 ps
CPU time 45.66 seconds
Started Apr 23 02:02:26 PM PDT 24
Finished Apr 23 02:03:12 PM PDT 24
Peak memory 200776 kb
Host smart-6d4af5f0-2f6b-4c44-91a9-bb95625857ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031457721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4031457721
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3316260563
Short name T1183
Test name
Test status
Simulation time 73291089444 ps
CPU time 111.35 seconds
Started Apr 23 02:02:29 PM PDT 24
Finished Apr 23 02:04:21 PM PDT 24
Peak memory 200748 kb
Host smart-30ae61e1-d179-436a-b52c-c7209aa6c7c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316260563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3316260563
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.927205273
Short name T640
Test name
Test status
Simulation time 128672279244 ps
CPU time 266.7 seconds
Started Apr 23 02:02:39 PM PDT 24
Finished Apr 23 02:07:06 PM PDT 24
Peak memory 200764 kb
Host smart-15cfc67a-54f7-4be1-9c37-37ccbb800a2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927205273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.927205273
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.781513599
Short name T407
Test name
Test status
Simulation time 2965398549 ps
CPU time 2 seconds
Started Apr 23 02:02:34 PM PDT 24
Finished Apr 23 02:02:36 PM PDT 24
Peak memory 197140 kb
Host smart-14802543-131a-46dc-b279-7cfc2a9aa797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781513599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.781513599
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3510427469
Short name T1184
Test name
Test status
Simulation time 150153888446 ps
CPU time 55.05 seconds
Started Apr 23 02:02:32 PM PDT 24
Finished Apr 23 02:03:28 PM PDT 24
Peak memory 201028 kb
Host smart-9109ec16-4442-4a7b-bf89-06ba3b6e6f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510427469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3510427469
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.757759379
Short name T1113
Test name
Test status
Simulation time 19997761265 ps
CPU time 579.51 seconds
Started Apr 23 02:02:37 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 200820 kb
Host smart-0b9daa3c-0ced-4748-86a5-9c057c960f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757759379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.757759379
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.780971650
Short name T693
Test name
Test status
Simulation time 3607857035 ps
CPU time 6.95 seconds
Started Apr 23 02:02:31 PM PDT 24
Finished Apr 23 02:02:39 PM PDT 24
Peak memory 199956 kb
Host smart-72ae8407-697e-400f-b77a-135f87ef314d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780971650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.780971650
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3878963714
Short name T289
Test name
Test status
Simulation time 35328793560 ps
CPU time 54.53 seconds
Started Apr 23 02:02:32 PM PDT 24
Finished Apr 23 02:03:27 PM PDT 24
Peak memory 200888 kb
Host smart-8e214082-3907-439f-ba80-a74336574f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878963714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3878963714
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.461686325
Short name T47
Test name
Test status
Simulation time 605022024 ps
CPU time 0.88 seconds
Started Apr 23 02:02:29 PM PDT 24
Finished Apr 23 02:02:30 PM PDT 24
Peak memory 196208 kb
Host smart-25772307-7a6d-40c6-9245-05a3a473580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461686325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.461686325
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1871720962
Short name T653
Test name
Test status
Simulation time 283441128 ps
CPU time 1.77 seconds
Started Apr 23 02:02:31 PM PDT 24
Finished Apr 23 02:02:33 PM PDT 24
Peak memory 199188 kb
Host smart-9da4be6c-e250-402d-88f9-1de12115ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871720962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1871720962
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1305230910
Short name T587
Test name
Test status
Simulation time 182335617591 ps
CPU time 730.96 seconds
Started Apr 23 02:02:37 PM PDT 24
Finished Apr 23 02:14:48 PM PDT 24
Peak memory 225676 kb
Host smart-7c81c066-5213-4fa5-876f-2352ec52fc7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305230910 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1305230910
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4085662123
Short name T559
Test name
Test status
Simulation time 1963500588 ps
CPU time 2.51 seconds
Started Apr 23 02:02:33 PM PDT 24
Finished Apr 23 02:02:36 PM PDT 24
Peak memory 199648 kb
Host smart-7c8efaac-d8c7-4f2a-b780-7d6d5d0e5b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085662123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4085662123
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1937510011
Short name T458
Test name
Test status
Simulation time 101220133056 ps
CPU time 80.54 seconds
Started Apr 23 02:02:25 PM PDT 24
Finished Apr 23 02:03:45 PM PDT 24
Peak memory 200840 kb
Host smart-70738d1d-a4fa-43ef-b753-223d42ded4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937510011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1937510011
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3312836839
Short name T539
Test name
Test status
Simulation time 18474335 ps
CPU time 0.52 seconds
Started Apr 23 02:02:54 PM PDT 24
Finished Apr 23 02:02:55 PM PDT 24
Peak memory 195132 kb
Host smart-9e9a787e-9df8-4958-8503-56973182fbe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312836839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3312836839
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.559034937
Short name T274
Test name
Test status
Simulation time 36934900936 ps
CPU time 34.6 seconds
Started Apr 23 02:02:42 PM PDT 24
Finished Apr 23 02:03:17 PM PDT 24
Peak memory 200884 kb
Host smart-30791784-04a5-4008-b81c-527ff7553d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559034937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.559034937
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3518030887
Short name T417
Test name
Test status
Simulation time 71648107597 ps
CPU time 59.51 seconds
Started Apr 23 02:02:40 PM PDT 24
Finished Apr 23 02:03:40 PM PDT 24
Peak memory 200896 kb
Host smart-6842ac54-e094-4a79-9b33-3edd0899239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518030887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3518030887
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3022223683
Short name T193
Test name
Test status
Simulation time 170910381276 ps
CPU time 61.87 seconds
Started Apr 23 02:02:42 PM PDT 24
Finished Apr 23 02:03:44 PM PDT 24
Peak memory 200768 kb
Host smart-30cb0292-5111-44be-aa0f-6c7fdfb2524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022223683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3022223683
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1885361952
Short name T518
Test name
Test status
Simulation time 33043766866 ps
CPU time 32.08 seconds
Started Apr 23 02:02:42 PM PDT 24
Finished Apr 23 02:03:15 PM PDT 24
Peak memory 200832 kb
Host smart-583521f7-23bc-4762-a10e-d54e0860433c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885361952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1885361952
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3003505476
Short name T382
Test name
Test status
Simulation time 64371365475 ps
CPU time 623.51 seconds
Started Apr 23 02:02:46 PM PDT 24
Finished Apr 23 02:13:10 PM PDT 24
Peak memory 200856 kb
Host smart-dee8b880-46e3-47ea-852b-2a7c65a4ac10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003505476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3003505476
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2605077411
Short name T615
Test name
Test status
Simulation time 10550424046 ps
CPU time 3.44 seconds
Started Apr 23 02:02:46 PM PDT 24
Finished Apr 23 02:02:50 PM PDT 24
Peak memory 200680 kb
Host smart-35e72f95-fd2c-4aaa-8e47-e110d3aa03e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605077411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2605077411
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2576121483
Short name T861
Test name
Test status
Simulation time 9078022585 ps
CPU time 16.5 seconds
Started Apr 23 02:02:40 PM PDT 24
Finished Apr 23 02:02:57 PM PDT 24
Peak memory 199240 kb
Host smart-8007bb1e-5f43-4136-b4bd-49d73149bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576121483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2576121483
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.288871771
Short name T265
Test name
Test status
Simulation time 9698690934 ps
CPU time 195.27 seconds
Started Apr 23 02:02:45 PM PDT 24
Finished Apr 23 02:06:00 PM PDT 24
Peak memory 200872 kb
Host smart-556ed73f-c237-4c26-848c-ec2d676572ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288871771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.288871771
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1555469064
Short name T373
Test name
Test status
Simulation time 4082476737 ps
CPU time 33.86 seconds
Started Apr 23 02:02:41 PM PDT 24
Finished Apr 23 02:03:15 PM PDT 24
Peak memory 198724 kb
Host smart-aaf302ca-f868-4f39-875b-f816d9b5f97f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555469064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1555469064
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1721806263
Short name T272
Test name
Test status
Simulation time 75032658192 ps
CPU time 108.03 seconds
Started Apr 23 02:02:47 PM PDT 24
Finished Apr 23 02:04:35 PM PDT 24
Peak memory 200676 kb
Host smart-18547843-d09e-48c6-8367-0fc4bf96c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721806263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1721806263
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1122133998
Short name T288
Test name
Test status
Simulation time 50714191786 ps
CPU time 9.48 seconds
Started Apr 23 02:02:44 PM PDT 24
Finished Apr 23 02:02:54 PM PDT 24
Peak memory 196596 kb
Host smart-d2aaa413-a9d5-4e4d-bc1b-eb37dc0dbe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122133998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1122133998
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.239262261
Short name T793
Test name
Test status
Simulation time 534100669 ps
CPU time 2.66 seconds
Started Apr 23 02:02:36 PM PDT 24
Finished Apr 23 02:02:39 PM PDT 24
Peak memory 199508 kb
Host smart-c9a08087-c81f-4861-96e4-2c358e02eb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239262261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.239262261
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1618312989
Short name T1048
Test name
Test status
Simulation time 73196675755 ps
CPU time 855.83 seconds
Started Apr 23 02:02:46 PM PDT 24
Finished Apr 23 02:17:02 PM PDT 24
Peak memory 225644 kb
Host smart-d67094ef-75e4-4ad4-bcce-9b1bd564ad10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618312989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1618312989
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2629753062
Short name T1045
Test name
Test status
Simulation time 2105789352 ps
CPU time 4.08 seconds
Started Apr 23 02:02:46 PM PDT 24
Finished Apr 23 02:02:50 PM PDT 24
Peak memory 199980 kb
Host smart-e487c560-2f9d-4ebd-bc0e-038e566b62c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629753062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2629753062
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3548948472
Short name T362
Test name
Test status
Simulation time 78951586039 ps
CPU time 53.87 seconds
Started Apr 23 02:02:37 PM PDT 24
Finished Apr 23 02:03:31 PM PDT 24
Peak memory 200844 kb
Host smart-59aedebe-75f8-43e1-82bd-e8727a852d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548948472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3548948472
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.245172098
Short name T1050
Test name
Test status
Simulation time 44804339 ps
CPU time 0.56 seconds
Started Apr 23 02:02:56 PM PDT 24
Finished Apr 23 02:02:57 PM PDT 24
Peak memory 196188 kb
Host smart-a5cb1c48-2d20-452e-b749-7134ea0ffb72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245172098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.245172098
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1877315402
Short name T873
Test name
Test status
Simulation time 146062908396 ps
CPU time 344.13 seconds
Started Apr 23 02:02:48 PM PDT 24
Finished Apr 23 02:08:33 PM PDT 24
Peak memory 200836 kb
Host smart-996ce2c4-6fc4-42b4-8802-d628714d6359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877315402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1877315402
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1370319547
Short name T392
Test name
Test status
Simulation time 25888755722 ps
CPU time 41.73 seconds
Started Apr 23 02:02:49 PM PDT 24
Finished Apr 23 02:03:31 PM PDT 24
Peak memory 200936 kb
Host smart-9e5b7a58-55cf-42c3-8990-695bca73db9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370319547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1370319547
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.4187392994
Short name T708
Test name
Test status
Simulation time 82230917322 ps
CPU time 66.52 seconds
Started Apr 23 02:02:51 PM PDT 24
Finished Apr 23 02:03:58 PM PDT 24
Peak memory 200840 kb
Host smart-7000d152-d5d1-4d49-965e-5d555cc96241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187392994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4187392994
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.330416659
Short name T1167
Test name
Test status
Simulation time 17061224597 ps
CPU time 10.73 seconds
Started Apr 23 02:02:53 PM PDT 24
Finished Apr 23 02:03:04 PM PDT 24
Peak memory 200388 kb
Host smart-71bc677e-a766-4863-92f2-2abaf736ac7a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330416659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.330416659
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1238396998
Short name T1110
Test name
Test status
Simulation time 124179657645 ps
CPU time 434.91 seconds
Started Apr 23 02:02:52 PM PDT 24
Finished Apr 23 02:10:07 PM PDT 24
Peak memory 200840 kb
Host smart-678315fe-ff7d-406a-98c1-7f125aa2b4c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238396998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1238396998
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2770377933
Short name T339
Test name
Test status
Simulation time 6692268527 ps
CPU time 12.29 seconds
Started Apr 23 02:02:52 PM PDT 24
Finished Apr 23 02:03:04 PM PDT 24
Peak memory 200760 kb
Host smart-fd70dc6c-8a82-48a7-8bb1-e10d056d2ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770377933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2770377933
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.905617678
Short name T807
Test name
Test status
Simulation time 53987999733 ps
CPU time 91.03 seconds
Started Apr 23 02:02:51 PM PDT 24
Finished Apr 23 02:04:22 PM PDT 24
Peak memory 201092 kb
Host smart-65e6397c-777a-41bd-93ab-902e818de912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905617678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.905617678
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3978236786
Short name T769
Test name
Test status
Simulation time 19914318092 ps
CPU time 544.72 seconds
Started Apr 23 02:02:53 PM PDT 24
Finished Apr 23 02:11:58 PM PDT 24
Peak memory 200768 kb
Host smart-0853954f-308d-4929-bd73-177981c14e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3978236786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3978236786
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2625773328
Short name T562
Test name
Test status
Simulation time 5974858211 ps
CPU time 53.09 seconds
Started Apr 23 02:02:53 PM PDT 24
Finished Apr 23 02:03:47 PM PDT 24
Peak memory 198880 kb
Host smart-11f71445-85ba-4651-a63b-97ca9c0f256b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625773328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2625773328
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.672988353
Short name T603
Test name
Test status
Simulation time 48049005243 ps
CPU time 83.79 seconds
Started Apr 23 02:02:53 PM PDT 24
Finished Apr 23 02:04:17 PM PDT 24
Peak memory 200892 kb
Host smart-32081813-aa65-4a52-9700-a77407b26af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672988353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.672988353
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1094396970
Short name T631
Test name
Test status
Simulation time 29549385480 ps
CPU time 43.51 seconds
Started Apr 23 02:02:55 PM PDT 24
Finished Apr 23 02:03:39 PM PDT 24
Peak memory 196932 kb
Host smart-2cfd7513-af77-4a81-9941-8ea8370280e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094396970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1094396970
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4278462364
Short name T1158
Test name
Test status
Simulation time 412840464 ps
CPU time 2.07 seconds
Started Apr 23 02:02:48 PM PDT 24
Finished Apr 23 02:02:51 PM PDT 24
Peak memory 199104 kb
Host smart-40fd87fd-8f1e-4028-8b34-25921fe22b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278462364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4278462364
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1247755792
Short name T160
Test name
Test status
Simulation time 205070874438 ps
CPU time 402.18 seconds
Started Apr 23 02:02:52 PM PDT 24
Finished Apr 23 02:09:34 PM PDT 24
Peak memory 210428 kb
Host smart-4192ec6a-e5c6-4aa1-8c2d-9ad0658263d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247755792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1247755792
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2979085039
Short name T666
Test name
Test status
Simulation time 22228309007 ps
CPU time 341.82 seconds
Started Apr 23 02:02:53 PM PDT 24
Finished Apr 23 02:08:35 PM PDT 24
Peak memory 216372 kb
Host smart-f58b5bf2-489b-48fa-bbe9-2b9f0329702b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979085039 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2979085039
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.455515771
Short name T919
Test name
Test status
Simulation time 1504647043 ps
CPU time 1.88 seconds
Started Apr 23 02:02:53 PM PDT 24
Finished Apr 23 02:02:55 PM PDT 24
Peak memory 199536 kb
Host smart-ac2e108e-2be1-44df-a773-25754f99ebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455515771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.455515771
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.178113256
Short name T1089
Test name
Test status
Simulation time 24974296980 ps
CPU time 9.9 seconds
Started Apr 23 02:02:49 PM PDT 24
Finished Apr 23 02:02:59 PM PDT 24
Peak memory 200784 kb
Host smart-253a160e-9e97-4b23-b3e8-d493171011fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178113256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.178113256
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1208129715
Short name T24
Test name
Test status
Simulation time 13899646 ps
CPU time 0.6 seconds
Started Apr 23 02:03:03 PM PDT 24
Finished Apr 23 02:03:04 PM PDT 24
Peak memory 196096 kb
Host smart-7f6a9977-efe8-4c9d-9dec-b26eb0e22a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208129715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1208129715
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.977976618
Short name T696
Test name
Test status
Simulation time 100397547498 ps
CPU time 73.54 seconds
Started Apr 23 02:02:55 PM PDT 24
Finished Apr 23 02:04:09 PM PDT 24
Peak memory 200788 kb
Host smart-98815762-c227-457a-8916-329dec8007d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977976618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.977976618
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1305721821
Short name T139
Test name
Test status
Simulation time 88467349290 ps
CPU time 28.51 seconds
Started Apr 23 02:02:55 PM PDT 24
Finished Apr 23 02:03:24 PM PDT 24
Peak memory 199380 kb
Host smart-0cf73119-e820-4507-b462-34421c8bc238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305721821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1305721821
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3894056980
Short name T260
Test name
Test status
Simulation time 120404230619 ps
CPU time 93.51 seconds
Started Apr 23 02:02:56 PM PDT 24
Finished Apr 23 02:04:30 PM PDT 24
Peak memory 200880 kb
Host smart-73a38905-fd63-4569-a6f8-b5c807f8d1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894056980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3894056980
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2955318213
Short name T726
Test name
Test status
Simulation time 68069676496 ps
CPU time 33.75 seconds
Started Apr 23 02:03:01 PM PDT 24
Finished Apr 23 02:03:35 PM PDT 24
Peak memory 199732 kb
Host smart-d8bafef3-6736-4885-a779-a8571a593ddb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955318213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2955318213
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.385407564
Short name T384
Test name
Test status
Simulation time 109670480172 ps
CPU time 871.45 seconds
Started Apr 23 02:03:01 PM PDT 24
Finished Apr 23 02:17:33 PM PDT 24
Peak memory 200784 kb
Host smart-8cd2d4c8-b4ff-4603-b8ab-11063005f6bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=385407564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.385407564
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2478955838
Short name T962
Test name
Test status
Simulation time 2743656648 ps
CPU time 1.92 seconds
Started Apr 23 02:02:59 PM PDT 24
Finished Apr 23 02:03:02 PM PDT 24
Peak memory 196776 kb
Host smart-7742877a-172b-40f9-906d-2623a08c309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478955838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2478955838
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3933739522
Short name T811
Test name
Test status
Simulation time 8791024614 ps
CPU time 15.33 seconds
Started Apr 23 02:03:03 PM PDT 24
Finished Apr 23 02:03:18 PM PDT 24
Peak memory 201096 kb
Host smart-9e309296-90a0-4f25-b97e-57a13942ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933739522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3933739522
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1067294526
Short name T281
Test name
Test status
Simulation time 17055755178 ps
CPU time 924.04 seconds
Started Apr 23 02:03:04 PM PDT 24
Finished Apr 23 02:18:29 PM PDT 24
Peak memory 200856 kb
Host smart-f075081c-713f-4409-9f54-121ec5f8127f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067294526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1067294526
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4057866079
Short name T967
Test name
Test status
Simulation time 4424527092 ps
CPU time 38.41 seconds
Started Apr 23 02:03:00 PM PDT 24
Finished Apr 23 02:03:39 PM PDT 24
Peak memory 200684 kb
Host smart-de3c941e-d5df-4fce-9af0-35363e94c476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057866079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4057866079
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2301507127
Short name T1023
Test name
Test status
Simulation time 75935659150 ps
CPU time 21.83 seconds
Started Apr 23 02:02:58 PM PDT 24
Finished Apr 23 02:03:20 PM PDT 24
Peak memory 200744 kb
Host smart-db81221c-b584-4ff7-98a2-e1b6e7926e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301507127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2301507127
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4171752348
Short name T822
Test name
Test status
Simulation time 3345770512 ps
CPU time 1.91 seconds
Started Apr 23 02:03:00 PM PDT 24
Finished Apr 23 02:03:02 PM PDT 24
Peak memory 196744 kb
Host smart-38865a39-c706-4abd-8d33-2fb75db634ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171752348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4171752348
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2196467033
Short name T633
Test name
Test status
Simulation time 676030037 ps
CPU time 2.1 seconds
Started Apr 23 02:02:57 PM PDT 24
Finished Apr 23 02:02:59 PM PDT 24
Peak memory 200068 kb
Host smart-f867f0f9-a386-457f-b3c5-7cebc14dd20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196467033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2196467033
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3858338498
Short name T710
Test name
Test status
Simulation time 143991893013 ps
CPU time 826.67 seconds
Started Apr 23 02:03:02 PM PDT 24
Finished Apr 23 02:16:50 PM PDT 24
Peak memory 210460 kb
Host smart-f80d41bb-c1ca-49ca-be7d-f5a2e1839aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858338498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3858338498
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.932983985
Short name T543
Test name
Test status
Simulation time 71567744125 ps
CPU time 413.22 seconds
Started Apr 23 02:03:03 PM PDT 24
Finished Apr 23 02:09:57 PM PDT 24
Peak memory 216600 kb
Host smart-e3955fcb-896b-48e2-a921-bfbb244bfda6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932983985 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.932983985
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2230849340
Short name T540
Test name
Test status
Simulation time 6938744954 ps
CPU time 14.81 seconds
Started Apr 23 02:02:59 PM PDT 24
Finished Apr 23 02:03:14 PM PDT 24
Peak memory 200284 kb
Host smart-da3368f3-72c4-45d3-80c9-20152f732e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230849340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2230849340
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.823026449
Short name T308
Test name
Test status
Simulation time 38998656778 ps
CPU time 7.44 seconds
Started Apr 23 02:02:56 PM PDT 24
Finished Apr 23 02:03:04 PM PDT 24
Peak memory 200756 kb
Host smart-8fce3355-ceff-4fa0-ad3f-f0f968afb106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823026449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.823026449
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.270629327
Short name T618
Test name
Test status
Simulation time 206851396 ps
CPU time 0.57 seconds
Started Apr 23 02:03:10 PM PDT 24
Finished Apr 23 02:03:11 PM PDT 24
Peak memory 196160 kb
Host smart-45ca43f5-8765-4281-ac2c-0a4382af5c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270629327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.270629327
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2133363869
Short name T317
Test name
Test status
Simulation time 53113933156 ps
CPU time 64.91 seconds
Started Apr 23 02:03:01 PM PDT 24
Finished Apr 23 02:04:07 PM PDT 24
Peak memory 200732 kb
Host smart-f6cdea15-112d-445d-b497-a5c6e7336ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133363869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2133363869
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1561746556
Short name T572
Test name
Test status
Simulation time 94516263485 ps
CPU time 17.6 seconds
Started Apr 23 02:03:05 PM PDT 24
Finished Apr 23 02:03:23 PM PDT 24
Peak memory 200784 kb
Host smart-32ae1bc8-1ece-4e77-9f38-6cea9a41ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561746556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1561746556
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2029598082
Short name T427
Test name
Test status
Simulation time 395384564470 ps
CPU time 72.96 seconds
Started Apr 23 02:03:03 PM PDT 24
Finished Apr 23 02:04:17 PM PDT 24
Peak memory 200828 kb
Host smart-9f39e03a-40fe-46df-98d3-7939fc3f46b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029598082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2029598082
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1066295039
Short name T692
Test name
Test status
Simulation time 29591596834 ps
CPU time 4.66 seconds
Started Apr 23 02:03:04 PM PDT 24
Finished Apr 23 02:03:09 PM PDT 24
Peak memory 200372 kb
Host smart-1c9cf4a5-5fdc-46fb-a3ec-d5e864a9469b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066295039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1066295039
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2489681104
Short name T1129
Test name
Test status
Simulation time 114710819255 ps
CPU time 516.62 seconds
Started Apr 23 02:03:07 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 200872 kb
Host smart-74df6d06-f5f5-47ad-af8d-06b2a1ccf0fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489681104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2489681104
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1350203074
Short name T739
Test name
Test status
Simulation time 7531846594 ps
CPU time 19.66 seconds
Started Apr 23 02:03:06 PM PDT 24
Finished Apr 23 02:03:26 PM PDT 24
Peak memory 200788 kb
Host smart-8b79bb2e-638b-4d81-a077-bedc22a205b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350203074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1350203074
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.684737063
Short name T851
Test name
Test status
Simulation time 103609072061 ps
CPU time 79.87 seconds
Started Apr 23 02:03:05 PM PDT 24
Finished Apr 23 02:04:25 PM PDT 24
Peak memory 200824 kb
Host smart-d2628ba0-6e52-48ed-bd3d-d7fa5009718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684737063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.684737063
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.108265024
Short name T39
Test name
Test status
Simulation time 23451368841 ps
CPU time 256.44 seconds
Started Apr 23 02:03:06 PM PDT 24
Finished Apr 23 02:07:23 PM PDT 24
Peak memory 200840 kb
Host smart-601d6bd2-7797-425b-a3d8-db0532f815f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108265024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.108265024
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2788421655
Short name T592
Test name
Test status
Simulation time 4436799179 ps
CPU time 42.19 seconds
Started Apr 23 02:03:02 PM PDT 24
Finished Apr 23 02:03:45 PM PDT 24
Peak memory 200076 kb
Host smart-7a9641b9-f1d1-471e-bc22-4fdb303f2733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788421655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2788421655
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1154713633
Short name T748
Test name
Test status
Simulation time 35708273858 ps
CPU time 29.7 seconds
Started Apr 23 02:03:09 PM PDT 24
Finished Apr 23 02:03:39 PM PDT 24
Peak memory 200672 kb
Host smart-c1cec4ee-a4e8-42bc-9348-8b12200ee4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154713633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1154713633
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3269318628
Short name T428
Test name
Test status
Simulation time 5509117391 ps
CPU time 4.96 seconds
Started Apr 23 02:03:06 PM PDT 24
Finished Apr 23 02:03:12 PM PDT 24
Peak memory 197100 kb
Host smart-025e34e6-b523-41d0-a947-47a0ca21524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269318628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3269318628
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1313228978
Short name T1126
Test name
Test status
Simulation time 481407738 ps
CPU time 2.03 seconds
Started Apr 23 02:03:02 PM PDT 24
Finished Apr 23 02:03:05 PM PDT 24
Peak memory 199364 kb
Host smart-88612a47-dacf-4b67-9992-e03e0da8d32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313228978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1313228978
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1933832423
Short name T620
Test name
Test status
Simulation time 95910028631 ps
CPU time 33.91 seconds
Started Apr 23 02:03:09 PM PDT 24
Finished Apr 23 02:03:43 PM PDT 24
Peak memory 200700 kb
Host smart-717d068b-038b-4def-8762-db14b696dee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933832423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1933832423
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1376402399
Short name T173
Test name
Test status
Simulation time 243244083900 ps
CPU time 711.11 seconds
Started Apr 23 02:03:07 PM PDT 24
Finished Apr 23 02:14:58 PM PDT 24
Peak memory 229976 kb
Host smart-18f4dfcf-5b37-4062-aac5-7ef6a8f87dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376402399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1376402399
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4013320213
Short name T16
Test name
Test status
Simulation time 739518243 ps
CPU time 2.18 seconds
Started Apr 23 02:03:06 PM PDT 24
Finished Apr 23 02:03:09 PM PDT 24
Peak memory 199496 kb
Host smart-0586fdb5-4bfb-4299-b33c-e9b325154091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013320213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4013320213
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1239834184
Short name T383
Test name
Test status
Simulation time 94515851688 ps
CPU time 117.52 seconds
Started Apr 23 02:03:01 PM PDT 24
Finished Apr 23 02:04:59 PM PDT 24
Peak memory 200904 kb
Host smart-cc41969e-7b44-46ad-90c3-09583905a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239834184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1239834184
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.887015694
Short name T852
Test name
Test status
Simulation time 12134030 ps
CPU time 0.56 seconds
Started Apr 23 02:03:22 PM PDT 24
Finished Apr 23 02:03:23 PM PDT 24
Peak memory 196148 kb
Host smart-b0cc595d-7fa1-404b-856e-c48fb85e47f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887015694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.887015694
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4044901393
Short name T1182
Test name
Test status
Simulation time 32653758358 ps
CPU time 31.59 seconds
Started Apr 23 02:03:11 PM PDT 24
Finished Apr 23 02:03:43 PM PDT 24
Peak memory 200772 kb
Host smart-8209c3a2-5064-41fc-8cb6-c10800cc12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044901393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4044901393
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2024560032
Short name T1155
Test name
Test status
Simulation time 97609205420 ps
CPU time 33.52 seconds
Started Apr 23 02:03:09 PM PDT 24
Finished Apr 23 02:03:43 PM PDT 24
Peak memory 200572 kb
Host smart-b3d26b3e-c9d1-4238-9a58-730a1a917bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024560032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2024560032
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1672607546
Short name T1080
Test name
Test status
Simulation time 275473457325 ps
CPU time 42.27 seconds
Started Apr 23 02:03:11 PM PDT 24
Finished Apr 23 02:03:54 PM PDT 24
Peak memory 200864 kb
Host smart-4ee44bb5-ddc7-443d-b835-c1efcf0460bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672607546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1672607546
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3883538941
Short name T611
Test name
Test status
Simulation time 45142961082 ps
CPU time 27.15 seconds
Started Apr 23 02:03:13 PM PDT 24
Finished Apr 23 02:03:41 PM PDT 24
Peak memory 200824 kb
Host smart-f35a576a-3e95-4676-8e1b-260a0a69f01d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883538941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3883538941
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1911308172
Short name T1
Test name
Test status
Simulation time 72796874875 ps
CPU time 537.83 seconds
Started Apr 23 02:03:20 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 200844 kb
Host smart-43b8f891-c946-464a-9907-b32852133cc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911308172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1911308172
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3920582202
Short name T893
Test name
Test status
Simulation time 5314964533 ps
CPU time 9.21 seconds
Started Apr 23 02:03:13 PM PDT 24
Finished Apr 23 02:03:22 PM PDT 24
Peak memory 199236 kb
Host smart-5d6ca360-6213-4376-ae51-9829cfe5dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920582202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3920582202
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1436512780
Short name T497
Test name
Test status
Simulation time 112372160799 ps
CPU time 63.7 seconds
Started Apr 23 02:03:12 PM PDT 24
Finished Apr 23 02:04:16 PM PDT 24
Peak memory 200984 kb
Host smart-f56be25c-8195-43d3-87e3-3460c9f55408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436512780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1436512780
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1242343110
Short name T455
Test name
Test status
Simulation time 14146766561 ps
CPU time 829.86 seconds
Started Apr 23 02:03:16 PM PDT 24
Finished Apr 23 02:17:06 PM PDT 24
Peak memory 200868 kb
Host smart-7c8f8f72-62bf-46cb-9307-3f648cc29b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242343110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1242343110
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1457381392
Short name T1141
Test name
Test status
Simulation time 6238203092 ps
CPU time 14.53 seconds
Started Apr 23 02:03:11 PM PDT 24
Finished Apr 23 02:03:26 PM PDT 24
Peak memory 199824 kb
Host smart-c818d911-2160-43ae-8e47-ab06264b63a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457381392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1457381392
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1802996538
Short name T279
Test name
Test status
Simulation time 108074741811 ps
CPU time 36.72 seconds
Started Apr 23 02:03:13 PM PDT 24
Finished Apr 23 02:03:50 PM PDT 24
Peak memory 200736 kb
Host smart-0db1c308-a663-45a8-89d7-761959585f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802996538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1802996538
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.220731856
Short name T433
Test name
Test status
Simulation time 43064434104 ps
CPU time 70.14 seconds
Started Apr 23 02:03:13 PM PDT 24
Finished Apr 23 02:04:24 PM PDT 24
Peak memory 196824 kb
Host smart-56104c0f-3003-4724-ac25-d0c6ffdd69a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220731856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.220731856
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2386427259
Short name T846
Test name
Test status
Simulation time 690031386 ps
CPU time 2.61 seconds
Started Apr 23 02:03:10 PM PDT 24
Finished Apr 23 02:03:13 PM PDT 24
Peak memory 199328 kb
Host smart-f5446094-5e3f-42f9-8185-314d264f1525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386427259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2386427259
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2714606658
Short name T818
Test name
Test status
Simulation time 499349417931 ps
CPU time 788.71 seconds
Started Apr 23 02:03:19 PM PDT 24
Finished Apr 23 02:16:28 PM PDT 24
Peak memory 200832 kb
Host smart-55f08da7-0fe8-4abc-b72a-767a1afe929b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714606658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2714606658
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1507240897
Short name T923
Test name
Test status
Simulation time 9244819081 ps
CPU time 7.63 seconds
Started Apr 23 02:03:12 PM PDT 24
Finished Apr 23 02:03:20 PM PDT 24
Peak memory 200648 kb
Host smart-4ab16cb2-ef2e-4f5a-9b73-35c07a16df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507240897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1507240897
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1560936291
Short name T399
Test name
Test status
Simulation time 43471561165 ps
CPU time 102.02 seconds
Started Apr 23 02:03:10 PM PDT 24
Finished Apr 23 02:04:53 PM PDT 24
Peak memory 200756 kb
Host smart-2ee767e4-cc80-4393-a6d0-1e9afc8cb92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560936291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1560936291
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.224341481
Short name T351
Test name
Test status
Simulation time 37769667 ps
CPU time 0.55 seconds
Started Apr 23 01:58:26 PM PDT 24
Finished Apr 23 01:58:27 PM PDT 24
Peak memory 196156 kb
Host smart-cee75f54-c0dd-41ce-ad8f-2a5d2f22afc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224341481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.224341481
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1318251902
Short name T780
Test name
Test status
Simulation time 140016240996 ps
CPU time 106.54 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 02:00:17 PM PDT 24
Peak memory 200820 kb
Host smart-a2e95643-be8f-409f-bb87-fccf224de3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318251902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1318251902
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3542839916
Short name T645
Test name
Test status
Simulation time 25579296486 ps
CPU time 45.94 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 01:59:11 PM PDT 24
Peak memory 200884 kb
Host smart-ac8732cc-036f-4653-8cd7-65217df99b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542839916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3542839916
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.4978128
Short name T1154
Test name
Test status
Simulation time 211796101107 ps
CPU time 404.28 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 02:05:14 PM PDT 24
Peak memory 200736 kb
Host smart-35b648d9-8fc0-4712-9de6-235147dba143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4978128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.4978128
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1934481516
Short name T988
Test name
Test status
Simulation time 24910261411 ps
CPU time 24.06 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:58:54 PM PDT 24
Peak memory 200480 kb
Host smart-68689e06-139b-40f4-9a3f-345d3c5a384a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934481516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1934481516
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1344313881
Short name T1036
Test name
Test status
Simulation time 55315115006 ps
CPU time 249.43 seconds
Started Apr 23 01:58:26 PM PDT 24
Finished Apr 23 02:02:36 PM PDT 24
Peak memory 200888 kb
Host smart-115c1d38-87fc-4621-b329-4166df7c0636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344313881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1344313881
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3212015864
Short name T894
Test name
Test status
Simulation time 2674973928 ps
CPU time 2.03 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:58:33 PM PDT 24
Peak memory 198512 kb
Host smart-8ee9c4cb-9c5e-44a8-ad15-d92d185f35de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212015864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3212015864
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3930450720
Short name T577
Test name
Test status
Simulation time 45186853857 ps
CPU time 21.61 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 01:58:48 PM PDT 24
Peak memory 201032 kb
Host smart-275fb407-d158-4d32-8189-14456a9b686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930450720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3930450720
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2886583748
Short name T3
Test name
Test status
Simulation time 20661009013 ps
CPU time 1135.54 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 02:17:25 PM PDT 24
Peak memory 200884 kb
Host smart-204c36fe-fadc-45f3-891f-12cd4cec2267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886583748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2886583748
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2445083804
Short name T575
Test name
Test status
Simulation time 5921497150 ps
CPU time 58.7 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:59:29 PM PDT 24
Peak memory 200224 kb
Host smart-136f5692-5554-4df7-86cc-fdfaac4acd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445083804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2445083804
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4006535017
Short name T1014
Test name
Test status
Simulation time 185859803564 ps
CPU time 100.06 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 02:00:09 PM PDT 24
Peak memory 200752 kb
Host smart-dd38cc07-cc87-4450-94ad-e39bb27bdaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006535017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4006535017
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.576312384
Short name T835
Test name
Test status
Simulation time 49260396893 ps
CPU time 10.17 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:58:39 PM PDT 24
Peak memory 196540 kb
Host smart-88a7b47e-744c-4512-b0ca-f52379a1bb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576312384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.576312384
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.94987337
Short name T310
Test name
Test status
Simulation time 5574566989 ps
CPU time 7.99 seconds
Started Apr 23 01:58:20 PM PDT 24
Finished Apr 23 01:58:28 PM PDT 24
Peak memory 200804 kb
Host smart-dda97f67-0d52-419d-9898-562013579515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94987337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.94987337
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.364872171
Short name T436
Test name
Test status
Simulation time 61729185556 ps
CPU time 642.23 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 02:09:12 PM PDT 24
Peak memory 225764 kb
Host smart-686009e9-6bf8-46a5-8c1c-2378f4ec8b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364872171 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.364872171
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1373951879
Short name T324
Test name
Test status
Simulation time 5393383042 ps
CPU time 1.96 seconds
Started Apr 23 01:58:27 PM PDT 24
Finished Apr 23 01:58:29 PM PDT 24
Peak memory 200256 kb
Host smart-97b6f055-4d1b-4508-abc4-c011d7342ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373951879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1373951879
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1538236990
Short name T948
Test name
Test status
Simulation time 9179363663 ps
CPU time 13.2 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:58:41 PM PDT 24
Peak memory 200692 kb
Host smart-65a5f91d-376d-4fd6-8697-1693ff2d6eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538236990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1538236990
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2422379148
Short name T269
Test name
Test status
Simulation time 28362177991 ps
CPU time 67.54 seconds
Started Apr 23 02:03:19 PM PDT 24
Finished Apr 23 02:04:27 PM PDT 24
Peak memory 200872 kb
Host smart-5e3e4ca6-19d3-4adc-971a-e946d74839fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422379148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2422379148
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2124452359
Short name T118
Test name
Test status
Simulation time 6798670845 ps
CPU time 63.23 seconds
Started Apr 23 02:03:23 PM PDT 24
Finished Apr 23 02:04:26 PM PDT 24
Peak memory 209060 kb
Host smart-8395d501-1f68-4311-a6a8-3d8f467d90e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124452359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2124452359
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1498656555
Short name T136
Test name
Test status
Simulation time 45071076446 ps
CPU time 9.43 seconds
Started Apr 23 02:03:24 PM PDT 24
Finished Apr 23 02:03:34 PM PDT 24
Peak memory 200784 kb
Host smart-d8c8a254-591f-441c-a81d-9d63a893438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498656555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1498656555
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3428477408
Short name T115
Test name
Test status
Simulation time 127661714314 ps
CPU time 796.04 seconds
Started Apr 23 02:03:24 PM PDT 24
Finished Apr 23 02:16:41 PM PDT 24
Peak memory 217312 kb
Host smart-58af36b1-fb7f-49f2-810a-78b16ad53f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428477408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3428477408
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2624552202
Short name T1086
Test name
Test status
Simulation time 170605447160 ps
CPU time 406.8 seconds
Started Apr 23 02:03:26 PM PDT 24
Finished Apr 23 02:10:14 PM PDT 24
Peak memory 217524 kb
Host smart-9934f929-a227-4fe4-8758-d5bbfe539128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624552202 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2624552202
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1773632743
Short name T829
Test name
Test status
Simulation time 54343193819 ps
CPU time 12.88 seconds
Started Apr 23 02:03:25 PM PDT 24
Finished Apr 23 02:03:38 PM PDT 24
Peak memory 200908 kb
Host smart-207903ee-dbce-4e94-b392-bb4b51ec5240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773632743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1773632743
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3708483669
Short name T1090
Test name
Test status
Simulation time 259424018294 ps
CPU time 1109.92 seconds
Started Apr 23 02:03:26 PM PDT 24
Finished Apr 23 02:21:57 PM PDT 24
Peak memory 217332 kb
Host smart-1280d42d-3750-43a0-b11c-15369adfc543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708483669 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3708483669
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.4046174798
Short name T57
Test name
Test status
Simulation time 238157858272 ps
CPU time 506.2 seconds
Started Apr 23 02:03:25 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 217532 kb
Host smart-d84e1960-1644-4d45-959a-0da611727c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046174798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.4046174798
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1995958171
Short name T220
Test name
Test status
Simulation time 144053064894 ps
CPU time 244.01 seconds
Started Apr 23 02:03:26 PM PDT 24
Finished Apr 23 02:07:30 PM PDT 24
Peak memory 200732 kb
Host smart-738e280c-4990-44d7-9b49-5b3fa2b228bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995958171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1995958171
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2357016674
Short name T1012
Test name
Test status
Simulation time 15917809681 ps
CPU time 52.25 seconds
Started Apr 23 02:03:25 PM PDT 24
Finished Apr 23 02:04:18 PM PDT 24
Peak memory 217156 kb
Host smart-2ff4d5cf-a3ee-4edd-866b-f1d5f359890b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357016674 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2357016674
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1395215424
Short name T869
Test name
Test status
Simulation time 18946921241 ps
CPU time 17.98 seconds
Started Apr 23 02:03:26 PM PDT 24
Finished Apr 23 02:03:45 PM PDT 24
Peak memory 200896 kb
Host smart-dcdbefe0-9a83-4e1f-8508-73acb3e6092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395215424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1395215424
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.248628722
Short name T738
Test name
Test status
Simulation time 83911987572 ps
CPU time 1618.61 seconds
Started Apr 23 02:03:26 PM PDT 24
Finished Apr 23 02:30:26 PM PDT 24
Peak memory 225656 kb
Host smart-dd398954-fb14-4d9a-bafc-86138971aa3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248628722 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.248628722
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1267371985
Short name T198
Test name
Test status
Simulation time 42461826822 ps
CPU time 365.97 seconds
Started Apr 23 02:03:34 PM PDT 24
Finished Apr 23 02:09:40 PM PDT 24
Peak memory 210136 kb
Host smart-b5ee3717-c24c-4ed9-91f1-c361fcd056e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267371985 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1267371985
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2651013787
Short name T473
Test name
Test status
Simulation time 57516892856 ps
CPU time 76.29 seconds
Started Apr 23 02:03:27 PM PDT 24
Finished Apr 23 02:04:43 PM PDT 24
Peak memory 200924 kb
Host smart-d372346f-1f5e-45f2-abf2-d84e56549185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651013787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2651013787
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1130045867
Short name T986
Test name
Test status
Simulation time 30222764180 ps
CPU time 161.63 seconds
Started Apr 23 02:03:33 PM PDT 24
Finished Apr 23 02:06:15 PM PDT 24
Peak memory 217536 kb
Host smart-78b54a76-1d78-49ec-9e61-e623a6cfb48c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130045867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1130045867
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3889902645
Short name T1172
Test name
Test status
Simulation time 40397429292 ps
CPU time 21.12 seconds
Started Apr 23 02:03:29 PM PDT 24
Finished Apr 23 02:03:50 PM PDT 24
Peak memory 200852 kb
Host smart-8d7bfa16-7ef8-4b59-bad0-acf5043c206b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889902645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3889902645
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3843355115
Short name T574
Test name
Test status
Simulation time 85880053259 ps
CPU time 725.63 seconds
Started Apr 23 02:03:29 PM PDT 24
Finished Apr 23 02:15:35 PM PDT 24
Peak memory 215020 kb
Host smart-e192f7c8-14ba-4376-af9b-a483ebf3dba0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843355115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3843355115
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3190711565
Short name T628
Test name
Test status
Simulation time 59814696 ps
CPU time 0.53 seconds
Started Apr 23 01:58:33 PM PDT 24
Finished Apr 23 01:58:34 PM PDT 24
Peak memory 196108 kb
Host smart-0737b27e-7743-497f-b42f-62b1c2b3fdf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190711565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3190711565
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2593851540
Short name T650
Test name
Test status
Simulation time 159682977029 ps
CPU time 73.45 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:59:43 PM PDT 24
Peak memory 200872 kb
Host smart-ef85ee57-ae65-43bc-acad-e01355493be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593851540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2593851540
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3056582069
Short name T688
Test name
Test status
Simulation time 90712397272 ps
CPU time 64.66 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 01:59:30 PM PDT 24
Peak memory 200840 kb
Host smart-ad4e9f3c-3848-44dc-b98a-0d4055b9a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056582069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3056582069
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2049441518
Short name T878
Test name
Test status
Simulation time 11281447070 ps
CPU time 21.53 seconds
Started Apr 23 01:58:27 PM PDT 24
Finished Apr 23 01:58:49 PM PDT 24
Peak memory 200772 kb
Host smart-a5f972c7-a425-48de-a3b4-6a3e4c34f640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049441518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2049441518
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3114646532
Short name T1032
Test name
Test status
Simulation time 173564119103 ps
CPU time 278.03 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 02:03:09 PM PDT 24
Peak memory 198064 kb
Host smart-f21091c1-101f-4cd1-91ba-c879904e88d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114646532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3114646532
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3644308636
Short name T442
Test name
Test status
Simulation time 319240833719 ps
CPU time 227.43 seconds
Started Apr 23 01:58:34 PM PDT 24
Finished Apr 23 02:02:22 PM PDT 24
Peak memory 200904 kb
Host smart-ebcfc652-5870-4de1-a20b-cf41d8f41be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644308636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3644308636
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3543045370
Short name T379
Test name
Test status
Simulation time 5712232381 ps
CPU time 4.41 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 01:58:40 PM PDT 24
Peak memory 200660 kb
Host smart-03244c07-3eef-4f20-9844-1038b336afa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543045370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3543045370
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1708122864
Short name T668
Test name
Test status
Simulation time 195004286820 ps
CPU time 61.19 seconds
Started Apr 23 01:58:27 PM PDT 24
Finished Apr 23 01:59:29 PM PDT 24
Peak memory 199940 kb
Host smart-c0f954ad-6650-4232-900b-dd641f5a6123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708122864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1708122864
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1046844790
Short name T489
Test name
Test status
Simulation time 2012241809 ps
CPU time 3.09 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 01:58:32 PM PDT 24
Peak memory 198928 kb
Host smart-04b8fc84-8d1e-44f3-8bcb-9c3c8d75c4c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046844790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1046844790
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3337498802
Short name T551
Test name
Test status
Simulation time 118214255493 ps
CPU time 32.86 seconds
Started Apr 23 01:58:32 PM PDT 24
Finished Apr 23 01:59:06 PM PDT 24
Peak memory 200704 kb
Host smart-9e4c0376-5457-4821-851e-bd8c5fc74477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337498802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3337498802
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.749724420
Short name T494
Test name
Test status
Simulation time 5060375848 ps
CPU time 4.46 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 01:58:40 PM PDT 24
Peak memory 196748 kb
Host smart-1b0c9499-f3bd-495a-9043-7a67aec7ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749724420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.749724420
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2946362888
Short name T519
Test name
Test status
Simulation time 492746784 ps
CPU time 1.83 seconds
Started Apr 23 01:58:27 PM PDT 24
Finished Apr 23 01:58:29 PM PDT 24
Peak memory 200600 kb
Host smart-9735c7f3-ace7-45a9-9f7c-041dc9bbdb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946362888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2946362888
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1921517021
Short name T958
Test name
Test status
Simulation time 390974825873 ps
CPU time 160.97 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 02:01:11 PM PDT 24
Peak memory 200784 kb
Host smart-e770538a-c410-4df2-bb66-a5951550bae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921517021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1921517021
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.4244088988
Short name T607
Test name
Test status
Simulation time 636462831 ps
CPU time 1.05 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:58:32 PM PDT 24
Peak memory 197584 kb
Host smart-0b106040-e201-4acb-81c4-d6b55c09bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244088988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.4244088988
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.606985915
Short name T549
Test name
Test status
Simulation time 134617974924 ps
CPU time 147.65 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 02:00:56 PM PDT 24
Peak memory 200872 kb
Host smart-c461066d-984c-4eef-99e0-b4c94571035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606985915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.606985915
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.834563276
Short name T766
Test name
Test status
Simulation time 111921502302 ps
CPU time 155.05 seconds
Started Apr 23 02:03:31 PM PDT 24
Finished Apr 23 02:06:06 PM PDT 24
Peak memory 200876 kb
Host smart-c9f54af2-dfa9-4126-a7d0-1267ee3f244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834563276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.834563276
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3874461805
Short name T934
Test name
Test status
Simulation time 82370781661 ps
CPU time 648.72 seconds
Started Apr 23 02:03:35 PM PDT 24
Finished Apr 23 02:14:24 PM PDT 24
Peak memory 217236 kb
Host smart-77719e0b-dd8c-41d5-b5c2-2fd8a64face9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874461805 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3874461805
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1505734622
Short name T234
Test name
Test status
Simulation time 104906707705 ps
CPU time 49.56 seconds
Started Apr 23 02:03:32 PM PDT 24
Finished Apr 23 02:04:22 PM PDT 24
Peak memory 200780 kb
Host smart-4136e367-2555-45bf-b06e-5d5a4a5afa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505734622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1505734622
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3587924500
Short name T533
Test name
Test status
Simulation time 188129424609 ps
CPU time 439.49 seconds
Started Apr 23 02:03:34 PM PDT 24
Finished Apr 23 02:10:54 PM PDT 24
Peak memory 200748 kb
Host smart-12d6f378-5ab1-47f6-a4b6-1ca3ee622691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587924500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3587924500
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3545841695
Short name T815
Test name
Test status
Simulation time 260135368854 ps
CPU time 847.83 seconds
Started Apr 23 02:03:34 PM PDT 24
Finished Apr 23 02:17:42 PM PDT 24
Peak memory 225748 kb
Host smart-927a163f-997a-483a-ae1c-90066a023944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545841695 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3545841695
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2856143473
Short name T567
Test name
Test status
Simulation time 70915732663 ps
CPU time 26.76 seconds
Started Apr 23 02:03:39 PM PDT 24
Finished Apr 23 02:04:06 PM PDT 24
Peak memory 200808 kb
Host smart-dac6b3c4-5702-4a5f-9998-36f4bee3da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856143473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2856143473
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.115332683
Short name T33
Test name
Test status
Simulation time 41857522722 ps
CPU time 562.34 seconds
Started Apr 23 02:03:38 PM PDT 24
Finished Apr 23 02:13:01 PM PDT 24
Peak memory 212408 kb
Host smart-c573e209-1ada-467e-92c1-d5dfcf8e2a5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115332683 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.115332683
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3161701060
Short name T239
Test name
Test status
Simulation time 24098692350 ps
CPU time 40.56 seconds
Started Apr 23 02:03:37 PM PDT 24
Finished Apr 23 02:04:18 PM PDT 24
Peak memory 200844 kb
Host smart-38710c98-51ed-481c-9cb9-e221ff2149ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161701060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3161701060
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1307571555
Short name T56
Test name
Test status
Simulation time 18133491130 ps
CPU time 217.03 seconds
Started Apr 23 02:03:37 PM PDT 24
Finished Apr 23 02:07:14 PM PDT 24
Peak memory 217332 kb
Host smart-65de8e94-95f6-421e-b64e-35ad4dfb524f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307571555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1307571555
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1071615209
Short name T862
Test name
Test status
Simulation time 26327645204 ps
CPU time 12.1 seconds
Started Apr 23 02:03:38 PM PDT 24
Finished Apr 23 02:03:50 PM PDT 24
Peak memory 200836 kb
Host smart-019e01b4-0b0b-4386-8ede-25335df44cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071615209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1071615209
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.829000035
Short name T918
Test name
Test status
Simulation time 37204975853 ps
CPU time 7.69 seconds
Started Apr 23 02:03:39 PM PDT 24
Finished Apr 23 02:03:47 PM PDT 24
Peak memory 200840 kb
Host smart-8b293e77-4ae0-48b1-be50-4a9e369a66c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829000035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.829000035
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3848856048
Short name T488
Test name
Test status
Simulation time 62075473501 ps
CPU time 419.49 seconds
Started Apr 23 02:03:41 PM PDT 24
Finished Apr 23 02:10:41 PM PDT 24
Peak memory 209056 kb
Host smart-2cbead4a-d60b-40c5-ad3e-634b311aa892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848856048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3848856048
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3515963247
Short name T796
Test name
Test status
Simulation time 250406359959 ps
CPU time 51.52 seconds
Started Apr 23 02:03:40 PM PDT 24
Finished Apr 23 02:04:32 PM PDT 24
Peak memory 200852 kb
Host smart-3b6688f4-ed69-413c-894b-c60bd886ae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515963247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3515963247
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.394573337
Short name T524
Test name
Test status
Simulation time 156289606759 ps
CPU time 244.94 seconds
Started Apr 23 02:03:42 PM PDT 24
Finished Apr 23 02:07:48 PM PDT 24
Peak memory 210368 kb
Host smart-2951b7b6-5eb9-4fbb-92dc-388cc0f8b4c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394573337 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.394573337
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2556845653
Short name T698
Test name
Test status
Simulation time 16476331028 ps
CPU time 203.28 seconds
Started Apr 23 02:03:41 PM PDT 24
Finished Apr 23 02:07:05 PM PDT 24
Peak memory 208980 kb
Host smart-dcebc814-1be0-4b98-879f-5d250dae0cc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556845653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2556845653
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.695409916
Short name T921
Test name
Test status
Simulation time 99092696586 ps
CPU time 72.15 seconds
Started Apr 23 02:03:42 PM PDT 24
Finished Apr 23 02:04:54 PM PDT 24
Peak memory 200840 kb
Host smart-f9daf435-b549-46af-8138-e427d8202f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695409916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.695409916
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2502238855
Short name T1135
Test name
Test status
Simulation time 148323197058 ps
CPU time 645.21 seconds
Started Apr 23 02:03:46 PM PDT 24
Finished Apr 23 02:14:32 PM PDT 24
Peak memory 217556 kb
Host smart-0387f52e-a3d3-4a25-84b2-9d84f1cf22ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502238855 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2502238855
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2141141526
Short name T1064
Test name
Test status
Simulation time 66088018 ps
CPU time 0.54 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 01:58:37 PM PDT 24
Peak memory 196148 kb
Host smart-48db7447-4db6-4dbf-828a-17ba982d3835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141141526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2141141526
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3351705128
Short name T137
Test name
Test status
Simulation time 109243186386 ps
CPU time 47.42 seconds
Started Apr 23 01:58:32 PM PDT 24
Finished Apr 23 01:59:20 PM PDT 24
Peak memory 200724 kb
Host smart-fe007671-d3ad-454b-ab21-8990c412b3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351705128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3351705128
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2132925206
Short name T602
Test name
Test status
Simulation time 19016950342 ps
CPU time 14.58 seconds
Started Apr 23 01:58:32 PM PDT 24
Finished Apr 23 01:58:47 PM PDT 24
Peak memory 200580 kb
Host smart-f1b74a07-ee1c-44bb-a029-cf40d51ad82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132925206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2132925206
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3771867745
Short name T224
Test name
Test status
Simulation time 96283218869 ps
CPU time 318.82 seconds
Started Apr 23 01:58:25 PM PDT 24
Finished Apr 23 02:03:45 PM PDT 24
Peak memory 200832 kb
Host smart-619294ca-40ef-4b1d-bb81-5de1ed138824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771867745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3771867745
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.504212620
Short name T723
Test name
Test status
Simulation time 58452523971 ps
CPU time 105.05 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 02:00:14 PM PDT 24
Peak memory 200580 kb
Host smart-b6fc71b2-2789-4f06-95dc-61444d43059a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504212620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.504212620
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.727985500
Short name T568
Test name
Test status
Simulation time 129785048084 ps
CPU time 492.78 seconds
Started Apr 23 01:58:31 PM PDT 24
Finished Apr 23 02:06:44 PM PDT 24
Peak memory 200704 kb
Host smart-d282d34f-3cd6-43d7-a7b0-b5c6ac931171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727985500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.727985500
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1085271053
Short name T18
Test name
Test status
Simulation time 1623734389 ps
CPU time 3.92 seconds
Started Apr 23 01:58:32 PM PDT 24
Finished Apr 23 01:58:36 PM PDT 24
Peak memory 200648 kb
Host smart-52e29d66-a024-4059-b3e2-9325b4b46ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085271053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1085271053
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2972427710
Short name T584
Test name
Test status
Simulation time 987714619 ps
CPU time 1.08 seconds
Started Apr 23 01:58:34 PM PDT 24
Finished Apr 23 01:58:35 PM PDT 24
Peak memory 200788 kb
Host smart-1157b59e-843c-4ff1-8ce5-8afb95037832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972427710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2972427710
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.96638205
Short name T292
Test name
Test status
Simulation time 17757456164 ps
CPU time 186 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 02:01:37 PM PDT 24
Peak memory 200836 kb
Host smart-bb8d3673-25d6-4b96-bf85-ff1364857c68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96638205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.96638205
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3077816562
Short name T377
Test name
Test status
Simulation time 4199543337 ps
CPU time 39.32 seconds
Started Apr 23 01:58:32 PM PDT 24
Finished Apr 23 01:59:11 PM PDT 24
Peak memory 198924 kb
Host smart-0dfb1945-032f-455b-840f-9bd729296b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077816562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3077816562
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2007068032
Short name T771
Test name
Test status
Simulation time 5138922759 ps
CPU time 4.88 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:58:36 PM PDT 24
Peak memory 199768 kb
Host smart-25329c17-9a10-4041-a7b8-d2e155d83db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007068032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2007068032
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4150990518
Short name T995
Test name
Test status
Simulation time 2783354340 ps
CPU time 3.69 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 01:58:34 PM PDT 24
Peak memory 196824 kb
Host smart-8f334921-9f46-4def-bcce-87145bdf750b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150990518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4150990518
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2546082656
Short name T782
Test name
Test status
Simulation time 291195175 ps
CPU time 1.3 seconds
Started Apr 23 01:58:33 PM PDT 24
Finished Apr 23 01:58:35 PM PDT 24
Peak memory 199356 kb
Host smart-6fec25fa-2636-4fb5-be72-54f68c1ea0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546082656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2546082656
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1596000162
Short name T19
Test name
Test status
Simulation time 134378484707 ps
CPU time 56.69 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 01:59:26 PM PDT 24
Peak memory 200848 kb
Host smart-1afc43aa-ce58-4ef7-b2df-c5a4877908df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596000162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1596000162
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.4162164851
Short name T183
Test name
Test status
Simulation time 190876877983 ps
CPU time 410.78 seconds
Started Apr 23 01:58:31 PM PDT 24
Finished Apr 23 02:05:23 PM PDT 24
Peak memory 226392 kb
Host smart-a52d1e06-a541-4f08-a495-69c6c4025b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162164851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.4162164851
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2943358004
Short name T425
Test name
Test status
Simulation time 497751383 ps
CPU time 1.74 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:58:33 PM PDT 24
Peak memory 200780 kb
Host smart-1e1de0da-c0c1-49a9-ac37-6e7c933937e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943358004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2943358004
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1941261121
Short name T629
Test name
Test status
Simulation time 118165797425 ps
CPU time 81.24 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 01:59:57 PM PDT 24
Peak memory 200832 kb
Host smart-c139233e-6f2c-479c-97fa-c3ccc0d753bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941261121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1941261121
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1436979947
Short name T194
Test name
Test status
Simulation time 76047203290 ps
CPU time 35.44 seconds
Started Apr 23 02:03:46 PM PDT 24
Finished Apr 23 02:04:22 PM PDT 24
Peak memory 200884 kb
Host smart-ad7e7f72-a453-4470-a085-561c2c2f1b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436979947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1436979947
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.648636655
Short name T1132
Test name
Test status
Simulation time 95579700372 ps
CPU time 75.15 seconds
Started Apr 23 02:03:45 PM PDT 24
Finished Apr 23 02:05:00 PM PDT 24
Peak memory 200828 kb
Host smart-7d8f9b71-90e8-4e20-9b5e-cd03a697c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648636655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.648636655
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1301399488
Short name T59
Test name
Test status
Simulation time 59213440090 ps
CPU time 260.29 seconds
Started Apr 23 02:03:45 PM PDT 24
Finished Apr 23 02:08:05 PM PDT 24
Peak memory 217500 kb
Host smart-f614bbc1-a1ef-4b88-abb3-cc71661fd806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301399488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1301399488
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3892233882
Short name T685
Test name
Test status
Simulation time 109417696819 ps
CPU time 320.17 seconds
Started Apr 23 02:03:47 PM PDT 24
Finished Apr 23 02:09:08 PM PDT 24
Peak memory 200908 kb
Host smart-43656dc6-d21c-48c0-9bd2-b4dde7094817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892233882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3892233882
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.287955500
Short name T445
Test name
Test status
Simulation time 31704896174 ps
CPU time 643.42 seconds
Started Apr 23 02:03:47 PM PDT 24
Finished Apr 23 02:14:31 PM PDT 24
Peak memory 217372 kb
Host smart-c5e224c6-658d-4c5d-bf2a-e0204eb45fc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287955500 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.287955500
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2873785022
Short name T166
Test name
Test status
Simulation time 50910107077 ps
CPU time 48.49 seconds
Started Apr 23 02:03:45 PM PDT 24
Finished Apr 23 02:04:34 PM PDT 24
Peak memory 200940 kb
Host smart-51e0db78-d91b-4908-a345-510ab4706fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873785022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2873785022
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.4017849028
Short name T125
Test name
Test status
Simulation time 79603448983 ps
CPU time 1128.04 seconds
Started Apr 23 02:03:50 PM PDT 24
Finished Apr 23 02:22:38 PM PDT 24
Peak memory 232452 kb
Host smart-45abbcaf-3b93-46df-b16e-2c8f83b2bc74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017849028 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.4017849028
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.804060304
Short name T262
Test name
Test status
Simulation time 113158932683 ps
CPU time 56.73 seconds
Started Apr 23 02:03:50 PM PDT 24
Finished Apr 23 02:04:47 PM PDT 24
Peak memory 200828 kb
Host smart-ea5877fe-5f3e-4a81-b5a2-38c19830a372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804060304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.804060304
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3065244698
Short name T1007
Test name
Test status
Simulation time 123315807368 ps
CPU time 495.51 seconds
Started Apr 23 02:03:48 PM PDT 24
Finished Apr 23 02:12:04 PM PDT 24
Peak memory 211248 kb
Host smart-83e96890-1ec8-423d-afd7-4f613b3382eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065244698 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3065244698
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3948554095
Short name T787
Test name
Test status
Simulation time 112365957168 ps
CPU time 166.3 seconds
Started Apr 23 02:03:49 PM PDT 24
Finished Apr 23 02:06:36 PM PDT 24
Peak memory 200788 kb
Host smart-b8daf3c4-a630-4fe2-a08a-c65e3cb1c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948554095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3948554095
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1404127221
Short name T896
Test name
Test status
Simulation time 168991401371 ps
CPU time 636.61 seconds
Started Apr 23 02:03:48 PM PDT 24
Finished Apr 23 02:14:25 PM PDT 24
Peak memory 217300 kb
Host smart-16ece3b4-45ec-4305-a9b1-b889d79e2c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404127221 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1404127221
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.4098969914
Short name T222
Test name
Test status
Simulation time 196029483279 ps
CPU time 165.82 seconds
Started Apr 23 02:03:53 PM PDT 24
Finished Apr 23 02:06:39 PM PDT 24
Peak memory 200808 kb
Host smart-183fd48d-566a-41e4-94a1-7b23ccb68480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098969914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.4098969914
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2160617229
Short name T1174
Test name
Test status
Simulation time 120052699290 ps
CPU time 254.67 seconds
Started Apr 23 02:03:53 PM PDT 24
Finished Apr 23 02:08:08 PM PDT 24
Peak memory 209316 kb
Host smart-85f49a4b-580a-4717-a6f0-e0f9eae24318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160617229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2160617229
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3016081737
Short name T1054
Test name
Test status
Simulation time 12176823245 ps
CPU time 11.06 seconds
Started Apr 23 02:03:54 PM PDT 24
Finished Apr 23 02:04:05 PM PDT 24
Peak memory 200904 kb
Host smart-1c93b610-961f-4a43-ad85-036fc5dd6fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016081737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3016081737
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.935966681
Short name T1082
Test name
Test status
Simulation time 99911833483 ps
CPU time 467.21 seconds
Started Apr 23 02:03:55 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 227376 kb
Host smart-e47a3975-3ea2-4531-abc4-b538f5f9774b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935966681 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.935966681
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1999054763
Short name T556
Test name
Test status
Simulation time 8304963986 ps
CPU time 9.49 seconds
Started Apr 23 02:03:53 PM PDT 24
Finished Apr 23 02:04:03 PM PDT 24
Peak memory 200784 kb
Host smart-ff49b68d-cf50-4c90-baca-a3ffa46578f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999054763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1999054763
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.174471366
Short name T535
Test name
Test status
Simulation time 128240529993 ps
CPU time 593.54 seconds
Started Apr 23 02:03:58 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 217508 kb
Host smart-36638b85-e623-4195-aa34-18780f738b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174471366 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.174471366
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2751124135
Short name T598
Test name
Test status
Simulation time 15957598 ps
CPU time 0.56 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:58:37 PM PDT 24
Peak memory 196208 kb
Host smart-ad5f3f9a-8d4d-452a-a971-b5381aaf779c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751124135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2751124135
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1408527288
Short name T981
Test name
Test status
Simulation time 29035879114 ps
CPU time 25.16 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:58:56 PM PDT 24
Peak memory 200804 kb
Host smart-29f2641f-b42d-43a5-adf9-994e94faaa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408527288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1408527288
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.970594149
Short name T721
Test name
Test status
Simulation time 64362388541 ps
CPU time 120.58 seconds
Started Apr 23 01:58:32 PM PDT 24
Finished Apr 23 02:00:33 PM PDT 24
Peak memory 200812 kb
Host smart-927fc170-3d85-4061-bf87-371e5e914059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970594149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.970594149
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.530628134
Short name T943
Test name
Test status
Simulation time 17064573612 ps
CPU time 29.18 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 01:58:59 PM PDT 24
Peak memory 200608 kb
Host smart-5a89b476-c467-46bc-926a-4a0636964d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530628134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.530628134
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1739415080
Short name T880
Test name
Test status
Simulation time 6282554342 ps
CPU time 9.78 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:58:41 PM PDT 24
Peak memory 197648 kb
Host smart-11b33fa7-f4c5-49db-8c8b-e4640eda73d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739415080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1739415080
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2038119892
Short name T426
Test name
Test status
Simulation time 281452446598 ps
CPU time 366.87 seconds
Started Apr 23 01:58:28 PM PDT 24
Finished Apr 23 02:04:36 PM PDT 24
Peak memory 200816 kb
Host smart-50c08352-387c-4929-a037-52fd51a5cbae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038119892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2038119892
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2878665009
Short name T758
Test name
Test status
Simulation time 4764621604 ps
CPU time 5.1 seconds
Started Apr 23 01:58:29 PM PDT 24
Finished Apr 23 01:58:35 PM PDT 24
Peak memory 200520 kb
Host smart-ee2cf31c-683d-4617-9074-04964103bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878665009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2878665009
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2393999673
Short name T1139
Test name
Test status
Simulation time 28383731065 ps
CPU time 50.92 seconds
Started Apr 23 01:58:31 PM PDT 24
Finished Apr 23 01:59:23 PM PDT 24
Peak memory 200944 kb
Host smart-65ad309f-c267-4ed0-9c24-e06d6a770517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393999673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2393999673
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3059788647
Short name T296
Test name
Test status
Simulation time 8453452085 ps
CPU time 97.47 seconds
Started Apr 23 01:58:31 PM PDT 24
Finished Apr 23 02:00:09 PM PDT 24
Peak memory 200840 kb
Host smart-62d7236b-834c-4c01-9f1d-051f1aa46780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3059788647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3059788647
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3952940557
Short name T957
Test name
Test status
Simulation time 5396173741 ps
CPU time 44.17 seconds
Started Apr 23 01:58:33 PM PDT 24
Finished Apr 23 01:59:18 PM PDT 24
Peak memory 199168 kb
Host smart-961b4818-c665-4bf0-ae82-edf9aeeb3a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952940557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3952940557
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2201789938
Short name T504
Test name
Test status
Simulation time 38829063745 ps
CPU time 38.45 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:59:09 PM PDT 24
Peak memory 200880 kb
Host smart-1cc20e0a-64e5-4f1a-945a-28fed784b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201789938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2201789938
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1494906277
Short name T596
Test name
Test status
Simulation time 36905619886 ps
CPU time 60.99 seconds
Started Apr 23 01:58:31 PM PDT 24
Finished Apr 23 01:59:32 PM PDT 24
Peak memory 196884 kb
Host smart-1d5fd251-1f9f-4f4b-b765-165a980a533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494906277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1494906277
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.625602606
Short name T440
Test name
Test status
Simulation time 479990158 ps
CPU time 1.44 seconds
Started Apr 23 01:58:32 PM PDT 24
Finished Apr 23 01:58:34 PM PDT 24
Peak memory 200196 kb
Host smart-5ea69416-ef6c-46d4-950f-32c94c31d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625602606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.625602606
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4256478249
Short name T1112
Test name
Test status
Simulation time 186684770527 ps
CPU time 1046.82 seconds
Started Apr 23 01:58:33 PM PDT 24
Finished Apr 23 02:16:01 PM PDT 24
Peak memory 200836 kb
Host smart-b02b714b-3d88-4be8-a2a0-be9aa667c6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256478249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4256478249
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2481748791
Short name T704
Test name
Test status
Simulation time 476285025787 ps
CPU time 432.94 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 02:05:49 PM PDT 24
Peak memory 228008 kb
Host smart-13627a5a-d70b-4528-b2d0-d5a0f185f8e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481748791 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2481748791
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.946714578
Short name T826
Test name
Test status
Simulation time 1029555219 ps
CPU time 2.17 seconds
Started Apr 23 01:58:31 PM PDT 24
Finished Apr 23 01:58:34 PM PDT 24
Peak memory 199248 kb
Host smart-50dd4224-5bd4-4838-8423-8177c6b50597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946714578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.946714578
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1994677418
Short name T935
Test name
Test status
Simulation time 152558926662 ps
CPU time 68.44 seconds
Started Apr 23 01:58:30 PM PDT 24
Finished Apr 23 01:59:39 PM PDT 24
Peak memory 200812 kb
Host smart-2e89a6a7-9787-4190-8dd2-3d1d5b617a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994677418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1994677418
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1073805472
Short name T167
Test name
Test status
Simulation time 100522792753 ps
CPU time 80.21 seconds
Started Apr 23 02:03:59 PM PDT 24
Finished Apr 23 02:05:20 PM PDT 24
Peak memory 200852 kb
Host smart-d9139682-d22f-4301-9182-72de582e270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073805472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1073805472
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3210612023
Short name T779
Test name
Test status
Simulation time 20651217318 ps
CPU time 32.94 seconds
Started Apr 23 02:03:58 PM PDT 24
Finished Apr 23 02:04:31 PM PDT 24
Peak memory 200908 kb
Host smart-1f70be39-d4dd-4648-923c-af5434c0b4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210612023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3210612023
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3445050485
Short name T174
Test name
Test status
Simulation time 121563899233 ps
CPU time 447.2 seconds
Started Apr 23 02:03:57 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 217332 kb
Host smart-76b0d672-3f71-49ee-a1cd-ec0c9dacdcd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445050485 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3445050485
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.968553999
Short name T301
Test name
Test status
Simulation time 23236677330 ps
CPU time 38.89 seconds
Started Apr 23 02:04:04 PM PDT 24
Finished Apr 23 02:04:43 PM PDT 24
Peak memory 200768 kb
Host smart-9970271b-8910-4002-b7a7-1f9afc740f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968553999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.968553999
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3393049312
Short name T955
Test name
Test status
Simulation time 26123681643 ps
CPU time 510.15 seconds
Started Apr 23 02:03:57 PM PDT 24
Finished Apr 23 02:12:28 PM PDT 24
Peak memory 215932 kb
Host smart-e71e0245-c341-45f6-bce1-15a4bf5885b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393049312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3393049312
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2126455673
Short name T214
Test name
Test status
Simulation time 34306598251 ps
CPU time 22.47 seconds
Started Apr 23 02:04:01 PM PDT 24
Finished Apr 23 02:04:24 PM PDT 24
Peak memory 200424 kb
Host smart-28964721-0318-410e-9e0c-d3503a86816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126455673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2126455673
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1617612016
Short name T1169
Test name
Test status
Simulation time 223449000199 ps
CPU time 398.5 seconds
Started Apr 23 02:04:04 PM PDT 24
Finished Apr 23 02:10:43 PM PDT 24
Peak memory 200784 kb
Host smart-ef0f5ad0-b549-4038-a673-ce43dbd3ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617612016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1617612016
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3999042799
Short name T585
Test name
Test status
Simulation time 76445747606 ps
CPU time 407.07 seconds
Started Apr 23 02:04:02 PM PDT 24
Finished Apr 23 02:10:49 PM PDT 24
Peak memory 217520 kb
Host smart-f5643ec0-c661-4a8b-81a5-643cc33de674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999042799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3999042799
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.656413481
Short name T960
Test name
Test status
Simulation time 34591662956 ps
CPU time 53.92 seconds
Started Apr 23 02:03:59 PM PDT 24
Finished Apr 23 02:04:53 PM PDT 24
Peak memory 200764 kb
Host smart-c3dd9fe6-6a37-4487-9ff9-08b30456a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656413481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.656413481
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1773653535
Short name T127
Test name
Test status
Simulation time 128476484683 ps
CPU time 1342.92 seconds
Started Apr 23 02:04:05 PM PDT 24
Finished Apr 23 02:26:29 PM PDT 24
Peak memory 225752 kb
Host smart-3253cb21-bca4-491a-b34a-e8a0729e4644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773653535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1773653535
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2447580828
Short name T783
Test name
Test status
Simulation time 287748609174 ps
CPU time 43.95 seconds
Started Apr 23 02:04:05 PM PDT 24
Finished Apr 23 02:04:49 PM PDT 24
Peak memory 200792 kb
Host smart-3a697639-7b4d-4a98-be3e-8a9a43f65001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447580828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2447580828
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3108979450
Short name T550
Test name
Test status
Simulation time 80639183918 ps
CPU time 1069.65 seconds
Started Apr 23 02:04:08 PM PDT 24
Finished Apr 23 02:21:59 PM PDT 24
Peak memory 233940 kb
Host smart-c9197e13-9dab-42ab-bc75-6f7be381a8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108979450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3108979450
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2101031155
Short name T203
Test name
Test status
Simulation time 67963544063 ps
CPU time 66.13 seconds
Started Apr 23 02:04:03 PM PDT 24
Finished Apr 23 02:05:10 PM PDT 24
Peak memory 200780 kb
Host smart-120cb0a4-59d0-4794-b26a-3792a79b5f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101031155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2101031155
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.4222127830
Short name T114
Test name
Test status
Simulation time 23954298171 ps
CPU time 127.02 seconds
Started Apr 23 02:04:05 PM PDT 24
Finished Apr 23 02:06:12 PM PDT 24
Peak memory 216460 kb
Host smart-d707bf9a-b2f9-45ad-af88-9477e049e0e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222127830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.4222127830
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.199933938
Short name T134
Test name
Test status
Simulation time 98382546642 ps
CPU time 149.92 seconds
Started Apr 23 02:04:03 PM PDT 24
Finished Apr 23 02:06:34 PM PDT 24
Peak memory 200856 kb
Host smart-dd7e7590-bf9e-49a7-8cf3-095dfabfe864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199933938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.199933938
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3918114345
Short name T329
Test name
Test status
Simulation time 23365459327 ps
CPU time 272.34 seconds
Started Apr 23 02:04:05 PM PDT 24
Finished Apr 23 02:08:38 PM PDT 24
Peak memory 217524 kb
Host smart-d8c9c6bc-5422-42c5-8f64-f2d879fdd804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918114345 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3918114345
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3911216866
Short name T208
Test name
Test status
Simulation time 44275237671 ps
CPU time 23.06 seconds
Started Apr 23 02:04:05 PM PDT 24
Finished Apr 23 02:04:28 PM PDT 24
Peak memory 200712 kb
Host smart-c0f040b2-efbd-4165-af35-b1bb9e837a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911216866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3911216866
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.228339259
Short name T1100
Test name
Test status
Simulation time 408894438612 ps
CPU time 241.77 seconds
Started Apr 23 02:04:08 PM PDT 24
Finished Apr 23 02:08:11 PM PDT 24
Peak memory 211892 kb
Host smart-9ed6e66a-dc88-4661-8c12-9d2cad3ecfcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228339259 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.228339259
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3546022440
Short name T850
Test name
Test status
Simulation time 11961829 ps
CPU time 0.58 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:58:37 PM PDT 24
Peak memory 196172 kb
Host smart-da35ad81-8236-41ea-a4d6-0cbe3773636b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546022440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3546022440
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1094818230
Short name T717
Test name
Test status
Simulation time 81019748015 ps
CPU time 31.77 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:59:11 PM PDT 24
Peak memory 200772 kb
Host smart-9019a0b1-36e5-4c67-a609-51379b390ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094818230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1094818230
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2855090977
Short name T546
Test name
Test status
Simulation time 22489088215 ps
CPU time 14 seconds
Started Apr 23 01:58:38 PM PDT 24
Finished Apr 23 01:58:52 PM PDT 24
Peak memory 200856 kb
Host smart-79bb349c-82c8-4367-bd0b-e07fc089fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855090977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2855090977
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.1023099091
Short name T838
Test name
Test status
Simulation time 26494286343 ps
CPU time 47.96 seconds
Started Apr 23 01:58:31 PM PDT 24
Finished Apr 23 01:59:20 PM PDT 24
Peak memory 200768 kb
Host smart-5745f771-a868-47db-a55c-bc79e6edf9e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023099091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1023099091
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1589287782
Short name T992
Test name
Test status
Simulation time 181368456663 ps
CPU time 1343.94 seconds
Started Apr 23 01:58:37 PM PDT 24
Finished Apr 23 02:21:02 PM PDT 24
Peak memory 200744 kb
Host smart-ae0b79b2-20a3-4e00-a7bf-1dee15e449c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589287782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1589287782
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1104637611
Short name T681
Test name
Test status
Simulation time 5606197601 ps
CPU time 2.58 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:58:39 PM PDT 24
Peak memory 199892 kb
Host smart-aa7ca0dd-c72e-446c-8517-bbc9382a18ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104637611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1104637611
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.708067315
Short name T874
Test name
Test status
Simulation time 105432723171 ps
CPU time 57.57 seconds
Started Apr 23 01:58:36 PM PDT 24
Finished Apr 23 01:59:35 PM PDT 24
Peak memory 209216 kb
Host smart-6b5f2409-60e2-45bd-a89c-c00117c9f27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708067315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.708067315
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.708686756
Short name T956
Test name
Test status
Simulation time 17750551071 ps
CPU time 1095.12 seconds
Started Apr 23 01:58:38 PM PDT 24
Finished Apr 23 02:16:53 PM PDT 24
Peak memory 200816 kb
Host smart-3610db4a-f100-48a6-8596-691a1dc803b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=708686756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.708686756
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1208714126
Short name T947
Test name
Test status
Simulation time 6384307246 ps
CPU time 53.2 seconds
Started Apr 23 01:58:35 PM PDT 24
Finished Apr 23 01:59:28 PM PDT 24
Peak memory 200044 kb
Host smart-9494aea3-e5e2-4a27-9c1d-6559b1b27a14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208714126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1208714126
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.4169756907
Short name T764
Test name
Test status
Simulation time 16706335934 ps
CPU time 9.05 seconds
Started Apr 23 01:58:33 PM PDT 24
Finished Apr 23 01:58:42 PM PDT 24
Peak memory 200812 kb
Host smart-9f1d09c0-0146-42df-90ed-948ff9cccca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169756907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4169756907
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3600344509
Short name T651
Test name
Test status
Simulation time 2928622827 ps
CPU time 4.35 seconds
Started Apr 23 01:58:34 PM PDT 24
Finished Apr 23 01:58:39 PM PDT 24
Peak memory 196672 kb
Host smart-8b0d6a46-f947-4697-ba94-cc8e2cb00933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600344509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3600344509
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2172420111
Short name T437
Test name
Test status
Simulation time 538739141 ps
CPU time 1.42 seconds
Started Apr 23 01:58:34 PM PDT 24
Finished Apr 23 01:58:36 PM PDT 24
Peak memory 199252 kb
Host smart-57e69505-41ce-43be-a39d-9a96ae8f2ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172420111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2172420111
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4141830959
Short name T724
Test name
Test status
Simulation time 116341796844 ps
CPU time 50.51 seconds
Started Apr 23 01:58:39 PM PDT 24
Finished Apr 23 01:59:30 PM PDT 24
Peak memory 200856 kb
Host smart-8b70b6cb-ce14-468e-98fd-c3d402227cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141830959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4141830959
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.4079023522
Short name T905
Test name
Test status
Simulation time 622746820695 ps
CPU time 604.37 seconds
Started Apr 23 01:58:37 PM PDT 24
Finished Apr 23 02:08:42 PM PDT 24
Peak memory 211724 kb
Host smart-270ed151-d33f-4ffc-b683-b66e382e7ce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079023522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.4079023522
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.563793531
Short name T1134
Test name
Test status
Simulation time 1187710740 ps
CPU time 1.21 seconds
Started Apr 23 01:58:34 PM PDT 24
Finished Apr 23 01:58:36 PM PDT 24
Peak memory 197960 kb
Host smart-d2e16d51-cb9b-4e18-ba89-7ed7c51ff2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563793531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.563793531
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.4061934663
Short name T699
Test name
Test status
Simulation time 5050935421 ps
CPU time 4.52 seconds
Started Apr 23 01:58:33 PM PDT 24
Finished Apr 23 01:58:38 PM PDT 24
Peak memory 198884 kb
Host smart-49efaaac-d341-45d8-a684-fae74387f59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061934663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.4061934663
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.40559580
Short name T116
Test name
Test status
Simulation time 370568602199 ps
CPU time 222 seconds
Started Apr 23 02:04:11 PM PDT 24
Finished Apr 23 02:07:53 PM PDT 24
Peak memory 210208 kb
Host smart-63390e58-f8f1-4f0a-a59a-03b30c25ed01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40559580 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.40559580
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3744824018
Short name T558
Test name
Test status
Simulation time 90891072223 ps
CPU time 126.92 seconds
Started Apr 23 02:04:12 PM PDT 24
Finished Apr 23 02:06:19 PM PDT 24
Peak memory 200776 kb
Host smart-723ba3f0-3b46-49c9-9746-c7e7844aa3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744824018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3744824018
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2123240869
Short name T80
Test name
Test status
Simulation time 257215844020 ps
CPU time 834.65 seconds
Started Apr 23 02:04:12 PM PDT 24
Finished Apr 23 02:18:07 PM PDT 24
Peak memory 227992 kb
Host smart-c5d30ec3-f5b1-4a4f-ad61-bf5307f20abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123240869 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2123240869
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3172774585
Short name T1041
Test name
Test status
Simulation time 320434883387 ps
CPU time 94.76 seconds
Started Apr 23 02:04:14 PM PDT 24
Finished Apr 23 02:05:49 PM PDT 24
Peak memory 200752 kb
Host smart-be177545-7fc9-413b-bc44-de4f6df970b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172774585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3172774585
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1514513721
Short name T965
Test name
Test status
Simulation time 58598623865 ps
CPU time 595.24 seconds
Started Apr 23 02:04:13 PM PDT 24
Finished Apr 23 02:14:09 PM PDT 24
Peak memory 225604 kb
Host smart-59b89939-dc5d-47b6-a43c-58de3bbb25be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514513721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1514513721
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.35553476
Short name T245
Test name
Test status
Simulation time 91146119778 ps
CPU time 58.83 seconds
Started Apr 23 02:04:11 PM PDT 24
Finished Apr 23 02:05:10 PM PDT 24
Peak memory 200868 kb
Host smart-e3e4f1f7-795b-4c15-96b5-99edadb82397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35553476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.35553476
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1639487100
Short name T736
Test name
Test status
Simulation time 150375083704 ps
CPU time 375.23 seconds
Started Apr 23 02:04:12 PM PDT 24
Finished Apr 23 02:10:27 PM PDT 24
Peak memory 217252 kb
Host smart-37d01abf-4bb4-499d-a90a-4c91ef1f6de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639487100 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1639487100
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1305946945
Short name T387
Test name
Test status
Simulation time 108769599588 ps
CPU time 177.66 seconds
Started Apr 23 02:04:14 PM PDT 24
Finished Apr 23 02:07:12 PM PDT 24
Peak memory 200772 kb
Host smart-c661d851-178f-4ceb-a14c-eeef3f19b2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305946945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1305946945
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.728135801
Short name T600
Test name
Test status
Simulation time 33846664607 ps
CPU time 103.94 seconds
Started Apr 23 02:04:18 PM PDT 24
Finished Apr 23 02:06:03 PM PDT 24
Peak memory 216460 kb
Host smart-8735e225-7ce0-44ed-9d09-4c71edf1098c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728135801 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.728135801
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1226001201
Short name T821
Test name
Test status
Simulation time 175563857175 ps
CPU time 300.46 seconds
Started Apr 23 02:04:13 PM PDT 24
Finished Apr 23 02:09:14 PM PDT 24
Peak memory 200880 kb
Host smart-d541bc66-92e8-419b-92b5-cee67169b003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226001201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1226001201
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.275211162
Short name T31
Test name
Test status
Simulation time 30064296872 ps
CPU time 262.93 seconds
Started Apr 23 02:04:17 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 216840 kb
Host smart-9a212e69-c06b-452d-8101-403d565ebf1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275211162 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.275211162
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.4256143196
Short name T722
Test name
Test status
Simulation time 106422677337 ps
CPU time 33.43 seconds
Started Apr 23 02:04:16 PM PDT 24
Finished Apr 23 02:04:50 PM PDT 24
Peak memory 200832 kb
Host smart-e5b429e9-122b-40cb-bb8a-44c1fdea60ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256143196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4256143196
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2954580254
Short name T977
Test name
Test status
Simulation time 68250150049 ps
CPU time 448.78 seconds
Started Apr 23 02:04:14 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 217376 kb
Host smart-36e961d9-83f5-4638-be9a-09e101892025
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954580254 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2954580254
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3520296700
Short name T990
Test name
Test status
Simulation time 81480540844 ps
CPU time 67.29 seconds
Started Apr 23 02:04:14 PM PDT 24
Finished Apr 23 02:05:22 PM PDT 24
Peak memory 200808 kb
Host smart-ae98b3ff-21cd-47f1-8a04-0f89bd1011ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520296700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3520296700
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3778865432
Short name T612
Test name
Test status
Simulation time 56361301211 ps
CPU time 353.49 seconds
Started Apr 23 02:04:15 PM PDT 24
Finished Apr 23 02:10:09 PM PDT 24
Peak memory 217444 kb
Host smart-7edf484c-9e61-4619-8084-780e818c1b5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778865432 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3778865432
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4226110386
Short name T446
Test name
Test status
Simulation time 59504048427 ps
CPU time 47.88 seconds
Started Apr 23 02:04:16 PM PDT 24
Finished Apr 23 02:05:04 PM PDT 24
Peak memory 200652 kb
Host smart-1cf5d6f0-fc69-4e5a-979f-ebd1fad8bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226110386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4226110386
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1644723292
Short name T431
Test name
Test status
Simulation time 21845899279 ps
CPU time 134.88 seconds
Started Apr 23 02:04:16 PM PDT 24
Finished Apr 23 02:06:32 PM PDT 24
Peak memory 216924 kb
Host smart-7bc989ab-a3e9-4819-8088-a73e1efe175c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644723292 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1644723292
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1567840623
Short name T885
Test name
Test status
Simulation time 52514654935 ps
CPU time 23.33 seconds
Started Apr 23 02:04:16 PM PDT 24
Finished Apr 23 02:04:40 PM PDT 24
Peak memory 200812 kb
Host smart-d0463dc4-ef26-411e-9be3-5fc8d4b7ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567840623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1567840623
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.627042722
Short name T987
Test name
Test status
Simulation time 19971661224 ps
CPU time 166.69 seconds
Started Apr 23 02:04:17 PM PDT 24
Finished Apr 23 02:07:04 PM PDT 24
Peak memory 217208 kb
Host smart-d2069584-83cc-44a1-998a-5a986c58d881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627042722 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.627042722
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%