Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.49 98.92 99.02 96.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.uart_core 98.98 98.92 99.02 97.96 100.00



Module Instance : tb.dut.uart_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.98 98.92 99.02 97.96 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.85 99.69 96.41 99.29 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
intr_hw_rx_break_err 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_frame_err 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_overflow 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_parity_err 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_timeout 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_watermark 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_empty 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_watermark 94.44 100.00 77.78 100.00 100.00
sync_rx 100.00 100.00 100.00
u_uart_rxfifo 97.22 100.00 88.89 100.00 100.00
u_uart_txfifo 97.22 100.00 88.89 100.00 100.00
uart_rx 100.00 100.00 100.00 100.00
uart_tx 100.00 100.00 100.00 100.00

Line Coverage for Module : uart_core
Line No.TotalCoveredPercent
TOTAL939298.92
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9611100.00
ALWAYS10344100.00
ALWAYS11144100.00
ALWAYS12077100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS16444100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN21111100.00
ALWAYS21377100.00
ALWAYS24455100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN27811100.00
ALWAYS30044100.00
ALWAYS31244100.00
CONT_ASSIGN33011100.00
ALWAYS33333100.00
ALWAYS3436583.33
CONT_ASSIGN35911100.00
CONT_ASSIGN36011100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36411100.00
CONT_ASSIGN38211100.00
ALWAYS38555100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN50511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
77 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
92 1 1
93 1 1
96 1 1
103 2 2
104 2 2
MISSING_ELSE
111 1 1
112 1 1
113 1 1
114 1 1
120 2 2
122 1 1
124 2 2
MISSING_ELSE
128 2 2
MISSING_ELSE
138 1 1
140 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
149 1 1
150 1 1
164 1 1
165 1 1
166 1 1
167 1 1
MISSING_ELSE
171 1 1
177 1 1
211 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
244 1 1
245 1 1
246 1 1
248 1 1
249 1 1
253 1 1
256 1 1
258 1 1
278 1 1
300 2 2
301 2 2
MISSING_ELSE
312 1 1
313 1 1
315 1 1
317 1 1
330 1 1
333 1 1
334 1 1
336 1 1
343 1 1
346 0 1
347 1 1
349 1 1
351 1 1
353 1 1
359 1 1
360 1 1
362 1 1
364 1 1
382 1 1
385 1 1
386 1 1
387 1 1
389 1 1
390 1 1
394 1 1
395 1 1
505 1 1


Cond Coverage for Module : uart_core
TotalCoveredPercent
Conditions10210199.02
Logical10210199.02
Non-Logical00
Event00

 LINE       77
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T6
11CoveredT2,T5,T6

 LINE       78
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       92
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T13,T17
11CoveredT1,T2,T3

 LINE       92
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------
-1--2-StatusTests
00CoveredT9,T13,T17
01CoveredT7,T9,T13
10CoveredT1,T2,T3

 LINE       92
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       93
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T9,T13
11CoveredT9,T13,T17

 LINE       93
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       96
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T13,T17

 LINE       96
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T13,T17

 LINE       96
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T13,T17

 LINE       144
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       166
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       177
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       198
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       211
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T9

 LINE       253
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       253
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       256
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       258
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T9

 LINE       258
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T9

 LINE       278
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T9,T13
110CoveredT7,T9,T15
111CoveredT1,T2,T3

 LINE       330
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       347
 EXPRESSION (uart_fifo_rxilvl == (RxFifoDepthW - 1))
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       362
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T9,T10

 LINE       364
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       382
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T9,T10

 LINE       382
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       394
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT7,T9,T12

 LINE       395
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T13,T17

 LINE       395
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : uart_core
Line No.TotalCoveredPercent
Branches 50 48 96.00
TERNARY 96 3 3 100.00
TERNARY 211 2 2 100.00
TERNARY 256 2 2 100.00
TERNARY 258 3 3 100.00
TERNARY 364 6 6 100.00
IF 103 3 3 100.00
CASE 111 4 4 100.00
IF 120 6 5 83.33
IF 164 3 3 100.00
IF 213 4 4 100.00
IF 244 2 2 100.00
IF 300 3 3 100.00
IF 312 2 2 100.00
IF 333 2 2 100.00
IF 343 3 2 66.67
IF 385 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 (((break_st_q == BRK_WAIT) || not_allzero_char)) ? -2-: 96 (allzero_err) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T13,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 211 (line_loopback) ?

Branches:
-1-StatusTests
1 Covered T2,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 256 (rxnf_enable) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 258 (sys_loopback) ? -2-: 258 (line_loopback) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T6,T9
0 1 Covered T2,T6,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 364 ((uart_rxto_en == 1'b0)) ? -2-: 364 (event_rx_timeout) ? -3-: 364 (rx_fifo_depth_changed) ? -4-: 364 ((rx_fifo_depth == '0)) ? -5-: 364 (rx_tick_baud) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T4,T9,T10
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 103 if ((!rst_ni)) -2-: 104 if (rx_enable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 case (reg2hw.ctrl.rxblvl.q)

Branches:
-1-StatusTests
2'h0 Covered T1,T2,T3
2'h1 Covered T1,T2,T3
2'h2 Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 120 if ((!rst_ni)) -2-: 122 case (break_st_q) -3-: 124 if (event_rx_break_err) -4-: 128 if (rx_in)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 BRK_CHK 1 - Covered T9,T13,T17
0 BRK_CHK 0 - Covered T1,T2,T3
0 BRK_WAIT - 1 Covered T9,T13,T17
0 BRK_WAIT - 0 Covered T9,T13,T17
0 default - - Not Covered


LineNo. Expression -1-: 164 if ((!rst_ni)) -2-: 166 if ((tx_enable || rx_enable))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 213 if ((!rst_ni)) -2-: 215 if (ovrd_tx_en) -3-: 217 if (sys_loopback)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T9,T13,T16
0 0 1 Covered T2,T6,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 244 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 300 if ((!rst_ni)) -2-: 301 if (tick_baud_x16)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 312 if ((uart_fifo_txilvl >= (TxFifoDepthW - 2)))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 333 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 if ((uart_fifo_rxilvl > (RxFifoDepthW - 1))) -2-: 347 if ((uart_fifo_rxilvl == (RxFifoDepthW - 1)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T2,T4,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 385 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : uart_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RxFifoDepth_A 1155 1155 0 0
TxFifoDepth_A 1155 1155 0 0


RxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.uart_core
Line No.TotalCoveredPercent
TOTAL939298.92
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9611100.00
ALWAYS10344100.00
ALWAYS11144100.00
ALWAYS12077100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS16444100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN21111100.00
ALWAYS21377100.00
ALWAYS24455100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN27811100.00
ALWAYS30044100.00
ALWAYS31244100.00
CONT_ASSIGN33011100.00
ALWAYS33333100.00
ALWAYS3436583.33
CONT_ASSIGN35911100.00
CONT_ASSIGN36011100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36411100.00
CONT_ASSIGN38211100.00
ALWAYS38555100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN50511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
77 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
92 1 1
93 1 1
96 1 1
103 2 2
104 2 2
MISSING_ELSE
111 1 1
112 1 1
113 1 1
114 1 1
120 2 2
122 1 1
124 2 2
MISSING_ELSE
128 2 2
MISSING_ELSE
138 1 1
140 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
149 1 1
150 1 1
164 1 1
165 1 1
166 1 1
167 1 1
MISSING_ELSE
171 1 1
177 1 1
211 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
220 1 1
244 1 1
245 1 1
246 1 1
248 1 1
249 1 1
253 1 1
256 1 1
258 1 1
278 1 1
300 2 2
301 2 2
MISSING_ELSE
312 1 1
313 1 1
315 1 1
317 1 1
330 1 1
333 1 1
334 1 1
336 1 1
343 1 1
346 0 1
347 1 1
349 1 1
351 1 1
353 1 1
359 1 1
360 1 1
362 1 1
364 1 1
382 1 1
385 1 1
386 1 1
387 1 1
389 1 1
390 1 1
394 1 1
395 1 1
505 1 1


Cond Coverage for Instance : tb.dut.uart_core
TotalCoveredPercent
Conditions10210199.02
Logical10210199.02
Non-Logical00
Event00

 LINE       77
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T6
11CoveredT2,T5,T6

 LINE       78
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       92
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T13,T17
11CoveredT1,T2,T3

 LINE       92
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------
-1--2-StatusTests
00CoveredT9,T13,T17
01CoveredT7,T9,T13
10CoveredT1,T2,T3

 LINE       92
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       93
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T9,T13
11CoveredT9,T13,T17

 LINE       93
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       96
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T13,T17

 LINE       96
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T13,T17

 LINE       96
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T13,T17

 LINE       144
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       166
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       177
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       198
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       211
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T9

 LINE       253
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       253
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       253
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       256
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       258
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T9

 LINE       258
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T9

 LINE       278
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T9,T13
110CoveredT7,T9,T15
111CoveredT1,T2,T3

 LINE       330
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       347
 EXPRESSION (uart_fifo_rxilvl == (RxFifoDepthW - 1))
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       362
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T9,T10

 LINE       364
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       364
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       382
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T9,T10

 LINE       382
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       394
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT7,T9,T12

 LINE       395
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T13,T17

 LINE       395
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.uart_core
Line No.TotalCoveredPercent
Branches 49 48 97.96
TERNARY 96 3 3 100.00
TERNARY 211 2 2 100.00
TERNARY 256 2 2 100.00
TERNARY 258 3 3 100.00
TERNARY 364 6 6 100.00
IF 103 3 3 100.00
CASE 111 4 4 100.00
IF 120 5 5 100.00
IF 164 3 3 100.00
IF 213 4 4 100.00
IF 244 2 2 100.00
IF 300 3 3 100.00
IF 312 2 2 100.00
IF 333 2 2 100.00
IF 343 3 2 66.67
IF 385 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 (((break_st_q == BRK_WAIT) || not_allzero_char)) ? -2-: 96 (allzero_err) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T13,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 211 (line_loopback) ?

Branches:
-1-StatusTests
1 Covered T2,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 256 (rxnf_enable) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 258 (sys_loopback) ? -2-: 258 (line_loopback) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T6,T9
0 1 Covered T2,T6,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 364 ((uart_rxto_en == 1'b0)) ? -2-: 364 (event_rx_timeout) ? -3-: 364 (rx_fifo_depth_changed) ? -4-: 364 ((rx_fifo_depth == '0)) ? -5-: 364 (rx_tick_baud) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T4,T9,T10
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 103 if ((!rst_ni)) -2-: 104 if (rx_enable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 case (reg2hw.ctrl.rxblvl.q)

Branches:
-1-StatusTests
2'h0 Covered T1,T2,T3
2'h1 Covered T1,T2,T3
2'h2 Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 120 if ((!rst_ni)) -2-: 122 case (break_st_q) -3-: 124 if (event_rx_break_err) -4-: 128 if (rx_in)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 BRK_CHK 1 - Covered T9,T13,T17
0 BRK_CHK 0 - Covered T1,T2,T3
0 BRK_WAIT - 1 Covered T9,T13,T17
0 BRK_WAIT - 0 Covered T9,T13,T17
0 default - - Excluded


LineNo. Expression -1-: 164 if ((!rst_ni)) -2-: 166 if ((tx_enable || rx_enable))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 213 if ((!rst_ni)) -2-: 215 if (ovrd_tx_en) -3-: 217 if (sys_loopback)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T9,T13,T16
0 0 1 Covered T2,T6,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 244 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 300 if ((!rst_ni)) -2-: 301 if (tick_baud_x16)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 312 if ((uart_fifo_txilvl >= (TxFifoDepthW - 2)))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 333 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 if ((uart_fifo_rxilvl > (RxFifoDepthW - 1))) -2-: 347 if ((uart_fifo_rxilvl == (RxFifoDepthW - 1)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T2,T4,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 385 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.uart_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RxFifoDepth_A 1155 1155 0 0
TxFifoDepth_A 1155 1155 0 0


RxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%