Module Definition
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Module : uart_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.uart_csr_assert 100.00 100.00



Module Instance : tb.dut.uart_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : uart_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
TlulOOBAddrErr_A 2147483647 17152417 0 0
ctrl_rd_A 2147483647 230405 0 0
intr_enable_rd_A 2147483647 205302 0 0
ovrd_rd_A 2147483647 229377 0 0
timeout_ctrl_rd_A 2147483647 230429 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 17152417 0 0
T2 415867 119994 0 0
T3 157044 0 0 0
T4 424089 0 0 0
T5 179728 0 0 0
T6 342175 0 0 0
T7 116517 0 0 0
T8 130358 0 0 0
T9 815972 276180 0 0
T10 261301 0 0 0
T11 109573 0 0 0
T13 0 238814 0 0
T14 0 20439 0 0
T16 0 122126 0 0
T24 0 139544 0 0
T25 0 147579 0 0
T26 0 93078 0 0
T27 0 145187 0 0
T28 0 52946 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 230405 0 0
T9 815972 9567 0 0
T10 261301 0 0 0
T11 109573 0 0 0
T12 159933 0 0 0
T13 768453 12322 0 0
T15 523708 0 0 0
T16 0 6642 0 0
T24 0 7068 0 0
T25 0 16670 0 0
T26 0 4886 0 0
T27 0 7307 0 0
T28 0 5482 0 0
T29 237751 0 0 0
T30 516488 0 0 0
T69 614136 0 0 0
T93 0 24022 0 0
T94 0 3477 0 0
T95 298236 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 205302 0 0
T9 815972 8451 0 0
T10 261301 0 0 0
T11 109573 0 0 0
T12 159933 0 0 0
T13 768453 11258 0 0
T15 523708 0 0 0
T16 0 5382 0 0
T24 0 5919 0 0
T25 0 14575 0 0
T26 0 4498 0 0
T27 0 6515 0 0
T28 0 5333 0 0
T29 237751 0 0 0
T30 516488 0 0 0
T69 614136 0 0 0
T93 0 21881 0 0
T94 0 3026 0 0
T95 298236 0 0 0

ovrd_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 229377 0 0
T9 815972 9938 0 0
T10 261301 0 0 0
T11 109573 0 0 0
T12 159933 0 0 0
T13 768453 12025 0 0
T15 523708 0 0 0
T16 0 6173 0 0
T24 0 6801 0 0
T25 0 16349 0 0
T26 0 5043 0 0
T27 0 7369 0 0
T28 0 5259 0 0
T29 237751 0 0 0
T30 516488 0 0 0
T69 614136 0 0 0
T93 0 24792 0 0
T94 0 3485 0 0
T95 298236 0 0 0

timeout_ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 230429 0 0
T9 815972 9343 0 0
T10 261301 0 0 0
T11 109573 0 0 0
T12 159933 0 0 0
T13 768453 12153 0 0
T15 523708 0 0 0
T16 0 6307 0 0
T24 0 6988 0 0
T25 0 16833 0 0
T26 0 4928 0 0
T27 0 7575 0 0
T28 0 5357 0 0
T29 237751 0 0 0
T30 516488 0 0 0
T69 614136 0 0 0
T93 0 24397 0 0
T94 0 3370 0 0
T95 298236 0 0 0