Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74235896	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30198596

1

T1

123

T2

148

T3

43330

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93972793	1			T1	78		T2	941		T3	237692
values[0x0]	4941477	1			T1	105		T2	98		T3	1925
values[0x1]	5520222	1			T1	114		T2	92		T3	1887

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51533460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52901032

1

T1

150

T2

418

T3

103270

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	413781	1			T2	3		T3	921		T4	120
valid_sources[0x01]	412243	1			T2	5		T3	967		T4	133
valid_sources[0x02]	381346	1			T2	3		T3	940		T4	156
valid_sources[0x03]	400033	1			T1	45		T2	2		T3	951
valid_sources[0x04]	427142	1			T3	952		T4	152		T7	175
valid_sources[0x05]	399070	1			T2	5		T3	959		T4	106
valid_sources[0x06]	400998	1			T2	3		T3	893		T4	135
valid_sources[0x07]	394635	1			T1	17		T2	1		T3	910
valid_sources[0x08]	390962	1			T2	9		T3	974		T4	147
valid_sources[0x09]	391425	1			T2	5		T3	968		T4	137
valid_sources[0x0a]	529421	1			T2	5		T3	934		T4	148
valid_sources[0x0b]	399451	1			T2	6		T3	970		T4	134
valid_sources[0x0c]	434149	1			T3	1000		T4	106		T7	80
valid_sources[0x0d]	422733	1			T3	1042		T4	151		T5	7
valid_sources[0x0e]	396462	1			T2	12		T3	932		T4	123
valid_sources[0x0f]	462325	1			T2	6		T3	863		T4	117
valid_sources[0x10]	397450	1			T2	2		T3	976		T4	121
valid_sources[0x11]	388540	1			T2	5		T3	950		T4	184
valid_sources[0x12]	388778	1			T2	2		T3	909		T4	132
valid_sources[0x13]	500588	1			T2	1		T3	985		T4	182
valid_sources[0x14]	473074	1			T2	2		T3	909		T4	132
valid_sources[0x15]	395256	1			T2	2		T3	874		T4	120
valid_sources[0x16]	408744	1			T2	12		T3	917		T4	125
valid_sources[0x17]	406745	1			T2	3		T3	923		T4	129
valid_sources[0x18]	387917	1			T2	6		T3	900		T4	138
valid_sources[0x19]	389050	1			T2	2		T3	923		T4	113
valid_sources[0x1a]	403463	1			T2	3		T3	944		T4	120
valid_sources[0x1b]	388450	1			T2	3		T3	887		T4	155
valid_sources[0x1c]	376292	1			T2	5		T3	901		T4	157
valid_sources[0x1d]	387862	1			T2	1		T3	951		T4	138
valid_sources[0x1e]	395764	1			T2	8		T3	983		T4	176
valid_sources[0x1f]	377601	1			T1	8		T2	6		T3	966
valid_sources[0x20]	370826	1			T2	4		T3	922		T4	156
valid_sources[0x21]	379466	1			T2	3		T3	954		T4	160
valid_sources[0x22]	389134	1			T2	3		T3	932		T4	171
valid_sources[0x23]	391892	1			T2	3		T3	967		T4	158
valid_sources[0x24]	379120	1			T2	5		T3	1001		T4	141
valid_sources[0x25]	435131	1			T2	6		T3	958		T4	142
valid_sources[0x26]	406918	1			T2	2		T3	969		T4	157
valid_sources[0x27]	418100	1			T2	4		T3	992		T4	150
valid_sources[0x28]	393553	1			T2	3		T3	991		T4	150
valid_sources[0x29]	391791	1			T2	5		T3	978		T4	126
valid_sources[0x2a]	380450	1			T1	21		T2	2		T3	951
valid_sources[0x2b]	439581	1			T2	3		T3	907		T4	156
valid_sources[0x2c]	392305	1			T2	4		T3	1028		T4	127
valid_sources[0x2d]	382567	1			T2	3		T3	898		T4	108
valid_sources[0x2e]	422293	1			T2	11		T3	920		T4	127
valid_sources[0x2f]	401027	1			T2	5		T3	960		T4	117
valid_sources[0x30]	387447	1			T2	4		T3	948		T4	109
valid_sources[0x31]	400359	1			T2	3		T3	936		T4	106
valid_sources[0x32]	427041	1			T2	5		T3	954		T4	159
valid_sources[0x33]	400830	1			T2	5		T3	975		T4	144
valid_sources[0x34]	392735	1			T2	4		T3	955		T4	116
valid_sources[0x35]	385429	1			T1	66		T2	3		T3	947
valid_sources[0x36]	382480	1			T1	14		T2	4		T3	940
valid_sources[0x37]	479063	1			T2	7		T3	920		T4	110
valid_sources[0x38]	444192	1			T2	7		T3	935		T4	125
valid_sources[0x39]	412791	1			T2	3		T3	905		T4	150
valid_sources[0x3a]	384696	1			T2	2		T3	948		T4	178
valid_sources[0x3b]	478347	1			T2	3		T3	962		T4	105
valid_sources[0x3c]	407639	1			T2	4		T3	944		T4	131
valid_sources[0x3d]	430297	1			T2	7		T3	912		T4	127
valid_sources[0x3e]	399873	1			T2	1		T3	931		T4	134
valid_sources[0x3f]	406620	1			T2	11		T3	886		T4	109
valid_sources[0x40]	398508	1			T2	2		T3	951		T4	122
valid_sources[0x41]	387144	1			T2	8		T3	900		T4	155
valid_sources[0x42]	451637	1			T2	7		T3	943		T4	116
valid_sources[0x43]	390779	1			T2	3		T3	939		T4	115
valid_sources[0x44]	429933	1			T2	2		T3	950		T4	151
valid_sources[0x45]	430775	1			T1	10		T2	4		T3	956
valid_sources[0x46]	398942	1			T2	9		T3	934		T4	158
valid_sources[0x47]	411045	1			T2	3		T3	941		T4	116
valid_sources[0x48]	489696	1			T2	1		T3	940		T4	130
valid_sources[0x49]	392072	1			T2	6		T3	958		T4	138
valid_sources[0x4a]	404246	1			T2	3		T3	1038		T4	116
valid_sources[0x4b]	436842	1			T2	2		T3	888		T4	168
valid_sources[0x4c]	397701	1			T2	6		T3	982		T4	178
valid_sources[0x4d]	448847	1			T2	4		T3	999		T4	156
valid_sources[0x4e]	481516	1			T2	9		T3	966		T4	166
valid_sources[0x4f]	406715	1			T2	9		T3	947		T4	146
valid_sources[0x50]	403219	1			T2	8		T3	962		T4	148
valid_sources[0x51]	413019	1			T2	5		T3	987		T4	118
valid_sources[0x52]	411209	1			T2	5		T3	927		T4	162
valid_sources[0x53]	386519	1			T1	3		T2	3		T3	899
valid_sources[0x54]	484566	1			T2	6		T3	949		T4	133
valid_sources[0x55]	397089	1			T2	1		T3	933		T4	116
valid_sources[0x56]	415393	1			T2	1		T3	1035		T4	156
valid_sources[0x57]	396205	1			T2	7		T3	937		T4	138
valid_sources[0x58]	411756	1			T2	4		T3	886		T4	167
valid_sources[0x59]	382054	1			T2	4		T3	904		T4	145
valid_sources[0x5a]	396585	1			T2	1		T3	958		T4	141
valid_sources[0x5b]	403072	1			T2	9		T3	921		T4	142
valid_sources[0x5c]	376705	1			T2	4		T3	926		T4	108
valid_sources[0x5d]	372640	1			T2	2		T3	952		T4	146
valid_sources[0x5e]	393341	1			T2	3		T3	956		T4	112
valid_sources[0x5f]	381225	1			T2	3		T3	918		T4	159
valid_sources[0x60]	393208	1			T2	4		T3	908		T4	158
valid_sources[0x61]	381387	1			T2	2		T3	926		T4	183
valid_sources[0x62]	393975	1			T3	952		T4	157		T5	2
valid_sources[0x63]	411067	1			T2	10		T3	893		T4	99
valid_sources[0x64]	394214	1			T2	1		T3	933		T4	143
valid_sources[0x65]	387254	1			T2	7		T3	908		T4	124
valid_sources[0x66]	411469	1			T2	2		T3	929		T4	145
valid_sources[0x67]	411342	1			T2	11		T3	905		T4	138
valid_sources[0x68]	379367	1			T2	8		T3	957		T4	134
valid_sources[0x69]	391767	1			T2	6		T3	979		T4	158
valid_sources[0x6a]	393416	1			T2	3		T3	939		T4	134
valid_sources[0x6b]	419357	1			T2	5		T3	969		T4	160
valid_sources[0x6c]	527974	1			T2	3		T3	933		T4	119
valid_sources[0x6d]	432100	1			T2	3		T3	1001		T4	137
valid_sources[0x6e]	384993	1			T2	3		T3	1048		T4	150
valid_sources[0x6f]	386869	1			T2	4		T3	956		T4	113
valid_sources[0x70]	414630	1			T2	4		T3	974		T4	162
valid_sources[0x71]	390957	1			T2	6		T3	953		T4	154
valid_sources[0x72]	441076	1			T2	2		T3	993		T4	116
valid_sources[0x73]	425075	1			T2	7		T3	898		T4	143
valid_sources[0x74]	455060	1			T1	9		T2	7		T3	841
valid_sources[0x75]	464068	1			T2	11		T3	980		T4	89
valid_sources[0x76]	375473	1			T2	3		T3	975		T4	119
valid_sources[0x77]	379808	1			T2	9		T3	947		T4	208
valid_sources[0x78]	391850	1			T2	4		T3	976		T4	148
valid_sources[0x79]	385000	1			T2	2		T3	903		T4	179
valid_sources[0x7a]	421408	1			T2	5		T3	933		T4	149
valid_sources[0x7b]	392695	1			T2	3		T3	923		T4	182
valid_sources[0x7c]	399604	1			T2	5		T3	913		T4	107
valid_sources[0x7d]	391975	1			T2	4		T3	902		T4	141
valid_sources[0x7e]	382358	1			T2	6		T3	930		T4	153
valid_sources[0x7f]	394028	1			T2	10		T3	971		T4	179
valid_sources[0x80]	393637	1			T2	9		T3	1038		T4	107

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20923245

1

T1

40

T2

78

T3

42333

values[0x0]

all_enables

biggest_size

4667111

1

T1

46

T2

40

T3

667

values[0x1]

all_enables

biggest_size

4608240

1

T1

37

T2

30

T3

330