Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15459517	0	0
ctrl_rd_A	2147483647	195231	0	0
intr_enable_rd_A	2147483647	172934	0	0
ovrd_rd_A	2147483647	193515	0	0
timeout_ctrl_rd_A	2147483647	196281	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15459517	0	0
T9	357460	114395	0	0
T10	328178	0	0	0
T11	268070	0	0	0
T12	578221	167896	0	0
T20	299666	0	0	0
T21	0	149091	0	0
T28	0	121436	0	0
T29	0	279796	0	0
T30	0	48891	0	0
T31	0	131388	0	0
T32	0	205487	0	0
T33	0	41995	0	0
T34	0	59689	0	0
T35	242701	0	0	0
T36	209148	0	0	0
T37	126513	0	0	0
T38	688370	0	0	0
T39	382998	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	195231	0	0
T12	578221	8550	0	0
T16	459797	0	0	0
T21	0	15919	0	0
T37	126513	0	0	0
T38	688370	0	0	0
T39	382998	0	0	0
T40	359151	0	0	0
T110	0	9785	0	0
T111	0	1928	0	0
T112	0	7641	0	0
T113	0	3202	0	0
T114	0	5272	0	0
T115	0	9603	0	0
T116	0	5902	0	0
T117	0	6912	0	0
T118	248125	0	0	0
T119	284147	0	0	0
T120	6673	0	0	0
T121	422749	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	172934	0	0
T3	717510	39	0	0
T4	306962	0	0	0
T5	22767	0	0	0
T6	894778	0	0	0
T7	367348	0	0	0
T8	757772	0	0	0
T9	357460	0	0	0
T10	328178	0	0	0
T11	268070	0	0	0
T12	0	7250	0	0
T21	0	14312	0	0
T35	242701	0	0	0
T63	0	34	0	0
T110	0	8683	0	0
T111	0	1743	0	0
T112	0	6791	0	0
T113	0	2758	0	0
T122	0	15	0	0
T123	0	37	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	193515	0	0
T12	578221	8242	0	0
T16	459797	0	0	0
T21	0	16362	0	0
T37	126513	0	0	0
T38	688370	0	0	0
T39	382998	0	0	0
T40	359151	0	0	0
T110	0	9851	0	0
T111	0	1987	0	0
T112	0	7281	0	0
T113	0	3083	0	0
T114	0	5246	0	0
T115	0	9316	0	0
T116	0	5929	0	0
T117	0	6853	0	0
T118	248125	0	0	0
T119	284147	0	0	0
T120	6673	0	0	0
T121	422749	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196281	0	0
T12	578221	8267	0	0
T16	459797	0	0	0
T21	0	16847	0	0
T37	126513	0	0	0
T38	688370	0	0	0
T39	382998	0	0	0
T40	359151	0	0	0
T110	0	9632	0	0
T111	0	1965	0	0
T112	0	7971	0	0
T113	0	3210	0	0
T114	0	5255	0	0
T115	0	9239	0	0
T116	0	5626	0	0
T117	0	6712	0	0
T118	248125	0	0	0
T119	284147	0	0	0
T120	6673	0	0	0
T121	422749	0	0	0