Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71762887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28660637

1

T1

253

T2

169201

T3

177

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90248536	1			T1	17299		T2	192735		T3	3135
values[0x0]	4808802	1			T1	135		T2	61293		T3	161
values[0x1]	5366186	1			T1	118		T2	68958		T3	137

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49772627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50650897

1

T1

5926

T2

221170

T3

1212

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	360479	1			T1	57		T2	1293		T3	17
valid_sources[0x01]	411428	1			T1	75		T2	1303		T3	9
valid_sources[0x02]	428266	1			T1	49		T2	1194		T3	14
valid_sources[0x03]	365399	1			T1	71		T2	1252		T3	11
valid_sources[0x04]	390322	1			T1	65		T2	1273		T3	10
valid_sources[0x05]	384969	1			T1	51		T2	1330		T3	18
valid_sources[0x06]	365063	1			T1	64		T2	1230		T3	17
valid_sources[0x07]	395618	1			T1	76		T2	1245		T3	9
valid_sources[0x08]	412333	1			T1	63		T2	1330		T3	16
valid_sources[0x09]	374648	1			T1	79		T2	1249		T3	15
valid_sources[0x0a]	377749	1			T1	76		T2	1212		T3	11
valid_sources[0x0b]	371592	1			T1	72		T2	1237		T3	7
valid_sources[0x0c]	382636	1			T1	66		T2	1232		T3	30
valid_sources[0x0d]	386739	1			T1	69		T2	1312		T3	8
valid_sources[0x0e]	345975	1			T1	77		T2	1355		T3	16
valid_sources[0x0f]	332772	1			T1	76		T2	1227		T3	12
valid_sources[0x10]	366318	1			T1	77		T2	1274		T3	14
valid_sources[0x11]	394501	1			T1	63		T2	1259		T3	15
valid_sources[0x12]	382085	1			T1	64		T2	1252		T3	21
valid_sources[0x13]	359133	1			T1	66		T2	1274		T3	17
valid_sources[0x14]	373490	1			T1	81		T2	1280		T3	9
valid_sources[0x15]	388989	1			T1	74		T2	1223		T3	13
valid_sources[0x16]	381507	1			T1	78		T2	1264		T3	17
valid_sources[0x17]	386948	1			T1	50		T2	1268		T3	8
valid_sources[0x18]	373958	1			T1	74		T2	1290		T3	11
valid_sources[0x19]	388134	1			T1	68		T2	1317		T3	19
valid_sources[0x1a]	372278	1			T1	51		T2	1264		T3	13
valid_sources[0x1b]	408853	1			T1	88		T2	1286		T3	14
valid_sources[0x1c]	441765	1			T1	78		T2	1319		T3	11
valid_sources[0x1d]	375388	1			T1	61		T2	1306		T3	15
valid_sources[0x1e]	375606	1			T1	78		T2	1295		T3	11
valid_sources[0x1f]	365785	1			T1	69		T2	1245		T3	9
valid_sources[0x20]	379110	1			T1	66		T2	1295		T3	10
valid_sources[0x21]	440924	1			T1	54		T2	1254		T3	9
valid_sources[0x22]	366155	1			T1	80		T2	1266		T3	14
valid_sources[0x23]	370675	1			T1	69		T2	1250		T3	15
valid_sources[0x24]	359173	1			T1	71		T2	1232		T3	28
valid_sources[0x25]	369422	1			T1	57		T2	1252		T3	19
valid_sources[0x26]	365187	1			T1	56		T2	1219		T3	12
valid_sources[0x27]	395107	1			T1	64		T2	1213		T3	14
valid_sources[0x28]	427347	1			T1	63		T2	1257		T3	17
valid_sources[0x29]	381462	1			T1	71		T2	1301		T3	7
valid_sources[0x2a]	432842	1			T1	58		T2	1245		T3	17
valid_sources[0x2b]	434565	1			T1	79		T2	1229		T3	16
valid_sources[0x2c]	359366	1			T1	63		T2	1303		T3	14
valid_sources[0x2d]	384073	1			T1	84		T2	1186		T3	18
valid_sources[0x2e]	405142	1			T1	76		T2	1286		T3	17
valid_sources[0x2f]	399689	1			T1	64		T2	1280		T3	14
valid_sources[0x30]	393941	1			T1	54		T2	1262		T3	14
valid_sources[0x31]	401459	1			T1	92		T2	1245		T3	10
valid_sources[0x32]	344789	1			T1	78		T2	1284		T3	18
valid_sources[0x33]	358944	1			T1	70		T2	1244		T3	15
valid_sources[0x34]	387783	1			T1	68		T2	1370		T3	14
valid_sources[0x35]	367216	1			T1	62		T2	1248		T3	8
valid_sources[0x36]	452760	1			T1	61		T2	1278		T3	14
valid_sources[0x37]	414531	1			T1	59		T2	1293		T3	14
valid_sources[0x38]	375357	1			T1	71		T2	1284		T3	13
valid_sources[0x39]	371444	1			T1	69		T2	1280		T3	8
valid_sources[0x3a]	366594	1			T1	77		T2	1302		T3	13
valid_sources[0x3b]	389373	1			T1	70		T2	1255		T3	15
valid_sources[0x3c]	416687	1			T1	74		T2	1198		T3	15
valid_sources[0x3d]	452691	1			T1	85		T2	1250		T3	14
valid_sources[0x3e]	477776	1			T1	63		T2	1275		T3	14
valid_sources[0x3f]	391699	1			T1	77		T2	1224		T3	12
valid_sources[0x40]	374830	1			T1	78		T2	1312		T3	11
valid_sources[0x41]	386154	1			T1	63		T2	1263		T3	17
valid_sources[0x42]	382011	1			T1	84		T2	1249		T3	9
valid_sources[0x43]	412642	1			T1	70		T2	1237		T3	12
valid_sources[0x44]	359528	1			T1	73		T2	1261		T3	11
valid_sources[0x45]	378735	1			T1	67		T2	1266		T3	17
valid_sources[0x46]	360196	1			T1	77		T2	1275		T3	12
valid_sources[0x47]	359384	1			T1	66		T2	1255		T3	11
valid_sources[0x48]	364530	1			T1	67		T2	1228		T3	14
valid_sources[0x49]	370348	1			T1	63		T2	1333		T3	19
valid_sources[0x4a]	367292	1			T1	66		T2	1211		T3	10
valid_sources[0x4b]	399880	1			T1	67		T2	1218		T3	19
valid_sources[0x4c]	407387	1			T1	68		T2	1237		T3	13
valid_sources[0x4d]	395581	1			T1	60		T2	1239		T3	8
valid_sources[0x4e]	400362	1			T1	66		T2	1222		T3	12
valid_sources[0x4f]	394009	1			T1	70		T2	1272		T3	10
valid_sources[0x50]	405716	1			T1	75		T2	1221		T3	13
valid_sources[0x51]	380012	1			T1	49		T2	1250		T3	20
valid_sources[0x52]	377424	1			T1	68		T2	1241		T3	17
valid_sources[0x53]	379543	1			T1	73		T2	1193		T3	12
valid_sources[0x54]	372327	1			T1	73		T2	1283		T3	12
valid_sources[0x55]	486647	1			T1	64		T2	1257		T3	14
valid_sources[0x56]	368668	1			T1	83		T2	1252		T3	9
valid_sources[0x57]	368163	1			T1	83		T2	1259		T3	13
valid_sources[0x58]	370455	1			T1	73		T2	1151		T3	15
valid_sources[0x59]	362400	1			T1	70		T2	1242		T3	24
valid_sources[0x5a]	433525	1			T1	51		T2	1264		T3	8
valid_sources[0x5b]	458285	1			T1	48		T2	1233		T3	15
valid_sources[0x5c]	375978	1			T1	63		T2	1226		T3	10
valid_sources[0x5d]	403619	1			T1	76		T2	1274		T3	16
valid_sources[0x5e]	408190	1			T1	65		T2	1163		T3	17
valid_sources[0x5f]	377920	1			T1	63		T2	1240		T3	10
valid_sources[0x60]	409054	1			T1	59		T2	1269		T3	11
valid_sources[0x61]	375455	1			T1	58		T2	1246		T3	13
valid_sources[0x62]	534280	1			T1	66		T2	1229		T3	21
valid_sources[0x63]	376272	1			T1	73		T2	1240		T3	9
valid_sources[0x64]	407118	1			T1	58		T2	1211		T3	10
valid_sources[0x65]	404019	1			T1	67		T2	1305		T3	10
valid_sources[0x66]	363630	1			T1	65		T2	1197		T3	11
valid_sources[0x67]	375055	1			T1	91		T2	1260		T3	10
valid_sources[0x68]	375701	1			T1	70		T2	1261		T3	13
valid_sources[0x69]	400441	1			T1	56		T2	1222		T3	17
valid_sources[0x6a]	380546	1			T1	77		T2	1393		T3	8
valid_sources[0x6b]	384563	1			T1	58		T2	1244		T3	14
valid_sources[0x6c]	373580	1			T1	53		T2	1253		T3	15
valid_sources[0x6d]	367271	1			T1	70		T2	1315		T3	13
valid_sources[0x6e]	430690	1			T1	75		T2	1263		T3	11
valid_sources[0x6f]	384413	1			T1	67		T2	1317		T3	8
valid_sources[0x70]	395209	1			T1	70		T2	1250		T3	14
valid_sources[0x71]	362248	1			T1	69		T2	1262		T3	12
valid_sources[0x72]	468629	1			T1	72		T2	1319		T3	15
valid_sources[0x73]	349482	1			T1	76		T2	1266		T3	10
valid_sources[0x74]	381339	1			T1	81		T2	1268		T3	15
valid_sources[0x75]	404762	1			T1	75		T2	1271		T3	7
valid_sources[0x76]	416343	1			T1	67		T2	1242		T3	13
valid_sources[0x77]	390727	1			T1	61		T2	1278		T3	9
valid_sources[0x78]	377982	1			T1	82		T2	1294		T3	10
valid_sources[0x79]	370866	1			T1	84		T2	1184		T3	20
valid_sources[0x7a]	379202	1			T1	57		T2	1265		T3	15
valid_sources[0x7b]	364554	1			T1	59		T2	1303		T3	17
valid_sources[0x7c]	391704	1			T1	62		T2	1259		T3	14
valid_sources[0x7d]	415866	1			T1	81		T2	1234		T3	11
valid_sources[0x7e]	374834	1			T1	56		T2	1251		T3	16
valid_sources[0x7f]	394002	1			T1	75		T2	1228		T3	15
valid_sources[0x80]	407057	1			T1	42		T2	1275		T3	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19642489

1

T1

184

T2

50101

T3

86

values[0x0]

all_enables

biggest_size

4537802

1

T1

47

T2

59690

T3

63

values[0x1]

all_enables

biggest_size

4480346

1

T1

22

T2

59410

T3

28