Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14941229	0	0
ctrl_rd_A	2147483647	259245	0	0
intr_enable_rd_A	2147483647	228129	0	0
ovrd_rd_A	2147483647	256850	0	0
timeout_ctrl_rd_A	2147483647	255230	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14941229	0	0
T2	490486	203047	0	0
T3	262059	0	0	0
T4	113739	0	0	0
T5	109386	0	0	0
T6	22124	0	0	0
T7	51248	0	0	0
T8	868941	0	0	0
T9	100715	0	0	0
T10	338326	0	0	0
T11	297696	0	0	0
T12	0	113224	0	0
T14	0	108459	0	0
T20	0	140215	0	0
T29	0	301916	0	0
T30	0	222529	0	0
T31	0	141160	0	0
T32	0	296215	0	0
T33	0	183592	0	0
T34	0	120608	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259245	0	0
T34	388379	5394	0	0
T43	0	1254	0	0
T57	0	5691	0	0
T107	0	10314	0	0
T108	0	17851	0	0
T109	0	12243	0	0
T110	0	20810	0	0
T111	0	15424	0	0
T112	0	7515	0	0
T113	0	22315	0	0
T114	122470	0	0	0
T115	227423	0	0	0
T116	298105	0	0	0
T117	976146	0	0	0
T118	451064	0	0	0
T119	251778	0	0	0
T120	778784	0	0	0
T121	236589	0	0	0
T122	222808	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	228129	0	0
T34	388379	4539	0	0
T43	0	1235	0	0
T57	0	4750	0	0
T107	0	9306	0	0
T108	0	15694	0	0
T109	0	10822	0	0
T110	0	18459	0	0
T111	0	14047	0	0
T112	0	6813	0	0
T114	122470	0	0	0
T115	227423	0	0	0
T116	298105	0	0	0
T117	976146	0	0	0
T118	451064	0	0	0
T119	251778	0	0	0
T120	778784	0	0	0
T121	236589	0	0	0
T122	222808	0	0	0
T123	0	8	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	256850	0	0
T34	388379	5322	0	0
T43	0	1222	0	0
T57	0	5603	0	0
T107	0	9930	0	0
T108	0	17339	0	0
T109	0	12040	0	0
T110	0	20674	0	0
T111	0	15489	0	0
T112	0	7849	0	0
T113	0	22505	0	0
T114	122470	0	0	0
T115	227423	0	0	0
T116	298105	0	0	0
T117	976146	0	0	0
T118	451064	0	0	0
T119	251778	0	0	0
T120	778784	0	0	0
T121	236589	0	0	0
T122	222808	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	255230	0	0
T34	388379	5481	0	0
T43	0	1493	0	0
T57	0	5647	0	0
T107	0	9830	0	0
T108	0	18219	0	0
T109	0	12113	0	0
T110	0	21011	0	0
T111	0	15005	0	0
T112	0	7733	0	0
T113	0	22148	0	0
T114	122470	0	0	0
T115	227423	0	0	0
T116	298105	0	0	0
T117	976146	0	0	0
T118	451064	0	0	0
T119	251778	0	0	0
T120	778784	0	0	0
T121	236589	0	0	0
T122	222808	0	0	0