Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14013840	0	0
ctrl_rd_A	2147483647	213563	0	0
intr_enable_rd_A	2147483647	190913	0	0
ovrd_rd_A	2147483647	213017	0	0
timeout_ctrl_rd_A	2147483647	213943	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14013840	0	0
T6	324427	130436	0	0
T7	271152	0	0	0
T8	137008	0	0	0
T9	464532	195876	0	0
T10	347099	0	0	0
T13	445301	0	0	0
T14	154540	0	0	0
T17	0	157671	0	0
T24	0	85066	0	0
T25	0	86362	0	0
T26	0	43393	0	0
T27	0	221788	0	0
T28	0	176066	0	0
T29	0	122499	0	0
T30	0	92857	0	0
T31	128223	0	0	0
T32	899970	0	0	0
T33	262892	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	213563	0	0
T16	49972	0	0	0
T24	698253	9761	0	0
T25	218242	0	0	0
T29	0	13389	0	0
T40	461038	0	0	0
T41	288918	0	0	0
T42	742714	0	0	0
T43	243304	0	0	0
T44	841627	0	0	0
T45	223571	0	0	0
T46	888469	0	0	0
T50	0	11571	0	0
T93	0	12759	0	0
T94	0	8208	0	0
T95	0	8236	0	0
T96	0	14304	0	0
T97	0	7796	0	0
T98	0	4896	0	0
T99	0	5029	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	190913	0	0
T16	49972	0	0	0
T24	698253	8784	0	0
T25	218242	0	0	0
T29	0	12444	0	0
T40	461038	0	0	0
T41	288918	0	0	0
T42	742714	0	0	0
T43	243304	0	0	0
T44	841627	0	0	0
T45	223571	0	0	0
T46	888469	0	0	0
T50	0	10425	0	0
T93	0	11119	0	0
T94	0	7632	0	0
T95	0	6969	0	0
T96	0	12629	0	0
T97	0	7011	0	0
T100	0	4	0	0
T101	0	41	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	213017	0	0
T16	49972	0	0	0
T24	698253	10060	0	0
T25	218242	0	0	0
T29	0	14030	0	0
T40	461038	0	0	0
T41	288918	0	0	0
T42	742714	0	0	0
T43	243304	0	0	0
T44	841627	0	0	0
T45	223571	0	0	0
T46	888469	0	0	0
T50	0	11534	0	0
T93	0	12043	0	0
T94	0	8822	0	0
T95	0	7966	0	0
T96	0	13831	0	0
T97	0	7700	0	0
T98	0	4868	0	0
T99	0	5023	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	213943	0	0
T16	49972	0	0	0
T24	698253	9657	0	0
T25	218242	0	0	0
T29	0	13430	0	0
T40	461038	0	0	0
T41	288918	0	0	0
T42	742714	0	0	0
T43	243304	0	0	0
T44	841627	0	0	0
T45	223571	0	0	0
T46	888469	0	0	0
T50	0	11948	0	0
T93	0	12410	0	0
T94	0	8568	0	0
T95	0	8249	0	0
T96	0	14003	0	0
T97	0	7768	0	0
T98	0	4862	0	0
T99	0	4918	0	0